[Intel-gfx] ✗ Ro.CI.BAT: warning for mutex: Do not spin/queue before performing ww_mutex deadlock avoidance (rev2)

== Series Details == Series: mutex: Do not spin/queue before performing ww_mutex deadlock avoidance (rev2) URL : https://patchwork.freedesktop.org/series/7788/ State : warning == Summary == Series 7788v2 mutex: Do not spin/queue before performing ww_mutex deadlock avoidance

[Intel-gfx] [PATCH i-g-t] igt_core: Search "." as final fallback for igt_fopen_data()

Some validation teams seem to run tests out of source directories that have been nfs mounted or rsync'd to different locations on the target machine. This causes the igt_srcdir that the tests were built with to be invalid on the machine the tests get run on. Add the current directory as a final

[Intel-gfx] [PATCH 2/4] drm/i915/skl+: calculate ddb minimum allocation (v5)

From: "Kumar, Mahesh" don't always use 8 ddb as minimum, instead calculate using proper algorithm. v2: optimizations as per Matt's comments. v3 (by Matt): - Fix boolean logic for !fb test in skl_ddb_min_alloc() - Adjust negative tiling format comparisons in

[Intel-gfx] Regression in i915 in kernel 4.6.0-git - bisected to f21a21983ef13a031

The latest mainline kernel (commit 3f59de0) shows a regression. The symptom is that as soon as the kernel is started, the display is blanked, and it is never turned on again. This problem was bisected to commit f21a21983ef13a031250c4c3f6018e29a549d0f1 ("drm/i915: Splitting intel_dp_detect").

[Intel-gfx] [PATCH] mutex: Report recursive ww_mutex locking early

Recursive locking for ww_mutexes was originally conceived as an exception. However, it is heavily used by the DRM atomic modesetting code. Currently, the recursive deadlock is checked after we have queued up for a busy-spin and as we never release the lock, we spin until kicked, whereupon the

[Intel-gfx] ✗ Ro.CI.BAT: warning for kbl and gen9 workarounds (rev5)

== Series Details == Series: kbl and gen9 workarounds (rev5) URL : https://patchwork.freedesktop.org/series/7824/ State : warning == Summary == Series 7824v5 kbl and gen9 workarounds http://patchwork.freedesktop.org/api/1.0/series/7824/revisions/5/mbox Test gem_exec_basic: Subgroup

[Intel-gfx] [PATCH 23/23] drm/i195/fbc: Add WaFbcNukeOnHostModify

Bspec states that we need to set nuke on modify all to prevent screen corruption with fbc on skl and kbl. v2: proper workaround name References: HSD#2227109, HSDES#1404569388 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_reg.h | 1 +

[Intel-gfx] [PATCH 22/23] drm/i915/gen9: Add WaFbcWakeMemOn

Set bit 8 in 0x43224 to prevent screen corruption and system hangs on high memory bandwidth conditions. The same wa also suggest setting bit 31 on ARB_CTL. According to another workaround we gain better idle power savings when FBC is enabled. v2: use correct workaround name References:

[Intel-gfx] [PATCH 21/23] drm/i915/gen9: Add WaFbcTurnOffFbcWatermark

According to bspec this prevents screen corruption when fbc is used. v2: This workaround has a name, use it (Ville) References: HSD#213, HSD#2137270, BSID#562 Cc: Paulo Zanoni Signed-off-by: Mika Kuoppala ---

[Intel-gfx] [PATCH 20/23] drm/i915/gen9: Add WaEnableChickenDCPR

Workaround for display underrun issues with Y & Yf Tiling. Set this on all gen9 as stated by bspec. v2: proper workaround name References: HSD#2136383, BSID#857 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 4

[Intel-gfx] ✗ Ro.CI.BAT: warning for kbl and gen9 workarounds

== Series Details == Series: kbl and gen9 workarounds URL : https://patchwork.freedesktop.org/series/7824/ State : warning == Summary == Series 7824v1 kbl and gen9 workarounds http://patchwork.freedesktop.org/api/1.0/series/7824/revisions/1/mbox Test drv_module_reload_basic:

[Intel-gfx] [PATCH igt v3] lib: Add simple sysfs accessors

igt_sysfs_set() for setting an attribute via sysfs, igt_sysfs_get() for reading. v2: Lots of little bugs in igt_sysfs_get() v3: Pass device to open, stop assuming Intel rules. v4: Test opening and reading! Signed-off-by: Chris Wilson --- lib/Makefile.sources | 2 +

Re: [Intel-gfx] [PATCH 21/23] drm/i915/gen9: Set fbc watermarks disabled

On Thu, May 26, 2016 at 06:53:18PM +0300, Ville Syrjälä wrote: > On Thu, May 26, 2016 at 06:29:44PM +0300, Mika Kuoppala wrote: > > According to bspec this prevents screen corruption when fbc is > > used. > > > > References: HSD#213, HSD#2137270 > > Cc: Paulo Zanoni

Re: [Intel-gfx] [PATCH 21/23] drm/i915/gen9: Set fbc watermarks disabled

On Thu, May 26, 2016 at 06:29:44PM +0300, Mika Kuoppala wrote: > According to bspec this prevents screen corruption when fbc is > used. > > References: HSD#213, HSD#2137270 > Cc: Paulo Zanoni > Signed-off-by: Mika Kuoppala > --- >

[Intel-gfx] [PATCH 17/23] drm/i915/kbl: Add WaForGAMHang

Add this workaround for A0 and B0 revisions References: HSD#2226935 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_lrc.c | 36 ++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git

[Intel-gfx] [PATCH 20/23] drm/i915/gen9: Set wa for display underrun issues with Y & Yf Tiling.

Set this on all gen9 as stated by bspec. References: HSD#2136383 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH 12/23] drm/i915/kbl: Add WaDisableGamClockGating

According to bspec we need to disable gam unit clock gating on on kbl revids A0 and B0. References: HSD#2226858, HSD#1944358 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 5 + 2 files changed, 6

[Intel-gfx] [PATCH 13/23] drm/i915/kbl: Add WaDisableDynamicCreditSharing

Bspec states that we need to turn off dynamic credit sharing on kbl revid a0 and b0. This happens by writing bit 28 on 0x4ab8. References: HSD#2225601, HSD#2226938, HSD#2225763 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_reg.h | 2 ++

[Intel-gfx] [PATCH 18/23] drm/i915: Add WaDisableGafsUnitClkGating for skl and kbl

We need this gafs bit to be enabled for hw fix to take effect. References: HSD#2227156, HSD#2227050 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++ 2 files changed, 7 insertions(+) diff

[Intel-gfx] [PATCH 15/23] drm/i915/gen9: Add WaDisableSkipCaching

Make sure that we never enable skip caching on gen9 by accident. References: HSD#2134698 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_mocs.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_mocs.c

[Intel-gfx] [PATCH 10/23] drm/i915/kbl: Add WaDisableLSQCROPERFforOCL

Extend the scope of this workaround, already used in skl, to also take effect in kbl. References: HSD#2132677 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_drv.h | 3 +++ drivers/gpu/drm/i915/intel_lrc.c| 5 +++--

[Intel-gfx] [PATCH 23/23] drm/i195/fbc: Enable wa to prevent fbc corruption with skl and kbl

Bspec states that we need to set nuke on modify all to prevent screen corruption with fbc on skl and kbl. References: HSDES#1404569388 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 6 ++ 2 files changed, 7

[Intel-gfx] [PATCH 16/23] drm/i915/skl: Add WAC6entrylatency

This workaround is for fbc working with rc6 on skylake. Bspec states that setting this bit needs to be coordinated with uncore but offers no further details. References: HSD#4712857 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_reg.h | 3 +++

[Intel-gfx] [PATCH 08/23] drm/i915/kbl: Add WaDisableSDEUnitClockGating

Add this workaround until upto kbl revid B0. References: HSD#1802092 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_pm.c | 18 -- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c

[Intel-gfx] [PATCH 05/23] drm/i915: Mimic skl with WaForceEnableNonCoherent

Past evidence with system hangs and hsds tie WaForceEnableNonCoherent and WaDisableHDCInvalidation to WaForceContextSaveRestoreNonCoherent. Documentation states that WaForceContextSaveRestoreNonCoherent would not be needed on skl past E0 but evidence proved otherwise. See commit <510650e8b2ab>

[Intel-gfx] [PATCH 09/23] drm/i915/edp: Add WaKVMNotificationOnConfigChange:bdw, skl

According to bspec this workaround helps to reduce lag and improve performance on edp. References: HSD#2134579 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 8 2 files changed, 11 insertions(+) diff

[Intel-gfx] [PATCH 22/23] drm/i915/gen9: Prevent fbc corruption/system hangs with high bw

Set bit 8 in 0x43224 to prevent screen corruption and system hangs on high memory bandwidth conditions. The same wa also suggest setting bit 31 on ARB_CTL. According to another workaround we gain better idle power savings when FBC is enabled. References: HSD#2137218, HSD#2227171, HSD#2136579 Cc:

[Intel-gfx] [PATCH 11/23] drm/i915/gen9: Enable must set chicken bits in config0 reg

The bspec states that these must be set in CONFIG0 for all gen9. References: HSD#2134995 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 22 ++ 2 files changed, 17 insertions(+), 8

[Intel-gfx] [PATCH 21/23] drm/i915/gen9: Set fbc watermarks disabled

According to bspec this prevents screen corruption when fbc is used. References: HSD#213, HSD#2137270 Cc: Paulo Zanoni Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_pm.c | 5 - 1 file changed, 4 insertions(+), 1

[Intel-gfx] [PATCH 06/23] drm/i915/kbl: Add WaEnableGapsTsvCreditFix

We need this crucial workaround from skl also to all kbl revisions. Lack of it was causing system hangs on skl enabling so this is a must have. References: HSD#2126660 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_ringbuffer.c | 13 +++-- 1 file

[Intel-gfx] [PATCH 19/23] drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing

Move this workaround to common gen9 workarounds and enable for all kbl revision. References: HSD#2135593 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_ringbuffer.c | 21 - 1 file changed, 8 insertions(+), 13 deletions(-) diff --git

[Intel-gfx] [PATCH 02/23] drm/i915/kbl: Add REVID macro

Add REVID macro for kbl to limit wa applicability to particular revision range. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_drv.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h

[Intel-gfx] [PATCH 07/23] drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0

Add this workaround for kbl revid A0 only. References: HSD#1911714 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_lrc.c| 16 drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++ 2 files changed, 22 insertions(+) diff --git

[Intel-gfx] [PATCH 03/23] drm/i915/kbl: Add WaSkipStolenMemoryFirstPage for A0

We need this for kbl a0 boards. Note that this should be also for bxt A0 but we omit that on purpose as bxt A0's are out of fashion already. References: HSD#1912158, HSD#4393097 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_stolen.c | 6 -- 1 file

[Intel-gfx] [PATCH 01/23] drm/i915/kbl: Init gen9 workarounds

Kabylake is part of gen9 family so init the generic gen9 workarounds for it. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_ringbuffer.c | 48 ++--- 1 file changed, 32 insertions(+), 16 deletions(-) diff --git

[Intel-gfx] [PATCH 04/23] drm/i915/gen9: Always apply WaForceContextSaveRestoreNonCoherent

The revision id range for this workaround has changed. So apply it to all revids on all gen9. References: HSD#2134449 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_ringbuffer.c | 11 --- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git

[Intel-gfx] [PATCH 00/23] kbl and gen9 workarounds

I noticed that we didn't setup any workarounds for kbl and so here is a series to get necessities covered on kbl. And while on it add few to bxt and skl. In the end there are also few fbc ones I bumped into. Mika Kuoppala (23): drm/i915/kbl: Init gen9 workarounds drm/i915/kbl: Add REVID macro

[Intel-gfx] [PATCH 14/23] drm/i915: Add WaInsertDummyPushConstP for bxt and kbl

Add this workaround for both bxt and kbl up to until rev B0. References: HSD#2136703 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++ 2 files changed, 11 insertions(+) diff --git

Re: [Intel-gfx] [PATCH] drm: Store the plane's index

On Thu, May 26, 2016 at 01:17:18PM +0100, Chris Wilson wrote: > Currently the plane's index is determined by walking the list of all > planes in the mode and finding the position of that plane in the list. A > linear walk, especially a linear walk within a linear walk as frequently > conceived by

[Intel-gfx] [PATCH igt v2 2/2] lib: Override the connector status using the sysfs status attribute

There are two paths to force enable a connector, via debugfs and via sysfs. sysfs has the advantage of being a stable interface and of updating the connector after application (allowing us to not force a reprobe from userspace). v2: Don't assume Intel only Signed-off-by: Chris Wilson

[Intel-gfx] [PATCH igt v2 1/2] lib: Add simple sysfs accessors

igt_sysfs_set() for setting an attribute via sysfs, igt_sysfs_get() for reading. v2: Lots of little bugs in igt_sysfs_get() v3: Pass device to open, stop assuming Intel rules. Signed-off-by: Chris Wilson --- lib/Makefile.sources | 2 + lib/igt_sysfs.c | 198

Re: [Intel-gfx] [PATCH igt 2/2] lib: Override the connector status using the sysfs status attribute

On Thu, May 26, 2016 at 05:39:32PM +0300, Ville Syrjälä wrote: > On Thu, May 26, 2016 at 03:14:30PM +0100, Chris Wilson wrote: > > There are two paths to force enable a connector, via debugfs and via > > sysfs. sysfs has the advantage of being a stable interface and of > > updating the connector

Re: [Intel-gfx] [PATCH igt 1/2] lib: Add simple sysfs accessors

On Thu, May 26, 2016 at 05:36:09PM +0300, Ville Syrjälä wrote: > > + > > + for (int n = 0; n < 16; n++) { > > + int len = sprintf(path, "/sys/class/drm/card%d", n); > > + sprintf(path + len, "/error"); > > That's goint to limit this to i915. I was thinking we could pass >

Re: [Intel-gfx] [PATCH igt 2/2] lib: Override the connector status using the sysfs status attribute

On Thu, May 26, 2016 at 03:14:30PM +0100, Chris Wilson wrote: > There are two paths to force enable a connector, via debugfs and via > sysfs. sysfs has the advantage of being a stable interface and of > updating the connector after application (allowing us to not force a > reprobe from userspace).

Re: [Intel-gfx] [PATCH igt 1/2] lib: Add simple sysfs accessors

On Thu, May 26, 2016 at 03:14:29PM +0100, Chris Wilson wrote: > igt_sysfs_set() for setting an attribute via sysfs, igt_sysfs_get() for > reading. > > Signed-off-by: Chris Wilson > --- > lib/Makefile.sources | 2 + > lib/igt_sysfs.c | 145 >

Re: [Intel-gfx] [PATCH] drm/i915: Register debugfs interface last

On Thu, May 26, 2016 at 02:17:27PM +0100, Chris Wilson wrote: > Currently debugfs files are created before the driver is even loads. > This gives the opportunity for userspace to open that interface and poke > around before the backing data structures are initialised - with the > possibility of

[Intel-gfx] [PATCH igt 1/2] lib: Add simple sysfs accessors

igt_sysfs_set() for setting an attribute via sysfs, igt_sysfs_get() for reading. Signed-off-by: Chris Wilson --- lib/Makefile.sources | 2 + lib/igt_sysfs.c | 145 +++ lib/igt_sysfs.h | 33 3

[Intel-gfx] ✗ Ro.CI.BAT: warning for series starting with [v3,01/10] drm/i915: Skip idling an idle engine (rev3)

== Series Details == Series: series starting with [v3,01/10] drm/i915: Skip idling an idle engine (rev3) URL : https://patchwork.freedesktop.org/series/7792/ State : warning == Summary == Series 7792v3 Series without cover letter

[Intel-gfx] [PATCH] drm/i915: Register debugfs interface last

Currently debugfs files are created before the driver is even loads. This gives the opportunity for userspace to open that interface and poke around before the backing data structures are initialised - with the possibility of oopsing or worse. Move the creation of the debugfs files to our

[Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [v3,01/10] drm/i915: Skip idling an idle engine (rev2)

== Series Details == Series: series starting with [v3,01/10] drm/i915: Skip idling an idle engine (rev2) URL : https://patchwork.freedesktop.org/series/7792/ State : failure == Summary == Series 7792v2 Series without cover letter

Re: [Intel-gfx] [PATCH] drm: Register the debugfs interfaces after loading the driver

On Thu, May 26, 2016 at 01:35:18PM +0100, Chris Wilson wrote: > In order to give the driver the chance to initialise the data structures > that will be exposed through debugfs, perform driver->load() before > registering the debugfs entries. (Otherwise it may be possible for > userspace to cause

Re: [Intel-gfx] [PATCH] drm/i915: Move legacy kernel context pinning to intel_ringbuffer.c

Chris Wilson writes: > [ text/plain ] > This is so that we have symmetry with intel_lrc.c and avoid a source of > if (i915.enable_execlists) layering violation within i915_gem_context.c - > that is we move the specific handling of the dev_priv->kernel_context > for

[Intel-gfx] [PATCH] drm: Register the debugfs interfaces after loading the driver

In order to give the driver the chance to initialise the data structures that will be exposed through debugfs, perform driver->load() before registering the debugfs entries. (Otherwise it may be possible for userspace to cause an oops through the debugfs interfaces.) As the driver load is now

Re: [Intel-gfx] [PATCH v3 03/10] drm/i915: Treat kernel context as initialised

On Thu, May 26, 2016 at 12:51:45PM +0100, Chris Wilson wrote: > On Thu, May 26, 2016 at 09:52:33AM +0100, Chris Wilson wrote: > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c > > b/drivers/gpu/drm/i915/intel_ringbuffer.c > > index 4e0aa7e9d5da..203b7952052a 100644 > > ---

Re: [Intel-gfx] [PATCH v3 02/10] drm/i915: Move legacy kernel context pinning to intel_ringbuffer.c

On Thu, May 26, 2016 at 03:04:11PM +0300, Mika Kuoppala wrote: > > + if (ce->state) { > > + i915_gem_context_reference(kctx); > > + > > + /* We may need to do things with the shrinker which > > +* require us to immediately switch back to the default > > +

Re: [Intel-gfx] ✗ Ro.CI.BAT: failure for drm/i915: Fix NULL pointer deference when out of PLLs in IVB

On Tue, 2016-05-24 at 07:00 +, Patchwork wrote: > == Series Details == > > Series: drm/i915: Fix NULL pointer deference when out of PLLs in IVB > URL   : https://patchwork.freedesktop.org/series/7458/ > State : failure > > == Summary == > > Series 7458v1 drm/i915: Fix NULL pointer deference

[Intel-gfx] [PATCH] drm: Store the plane's index

Currently the plane's index is determined by walking the list of all planes in the mode and finding the position of that plane in the list. A linear walk, especially a linear walk within a linear walk as frequently conceived by i915.ko [O(N^2)] quickly comes to dominate profiles. The plane's

Re: [Intel-gfx] [PATCH v3 05/10] drm/i915: No need to wait for idle on L3 remap

On to, 2016-05-26 at 09:52 +0100, Chris Wilson wrote: > As the L3 remapping is applied before the next execution, there is no > need to wait until all previous uses are idle, the application will not > occur any sooner. > > Signed-off-by: Chris Wilson Reviewed-by:

Re: [Intel-gfx] [PATCH v3 05/10] drm/i915: No need to wait for idle on L3 remap

Chris Wilson writes: > [ text/plain ] > As the L3 remapping is applied before the next execution, there is no > need to wait until all previous uses are idle, the application will not > occur any sooner. > > Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH v3 02/10] drm/i915: Move legacy kernel context pinning to intel_ringbuffer.c

Chris Wilson writes: > [ text/plain ] > This is so that we have symmetry with intel_lrc.c and avoid a source of > if (i915.enable_execlists) layering violation within i915_gem_context.c - > that is we move the specific handling of the dev_priv->kernel_context > for

Re: [Intel-gfx] [PATCH v3 09/10] drm/i915: Remove superfluous powersave work flushing

On Thu, May 26, 2016 at 02:45:09PM +0300, Ville Syrjälä wrote: > On Thu, May 26, 2016 at 09:52:39AM +0100, Chris Wilson wrote: > > Instead of flushing the outstanding enabling, remember the requested > > frequency to apply when the powersave work runs. > > I didn't see a patch to move the

Re: [Intel-gfx] [PATCH 0/9] drm/i915: Reapply page flip atomic preparation patches.

Op 26-05-16 om 13:46 schreef Ville Syrjälä: > On Thu, May 26, 2016 at 01:38:02PM +0200, Maarten Lankhorst wrote: >> Op 26-05-16 om 13:35 schreef Ville Syrjälä: >>> On Thu, May 26, 2016 at 12:37:56PM +0200, Maarten Lankhorst wrote: Add some minor changes to prevent bisect breaking.

Re: [Intel-gfx] [PATCH v3 03/10] drm/i915: Treat kernel context as initialised

On Thu, May 26, 2016 at 09:52:33AM +0100, Chris Wilson wrote: > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c > b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 4e0aa7e9d5da..203b7952052a 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++

Re: [Intel-gfx] [PATCH 0/9] drm/i915: Reapply page flip atomic preparation patches.

On Thu, May 26, 2016 at 01:38:02PM +0200, Maarten Lankhorst wrote: > Op 26-05-16 om 13:35 schreef Ville Syrjälä: > > On Thu, May 26, 2016 at 12:37:56PM +0200, Maarten Lankhorst wrote: > >> Add some minor changes to prevent bisect breaking. > >> > >> Main change is making sure crtc_state is not

Re: [Intel-gfx] [PATCH v3 09/10] drm/i915: Remove superfluous powersave work flushing

On Thu, May 26, 2016 at 09:52:39AM +0100, Chris Wilson wrote: > Instead of flushing the outstanding enabling, remember the requested > frequency to apply when the powersave work runs. I didn't see a patch to move the frequency init to happen before debugfs init. So methinks we still need the

Re: [Intel-gfx] [PATCH v3 06/10] drm/i915: Split idling from forcing context switch

On to, 2016-05-26 at 09:52 +0100, Chris Wilson wrote: > We only need to force a switch to the kernel context placeholder during > eviction. All other uses of i915_gpu_idle() just want to wait until > existing work on the GPU is idle. Rename i915_gpu_idle() to > i915_gem_wait_for_idle() to avoid

Re: [Intel-gfx] [PATCH 0/9] drm/i915: Reapply page flip atomic preparation patches.

Op 26-05-16 om 13:35 schreef Ville Syrjälä: > On Thu, May 26, 2016 at 12:37:56PM +0200, Maarten Lankhorst wrote: >> Add some minor changes to prevent bisect breaking. >> >> Main change is making sure crtc_state is not freed while the mmio update >> still runs. > I didn't see fixes for the other

Re: [Intel-gfx] [PATCH 0/9] drm/i915: Reapply page flip atomic preparation patches.

On Thu, May 26, 2016 at 12:37:56PM +0200, Maarten Lankhorst wrote: > Add some minor changes to prevent bisect breaking. > > Main change is making sure crtc_state is not freed while the mmio update > still runs. I didn't see fixes for the other obvious issues. > > Maarten Lankhorst (9): >

Re: [Intel-gfx] [PATCH v3 07/10] drm/i915: Only switch to default context when evicting from GGTT

On to, 2016-05-26 at 09:52 +0100, Chris Wilson wrote: > The contexts only pin space within the global GTT. Therefore forcing the > switch to the perma-pinned kernel context only has an effect when trying > to evict from and find room within the global GTT. We can then restrict > the switch to only

Re: [Intel-gfx] [PATCHv6 5/5] drm/i915/dp: Enable Upfront link training for typeC DP support on BXT

On Thu, May 26, 2016 at 10:03:22AM +, R, Durgadoss wrote: > > > -Original Message- > > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > > Sent: Wednesday, May 25, 2016 9:05 PM > > To: R, Durgadoss > > Cc: intel-gfx@lists.freedesktop.org; Conselvan

Re: [Intel-gfx] [PATCH] drm/i915: Move legacy kernel context pinning to intel_ringbuffer.c

On to, 2016-05-26 at 12:18 +0100, Chris Wilson wrote: > This is so that we have symmetry with intel_lrc.c and avoid a source of > if (i915.enable_execlists) layering violation within i915_gem_context.c - > that is we move the specific handling of the dev_priv->kernel_context > for legacy

Re: [Intel-gfx] [PATCH] drm: Store the plane's index

On Thu, May 26, 2016 at 10:34:57AM +0100, Chris Wilson wrote: > Currently the plane's index is determined by walking the list of all > planes in the mode and finding the position of that plane in the list. A > linear walk, especially a linear walk within a linear walk as frequently > conceived by

Re: [Intel-gfx] ✗ Ro.CI.BAT: failure for drm/i915: Reapply page flip atomic preparation patches.

Op 26-05-16 om 13:02 schreef Patchwork: > == Series Details == > > Series: drm/i915: Reapply page flip atomic preparation patches. > URL : https://patchwork.freedesktop.org/series/7801/ > State : failure > > == Summary == > > Series 7801v1 drm/i915: Reapply page flip atomic preparation patches.

[Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [1/6] drm/i915: Skip idling an idle engine (rev9)

== Series Details == Series: series starting with [1/6] drm/i915: Skip idling an idle engine (rev9) URL : https://patchwork.freedesktop.org/series/7708/ State : failure == Summary == Applying: drm/i915: Skip idling an idle engine Applying: drm/i915: Move legacy kernel context pinning to

[Intel-gfx] [PATCH] drm/i915: Move legacy kernel context pinning to intel_ringbuffer.c

This is so that we have symmetry with intel_lrc.c and avoid a source of if (i915.enable_execlists) layering violation within i915_gem_context.c - that is we move the specific handling of the dev_priv->kernel_context for legacy submission into the legacy submission code. This depends upon the

Re: [Intel-gfx] [PATCH] mutex: Do not spin/queue before performing ww_mutex deadlock avoidance

Op 26-05-16 om 12:43 schreef Chris Wilson: > On Thu, May 26, 2016 at 12:37:30PM +0200, Maarten Lankhorst wrote: >> The check should also not be for NULL, but for use_ww_ctx. >> This way the if check is optimized out for the ww_ctx path, where >> ww_ctx is always non-null. > The compiler can see

[Intel-gfx] ✗ Ro.CI.BAT: failure for drm/i915: Reapply page flip atomic preparation patches.

== Series Details == Series: drm/i915: Reapply page flip atomic preparation patches. URL : https://patchwork.freedesktop.org/series/7801/ State : failure == Summary == Series 7801v1 drm/i915: Reapply page flip atomic preparation patches.

Re: [Intel-gfx] [PATCH] mutex: Do not spin/queue before performing ww_mutex deadlock avoidance

On Thu, May 26, 2016 at 12:37:30PM +0200, Maarten Lankhorst wrote: > The check should also not be for NULL, but for use_ww_ctx. > This way the if check is optimized out for the ww_ctx path, where > ww_ctx is always non-null. The compiler can see use_ww_ctx == false => ww_ctx == NULL just as well

[Intel-gfx] [PATCH 9/9] drm/i915: Pass atomic states to fbc update functions.

This is required to let fbc updates run async. It has a lot of checks whether certain locks are taken, which can be removed when the relevant states are passed in as pointers. Signed-off-by: Maarten Lankhorst Reviewed-by: Patrik Jakobsson

[Intel-gfx] [PATCH 5/9] drm/i915: Remove cs based page flip support, v2.

With mmio flips now available on all platforms it's time to remove support for cs flips. Changes since v1: - Rebase for legacy cursor updates. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/i915_debugfs.c | 19 +- drivers/gpu/drm/i915/i915_irq.c

[Intel-gfx] [PATCH 7/9] drm/i915: Remove queue_flip pointer.

With the removal of cs support this is no longer reachable. Can be revived if needed. Signed-off-by: Maarten Lankhorst Reviewed-by: Patrik Jakobsson --- drivers/gpu/drm/i915/i915_drv.h | 5 -

[Intel-gfx] [PATCH 6/9] drm/i915: Remove use_mmio_flip kernel parameter.

With the removal of cs flips this is always force enabled. Signed-off-by: Maarten Lankhorst Reviewed-by: Patrik Jakobsson --- drivers/gpu/drm/i915/i915_params.c | 5 - drivers/gpu/drm/i915/i915_params.h | 1 -

[Intel-gfx] [PATCH 3/9] drm/i915: Add the exclusive fence to plane_state.

Set plane_state->base.fence to the dma_buf exclusive fence, and add a wait to the mmio function. This will make it easier to unify plane updates later on. Signed-off-by: Maarten Lankhorst Reviewed-by: Patrik Jakobsson ---

[Intel-gfx] [PATCH 4/9] drm/i915: Rework intel_crtc_page_flip to be almost atomic, v4.

Create a work structure that will be used for all changes. This will be used later on in the atomic commit function. Changes since v1: - Free old_crtc_state from unpin_work_fn properly. Changes since v2: - Add hunk for calling hw state verifier. - Add missing support for color spaces. Changes

[Intel-gfx] [PATCH 8/9] drm/i915: Remove reset_counter from intel_crtc.

With the removal of cs-based flips all mmio waits will finish without requiring the reset counter, because the waits will complete during gpu reset. Signed-off-by: Maarten Lankhorst Reviewed-by: Patrik Jakobsson ---

[Intel-gfx] [PATCH 0/9] drm/i915: Reapply page flip atomic preparation patches.

Add some minor changes to prevent bisect breaking. Main change is making sure crtc_state is not freed while the mmio update still runs. Maarten Lankhorst (9): drm/i915: Allow mmio updates on all platforms, v3. drm/i915: Convert flip_work to a list, v2. drm/i915: Add the exclusive fence to

[Intel-gfx] [PATCH 1/9] drm/i915: Allow mmio updates on all platforms, v3.

With intel_pipe_update begin/end we ensure that the mmio updates don't run during vblank interrupt, using the hw counter we can be sure that when current vblank count != vblank count at the time of pipe_update_end the mmio update is complete. This allows us to use mmio updates on all platforms,

[Intel-gfx] [PATCH 2/9] drm/i915: Convert flip_work to a list, v2.

This will be required to allow more than 1 outstanding update in the future. For now it's unclear how this will will be handled, but with a list it's definitely possible. Changes since v1: - Changed to prevent breaking with the legacy cursor update changes. Signed-off-by: Maarten Lankhorst

Re: [Intel-gfx] [PATCH] mutex: Do not spin/queue before performing ww_mutex deadlock avoidance

Op 26-05-16 om 10:31 schreef Chris Wilson: > The ww_mutex has the property of allowing the lock to detect and report > when it may be used in deadlocking scenarios (to allow the caller to > unwind its locks and avoid the deadlock). This detection needs to be > performed before we queue up for the

Re: [Intel-gfx] [PATCH v2 2/6] drm/i915: Move legacy kernel context pinning to intel_ringbuffer.c

On Thu, May 26, 2016 at 01:22:04PM +0300, Joonas Lahtinen wrote: > > @@ -2327,6 +2350,14 @@ void intel_cleanup_engine(struct intel_engine_cs > > *engine) > >   > >   i915_cmd_parser_fini_ring(engine); > >   i915_gem_batch_pool_fini(>batch_pool); > > + > > + kctx = dev_priv->kernel_context;

Re: [Intel-gfx] [PATCH v2 2/6] drm/i915: Move legacy kernel context pinning to intel_ringbuffer.c

On ke, 2016-05-25 at 15:04 +0100, Chris Wilson wrote: > This is so that we have symmetry with intel_lrc.c and avoid a source of > if (i915.enable_execlists) layering violation within i915_gem_context.c - > that is we move the specific handling of the dev_priv->kernel_context > for legacy

Re: [Intel-gfx] [PATCHv6 5/5] drm/i915/dp: Enable Upfront link training for typeC DP support on BXT

> -Original Message- > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > Sent: Wednesday, May 25, 2016 9:05 PM > To: R, Durgadoss > Cc: intel-gfx@lists.freedesktop.org; Conselvan De Oliveira, Ander > > Subject: Re:

[Intel-gfx] ✗ Ro.CI.BAT: failure for drm: Store the plane's index

== Series Details == Series: drm: Store the plane's index URL : https://patchwork.freedesktop.org/series/7796/ State : failure == Summary == Series 7796v1 drm: Store the plane's index http://patchwork.freedesktop.org/api/1.0/series/7796/revisions/1/mbox Test drv_hangman: Subgroup

[Intel-gfx] [PATCH] drm: Store the plane's index

Currently the plane's index is determined by walking the list of all planes in the mode and finding the position of that plane in the list. A linear walk, especially a linear walk within a linear walk as frequently conceived by i915.ko [O(N^2)] quickly comes to dominate profiles. The plane's

[Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [v3,01/10] drm/i915: Skip idling an idle engine

== Series Details == Series: series starting with [v3,01/10] drm/i915: Skip idling an idle engine URL : https://patchwork.freedesktop.org/series/7792/ State : failure == Summary == Series 7792v1 Series without cover letter http://patchwork.freedesktop.org/api/1.0/series/7792/revisions/1/mbox

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Implement intel_dp_autotest_video_pattern function for DP Video pattern compliance tests

On Wed, 2016-05-25 at 15:46 -0700, Manasi Navare wrote: > On Mon, May 23, 2016 at 03:00:20PM +0300, Ander Conselvan De Oliveira wrote: > > > > On Fri, 2016-04-29 at 18:28 -0700, Manasi Navare wrote: > > > > > > This video pattern test function gets invoked through the > > > compliance test

[Intel-gfx] ✗ Ro.CI.BAT: warning for mutex: Do not spin/queue before performing ww_mutex deadlock avoidance

== Series Details == Series: mutex: Do not spin/queue before performing ww_mutex deadlock avoidance URL : https://patchwork.freedesktop.org/series/7788/ State : warning == Summary == Series 7788v1 mutex: Do not spin/queue before performing ww_mutex deadlock avoidance

Re: [Intel-gfx] [PATCH 4/5] Add support for forcing 6 bpc on DP pipes.

On Wed, 2016-05-25 at 17:42 -0700, Manasi Navare wrote: > On Tue, May 24, 2016 at 08:45:45AM +0300, Ander Conselvan De Oliveira wrote: > > > > On Mon, 2016-05-23 at 10:42 -0700, Jim Bride wrote: > > > > > > On Mon, May 23, 2016 at 11:22:17AM +0300, Ander Conselvan De Oliveira > > > wrote: > > >

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Fixes to support the DP Compliance EDID tests.

On Wed, 2016-05-25 at 17:22 -0700, Manasi Navare wrote: > On Mon, May 23, 2016 at 11:18:20AM +0300, Ander Conselvan De Oliveira wrote: > > > > On Fri, 2016-04-29 at 18:28 -0700, Manasi Navare wrote: > > > > > > This patch addresses a few issues from the original patch for > > > DP Compliance

[Intel-gfx] [PATCH v3 08/10] drm/i915: Preserve current RPS frequency

Select idle frequency during initialisation, then reset the last known frequency when re-enabling. This allows us to preserve the user selected frequency across resets. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_pm.c | 34

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