On ke, 2017-02-22 at 16:52 +0100, Arkadiusz Hiler wrote:
> On Wed, Feb 22, 2017 at 04:30:49PM +0100, Arkadiusz Hiler wrote:
> >
> > On Wed, Feb 22, 2017 at 12:53:47PM +, Chris Wilson wrote:
> > >
> > > Now plan for having fw_path overriden by a i915_param.guc_firmware.
> > >
> > > Perhaps so
== Series Details ==
Series: GLK plane/scaling fixes (rev2)
URL : https://patchwork.freedesktop.org/series/20051/
State : success
== Summary ==
Series 20051v2 GLK plane/scaling fixes
https://patchwork.freedesktop.org/api/1.0/series/20051/revisions/2/mbox/
fi-bdw-5557u total:253 pass:242
As we handoff the GPU reset to the waiter, we need to check we don't
miss a wakeup if it has already been sent prior to us starting the wait.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers
On ke, 2017-02-22 at 16:29 +0100, Arkadiusz Hiler wrote:
> On Wed, Feb 22, 2017 at 03:59:01PM +0200, Joonas Lahtinen wrote:
> >
> > > + * @huc: intel_huc struct
> > > *
> > > * Called early during driver load, but after GEM is initialised. The
> > > loading
> > > * will continue only when d
It had only one callsite and existed to keep the code clearer. Now
having shared the wait-on-error between phases and with plans to change
the wait-for-execute in the next few patches, remove the out of line
wait loop and move it into the main body of i915_wait_request.
Signed-off-by: Chris Wilson
When dma_fence_signal() is called, it sets a flag to indicate the fence
is complete. Before the dma_fence is signaled, the seqno check will
first be passed. During an unlocked check (such as inside a waiter), it
is possible for the fence to be signaled even though the seqno has been
reset (by engin
Add a mock selftest to preempt a request and check that we cancel it,
requeue the request and then complete its execution.
v2: Error leaks no more.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/i915_gem_request.c | 64 +++
drivers/gpu/drm/i915/selftests/mock
If we change the wait_queue_t from using the autoremove_wake_function to
the default_wake_function, we no longer have to restore the wait_queue_t
entry on the wait_queue_head_t list after being woken up by it, as we
are unusual in sleeping multiple times on the same wait_queue_t.
Signed-off-by: Ch
Tvrkto ordered a stay of execution for the intel_wait_helpers.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Now that the code is getting simpler, we can reduce the indentation when
waiting for the global_seqno.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_request.c | 39 +++--
1 file changed, 18 insertions(+), 21 deletions(-)
d
A request is assigned a global seqno only when it is on the hardware
execution queue. The global seqno can be used to maintain a list of
requests on the same engine in retirement order, for example for
constructing a priority queue for waiting. Prior to its execution, or
if it is subsequently remov
Add ourselves to the gpu error waitqueue earlier on, even before we
determine we have to wait on the seqno. This is so that we can then
share the waitqueue between stages in subsequent patches.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu
Combine the common code for the pair of waiters into a single function.
v2: Rename reset_request to wait_request_check_and_reset
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/driv
After the request is cancelled, we then need to remove it from the
global execution timeline and return it to the context timeline, the
inverse of submit_request().
v2: Move manipulation of struct intel_wait to helpers
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i91
Move the companion functions next to each other.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_request.c | 161 +++-
1 file changed, 77 insertions(+), 84 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
Replace the global device seqno with one for each engine, and account
for in-flight seqno on each separately. This is consistent with
dma-fence as each timeline has separate fence-contexts for each engine
and a seqno is only ordered within a fence-context (i.e. seqno do not
need to be ordered wrt
Use a local variable to avoid having to type out the full name of the
gpu_error wait_queue.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_request.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
The plan in the near-future is to allow requests to be removed from the
signaler. We can no longer then rely on holding a reference to the
request for the duration it is in the signaling tree, and instead must
obtain a reference to the request for the current operation using RCU.
Signed-off-by: Ch
If we preempt a request and remove it from the execution queue, we need
to undo its global seqno and restart any waiters.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_breadcrumbs.c | 71 +---
drivers/gpu/drm/i915/intel_ringbu
On reflection, we are only using the execute fence as a waitqueue on the
global_seqno and not using it for dependency tracking between fences
(unlike the submit and dma fences). By only treating it as a waitqueue,
we can then treat it similar to the other waitqueues during submit,
making the code s
On Wed, Feb 22, 2017 at 10:18:33PM -0500, Lyude wrote:
> Now that we can just disable HPD storm detection, there's no need to
> sleep between each hotplug cycle.
>
> Signed-off-by: Lyude
> ---
> tests/chamelium.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/test
Geminilake has a third sprite plane (or fourth universal plane) that is
independent from the cursor. Make sure that for_each_plane_id_on_crtc()
is aware of that extra plane so that the watermark code takes it into
account.
Fixes: e9c9882556fc ("drm/i915/glk: Configure number of sprite planes prope
Ander Conselvan de Oliveira (4):
drm/i915/glk: Fix watermark computations for third sprite plane
drm/i915/glk: Fix maximum scaling factor for Geminilake scalers
drm/i915/glk: Pass dev_priv to intel_atomic_setup_scalers()
drm/i915/glk: Fix Geminilake scalers mode programming
drivers/gpu/dr
Pass dev_priv to intel_atomic_setup_scalers(). The next patch will need
a dev_priv pointer.
Cc: Ville Syrjälä
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_atomic.c | 10 +-
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h
Geminilake scalers can do 7x7 filtering for all supported input sizes,
so it doesn't need the "high quality" mode programming, which was
actually removed from that platform.
v2: Split dev_priv parameter change out. (Ville)
Cc: Ville Syrjälä ,
Signed-off-by: Ander Conselvan de Oliveira
---
drive
Geminilake can output two pixels per clock, and that affects the maximum
scaling factor for its scalers. Take that into account and avoid the
following warning:
WARNING: CPU: 1 PID: 593 at drivers/gpu/drm/i915/intel_display.c:13223
skl_max_scale.part.129+0x78/0x80 [i915]
WARN_ON_ONCE(!crtc_clock
Regards
Shashank
On 2/22/2017 10:59 PM, Ville Syrjälä wrote:
On Wed, Feb 22, 2017 at 06:48:30PM +0530, Shashank Sharma wrote:
Geminilake platform sports a native HDMI 2.0 controller, and is
capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
mendates scrambling for these higher clocks,
On Thu, Feb 16, 2017 at 9:46 AM, Ville Syrjälä
wrote:
> On Thu, Feb 16, 2017 at 09:24:09AM -0800, Manasi Navare wrote:
>> On Thu, Feb 16, 2017 at 07:18:57PM +0200, Ville Syrjälä wrote:
>> > On Thu, Feb 16, 2017 at 09:07:53AM -0800, Manasi Navare wrote:
>> > > On Thu, Feb 16, 2017 at 05:30:07PM +02
Regards
Shashank
On 2/22/2017 10:54 PM, Ville Syrjälä wrote:
On Wed, Feb 22, 2017 at 06:48:29PM +0530, Shashank Sharma wrote:
HDMI 2.0 spec mandates scrambling for modes with pixel clock higher
than 340 MHz. This patch adds few new functions in drm layer for
core drivers to enable/disable scr
Thanks for the review Ville, my comments inline.
Regards
Shashank
On 2/22/2017 10:39 PM, Ville Syrjälä wrote:
On Wed, Feb 22, 2017 at 06:48:26PM +0530, Shashank Sharma wrote:
From: Thierry Reding
SCDC is a mechanism defined in the HDMI 2.0 specification that allows
the source and sink devi
Recently we added i915_hpd_storm_ctl into i915's debugfs directory,
which allows us to control the thresholds i915 uses for detecting
hotplug interrupt storms from userspace, along with the ability to
entirely disable them. This adds some helper functions into IGT to
enable making use of this featu
Now that we can just disable HPD storm detection, there's no need to
sleep between each hotplug cycle.
Signed-off-by: Lyude
---
tests/chamelium.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/tests/chamelium.c b/tests/chamelium.c
index 849e1ac..810c955 100644
--- a/tes
On 22/02/17 18:31, Michel Thierry wrote:
v2: Use new igt_sysfs_write, add len > 0 assert in igt_sysfs_set to
catch future errors, clean-up strcasecmp logic (Chris).
Nevermind, didn't see you were faster than me...
___
Intel-gfx mailing list
Intel-gfx@
clear_error_state was not doing anything (igt_sysfs_set was not writing to
the error file because strlen was 0).
Also fix assert_entry to catch this issue; strcasecmp returns 0 when
there's a match, or an integer in a mismatch.
v2: Use new igt_sysfs_write, add len > 0 assert in igt_sysfs_set to
c
On 22/02/17 18:04, Chris Wilson wrote:
On Thu, Feb 23, 2017 at 01:52:04AM +, Chris Wilson wrote:
On Wed, Feb 22, 2017 at 05:26:29PM -0800, Michel Thierry wrote:
static void clear_error_state(void)
{
- igt_sysfs_set(sysfs, "error", "");
+ igt_sysfs_set(sysfs, "error", " ");
On Thu, Feb 23, 2017 at 01:52:04AM +, Chris Wilson wrote:
> On Wed, Feb 22, 2017 at 05:26:29PM -0800, Michel Thierry wrote:
> > static void clear_error_state(void)
> > {
> > - igt_sysfs_set(sysfs, "error", "");
> > + igt_sysfs_set(sysfs, "error", " ");
>
> My bad, I was expecting it writ
== Series Details ==
Series: drm/i915/guc: fix mmio whitelist mmio_start offset and add reminder
(rev2)
URL : https://patchwork.freedesktop.org/series/17287/
State : success
== Summary ==
Series 17287v2 drm/i915/guc: fix mmio whitelist mmio_start offset and add
reminder
https://patchwork.fre
On Wed, Feb 22, 2017 at 05:26:29PM -0800, Michel Thierry wrote:
> clear_error_state was not doing anything (igt_sysfs_set was not writing to
> the error file).
>
> Also fix assert_entry to catch this issue; strcasecmp returns 0 when
> there's a match, or an integer in a mismatch.
>
> Finally, onl
clear_error_state was not doing anything (igt_sysfs_set was not writing to
the error file).
Also fix assert_entry to catch this issue; strcasecmp returns 0 when
there's a match, or an integer in a mismatch.
Finally, only print part of the error string when the assert fails.
Cc: Chris Wilson
Fix
The mmio_start offset for the whitelist is the first FORCE_TO_NONPRIV
register the GuC can use to restore the provided whitelist when an
engine reset via GuC (which we still don't support) is triggered.
We're currently adding the mmio_base of the engine to the absolute
address of the RCS version o
Thanks Imre. I see, it's a little hard to read, need to check the final state
across 2 level function return value.
Thanks.
Best Regards.
Weinan, LI
> -Original Message-
> From: Deak, Imre
> Sent: Wednesday, February 22, 2017 4:56 PM
> To: Li, Weinan Z
> Cc: intel-gfx@lists.freedesktop
On Wed, Feb 22, 2017 at 06:02:46PM +, Chris Wilson wrote:
> On Wed, Feb 22, 2017 at 11:39:30AM +, Chris Wilson wrote:
> > On Wed, Feb 22, 2017 at 01:27:41PM +0200, Joonas Lahtinen wrote:
> > > On ma, 2017-02-20 at 12:47 +, Chris Wilson wrote:
> > > > Testing with concurrent GGTT accesse
== Series Details ==
Series: drm/i915/: DMC 1.04 for Geminilake
URL : https://patchwork.freedesktop.org/series/20091/
State : warning
== Summary ==
Series 20091v1 drm/i915/: DMC 1.04 for Geminilake
https://patchwork.freedesktop.org/api/1.0/series/20091/revisions/1/mbox/
Test prime_vgem:
On Wed, 2017-02-22 at 09:59 +0530, Archit Taneja wrote:
>
> On 02/22/2017 05:31 AM, Pandiyan, Dhinakaran wrote:
> > On Fri, 2017-02-17 at 15:37 +0530, Archit Taneja wrote:
> >>
> >> On 02/16/2017 05:43 AM, Pandiyan, Dhinakaran wrote:
> >>> On Wed, 2017-02-15 at 16:53 +0530, Archit Taneja wrote:
>
On Wed, Feb 22, 2017 at 08:52:45PM -, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v2,01/15] drm/i915: Keep a global seqno
> per-engine (rev2)
> URL : https://patchwork.freedesktop.org/series/20056/
> State : warning
>
> == Summary ==
>
> Series 20056v2 Series
== Series Details ==
Series: series starting with [v2,01/15] drm/i915: Keep a global seqno
per-engine (rev2)
URL : https://patchwork.freedesktop.org/series/20056/
State : warning
== Summary ==
Series 20056v2 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/20056/re
== Series Details ==
Series: drm/i915: Check against the signaled bit for fences/requests (rev2)
URL : https://patchwork.freedesktop.org/series/20085/
State : warning
== Summary ==
Series 20085v2 drm/i915: Check against the signaled bit for fences/requests
https://patchwork.freedesktop.org/api
There is a nre version of DMC available for GLK.
The release notes mentions:
This FW has the fix to remove the hang conditions due to
some debug related issues.
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_csr.c | 4 ++--
1 file changed, 2 insertions(+), 2 del
== Series Details ==
Series: series starting with [1/5] drm/i915/gtt: Prefer i915_vm_is_48bit() over
macro
URL : https://patchwork.freedesktop.org/series/20086/
State : success
== Summary ==
Series 20086v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/20086/revi
== Series Details ==
Series: Enable OA unit for Gen 8 and 9 in i915 perf
URL : https://patchwork.freedesktop.org/series/20084/
State : success
== Summary ==
Series 20084v1 Enable OA unit for Gen 8 and 9 in i915 perf
https://patchwork.freedesktop.org/api/1.0/series/20084/revisions/1/mbox/
fi-b
After the request is cancelled, we then need to remove it from the
global execution timeline and return it to the context timeline, the
inverse of submit_request().
v2: Move manipulation of struct intel_wait to helpers
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: don't leak the gem object
URL : https://patchwork.freedesktop.org/series/20077/
State : success
== Summary ==
Series 20077v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/20077/revisions/
== Series Details ==
Series: Some minor i915-perf prep changes
URL : https://patchwork.freedesktop.org/series/20073/
State : success
== Summary ==
Series 20073v1 Some minor i915-perf prep changes
https://patchwork.freedesktop.org/api/1.0/series/20073/revisions/1/mbox/
fi-bdw-5557u total:2
On Wed, Feb 22, 2017 at 04:53:35PM +, Tvrtko Ursulin wrote:
>
> On 17/02/2017 15:51, Chris Wilson wrote:
> > if (engine->irq_seqno_barrier &&
> >-rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current &&
> > test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_po
On Wed, Feb 22, 2017 at 11:39:30AM +, Chris Wilson wrote:
> On Wed, Feb 22, 2017 at 01:27:41PM +0200, Joonas Lahtinen wrote:
> > On ma, 2017-02-20 at 12:47 +, Chris Wilson wrote:
> > > Testing with concurrent GGTT accesses no longer show the coherency
> > > problems from yonder, commit 5bab
When dma_fence_signal() is called, it sets a flag to indicate the fence
is complete. Before the dma_fence is signaled, the seqno check will
first be passed. During an unlocked check (such as inside a waiter), it
is possible for the fence to be signaled even though the seqno has been
reset (by engin
== Series Details ==
Series: drm/i915/lspcon: Switch back to PCON mode after output replug (rev2)
URL : https://patchwork.freedesktop.org/series/20072/
State : success
== Summary ==
Series 20072v2 drm/i915/lspcon: Switch back to PCON mode after output replug
https://patchwork.freedesktop.org/a
On Wed, Feb 22, 2017 at 05:26:34PM +, Tvrtko Ursulin wrote:
>
> On 17/02/2017 15:51, Chris Wilson wrote:
> >A significant cost in setting up a wait is the overhead of enabling the
> >interrupt. As we disable the interrupt whenever the queue of waiters is
> >empty, if we are frequently waiting
On Wed, Feb 22, 2017 at 05:30:59PM +, Tvrtko Ursulin wrote:
>
> On 22/02/2017 16:42, Chris Wilson wrote:
> >When dma_fence_signal() is called, it sets a flag to indicate the fenece
> >is complete. Before the dma_fence is signaled, the seqno check will
> >first be passed. However, if the reques
On 22/02/2017 16:42, Chris Wilson wrote:
When dma_fence_signal() is called, it sets a flag to indicate the fenece
is complete. Before the dma_fence is signaled, the seqno check will
first be passed. However, if the request is being held by an observer
across a global seqno reset, it is possible
On Wed, Feb 22, 2017 at 06:48:30PM +0530, Shashank Sharma wrote:
> Geminilake platform sports a native HDMI 2.0 controller, and is
> capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
> mendates scrambling for these higher clocks, for reduced RF footprint.
>
> This patch checks if the moni
On 17/02/2017 15:51, Chris Wilson wrote:
A significant cost in setting up a wait is the overhead of enabling the
interrupt. As we disable the interrupt whenever the queue of waiters is
empty, if we are frequently waiting on alternating batches, we end up
re-enabling the interrupt on a frequent b
On Wed, Feb 22, 2017 at 06:54:24PM +0200, Mika Kuoppala wrote:
> The pdp rewrite to force tlb flush is only a 32bit ppgtt
> trick. That should not be needed with 48bit ppgtt.
>
> Cc: Chris Wilson
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
> 1 file change
On Wed, Feb 22, 2017 at 06:48:29PM +0530, Shashank Sharma wrote:
> HDMI 2.0 spec mandates scrambling for modes with pixel clock higher
> than 340 MHz. This patch adds few new functions in drm layer for
> core drivers to enable/disable scrambling.
>
> This patch adds:
> - A function to detect scram
== Series Details ==
Series: HDMI 2.0: Scrambling in DRM layer (rev4)
URL : https://patchwork.freedesktop.org/series/19161/
State : success
== Summary ==
Series 19161v4 HDMI 2.0: Scrambling in DRM layer
https://patchwork.freedesktop.org/api/1.0/series/19161/revisions/4/mbox/
fi-bdw-5557u
On Wed, Feb 22, 2017 at 06:54:25PM +0200, Mika Kuoppala wrote:
> If we manage to tangle errorpaths and get call to callbacks,
> it is better to defensively keep them as null until object init is
> finished so that we get clean null deref on callsite,
> instead of more cryptic wreckage with partly i
On Wed, Feb 22, 2017 at 06:54:23PM +0200, Mika Kuoppala wrote:
> Instead of using the subjective term legacy, use more descriptive and
> less loaded name '32bit' where appropriate.
Hmm. We have a mix of 32/48bit and 3/4 level. I think here we are better
using e.g.
gen8_mm_switch_3lvl
On Wed, Feb 22, 2017 at 06:54:22PM +0200, Mika Kuoppala wrote:
> Don't mark pdps clear if never do the necessary actions
> with the hardware to make them clear.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 17 -
> 1 file changed, 8 insertions(+), 9
On Wed, Feb 22, 2017 at 06:48:26PM +0530, Shashank Sharma wrote:
> From: Thierry Reding
>
> SCDC is a mechanism defined in the HDMI 2.0 specification that allows
> the source and sink devices to communicate.
>
> This commit introduces helpers to access the SCDC and provides the
> symbolic names
On Wed, Feb 22, 2017 at 04:53:35PM +, Tvrtko Ursulin wrote:
>
> On 17/02/2017 15:51, Chris Wilson wrote:
> >@@ -4034,9 +4038,8 @@ __i915_request_irq_complete(const struct
> >drm_i915_gem_request *req)
> > * is woken.
> > */
> > if (engine->irq_seqno_barrier &&
> >-rcu_ac
On 17/02/2017 15:51, Chris Wilson wrote:
As execlists and other non-semaphore multi-engine devices coordinate
between engines using interrupts, we can shave off a few 10s of
microsecond of scheduling latency by doing the fence signaling from the
interrupt as opposed to a RT kthread. (Realistical
Don't mark pdps clear if never do the necessary actions
with the hardware to make them clear.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm
Instead of using the subjective term legacy, use more descriptive and
less loaded name '32bit' where appropriate.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 20 ++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 8
drivers/gpu/drm/i915/intel_lrc.c
If we setup the vm size early, we can use the newly introduced
i915_vm_is_48bit() in majority of callsites wanting to know the vm size.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 58 +
1 file changed, 33 insertions(+), 25 deletions(
If we manage to tangle errorpaths and get call to callbacks,
it is better to defensively keep them as null until object init is
finished so that we get clean null deref on callsite,
instead of more cryptic wreckage with partly initialized vm objects.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/
The pdp rewrite to force tlb flush is only a 32bit ppgtt
trick. That should not be needed with 48bit ppgtt.
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_g
== Series Details ==
Series: drm: Add name for DRM_DP_DUAL_MODE_LSPCON
URL : https://patchwork.freedesktop.org/series/20062/
State : success
== Summary ==
Series 20062v1 drm: Add name for DRM_DP_DUAL_MODE_LSPCON
https://patchwork.freedesktop.org/api/1.0/series/20062/revisions/1/mbox/
fi-bdw-5
When dma_fence_signal() is called, it sets a flag to indicate the fenece
is complete. Before the dma_fence is signaled, the seqno check will
first be passed. However, if the request is being held by an observer
across a global seqno reset, it is possible for the observer to not
notice the seqno com
Assuming a uniform mask across all slices, this enables userspace to
determine the specific sub slices enabled. This information is required,
for example, to be able to analyse some OA counter reports where the
counter configuration depends on the HW sub slice configuration.
Signed-off-by: Robert
This extends i915 perf to support periodic sampling of OA metrics for BDW, CHV,
SKL and BXT.
I've recently been working through a number of issues that were uncovered once
I started adapting the gen7 IGT tests. Some further issues were also noticed by
others using INTEL_performance_query in Mesa.
Enables userspace to determine the number of slices enabled and also
know what specific slices are enabled. This information is required, for
example, to be able to analyse some OA counter reports where the counter
configuration depends on the HW slice configuration.
Signed-off-by: Robert Bragg
-
Since the exponent for periodic OA counter sampling is maintained in a
per-context register while we want to treat it as if it were global
state we need to be able to safely issue an mmio write to a per-context
register and affect any currently running context.
We have to take some extra care in t
Adds a static OA unit, MUX, B Counter + Flex EU configurations for basic
render metrics on Broadwell, Cherryview, Skylake and Broxton. These are
auto generated from an XML description of metric sets, currently
maintained in gputop, ref:
https://github.com/rib/gputop
> gputop-data/oa-*.xml
> scr
Enables access to OA unit metrics for BDW, CHV, SKL and BXT which all
share (more-or-less) the same OA unit design.
Of particular note in comparison to Haswell: some OA unit HW config
state has become per-context state and as a consequence it is somewhat
more complicated to manage synchronous stat
On 22 February 2017 at 16:12, Chris Wilson wrote:
> On Wed, Feb 22, 2017 at 04:01:06PM +, Matthew Auld wrote:
>> Always use i915_gem_object_put over i915_gem_object_free if we can.
>>
>> Signed-off-by: Matthew Auld
>> Cc: Chris Wilson
>> Cc: Joonas Lahtinen
>> ---
>> drivers/gpu/drm/i915/i
== Series Details ==
Series: GuC Scrub vol. 1 (rev4)
URL : https://patchwork.freedesktop.org/series/16856/
State : success
== Summary ==
Series 16856v4 GuC Scrub vol. 1
https://patchwork.freedesktop.org/api/1.0/series/16856/revisions/4/mbox/
fi-bdw-5557u total:253 pass:242 dwarn:0 dfa
On Wed, Feb 22, 2017 at 04:01:05PM +, Matthew Auld wrote:
> For our fake dma objects we can leak the underlying gem object if we
> fail to pin our "backing storage".
>
> [ 39.952618]
> =
> [ 39.952625] BUG mock_ob
On Wed, Feb 22, 2017 at 04:01:06PM +, Matthew Auld wrote:
> Always use i915_gem_object_put over i915_gem_object_free if we can.
>
> Signed-off-by: Matthew Auld
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> ---
> drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +-
> 1 file changed, 1 insertion(+),
For our fake dma objects we can leak the underlying gem object if we
fail to pin our "backing storage".
[ 39.952618]
=
[ 39.952625] BUG mock_object (Tainted: G U ): Objects remaining
in mock_object on __k
Always use i915_gem_object_put over i915_gem_object_free if we can.
Signed-off-by: Matthew Auld
Cc: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c
b/drivers/
== Series Details ==
Series: drm/i915: Stop using RP_DOWN_EI on Baytrail (rev2)
URL : https://patchwork.freedesktop.org/series/20019/
State : success
== Summary ==
Series 20019v2 drm/i915: Stop using RP_DOWN_EI on Baytrail
https://patchwork.freedesktop.org/api/1.0/series/20019/revisions/2/mbox
On Wed, Feb 22, 2017 at 04:30:49PM +0100, Arkadiusz Hiler wrote:
> On Wed, Feb 22, 2017 at 12:53:47PM +, Chris Wilson wrote:
> > On Wed, Feb 22, 2017 at 01:41:25PM +0100, Arkadiusz Hiler wrote:
> > > Currently fw->path values can represent one of three possible states:
> > >
> > > 1) NULL - d
This updates the tail pointer race workaround handling to updating the
'aged' pointer before looking to start aging a new one. There's the
possibility that there is already new data available and so we can
immediately start aging a new pointer without having to first wait for a
later hrtimer callba
On Wed, Feb 22, 2017 at 12:53:47PM +, Chris Wilson wrote:
> On Wed, Feb 22, 2017 at 01:41:25PM +0100, Arkadiusz Hiler wrote:
> > Currently fw->path values can represent one of three possible states:
> >
> > 1) NULL - device without the uC
> > 2) '\0' - device with the uC but have no firmware
On Wed, Feb 22, 2017 at 03:59:01PM +0200, Joonas Lahtinen wrote:
> On ke, 2017-02-22 at 13:41 +0100, Arkadiusz Hiler wrote:
> > Trying to have subject_verb_object ordering and more descriptive names,
> > the intel_huc_init() and intel_guc_init() functions are renamed:
> >
> > * `intel_guc` is the
A minor improvement to debugging output
Signed-off-by: Robert Bragg
---
drivers/gpu/drm/i915/i915_perf.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 383b5769a851..19d0e4222974 100644
--- a/dri
This change is pre-emptively aiming to avoid a potential cause of kernel
logging noise in case some condition were to result in us seeing invalid
OA reports.
The workaround for the OA unit's tail pointer race condition is what
avoids the primary know cause of invalid reports being seen and with
th
A small set of i915 perf changes that could ideally land before the gen8+
patches I hope to send out soon.
These are based on top of the gen7 tail pointer race workaround changes that
were sent out recently.
Robert Bragg (3):
drm/i915/perf: improve invalid OA format debug message
drm/i915/per
At least a ParadTech PS175 LSPCON chip/firmware uses long instead of
short pulses to signal output unplug/plug events. This is contrary to
how branch devices normally work which use short HPD signaling. This
chip will also switch to LS mode after an unplug event, which could be
the consequence of t
On 22/02/2017 14:26, Chris Wilson wrote:
On Wed, Feb 22, 2017 at 02:16:49PM +, Tvrtko Ursulin wrote:
On 22/02/2017 11:46, Chris Wilson wrote:
Combine the common code for the pair of waiters into a single function.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c |
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