Re: [Intel-gfx] [PATCH 09/18] drm/i915: support inserting 64K pages in the ppgtt

Hi Matthew, [auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on next-20170405] [cannot apply to v4.11-rc5] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Matthew

Re: [Intel-gfx] [PATCH] drm/atomic: Add connector atomic_check function.

On Wed, 2017-04-05 at 12:06 +0200, Daniel Vetter wrote: > On Wed, Apr 05, 2017 at 10:41:24AM +0200, Maarten Lankhorst wrote: > > The connector atomic check function may be called multiple times, > > or not at all. It's mostly useful for implementing properties but if you > > call check_modeset

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Use the right mapping_gfp_mask for final shmem allocation

== Series Details == Series: drm/i915: Use the right mapping_gfp_mask for final shmem allocation URL : https://patchwork.freedesktop.org/series/22554/ State : success == Summary == Series 22554v1 drm/i915: Use the right mapping_gfp_mask for final shmem allocation

[Intel-gfx] [PATCH] drm/i915: Use the right mapping_gfp_mask for final shmem allocation

Many sightings report the greater prevalence of allocation failures. This is all due to the incorrect use of mapping_gfp_constraint(), so remove it in favour of just querying the mapping_gfp_mask() which are the exact gfp_t we wanted in the first place. We still do expect a higher chance of

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Treat WC a separate cache domain

== Series Details == Series: drm/i915: Treat WC a separate cache domain URL : https://patchwork.freedesktop.org/series/22549/ State : success == Summary == Series 22549v1 drm/i915: Treat WC a separate cache domain https://patchwork.freedesktop.org/api/1.0/series/22549/revisions/1/mbox/

[Intel-gfx] [PATCH] drm/i915: Treat WC a separate cache domain

When discussing a new WC mmap, we based the interface upon the assumption that GTT was fully coherent. How naive! Commits 3b5724d702ef ("drm/i915: Wait for writes through the GTT to land before reading back") and ed4596ea992d ("drm/i915/guc: WA to address the Ringbuffer coherency issue")

[Intel-gfx] [maintainer-tools PATCH v2] dim: Add examples section to dim.rst

Along with a recipe for creating a topic branch and sending a pull request from it. Signed-off-by: Sean Paul --- Changes in v2: - Address danvet's comments - added paragraph about selecting a baseline - s_origin/master_*baseline*_ - s/build test/test/ -

Re: [Intel-gfx] [PATCH 00/15] acquire ctx wire-up, part 2

On Mon, Apr 3, 2017 at 4:32 AM, Daniel Vetter wrote: > Hi all, > > Partially this is a resend of the patches now unblocked by the vmwgfx atomic > conversion just merged. I could entirely drop the vmwgfx patch since it's all > fixed now. > > Then a bit of follow-up, plus

Re: [Intel-gfx] [PATCH 04/15] drm/atomic-helper: remove modeset_lock_all from helper_resume

On Mon, Apr 3, 2017 at 4:32 AM, Daniel Vetter wrote: > Atomic code rely shouldn't rely on the magic hidden acquire context. Repeated rely in commit message. I'm assuming you mean: "Atomic code shouldn't rely on the magic hidden acquire context." > > v2: Remove unused

[Intel-gfx] ✓ Fi.CI.BAT: success for Enable OA unit for Gen 8 and 9 in i915 perf (rev5)

== Series Details == Series: Enable OA unit for Gen 8 and 9 in i915 perf (rev5) URL : https://patchwork.freedesktop.org/series/20084/ State : success == Summary == Series 20084v5 Enable OA unit for Gen 8 and 9 in i915 perf

[Intel-gfx] [PATCH v2] drm/i915/perf: per-gen timebase for checking sample freq

An oa_exponent_to_ns() utility and per-gen timebase constants where recently removed when updating the tail pointer race condition WA, and this restores those so we can update the _PROP_OA_EXPONENT validation done in read_properties_unlocked() to not assume we have a 12.5MHz timebase as we did for

Re: [Intel-gfx] [PATCH v3 6/7] drm/i915/perf: per-gen timebase for checking sample freq

On Wed, Apr 5, 2017 at 6:26 PM, Ville Syrjälä wrote: > On Wed, Apr 05, 2017 at 06:17:36PM +0100, Lionel Landwerlin wrote: > > On 05/04/17 18:06, Ville Syrjälä wrote: > > > On Wed, Apr 05, 2017 at 05:23:19PM +0100, Robert Bragg wrote: > > >> An oa_exponent_to_ns()

Re: [Intel-gfx] [PATCH v3 6/7] drm/i915/perf: per-gen timebase for checking sample freq

On Wed, Apr 05, 2017 at 06:17:36PM +0100, Lionel Landwerlin wrote: > On 05/04/17 18:06, Ville Syrjälä wrote: > > On Wed, Apr 05, 2017 at 05:23:19PM +0100, Robert Bragg wrote: > >> An oa_exponent_to_ns() utility and per-gen timebase constants where > >> recently removed when updating the tail

Re: [Intel-gfx] [PATCH v3 6/7] drm/i915/perf: per-gen timebase for checking sample freq

On 05/04/17 18:06, Ville Syrjälä wrote: On Wed, Apr 05, 2017 at 05:23:19PM +0100, Robert Bragg wrote: An oa_exponent_to_ns() utility and per-gen timebase constants where recently removed when updating the tail pointer race condition WA, and this restores those so we can update the

Re: [Intel-gfx] [PATCH v3 6/7] drm/i915/perf: per-gen timebase for checking sample freq

On Wed, Apr 05, 2017 at 05:23:19PM +0100, Robert Bragg wrote: > An oa_exponent_to_ns() utility and per-gen timebase constants where > recently removed when updating the tail pointer race condition WA, and > this restores those so we can update the _PROP_OA_EXPONENT validation > done in

[Intel-gfx] ✓ Fi.CI.BAT: success for Classify the engines in class + instance

== Series Details == Series: Classify the engines in class + instance URL : https://patchwork.freedesktop.org/series/22535/ State : success == Summary == Series 22535v1 Classify the engines in class + instance https://patchwork.freedesktop.org/api/1.0/series/22535/revisions/1/mbox/

Re: [Intel-gfx] [PATCH v3 6/7] drm/i915/perf: per-gen timebase for checking sample freq

Hey Rob, Thanks for sending this, it looks good to me. I think we also need to update the oa_sample_rate_hard_limit & i915_oa_max_sample_rate variables. This patch is : Reviewed-by: Lionel Landwerlin On 05/04/17 17:23, Robert Bragg wrote: An

Re: [Intel-gfx] [PATCH i-g-t v3] benchmarks/gem_wsim: Command submission workload simulator

On Wed, Apr 05, 2017 at 05:14:01PM +0100, Tvrtko Ursulin wrote: > +static void > +__emit_bb_end(struct w_step *w, bool terminate, bool seqnos, uint32_t seqno) > +{ > + const uint32_t bbe = 0xa << 23; > + unsigned long bb_sz = get_bb_sz(>duration); > + unsigned long mmap_start,

[Intel-gfx] ✓ Fi.CI.BAT: success for Enable OA unit for Gen 8 and 9 in i915 perf (rev4)

== Series Details == Series: Enable OA unit for Gen 8 and 9 in i915 perf (rev4) URL : https://patchwork.freedesktop.org/series/20084/ State : success == Summary == Series 20084v4 Enable OA unit for Gen 8 and 9 in i915 perf

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915: Suspend GuC prior to GPU Reset during GEM suspend

On 05/04/17 05:24, Chris Wilson wrote: On Wed, Apr 05, 2017 at 03:51:50PM +0530, Sagar Arun Kamble wrote: i915 is currently doing Full GPU reset at the end of suspend followed by GuC suspend. This reset bypasses the GuC. We need to tell the GuC to suspend before we do a direct

[Intel-gfx] [PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

Cc: Tvrtko Ursulin Cc: Paulo Zanoni Cc: Rodrigo Vivi Cc: Chris Wilson Cc: Daniele Ceraolo Spurio Signed-off-by: Oscar Mateo ---

[Intel-gfx] [PATCH 2/5] drm/i915: Use the same vfunc for BSD2 ring init

If we needed to do something different for the init functions, we could always look at the instance number to make the distinction.But, in any case, the two functions are virtually identical already (please notice that BSD2_RING is only used from gen8 onwards). Cc: Tvrtko Ursulin

[Intel-gfx] [PATCH 0/5] Classify the engines in class + instance

This refactoring helps simplify a few things here and there. Daniele Ceraolo Spurio (2): drm/i915: Classify the engines in class + instance drm/i915: Use the engine class to get the context size Oscar Mateo (3): drm/i915: Use the same vfunc for BSD2 ring init drm/i915: Generate the

[Intel-gfx] [PATCH 1/5] drm/i915: Classify the engines in class + instance

From: Daniele Ceraolo Spurio In such a way that vcs and vcs2 are just two different instances (0 and 1) of the same engine class (VIDEO_DECODE_CLASS). Cc: Tvrtko Ursulin Cc: Paulo Zanoni Cc: Rodrigo Vivi

[Intel-gfx] [PATCH 5/5] drm/i915: Use the engine class to get the context size

From: Daniele Ceraolo Spurio Technically speaking, the context size is per engine class, not per instance. Cc: Tvrtko Ursulin Cc: Paulo Zanoni Cc: Rodrigo Vivi Cc: Chris Wilson

[Intel-gfx] [PATCH 3/5] drm/i915: Generate the engine name based on the instance number

Not really needed, but makes the next change a little bit more compact. Cc: Tvrtko Ursulin Cc: Paulo Zanoni Cc: Rodrigo Vivi Cc: Chris Wilson Cc: Daniele Ceraolo Spurio

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915: Assert the engine is idle before overwiting the HWS (rev2)

== Series Details == Series: series starting with [1/2] drm/i915: Assert the engine is idle before overwiting the HWS (rev2) URL : https://patchwork.freedesktop.org/series/22527/ State : warning == Summary == Series 22527v2 Series without cover letter

[Intel-gfx] [PATCH v3 6/7] drm/i915/perf: per-gen timebase for checking sample freq

An oa_exponent_to_ns() utility and per-gen timebase constants where recently removed when updating the tail pointer race condition WA, and this restores those so we can update the _PROP_OA_EXPONENT validation done in read_properties_unlocked() to not assume we have a 12.5KHz timebase as we did for

[Intel-gfx] [PATCH v3 4/7] drm/i915/perf: Add OA unit support for Gen 8+

Enables access to OA unit metrics for BDW, CHV, SKL and BXT which all share (more-or-less) the same OA unit design. Of particular note in comparison to Haswell: some OA unit HW config state has become per-context state and as a consequence it is somewhat more complicated to manage synchronous

[Intel-gfx] [PATCH v3 1/7] drm/i915: expose _SLICE_MASK GETPARM

Enables userspace to determine the number of slices enabled and also know what specific slices are enabled. This information is required, for example, to be able to analyse some OA counter reports where the counter configuration depends on the HW slice configuration. Signed-off-by: Robert Bragg

[Intel-gfx] [PATCH v3 7/7] drm/i915/perf: remove perf.hook_lock

In earlier iterations of the i915-perf driver we had a number of callbacks/hooks from other parts of the i915 driver to e.g. notify us when a legacy context was pinned and these could run asynchronously with respect to the stream file operations and might also run in atomic context.

[Intel-gfx] [PATCH v3 2/7] drm/i915: expose _SUBSLICE_MASK GETPARM

Assuming a uniform mask across all slices, this enables userspace to determine the specific sub slices enabled. This information is required, for example, to be able to analyse some OA counter reports where the counter configuration depends on the HW sub slice configuration. Signed-off-by: Robert

[Intel-gfx] [PATCH v3 3/7] drm/i915/perf: Add 'render basic' Gen8+ OA unit configs

Adds a static OA unit, MUX, B Counter + Flex EU configurations for basic render metrics on Broadwell, Cherryview, Skylake and Broxton. These are auto generated from an XML description of metric sets, currently maintained in gputop, ref: https://github.com/rib/gputop > gputop-data/oa-*.xml >

[Intel-gfx] [PATCH v3 0/7] Enable OA unit for Gen 8 and 9 in i915 perf

Adds some R/Bs from from Matthew and some updates based on Matthew's feedback Notably the 'Add OA unit support for Gen 8+' patch now avoids duplicating lots of fiddly tail race workaround code by adding a vfunc for reading the OA tail pointer register. Robert Bragg (7): drm/i915: expose

[Intel-gfx] [PATCH i-g-t v3] benchmarks/gem_wsim: Command submission workload simulator

From: Tvrtko Ursulin Tool which emits batch buffers to engines with configurable sequences, durations, contexts, dependencies and userspace waits. Unfinished but shows promise so sending out for early feedback. v2: * Load workload descriptors from files. (also -w) *

[Intel-gfx] ✓ Fi.CI.BAT: success for Some minor i915-perf prep changes (rev3)

== Series Details == Series: Some minor i915-perf prep changes (rev3) URL : https://patchwork.freedesktop.org/series/20073/ State : success == Summary == Series 20073v3 Some minor i915-perf prep changes https://patchwork.freedesktop.org/api/1.0/series/20073/revisions/3/mbox/ Test kms_flip:

Re: [Intel-gfx] [PATCH v3] drm/i915/perf: rate limit spurious oa report notice

On 04/05, Robert Bragg wrote: > Instead of initializing and summarising the number of throttled messages in > the driver _init / _fini we now do this when opening / closing an OA stream. > > --- >8 --- > > This change is pre-emptively aiming to avoid a potential cause of kernel > logging noise

[Intel-gfx] [PATCH v2] drm/i915: Advance ring->head fully when idle

When we retire the last request on the ring, before we ever access that ring again we know it will be completely idle and so we can advance the ring->head fully to the end (i.e. ring->tail) and not just to the start of the breadcrumb. This allows us to skip re-emitting the breadcrumb after

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915: Suspend GuC prior to GPU Reset during GEM suspend

On 2017-04-05 18:46, Kamble, Sagar A wrote: On 4/5/2017 6:32 PM, David Weinehall wrote: On 2017-04-05 15:54, Joonas Lahtinen wrote: On ke, 2017-04-05 at 15:51 +0530, Sagar Arun Kamble wrote: i915 is currently doing Full GPU reset at the end of suspend followed by GuC suspend. This reset

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Assert the engine is idle before overwiting the HWS

== Series Details == Series: series starting with [1/2] drm/i915: Assert the engine is idle before overwiting the HWS URL : https://patchwork.freedesktop.org/series/22527/ State : failure == Summary == Series 22527v1 Series without cover letter

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915: Suspend GuC prior to GPU Reset during GEM suspend

On 4/5/2017 6:32 PM, David Weinehall wrote: On 2017-04-05 15:54, Joonas Lahtinen wrote: On ke, 2017-04-05 at 15:51 +0530, Sagar Arun Kamble wrote: i915 is currently doing Full GPU reset at the end of suspend followed by GuC suspend. This reset bypasses the GuC. We need to tell the GuC to

[Intel-gfx] [PATCH v3] drm/i915/perf: rate limit spurious oa report notice

Instead of initializing and summarising the number of throttled messages in the driver _init / _fini we now do this when opening / closing an OA stream. --- >8 --- This change is pre-emptively aiming to avoid a potential cause of kernel logging noise in case some condition were to result in us

Re: [Intel-gfx] [PATCH v2 5/5] drm/i915: Add more OA configs for BDW, CHV, SKL + BXT

On Mon, Mar 27, 2017 at 7:16 PM, Matthew Auld < matthew.william.a...@gmail.com> wrote: > On 03/23, Robert Bragg wrote: > > These are auto generated from an XML description of metric sets, > > currently maintained in gputop, ref: > > > > https://github.com/rib/gputop > > > gputop-data/oa-*.xml >

[Intel-gfx] [PATCH 2/2] drm/i915: Advance ring->head fully when idle

When we retire the last request on the ring, before we ever access that ring again we know it will be completely idle and so we can advance the ring->head fully to the end (i.e. ring->tail) and not just to the start of the breadcrumb. This allows us to skip re-emitting the breadcrumb after

[Intel-gfx] [PATCH 1/2] drm/i915: Assert the engine is idle before overwiting the HWS

When we update the global seqno (on the engine timeline), we modify HW state (both registers and mapped pages). As we do this, we should be sure that the HW is idle and we are not causing a conflict. The caller is supposed to wait_for_idle before calling us to update the seqno, so let's assert

Re: [Intel-gfx] [PATCH 07/18] drm/i915: introduce ppgtt page coloring

On 5 April 2017 at 15:02, Chris Wilson wrote: > On Wed, Apr 05, 2017 at 02:50:41PM +0100, Matthew Auld wrote: >> On 5 April 2017 at 14:41, Chris Wilson wrote: >> > On Tue, Apr 04, 2017 at 11:11:17PM +0100, Matthew Auld wrote: >> >> To enable

Re: [Intel-gfx] [PATCH 07/18] drm/i915: introduce ppgtt page coloring

On Wed, Apr 05, 2017 at 02:50:41PM +0100, Matthew Auld wrote: > On 5 April 2017 at 14:41, Chris Wilson wrote: > > On Tue, Apr 04, 2017 at 11:11:17PM +0100, Matthew Auld wrote: > >> To enable 64K pages we need to set the intermediate-page-size(IPS) bit > >> of the pde,

Re: [Intel-gfx] [PATCH 07/18] drm/i915: introduce ppgtt page coloring

On 5 April 2017 at 14:41, Chris Wilson wrote: > On Tue, Apr 04, 2017 at 11:11:17PM +0100, Matthew Auld wrote: >> To enable 64K pages we need to set the intermediate-page-size(IPS) bit >> of the pde, therefore a page table is said to be either operating in 64K >> or 4K

Re: [Intel-gfx] [PATCH 0/3] drm/i915: Fix SKL+ 90/270 degree rotated scanout

On Fri, Mar 31, 2017 at 10:23:18PM +0100, Chris Wilson wrote: > On Fri, Mar 31, 2017 at 09:00:53PM +0300, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > I figured it's about time I fix what I broke with my fb offset stuff. > > I've posted the

Re: [Intel-gfx] [PATCH 07/18] drm/i915: introduce ppgtt page coloring

On Tue, Apr 04, 2017 at 11:11:17PM +0100, Matthew Auld wrote: > To enable 64K pages we need to set the intermediate-page-size(IPS) bit > of the pde, therefore a page table is said to be either operating in 64K > or 4K mode. To accommodate this vm placement restriction we introduce a > color for

Re: [Intel-gfx] [PATCH 09/15] drm/msm: Nerf zpos property

On Mon, Apr 03, 2017 at 10:32:58AM +0200, Daniel Vetter wrote: > It's not wired up, and if it is, it should be moved over to the new > fancy standardized zpos property exposed through > drm_plane_create_zpos_property(). > > Cc: Rob Clark > Signed-off-by: Daniel Vetter

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/glk: limit pixel clock to 99% of cdclk workaround (rev2)

== Series Details == Series: drm/i915/glk: limit pixel clock to 99% of cdclk workaround (rev2) URL : https://patchwork.freedesktop.org/series/22404/ State : success == Summary == Series 22404v2 drm/i915/glk: limit pixel clock to 99% of cdclk workaround

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Only report a wakeup if the waiter was truly asleep (rev2)

== Series Details == Series: drm/i915: Only report a wakeup if the waiter was truly asleep (rev2) URL : https://patchwork.freedesktop.org/series/22445/ State : success == Summary == Series 22445v2 drm/i915: Only report a wakeup if the waiter was truly asleep

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915: Suspend GuC prior to GPU Reset during GEM suspend

On 2017-04-05 15:54, Joonas Lahtinen wrote: On ke, 2017-04-05 at 15:51 +0530, Sagar Arun Kamble wrote: i915 is currently doing Full GPU reset at the end of suspend followed by GuC suspend. This reset bypasses the GuC. We need to tell the GuC to suspend before we do a direct intel_gpu_reset,

[Intel-gfx] [PATCH] drm/i915/glk: limit pixel clock to 99% of cdclk workaround

As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz. Practically we can achive only 99% of these cdclk values (HW team checking on this). So cdclk should be calculated for the given pixclk as per that otherwise it may lead to screen corruption, explained below: 1. For DSI AUO

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915: Suspend GuC prior to GPU Reset during GEM suspend

On Wed, Apr 05, 2017 at 03:54:27PM +0300, Joonas Lahtinen wrote: > On ke, 2017-04-05 at 15:51 +0530, Sagar Arun Kamble wrote: > > i915 is currently doing Full GPU reset at the end of suspend followed by > > GuC suspend. This reset bypasses the GuC. We need to tell the GuC to > > suspend before we

Re: [Intel-gfx] [PATCH 01/18] drm/i915: add page_size_mask to dev_info

On ke, 2017-04-05 at 09:45 +0100, Chris Wilson wrote: > > Also not in this patch. First patch is to set everything to the status > quo. Last patch will be to enable the (completed) feature on the > platforms using. In testing, that enabling patch comes early on to check > bisection of the series.

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915: Suspend GuC prior to GPU Reset during GEM suspend

On ke, 2017-04-05 at 15:51 +0530, Sagar Arun Kamble wrote: > i915 is currently doing Full GPU reset at the end of suspend followed by > GuC suspend. This reset bypasses the GuC. We need to tell the GuC to > suspend before we do a direct intel_gpu_reset, Otherwise the gpu state will > no longer

[Intel-gfx] [PATCH v2] drm/i915: Only report a wakeup if the waiter was truly asleep

If we attempt to wake up a waiter, who is currently checking the seqno it will be in the TASK_INTERRUPTIBLE state and ttwu will report success. However, it is actually awake and functioning -- so delay reporting the actual wake up until it sleeps. v2: Defend against !CONFIG_SMP References:

Re: [Intel-gfx] [PATCH 02/18] drm/i915: introduce drm_i915_gem_object page_size members

On Wed, Apr 05, 2017 at 01:32:30PM +0100, Chris Wilson wrote: > An approach that might be interesting. On pinning the pages > (i.e. ops->get_pages) if we fill in the bitmask of page sizes, something > like > > for_each_sg() { > obj->mm.page_sizes |= fls(sg->length); > > obj->mm.pages_sizes

Re: [Intel-gfx] [PATCH 02/18] drm/i915: introduce drm_i915_gem_object page_size members

On Wed, Apr 05, 2017 at 11:07:55AM +0100, Matthew Auld wrote: > On 04/05, Chris Wilson wrote: > > On Wed, Apr 05, 2017 at 08:49:17AM +0200, Daniel Vetter wrote: > > > On Tue, Apr 04, 2017 at 11:11:12PM +0100, Matthew Auld wrote: > > > > diff --git a/drivers/gpu/drm/i915/i915_gem_object.h > > > >

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915: Suspend GuC prior to GPU Reset during GEM suspend

On Wed, Apr 05, 2017 at 03:51:50PM +0530, Sagar Arun Kamble wrote: > i915 is currently doing Full GPU reset at the end of suspend followed by > GuC suspend. This reset bypasses the GuC. We need to tell the GuC to > suspend before we do a direct intel_gpu_reset, Otherwise the gpu state will > no

Re: [Intel-gfx] [PATCH] drm/i915: Only report a wakeup if the waiter was truly asleep

Hi Chris, [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on next-20170405] [cannot apply to v4.11-rc5] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Chris-Wilson

Re: [Intel-gfx] [PATCH 02/18] drm/i915: introduce drm_i915_gem_object page_size members

On Wed, Apr 05, 2017 at 11:07:55AM +0100, Matthew Auld wrote: > On 04/05, Chris Wilson wrote: > > On Wed, Apr 05, 2017 at 08:49:17AM +0200, Daniel Vetter wrote: > > > On Tue, Apr 04, 2017 at 11:11:12PM +0100, Matthew Auld wrote: > > > > Signed-off-by: Matthew Auld > > > >

Re: [Intel-gfx] [PATCH maintainer-tools 3/3] dim.rst: update CONTRIBUTING instructions

On Wed, Apr 05, 2017 at 12:15:25PM +0100, Eric Engestrom wrote: > Suggest using git-config instead of a flag on format-patch. > While at it, use the more common "PATCH foo" subject prefix. > > Signed-off-by: Eric Engestrom > --- > dim.rst | 5 +++-- > 1 file changed,

Re: [Intel-gfx] [PATCH maintainer-tools 1/3] make: run check on current `dim`, not the installed one

On Wed, 05 Apr 2017, Eric Engestrom wrote: > Signed-off-by: Eric Engestrom For me "current dim" *is* the "installed one". ;) Pushed patches 1-2. BR, Jani. > --- > Makefile | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff

Re: [Intel-gfx] [PATCH maintainer-tools 3/3] dim.rst: update CONTRIBUTING instructions

On Wed, 05 Apr 2017, Eric Engestrom wrote: > Suggest using git-config instead of a flag on format-patch. > While at it, use the more common "PATCH foo" subject prefix. More common? That's all so subjective. And I've mostly used [dim PATCH]... BR, Jani. > >

Re: [Intel-gfx] [PATCH 08/15] drm/i915: Nuke intel_atomic_legacy_gamma_set

On Tue, Apr 04, 2017 at 12:44:26PM +0200, Maarten Lankhorst wrote: > Op 03-04-17 om 10:32 schreef Daniel Vetter: > > We do set DRIVER_ATOMIC now. > > > > Signed-off-by: Daniel Vetter > > --- > > drivers/gpu/drm/i915/intel_display.c | 44 > >

[Intel-gfx] [PATCH maintainer-tools 1/3] make: run check on current `dim`, not the installed one

Signed-off-by: Eric Engestrom --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index b4cea98..4291049 100644 --- a/Makefile +++ b/Makefile @@ -33,7 +33,7 @@ shellcheck: shellcheck $(SC_EXCLUDE) dim

[Intel-gfx] [PATCH maintainer-tools 3/3] dim.rst: update CONTRIBUTING instructions

Suggest using git-config instead of a flag on format-patch. While at it, use the more common "PATCH foo" subject prefix. Signed-off-by: Eric Engestrom --- dim.rst | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/dim.rst b/dim.rst index

[Intel-gfx] [PATCH maintainer-tools 2/3] dim: send 'not configured' error to stderr

This fixes `make check` when dim is not configured. Signed-off-by: Eric Engestrom --- dim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dim b/dim index 588e859..b373901 100755 --- a/dim +++ b/dim @@ -197,7 +197,7 @@ export __dim_running=1 if [

Re: [Intel-gfx] [PATCH] drm/i915: Only report a wakeup if the waiter was truly asleep

Hi Chris, [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on next-20170405] [cannot apply to v4.11-rc5] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Chris-Wilson

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/1] drm/i915: Suspend GuC prior to GPU Reset during GEM suspend

== Series Details == Series: series starting with [v2,1/1] drm/i915: Suspend GuC prior to GPU Reset during GEM suspend URL : https://patchwork.freedesktop.org/series/22512/ State : success == Summary == Series 22512v1 Series without cover letter

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable atomic for VLV/CHV

On Tue, Apr 04, 2017 at 05:34:17PM -, Patchwork wrote: > == Series Details == > > Series: drm/i915: Enable atomic for VLV/CHV > URL : https://patchwork.freedesktop.org/series/20634/ > State : success > > == Summary == > > Series 20634v1 drm/i915: Enable atomic for VLV/CHV >

Re: [Intel-gfx] [PATCH] drm/atomic: Add connector atomic_check function.

Op 05-04-17 om 12:06 schreef Daniel Vetter: > On Wed, Apr 05, 2017 at 10:41:24AM +0200, Maarten Lankhorst wrote: >> The connector atomic check function may be called multiple times, >> or not at all. It's mostly useful for implementing properties but if you >> call check_modeset twice it can be

[Intel-gfx] [PATCH v2 1/1] drm/i915: Suspend GuC prior to GPU Reset during GEM suspend

i915 is currently doing Full GPU reset at the end of suspend followed by GuC suspend. This reset bypasses the GuC. We need to tell the GuC to suspend before we do a direct intel_gpu_reset, Otherwise the gpu state will no longer match the GuC's expectations and its suspend will not be successful.

Re: [Intel-gfx] [PATCH 02/18] drm/i915: introduce drm_i915_gem_object page_size members

On 04/05, Chris Wilson wrote: > On Wed, Apr 05, 2017 at 08:49:17AM +0200, Daniel Vetter wrote: > > On Tue, Apr 04, 2017 at 11:11:12PM +0100, Matthew Auld wrote: > > > Signed-off-by: Matthew Auld > > > --- > > > drivers/gpu/drm/i915/i915_gem.c| 5 + > > >

[Intel-gfx] [PATCH i-g-t] tests/meta_test: Add a meta test for sanity checks of CI systems

The intention of this test is use it to test that the CI system that runs IGT is collecting the results correctly. For: VIZ-10281 Signed-off-by: Marta Lofstedt --- tests/Makefile.sources | 1 + tests/intel-ci/meta.testlist | 7 +++ tests/meta_test.c

Re: [Intel-gfx] [PATCH] drm/atomic: Add connector atomic_check function.

On Wed, Apr 05, 2017 at 10:41:24AM +0200, Maarten Lankhorst wrote: > The connector atomic check function may be called multiple times, > or not at all. It's mostly useful for implementing properties but if you > call check_modeset twice it can be used for other modeset related checks > as well. >

Re: [Intel-gfx] [PATCH i-g-t v2] tests/kms_atomic_allow_modeset: Add DRM_MODE_ATOMIC_ALLOW_MODESET test

On Tue, 2017-04-04 at 14:28 +0200, Maarten Lankhorst wrote: > Hey, > > Op 04-04-17 om 13:59 schreef Mika Kahola: > > > > When doing a full atomic modeset, kernel should fail if the flag > > DRM_MODE_ATOMIC_ALLOW_MODESET is not set. Let's add this test as > > part of > > Intel-GPU-Tools. The test

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/atomic: Add connector atomic_check function.

== Series Details == Series: drm/atomic: Add connector atomic_check function. URL : https://patchwork.freedesktop.org/series/22507/ State : success == Summary == Series 22507v1 drm/atomic: Add connector atomic_check function.

Re: [Intel-gfx] [PATCH 1/1] drm/i915: Suspend GuC during GEM Suspend prior to GPU Reset

On 4/5/2017 2:30 PM, Chris Wilson wrote: On Wed, Apr 05, 2017 at 11:04:34AM +0530, Sagar Arun Kamble wrote: During S3/S4 suspend, i915 sends HOST2GUC with ENTER_S_STATE action for suspending GuC. GuC stops scheduling at this point. i915 is currently doing explicit GPU reset during suspend

Re: [Intel-gfx] [dim PATCH 4/4] dim: run executables in $PATH named dim-subcommand as dim subcommands

On Wed, Apr 05, 2017 at 10:28:06AM +0300, Jani Nikula wrote: > On Tue, 04 Apr 2017, Daniel Vetter wrote: > > On Tue, Apr 04, 2017 at 04:59:02PM +0300, Jani Nikula wrote: > >> Similar to git. Don't allow override of internal commands though. > > > > git did this, and then went to

Re: [Intel-gfx] [PATCH] drm/i915/guc: Use GUC prefix for CORE_FAMILY definitions

On Tue, Apr 04, 2017 at 02:52:06PM +0100, Tvrtko Ursulin wrote: > > On 04/04/2017 14:38, Michal Wajdeczko wrote: > >Almost all other GuC fw definitions are using GUC|guc prefix. > >While around, in get_core_family() change explicit WARN into MISSING_CASE > >as it looks more appropriate, since GuC

Re: [Intel-gfx] [PATCH] drm/atomic: Acquire connection_mutex lock in drm_helper_probe_single_connector_modes, v3.

On Wed, Apr 05, 2017 at 10:11:18AM +0200, Maarten Lankhorst wrote: > mode_valid() called from drm_helper_probe_single_connector_modes() > may need to look at connector->state because what a valid mode is may > depend on connector properties being set. For example some HDMI modes > might be

Re: [Intel-gfx] [PATCH 1/1] drm/i915: Suspend GuC during GEM Suspend prior to GPU Reset

On Wed, Apr 05, 2017 at 11:04:34AM +0530, Sagar Arun Kamble wrote: > During S3/S4 suspend, i915 sends HOST2GUC with ENTER_S_STATE action > for suspending GuC. GuC stops scheduling at this point. i915 is > currently doing explicit GPU reset during suspend ensuring GEM is idle. > Suspend GuC prior

Re: [Intel-gfx] [maintainer-tools PATCH] dim: Add examples section to dim.rst

On Mon, Apr 03, 2017 at 01:42:18PM -0400, Sean Paul wrote: > Along with a recipe for creating a topic branch and sending a pull > request from it. > > Signed-off-by: Sean Paul > --- > dim.rst | 50 ++ > 1 file changed, 50

Re: [Intel-gfx] [RFC PATCH 00/18] drm/i915: initial support for huge gtt pages V2

On Tue, Apr 04, 2017 at 11:11:10PM +0100, Matthew Auld wrote: > Same as before, folding in review comments. Notably we now hook in transparent > huge pages through by shmem, and *attempt* to deal with all the fun which that > brings. Again should be considered very much RFC. But where's the

Re: [Intel-gfx] [PATCH 02/18] drm/i915: introduce drm_i915_gem_object page_size members

On Wed, Apr 05, 2017 at 08:49:17AM +0200, Daniel Vetter wrote: > On Tue, Apr 04, 2017 at 11:11:12PM +0100, Matthew Auld wrote: > > Signed-off-by: Matthew Auld > > --- > > drivers/gpu/drm/i915/i915_gem.c| 5 + > > drivers/gpu/drm/i915/i915_gem_object.h | 3 +++

Re: [Intel-gfx] [PATCH 01/18] drm/i915: add page_size_mask to dev_info

On Wed, Apr 05, 2017 at 09:19:49AM +0300, Joonas Lahtinen wrote: > On ti, 2017-04-04 at 23:11 +0100, Matthew Auld wrote: > > +++ b/drivers/gpu/drm/i915/i915_pci.c > > @@ -56,6 +56,10 @@ > >   .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 } > >   > >  /* Keep in gen based order, and

Re: [Intel-gfx] [PATCH 01/18] drm/i915: add page_size_mask to dev_info

On Tue, Apr 04, 2017 at 11:11:11PM +0100, Matthew Auld wrote: > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h > b/drivers/gpu/drm/i915/i915_gem_gtt.h > index fb15684c1d83..27b2b9e681db 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.h > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h > @@ -42,7

[Intel-gfx] [PATCH] drm/atomic: Add connector atomic_check function.

The connector atomic check function may be called multiple times, or not at all. It's mostly useful for implementing properties but if you call check_modeset twice it can be used for other modeset related checks as well. Signed-off-by: Maarten Lankhorst ---

Re: [Intel-gfx] [PATCH] drm/i915: Typo fix - 'pipe bpc' to 'pipe bpp'

On Wed, 05 Apr 2017, Jani Nikula wrote: > On Tue, 04 Apr 2017, Dhinakaran Pandiyan > wrote: >> Noticed this while I was looking at some debug output, >> [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output >>

[Intel-gfx] [PATCH] drm/atomic: Acquire connection_mutex lock in drm_helper_probe_single_connector_modes, v3.

mode_valid() called from drm_helper_probe_single_connector_modes() may need to look at connector->state because what a valid mode is may depend on connector properties being set. For example some HDMI modes might be rejected when a connector property forces the connector into DVI mode. Some

Re: [Intel-gfx] [PATCH] drm/i915: Typo fix - 'pipe bpc' to 'pipe bpp'

On Tue, 04 Apr 2017, Dhinakaran Pandiyan wrote: > Noticed this while I was looking at some debug output, > [drm:intel_hdmi_compute_config [i915]] picking bpc to 12 for HDMI output > [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 36 for HDMI > > I

Re: [Intel-gfx] [PATCH V4] drm/i915: Enhanced disable access to stolen memory as a guest

On Wed, 05 Apr 2017, Daniel Vetter wrote: > On Wed, Apr 05, 2017 at 10:08:26AM +0800, Xiong Zhang wrote: >> Stolen memory is in RMRR and has identity mapping in iommu, so >> gt could access stolen memory in host OS. While RMRR isn't supported >> by kvm, both EPT and guest iommu

Re: [Intel-gfx] [dim PATCH 4/4] dim: run executables in $PATH named dim-subcommand as dim subcommands

On Tue, 04 Apr 2017, Daniel Vetter wrote: > On Tue, Apr 04, 2017 at 04:59:02PM +0300, Jani Nikula wrote: >> Similar to git. Don't allow override of internal commands though. > > git did this, and then went to a slightly different version because > git doesn't complete to a space

Re: [Intel-gfx] linux-next: build warning after merge of the drm-misc tree

On 04/05/2017 02:41 AM, Stephen Rothwell wrote: > Hi all, > > After merging the drm-misc tree, today's linux-next build > (arm_multi_v7_defconfig) produced this warning: > > drivers/gpu/drm/bridge/synopsys/dw-hdmi.c:608:13: warning: > 'hdmi_bus_fmt_is_yuv420' defined but not used

Re: [Intel-gfx] [PATCH V4] drm/i915: Enhanced disable access to stolen memory as a guest

On Wed, Apr 05, 2017 at 10:08:26AM +0800, Xiong Zhang wrote: > Stolen memory is in RMRR and has identity mapping in iommu, so > gt could access stolen memory in host OS. While RMRR isn't supported > by kvm, both EPT and guest iommu domain lack of maaping for stolen memory, > so both vcpu and gt

Re: [Intel-gfx] [PATCH 02/18] drm/i915: introduce drm_i915_gem_object page_size members

On Tue, Apr 04, 2017 at 11:11:12PM +0100, Matthew Auld wrote: > Signed-off-by: Matthew Auld > --- > drivers/gpu/drm/i915/i915_gem.c| 5 + > drivers/gpu/drm/i915/i915_gem_object.h | 3 +++ > 2 files changed, 8 insertions(+) > > diff --git

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