[Intel-gfx] [PATCH] drm/i915: enable WaDisableDopClkGating for SKL GT4

This WA is required when decopled frequencies for slice and unslice are enabled. This disables DOP clock gating for SKL GT4. Cc: David Weinehall Signed-off-by: Praveen Paneri --- drivers/gpu/drm/i915/intel_pm.c | 6 ++ 1 file

[Intel-gfx] [PATCH] dma-buf/sync_file: Allow multiple sync_files to wrap a single dma-fence

Up until recently sync_file were create to export a single dma-fence to userspace, and so we could canabalise a bit insie dma-fence to mark whether or not we had enable polling for the sync_file itself. However, with the advent of syncobj, we do allow userspace to create multiple sync_files for a

Re: [Intel-gfx] [PATCH 5/8] drm/i915: Upscale scaler max scale for NV12

On Mon, 24 Jul 2017 09:57:46 +0530 Vidya Srinivas wrote: > From: Chandra Konduru > > This patch updates scaler max limit support for NV12 > > v2: Rebased (me) > > v3: Rebased (me) > > v4: Missed the Tested-by/Reviewed-by in the previous

[Intel-gfx] [PATCH v5] drm/i915/edp: Allow alternate fixed mode for eDP if available.

Some fixed resolution panels actually support more than one mode, with the only thing different being the refresh rate. Having this alternate mode available to us is desirable, because it allows us to test PSR on panels whose setup time at the preferred mode is too long. With this patch we allow

[Intel-gfx] [PATCH v6 i-g-t] igt/perf: add tests to verify create/destroy userspace configs

v2: Add tests regarding removing configs (Matthew) Add tests regarding adding/removing configs without permissions (Matthew) v3: Add some flex registers (Matthew) v4: memset oa_config to 0 (Lionel) Change error code for removing unexisting config EINVAL->ENOENT (Lionel) v5: Update

[Intel-gfx] [PATCH v8 6/6] drm/i915/perf: Implement I915_PERF_ADD/REMOVE_CONFIG interface

The motivation behind this new interface is expose at runtime the creation of new OA configs which can be used as part of the i915 perf open interface. This will enable the kernel to learn new configs which may be experimental, or otherwise not part of the core set currently available through the

[Intel-gfx] [PATCH v8 5/6] drm/i915: reorder NOA register definition to follow addresses

It makes things easier to read to implement whitelisting in the following patches. Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_reg.h | 212 1 file changed, 106 insertions(+), 106 deletions(-) diff --git

[Intel-gfx] [PATCH v8 4/6] drm/i915/perf: disable NOA logic when not used

We already do it on Haswell and the documentation says it saves power. Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_perf.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c

[Intel-gfx] [PATCH v8 3/6] drm/i915/perf: leave GDT_CHICKEN_BITS programming in configs

There will be a need for userspaces configurations to set this register. We can apply the same model inside the kernel for test configs. Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_oa_bdw.c| 2 ++ drivers/gpu/drm/i915/i915_oa_bxt.c| 1 +

[Intel-gfx] [PATCH v8 0/6] Add support for loadable OA configs

Hi, Here is a v8 with some more changes following Andrzej's comment on whitelisted registers. I've also added some documentation. Cheers, Lionel Landwerlin (6): drm/i915/perf: fix flex eu registers programming drm/i915/perf: prune OA configs drm/i915/perf: leave GDT_CHICKEN_BITS

[Intel-gfx] [PATCH v8 1/6] drm/i915/perf: fix flex eu registers programming

We were reserving fewer dwords in the ring than necessary. Indeed we're always writing all registers once, so discard the actual number of registers given by the user and just program the whitelisted ones once. Fixes: 19f81df2859e ("drm/i915/perf: Add OA unit support for Gen 8+") Reported-by:

Re: [Intel-gfx] [PATCH 5/8] drm: Nuke drm_atomic_helper_plane_set_property

On Tue, Jul 25, 2017 at 10:01:19AM +0200, Daniel Vetter wrote: > It's dead code, the core handles all this directly now. This also > allows us to unexport drm_atomic_helper_plane_set_property. > > Signed-off-by: Daniel Vetter > Cc: Liviu Dudau > Cc:

Re: [Intel-gfx] [PATCH igt 10/10] igt/gem_eio: i915.reset is no longer a boolean

On Fri, Jul 28, 2017 at 02:50:30PM +0100, Chris Wilson wrote: > Quoting Michał Winiarski (2017-07-28 14:36:46) > > On Fri, Jul 28, 2017 at 01:08:08PM +0100, Chris Wilson wrote: > > > Signed-off-by: Chris Wilson > > > --- > > > tests/gem_eio.c | 2 +- > > > 1 file

Re: [Intel-gfx] [PATCH igt 05/10] igt/drv_hangman: Skip if resets are disallowed

Quoting Michał Winiarski (2017-07-28 14:53:40) > On Fri, Jul 28, 2017 at 01:08:03PM +0100, Chris Wilson wrote: > > If we tell the machine to reset but they are disallowed, we will leave > > the system in a wedged state, preventing the majority of subsequent > > tests. > > --- > >

Re: [Intel-gfx] [PATCH igt 05/10] igt/drv_hangman: Skip if resets are disallowed

Quoting Michał Winiarski (2017-07-28 14:53:40) > On Fri, Jul 28, 2017 at 01:08:03PM +0100, Chris Wilson wrote: > > If we tell the machine to reset but they are disallowed, we will leave > > the system in a wedged state, preventing the majority of subsequent > > tests. > > --- > >

Re: [Intel-gfx] [PATCH igt 05/10] igt/drv_hangman: Skip if resets are disallowed

On Fri, Jul 28, 2017 at 01:08:03PM +0100, Chris Wilson wrote: > If we tell the machine to reset but they are disallowed, we will leave > the system in a wedged state, preventing the majority of subsequent > tests. > --- > tests/drv_hangman.c | 3 +++ > 1 file changed, 3 insertions(+) Missed

Re: [Intel-gfx] [PATCH igt 10/10] igt/gem_eio: i915.reset is no longer a boolean

Quoting Michał Winiarski (2017-07-28 14:36:46) > On Fri, Jul 28, 2017 at 01:08:08PM +0100, Chris Wilson wrote: > > Signed-off-by: Chris Wilson > > --- > > tests/gem_eio.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/tests/gem_eio.c

Re: [Intel-gfx] [PATCH 11/21] drm/i915: support 1G pages for the 48b PPGTT

Quoting Matthew Auld (2017-07-25 20:21:23) > Support inserting 1G gtt pages into the 48b PPGTT. > > v2: sanity check sg->length against page_size > > Signed-off-by: Matthew Auld > Cc: Joonas Lahtinen > Cc: Chris Wilson

Re: [Intel-gfx] [PATCH igt 10/10] igt/gem_eio: i915.reset is no longer a boolean

On Fri, Jul 28, 2017 at 01:08:08PM +0100, Chris Wilson wrote: > Signed-off-by: Chris Wilson > --- > tests/gem_eio.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/tests/gem_eio.c b/tests/gem_eio.c > index 3c826626..15120842 100644 > ---

Re: [Intel-gfx] [PATCH 01/21] mm/shmem: introduce shmem_file_setup_with_mnt

On Tue, Jul 25, 2017 at 08:21:13PM +0100, Matthew Auld wrote: > We are planning to use our own tmpfs mnt in i915 in place of the > shm_mnt, such that we can control the mount options, in particular > huge=, which we require to support huge-gtt-pages. So rather than roll > our own version of

[Intel-gfx] [PATCH] dim: Use mtime, not ctime

mtime is when the file contents last changed, ctime when attributes in the inode last changed. We want the former. For some reason ctime in my rr-cache is always very recent. Signed-off-by: Daniel Vetter --- dim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[Intel-gfx] [PATCH i-g-t] tests/kms_plane_multiple: Fix reference CRC

When grabbing reference CRC with igt_pipe_crc_get_crcs() the number of words in igt_crc_t structure was incorrectly collected. The fix here is to switch to igt_pipe_crc_collect_crc() function when collecting CRC for reference frame. The problem was caught by CI system and at least affects on HSW

Re: [Intel-gfx] [PATCH igt 09/10] igt/gem_userptr_blits: Errors from gup are permanent

On Fri, Jul 28, 2017 at 01:08:07PM +0100, Chris Wilson wrote: > After triggering an error (such as trying to use userptr on a GTT > mmaping), we store the EFAULT on the object permanently. So to test the > error, we must sacrifice the object and recreate the userptr handle. > We restrict the error

[Intel-gfx] [PATCH igt 03/10] igt/gem_ctx_switch: Exercise all engines at once

Just a small variant to apply a continuous context-switch load to all engines. --- tests/gem_ctx_switch.c | 80 ++ 1 file changed, 80 insertions(+) diff --git a/tests/gem_ctx_switch.c b/tests/gem_ctx_switch.c index b6ea71cf..df22efec 100644 ---

[Intel-gfx] [PATCH igt 09/10] igt/gem_userptr_blits: Errors from gup are permanent

After triggering an error (such as trying to use userptr on a GTT mmaping), we store the EFAULT on the object permanently. So to test the error, we must sacrifice the object and recreate the userptr handle. We restrict the error to just one of the overlapping userptr handles to check the object

[Intel-gfx] [PATCH igt 02/10] igt/gem_mmap_gtt: Simulate gdb inspecting a GTT mmap using ptrace()

gdb uses ptrace() to peek and poke bytes of the target's address space. The kernel must implement an vm_ops->access() handler or else gdb will be unable to inspect the pointer and report it as out-of-bounds. Worse than useless as it causes immediate suspicion of the valid GTT pointer.

[Intel-gfx] [PATCH igt 07/10] igt/gem_exec_suspend: Try to suspend with a pending GPU hang

Ensure that we can suspend the GPU even if it is currently busy in an indefinite loop, requiring us to declare the task hung. --- tests/gem_exec_suspend.c | 19 +++ 1 file changed, 19 insertions(+) diff --git a/tests/gem_exec_suspend.c b/tests/gem_exec_suspend.c index

[Intel-gfx] [PATCH igt 05/10] igt/drv_hangman: Skip if resets are disallowed

If we tell the machine to reset but they are disallowed, we will leave the system in a wedged state, preventing the majority of subsequent tests. --- tests/drv_hangman.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/drv_hangman.c b/tests/drv_hangman.c index 0551ec16..de57e128

[Intel-gfx] [PATCH igt 08/10] igt/gem_exec_fence: Exercise merging fences

Execute the same batch on each engine and check that the composite fence across all engines completes only after the batch is completed on every engine. Signed-off-by: Chris Wilson --- tests/gem_exec_fence.c | 120 + 1

[Intel-gfx] [PATCH igt 10/10] igt/gem_eio: i915.reset is no longer a boolean

Signed-off-by: Chris Wilson --- tests/gem_eio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/gem_eio.c b/tests/gem_eio.c index 3c826626..15120842 100644 --- a/tests/gem_eio.c +++ b/tests/gem_eio.c @@ -53,7 +53,7 @@ static bool

[Intel-gfx] [PATCH igt 04/10] igt/gem_exec_schedule: Exercise reordering with many priority levels

Apply a little more stress to the scheduler. --- lib/igt_rand.h| 6 +++ tests/gem_exec_schedule.c | 108 +- 2 files changed, 113 insertions(+), 1 deletion(-) diff --git a/lib/igt_rand.h b/lib/igt_rand.h index f664af41..c9cb3243 100644 ---

[Intel-gfx] [PATCH igt 01/10] tests/prime_rw: Add basic tests for reading/writing to a dmabuf

The idea is to implement read(dmabuf) and write(dambuf) so provide some tests. Signed-off-by: Chris Wilson --- tests/Makefile.sources | 1 + tests/prime_rw.c | 179 + 2 files changed, 180 insertions(+) create

[Intel-gfx] [PATCH igt 06/10] igt/gem_ringfill: Prime execbuf before measuring ring size

Make sure that our buffers are ready and loaded to reduce the initial stall. --- tests/gem_ringfill.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/tests/gem_ringfill.c b/tests/gem_ringfill.c index b52996a4..01cbd0a9 100644 --- a/tests/gem_ringfill.c +++

Re: [Intel-gfx] [PATCH 01/21] mm/shmem: introduce shmem_file_setup_with_mnt

Ping on the core MM folks. We'd need either an ack or nack on this one to proceed with the huge page work for i915. Regards, Joonas On ti, 2017-07-25 at 20:21 +0100, Matthew Auld wrote: > We are planning to use our own tmpfs mnt in i915 in place of the > shm_mnt, such that we can control the

[Intel-gfx] [CI] drm/i915/selftests: Retarget igt_render_engine_reset_fallback()

The purpose of the test was to check per-engine resets would fallback to the global reset when required, but first we actually need a test for a basic i915_handle_error()! Cc: Mika Kuoppala Cc: Michel Thierry Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH 3/4] lib/scatterlist: Introduce and export __sg_alloc_table_from_pages

Quoting Tvrtko Ursulin (2017-07-27 10:05:03) > From: Tvrtko Ursulin > > Drivers like i915 benefit from being able to control the maxium > size of the sg coallesced segment while building the scatter- > gather list. > > Introduce and export the

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Use __sg_alloc_table_from_pages for userptr allocations

Quoting Tvrtko Ursulin (2017-07-27 10:05:04) > From: Tvrtko Ursulin > > With the addition of __sg_alloc_table_from_pages we can control > the maximum coallescing size and eliminate a separate path for > allocating backing store here. > > Similar to 871dfbd67d4e

Re: [Intel-gfx] [PATCH 2/4] lib/scatterlist: Avoid potential scatterlist entry overflow

Quoting Tvrtko Ursulin (2017-07-27 10:05:02) > From: Tvrtko Ursulin > > Since the scatterlist length field is an unsigned int, make > sure that sg_alloc_table_from_pages does not overflow it while > coallescing pages to a single entry. > > v2: Drop reference to future

Re: [Intel-gfx] [PATCH] drm/i915: Include mbox details for pcode read/write failures

Quoting Daniel Vetter (2017-07-28 10:28:05) > On Fri, Jul 28, 2017 at 09:50:22AM +0100, Chris Wilson wrote: > > If we fail at punit communication, include both the mbox address and the > > value we tried to write so that we can identify the invalid sequence. > > > > Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH] drm/i915: Disable GPU resets for 915g (earliest gen3 desktop)

Quoting Chris Wilson (2017-07-27 17:24:20) > Quoting Daniel Vetter (2017-07-27 15:36:49) > > On Mon, Jul 24, 2017 at 11:14:13AM +0100, Chris Wilson wrote: > > > The CI farm reports that trying to write to the PCI config (GDRST: 0xc0) > > > results in an immediate and silent reboot on Grantsdale

Re: [Intel-gfx] [PATCH v2 4/4] drm/i915: Acquire PUNIT->PMIC bus for intel_uncore_forcewake_reset()

On Thu, Jul 06, 2017 at 09:24:50PM +0200, Hans de Goede wrote: > intel_uncore_forcewake_reset() does forcewake puts and gets as such > we need to make sure that no-one tries to access the PUNIT->PMIC bus > (on systems where this bus is shared) while it runs, otherwise bad > things happen. > >

Re: [Intel-gfx] [PATCH] drm/i915: Include mbox details for pcode read/write failures

On Fri, Jul 28, 2017 at 09:50:22AM +0100, Chris Wilson wrote: > If we fail at punit communication, include both the mbox address and the > value we tried to write so that we can identify the invalid sequence. > > Signed-off-by: Chris Wilson > Cc: Daniel Vetter

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Include mbox details for pcode read/write failures

== Series Details == Series: drm/i915: Include mbox details for pcode read/write failures URL : https://patchwork.freedesktop.org/series/28030/ State : success == Summary == Series 28030v1 drm/i915: Include mbox details for pcode read/write failures

[Intel-gfx] [PATCH] drm/i915: Include mbox details for pcode read/write failures

If we fail at punit communication, include both the mbox address and the value we tried to write so that we can identify the invalid sequence. Signed-off-by: Chris Wilson Cc: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 21

Re: [Intel-gfx] [PATCH v13 5/7] vfio: ABI for mdev display dma-buf operation

Hi, > +/** > + * VFIO_DEVICE_QUERY_GFX_PLANE - _IOW(VFIO_TYPE, VFIO_BASE + 14, > struct vfio_device_query_gfx_plane) > + * > + * Set the drm_plane_type and retrieve information about the gfx > plane. + * > + * Return: 0 on success, -errno on failure. I think this should be more verbose,

Re: [Intel-gfx] [PATCH 0/5] drm/atomic: Interruptible locks for everyone!

Op 27-07-17 om 17:30 schreef Daniel Vetter: > On Thu, Jul 27, 2017 at 03:45:11PM +0100, Emil Velikov wrote: >> Hi Maarten >> >> On 27 July 2017 at 13:58, Maarten Lankhorst >> wrote: >>> drm_atomic_commit could previous have always failed when waits failed, >>>