Re: [Intel-gfx] [PATCH 2/2] drm/i915/mst: Use MST sideband message transaction for dpms

On 2017-09-05 18:26, Dhinakaran Pandiyan wrote: > Use the POWER_DOWN_PHY and POWER_UP_PHY sideband message trasactions to > set power states for downstream sinks. Apart from giving us the ability > to set power state for individual sinks, this fixes the below test for > me > > $ xrandr --display

Re: [Intel-gfx] [PATCH 1/2] drm/dp/mst: Sideband message transaction to power up/down nodes

On 2017-09-05 18:26, Dhinakaran Pandiyan wrote: > The POWER_DOWN_PHY and POWER_UP_PHY sideband message transactions allow > the source to reqest any node in a mst path or a whole path to be > powered down or up. This allows drivers to target a specific sink in the > MST topology, an improvement

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod)

== Series Details == Series: drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) URL : https://patchwork.freedesktop.org/series/29909/ State : success == Summary == Test kms_sysfs_edid_timing: pass -> WARN (shard-hsw) fdo#100047 Test perf:

[Intel-gfx] ✗ Fi.CI.IGT: failure for Experimental Revert "drm/i915: Re-enable per-engine reset for Broxton"

== Series Details == Series: Experimental Revert "drm/i915: Re-enable per-engine reset for Broxton" URL : https://patchwork.freedesktop.org/series/29905/ State : failure == Summary == Test kms_busy: Subgroup basic-flip-C: pass -> SKIP (shard-hsw) Test

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/guc: Add GuC Load time to debugfs

== Series Details == Series: series starting with [1/2] drm/i915/guc: Add GuC Load time to debugfs URL : https://patchwork.freedesktop.org/series/29921/ State : failure == Summary == CHK include/config/kernel.release CHK include/generated/uapi/linux/version.h CHK

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write

== Series Details == Series: series starting with [1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write URL : https://patchwork.freedesktop.org/series/29920/ State : failure == Summary == CHK include/config/kernel.release CHK

[Intel-gfx] [PATCH 2/2] drm/i915/huc: Add HuC Load time to debugfs

This patch uses jiffies to calculate the huc load time and add it as a field to debugfs. This information can be useful for testing to know how much time huc takes to load. Cc: Sujaritha Sundaresan Cc: Oscar Mateo Lozano Cc: Michal

[Intel-gfx] [PATCH 1/2] drm/i915/guc: Add GuC Load time to debugfs

Calculate the time that GuC takes to load. This information could be very useful in determining if GuC is taking unreasonably long time to load in a certain platforms. v2: Calculate time before logs are collected. Move the guc_load_time variable as a part of intel_uc_fw struct. Store only final

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2] drm/dp/mst: Sideband message transaction to power up/down nodes (rev2)

== Series Details == Series: series starting with [v2] drm/dp/mst: Sideband message transaction to power up/down nodes (rev2) URL : https://patchwork.freedesktop.org/series/29853/ State : failure == Summary == Series 29853v2 series starting with [v2] drm/dp/mst: Sideband message transaction

[Intel-gfx] [PATCH 5/6] drm/i915: Transform WaDisableDynamicCreditSharing into a simple register write

GAMT_CHKN_BIT_REG does not live in the context image. Cc: Chris Wilson Cc: Mika Kuoppala Cc: Rodrigo Vivi Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++-- 1 file

[Intel-gfx] [PATCH 3/6] drm/i915: WaPushConstantDereferenceHoldDisable needs to modify a masked register

So do it correctly. Cc: Chris Wilson Cc: Mika Kuoppala Cc: Rodrigo Vivi Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- 1 file changed, 1 insertion(+), 1

[Intel-gfx] [PATCH 6/6] drm/i915: Transform WaDisablePooledEuLoadBalancingFix into a simple register write

FF_SLICE_CS_CHICKEN2 does not belong to the context image. Cc: Chris Wilson Cc: Mika Kuoppala Cc: Rodrigo Vivi Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++-- 1

[Intel-gfx] [PATCH 2/6] drm/i915: Transform WaDisableI2mCycleOnWRPort into a simple reg write

GAMT_CHKN_BIT_REG does not live in the context. Cc: Chris Wilson Cc: Mika Kuoppala Cc: Rodrigo Vivi Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/intel_engine_cs.c | 7 --- 1 file

[Intel-gfx] [PATCH 1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write

Afaict, GEN9_GAMT_ECO_REG_RW_IA does not live in the context, so writing it on every context creation is overkill (and wrong). v2: Missing end parenthesis Cc: Chris Wilson Cc: Mika Kuoppala Cc: Rodrigo Vivi

[Intel-gfx] [PATCH v2] drm/dp/mst: Sideband message transaction to power up/down nodes

The POWER_DOWN_PHY and POWER_UP_PHY sideband message transactions allow the source to reqest any node in a mst path or a whole path to be powered down or up. This allows drivers to target a specific sink in the MST topology, an improvement over just power managing the imediate downstream device.

[Intel-gfx] [PATCH 4/6] drm/i915: Transform WaDisableGafsUnitClkGating into a simple reg write

GEN7_UCGCTL4 does not live in the context. Cc: Chris Wilson Cc: Mika Kuoppala Cc: Rodrigo Vivi Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/intel_engine_cs.c | 9 ++--- 1 file

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: Kill GEN_RANGE in favor of INTEL_GEN.

== Series Details == Series: drm/i915: Kill GEN_RANGE in favor of INTEL_GEN. URL : https://patchwork.freedesktop.org/series/29903/ State : warning == Summary == Test kms_busy: Subgroup basic-modeset-C: pass -> SKIP (shard-hsw) Test kms_plane:

Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod)

On Wed, Sep 6, 2017 at 3:03 PM, Rodrigo Vivi wrote: > Wa for B-stepping only. > > A for a hang issue that requires throttling EU performace > to 12.5% to avoid back pressure to thread dispatch > > v2: Rebased. No change from v1. > > Signed-off-by: Rodrigo Vivi

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: Disable snooping (userptr, set-cache-level) on gen4

== Series Details == Series: drm/i915: Disable snooping (userptr, set-cache-level) on gen4 URL : https://patchwork.freedesktop.org/series/29901/ State : warning == Summary == Test kms_atomic_transition: Subgroup plane-use-after-nonblocking-unbind: fail ->

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Add NV12 as supported format for primary plane

On Wed, Sep 6, 2017 at 3:02 PM, Matt Roper wrote: > On Wed, Sep 06, 2017 at 02:49:07PM -0700, Kristian Høgsberg wrote: >> On Wed, Sep 6, 2017 at 1:17 PM, Matt Roper wrote: >> > On Wed, Sep 06, 2017 at 12:12:10PM -0700, Rodrigo Vivi wrote: >>

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod)

== Series Details == Series: drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) URL : https://patchwork.freedesktop.org/series/29909/ State : success == Summary == Series 29909v1 drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod)

[Intel-gfx] [PATCH] drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod)

Wa for B-stepping only. A for a hang issue that requires throttling EU performace to 12.5% to avoid back pressure to thread dispatch v2: Rebased. No change from v1. Signed-off-by: Rodrigo Vivi Reviewed-by: Oscar Mateo ---

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Add NV12 as supported format for primary plane

On Wed, Sep 06, 2017 at 02:49:07PM -0700, Kristian Høgsberg wrote: > On Wed, Sep 6, 2017 at 1:17 PM, Matt Roper wrote: > > On Wed, Sep 06, 2017 at 12:12:10PM -0700, Rodrigo Vivi wrote: > >> On Wed, Sep 06, 2017 at 09:36:27AM -0700, Matt Roper wrote: > >> > On Mon, Aug

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Transform WaInPlaceDecompressionHang to a simple reg write

== Series Details == Series: drm/i915: Transform WaInPlaceDecompressionHang to a simple reg write URL : https://patchwork.freedesktop.org/series/29906/ State : failure == Summary == CHK include/config/kernel.release CHK include/generated/uapi/linux/version.h CHK

Re: [Intel-gfx] [PATCH] drm/i915: Clear local engine-needs-reset bit if in progress elsewhere

Quoting Jeff McGee (2017-08-29 18:01:47) > On Tue, Aug 29, 2017 at 04:17:46PM +0100, Chris Wilson wrote: > > Quoting Jeff McGee (2017-08-29 16:04:17) > > > On Tue, Aug 29, 2017 at 10:07:18AM +0100, Chris Wilson wrote: > > > > Quoting Jeff McGee (2017-08-28 21:18:44) > > > > > On Mon, Aug 28, 2017

Re: [Intel-gfx] [PATCH 64/67] drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod)

On 04/06/2017 12:16 PM, Rodrigo Vivi wrote: Wa for B-stepping only. A for a hang issue that requires throttling EU performace to 12.5% to avoid back pressure to thread dispatch Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_reg.h| 1 +

Re: [Intel-gfx] [PATCH] drm/i915: Transform WaInPlaceDecompressionHang to a simple reg write

On 09/06/2017 02:43 PM, Chris Wilson wrote: Quoting Oscar Mateo (2017-09-06 22:27:47) On 09/06/2017 02:19 PM, Chris Wilson wrote: Quoting Oscar Mateo (2017-09-06 22:12:11) Afaict, GEN9_GAMT_ECO_REG_RW_IA does not live in the context, so writing it on every context creation is overkill (and

Re: [Intel-gfx] [GIT PULL] gvt fix for 4.14-rc1

On Wed, 2017-09-06 at 11:59 +0800, Zhenyu Wang wrote: > Hi, here's one regression fix for 4.14-rc1 which made gvt init failed > with latest linus master. thanks. pulled to drm-intel-next-fixes that will be sent to linus next soon. > > Thanks. > -- > The following changes since commit

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Add NV12 as supported format for primary plane

On Wed, Sep 6, 2017 at 1:17 PM, Matt Roper wrote: > On Wed, Sep 06, 2017 at 12:12:10PM -0700, Rodrigo Vivi wrote: >> On Wed, Sep 06, 2017 at 09:36:27AM -0700, Matt Roper wrote: >> > On Mon, Aug 28, 2017 at 04:22:20PM +0530, Vidya Srinivas wrote: >> > > From: Chandra

Re: [Intel-gfx] [PATCH] drm/i915: Transform WaInPlaceDecompressionHang to a simple reg write

Quoting Oscar Mateo (2017-09-06 22:27:47) > > > On 09/06/2017 02:19 PM, Chris Wilson wrote: > > Quoting Oscar Mateo (2017-09-06 22:12:11) > >> Afaict, GEN9_GAMT_ECO_REG_RW_IA does not live in the context, so writing > >> it on every context creation is overkill (and wrong). > >> > >> Cc: Mika

Re: [Intel-gfx] [PATCH] drm/i915: Transform WaInPlaceDecompressionHang to a simple reg write

On 09/06/2017 02:19 PM, Chris Wilson wrote: Quoting Oscar Mateo (2017-09-06 22:12:11) Afaict, GEN9_GAMT_ECO_REG_RW_IA does not live in the context, so writing it on every context creation is overkill (and wrong). Cc: Mika Kuoppala Cc: Rodrigo Vivi

Re: [Intel-gfx] [PATCH] drm/i915: Transform WaInPlaceDecompressionHang to a simple reg write

Quoting Oscar Mateo (2017-09-06 22:12:11) > Afaict, GEN9_GAMT_ECO_REG_RW_IA does not live in the context, so writing > it on every context creation is overkill (and wrong). > > Cc: Mika Kuoppala > Cc: Rodrigo Vivi > Signed-off-by: Oscar Mateo

Re: [Intel-gfx] [PATCH] drm/i915: Transform WaInPlaceDecompressionHang to a simple reg write

Hey Mika, Regarding this patch: is there a consensus on where is the most appropriate place to apply workarounds? My understanding is that per-context workarounds (WAS_SET_BIT, etc...) go in xxx_init_workarounds, while those that are needed only during initialization (I915_WRITE) go in

Re: [Intel-gfx] [PATCH] drm/i915: Lift has-pinned-pages to caller of ____i915_gem_object_get_pages

Quoting Matthew Auld (2017-09-06 21:45:38) > On 6 September 2017 at 14:52, Chris Wilson wrote: > > i915_gem_object_attach_phys() is trying to swap out its shmemfs pages > > for a new set of physically contiguous pages, but unfortunately triggers > > an assert inside

[Intel-gfx] [PATCH] drm/i915: Transform WaInPlaceDecompressionHang to a simple reg write

Afaict, GEN9_GAMT_ECO_REG_RW_IA does not live in the context, so writing it on every context creation is overkill (and wrong). Cc: Mika Kuoppala Cc: Rodrigo Vivi Signed-off-by: Oscar Mateo ---

Re: [Intel-gfx] [PATCH] drm/i915: Kill GEN_RANGE in favor of INTEL_GEN.

Quoting Vivi, Rodrigo (2017-09-06 21:13:07) > On Wed, 2017-09-06 at 20:57 +0100, Chris Wilson wrote: > > Quoting Rodrigo Vivi (2017-09-06 20:51:37) > > > Instead of limiting the range with this unusual GEN_RANGE > > > let's assume following platforms would use same scheme > > > unless stated

[Intel-gfx] ✓ Fi.CI.BAT: success for Experimental Revert "drm/i915: Re-enable per-engine reset for Broxton"

== Series Details == Series: Experimental Revert "drm/i915: Re-enable per-engine reset for Broxton" URL : https://patchwork.freedesktop.org/series/29905/ State : success == Summary == Series 29905v1 Experimental Revert "drm/i915: Re-enable per-engine reset for Broxton"

Re: [Intel-gfx] [PATCH] drm/i915: Lift has-pinned-pages to caller of ____i915_gem_object_get_pages

On 6 September 2017 at 14:52, Chris Wilson wrote: > i915_gem_object_attach_phys() is trying to swap out its shmemfs pages > for a new set of physically contiguous pages, but unfortunately triggers > an assert inside get-pages. > > Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH] drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk

On Tue, Sep 05, 2017 at 12:30:13PM -0700, Rodrigo Vivi wrote: > Skip compressing 1 segment at the end of the frame, > avoid a pixel count mismatch nuke event when last active > pixel and dummy pixel has same color for Odd Plane > Width / Height. > > For both platforms Gemini Lake and Cannon Lake.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Kill GEN_RANGE in favor of INTEL_GEN.

== Series Details == Series: drm/i915: Kill GEN_RANGE in favor of INTEL_GEN. URL : https://patchwork.freedesktop.org/series/29903/ State : success == Summary == Series 29903v1 drm/i915: Kill GEN_RANGE in favor of INTEL_GEN.

[Intel-gfx] [PATCH] Experimental Revert "drm/i915: Re-enable per-engine reset for Broxton"

This reverts commit 41e61020e821487489526e50b8e2e223342b7b93. --- drivers/gpu/drm/i915/i915_pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index f060536cc405..4672fc40de3c 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disable snooping (userptr, set-cache-level) on gen4

== Series Details == Series: drm/i915: Disable snooping (userptr, set-cache-level) on gen4 URL : https://patchwork.freedesktop.org/series/29901/ State : success == Summary == Series 29901v1 drm/i915: Disable snooping (userptr, set-cache-level) on gen4

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Add NV12 as supported format for primary plane

On Wed, Sep 06, 2017 at 12:12:10PM -0700, Rodrigo Vivi wrote: > On Wed, Sep 06, 2017 at 09:36:27AM -0700, Matt Roper wrote: > > On Mon, Aug 28, 2017 at 04:22:20PM +0530, Vidya Srinivas wrote: > > > From: Chandra Konduru > > > > > > This patch adds NV12 to list of

Re: [Intel-gfx] [PATCH] drm/i915: Kill GEN_RANGE in favor of INTEL_GEN.

On Wed, 2017-09-06 at 20:57 +0100, Chris Wilson wrote: > Quoting Rodrigo Vivi (2017-09-06 20:51:37) > > Instead of limiting the range with this unusual GEN_RANGE > > let's assume following platforms would use same scheme > > unless stated otherwise. > > No. This is uabi that should indeed be

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Allow the reg_read ioctl to read the RCS TIMESTAMP register

On Wed, Sep 06, 2017 at 12:32:15PM -0700, Rodrigo Vivi wrote: > On Wed, Sep 6, 2017 at 12:16 PM, Rodrigo Vivi wrote: > > On Wed, Sep 6, 2017 at 11:26 AM, Nanley Chery wrote: > >> On Tue, Sep 05, 2017 at 07:04:44PM +, Vivi, Rodrigo wrote: > >>>

Re: [Intel-gfx] Supporting Intel GPU tracing in gpuvis

On 09/06/2017 12:45 PM, Michael Sartain wrote: On Wed, Sep 6, 2017, at 03:09 AM, Chris Wilson wrote: We already have those tracepoint equivs and a script to generate a similar visualisation: intel-gpu-tools/scripts/trace.pl, but only looking at the scheduling issue from the gpu pov. But it's

Re: [Intel-gfx] [PATCH] drm/i915: Kill GEN_RANGE in favor of INTEL_GEN.

Quoting Rodrigo Vivi (2017-09-06 20:51:37) > Instead of limiting the range with this unusual GEN_RANGE > let's assume following platforms would use same scheme > unless stated otherwise. No. This is uabi that should indeed be checked before exposed and not assumed that unprivileged access to a

[Intel-gfx] [PATCH] drm/i915: Kill GEN_RANGE in favor of INTEL_GEN.

Instead of limiting the range with this unusual GEN_RANGE let's assume following platforms would use same scheme unless stated otherwise. In our regular flow of platform enabling we check for INTEL_GEN occurences, while GEN_RANGE had only this specific usage and consequently got forgotten,

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Allow the reg_read ioctl to read the RCS TIMESTAMP register

On Wed, Sep 6, 2017 at 12:16 PM, Rodrigo Vivi wrote: > On Wed, Sep 6, 2017 at 11:26 AM, Nanley Chery wrote: >> On Tue, Sep 05, 2017 at 07:04:44PM +, Vivi, Rodrigo wrote: >>> On Tue, 2017-09-05 at 11:45 -0700, Nanley Chery wrote: >>> > From: Ben

[Intel-gfx] [CI] drm/i915: Disable snooping (userptr, set-cache-level) on gen4

The original gen4 has an issue where writes (both render and blt) into snoopable pages are lost. We've previously worked around this in userspace (ddx, igt) by simply not requesting snoopable buffers, but upon rediscovering this problem for a third time, make the kernel reject such requests with

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Allow the reg_read ioctl to read the RCS TIMESTAMP register

On Wed, Sep 6, 2017 at 11:26 AM, Nanley Chery wrote: > On Tue, Sep 05, 2017 at 07:04:44PM +, Vivi, Rodrigo wrote: >> On Tue, 2017-09-05 at 11:45 -0700, Nanley Chery wrote: >> > From: Ben Widawsky >> >> Do we have a signed-off by him? >>

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Add NV12 as supported format for primary plane

On Wed, Sep 06, 2017 at 09:36:27AM -0700, Matt Roper wrote: > On Mon, Aug 28, 2017 at 04:22:20PM +0530, Vidya Srinivas wrote: > > From: Chandra Konduru > > > > This patch adds NV12 to list of supported formats for > > primary plane > > > > v2: Rebased (Chandra

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Allow the reg_read ioctl to read the RCS TIMESTAMP register

On Tue, Sep 05, 2017 at 07:04:44PM +, Vivi, Rodrigo wrote: > On Tue, 2017-09-05 at 11:45 -0700, Nanley Chery wrote: > > From: Ben Widawsky > > Do we have a signed-off by him? > Maybe go with you as author and suggested-by Ben? > He's good with the second

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Disable MI_STORE_DATA_IMM for i915g/i915gm (rev2)

== Series Details == Series: drm/i915: Disable MI_STORE_DATA_IMM for i915g/i915gm (rev2) URL : https://patchwork.freedesktop.org/series/29890/ State : success == Summary == Test kms_flip: Subgroup plain-flip-fb-recreate: fail -> PASS (shard-hsw) fdo#102504

Re: [Intel-gfx] [PATCH 1/2] drm/dp/mst: Sideband message transaction to power up/down nodes

On Wed, 2017-09-06 at 11:40 -0400, Lyude Paul wrote: > On Tue, 2017-09-05 at 18:26 -0700, Dhinakaran Pandiyan wrote: > > The POWER_DOWN_PHY and POWER_UP_PHY sideband message transactions > > allow > > the source to reqest any node in a mst path or a whole path to be > > powered down or up. This

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Disable MI_STORE_DATA_IMM for i915g/i915gm

== Series Details == Series: drm/i915: Disable MI_STORE_DATA_IMM for i915g/i915gm URL : https://patchwork.freedesktop.org/series/29890/ State : success == Summary == Test kms_flip: Subgroup plain-flip-fb-recreate: fail -> PASS (shard-hsw) fdo#102504 Test

[Intel-gfx] ✗ Fi.CI.IGT: warning for lib: Disable MI_STORE_DATA_IMM for gen3 (i915g and i915gm)

== Series Details == Series: lib: Disable MI_STORE_DATA_IMM for gen3 (i915g and i915gm) URL : https://patchwork.freedesktop.org/series/29889/ State : warning == Summary == Test perf: Subgroup polling: fail -> PASS (shard-hsw) fdo#102252 +1 Test kms_flip:

[Intel-gfx] ✓ Fi.CI.IGT: success for tests: Add kms_atomic_interruptible test, v2.

== Series Details == Series: tests: Add kms_atomic_interruptible test, v2. URL : https://patchwork.freedesktop.org/series/29877/ State : success == Summary == Test perf: Subgroup blocking: fail -> PASS (shard-hsw) fdo#102252 Test kms_flip: Subgroup

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Add NV12 as supported format for primary plane

On Mon, Aug 28, 2017 at 04:22:20PM +0530, Vidya Srinivas wrote: > From: Chandra Konduru > > This patch adds NV12 to list of supported formats for > primary plane > > v2: Rebased (Chandra Konduru) > > v3: Rebased (me) > > v4: Review comments by Ville addressed >

Re: [Intel-gfx] [PATCH] drm/i915: Re-enable per-engine reset for Broxton

Quoting Michel Thierry (2017-09-06 16:25:06) > On 05/09/17 06:57, Chris Wilson wrote: > > Quoting Chris Wilson (2017-08-21 15:55:34) > >> Quoting Michel Thierry (2017-08-18 18:23:42) > >>> The corruption in CSB mmio reads we were seeing has been tracked down to > >>> incorrectly touching forcewake

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disable MI_STORE_DATA_IMM for i915g/i915gm (rev2)

== Series Details == Series: drm/i915: Disable MI_STORE_DATA_IMM for i915g/i915gm (rev2) URL : https://patchwork.freedesktop.org/series/29890/ State : success == Summary == Series 29890v2 drm/i915: Disable MI_STORE_DATA_IMM for i915g/i915gm

Re: [Intel-gfx] [PATCH 1/2] drm/dp/mst: Sideband message transaction to power up/down nodes

On Tue, 2017-09-05 at 18:26 -0700, Dhinakaran Pandiyan wrote: > The POWER_DOWN_PHY and POWER_UP_PHY sideband message transactions > allow > the source to reqest any node in a mst path or a whole path to be > powered down or up. This allows drivers to target a specific sink in > the > MST topology,

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] lib/scatterlist: Fix offset type in sg_alloc_table_from_pages (rev6)

== Series Details == Series: series starting with [1/5] lib/scatterlist: Fix offset type in sg_alloc_table_from_pages (rev6) URL : https://patchwork.freedesktop.org/series/28151/ State : failure == Summary == Series 28151v6 series starting with [1/5] lib/scatterlist: Fix offset type in

[Intel-gfx] [PATCH v2] drm/i915: Disable MI_STORE_DATA_IMM for i915g/i915gm

The early gen3 machines (i915g/Grantsdale and i915gm/Alviso) share a lot of characteristics in their MI/GTT blocks with gen2, and in particular can only use physical addresses in MI_STORE_DATA_IMM. This makes it incompatible with our usage, so include those two machines in the blacklist to prevent

Re: [Intel-gfx] [PATCH] drm/i915: Re-enable per-engine reset for Broxton

On 05/09/17 06:57, Chris Wilson wrote: Quoting Chris Wilson (2017-08-21 15:55:34) Quoting Michel Thierry (2017-08-18 18:23:42) The corruption in CSB mmio reads we were seeing has been tracked down to incorrectly touching forcewake of all domains, following an engine reset. It is still a

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Unify skylake plane update

On Tue, Aug 29, 2017 at 12:48:03PM +0300, Juha-Pekka Heikkila wrote: > Don't handle skylake primary plane separately as it is similar > plane as the others. > > Signed-off-by: Juha-Pekka Heikkila > --- > drivers/gpu/drm/i915/intel_display.c | 81 >

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disable MI_STORE_DATA_IMM for i915g/i915gm

== Series Details == Series: drm/i915: Disable MI_STORE_DATA_IMM for i915g/i915gm URL : https://patchwork.freedesktop.org/series/29890/ State : success == Summary == Series 29890v1 drm/i915: Disable MI_STORE_DATA_IMM for i915g/i915gm

Re: [Intel-gfx] [PATCH] drm/i915: Disable MI_STORE_DATA_IMM for i915g/i915gm

Quoting Ville Syrjälä (2017-09-06 16:00:49) > On Wed, Sep 06, 2017 at 03:40:08PM +0100, Chris Wilson wrote: > > The early gen3 machines (i915g/Grantsdale and i915gm/Alviso) share a lot > > of characteristics in their MI/GTT blocks with gen2, and in particular > > can only use physical addresses in

Re: [Intel-gfx] [PATCH] drm/i915: Disable MI_STORE_DATA_IMM for i915g/i915gm

On Wed, Sep 06, 2017 at 03:40:08PM +0100, Chris Wilson wrote: > The early gen3 machines (i915g/Grantsdale and i915gm/Alviso) share a lot > of characteristics in their MI/GTT blocks with gen2, and in particular > can only use physical addresses in MI_STORE_DATA_IMM. This makes it > incompatible

[Intel-gfx] ✓ Fi.CI.BAT: success for lib: Disable MI_STORE_DATA_IMM for gen3 (i915g and i915gm)

== Series Details == Series: lib: Disable MI_STORE_DATA_IMM for gen3 (i915g and i915gm) URL : https://patchwork.freedesktop.org/series/29889/ State : success == Summary == IGT patchset tested on top of latest successful build 918863f8e3e8f49235fd2e4a36e11f386c06c11c intel_display_poller: Fix

[Intel-gfx] [PATCH v3 5/5] tools/testing/scatterlist: Test new __sg_alloc_table_from_pages

From: Tvrtko Ursulin Exercise the new __sg_alloc_table_from_pages API (and through it also the old sg_alloc_table_from_pages), checking that the created table has the expected number of segments depending on the sequence of input pages and other conditions. v2: Move to

Re: [Intel-gfx] [PATCH] drm/i915: Disable MI_STORE_DATA_IMM for i915g/i915gm

Quoting Chris Wilson (2017-09-06 15:40:08) > The early gen3 machines (i915g/Grantsdale and i915gm/Alviso) share a lot > of characteristics in their MI/GTT blocks with gen2, and in particular > can only use physical addresses in MI_STORE_DATA_IMM. This makes it > incompatible with our usage, so

Re: [Intel-gfx] [PATCH igt] lib: Disable MI_STORE_DATA_IMM for gen3 (i915g and i915gm)

On Wed, Sep 06, 2017 at 03:36:15PM +0100, Chris Wilson wrote: > The early gen3 machines inherited the MI block and restrictions from > gen2, and may only use physical addresses in conjunction with > MI_STORE_DATA_IMM -- that makes it unusable for us from userspace, where > we can only use virtual

[Intel-gfx] [PATCH] drm/i915: Disable MI_STORE_DATA_IMM for i915g/i915gm

The early gen3 machines (i915g/Grantsdale and i915gm/Alviso) share a lot of characteristics in their MI/GTT blocks with gen2, and in particular can only use physical addresses in MI_STORE_DATA_IMM. This makes it incompatible with our usage, so include those two machines in the blacklist to prevent

[Intel-gfx] [PATCH igt] lib: Disable MI_STORE_DATA_IMM for gen3 (i915g and i915gm)

The early gen3 machines inherited the MI block and restrictions from gen2, and may only use physical addresses in conjunction with MI_STORE_DATA_IMM -- that makes it unusable for us from userspace, where we can only use virtual offsets. Signed-off-by: Chris Wilson ---

Re: [Intel-gfx] [PATCH i-g-t] lib/sysfs: Fix fbcon rebind

On Wed, Sep 06, 2017 at 03:08:40PM +0100, Chris Wilson wrote: > Quoting ville.syrj...@linux.intel.com (2017-09-06 14:04:01) > > From: Ville Syrjälä > > > > "echo 1 > vtconN/bind" doesn't actually do anything. Looks like the only > > way to rebind fbcon is to unbind

[Intel-gfx] ✓ Fi.CI.IGT: success for lib/sysfs: Fix fbcon rebind

== Series Details == Series: lib/sysfs: Fix fbcon rebind URL : https://patchwork.freedesktop.org/series/29880/ State : success == Summary == Test kms_flip: Subgroup plain-flip-fb-recreate-interruptible: pass -> FAIL (shard-hsw) fdo#100368 Test perf:

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Lift has-pinned-pages to caller of ____i915_gem_object_get_pages

== Series Details == Series: drm/i915: Lift has-pinned-pages to caller of i915_gem_object_get_pages URL : https://patchwork.freedesktop.org/series/29885/ State : warning == Summary == Series 29885v1 drm/i915: Lift has-pinned-pages to caller of i915_gem_object_get_pages

Re: [Intel-gfx] [PATCH i-g-t] lib/sysfs: Fix fbcon rebind

Quoting ville.syrj...@linux.intel.com (2017-09-06 14:04:01) > From: Ville Syrjälä > > "echo 1 > vtconN/bind" doesn't actually do anything. Looks like the only > way to rebind fbcon is to unbind the current console. > > I suppose the failure to rebind might be a

Re: [Intel-gfx] [PATCH i-g-t 12/22] meson: basic build system support

On Tue, 05 Sep 2017, Daniel Vetter wrote: > Why? > > Because it's fast. And that's not even the main reason from my perspective! ;) Please find some comments inline. None of them are blockers. BR, Jani. > > Like really, really fast. > > Some data (from a snb laptop, so

[Intel-gfx] ✓ Fi.CI.BAT: success for tests: Add kms_atomic_interruptible test, v2.

== Series Details == Series: tests: Add kms_atomic_interruptible test, v2. URL : https://patchwork.freedesktop.org/series/29877/ State : success == Summary == IGT patchset tested on top of latest successful build 918863f8e3e8f49235fd2e4a36e11f386c06c11c intel_display_poller: Fix truncation

[Intel-gfx] [PATCH] drm/i915: Lift has-pinned-pages to caller of ____i915_gem_object_get_pages

i915_gem_object_attach_phys() is trying to swap out its shmemfs pages for a new set of physically contiguous pages, but unfortunately triggers an assert inside get-pages. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem.c | 6 -- 1 file changed, 4

[Intel-gfx] ✓ Fi.CI.BAT: success for lib/sysfs: Fix fbcon rebind

== Series Details == Series: lib/sysfs: Fix fbcon rebind URL : https://patchwork.freedesktop.org/series/29880/ State : success == Summary == IGT patchset tested on top of latest successful build 918863f8e3e8f49235fd2e4a36e11f386c06c11c intel_display_poller: Fix truncation of a test name.

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Re-enable GTT following a device reset (rev2)

Quoting Patchwork (2017-09-06 12:34:12) > == Series Details == > > Series: drm/i915: Re-enable GTT following a device reset (rev2) > URL : https://patchwork.freedesktop.org/series/29845/ > State : warning > > == Summary == > > Series 29845v2 drm/i915: Re-enable GTT following a device reset >

[Intel-gfx] [PATCH i-g-t] lib/sysfs: Fix fbcon rebind

From: Ville Syrjälä "echo 1 > vtconN/bind" doesn't actually do anything. Looks like the only way to rebind fbcon is to unbind the current console. I suppose the failure to rebind might be a kernel bug, but I can't be bothered to decode the vt.c spaghetti so let's

[Intel-gfx] ✗ Fi.CI.BAT: warning for tests: Add kms_atomic_interruptible test, v2.

== Series Details == Series: tests: Add kms_atomic_interruptible test, v2. URL : https://patchwork.freedesktop.org/series/29877/ State : warning == Summary == IGT patchset tested on top of latest successful build 918863f8e3e8f49235fd2e4a36e11f386c06c11c intel_display_poller: Fix truncation

Re: [Intel-gfx] [PATCH v2] drm/i915: Re-enable GTT following a device reset

Quoting Ville Syrjälä (2017-09-06 13:13:05) > On Wed, Sep 06, 2017 at 12:14:05PM +0100, Chris Wilson wrote: > > Ville Syrjälä spotted that PGETBL_CTL was losing its enable bit upon a > > reset. That was causing the display to show garbage on his 945gm. On my > > i915gm the effect was far more

Re: [Intel-gfx] [PATCH v2 5/5] tools/testing/scatterlist: Test new __sg_alloc_table_from_pages

Quoting Tvrtko Ursulin (2017-09-06 13:10:57) > > On 06/09/2017 11:48, Chris Wilson wrote: > > All ascending. Interesting challenge for 3,2,1,0; it can be coalesced, > > we just don't. I wonder if we are missing some like that. But for the > > Hm, how do you think descending pages could be

[Intel-gfx] [PATCH i-g-t] tests: Add kms_atomic_interruptible test, v2.

This tests the various parts of atomic that I want to make interruptible. Running with --debug shows the stats from __igt_sigiter_continue, which can be used to make sure that we don't fall over. The default igt kms helpers use drmIoctl, which is not intercepted by igt_while_interruptible. Only

Re: [Intel-gfx] [PATCH v2] drm/i915: Re-enable GTT following a device reset

On Wed, Sep 06, 2017 at 12:14:05PM +0100, Chris Wilson wrote: > Ville Syrjälä spotted that PGETBL_CTL was losing its enable bit upon a > reset. That was causing the display to show garbage on his 945gm. On my > i915gm the effect was far more severe; re-enabling the display following > the reset

Re: [Intel-gfx] [PATCH v2] drm/i915: Re-enable GTT following a device reset

On Wed, Sep 06, 2017 at 12:14:05PM +0100, Chris Wilson wrote: > Ville Syrjälä spotted that PGETBL_CTL was losing its enable bit upon a > reset. That was causing the display to show garbage on his 945gm. On my > i915gm the effect was far more severe; re-enabling the display following > the reset

Re: [Intel-gfx] [PATCH v2 5/5] tools/testing/scatterlist: Test new __sg_alloc_table_from_pages

On 06/09/2017 11:48, Chris Wilson wrote: Quoting Tvrtko Ursulin (2017-09-05 11:24:03) From: Tvrtko Ursulin Exercise the new __sg_alloc_table_from_pages API (and through it also the old sg_alloc_table_from_pages), checking that the created table has the expected

Re: [Intel-gfx] [PATCH i-g-t 07/22] lib: clean up header includes

Quoting Daniel Vetter (2017-09-05 13:36:09) > diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c > index f2a94b5572ea..a2061ff6138e 100644 > --- a/lib/igt_dummyload.c > +++ b/lib/igt_dummyload.c > @@ -22,11 +22,18 @@ > * > */ > > -#include "igt.h" > -#include "igt_dummyload.h" >

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Re-enable GTT following a device reset (rev2)

== Series Details == Series: drm/i915: Re-enable GTT following a device reset (rev2) URL : https://patchwork.freedesktop.org/series/29845/ State : warning == Summary == Series 29845v2 drm/i915: Re-enable GTT following a device reset

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Move device_info.has_snoop into the static tables

== Series Details == Series: drm/i915: Move device_info.has_snoop into the static tables URL : https://patchwork.freedesktop.org/series/29870/ State : warning == Summary == Series 29870v1 drm/i915: Move device_info.has_snoop into the static tables

[Intel-gfx] [PATCH v2] drm/i915: Re-enable GTT following a device reset

Ville Syrjälä spotted that PGETBL_CTL was losing its enable bit upon a reset. That was causing the display to show garbage on his 945gm. On my i915gm the effect was far more severe; re-enabling the display following the reset without PGETBL_CTL being enabled lead to an immediate hard hang. We do

[Intel-gfx] [CI] drm/i915: Move device_info.has_snoop into the static tables

Currently we define any !llc machine as using snoop instead. However, some platforms run into trouble using snoop that we would like to disable, and to do so easily we want to be able to use the static device_info tables. v2: Leave the old snoop = !llc as a warning for the time being to check

Re: [Intel-gfx] [PATCH v2 5/5] tools/testing/scatterlist: Test new __sg_alloc_table_from_pages

Quoting Tvrtko Ursulin (2017-09-05 11:24:03) > From: Tvrtko Ursulin > > Exercise the new __sg_alloc_table_from_pages API (and through > it also the old sg_alloc_table_from_pages), checking that the > created table has the expected number of segments depending on > the

Re: [Intel-gfx] [PATCH] drm/i915/dsi: Silence atomic update failure with DSI panel

On Tue, 2017-09-05 at 18:11 +0200, Daniel Vetter wrote: > On Tue, Sep 05, 2017 at 04:35:04PM +0300, Mika Kahola wrote: > > > > It appears that we cannot trust scanline counters when MIPI/DSI > > display is > > connected. In CI system this appears as flickering errors that > > randomly > > appear

[Intel-gfx] ✓ Fi.CI.IGT: success for RFC: meson build system support (rev6)

== Series Details == Series: RFC: meson build system support (rev6) URL : https://patchwork.freedesktop.org/series/29823/ State : success == Summary == Test kms_busy: Subgroup extended-modeset-hang-newfb-with-reset-render-C: pass -> DMESG-WARN (shard-hsw)

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