[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/cnl: Fix aux selection for WA 1178

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: Fix aux selection for WA 1178
URL   : https://patchwork.freedesktop.org/series/36997/
State : warning

== Summary ==

Test kms_flip:
Subgroup flip-vs-expired-vblank-interruptible:
fail   -> PASS   (shard-hsw) fdo#102887
Subgroup vblank-vs-dpms-suspend-interruptible:
pass   -> SKIP   (shard-snb)
Subgroup flip-vs-blocking-wf-vblank:
pass   -> FAIL   (shard-hsw) fdo#100368
Subgroup 2x-plain-flip-fb-recreate:
fail   -> PASS   (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-indfb-draw-mmap-gtt:
pass   -> FAIL   (shard-apl) fdo#101623 +1
Test perf:
Subgroup buffer-fill:
pass   -> FAIL   (shard-apl) fdo#103755
Test drv_suspend:
Subgroup fence-restore-untiled:
skip   -> PASS   (shard-snb) fdo#102365

fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365

shard-apltotal:2753 pass:1714 dwarn:1   dfail:0   fail:24  skip:1013 
time:13971s
shard-hswtotal:2753 pass:1725 dwarn:1   dfail:0   fail:11  skip:1015 
time:15388s
shard-snbtotal:2753 pass:1317 dwarn:1   dfail:0   fail:11  skip:1424 
time:7829s
Blacklisted hosts:
shard-kbltotal:2753 pass:1839 dwarn:3   dfail:0   fail:24  skip:887 
time:11031s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7760/shards.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/execlists: Inhibit context save/restore for the fake preempt context (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/execlists: Inhibit context save/restore for the fake preempt 
context (rev2)
URL   : https://patchwork.freedesktop.org/series/36984/
State : warning

== Summary ==

Test perf:
Subgroup oa-exponents:
pass   -> FAIL   (shard-apl) fdo#102254
Subgroup buffer-fill:
pass   -> FAIL   (shard-apl) fdo#103755
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
pass   -> FAIL   (shard-snb) fdo#101623 +1
Subgroup fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt:
pass   -> DMESG-FAIL (shard-apl) fdo#103167
Test drv_suspend:
Subgroup fence-restore-untiled:
skip   -> PASS   (shard-snb) fdo#102365
Test kms_flip:
Subgroup flip-vs-expired-vblank-interruptible:
fail   -> PASS   (shard-hsw) fdo#102887
Subgroup vblank-vs-dpms-suspend-interruptible:
pass   -> SKIP   (shard-snb)
Test kms_cursor_legacy:
Subgroup flip-vs-cursor-atomic:
pass   -> FAIL   (shard-hsw) fdo#102670

fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670

shard-apltotal:2753 pass:1713 dwarn:1   dfail:1   fail:24  skip:1013 
time:14181s
shard-hswtotal:2753 pass:1724 dwarn:1   dfail:0   fail:12  skip:1015 
time:15423s
shard-snbtotal:2753 pass:1316 dwarn:1   dfail:0   fail:12  skip:1424 
time:7787s
Blacklisted hosts:
shard-kbltotal:2753 pass:1829 dwarn:9   dfail:0   fail:26  skip:889 
time:11020s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7759/shards.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Move LRC register offsets to a header file (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Move LRC register offsets to a header file (rev4)
URL   : https://patchwork.freedesktop.org/series/36930/
State : success

== Summary ==

Test kms_flip:
Subgroup flip-vs-expired-vblank-interruptible:
fail   -> PASS   (shard-hsw) fdo#102887
Subgroup vblank-vs-modeset-suspend:
pass   -> FAIL   (shard-snb) fdo#102365 +1
Subgroup 2x-plain-flip-fb-recreate:
fail   -> PASS   (shard-hsw)
Subgroup plain-flip-fb-recreate-interruptible:
pass   -> FAIL   (shard-hsw) fdo#100368
Test kms_cursor_crc:
Subgroup cursor-256x256-suspend:
pass   -> INCOMPLETE (shard-hsw) fdo#103375
Subgroup cursor-128x128-suspend:
pass   -> INCOMPLETE (shard-hsw) fdo#103540
Test perf:
Subgroup oa-exponents:
pass   -> FAIL   (shard-apl) fdo#102254
Subgroup buffer-fill:
pass   -> FAIL   (shard-apl) fdo#103755
Subgroup blocking:
pass   -> FAIL   (shard-hsw) fdo#102252
Test kms_sysfs_edid_timing:
warn   -> PASS   (shard-apl) fdo#100047

fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047

shard-apltotal:2753 pass:1715 dwarn:1   dfail:0   fail:24  skip:1013 
time:14028s
shard-hswtotal:2639 pass:1655 dwarn:1   dfail:0   fail:12  skip:968 
time:14280s
shard-snbtotal:2753 pass:1318 dwarn:1   dfail:0   fail:11  skip:1423 
time:7905s
Blacklisted hosts:
shard-kbltotal:2735 pass:1817 dwarn:4   dfail:1   fail:23  skip:889 
time:10759s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7757/shards.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/6] drm/i915/guc: Grab RPM wakelock while disabling GuC interrupts

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/6] drm/i915/guc: Grab RPM wakelock while 
disabling GuC interrupts
URL   : https://patchwork.freedesktop.org/series/37011/
State : success

== Summary ==

Series 37011v1 series starting with [v3,1/6] drm/i915/guc: Grab RPM wakelock 
while disabling GuC interrupts
https://patchwork.freedesktop.org/api/1.0/series/37011/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> DMESG-FAIL (fi-elk-e7500) fdo#103989 +2
Test kms_force_connector_basic:
Subgroup prune-stale-modes:
skip   -> PASS   (fi-ivb-3520m)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-snb-2520m) fdo#103713
pass   -> INCOMPLETE (fi-bdw-5557u) fdo#104162

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104162 https://bugs.freedesktop.org/show_bug.cgi?id=104162

fi-bdw-5557u total:245  pass:227  dwarn:0   dfail:0   fail:0   skip:17 
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:429s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:373s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:490s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:281s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:491s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:466s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:452s
fi-elk-e7500 total:224  pass:168  dwarn:9   dfail:1   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:284s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:509s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:391s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:398s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:417s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:461s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:415s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:461s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:498s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:453s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:501s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:430s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:512s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:526s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:485s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:473s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:416s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:431s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:516s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:397s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:565s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:474s
fi-pnv-d510 failed to collect. IGT log at Patchwork_7765/fi-pnv-d510/igt.log

f9207df88e2a2a5803e1ddee7738c1a1aa2fcb74 drm-tip: 2018y-01m-23d-23h-25m-55s UTC 
integration manifest
b6c18893698e Revert "drm/i915/guc: Keep GuC log disabled by default"
a4fb4792fbd2 drm/i915/guc: Fix comments style in intel_guc_log.c
a0cb15d86c6f drm/i915/guc: Update name and prototype of i915_guc_log_control
29d907ffd97c drm/i915/guc: Fix lockdep due to log relay channel handling under 
struct_mutex
92c7090822b3 drm/i915/guc: Enable interrupts before resuming GuC during runtime 
resume
045185e800e7 drm/i915/guc: Grab RPM wakelock while disabling GuC interrupts

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7765/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915: Use enum plane_id for frontbuffer tracking

[Pandiyan, Dhinakaran]

On Tue, 2018-01-23 at 20:33 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Replace the ad-hoc plane indexing scheme used by the frontbuffer
> tracking with enum plane_id.
> 
> The old video overlay not being part of the plane_id namespace
> will just be given the high bit.

I'm curious why the bit corresponding to PLANE_SPRITE0 is not re-used
for the overlay. From a cursory read seems like platforms with overlays
and sprites are mutually exclusive.

Related question, how different is this overlay from the sprite planes?


> 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  | 11 +++
>  drivers/gpu/drm/i915/intel_display.c |  4 ++--
>  drivers/gpu/drm/i915/intel_fbc.c |  2 +-
>  drivers/gpu/drm/i915/intel_sprite.c  |  4 +++-
>  4 files changed, 9 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8333692dac5a..bd545b1c9546 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2404,16 +2404,11 @@ enum hdmi_force_audio {
>   *
>   * We have one bit per pipe and per scanout plane type.
>   */
> -#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
>  #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
> -#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
> - (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
> -#define INTEL_FRONTBUFFER_CURSOR(pipe) \
> - (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe
> -#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
> - (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe
> +#define INTEL_FRONTBUFFER(pipe, plane_id) \
> + (1 << ((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
>  #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
> - (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + 
> (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe
> + (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + 
> INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
>  #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
>   (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index d585ce4c8732..3cc35add362f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13168,7 +13168,7 @@ intel_primary_plane_create(struct drm_i915_private 
> *dev_priv, enum pipe pipe)
>   else
>   primary->i9xx_plane = (enum i9xx_plane_id) pipe;
>   primary->id = PLANE_PRIMARY;
> - primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
> + primary->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, primary->id);
>   primary->check_plane = intel_check_primary_plane;
>  
>   if (INTEL_GEN(dev_priv) >= 9) {
> @@ -13289,7 +13289,7 @@ intel_cursor_plane_create(struct drm_i915_private 
> *dev_priv,
>   cursor->pipe = pipe;
>   cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
>   cursor->id = PLANE_CURSOR;
> - cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
> + cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
>  
>   if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
>   cursor->update_plane = i845_update_cursor;
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c 
> b/drivers/gpu/drm/i915/intel_fbc.c
> index 9dc2b8b5f2db..a8a8a80497a8 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -1373,7 +1373,7 @@ void intel_fbc_init(struct drm_i915_private *dev_priv)
>  
>   for_each_pipe(dev_priv, pipe) {
>   fbc->possible_framebuffer_bits |=
> - INTEL_FRONTBUFFER_PRIMARY(pipe);
> + INTEL_FRONTBUFFER(pipe, PLANE_PRIMARY);
>  
>   if (fbc_on_pipe_a_only(dev_priv))
>   break;
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
> b/drivers/gpu/drm/i915/intel_sprite.c
> index a92c748ca8ab..18ef0392362e 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -345,6 +345,8 @@ skl_plane_get_hw_state(struct intel_plane *plane)
>   return ret;
>  }
>  
> +
> +
>  static void
>  chv_update_csc(struct intel_plane *plane, uint32_t format)
>  {
> @@ -1427,7 +1429,7 @@ intel_sprite_plane_create(struct drm_i915_private 
> *dev_priv,
>   intel_plane->pipe = pipe;
>   intel_plane->i9xx_plane = plane;
>   intel_plane->id = PLANE_SPRITE0 + plane;
> - intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
> + intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, intel_plane->id);
>   intel_plane->check_plane = intel_check_sprite_plane;
>  
>   possible_crtcs = (1 << pipe);
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 4/6] drm/i915/guc: Update name and prototype of i915_guc_log_control

[Sagar Arun Kamble]

i915_guc_log_control is GuC interface and GuC APIs that are not user
facing should be named with "intel_guc" prefix hence we change name to
intel_guc_log_control. Also changed the parameter to intel_guc struct.

Suggested-by: Michal Wajdeczko 
Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_debugfs.c  | 5 +++--
 drivers/gpu/drm/i915/intel_guc_log.c | 4 ++--
 drivers/gpu/drm/i915/intel_guc_log.h | 2 +-
 3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index b45be0d..c10a9e8 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2467,14 +2467,15 @@ static int i915_guc_log_control_get(void *data, u64 
*val)
 static int i915_guc_log_control_set(void *data, u64 val)
 {
struct drm_i915_private *dev_priv = data;
+   struct intel_guc *guc = _priv->guc;
 
if (!HAS_GUC(dev_priv))
return -ENODEV;
 
-   if (!dev_priv->guc.log.vma)
+   if (!guc->log.vma)
return -EINVAL;
 
-   return i915_guc_log_control(dev_priv, val);
+   return intel_guc_log_control(guc, val);
 }
 
 DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 35de889..27eb545 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -637,9 +637,9 @@ void intel_guc_log_destroy(struct intel_guc *guc)
i915_vma_unpin_and_release(>log.vma);
 }
 
-int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
+int intel_guc_log_control(struct intel_guc *guc, u64 control_val)
 {
-   struct intel_guc *guc = _priv->guc;
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
bool enable_logging = control_val > 0;
u32 verbosity;
int ret;
diff --git a/drivers/gpu/drm/i915/intel_guc_log.h 
b/drivers/gpu/drm/i915/intel_guc_log.h
index c638b9d..dab0e94 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.h
+++ b/drivers/gpu/drm/i915/intel_guc_log.h
@@ -64,7 +64,7 @@ struct intel_guc_log {
 void intel_guc_log_init_early(struct intel_guc *guc);
 int intel_guc_log_relay_create(struct intel_guc *guc);
 void intel_guc_log_relay_destroy(struct intel_guc *guc);
-int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
+int intel_guc_log_control(struct intel_guc *guc, u64 control_val);
 void i915_guc_log_register(struct drm_i915_private *dev_priv);
 void i915_guc_log_unregister(struct drm_i915_private *dev_priv);
 
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 6/6] [HAX] Revert "drm/i915/guc: Keep GuC log disabled by default"

[Sagar Arun Kamble]

Comment DRM_ERROR_RATELIMIT outputs as log capturer won't be
running.

This reverts commit bd724318b682587ad2f989ab8e0f7b3d4486ced5.
---
 drivers/gpu/drm/i915/i915_params.h   | 2 +-
 drivers/gpu/drm/i915/intel_guc_log.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 430f5f9..c963603 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -48,7 +48,7 @@
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
param(int, enable_guc, 0) \
-   param(int, guc_log_level, 0) \
+   param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
param(int, mmio_debug, 0) \
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 7c6c41b..a076d29 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -249,7 +249,7 @@ static bool guc_check_log_buf_overflow(struct intel_guc 
*guc,
/* buffer_full_cnt is a 4 bit counter */
guc->log.total_overflow_count[type] += 16;
}
-   DRM_ERROR_RATELIMITED("GuC log buffer overflow\n");
+   //DRM_ERROR_RATELIMITED("GuC log buffer overflow\n");
}
 
return overflow;
@@ -367,7 +367,7 @@ static void guc_read_update_log_buffer(struct intel_guc 
*guc)
 * Used rate limited to avoid deluge of messages, logs might be
 * getting consumed by User at a slow rate.
 */
-   DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n");
+   //DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n");
guc->log.capture_miss_count++;
}
 
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 3/6] drm/i915/guc: Fix lockdep due to log relay channel handling under struct_mutex

[Sagar Arun Kamble]

This patch fixes lockdep issue due to circular locking dependency of
struct_mutex, i_mutex_key, mmap_sem, relay_channels_mutex.
For GuC log relay channel we create debugfs file that requires i_mutex_key
lock and we are doing that under struct_mutex. So we introduced newer
dependency as:
>struct_mutex --> >s_type->i_mutex_key#3 --> >mmap_sem
However, there is dependency from mmap_sem to struct_mutex. Hence we
separate the relay create/destroy operation from under struct_mutex.

==
WARNING: possible circular locking dependency detected
4.15.0-rc6-CI-Patchwork_7614+ #1 Not tainted
--
debugfs_test/1388 is trying to acquire lock:
 (>struct_mutex){+.+.}, at: [] 
i915_mutex_lock_interruptible+0x47/0x130 [i915]

but task is already holding lock:
 (>mmap_sem){}, at: [<29a9c131>] __do_page_fault+0x106/0x560

which lock already depends on the new lock.

the existing dependency chain (in reverse order) is:

-> #3 (>mmap_sem){}:
   _copy_to_user+0x1e/0x70
   filldir+0x8c/0xf0
   dcache_readdir+0xeb/0x160
   iterate_dir+0xdc/0x140
   SyS_getdents+0xa0/0x130
   entry_SYSCALL_64_fastpath+0x1c/0x89

-> #2 (>s_type->i_mutex_key#3){}:
   start_creating+0x59/0x110
   __debugfs_create_file+0x2e/0xe0
   relay_create_buf_file+0x62/0x80
   relay_late_setup_files+0x84/0x250
   guc_log_late_setup+0x4f/0x110 [i915]
   i915_guc_log_register+0x32/0x40 [i915]
   i915_driver_load+0x7b6/0x1720 [i915]
   i915_pci_probe+0x2e/0x90 [i915]
   pci_device_probe+0x9c/0x120
   driver_probe_device+0x2a3/0x480
   __driver_attach+0xd9/0xe0
   bus_for_each_dev+0x57/0x90
   bus_add_driver+0x168/0x260
   driver_register+0x52/0xc0
   do_one_initcall+0x39/0x150
   do_init_module+0x56/0x1ef
   load_module+0x231c/0x2d70
   SyS_finit_module+0xa5/0xe0
   entry_SYSCALL_64_fastpath+0x1c/0x89

-> #1 (relay_channels_mutex){+.+.}:
   relay_open+0x12c/0x2b0
   intel_guc_log_runtime_create+0xab/0x230 [i915]
   intel_guc_init+0x81/0x120 [i915]
   intel_uc_init+0x29/0xa0 [i915]
   i915_gem_init+0x182/0x530 [i915]
   i915_driver_load+0xaa9/0x1720 [i915]
   i915_pci_probe+0x2e/0x90 [i915]
   pci_device_probe+0x9c/0x120
   driver_probe_device+0x2a3/0x480
   __driver_attach+0xd9/0xe0
   bus_for_each_dev+0x57/0x90
   bus_add_driver+0x168/0x260
   driver_register+0x52/0xc0
   do_one_initcall+0x39/0x150
   do_init_module+0x56/0x1ef
   load_module+0x231c/0x2d70
   SyS_finit_module+0xa5/0xe0
   entry_SYSCALL_64_fastpath+0x1c/0x89

-> #0 (>struct_mutex){+.+.}:
   __mutex_lock+0x81/0x9b0
   i915_mutex_lock_interruptible+0x47/0x130 [i915]
   i915_gem_fault+0x201/0x790 [i915]
   __do_fault+0x15/0x70
   __handle_mm_fault+0x677/0xdc0
   handle_mm_fault+0x14f/0x2f0
   __do_page_fault+0x2d1/0x560
   page_fault+0x4c/0x60

other info that might help us debug this:

Chain exists of:
  >struct_mutex --> >s_type->i_mutex_key#3 --> >mmap_sem

 Possible unsafe locking scenario:

   CPU0CPU1
   
  lock(>mmap_sem);
   lock(>s_type->i_mutex_key#3);
   lock(>mmap_sem);
  lock(>struct_mutex);

 *** DEADLOCK ***

1 lock held by debugfs_test/1388:
 #0:  (>mmap_sem){}, at: [<29a9c131>] 
__do_page_fault+0x106/0x560

stack backtrace:
CPU: 2 PID: 1388 Comm: debugfs_test Not tainted 4.15.0-rc6-CI-Patchwork_7614+ #1
Hardware name: To Be Filled By O.E.M. To Be Filled By O.E.M./J4205-ITX, BIOS 
P1.10 09/29/2016
Call Trace:
 dump_stack+0x5f/0x86
 print_circular_bug.isra.18+0x1d0/0x2c0
 __lock_acquire+0x14ae/0x1b60
 ? lock_acquire+0xaf/0x200
 lock_acquire+0xaf/0x200
 ? i915_mutex_lock_interruptible+0x47/0x130 [i915]
 __mutex_lock+0x81/0x9b0
 ? i915_mutex_lock_interruptible+0x47/0x130 [i915]
 ? i915_mutex_lock_interruptible+0x47/0x130 [i915]
 ? i915_mutex_lock_interruptible+0x47/0x130 [i915]
 i915_mutex_lock_interruptible+0x47/0x130 [i915]
 ? __pm_runtime_resume+0x4f/0x80
 i915_gem_fault+0x201/0x790 [i915]
 __do_fault+0x15/0x70
 ? _raw_spin_unlock+0x29/0x40
 __handle_mm_fault+0x677/0xdc0
 handle_mm_fault+0x14f/0x2f0
 __do_page_fault+0x2d1/0x560
 ? page_fault+0x36/0x60
 page_fault+0x4c/0x60

v2: Added lock protection to guc->log.runtime.relay_chan (Chris)
Fixed locking inside guc_flush_logs uncovered by new lockdep.

v3: Locking guc_read_update_log_buffer entirely with relay_lock. (Chris)
Prepared intel_guc_init_early. Moved relay_lock inside relay_create
relay_destroy, relay_file_create, guc_read_update_log_buffer. (Michal)
Removed struct_mutex lock around guc_log_flush and removed usage
of guc_log_has_relay() from runtime_create path as it needs
struct_mutex lock.

Bugzilla: 

[Intel-gfx] [PATCH v3 2/6] drm/i915/guc: Enable interrupts before resuming GuC during runtime resume

[Sagar Arun Kamble]

GuC log streaming needs interrupts enabled prior to GuC resume but
runtime pm interrupt setup was happening post GuC resume. Fix it.
While at it, fix the unwinding of steps in the runtime suspend path.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104695
Signed-off-by: Sagar Arun Kamble 
Cc: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Cc: Joonas Lahtinen 
Cc: Marta Lofstedt 
Reviewed-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.c | 13 +
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1fbe378..95e1c16 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2600,6 +2600,11 @@ static int intel_runtime_suspend(struct device *kdev)
 
intel_runtime_pm_enable_interrupts(dev_priv);
 
+   intel_guc_resume(dev_priv);
+
+   i915_gem_init_swizzling(dev_priv);
+   i915_gem_restore_fences(dev_priv);
+
enable_rpm_wakeref_asserts(dev_priv);
 
return ret;
@@ -2665,8 +2670,6 @@ static int intel_runtime_resume(struct device *kdev)
if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
 
-   intel_guc_resume(dev_priv);
-
if (IS_GEN9_LP(dev_priv)) {
bxt_disable_dc9(dev_priv);
bxt_display_core_init(dev_priv, true);
@@ -2681,6 +2684,10 @@ static int intel_runtime_resume(struct device *kdev)
 
intel_uncore_runtime_resume(dev_priv);
 
+   intel_runtime_pm_enable_interrupts(dev_priv);
+
+   intel_guc_resume(dev_priv);
+
/*
 * No point of rolling back things in case of an error, as the best
 * we can do is to hope that things will still work (and disable RPM).
@@ -2688,8 +2695,6 @@ static int intel_runtime_resume(struct device *kdev)
i915_gem_init_swizzling(dev_priv);
i915_gem_restore_fences(dev_priv);
 
-   intel_runtime_pm_enable_interrupts(dev_priv);
-
/*
 * On VLV/CHV display interrupts are part of the display
 * power well, so hpd is reinitialized from there. For
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 5/6] drm/i915/guc: Fix comments style in intel_guc_log.c

[Sagar Arun Kamble]

Use consistent multi-line comment style as per guideline.

Suggested-by: Michal Wajdeczko 
Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_guc_log.c | 49 +++-
 1 file changed, 32 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 27eb545..7c6c41b 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -30,7 +30,7 @@
 
 static void guc_log_capture_logs(struct intel_guc *guc);
 
-/**
+/*
  * DOC: GuC firmware log
  *
  * Firmware log is enabled by setting i915.guc_log_level to the positive level.
@@ -81,7 +81,8 @@ static int subbuf_start_callback(struct rchan_buf *buf,
 void *prev_subbuf,
 size_t prev_padding)
 {
-   /* Use no-overwrite mode by default, where relay will stop accepting
+   /*
+* Use no-overwrite mode by default, where relay will stop accepting
 * new data if there are no empty sub buffers left.
 * There is no strict synchronization enforced by relay between Consumer
 * and Producer. In overwrite mode, there is a possibility of getting
@@ -107,7 +108,8 @@ static struct dentry *create_buf_file_callback(const char 
*filename,
 {
struct dentry *buf_file;
 
-   /* This to enable the use of a single buffer for the relay channel and
+   /*
+* This to enable the use of a single buffer for the relay channel and
 * correspondingly have a single file exposed to User, through which
 * it can collect the logs in order without any post-processing.
 * Need to set 'is_global' even if parent is NULL for early logging.
@@ -117,7 +119,8 @@ static struct dentry *create_buf_file_callback(const char 
*filename,
if (!parent)
return NULL;
 
-   /* Not using the channel filename passed as an argument, since for each
+   /*
+* Not using the channel filename passed as an argument, since for each
 * channel relay appends the corresponding CPU number to the filename
 * passed in relay_open(). This should be fine as relay just needs a
 * dentry of the file associated with the channel buffer and that file's
@@ -158,7 +161,8 @@ static int guc_log_relay_file_create(struct intel_guc *guc)
/* For now create the log file in /sys/kernel/debug/dri/0 dir */
log_dir = dev_priv->drm.primary->debugfs_root;
 
-   /* If /sys/kernel/debug/dri/0 location do not exist, then debugfs is
+   /*
+* If /sys/kernel/debug/dri/0 location do not exist, then debugfs is
 * not mounted and so can't create the relay file.
 * The relay API seems to fit well with debugfs only, for availing relay
 * there are 3 requirements which can be met for debugfs file only in a
@@ -195,7 +199,8 @@ static bool guc_log_has_relay(struct intel_guc *guc)
 
 static void guc_move_to_next_buf(struct intel_guc *guc)
 {
-   /* Make sure the updates made in the sub buffer are visible when
+   /*
+* Make sure the updates made in the sub buffer are visible when
 * Consumer sees the following update to offset inside the sub buffer.
 */
smp_wmb();
@@ -215,7 +220,8 @@ static void *guc_get_write_buffer(struct intel_guc *guc)
if (!guc_log_has_relay(guc))
return NULL;
 
-   /* Just get the base address of a new sub buffer and copy data into it
+   /*
+* Just get the base address of a new sub buffer and copy data into it
 * ourselves. NULL will be returned in no-overwrite mode, if all sub
 * buffers are full. Could have used the relay_write() to indirectly
 * copy the data, but that would have been bit convoluted, as we need to
@@ -290,7 +296,8 @@ static void guc_read_update_log_buffer(struct intel_guc 
*guc)
dst_data += PAGE_SIZE;
 
for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
-   /* Make a copy of the state structure, inside GuC log buffer
+   /*
+* Make a copy of the state structure, inside GuC log buffer
 * (which is uncached mapped), on the stack to avoid reading
 * from it multiple times.
 */
@@ -317,7 +324,8 @@ static void guc_read_update_log_buffer(struct intel_guc 
*guc)
memcpy(log_buf_snapshot_state, _buf_state_local,
   sizeof(struct guc_log_buffer_state));
 
-   /* The write pointer could have been updated by GuC firmware,
+   /*
+* The write pointer could have been updated by GuC firmware,
 * after sending the flush interrupt to Host, for consistency
 * set 

[Intel-gfx] [PATCH v3 1/6] drm/i915/guc: Grab RPM wakelock while disabling GuC interrupts

[Sagar Arun Kamble]

Disabling GuC interrupts involves access to GuC IRQ control registers
hence ensure device is RPM awake.

v2: Add comment about need to synchronize flush work and log runtime
destroy

v3: Moved patch earlier in the series and removed comment about future
work. (Tvrtko)

v4-v5: Rebase.

v6: Added assert_rpm_wakelock_held() to gen9_*_guc_interrupts. (Chris)

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_irq.c  | 6 ++
 drivers/gpu/drm/i915/intel_guc_log.c | 3 +++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3517c65..85c46a2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -452,6 +452,8 @@ void gen6_disable_rps_interrupts(struct drm_i915_private 
*dev_priv)
 
 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
 {
+   assert_rpm_wakelock_held(dev_priv);
+
spin_lock_irq(_priv->irq_lock);
gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
spin_unlock_irq(_priv->irq_lock);
@@ -459,6 +461,8 @@ void gen9_reset_guc_interrupts(struct drm_i915_private 
*dev_priv)
 
 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
 {
+   assert_rpm_wakelock_held(dev_priv);
+
spin_lock_irq(_priv->irq_lock);
if (!dev_priv->guc.interrupts_enabled) {
WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
@@ -471,6 +475,8 @@ void gen9_enable_guc_interrupts(struct drm_i915_private 
*dev_priv)
 
 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
 {
+   assert_rpm_wakelock_held(dev_priv);
+
spin_lock_irq(_priv->irq_lock);
dev_priv->guc.interrupts_enabled = false;
 
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 2ffc966..8f2da30 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -639,7 +639,10 @@ void i915_guc_log_unregister(struct drm_i915_private 
*dev_priv)
 
mutex_lock(_priv->drm.struct_mutex);
/* GuC logging is currently the only user of Guc2Host interrupts */
+   intel_runtime_pm_get(dev_priv);
gen9_disable_guc_interrupts(dev_priv);
+   intel_runtime_pm_put(dev_priv);
+
guc_log_runtime_destroy(_priv->guc);
mutex_unlock(_priv->drm.struct_mutex);
 }
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Use enum plane_id for frontbuffer tracking

[Patchwork]

== Series Details ==

Series: drm/i915: Use enum plane_id for frontbuffer tracking
URL   : https://patchwork.freedesktop.org/series/36991/
State : failure

== Summary ==

Test kms_flip:
Subgroup 2x-wf_vblank-ts-check-interruptible:
pass   -> FAIL   (shard-hsw)
Subgroup flip-vs-expired-vblank-interruptible:
fail   -> PASS   (shard-hsw) fdo#102887
Subgroup vblank-vs-modeset-suspend:
pass   -> SKIP   (shard-snb) fdo#102365 +1
Subgroup vblank-vs-modeset-suspend-interruptible:
pass   -> DMESG-WARN (shard-snb)
Subgroup plain-flip-fb-recreate-interruptible:
pass   -> FAIL   (shard-hsw) fdo#100368
Test kms_sysfs_edid_timing:
warn   -> PASS   (shard-apl) fdo#100047
Test gem_softpin:
Subgroup noreloc-s4:
fail   -> SKIP   (shard-snb) fdo#103375
Test perf:
Subgroup buffer-fill:
pass   -> FAIL   (shard-apl) fdo#103755

fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755

shard-apltotal:2753 pass:1716 dwarn:1   dfail:0   fail:23  skip:1013 
time:14064s
shard-hswtotal:2753 pass:1723 dwarn:1   dfail:0   fail:13  skip:1015 
time:15328s
shard-snbtotal:2753 pass:1317 dwarn:2   dfail:0   fail:9   skip:1425 
time:7847s
Blacklisted hosts:
shard-kbltotal:2753 pass:1821 dwarn:16  dfail:1   fail:24  skip:891 
time:3s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7755/shards.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/cnp: Ignore VBT request for know invalid DDC pin.

[Patchwork]

== Series Details ==

Series: drm/i915/cnp: Ignore VBT request for know invalid DDC pin.
URL   : https://patchwork.freedesktop.org/series/36988/
State : success

== Summary ==

Test kms_flip:
Subgroup 2x-plain-flip-fb-recreate:
fail   -> PASS   (shard-hsw)
Subgroup flip-vs-expired-vblank-interruptible:
fail   -> PASS   (shard-hsw) fdo#102887
Test drv_suspend:
Subgroup fence-restore-untiled:
skip   -> PASS   (shard-snb) fdo#102365
Test gem_softpin:
Subgroup noreloc-s4:
fail   -> SKIP   (shard-snb) fdo#103375

fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375

shard-apltotal:2753 pass:1716 dwarn:1   dfail:0   fail:22  skip:1013 
time:13982s
shard-hswtotal:2753 pass:1726 dwarn:1   dfail:0   fail:10  skip:1015 
time:15436s
shard-snbtotal:2753 pass:1319 dwarn:1   dfail:0   fail:9   skip:1424 
time:7928s
Blacklisted hosts:
shard-kbltotal:2753 pass:1836 dwarn:3   dfail:0   fail:24  skip:890 
time:11032s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7754/shards.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v2] drm/i915/execlists: Inhibit context save/restore for the fake preempt context

[Michel Thierry]

On 1/23/2018 1:04 PM, Chris Wilson wrote:

We only use the preempt context to inject an idle point into execlists.
We never need to reference its logical state, so tell the GPU never to
load it or save it.

v2: BIT(2) for save-inhibit.

N.B. Daniele mentioned this bit mbz for ICL, and has been moved into the
submission process rather than the context image.

Suggested-by: Daniele Ceraolo Spurio 
Signed-off-by: Chris Wilson 
Cc: Michal Winiarski 
Cc: Michel Thierry 
Cc: Michal Wajdeczko 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
Cc: Daniele Ceraolo Spurio 
---
  drivers/gpu/drm/i915/intel_lrc.c | 4 
  drivers/gpu/drm/i915/intel_lrc.h | 1 +
  2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 22d471a4228d..c28f267a8417 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2285,6 +2285,10 @@ populate_lr_context(struct i915_gem_context *ctx,
if (!engine->default_state)
regs[CTX_CONTEXT_CONTROL + 1] |=
_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
+   if (ctx->hw_id == PREEMPT_ID)
+   regs[CTX_CONTEXT_CONTROL + 1] |=
+   _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
+  CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT);



This shouldn't break anything and ICL is not merged yet (plus things may 
still change) so if you want to merge this,


Reviewed-by: Michel Thierry 


i915_gem_object_unpin_map(ctx_obj);
  
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h

index 6d4f9b995a11..636ced41225d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -37,6 +37,7 @@
  #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH   (1 << 3)
  #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT   (1 << 0)
  #define   CTX_CTRL_RS_CTX_ENABLE(1 << 1)
+#define  CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT  (1 << 2)


CTX_CTRL_INHIBIT_SYN_CTX_SWITCH should be here, but that's for another 
patch ;)



  #define RING_CONTEXT_STATUS_BUF_BASE(engine)  _MMIO((engine)->mmio_base + 
0x370)
  #define RING_CONTEXT_STATUS_BUF_LO(engine, i) _MMIO((engine)->mmio_base + 
0x370 + (i) * 8)
  #define RING_CONTEXT_STATUS_BUF_HI(engine, i) _MMIO((engine)->mmio_base + 
0x370 + (i) * 8 + 4)


___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 06/17] drm/i915/icl: Do not fix dbuf block size to 512

[James Ausmus]

On Tue, Jan 23, 2018 at 05:05:25PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar 
> 
> GEN9/10 had fixed DBuf block size of 512. Dbuf block size is not a
> fixed number anymore in GEN11, it varies according to bits per pixel
> and tiling. If 8bpp & Yf-tile surface, block size = 256 else block
> size = 512
> 
> This patch addresses the same.
> 
> v2 (from Paulo):
>   - Make it compile.
>   - Fix a few coding style issues.
> v3
>   - Rebase on top of upstream patches
> 
> Signed-off-by: Mahesh Kumar 
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/i915_drv.h |  1 +
>  drivers/gpu/drm/i915/intel_pm.c | 27 ---
>  2 files changed, 21 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8333692dac5a..cc5ac327f267 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1460,6 +1460,7 @@ struct skl_wm_params {
>   uint_fixed_16_16_t plane_blocks_per_line;
>   uint_fixed_16_16_t y_tile_minimum;
>   uint32_t linetime_us;
> + uint32_t dbuf_block_size;
>  };
>  
>  /*
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 11aac65d1543..44d952a3d9a6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4312,7 +4312,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
>  */
>  static uint_fixed_16_16_t
>  skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
> -uint8_t cpp, uint32_t latency)
> +uint8_t cpp, uint32_t latency, uint32_t dbuf_block_size)
>  {
>   uint32_t wm_intermediate_val;
>   uint_fixed_16_16_t ret;
> @@ -4321,7 +4321,7 @@ skl_wm_method1(const struct drm_i915_private *dev_priv, 
> uint32_t pixel_rate,
>   return FP_16_16_MAX;
>  
>   wm_intermediate_val = latency * pixel_rate * cpp;
> - ret = div_fixed16(wm_intermediate_val, 1000 * 512);
> + ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
>  
>   if (INTEL_GEN(dev_priv) >= 10)
>   ret = add_fixed16_u32(ret, 1);
> @@ -4431,6 +4431,15 @@ skl_compute_plane_wm_params(const struct 
> drm_i915_private *dev_priv,
>   wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
>intel_pstate);
>  
> + if (INTEL_GEN(dev_priv) >= 11) {
> + if (fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 8)
> + wp->dbuf_block_size = 256;
> + else
> + wp->dbuf_block_size = 512;
> + } else {
> + wp->dbuf_block_size = 512;
> + }

This could be simplified as (approximately)

wp->dbuf_block_size = 512;
if (INTEL_GEN(dev_priv) >= 11 && fb->modifier == I915_FORMAT_MOD_Yf_TILED &&
wp->cpp == 8)
wp->dbuf_block_size = 256;


> +
>   if (drm_rotation_90_or_270(pstate->rotation)) {
>  
>   switch (wp->cpp) {
> @@ -4457,7 +4466,8 @@ skl_compute_plane_wm_params(const struct 
> drm_i915_private *dev_priv,
>   wp->plane_bytes_per_line = wp->width * wp->cpp;
>   if (wp->y_tiled) {
>   interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *
> -wp->y_min_scanlines, 512);
> +wp->y_min_scanlines,
> +wp->dbuf_block_size);
>  
>   if (INTEL_GEN(dev_priv) >= 10)
>   interm_pbpl++;
> @@ -4465,10 +4475,12 @@ skl_compute_plane_wm_params(const struct 
> drm_i915_private *dev_priv,
>   wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
>   wp->y_min_scanlines);
>   } else if (wp->x_tiled && IS_GEN9(dev_priv)) {
> - interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512);
> + interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
> +wp->dbuf_block_size);
>   wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
>   } else {
> - interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512) + 1;
> + interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
> +wp->dbuf_block_size) + 1;
>   wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
>   }
>  
> @@ -4515,7 +4527,7 @@ static int skl_compute_plane_wm(const struct 
> drm_i915_private *dev_priv,
>   latency += 15;
>  
>   method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
> -  wp->cpp, latency);
> +  wp->cpp, latency, wp->dbuf_block_size);
>   method2 = skl_wm_method2(wp->plane_pixel_rate,
>cstate->base.adjusted_mode.crtc_htotal,
>   

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/lrc: Update reg_state macros to pass checkpatch

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/lrc: Update reg_state macros to 
pass checkpatch
URL   : https://patchwork.freedesktop.org/series/37005/
State : success

== Summary ==

Series 37005v1 series starting with [1/2] drm/i915/lrc: Update reg_state macros 
to pass checkpatch
https://patchwork.freedesktop.org/api/1.0/series/37005/revisions/1/mbox/

Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass   -> DMESG-WARN (fi-elk-e7500) fdo#103989 +1
Test kms_force_connector_basic:
Subgroup prune-stale-modes:
skip   -> PASS   (fi-ivb-3520m)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-snb-2520m) fdo#103713

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:419s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:425s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:371s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:490s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:280s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:484s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:471s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:452s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:280s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:511s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:394s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:400s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:410s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:458s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:413s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:459s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:494s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:454s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:501s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:581s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:433s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:503s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:527s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:488s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:483s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:418s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:436s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:516s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:394s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:567s
fi-glk-dsi   total:288  pass:257  dwarn:0   dfail:0   fail:1   skip:30  
time:476s

f9207df88e2a2a5803e1ddee7738c1a1aa2fcb74 drm-tip: 2018y-01m-23d-23h-25m-55s UTC 
integration manifest
0768ca315b93 drm/i915: Move LRC register offsets to a header file
32dc9f20aecf drm/i915/lrc: Update reg_state macros to pass checkpatch

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7764/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 05/17] drm/i915/icl: Don't allocate fixed bypass path blocks for ICL

[James Ausmus]

On Tue, Jan 23, 2018 at 05:05:24PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar 
> 
> GEN9 onwards bypass path allocation of 4 blocks was needed, as per
> hardware design. ICL doesn't require bypass path allocation of 4 DDB
> blocks, handling the same in this patch.
> 
> v2 (from Paulo):
>   - No need for a comment that says what the code already says.
> 
> Reviewed-by: Paulo Zanoni 
> Signed-off-by: Mahesh Kumar 
> Signed-off-by: Paulo Zanoni 

Reviewed-by: James Ausmus 

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0b92ea1dbd40..11aac65d1543 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3778,7 +3778,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device 
> *dev,
>   ddb_size = INTEL_INFO(dev_priv)->ddb_size;
>   WARN_ON(ddb_size == 0);
>  
> - ddb_size -= 4; /* 4 blocks for bypass path allocation */
> + if (INTEL_GEN(dev_priv) < 11)
> + ddb_size -= 4; /* 4 blocks for bypass path allocation */
>  
>   /*
>* If the state doesn't change the active CRTC's, then there's
> -- 
> 2.14.3
> 
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 04/17] drm/i915/icl: Enable both DBuf slices during init

[James Ausmus]

On Tue, Jan 23, 2018 at 05:05:23PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar 
> 
> ICL has 2 slices of DBuf, enable both the slices during display init.
> 
> Ideally we should only enable the second slice when needed in order to
> save power, but while we're not there yet, adopt the simpler solution
> to keep us bug-free.
> 
> v2 (from Paulo):
>   - Add the TODO comment.
>   - Reorganize where things are defined.
>   - Fix indentation.
>   - Remove unnecessary POSTING_READ() calls.
>   - Improve the commit message.
> 
> Signed-off-by: Mahesh Kumar 
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/i915_reg.h |  2 ++
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 34 
> +++--
>  2 files changed, 34 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 979bc06a59f4..1746df9a263d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7122,6 +7122,8 @@ enum {
>  #define  DISP_DATA_PARTITION_5_6 (1<<6)
>  #define  DISP_IPC_ENABLE (1<<3)
>  #define DBUF_CTL _MMIO(0x45008)
> +#define DBUF_CTL_S1  _MMIO(0x45008)

Since it's the exact same register, is it really worth duplicating, or
should we just use the existing DBUF_CTL instead of adding DBUF_CTL_S1?


> +#define DBUF_CTL_S2  _MMIO(0x44FE8)
>  #define  DBUF_POWER_REQUEST  (1<<31)
>  #define  DBUF_POWER_STATE(1<<30)
>  #define GEN7_MSG_CTL _MMIO(0x45010)
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 2556db16c76a..7801a425398f 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2610,6 +2610,36 @@ static void gen9_dbuf_disable(struct drm_i915_private 
> *dev_priv)
>   DRM_ERROR("DBuf power disable timeout!\n");
>  }
>  
> +/*
> + * TODO: we shouldn't always enable DBUF_CTL_S2, we should only enable it 
> when
> + * needed and keep it disabled as much as possible.
> + */
> +static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
> +{
> + I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST);
> + I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) | DBUF_POWER_REQUEST);
> + POSTING_READ(DBUF_CTL_S2);
> +
> + udelay(10);

BSpec says to poll, and timeout/fail after 10 uS, rather than
unconditionally busy wait - worth making more complex to potentially
save a few uS of busy wait?

> +
> + if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
> + !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
> + DRM_ERROR("DBuf power enable timeout\n");
> +}
> +
> +static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
> +{
> + I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) & ~DBUF_POWER_REQUEST);
> + I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) & ~DBUF_POWER_REQUEST);
> + POSTING_READ(DBUF_CTL_S2);
> +
> + udelay(10);
> +
> + if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
> + (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
> + DRM_ERROR("DBuf power disable timeout!\n");
> +}
> +
>  static void skl_display_core_init(struct drm_i915_private *dev_priv,
>  bool resume)
>  {
> @@ -2920,7 +2950,7 @@ static void icl_display_core_init(struct 
> drm_i915_private *dev_priv,
>   icl_init_cdclk(dev_priv);
>  
>   /* 6. Enable DBUF. */
> - gen9_dbuf_enable(dev_priv);
> + icl_dbuf_enable(dev_priv);
>  
>   /* 7. Setup MBUS. */
>   /* FIXME: MBUS code not here yet. */
> @@ -2940,7 +2970,7 @@ static void icl_display_core_uninit(struct 
> drm_i915_private *dev_priv)
>   /* 1. Disable all display engine functions -> aready done */
>  
>   /* 2. Disable DBUF */
> - gen9_dbuf_disable(dev_priv);
> + icl_dbuf_disable(dev_priv);
>  
>   /* 3. Disable CD clock */
>   icl_uninit_cdclk(dev_priv);
> -- 
> 2.14.3
> 
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 1/2] drm/i915/lrc: Update reg_state macros to pass checkpatch

[Michel Thierry]

The macros we use to init the reg_state had the following issues reported
by checkpatch --strict.

  Macro argument reuse 'reg_state' - possible side-effects
  Macro argument reuse 'pos' - possible side-effects
  Macro argument reuse 'ppgtt' - possible side-effects
  spaces preferred around that '+' (ctx:VxV)

So fix these issues before they are moved to a new header file.

Suggested-by: Chris Wilson 
Signed-off-by: Michel Thierry 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_lrc.c | 21 +
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index bb6debbeebc0..e48ba0335782 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -186,19 +186,24 @@
 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
 
 #define CTX_REG(reg_state, pos, reg, val) do { \
-   (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
-   (reg_state)[(pos)+1] = (val); \
+   u32 *reg_state__ = (reg_state); \
+   const u32 pos__ = (pos); \
+   (reg_state__)[(pos__) + 0] = i915_mmio_reg_offset(reg); \
+   (reg_state__)[(pos__) + 1] = (val); \
 } while (0)
 
-#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do {   \
-   const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
-   reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
-   reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
+#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
+   u32 *reg_state__ = (reg_state); \
+   const u64 addr__ = i915_page_dir_dma_addr((ppgtt), (n)); \
+   (reg_state__)[CTX_PDP ## n ## _UDW + 1] = upper_32_bits(addr__); \
+   (reg_state__)[CTX_PDP ## n ## _LDW + 1] = lower_32_bits(addr__); \
 } while (0)
 
 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
-   reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(>pml4)); \
-   reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(>pml4)); \
+   u32 *reg_state__ = (reg_state); \
+   const u64 addr__ = px_dma(>pml4); \
+   (reg_state__)[CTX_PDP0_UDW + 1] = upper_32_bits(addr__); \
+   (reg_state__)[CTX_PDP0_LDW + 1] = lower_32_bits(addr__); \
 } while (0)
 
 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT   0x17
-- 
2.15.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 2/2] drm/i915: Move LRC register offsets to a header file

[Michel Thierry]

Newer platforms may have subtle offset changes, which will increase the
number of defines, so it is probably better to start moving them to its
own header file. Also move the macros used while setting the reg state.

v2: Rename to intel_lrc_reg.h, to be consistent with i915_reg.h and
intel_guc_reg.h (Chris)
v3: License notice shenanigans.
v4: Documentation/process/coding-style.rst is always right (Chris)
v5: Rebase.

Signed-off-by: Michel Thierry 
Cc: Michal Wajdeczko 
Cc: Lucas De Marchi 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_lrc.c | 55 +-
 drivers/gpu/drm/i915/intel_lrc_reg.h | 65 
 2 files changed, 66 insertions(+), 54 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_lrc_reg.h

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e48ba0335782..68d777272e1b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -137,6 +137,7 @@
 #include 
 #include "i915_drv.h"
 #include "i915_gem_render_state.h"
+#include "intel_lrc_reg.h"
 #include "intel_mocs.h"
 
 #define RING_EXECLIST_QFULL(1 << 0x2)
@@ -156,60 +157,6 @@
 #define GEN8_CTX_STATUS_COMPLETED_MASK \
 (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED)
 
-#define CTX_LRI_HEADER_0   0x01
-#define CTX_CONTEXT_CONTROL0x02
-#define CTX_RING_HEAD  0x04
-#define CTX_RING_TAIL  0x06
-#define CTX_RING_BUFFER_START  0x08
-#define CTX_RING_BUFFER_CONTROL0x0a
-#define CTX_BB_HEAD_U  0x0c
-#define CTX_BB_HEAD_L  0x0e
-#define CTX_BB_STATE   0x10
-#define CTX_SECOND_BB_HEAD_U   0x12
-#define CTX_SECOND_BB_HEAD_L   0x14
-#define CTX_SECOND_BB_STATE0x16
-#define CTX_BB_PER_CTX_PTR 0x18
-#define CTX_RCS_INDIRECT_CTX   0x1a
-#define CTX_RCS_INDIRECT_CTX_OFFSET0x1c
-#define CTX_LRI_HEADER_1   0x21
-#define CTX_CTX_TIMESTAMP  0x22
-#define CTX_PDP3_UDW   0x24
-#define CTX_PDP3_LDW   0x26
-#define CTX_PDP2_UDW   0x28
-#define CTX_PDP2_LDW   0x2a
-#define CTX_PDP1_UDW   0x2c
-#define CTX_PDP1_LDW   0x2e
-#define CTX_PDP0_UDW   0x30
-#define CTX_PDP0_LDW   0x32
-#define CTX_LRI_HEADER_2   0x41
-#define CTX_R_PWR_CLK_STATE0x42
-#define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
-
-#define CTX_REG(reg_state, pos, reg, val) do { \
-   u32 *reg_state__ = (reg_state); \
-   const u32 pos__ = (pos); \
-   (reg_state__)[(pos__) + 0] = i915_mmio_reg_offset(reg); \
-   (reg_state__)[(pos__) + 1] = (val); \
-} while (0)
-
-#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
-   u32 *reg_state__ = (reg_state); \
-   const u64 addr__ = i915_page_dir_dma_addr((ppgtt), (n)); \
-   (reg_state__)[CTX_PDP ## n ## _UDW + 1] = upper_32_bits(addr__); \
-   (reg_state__)[CTX_PDP ## n ## _LDW + 1] = lower_32_bits(addr__); \
-} while (0)
-
-#define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
-   u32 *reg_state__ = (reg_state); \
-   const u64 addr__ = px_dma(>pml4); \
-   (reg_state__)[CTX_PDP0_UDW + 1] = upper_32_bits(addr__); \
-   (reg_state__)[CTX_PDP0_LDW + 1] = lower_32_bits(addr__); \
-} while (0)
-
-#define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT   0x17
-#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT   0x26
-#define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT  0x19
-
 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
 #define WA_TAIL_DWORDS 2
diff --git a/drivers/gpu/drm/i915/intel_lrc_reg.h 
b/drivers/gpu/drm/i915/intel_lrc_reg.h
new file mode 100644
index ..6475ed19bce4
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_lrc_reg.h
@@ -0,0 +1,65 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2014-2018 Intel Corporation
+ */
+
+#ifndef _INTEL_LRC_REG_H_
+#define _INTEL_LRC_REG_H_
+
+/* GEN8+ Reg State Context */
+#define CTX_LRI_HEADER_0   0x01
+#define CTX_CONTEXT_CONTROL0x02
+#define CTX_RING_HEAD  0x04
+#define CTX_RING_TAIL  0x06
+#define CTX_RING_BUFFER_START  0x08
+#define CTX_RING_BUFFER_CONTROL0x0a
+#define CTX_BB_HEAD_U  0x0c
+#define CTX_BB_HEAD_L  0x0e
+#define CTX_BB_STATE   0x10
+#define CTX_SECOND_BB_HEAD_U   0x12
+#define CTX_SECOND_BB_HEAD_L   0x14
+#define CTX_SECOND_BB_STATE0x16
+#define CTX_BB_PER_CTX_PTR 0x18
+#define CTX_RCS_INDIRECT_CTX   0x1a
+#define CTX_RCS_INDIRECT_CTX_OFFSET0x1c
+#define CTX_LRI_HEADER_1   

Re: [Intel-gfx] [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values

[James Ausmus]

On Tue, Jan 23, 2018 at 05:05:21PM -0200, Paulo Zanoni wrote:
> On ICL we have two sets of registers: one for port A and another for
> port B. The set of port A registers is the same as the CNL registers.
> 
> Since the procmon table on ICL is the same we want to reuse the CNL
> function. To do that we add a port argument and make CNL always call
> the function passing port A. This way, we'll be able to easily reuse
> the function on ICL when we add icl_display_core_init().
> 
> v2: Don't use _PICK() when you can use a ternary operator.
> 
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 26 ++
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 21 ++---
>  2 files changed, 40 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d72e206b2b9f..ebf6261d30fd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2102,6 +2102,32 @@ enum i915_power_well_id {
>  #define CNL_PORT_COMP_DW9_MMIO(0x162124)
>  #define CNL_PORT_COMP_DW10   _MMIO(0x162128)
>  
> +#define _ICL_PORT_COMP_DW0_A 0x162100
> +#define _ICL_PORT_COMP_DW0_B 0x6C100
> +#define ICL_PORT_COMP_DW0(port)  _MMIO((port == PORT_A) ?
> \
> +   _ICL_PORT_COMP_DW0_A :\
> +   _ICL_PORT_COMP_DW0_B)
> +#define _ICL_PORT_COMP_DW1_A 0x162104
> +#define _ICL_PORT_COMP_DW1_B 0x6C104
> +#define ICL_PORT_COMP_DW1(port)  _MMIO((port == PORT_A) ?
> \
> +   _ICL_PORT_COMP_DW1_A :\
> +   _ICL_PORT_COMP_DW1_B)
> +#define _ICL_PORT_COMP_DW3_A 0x16210C
> +#define _ICL_PORT_COMP_DW3_B 0x6C10C
> +#define ICL_PORT_COMP_DW3(port)  _MMIO((port == PORT_A) ?
> \
> +   _ICL_PORT_COMP_DW3_A :\
> +   _ICL_PORT_COMP_DW3_B)
> +#define _ICL_PORT_COMP_DW9_A 0x162124
> +#define _ICL_PORT_COMP_DW9_B 0x6C124
> +#define ICL_PORT_COMP_DW9(port)  _MMIO((port == PORT_A) ?
> \
> +   _ICL_PORT_COMP_DW9_A :\
> +   _ICL_PORT_COMP_DW9_B)
> +#define _ICL_PORT_COMP_DW10_A0x162128
> +#define _ICL_PORT_COMP_DW10_B0x6C128
> +#define ICL_PORT_COMP_DW10(port) _MMIO((port == PORT_A) ?\
> +   _ICL_PORT_COMP_DW10_A :   \
> +   _ICL_PORT_COMP_DW10_B)
> +
>  /* BXT PHY Ref registers */
>  #define _PORT_REF_DW3_A  0x16218C
>  #define _PORT_REF_DW3_BC 0x6C18C
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 5b1aa4b9c72c..73dd525d241a 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2758,12 +2758,19 @@ static const struct cnl_procmon {
>   { .dw1 = 0x0044, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
>  };
>  
> -static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv)
> +/*
> + * CNL has just one set of registers, while ICL has two sets: one for port A 
> and
> + * the other for port B. The CNL registers are equivalent to the ICL port A
> + * registers, that's why we call the ICL macros even though the function has 
> CNL
> + * on its name.
> + */
> +static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
> +enum port port)
>  {
>   const struct cnl_procmon *procmon;
>   u32 val;
>  
> - val = I915_READ(CNL_PORT_COMP_DW3);
> + val = I915_READ(ICL_PORT_COMP_DW3(port));
>   switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
>   default:
>   MISSING_CASE(val);
> @@ -2784,13 +2791,13 @@ static void cnl_set_procmon_ref_values(struct 
> drm_i915_private *dev_priv)
>   break;
>   }
>  
> - val = I915_READ(CNL_PORT_COMP_DW1);
> + val = I915_READ(ICL_PORT_COMP_DW1(port));
>   val &= ~((0xff << 16) | 0xff);
>   val |= procmon->dw1;
> - I915_WRITE(CNL_PORT_COMP_DW1, val);
> + I915_WRITE(ICL_PORT_COMP_DW1(port), val);
>  
> - I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9);
> - I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10);
> + I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);
> + I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
>  }
>  
>  static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool 
> resume)
> @@ -2811,7 +2818,7 @@ static void cnl_display_core_init(struct 
> drm_i915_private *dev_priv, bool resume
>   val &= ~CNL_COMP_PWR_DOWN;
>   

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Fix aux selection for WA 1178

[Rodrigo Vivi]

On Tue, Jan 23, 2018 at 11:13:14PM +, Lucas De Marchi wrote:
> On Tue, Jan 23, 2018 at 01:52:45PM -0800, Rodrigo Vivi wrote:
> > Current code always select _CNL_AUX_ANAOVRD1_B
> > register regardless the pw in use.
> > 
> > CNL_DISP_PW_AUX_B = 9
> > CNL_DISP_PW_AUX_C = 10
> > CNL_DISP_PW_AUX_D = 11
> > 
> > And for pick we want
> > 
> > B = 0
> > C = 1
> > D = 2
> > 
> > Fixes: ddd39e4b3f8f ("drm/i915/cnl: apply Display WA #1178 to fix type C 
> > dongles")
> > Cc: Lucas De Marchi 
> > Signed-off-by: Rodrigo Vivi 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index abd9ee876186..42ced2f3ae7e 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8422,7 +8422,7 @@ enum skl_power_gate {
> >  #define  SKL_PW_TO_PG(pw)  ((pw) - SKL_DISP_PW_1 + SKL_PG1)
> >  #define  SKL_FUSE_PG_DIST_STATUS(pg)   (1 << (27 - (pg)))
> >  
> > -#define _CNL_AUX_REG_IDX(pw)   ((pw - 1) >> 4)
> > +#define _CNL_AUX_REG_IDX(pw)   ((pw) - 9)
> 
> Ugh, I guess I based this on the _HSW_PW_REG_IDX() macro and made a
> complete mess out of it, sorry.

whatever you did back there I fully agreed, so my bad as well

> 
> Acked-by: Lucas De Marchi 

merged. thanks.

> 
> 
> Lucas De Marchi
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Extend Wa 1178 to Aux F.

[Lucas De Marchi]

On Tue, Jan 23, 2018 at 01:57:13PM -0800, Rodrigo Vivi wrote:
> We also need to extend this WA to Aux F.
> 
> Cc: Dhinakaran Pandiyan 
> Cc: Lucas De Marchi 
> Signed-off-by: Rodrigo Vivi 

Reviewed-by: Lucas De Marchi 

Lucas De Marchi

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 4 +++-
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
>  2 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 671303a0310f..2916124d2950 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8435,10 +8435,12 @@ enum skl_power_gate {
>  #define _CNL_AUX_ANAOVRD1_B  0x162250
>  #define _CNL_AUX_ANAOVRD1_C  0x162210
>  #define _CNL_AUX_ANAOVRD1_D  0x1622D0
> +#define _CNL_AUX_ANAOVRD1_F  0x162A90
>  #define CNL_AUX_ANAOVRD1(pw) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw), \
>   _CNL_AUX_ANAOVRD1_B, \
>   _CNL_AUX_ANAOVRD1_C, \
> - _CNL_AUX_ANAOVRD1_D))
> + _CNL_AUX_ANAOVRD1_D, \
> + _CNL_AUX_ANAOVRD1_F))
>  #define   CNL_AUX_ANAOVRD1_ENABLE(1<<16)
>  #define   CNL_AUX_ANAOVRD1_LDO_BYPASS(1<<23)
>  
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 27174d49a529..73700a41723e 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -395,7 +395,7 @@ static void hsw_power_well_enable(struct drm_i915_private 
> *dev_priv,
>   /* Display WA #1178: cnl */
>   if (IS_CANNONLAKE(dev_priv) &&
>   (id == CNL_DISP_PW_AUX_B || id == CNL_DISP_PW_AUX_C ||
> -  id == CNL_DISP_PW_AUX_D)) {
> +  id == CNL_DISP_PW_AUX_D || id == CNL_DISP_PW_AUX_F)) {
>   val = I915_READ(CNL_AUX_ANAOVRD1(id));
>   val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
>   I915_WRITE(CNL_AUX_ANAOVRD1(id), val);
> -- 
> 2.13.6
> 
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/cnp: Ignore VBT request for know invalid DDC pin.

[Rodrigo Vivi]

On Tue, Jan 23, 2018 at 05:40:50PM +, Rodrigo Vivi wrote:
> Let's ignore VBT request if the pin is clearly wrong.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104139
> Cc: Kai Heng Feng 
> Signed-off-by: Rodrigo Vivi 

Reviewed-by: Radhakrishna Sripada 
(f2f)
thanks

merged to dinq.

> ---
>  drivers/gpu/drm/i915/intel_bios.c | 11 ---
>  1 file changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_bios.c 
> b/drivers/gpu/drm/i915/intel_bios.c
> index b0668202dc7e..95f0b310d656 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -1115,9 +1115,14 @@ static const u8 cnp_ddc_pin_map[] = {
>  
>  static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
>  {
> - if (HAS_PCH_CNP(dev_priv) &&
> - vbt_pin > 0 && vbt_pin < ARRAY_SIZE(cnp_ddc_pin_map))
> - return cnp_ddc_pin_map[vbt_pin];
> + if (HAS_PCH_CNP(dev_priv)) {
> + if (vbt_pin > 0 && vbt_pin < ARRAY_SIZE(cnp_ddc_pin_map))
> + return cnp_ddc_pin_map[vbt_pin];
> + if (vbt_pin > GMBUS_PIN_4_CNP) {
> + DRM_DEBUG_KMS("Ignoring alternate pin: VBT claims DDC 
> pin %d, which is not valid for this platform\n", vbt_pin);
> + return 0;
> + }
> + }
>  
>   return vbt_pin;
>  }
> -- 
> 2.13.6
> 
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev8)

[Patchwork]

== Series Details ==

Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for 
another SKU. (rev8)
URL   : https://patchwork.freedesktop.org/series/36828/
State : failure

== Summary ==

Applying: drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
Applying: drm/i915/cnl: Extend Wa 1178 to Aux F.
Applying: drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition.
Applying: drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F.
Applying: drm/i915/cnl: Add right GMBUS pin number for HDMI on Port F.
Applying: drm/i915: For HPD connected port use hpd_pin instead of port.
Applying: drm/i915/cnl: Add HPD support for Port F.
Applying: drm/i915/cnl: Enable DDI-F on Cannonlake.
error: Failed to merge in the changes.
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/i915_reg.h
M   drivers/gpu/drm/i915/intel_display.c
M   drivers/gpu/drm/i915/intel_display.h
M   drivers/gpu/drm/i915/intel_runtime_pm.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_runtime_pm.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_runtime_pm.c
Auto-merging drivers/gpu/drm/i915/intel_display.h
Auto-merging drivers/gpu/drm/i915/intel_display.c
Auto-merging drivers/gpu/drm/i915/i915_reg.h
Patch failed at 0008 drm/i915/cnl: Enable DDI-F on Cannonlake.
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Fix aux selection for WA 1178

[Lucas De Marchi]

On Tue, Jan 23, 2018 at 01:52:45PM -0800, Rodrigo Vivi wrote:
> Current code always select _CNL_AUX_ANAOVRD1_B
> register regardless the pw in use.
> 
> CNL_DISP_PW_AUX_B = 9
> CNL_DISP_PW_AUX_C = 10
> CNL_DISP_PW_AUX_D = 11
> 
> And for pick we want
> 
> B = 0
> C = 1
> D = 2
> 
> Fixes: ddd39e4b3f8f ("drm/i915/cnl: apply Display WA #1178 to fix type C 
> dongles")
> Cc: Lucas De Marchi 
> Signed-off-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index abd9ee876186..42ced2f3ae7e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8422,7 +8422,7 @@ enum skl_power_gate {
>  #define  SKL_PW_TO_PG(pw)((pw) - SKL_DISP_PW_1 + SKL_PG1)
>  #define  SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
>  
> -#define _CNL_AUX_REG_IDX(pw) ((pw - 1) >> 4)
> +#define _CNL_AUX_REG_IDX(pw) ((pw) - 9)

Ugh, I guess I based this on the _HSW_PW_REG_IDX() macro and made a
complete mess out of it, sorry.

Acked-by: Lucas De Marchi 


Lucas De Marchi
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm/i915/cnl: Don't try to manage Port F power wells on all CNL.

[Rodrigo Vivi]

SKUs that lacks on the full port F split will just time out
when touching this power well bits, causing a noisy warn.

v2: Suggested-by: Imre. Temporarily remove the aux pw id after setting
it instead of duplicating and redefining everything.
v3: Simplify even more the logic, using one that don't mix the
array size with the pw bits. Also add a comment.

Cc: Dhinakaran Pandiyan 
Cc: Lucas De Marchi 
Cc: Imre Deak 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 4b215acea439..30e50ea16960 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2544,6 +2544,16 @@ int intel_power_domains_init(struct drm_i915_private 
*dev_priv)
set_power_wells(power_domains, skl_power_wells);
} else if (IS_CANNONLAKE(dev_priv)) {
set_power_wells(power_domains, cnl_power_wells);
+
+   /*
+* DDI and Aux IO are getting enabled for all ports
+* regardless the presence or use. So, in order to avoid
+* timeouts, lets remove them from the list
+* for the SKUs without port F.
+*/
+   if (!IS_CNL_WITH_PORT_F(dev_priv))
+   power_domains->power_well_count -= 2;
+
} else if (IS_BROXTON(dev_priv)) {
set_power_wells(power_domains, bxt_power_wells);
} else if (IS_GEMINILAKE(dev_priv)) {
-- 
2.13.6

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Fix DP max rate for Cannonlake with port F.

[Manasi Navare]

On Tue, Jan 23, 2018 at 02:32:57PM -0800, Rodrigo Vivi wrote:
> On CNL SKUs that uses port F,  max DP rate is 8.1G for all
> ports when we have the elevated voltage.
>

Just a nit here on the commit message. Would it make more sense
to mention the elevated voltage numerical value instead of just
elevated voltage?

Other than that the rate selection logic is correct.

Reviewed-by: Manasi Navare 

Manasi
 
> v2: Make commit message more generic.
> v3: Move conditions to a helper to get easier to read. (Ville).
> 
> Cc: Ville Syrjälä 
> Cc: Lucas De Marchi 
> Cc: Manasi Navare 
> Signed-off-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 29 ++---
>  1 file changed, 22 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 2b26ffe100b1..31a968f20761 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -220,15 +220,34 @@ intel_dp_downstream_max_dotclock(struct intel_dp 
> *intel_dp)
>   return max_dotclk;
>  }
>  
> +static int cnl_adjusted_max_rate(struct intel_dp *intel_dp, int size)
> +{
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> + enum port port = dig_port->base.port;
> +
> + u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> +
> + /* Low voltage SKUs are limited to max of 5.4G */
> + if (voltage == VOLTAGE_INFO_0_85V)
> + return size - 2;
> +
> + /* For this SKU 8.1G is supported in all ports */
> + if(IS_CNL_WITH_PORT_F(dev_priv))
> + return size;
> +
> + /* For other SKUs, max rate on ports A and B is 5.4G */
> + if (port == PORT_A || port == PORT_D)
> + return size - 2;
> +}
> +
>  static void
>  intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  {
>   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>   struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> - enum port port = dig_port->base.port;
>   const int *source_rates;
>   int size;
> - u32 voltage;
>  
>   /* This should only be done once */
>   WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
> @@ -238,11 +257,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>   size = ARRAY_SIZE(bxt_rates);
>   } else if (IS_CANNONLAKE(dev_priv)) {
>   source_rates = cnl_rates;
> - size = ARRAY_SIZE(cnl_rates);
> - voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> - if (port == PORT_A || port == PORT_D ||
> - voltage == VOLTAGE_INFO_0_85V)
> - size -= 2;
> + size = cnl_adjusted_max_rate(intel_dp, ARRAY_SIZE(cnl_rates));
>   } else if (IS_GEN9_BC(dev_priv)) {
>   source_rates = skl_rates;
>   size = ARRAY_SIZE(skl_rates);
> -- 
> 2.13.6
> 
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev7)

[Patchwork]

== Series Details ==

Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for 
another SKU. (rev7)
URL   : https://patchwork.freedesktop.org/series/36828/
State : failure

== Summary ==

Applying: drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
Applying: drm/i915/cnl: Extend Wa 1178 to Aux F.
Applying: drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition.
Applying: drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F.
Applying: drm/i915/cnl: Add right GMBUS pin number for HDMI on Port F.
Applying: drm/i915: For HPD connected port use hpd_pin instead of port.
Applying: drm/i915/cnl: Add HPD support for Port F.
Applying: drm/i915/cnl: Enable DDI-F on Cannonlake.
error: Failed to merge in the changes.
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/i915_reg.h
M   drivers/gpu/drm/i915/intel_display.c
M   drivers/gpu/drm/i915/intel_display.h
M   drivers/gpu/drm/i915/intel_runtime_pm.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_runtime_pm.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_runtime_pm.c
Auto-merging drivers/gpu/drm/i915/intel_display.h
Auto-merging drivers/gpu/drm/i915/intel_display.c
Auto-merging drivers/gpu/drm/i915/i915_reg.h
Patch failed at 0008 drm/i915/cnl: Enable DDI-F on Cannonlake.
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm/i915/cnl: Fix DP max rate for Cannonlake with port F.

[Rodrigo Vivi]

On CNL SKUs that uses port F,  max DP rate is 8.1G for all
ports when we have the elevated voltage.

v2: Make commit message more generic.
v3: Move conditions to a helper to get easier to read. (Ville).

Cc: Ville Syrjälä 
Cc: Lucas De Marchi 
Cc: Manasi Navare 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_dp.c | 29 ++---
 1 file changed, 22 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2b26ffe100b1..31a968f20761 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -220,15 +220,34 @@ intel_dp_downstream_max_dotclock(struct intel_dp 
*intel_dp)
return max_dotclk;
 }
 
+static int cnl_adjusted_max_rate(struct intel_dp *intel_dp, int size)
+{
+   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+   struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+   enum port port = dig_port->base.port;
+
+   u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
+
+   /* Low voltage SKUs are limited to max of 5.4G */
+   if (voltage == VOLTAGE_INFO_0_85V)
+   return size - 2;
+
+   /* For this SKU 8.1G is supported in all ports */
+   if(IS_CNL_WITH_PORT_F(dev_priv))
+   return size;
+
+   /* For other SKUs, max rate on ports A and B is 5.4G */
+   if (port == PORT_A || port == PORT_D)
+   return size - 2;
+}
+
 static void
 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 {
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
-   enum port port = dig_port->base.port;
const int *source_rates;
int size;
-   u32 voltage;
 
/* This should only be done once */
WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
@@ -238,11 +257,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
size = ARRAY_SIZE(bxt_rates);
} else if (IS_CANNONLAKE(dev_priv)) {
source_rates = cnl_rates;
-   size = ARRAY_SIZE(cnl_rates);
-   voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
-   if (port == PORT_A || port == PORT_D ||
-   voltage == VOLTAGE_INFO_0_85V)
-   size -= 2;
+   size = cnl_adjusted_max_rate(intel_dp, ARRAY_SIZE(cnl_rates));
} else if (IS_GEN9_BC(dev_priv)) {
source_rates = skl_rates;
size = ARRAY_SIZE(skl_rates);
-- 
2.13.6

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v2] drm/i915/edp: Do not do link training fallback or prune modes on EDP

[Manasi Navare]

On Tue, Jan 23, 2018 at 02:57:04PM +0200, Imre Deak wrote:
> On Tue, Jan 23, 2018 at 11:48:22AM +0200, Jani Nikula wrote:
> > On Mon, 22 Jan 2018, Imre Deak  wrote:
> > > On Fri, Jan 19, 2018 at 05:45:16PM +0200, Imre Deak wrote:
> > >> On Thu, Oct 12, 2017 at 12:13:38PM -0700, Manasi Navare wrote:
> > >> > In case of eDP because the panel has a fixed mode, the link rate
> > >> > and lane count at which it is trained corresponds to the link BW
> > >> > required to support the native resolution of the panel. In case of
> > >> > panles with lower resolutions where fewer lanes are hooked up 
> > >> > internally,
> > >> > that number is reflected in the MAX_LANE_COUNT DPCD register of the 
> > >> > panel.
> > >> > So it is pointless to fallback to lower link rate/lane count in case
> > >> > of link training failure on eDP connector since the lower link BW
> > >> > will not support the native resolution of the panel and we cannot
> > >> > prune the preferred mode on the eDP connector.
> > >> > 
> > >> > In case of Link training failure on the eDP panel, something is wrong
> > >> > in the HW internally and hence driver errors out with a loud
> > >> > and clear DRM_ERROR message.
> > >> > 
> > >> > v2:
> > >> > * Fix the DEBUG_ERROR and add {} in else (Ville Syrjala)
> > >> > 
> > >> > Cc: Clinton Taylor 
> > >> > Cc: Jim Bride 
> > >> > Cc: Jani Nikula 
> > >> > Cc: Ville Syrjala 
> > >> > Cc: Dave Airlie 
> > >> > Cc: Daniel Vetter 
> > >> > Signed-off-by: Manasi Navare 
> > >> > Reviewed-by: Ville Syrjala 
> > >> 
> > >> This fell through the cracks, looks like it partially fixes
> > >> https://bugs.freedesktop.org/show_bug.cgi?id=103369
> > >> 
> > >> Why link training fails there is not clear.
> > >
> > > Ok, the link training fail turned out to be a race between a modeset
> > > link training and a link retraining called from
> > > runtime_resume->intel_hpd_init->dp_detect. As Ville pointed out that
> > > one was fixed meanwhile by
> > >
> > > commit 42e5e65765265485ecf2a480c244d76c2c624449
> > > Author: Daniel Vetter 
> > > AuthorDate: Mon Nov 13 17:01:40 2017 +0100
> > > Commit: Daniel Vetter 
> > > CommitDate: Thu Nov 23 14:59:07 2017 +0100
> > >
> > > drm/i915: sync dp link status checks against atomic commmits
> > >
> > > I merged now this fix to address the other issue, adding the above bug
> > > as reference. Thanks for the patch and the review.
> > 
> > Thanks for the follow-up... but should we have added a Fixes: or cc:
> > stable tag here?
> 
> Fixes: 9301397a63b3 ("drm/i915: Implement Link Rate fallback on Link
> training failure")
> 
> I wasn't sure about stable, since for me the link training failure
> happened only due to the bug fixed by 42e5e65765265. In any case I can't
> see how it could cause problems, so yes let's Cc: stable too.
> 
> --Imre

Thanks for your feedback Imre and Jani.
This patch avoids fallback and modeset retry for link train failure on edp.
But lately we have seen a bunch of buggy panels that require just another 
modeset
at same link params to pass link training.
So one idea I had and as suggested by DK was that we try harder before failing 
on eDP.

So I was planning to add this code:
On eDP, if link train fails -> power cycle the panel -> Just call modeset retry 
function
without fallback -> send a uevent for modeset retry.

What do you think?

Manasi
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. (rev6)

[Patchwork]

== Series Details ==

Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for 
another SKU. (rev6)
URL   : https://patchwork.freedesktop.org/series/36828/
State : failure

== Summary ==

Applying: drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
Applying: drm/i915/cnl: Extend Wa 1178 to Aux F.
Applying: drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition.
Applying: drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F.
Applying: drm/i915/cnl: Add right GMBUS pin number for HDMI on Port F.
Applying: drm/i915: For HPD connected port use hpd_pin instead of port.
Applying: drm/i915/cnl: Add HPD support for Port F.
Applying: drm/i915/cnl: Enable DDI-F on Cannonlake.
error: Failed to merge in the changes.
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/i915_reg.h
M   drivers/gpu/drm/i915/intel_display.c
M   drivers/gpu/drm/i915/intel_display.h
M   drivers/gpu/drm/i915/intel_runtime_pm.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_runtime_pm.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_runtime_pm.c
Auto-merging drivers/gpu/drm/i915/intel_display.h
Auto-merging drivers/gpu/drm/i915/intel_display.c
Auto-merging drivers/gpu/drm/i915/i915_reg.h
Patch failed at 0008 drm/i915/cnl: Enable DDI-F on Cannonlake.
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Fix aux selection for WA 1178

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: Fix aux selection for WA 1178
URL   : https://patchwork.freedesktop.org/series/36997/
State : success

== Summary ==

Series 36997v1 drm/i915/cnl: Fix aux selection for WA 1178
https://patchwork.freedesktop.org/api/1.0/series/36997/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
dmesg-fail -> DMESG-WARN (fi-elk-e7500) fdo#103989
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> INCOMPLETE (fi-hsw-4770) fdo#103375
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:422s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:428s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:379s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:487s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:281s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:484s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:492s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:466s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:456s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:276s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:512s
fi-hsw-4770  total:244  pass:220  dwarn:0   dfail:0   fail:0   skip:23 
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:400s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:415s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:450s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:414s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:460s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:496s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:449s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:499s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:582s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:426s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:512s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:529s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:489s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:479s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:416s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:400s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:561s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:471s

5e022f5f329c7909cb9aa938364072329f694fb2 drm-tip: 2018y-01m-23d-17h-29m-20s UTC 
integration manifest
1d4d6da9c90e drm/i915/cnl: Fix aux selection for WA 1178

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7760/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm/i915/cnl: Extend Wa 1178 to Aux F.

[Rodrigo Vivi]

We also need to extend this WA to Aux F.

Cc: Dhinakaran Pandiyan 
Cc: Lucas De Marchi 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_reg.h | 4 +++-
 drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 671303a0310f..2916124d2950 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8435,10 +8435,12 @@ enum skl_power_gate {
 #define _CNL_AUX_ANAOVRD1_B0x162250
 #define _CNL_AUX_ANAOVRD1_C0x162210
 #define _CNL_AUX_ANAOVRD1_D0x1622D0
+#define _CNL_AUX_ANAOVRD1_F0x162A90
 #define CNL_AUX_ANAOVRD1(pw)   _MMIO(_PICK(_CNL_AUX_REG_IDX(pw), \
_CNL_AUX_ANAOVRD1_B, \
_CNL_AUX_ANAOVRD1_C, \
-   _CNL_AUX_ANAOVRD1_D))
+   _CNL_AUX_ANAOVRD1_D, \
+   _CNL_AUX_ANAOVRD1_F))
 #define   CNL_AUX_ANAOVRD1_ENABLE  (1<<16)
 #define   CNL_AUX_ANAOVRD1_LDO_BYPASS  (1<<23)
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 27174d49a529..73700a41723e 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -395,7 +395,7 @@ static void hsw_power_well_enable(struct drm_i915_private 
*dev_priv,
/* Display WA #1178: cnl */
if (IS_CANNONLAKE(dev_priv) &&
(id == CNL_DISP_PW_AUX_B || id == CNL_DISP_PW_AUX_C ||
-id == CNL_DISP_PW_AUX_D)) {
+id == CNL_DISP_PW_AUX_D || id == CNL_DISP_PW_AUX_F)) {
val = I915_READ(CNL_AUX_ANAOVRD1(id));
val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
I915_WRITE(CNL_AUX_ANAOVRD1(id), val);
-- 
2.13.6

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm/i915/cnl: Fix aux selection for WA 1178

[Rodrigo Vivi]

Current code always select _CNL_AUX_ANAOVRD1_B
register regardless the pw in use.

CNL_DISP_PW_AUX_B = 9
CNL_DISP_PW_AUX_C = 10
CNL_DISP_PW_AUX_D = 11

And for pick we want

B = 0
C = 1
D = 2

Fixes: ddd39e4b3f8f ("drm/i915/cnl: apply Display WA #1178 to fix type C 
dongles")
Cc: Lucas De Marchi 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index abd9ee876186..42ced2f3ae7e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8422,7 +8422,7 @@ enum skl_power_gate {
 #define  SKL_PW_TO_PG(pw)  ((pw) - SKL_DISP_PW_1 + SKL_PG1)
 #define  SKL_FUSE_PG_DIST_STATUS(pg)   (1 << (27 - (pg)))
 
-#define _CNL_AUX_REG_IDX(pw)   ((pw - 1) >> 4)
+#define _CNL_AUX_REG_IDX(pw)   ((pw) - 9)
 #define _CNL_AUX_ANAOVRD1_B0x162250
 #define _CNL_AUX_ANAOVRD1_C0x162210
 #define _CNL_AUX_ANAOVRD1_D0x1622D0
-- 
2.13.6

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Inhibit context save/restore for the fake preempt context

[Chris Wilson]

Quoting Chris Wilson (2018-01-23 17:05:57)
> We only use the preempt context to inject an idle point into execlists.
> We never need to reference its logical state, so tell the GPU never to
> load it or save it.
> 
> Suggested-by: Daniele Ceraolo Spurio 
> Signed-off-by: Chris Wilson 
> Cc: Michal Winiarski 
> Cc: Michel Thierry 
> Cc: Michal Wajdeczko 
> Cc: Tvrtko Ursulin 
> Cc: Mika Kuoppala 
> ---
> Please check the register definition. I know the save-inhibit bit used
> to exist, I don't know if it is BIT(1) in RING_CONTEXT_CONTROL -- it
> feels like it should be, and the numbers indicate that it does
> something beneficial.

Fwiw, seems to be within normal variation. Just had a string of bad runs
on drm-tip contrasting with a set of good runs with the patch. With a
large enough sample size, no significance. :( Maybe with a bit more tuning
this will have larger impact. Still, I think it's the right thing to do.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Inhibit context save/restore for the fake preempt context (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/execlists: Inhibit context save/restore for the fake preempt 
context (rev2)
URL   : https://patchwork.freedesktop.org/series/36984/
State : success

== Summary ==

Series 36984v2 drm/i915/execlists: Inhibit context save/restore for the fake 
preempt context
https://patchwork.freedesktop.org/api/1.0/series/36984/revisions/2/mbox/

Test debugfs_test:
Subgroup read_all_entries:
dmesg-fail -> DMESG-WARN (fi-elk-e7500) fdo#103989
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:420s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:424s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:373s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:488s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:281s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:481s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:465s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:453s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:280s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:510s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:392s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:401s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:411s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:464s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:419s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:464s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:496s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:450s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:502s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:577s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:433s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:506s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:526s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:487s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:486s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:416s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:393s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:564s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:468s

5e022f5f329c7909cb9aa938364072329f694fb2 drm-tip: 2018y-01m-23d-17h-29m-20s UTC 
integration manifest
929a46223830 drm/i915/execlists: Inhibit context save/restore for the fake 
preempt context

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7759/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915: Use enum plane_id for frontbuffer tracking

[Chris Wilson]

Quoting Ville Syrjala (2018-01-23 18:33:43)
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
> b/drivers/gpu/drm/i915/intel_sprite.c
> index a92c748ca8ab..18ef0392362e 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -345,6 +345,8 @@ skl_plane_get_hw_state(struct intel_plane *plane)
> return ret;
>  }
>  
> +
> +
>  static void
>  chv_update_csc(struct intel_plane *plane, uint32_t format)
>  {

And just in case this unwanted chunk managed to escape notice...
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915: Use enum plane_id for frontbuffer tracking

[Chris Wilson]

Quoting Ville Syrjala (2018-01-23 18:33:43)
> From: Ville Syrjälä 
> 
> Replace the ad-hoc plane indexing scheme used by the frontbuffer
> tracking with enum plane_id.
> 
> The old video overlay not being part of the plane_id namespace
> will just be given the high bit.
> 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  | 11 +++
>  drivers/gpu/drm/i915/intel_display.c |  4 ++--
>  drivers/gpu/drm/i915/intel_fbc.c |  2 +-
>  drivers/gpu/drm/i915/intel_sprite.c  |  4 +++-
>  4 files changed, 9 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8333692dac5a..bd545b1c9546 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2404,16 +2404,11 @@ enum hdmi_force_audio {
>   *
>   * We have one bit per pipe and per scanout plane type.
>   */
> -#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
>  #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8

I would feel safer with a BUILD_BUG_ON to catch plane_id overflowing
INTEL_FRONTBUFFER_BITS_PER_PIPE (-1 for the overlay reservation).

> -#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
> -   (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
> -#define INTEL_FRONTBUFFER_CURSOR(pipe) \
> -   (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe
> -#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
> -   (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe
> +#define INTEL_FRONTBUFFER(pipe, plane_id) \
> +   (1 << ((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
>  #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
> -   (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + 
> (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe
> +   (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + 
> INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
>  #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
> (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))

The conversion looks straightforward nevertheless, and indeed no reason
to have move than one indexing id for a plane.
Reviewed-by: Chris Wilson 
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Add AUX-F support

[Rodrigo Vivi]

On Tue, Jan 23, 2018 at 02:43:22AM +, Pandiyan, Dhinakaran wrote:
> 
> 
> 
> On Mon, 2018-01-22 at 15:59 -0800, Rodrigo Vivi wrote:
> > On some Cannonlake SKUs we have a dedicated Aux for port F,
> > that is only the full split between port A and port E.
> > 
> > There is still no Aux E for Port E, as in previous platforms,
> > because port_E still means shared lanes with port A.
> > 
> > v2: Rebase.
> > v3: Add couple missed PORT_F cases on intel_dp.
> > v4: Rebase and fix commit message.
> > v5: Squash Imre's "drm/i915: Add missing AUX_F power well string"
> > v6: Rebase on top of display headers rework.
> > v7: s/IS_CANNONLAKE/IS_CNL_WITH_PORT_F (DK)
> > v8: Fix Aux bits for Port F (DK)
> > 
> > Cc: Dhinakaran Pandiyan 
> > Cc: Lucas De Marchi 
> > Cc: Imre Deak 
> > Cc: Manasi Navare 
> > Cc: Ville Syrjälä 
> > Signed-off-by: Rodrigo Vivi 
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h |  1 +
> >  drivers/gpu/drm/i915/i915_irq.c |  6 ++
> >  drivers/gpu/drm/i915/i915_reg.h |  9 +
> >  drivers/gpu/drm/i915/intel_display.h|  1 +
> >  drivers/gpu/drm/i915/intel_dp.c |  8 
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +++
> >  6 files changed, 36 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h 
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 3d3727829ac7..7206c7c5f81c 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1255,6 +1255,7 @@ enum modeset_restore {
> >  #define DP_AUX_B 0x10
> >  #define DP_AUX_C 0x20
> >  #define DP_AUX_D 0x30
> > +#define DP_AUX_F 0x50
> 
> How is this decided? Looks like drivers/gpu/drm/i915/gvt/opregion.c
> <> needs to be updated too. I guess that's a
> separate patch. 

Thanks! Another thing that was totally wrong here...

It is defined by VBT.

"Block 2 (General Bytes Definition)"
Aux Channel: "0x60 = DisplayPort Aux F"

> 
> >  
> >  #define DDC_PIN_B  0x05
> >  #define DDC_PIN_C  0x04
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c 
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index db3466ec6faa..0af970d4b3cf 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -2579,6 +2579,9 @@ gen8_de_irq_handler(struct drm_i915_private 
> > *dev_priv, u32 master_ctl)
> > GEN9_AUX_CHANNEL_C |
> > GEN9_AUX_CHANNEL_D;
> >  
> > +   if (IS_CNL_WITH_PORT_F(dev_priv))
> > +   tmp_mask |= CNL_AUX_CHANNEL_F;
> > +
> > if (iir & tmp_mask) {
> > dp_aux_irq_handler(dev_priv);
> > found = true;
> > @@ -3617,6 +3620,9 @@ static void gen8_de_irq_postinstall(struct 
> > drm_i915_private *dev_priv)
> > de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
> > }
> >  
> > +   if (IS_CNL_WITH_PORT_F(dev_priv))
> > +   de_port_masked |= CNL_AUX_CHANNEL_F;
> > +
> > de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
> >GEN8_PIPE_FIFO_UNDERRUN;
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index abd9ee876186..ebdee212767a 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1312,6 +1312,7 @@ enum i915_power_well_id {
> > CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
> > CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
> > CNL_DISP_PW_AUX_D,
> > +   CNL_DISP_PW_AUX_F,
> >  
> > SKL_DISP_PW_1 = 14,
> > SKL_DISP_PW_2,
> > @@ -5284,6 +5285,13 @@ enum {
> >  #define _DPD_AUX_CH_DATA4  (dev_priv->info.display_mmio_offset + 0x64320)
> >  #define _DPD_AUX_CH_DATA5  (dev_priv->info.display_mmio_offset + 0x64324)
> >  
> > +#define _DPF_AUX_CH_CTL(dev_priv->info.display_mmio_offset + 
> > 0x64510)
> > +#define _DPF_AUX_CH_DATA1  (dev_priv->info.display_mmio_offset + 0x64514)
> > +#define _DPF_AUX_CH_DATA2  (dev_priv->info.display_mmio_offset + 0x64518)
> > +#define _DPF_AUX_CH_DATA3  (dev_priv->info.display_mmio_offset + 0x6451c)
> > +#define _DPF_AUX_CH_DATA4  (dev_priv->info.display_mmio_offset + 0x64520)
> > +#define _DPF_AUX_CH_DATA5  (dev_priv->info.display_mmio_offset + 0x64524)
> > +
> >  #define DP_AUX_CH_CTL(port)_MMIO_PORT(port, _DPA_AUX_CH_CTL, 
> > _DPB_AUX_CH_CTL)
> >  #define DP_AUX_CH_DATA(port, i)_MMIO(_PORT(port, _DPA_AUX_CH_DATA1, 
> > _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
> >  
> > @@ -6939,6 +6947,7 @@ enum {
> >  #define GEN8_DE_PORT_IMR _MMIO(0x4)
> >  #define GEN8_DE_PORT_IIR _MMIO(0x8)
> >  #define GEN8_DE_PORT_IER _MMIO(0xc)
> > +#define  CNL_AUX_CHANNEL_F (1 << 28)
> >  #define  GEN9_AUX_CHANNEL_D(1 << 27)
> >  #define  

[Intel-gfx] [PATCH v2] drm/i915/execlists: Inhibit context save/restore for the fake preempt context

[Chris Wilson]

We only use the preempt context to inject an idle point into execlists.
We never need to reference its logical state, so tell the GPU never to
load it or save it.

v2: BIT(2) for save-inhibit.

N.B. Daniele mentioned this bit mbz for ICL, and has been moved into the
submission process rather than the context image.

Suggested-by: Daniele Ceraolo Spurio 
Signed-off-by: Chris Wilson 
Cc: Michal Winiarski 
Cc: Michel Thierry 
Cc: Michal Wajdeczko 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
Cc: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/intel_lrc.c | 4 
 drivers/gpu/drm/i915/intel_lrc.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 22d471a4228d..c28f267a8417 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2285,6 +2285,10 @@ populate_lr_context(struct i915_gem_context *ctx,
if (!engine->default_state)
regs[CTX_CONTEXT_CONTROL + 1] |=
_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
+   if (ctx->hw_id == PREEMPT_ID)
+   regs[CTX_CONTEXT_CONTROL + 1] |=
+   _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
+  CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT);
 
i915_gem_object_unpin_map(ctx_obj);
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 6d4f9b995a11..636ced41225d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -37,6 +37,7 @@
 #define  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH   (1 << 3)
 #define  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT   (1 << 0)
 #define   CTX_CTRL_RS_CTX_ENABLE(1 << 1)
+#define  CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT  (1 << 2)
 #define RING_CONTEXT_STATUS_BUF_BASE(engine)   _MMIO((engine)->mmio_base + 
0x370)
 #define RING_CONTEXT_STATUS_BUF_LO(engine, i)  _MMIO((engine)->mmio_base + 
0x370 + (i) * 8)
 #define RING_CONTEXT_STATUS_BUF_HI(engine, i)  _MMIO((engine)->mmio_base + 
0x370 + (i) * 8 + 4)
-- 
2.15.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Inhibit context save/restore for the fake preempt context

[Chris Wilson]

Quoting Daniele Ceraolo Spurio (2018-01-23 19:37:30)
> 
> 
> On 23/01/18 10:53, Michel Thierry wrote:
> > On 1/23/2018 9:05 AM, Chris Wilson wrote:
> >> We only use the preempt context to inject an idle point into execlists.
> >> We never need to reference its logical state, so tell the GPU never to
> >> load it or save it.
> >>
> >> Suggested-by: Daniele Ceraolo Spurio 
> 
> I don't think I deserve credit for this...

You mentioned this was why you thought icl might be faster... Ergo, you
are responsible :-p
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v4] drm/i915: Move LRC register offsets to a header file

[Chris Wilson]

Quoting Michel Thierry (2018-01-23 19:50:57)
> Newer platforms may have subtle offset changes, which will increase the
> number of defines, so it is probably better to start moving them to its
> own header file. Also move the macros used while setting the reg state.
> 
> v2: Rename to intel_lrc_reg.h, to be consistent with i915_reg.h and
> intel_guc_reg.h (Chris)
> 
> v3: License notice shenanigans.
> 
> v4: Documentation/process/coding-style.rst is always right (Chris)
> 
> Signed-off-by: Michel Thierry 
> Cc: Michal Wajdeczko 
> Cc: Lucas De Marchi 
> Cc: Chris Wilson 
> ---
> +#define CTX_REG(reg_state, pos, reg, val) do { \
> +   (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
> +   (reg_state)[(pos)+1] = (val); \
> +} while (0)
> +
> +#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do {   \
> +   const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
> +   reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
> +   reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \

I know this is a mechanical copy, but we should (reg_state)
nevertheless. We might as well go the extra step and do
u32 regs__ = (reg_state); to silence checkpatch (and pos__).

> +} while (0)
> +
> +#define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
> +   reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(>pml4)); \
> +   reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(>pml4)); \

const u64 addr__ = px_dma() as well.

The jury is out on whether this should be one or two patches. Perfection
would probably be the checkpatch corrections followed by the move (that
way, CI shouldn't complain about the violations).
-Chris

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [igt-dev] [PATCH igt] tests: Add a random load generator

[Chris Wilson]

Quoting Antonio Argenziano (2018-01-23 19:03:48)
> 
> 
> On 21/01/18 12:20, Chris Wilson wrote:
> > Apply a random load to one or all engines in order to apply stress to
> > RPS as it tries to constantly adjust the GPU frequency to meet the
> > changing workload.
> > 
> > Signed-off-by: Chris Wilson 
> > ---
> >   tests/Makefile.sources |   1 +
> >   tests/gem_exec_load.c  | 124 
> > +
> >   2 files changed, 125 insertions(+)
> >   create mode 100644 tests/gem_exec_load.c
> > 
> > diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> > index 6d3857949..5c6242bca 100644
> > --- a/tests/Makefile.sources
> > +++ b/tests/Makefile.sources
> > @@ -83,6 +83,7 @@ TESTS_progs = \
> >   gem_exec_gttfill \
> >   gem_exec_latency \
> >   gem_exec_lut_handle \
> > + gem_exec_load \
> >   gem_exec_nop \
> >   gem_exec_parallel \
> >   gem_exec_params \
> > diff --git a/tests/gem_exec_load.c b/tests/gem_exec_load.c
> > new file mode 100644
> > index 0..d3618f6c0
> > --- /dev/null
> > +++ b/tests/gem_exec_load.c
> > @@ -0,0 +1,124 @@
> > +/*
> > + * Copyright © 2018 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the 
> > "Software"),
> > + * to deal in the Software without restriction, including without 
> > limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including the 
> > next
> > + * paragraph) shall be included in all copies or substantial portions of 
> > the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 
> > OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 
> > OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
> > DEALINGS
> > + * IN THE SOFTWARE.
> > + */
> > +
> > +#include "igt.h"
> > +#include "igt_rand.h"
> > +#include "igt_sysfs.h"
> > +
> > +IGT_TEST_DESCRIPTION("Apply a random load to each engine");
> > +
> > +static inline uint32_t randmax(uint32_t *state, uint32_t ep_ro)
> > +{
> > + return (uint64_t)hars_petruska_f54_1_random(state) * ep_ro >> 32;
> > +}
> > +
> > +static void one(int fd, unsigned int engine, int scale, unsigned int 
> > timeout)
> > +{
> > + struct timespec tv = {};
> > + uint32_t prng = engine;
> > + igt_spin_t *spin[2] = {};
> > + unsigned int max;
> > + int sysfs;
> > +
> > + sysfs = igt_sysfs_open(fd, NULL);
> > +
> > + max = sysfs < 0 ? 1 : igt_sysfs_get_u32(sysfs, "gt_max_freq_mhz");
> > +
> > + do {
> > + /*
> > +  * For every second, we randomly assign a desire % busyness
> > +  * and the frequency with which to submit a batch, defining
> > +  * a pulse-width modulation (pwm).
> > +  */
> > + unsigned int pwm = randmax(, 1000);
> > + unsigned int load = randmax(, pwm / scale);
> > + const unsigned int interval = 1e6 / pwm;
> > + unsigned int cur =
> > + sysfs < 0 ? 1 : igt_sysfs_get_u32(sysfs, 
> > "gt_cur_freq_mhz");
> > +
> > + while (pwm--) {
> > + if (randmax(, pwm * cur) <= load * max) {
> > + spin[1] = __igt_spin_batch_new(fd, 0, engine, 
> > 0);
> > + load--;
> > + }
> > + igt_spin_batch_free(fd, spin[0]);
> > + spin[0] = spin[1];
> > + spin[1] = NULL;
> > +
> > + usleep(interval);
> > + }
> > + } while (igt_seconds_elapsed() < timeout);
> 
> Why not igt_until_timeout()?

I wasn't expecting it to be so simple and forgot about
igt_until_timeout. So no reason other than oversight.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits

[Patchwork]

== Series Details ==

Series: ICL display initialization and some plane bits
URL   : https://patchwork.freedesktop.org/series/36993/
State : failure

== Summary ==

Series 36993v1 ICL display initialization and some plane bits
https://patchwork.freedesktop.org/api/1.0/series/36993/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> FAIL   (fi-skl-6260u)
pass   -> FAIL   (fi-skl-6600u)
pass   -> FAIL   (fi-skl-6700hq) fdo#101144 +2
pass   -> FAIL   (fi-skl-6700k2) fdo#103191 +1
pass   -> FAIL   (fi-skl-6770hq)
pass   -> FAIL   (fi-skl-guc)
pass   -> FAIL   (fi-bxt-dsi)
pass   -> FAIL   (fi-bxt-j4205)
pass   -> FAIL   (fi-kbl-7500u)
pass   -> FAIL   (fi-kbl-7560u)
pass   -> FAIL   (fi-kbl-7567u)
pass   -> FAIL   (fi-kbl-r)
pass   -> FAIL   (fi-glk-1)
Subgroup suspend-read-crc-pipe-b:
pass   -> FAIL   (fi-skl-6260u)
pass   -> FAIL   (fi-skl-6600u)
pass   -> FAIL   (fi-skl-6770hq)
pass   -> FAIL   (fi-skl-guc)
pass   -> FAIL   (fi-bxt-dsi)
pass   -> FAIL   (fi-bxt-j4205)
pass   -> FAIL   (fi-kbl-7500u)
pass   -> FAIL   (fi-kbl-7560u)
pass   -> FAIL   (fi-kbl-7567u)
pass   -> FAIL   (fi-kbl-r)
pass   -> FAIL   (fi-glk-1)
Subgroup suspend-read-crc-pipe-c:
pass   -> FAIL   (fi-skl-6260u) fdo#104108 +3
pass   -> FAIL   (fi-skl-guc)
pass   -> FAIL   (fi-bxt-dsi)
pass   -> FAIL   (fi-bxt-j4205)
pass   -> FAIL   (fi-kbl-7500u)
pass   -> FAIL   (fi-kbl-7560u)
pass   -> FAIL   (fi-kbl-7567u)
pass   -> FAIL   (fi-kbl-r)
pass   -> FAIL   (fi-glk-1)

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:418s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:424s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:371s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:486s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:280s
fi-bxt-dsi   total:288  pass:255  dwarn:0   dfail:0   fail:3   skip:30  
time:480s
fi-bxt-j4205 total:288  pass:256  dwarn:0   dfail:0   fail:3   skip:29  
time:486s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:469s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:454s
fi-elk-e7500 total:224  pass:168  dwarn:9   dfail:1   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:279s
fi-glk-1 total:288  pass:257  dwarn:0   dfail:0   fail:3   skip:28  
time:520s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:390s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:400s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:411s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:459s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:413s
fi-kbl-7500u total:288  pass:260  dwarn:1   dfail:0   fail:3   skip:24  
time:455s
fi-kbl-7560u total:288  pass:266  dwarn:0   dfail:0   fail:3   skip:19  
time:514s
fi-kbl-7567u total:288  pass:265  dwarn:0   dfail:0   fail:3   skip:11  
time:447s
fi-kbl-r total:288  pass:258  dwarn:0   dfail:0   fail:3   skip:27  
time:516s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:594s
fi-skl-6260u total:288  pass:265  dwarn:0   dfail:0   fail:3   skip:20  
time:429s
fi-skl-6600u total:288  pass:258  dwarn:0   dfail:0   fail:3   skip:27  
time:518s
fi-skl-6700hqtotal:288  pass:259  dwarn:0   dfail:0   fail:3   skip:26  
time:542s
fi-skl-6700k2total:288  pass:261  dwarn:0   dfail:0   fail:3   skip:24  
time:480s
fi-skl-6770hqtotal:288  pass:265  dwarn:0   dfail:0   

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Move LRC register offsets to a header file (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Move LRC register offsets to a header file (rev4)
URL   : https://patchwork.freedesktop.org/series/36930/
State : success

== Summary ==

Series 36930v4 drm/i915: Move LRC register offsets to a header file
https://patchwork.freedesktop.org/api/1.0/series/36930/revisions/4/mbox/

Test debugfs_test:
Subgroup read_all_entries:
dmesg-fail -> DMESG-WARN (fi-elk-e7500) fdo#103989
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:418s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:372s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:484s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:281s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:478s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:480s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:467s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:456s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:180  dwarn:0   dfail:0   fail:0   skip:108 
time:280s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:512s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:391s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:399s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:409s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:449s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:412s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:460s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:496s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:454s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:502s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:572s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:430s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:509s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:528s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:484s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:478s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:421s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:524s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:398s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:569s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:469s
fi-bdw-gvtdvm failed to collect. IGT log at Patchwork_7757/fi-bdw-gvtdvm/igt.log

5e022f5f329c7909cb9aa938364072329f694fb2 drm-tip: 2018y-01m-23d-17h-29m-20s UTC 
integration manifest
ecefca426ef3 drm/i915: Move LRC register offsets to a header file

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7757/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v4] drm/i915: Move LRC register offsets to a header file

[Michel Thierry]

Newer platforms may have subtle offset changes, which will increase the
number of defines, so it is probably better to start moving them to its
own header file. Also move the macros used while setting the reg state.

v2: Rename to intel_lrc_reg.h, to be consistent with i915_reg.h and
intel_guc_reg.h (Chris)

v3: License notice shenanigans.

v4: Documentation/process/coding-style.rst is always right (Chris)

Signed-off-by: Michel Thierry 
Cc: Michal Wajdeczko 
Cc: Lucas De Marchi 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_lrc.c | 50 +-
 drivers/gpu/drm/i915/intel_lrc_reg.h | 60 
 2 files changed, 61 insertions(+), 49 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_lrc_reg.h

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index bb6debbeebc0..68d777272e1b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -137,6 +137,7 @@
 #include 
 #include "i915_drv.h"
 #include "i915_gem_render_state.h"
+#include "intel_lrc_reg.h"
 #include "intel_mocs.h"
 
 #define RING_EXECLIST_QFULL(1 << 0x2)
@@ -156,55 +157,6 @@
 #define GEN8_CTX_STATUS_COMPLETED_MASK \
 (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED)
 
-#define CTX_LRI_HEADER_0   0x01
-#define CTX_CONTEXT_CONTROL0x02
-#define CTX_RING_HEAD  0x04
-#define CTX_RING_TAIL  0x06
-#define CTX_RING_BUFFER_START  0x08
-#define CTX_RING_BUFFER_CONTROL0x0a
-#define CTX_BB_HEAD_U  0x0c
-#define CTX_BB_HEAD_L  0x0e
-#define CTX_BB_STATE   0x10
-#define CTX_SECOND_BB_HEAD_U   0x12
-#define CTX_SECOND_BB_HEAD_L   0x14
-#define CTX_SECOND_BB_STATE0x16
-#define CTX_BB_PER_CTX_PTR 0x18
-#define CTX_RCS_INDIRECT_CTX   0x1a
-#define CTX_RCS_INDIRECT_CTX_OFFSET0x1c
-#define CTX_LRI_HEADER_1   0x21
-#define CTX_CTX_TIMESTAMP  0x22
-#define CTX_PDP3_UDW   0x24
-#define CTX_PDP3_LDW   0x26
-#define CTX_PDP2_UDW   0x28
-#define CTX_PDP2_LDW   0x2a
-#define CTX_PDP1_UDW   0x2c
-#define CTX_PDP1_LDW   0x2e
-#define CTX_PDP0_UDW   0x30
-#define CTX_PDP0_LDW   0x32
-#define CTX_LRI_HEADER_2   0x41
-#define CTX_R_PWR_CLK_STATE0x42
-#define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
-
-#define CTX_REG(reg_state, pos, reg, val) do { \
-   (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
-   (reg_state)[(pos)+1] = (val); \
-} while (0)
-
-#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do {   \
-   const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
-   reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
-   reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
-} while (0)
-
-#define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
-   reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(>pml4)); \
-   reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(>pml4)); \
-} while (0)
-
-#define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT   0x17
-#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT   0x26
-#define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT  0x19
-
 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
 #define WA_TAIL_DWORDS 2
diff --git a/drivers/gpu/drm/i915/intel_lrc_reg.h 
b/drivers/gpu/drm/i915/intel_lrc_reg.h
new file mode 100644
index ..7dc53707ef1a
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_lrc_reg.h
@@ -0,0 +1,60 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2014-2018 Intel Corporation
+ */
+
+#ifndef _INTEL_LRC_REG_H_
+#define _INTEL_LRC_REG_H_
+
+/* GEN8+ Reg State Context */
+#define CTX_LRI_HEADER_0   0x01
+#define CTX_CONTEXT_CONTROL0x02
+#define CTX_RING_HEAD  0x04
+#define CTX_RING_TAIL  0x06
+#define CTX_RING_BUFFER_START  0x08
+#define CTX_RING_BUFFER_CONTROL0x0a
+#define CTX_BB_HEAD_U  0x0c
+#define CTX_BB_HEAD_L  0x0e
+#define CTX_BB_STATE   0x10
+#define CTX_SECOND_BB_HEAD_U   0x12
+#define CTX_SECOND_BB_HEAD_L   0x14
+#define CTX_SECOND_BB_STATE0x16
+#define CTX_BB_PER_CTX_PTR 0x18
+#define CTX_RCS_INDIRECT_CTX   0x1a
+#define CTX_RCS_INDIRECT_CTX_OFFSET0x1c
+#define CTX_LRI_HEADER_1   0x21
+#define CTX_CTX_TIMESTAMP  0x22
+#define CTX_PDP3_UDW   0x24
+#define CTX_PDP3_LDW   0x26
+#define CTX_PDP2_UDW   0x28
+#define CTX_PDP2_LDW   

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Inhibit context save/restore for the fake preempt context

[Daniele Ceraolo Spurio]

On 23/01/18 10:53, Michel Thierry wrote:

On 1/23/2018 9:05 AM, Chris Wilson wrote:

We only use the preempt context to inject an idle point into execlists.
We never need to reference its logical state, so tell the GPU never to
load it or save it.

Suggested-by: Daniele Ceraolo Spurio 


I don't think I deserve credit for this...


Signed-off-by: Chris Wilson 
Cc: Michal Winiarski 
Cc: Michel Thierry 
Cc: Michal Wajdeczko 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
---
Please check the register definition. I know the save-inhibit bit used
to exist, I don't know if it is BIT(1) in RING_CONTEXT_CONTROL -- it
feels like it should be, and the numbers indicate that it does
something beneficial.


Hi,


-Chris
---
  drivers/gpu/drm/i915/intel_lrc.c | 4 
  drivers/gpu/drm/i915/intel_lrc.h | 1 +
  2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
b/drivers/gpu/drm/i915/intel_lrc.c

index 22d471a4228d..c28f267a8417 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2285,6 +2285,10 @@ populate_lr_context(struct i915_gem_context *ctx,
  if (!engine->default_state)
  regs[CTX_CONTEXT_CONTROL + 1] |=
  _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
+    if (ctx->hw_id == PREEMPT_ID)
+    regs[CTX_CONTEXT_CONTROL + 1] |=
+    _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
+   CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT);
  i915_gem_object_unpin_map(ctx_obj);
diff --git a/drivers/gpu/drm/i915/intel_lrc.h 
b/drivers/gpu/drm/i915/intel_lrc.h

index 6d4f9b995a11..e6e2c1774600 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -36,6 +36,7 @@
  #define RING_CONTEXT_CONTROL(engine)
_MMIO((engine)->mmio_base + 0x244)

  #define  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH    (1 << 3)
  #define  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT    (1 << 0)
+#define  CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT    (1 << 1)
  #define   CTX_CTRL_RS_CTX_ENABLE    (1 << 1)


BIT(0) is Engine Context Restore Inhibit,
BIT(1) is Resource Streamer Context Enable (in RCS), and
BIT(2) is Context Save Inhibit.



FYI, specs also says that BIT(2) is deprecated and must not be set for ICL.

Daniele



  #define RING_CONTEXT_STATUS_BUF_BASE(engine)
_MMIO((engine)->mmio_base + 0x370)
  #define RING_CONTEXT_STATUS_BUF_LO(engine, i)
_MMIO((engine)->mmio_base + 0x370 + (i) * 8)



___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits

[Patchwork]

== Series Details ==

Series: ICL display initialization and some plane bits
URL   : https://patchwork.freedesktop.org/series/36993/
State : failure

== Summary ==

Series 36993v1 ICL display initialization and some plane bits
https://patchwork.freedesktop.org/api/1.0/series/36993/revisions/1/mbox/

Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-a-frame-sequence:
pass   -> FAIL   (fi-skl-6700k2) fdo#103191 +2
Subgroup suspend-read-crc-pipe-a:
pass   -> FAIL   (fi-skl-6260u)
pass   -> FAIL   (fi-skl-6600u)
pass   -> FAIL   (fi-skl-6700hq) fdo#101144 +2
pass   -> FAIL   (fi-skl-6770hq)
pass   -> FAIL   (fi-skl-guc)
pass   -> FAIL   (fi-bxt-dsi)
pass   -> FAIL   (fi-bxt-j4205)
pass   -> FAIL   (fi-kbl-7500u)
pass   -> FAIL   (fi-kbl-7560u)
pass   -> FAIL   (fi-kbl-7567u)
pass   -> FAIL   (fi-kbl-r)
pass   -> FAIL   (fi-glk-1)
Subgroup suspend-read-crc-pipe-b:
pass   -> FAIL   (fi-skl-6260u)
pass   -> FAIL   (fi-skl-6600u)
pass   -> FAIL   (fi-skl-6770hq)
pass   -> FAIL   (fi-skl-guc)
pass   -> FAIL   (fi-bxt-dsi)
pass   -> FAIL   (fi-bxt-j4205)
pass   -> FAIL   (fi-kbl-7500u)
pass   -> FAIL   (fi-kbl-7560u)
pass   -> FAIL   (fi-kbl-7567u)
pass   -> FAIL   (fi-kbl-r)
pass   -> FAIL   (fi-glk-1)
Subgroup suspend-read-crc-pipe-c:
pass   -> FAIL   (fi-skl-6260u) fdo#104108 +3
pass   -> FAIL   (fi-skl-guc)
pass   -> FAIL   (fi-bxt-dsi)
pass   -> FAIL   (fi-bxt-j4205)
pass   -> FAIL   (fi-kbl-7500u)
pass   -> FAIL   (fi-kbl-7560u)
pass   -> FAIL   (fi-kbl-7567u)
pass   -> FAIL   (fi-kbl-r)
pass   -> FAIL   (fi-glk-1)

fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:429s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:428s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:370s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:482s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:283s
fi-bxt-dsi   total:288  pass:255  dwarn:0   dfail:0   fail:3   skip:30  
time:479s
fi-bxt-j4205 total:288  pass:256  dwarn:0   dfail:0   fail:3   skip:29  
time:486s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:470s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:463s
fi-elk-e7500 total:224  pass:168  dwarn:9   dfail:1   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:280s
fi-glk-1 total:288  pass:257  dwarn:0   dfail:0   fail:3   skip:28  
time:517s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:390s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:400s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:412s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:458s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:414s
fi-kbl-7500u total:288  pass:260  dwarn:1   dfail:0   fail:3   skip:24  
time:456s
fi-kbl-7560u total:288  pass:266  dwarn:0   dfail:0   fail:3   skip:19  
time:510s
fi-kbl-7567u total:288  pass:265  dwarn:0   dfail:0   fail:3   skip:11  
time:449s
fi-kbl-r total:288  pass:258  dwarn:0   dfail:0   fail:3   skip:27  
time:506s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:575s
fi-skl-6260u total:288  pass:265  dwarn:0   dfail:0   fail:3   skip:20  
time:427s
fi-skl-6600u total:288  pass:258  dwarn:0   dfail:0   fail:3   skip:27  
time:519s
fi-skl-6700hqtotal:288  pass:259  dwarn:0   dfail:0   fail:3   skip:26  
time:547s
fi-skl-6700k2total:288  pass:260  dwarn:0   dfail:0   fail:4   skip:24  
time:498s
fi-skl-6770hqtotal:288  pass:265  dwarn:0   dfail:0   fail:3   skip:20  
time:477s
fi-skl-guc   total:288  pass:257  dwarn:0   dfail:0   fail:3   skip:28  
time:410s
fi-snb-2520m 

[Intel-gfx] [PATCH 09/17] drm/i915/icl: Introduce MBus related registers

[Paulo Zanoni]

From: Mahesh Kumar 

This patch introduce MBus control registers and their bit-fields
MBUS_ABOX_CTL
MBUS_BBOX_CTL
MBUS_DBOX_CTL
MBUS_UBOX_CTL

Changes Since V1:
 - Use function like macros (Paulo)
 - fix copy-paste error (Paulo)

Reviewed-by: Paulo Zanoni 
Signed-off-by: Mahesh Kumar 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_reg.h | 25 +
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1746df9a263d..0cb77cd18cdb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2679,6 +2679,31 @@ enum i915_power_well_id {
 #define LM_FIFO_WATERMARK   0x001F
 #define MI_ARB_STATE   _MMIO(0x20e4) /* 915+ only */
 
+#define MBUS_ABOX_CTL  _MMIO(0x45038)
+#define MBUS_ABOX_BW_CREDIT_MASK   (3 << 20)
+#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
+#define MBUS_ABOX_B_CREDIT_MASK(0xF << 16)
+#define MBUS_ABOX_B_CREDIT(x)  ((x) << 16)
+#define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
+#define MBUS_ABOX_BT_CREDIT_POOL2(x)   ((x) << 8)
+#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
+#define MBUS_ABOX_BT_CREDIT_POOL1(x)   ((x) << 0)
+
+#define _PIPEA_MBUS_DBOX_CTL   0x7003C
+#define _PIPEB_MBUS_DBOX_CTL   0x7103C
+#define PIPE_MBUS_DBOX_CTL(pipe)   _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
+  _PIPEB_MBUS_DBOX_CTL)
+#define MBUS_DBOX_BW_CREDIT_MASK   (3 << 14)
+#define MBUS_DBOX_BW_CREDIT(x) ((x) << 14)
+#define MBUS_DBOX_B_CREDIT_MASK(0x1F << 8)
+#define MBUS_DBOX_B_CREDIT(x)  ((x) << 8)
+#define MBUS_DBOX_A_CREDIT_MASK(0xF << 0)
+#define MBUS_DBOX_A_CREDIT(x)  ((x) << 0)
+
+#define MBUS_UBOX_CTL  _MMIO(0x4503C)
+#define MBUS_BBOX_CTL_S1   _MMIO(0x45040)
+#define MBUS_BBOX_CTL_S2   _MMIO(0x45044)
+
 /* Make render/texture TLB fetches lower priorty than associated data
  *   fetches. This is not turned on by default
  */
-- 
2.14.3

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 08/17] drm/i915/icl: NV12 y-plane ddb is not in same plane

[Paulo Zanoni]

From: Mahesh Kumar 

We don't have planar pixel format support implemented for ICL yet.
ICL require 2 display planes to be allocated for Planar formats unlike
previous GEN. So ICL/GEN11 doesn't require to write Y-plane ddb data in
NV12_BUF_CFG register and PLANE_NV12_BUF_CFG register is removed in ICL.

This patch removes the PLANE_NV12_BUF_CFG write for ICL.

Changes Since V1:
 - Improve commit message as per Paulo's comment

Reviewed-by: Paulo Zanoni 
Signed-off-by: Mahesh Kumar 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_pm.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c6d31a5075ad..0237362ccf83 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4832,8 +4832,10 @@ static void skl_write_plane_wm(struct intel_crtc 
*intel_crtc,
 
skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
>plane[pipe][plane_id]);
-   skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
-   >y_plane[pipe][plane_id]);
+   if (INTEL_GEN(dev_priv) < 11)
+   skl_ddb_entry_write(dev_priv,
+   PLANE_NV12_BUF_CFG(pipe, plane_id),
+   >y_plane[pipe][plane_id]);
 }
 
 static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
-- 
2.14.3

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 17/17] drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field

[Paulo Zanoni]

From: James Ausmus 

ICL+ adds changes the PLANE_CTL_FORMAT field from [27:24] to [27:23],
however, all existing PLANE_CTL_FORMAT_* definitions still map to the
correct values.  Add an ICL_PLANE_CTL_FORMAT_MASK definition, and use
that for masking for the conversion to fourcc.

v2: No changes

v3: Change new definition name, drop comment (Rodrigo)

Cc: Rodrigo Vivi 
Reviewed-by: Paulo Zanoni 
Signed-off-by: James Ausmus 
---
 drivers/gpu/drm/i915/i915_reg.h  | 6 ++
 drivers/gpu/drm/i915/intel_display.c | 5 -
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0cb77cd18cdb..1218a6a88cd8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6372,6 +6372,11 @@ enum {
 #define _PLANE_CTL_3_A 0x70380
 #define   PLANE_CTL_ENABLE (1 << 31)
 #define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)   /* Pre-GLK */
+/*
+ * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
+ * expanded to include bit 23 as well. However, the shift-24 based values
+ * correctly map to the same formats in ICL, as long as bit 23 is set to 0
+ */
 #define   PLANE_CTL_FORMAT_MASK(0xf << 24)
 #define   PLANE_CTL_FORMAT_YUV422  (  0 << 24)
 #define   PLANE_CTL_FORMAT_NV12(  1 << 24)
@@ -6381,6 +6386,7 @@ enum {
 #define   PLANE_CTL_FORMAT_AYUV(  8 << 24)
 #define   PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
 #define   PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
+#define   ICL_PLANE_CTL_FORMAT_MASK(0x1f << 23)
 #define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23) /* Pre-GLK */
 #define   PLANE_CTL_KEY_ENABLE_MASK(0x3 << 21)
 #define   PLANE_CTL_KEY_ENABLE_SOURCE  (  1 << 21)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 3eb2359c221b..7d5362e8bc3d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8516,7 +8516,10 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 
val = I915_READ(PLANE_CTL(pipe, plane_id));
 
-   pixel_format = val & PLANE_CTL_FORMAT_MASK;
+   if (INTEL_GEN(dev_priv) >= 11)
+   pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
+   else
+   pixel_format = val & PLANE_CTL_FORMAT_MASK;
 
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
-- 
2.14.3

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 13/17] drm/i915/icl: Enable 2nd DBuf slice only when needed

[Paulo Zanoni]

From: Mahesh Kumar 

ICL has two slices of DBuf, each slice of size 1024 blocks.
We should not always enable slice-2. It should be enabled only if
display total required BW is > 12GBps OR more than 1 pipes are enabled.

Changes since V1:
 - typecast total_data_rate to u64 before multiplication to solve any
   possible overflow (Rodrigo)
 - fix where skl_wm_get_hw_state was memsetting ddb, resulting
   enabled_slices to become zero
 - Fix the logic of calculating ddb_size
Changes since V2:
 - If no-crtc is part of commit required_slices will have value "0",
   don't try to disable DBuf slice.

Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/intel_display.c| 12 +++
 drivers/gpu/drm/i915/intel_drv.h|  6 
 drivers/gpu/drm/i915/intel_pm.c | 64 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 47 +---
 4 files changed, 110 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index bad3b112ac3e..3eb2359c221b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12117,6 +12117,8 @@ static void skl_update_crtcs(struct drm_atomic_state 
*state)
bool progress;
enum pipe pipe;
int i;
+   uint8_t hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
+   uint8_t required_slices = intel_state->wm_results.ddb.enabled_slices;
 
const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
 
@@ -12125,6 +12127,11 @@ static void skl_update_crtcs(struct drm_atomic_state 
*state)
if (new_crtc_state->active)
entries[i] = 
_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
 
+   /* If 2nd DBuf slice required, enable it here */
+   if (INTEL_GEN(dev_priv) >= 11 && required_slices &&
+required_slices > hw_enabled_slices)
+   icl_dbuf_slices_update(dev_priv, required_slices);
+
/*
 * Whenever the number of active pipes changes, we need to make sure we
 * update the pipes in the right order so that their ddb allocations
@@ -12175,6 +12182,11 @@ static void skl_update_crtcs(struct drm_atomic_state 
*state)
progress = true;
}
} while (progress);
+
+   /* If 2nd DBuf slice is no more required disable it */
+   if (INTEL_GEN(dev_priv) >= 11 && required_slices &&
+required_slices < hw_enabled_slices)
+   icl_dbuf_slices_update(dev_priv, required_slices);
 }
 
 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c5d6092aca41..d4639a161fe3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -140,6 +140,10 @@
 #define KHz(x) (1000 * (x))
 #define MHz(x) KHz(1000 * (x))
 
+#define KBps(x) (1000 * (x))
+#define MBps(x) KBps(1000 * (x))
+#define GBps(x) ((uint64_t) 1000 * MBps((x)))
+
 /*
  * Display related stuff
  */
@@ -1890,6 +1894,8 @@ bool intel_display_power_get_if_enabled(struct 
drm_i915_private *dev_priv,
enum intel_display_power_domain domain);
 void intel_display_power_put(struct drm_i915_private *dev_priv,
 enum intel_display_power_domain domain);
+void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
+   uint8_t req_slices);
 
 static inline void
 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e8d98857c208..d4cd631377da 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3767,9 +3767,42 @@ bool intel_can_enable_sagv(struct drm_atomic_state 
*state)
return true;
 }
 
+static unsigned int intel_get_ddb_size(struct drm_i915_private *dev_priv,
+  const struct intel_crtc_state *cstate,
+  const unsigned int total_data_rate,
+  const int num_active,
+  struct skl_ddb_allocation *ddb)
+{
+   const struct drm_display_mode *adjusted_mode;
+   u64 total_data_bw;
+   u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
+
+   WARN_ON(ddb_size == 0);
+
+   if (INTEL_GEN(dev_priv) < 11)
+   return ddb_size - 4; /* 4 blocks for bypass path allocation */
+
+   adjusted_mode = >base.adjusted_mode;
+   total_data_bw = (u64)total_data_rate * drm_mode_vrefresh(adjusted_mode);
+
+   /*
+* 12GB/s is maximum BW supported by single DBuf slice.
+*/
+   if (total_data_bw >= GBps(12) || num_active > 1)
+   ddb->enabled_slices = 2;
+   else {
+ 

[Intel-gfx] [PATCH 16/17] drm/i915/icl: enable SAGV for ICL platform

[Paulo Zanoni]

From: Mahesh Kumar 

Enable SAGV for ICL platform.

Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1edd1445ab5b..dedc76781524 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3605,7 +3605,7 @@ static bool
 intel_has_sagv(struct drm_i915_private *dev_priv)
 {
if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
-   IS_CANNONLAKE(dev_priv))
+   IS_CANNONLAKE(dev_priv) || IS_ICELAKE(dev_priv))
return true;
 
if (IS_SKYLAKE(dev_priv) &&
-- 
2.14.3

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 14/17] drm/i915/icl: update ddb entry start/end mask during hw ddb readout

[Paulo Zanoni]

From: Mahesh Kumar 

Gen11/ICL onward ddb entry start/end mask is increased from 10 bits to
11 bits. This patch make changes to use proper mask for ICL+ during
hardware ddb value readout.

Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/intel_pm.c | 18 ++
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d4cd631377da..84a5b13fdee2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3860,10 +3860,18 @@ static unsigned int skl_cursor_allocation(int 
num_active)
return 8;
 }
 
-static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
+static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
+  struct skl_ddb_entry *entry, u32 reg)
 {
-   entry->start = reg & 0x3ff;
-   entry->end = (reg >> 16) & 0x3ff;
+   uint16_t mask;
+
+   if (INTEL_GEN(dev_priv) >= 11)
+   mask = 0x7ff;
+   else
+   mask = 0x3ff;
+   entry->start = reg & mask;
+   entry->end = (reg >> 16) & mask;
+
if (entry->end)
entry->end += 1;
 }
@@ -3894,7 +3902,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private 
*dev_priv,
else
val = I915_READ(CUR_BUF_CFG(pipe));
 
-   skl_ddb_entry_init_from_hw(>plane[pipe][plane_id], 
val);
+   skl_ddb_entry_init_from_hw(dev_priv,
+  >plane[pipe][plane_id],
+  val);
}
 
intel_display_power_put(dev_priv, power_domain);
-- 
2.14.3

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 12/17] drm/i915/icl: track dbuf slice-2 status

[Paulo Zanoni]

From: Mahesh Kumar 

This patch adds support to start tracking status of DBUF slices.
This is foundation to introduce support for enabling/disabling second
DBUF slice dynamically for ICL.

Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/intel_display.c|  5 +
 drivers/gpu/drm/i915/intel_pm.c | 20 
 drivers/gpu/drm/i915/intel_runtime_pm.c |  4 
 4 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cc5ac327f267..eae18661eaec 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1435,6 +1435,7 @@ static inline bool skl_ddb_entry_equal(const struct 
skl_ddb_entry *e1,
 struct skl_ddb_allocation {
struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* 
packed/uv */
struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
+   uint8_t enabled_slices; /* GEN11 has configurable 2 slices */
 };
 
 struct skl_wm_values {
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 0dc4ef6cd46e..bad3b112ac3e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11302,6 +11302,11 @@ static void verify_wm_state(struct drm_crtc *crtc,
skl_ddb_get_hw_state(dev_priv, _ddb);
sw_ddb = _priv->wm.skl_hw.ddb;
 
+   if (INTEL_GEN(dev_priv) >= 11)
+   if (hw_ddb.enabled_slices != sw_ddb->enabled_slices)
+   DRM_ERROR("mismatch in DBUF Slices (expected %u, got 
%u)\n",
+ sw_ddb->enabled_slices,
+ hw_ddb.enabled_slices);
/* planes */
for_each_universal_plane(dev_priv, pipe, plane) {
hw_plane_wm = _wm.planes[plane];
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0237362ccf83..e8d98857c208 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3570,6 +3570,23 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
 }
 
+static uint8_t intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)
+{
+   uint8_t enabled_slices;
+
+   /* Slice 1 will always be enabled */
+   enabled_slices = 1;
+
+   /* Gen prior to GEN11 have only one DBuf slice */
+   if (INTEL_GEN(dev_priv) < 11)
+   return enabled_slices;
+
+   if (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
+   enabled_slices++;
+
+   return enabled_slices;
+}
+
 /*
  * FIXME: We still don't have the proper code detect if we need to apply the 
WA,
  * so assume we'll always need it in order to avoid underruns.
@@ -3828,6 +3845,8 @@ void skl_ddb_get_hw_state(struct drm_i915_private 
*dev_priv,
 
memset(ddb, 0, sizeof(*ddb));
 
+   ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
+
for_each_intel_crtc(_priv->drm, crtc) {
enum intel_display_power_domain power_domain;
enum plane_id plane_id;
@@ -5049,6 +5068,7 @@ skl_copy_wm_for_pipe(struct skl_wm_values *dst,
   sizeof(dst->ddb.y_plane[pipe]));
memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
   sizeof(dst->ddb.plane[pipe]));
+   dst->ddb.enabled_slices = src->ddb.enabled_slices;
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index a6ed01a528bd..13c8dad95b84 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2625,6 +2625,8 @@ static void icl_dbuf_enable(struct drm_i915_private 
*dev_priv)
if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
!(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
DRM_ERROR("DBuf power enable timeout\n");
+   else
+   dev_priv->wm.skl_hw.ddb.enabled_slices = 2;
 }
 
 static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
@@ -2638,6 +2640,8 @@ static void icl_dbuf_disable(struct drm_i915_private 
*dev_priv)
if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
DRM_ERROR("DBuf power disable timeout!\n");
+   else
+   dev_priv->wm.skl_hw.ddb.enabled_slices = 0;
 }
 
 static void icl_mbus_init(struct drm_i915_private *dev_priv)
-- 
2.14.3

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 10/17] drm/i915/icl: initialize MBus during display init

[Paulo Zanoni]

From: Mahesh Kumar 

This patch initializes MBus during display initialization.

Changes since V2 (from Paulo):
 - Don't forget to remove the WARN_ON(1) call.
Changes since V1:
 - Rebase to use function like Macros

Reviewed-by: Paulo Zanoni 
Signed-off-by: Mahesh Kumar 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 14 +-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 7801a425398f..a6ed01a528bd 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2640,6 +2640,18 @@ static void icl_dbuf_disable(struct drm_i915_private 
*dev_priv)
DRM_ERROR("DBuf power disable timeout!\n");
 }
 
+static void icl_mbus_init(struct drm_i915_private *dev_priv)
+{
+   uint32_t val;
+
+   val = MBUS_ABOX_BT_CREDIT_POOL1(16) |
+ MBUS_ABOX_BT_CREDIT_POOL2(16) |
+ MBUS_ABOX_B_CREDIT(1) |
+ MBUS_ABOX_BW_CREDIT(1);
+
+   I915_WRITE(MBUS_ABOX_CTL, val);
+}
+
 static void skl_display_core_init(struct drm_i915_private *dev_priv,
   bool resume)
 {
@@ -2953,7 +2965,7 @@ static void icl_display_core_init(struct drm_i915_private 
*dev_priv,
icl_dbuf_enable(dev_priv);
 
/* 7. Setup MBUS. */
-   /* FIXME: MBUS code not here yet. */
+   icl_mbus_init(dev_priv);
 
/* 8. CHICKEN_DCPR_1 */
I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
-- 
2.14.3

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 11/17] drm/i915/icl: program mbus during pipe enable

[Paulo Zanoni]

From: Mahesh Kumar 

This patch program default values of MBus credit during pipe enable.

Changes since V2:
 - We don't need to do anything when disabling the pipe
Changes Since V1:
 - Add WARN_ON (Paulo)
 - Remove TODO comment
 - Program 0 during pipe disable
 - Rebase

Reviewed-by: Paulo Zanoni 
Signed-off-by: Mahesh Kumar 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_display.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index d585ce4c8732..0dc4ef6cd46e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5380,6 +5380,23 @@ static void glk_pipe_scaler_clock_gating_wa(struct 
drm_i915_private *dev_priv,
I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
 }
 
+static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
+{
+   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+   enum pipe pipe = crtc->pipe;
+   uint32_t val;
+
+   if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0))
+   return;
+
+   val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2);
+
+   /* Program B credit equally to all pipes */
+   val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes);
+
+   I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
+}
+
 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
struct drm_atomic_state *old_state)
 {
@@ -5457,6 +5474,9 @@ static void haswell_crtc_enable(struct intel_crtc_state 
*pipe_config,
if (dev_priv->display.initial_watermarks != NULL)
dev_priv->display.initial_watermarks(old_intel_state, 
pipe_config);
 
+   if (INTEL_GEN(dev_priv) >= 11)
+   icl_pipe_mbus_enable(intel_crtc);
+
/* XXX: Do the pipe assertions at the right place for BXT DSI. */
if (!transcoder_is_dsi(cpu_transcoder))
intel_enable_pipe(pipe_config);
-- 
2.14.3

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 15/17] drm/i915/gen11: fix the SAGV block time for gen11

[Paulo Zanoni]

It's 10us for gen 11.

Reviewed-by: Mahesh Kumar 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_pm.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 84a5b13fdee2..1edd1445ab5b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3711,11 +3711,18 @@ bool intel_can_enable_sagv(struct drm_atomic_state 
*state)
struct intel_crtc_state *cstate;
enum pipe pipe;
int level, latency;
-   int sagv_block_time_us = IS_GEN9(dev_priv) ? 30 : 20;
+   int sagv_block_time_us;
 
if (!intel_has_sagv(dev_priv))
return false;
 
+   if (IS_GEN9(dev_priv))
+   sagv_block_time_us = 30;
+   else if (IS_GEN10(dev_priv))
+   sagv_block_time_us = 20;
+   else
+   sagv_block_time_us = 10;
+
/*
 * SKL+ workaround: bspec recommends we disable the SAGV when we have
 * more then one pipe enabled
-- 
2.14.3

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 04/17] drm/i915/icl: Enable both DBuf slices during init

[Paulo Zanoni]

From: Mahesh Kumar 

ICL has 2 slices of DBuf, enable both the slices during display init.

Ideally we should only enable the second slice when needed in order to
save power, but while we're not there yet, adopt the simpler solution
to keep us bug-free.

v2 (from Paulo):
  - Add the TODO comment.
  - Reorganize where things are defined.
  - Fix indentation.
  - Remove unnecessary POSTING_READ() calls.
  - Improve the commit message.

Signed-off-by: Mahesh Kumar 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_reg.h |  2 ++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 34 +++--
 2 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 979bc06a59f4..1746df9a263d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7122,6 +7122,8 @@ enum {
 #define  DISP_DATA_PARTITION_5_6   (1<<6)
 #define  DISP_IPC_ENABLE   (1<<3)
 #define DBUF_CTL   _MMIO(0x45008)
+#define DBUF_CTL_S1_MMIO(0x45008)
+#define DBUF_CTL_S2_MMIO(0x44FE8)
 #define  DBUF_POWER_REQUEST(1<<31)
 #define  DBUF_POWER_STATE  (1<<30)
 #define GEN7_MSG_CTL   _MMIO(0x45010)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 2556db16c76a..7801a425398f 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2610,6 +2610,36 @@ static void gen9_dbuf_disable(struct drm_i915_private 
*dev_priv)
DRM_ERROR("DBuf power disable timeout!\n");
 }
 
+/*
+ * TODO: we shouldn't always enable DBUF_CTL_S2, we should only enable it when
+ * needed and keep it disabled as much as possible.
+ */
+static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
+{
+   I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST);
+   I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) | DBUF_POWER_REQUEST);
+   POSTING_READ(DBUF_CTL_S2);
+
+   udelay(10);
+
+   if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
+   !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
+   DRM_ERROR("DBuf power enable timeout\n");
+}
+
+static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
+{
+   I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) & ~DBUF_POWER_REQUEST);
+   I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) & ~DBUF_POWER_REQUEST);
+   POSTING_READ(DBUF_CTL_S2);
+
+   udelay(10);
+
+   if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
+   (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
+   DRM_ERROR("DBuf power disable timeout!\n");
+}
+
 static void skl_display_core_init(struct drm_i915_private *dev_priv,
   bool resume)
 {
@@ -2920,7 +2950,7 @@ static void icl_display_core_init(struct drm_i915_private 
*dev_priv,
icl_init_cdclk(dev_priv);
 
/* 6. Enable DBUF. */
-   gen9_dbuf_enable(dev_priv);
+   icl_dbuf_enable(dev_priv);
 
/* 7. Setup MBUS. */
/* FIXME: MBUS code not here yet. */
@@ -2940,7 +2970,7 @@ static void icl_display_core_uninit(struct 
drm_i915_private *dev_priv)
/* 1. Disable all display engine functions -> aready done */
 
/* 2. Disable DBUF */
-   gen9_dbuf_disable(dev_priv);
+   icl_dbuf_disable(dev_priv);
 
/* 3. Disable CD clock */
icl_uninit_cdclk(dev_priv);
-- 
2.14.3

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 07/17] drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed

[Paulo Zanoni]

From: Mahesh Kumar 

ICL require DDB allocation of plane to be more than "minimum display
buffer needed" for each level in order to enable WM level.

This patch implements and consider the same while allocating DDB
and enabling WM.

Changes Since V1:
 - rebase
Changes Since V2:
 - Remove extra parentheses
 - Use FP16.16 only when absolutely necessary (Paulo)
Changes Since V3:
 - Rebase
Changes since v4 (from Paulo)
 - Coding style issue.

Reviewed-by: Paulo Zanoni 
Signed-off-by: Mahesh Kumar 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_pm.c | 30 +-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 44d952a3d9a6..c6d31a5075ad 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4510,6 +4510,7 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
struct intel_atomic_state *state =
to_intel_atomic_state(cstate->base.state);
bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
+   uint32_t min_disp_buf_needed;
 
if (latency == 0 ||
!intel_wm_plane_visible(cstate, intel_pstate)) {
@@ -4568,7 +4569,34 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
}
}
 
-   if (res_blocks >= ddb_allocation || res_lines > 31) {
+   if (INTEL_GEN(dev_priv) >= 11) {
+   if (wp->y_tiled) {
+   uint32_t extra_lines;
+   uint_fixed_16_16_t fp_min_disp_buf_needed;
+
+   if (res_lines % wp->y_min_scanlines == 0)
+   extra_lines = wp->y_min_scanlines;
+   else
+   extra_lines = wp->y_min_scanlines * 2 -
+ res_lines % wp->y_min_scanlines;
+
+   fp_min_disp_buf_needed = mul_u32_fixed16(res_lines +
+   extra_lines,
+   wp->plane_blocks_per_line);
+   min_disp_buf_needed = fixed16_to_u32_round_up(
+   fp_min_disp_buf_needed);
+   } else {
+   min_disp_buf_needed = DIV_ROUND_UP(res_blocks * 11, 10);
+   }
+   } else {
+   /*
+* To enable a WM level ddb_allocation should be
+* greater than result blocks for GEN-9/10.
+*/
+   min_disp_buf_needed = res_blocks + 1;
+   }
+
+   if (min_disp_buf_needed > ddb_allocation || res_lines > 31) {
*enabled = false;
 
/*
-- 
2.14.3

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 06/17] drm/i915/icl: Do not fix dbuf block size to 512

[Paulo Zanoni]

From: Mahesh Kumar 

GEN9/10 had fixed DBuf block size of 512. Dbuf block size is not a
fixed number anymore in GEN11, it varies according to bits per pixel
and tiling. If 8bpp & Yf-tile surface, block size = 256 else block
size = 512

This patch addresses the same.

v2 (from Paulo):
  - Make it compile.
  - Fix a few coding style issues.
v3
  - Rebase on top of upstream patches

Signed-off-by: Mahesh Kumar 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c | 27 ---
 2 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8333692dac5a..cc5ac327f267 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1460,6 +1460,7 @@ struct skl_wm_params {
uint_fixed_16_16_t plane_blocks_per_line;
uint_fixed_16_16_t y_tile_minimum;
uint32_t linetime_us;
+   uint32_t dbuf_block_size;
 };
 
 /*
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 11aac65d1543..44d952a3d9a6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4312,7 +4312,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 */
 static uint_fixed_16_16_t
 skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
-  uint8_t cpp, uint32_t latency)
+  uint8_t cpp, uint32_t latency, uint32_t dbuf_block_size)
 {
uint32_t wm_intermediate_val;
uint_fixed_16_16_t ret;
@@ -4321,7 +4321,7 @@ skl_wm_method1(const struct drm_i915_private *dev_priv, 
uint32_t pixel_rate,
return FP_16_16_MAX;
 
wm_intermediate_val = latency * pixel_rate * cpp;
-   ret = div_fixed16(wm_intermediate_val, 1000 * 512);
+   ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
 
if (INTEL_GEN(dev_priv) >= 10)
ret = add_fixed16_u32(ret, 1);
@@ -4431,6 +4431,15 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
 intel_pstate);
 
+   if (INTEL_GEN(dev_priv) >= 11) {
+   if (fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 8)
+   wp->dbuf_block_size = 256;
+   else
+   wp->dbuf_block_size = 512;
+   } else {
+   wp->dbuf_block_size = 512;
+   }
+
if (drm_rotation_90_or_270(pstate->rotation)) {
 
switch (wp->cpp) {
@@ -4457,7 +4466,8 @@ skl_compute_plane_wm_params(const struct drm_i915_private 
*dev_priv,
wp->plane_bytes_per_line = wp->width * wp->cpp;
if (wp->y_tiled) {
interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *
-  wp->y_min_scanlines, 512);
+  wp->y_min_scanlines,
+  wp->dbuf_block_size);
 
if (INTEL_GEN(dev_priv) >= 10)
interm_pbpl++;
@@ -4465,10 +4475,12 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
wp->y_min_scanlines);
} else if (wp->x_tiled && IS_GEN9(dev_priv)) {
-   interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512);
+   interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
+  wp->dbuf_block_size);
wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
} else {
-   interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512) + 1;
+   interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
+  wp->dbuf_block_size) + 1;
wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
}
 
@@ -4515,7 +4527,7 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
latency += 15;
 
method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
-wp->cpp, latency);
+wp->cpp, latency, wp->dbuf_block_size);
method2 = skl_wm_method2(wp->plane_pixel_rate,
 cstate->base.adjusted_mode.crtc_htotal,
 latency,
@@ -4525,7 +4537,8 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
selected_result = max_fixed16(method2, wp->y_tile_minimum);
} else {
if ((wp->cpp * cstate->base.adjusted_mode.crtc_htotal /
-512 < 1) && (wp->plane_bytes_per_line / 512 < 1))
+

[Intel-gfx] [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values

[Paulo Zanoni]

On ICL we have two sets of registers: one for port A and another for
port B. The set of port A registers is the same as the CNL registers.

Since the procmon table on ICL is the same we want to reuse the CNL
function. To do that we add a port argument and make CNL always call
the function passing port A. This way, we'll be able to easily reuse
the function on ICL when we add icl_display_core_init().

v2: Don't use _PICK() when you can use a ternary operator.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_reg.h | 26 ++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 21 ++---
 2 files changed, 40 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d72e206b2b9f..ebf6261d30fd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2102,6 +2102,32 @@ enum i915_power_well_id {
 #define CNL_PORT_COMP_DW9  _MMIO(0x162124)
 #define CNL_PORT_COMP_DW10 _MMIO(0x162128)
 
+#define _ICL_PORT_COMP_DW0_A   0x162100
+#define _ICL_PORT_COMP_DW0_B   0x6C100
+#define ICL_PORT_COMP_DW0(port)_MMIO((port == PORT_A) ?
\
+ _ICL_PORT_COMP_DW0_A :\
+ _ICL_PORT_COMP_DW0_B)
+#define _ICL_PORT_COMP_DW1_A   0x162104
+#define _ICL_PORT_COMP_DW1_B   0x6C104
+#define ICL_PORT_COMP_DW1(port)_MMIO((port == PORT_A) ?
\
+ _ICL_PORT_COMP_DW1_A :\
+ _ICL_PORT_COMP_DW1_B)
+#define _ICL_PORT_COMP_DW3_A   0x16210C
+#define _ICL_PORT_COMP_DW3_B   0x6C10C
+#define ICL_PORT_COMP_DW3(port)_MMIO((port == PORT_A) ?
\
+ _ICL_PORT_COMP_DW3_A :\
+ _ICL_PORT_COMP_DW3_B)
+#define _ICL_PORT_COMP_DW9_A   0x162124
+#define _ICL_PORT_COMP_DW9_B   0x6C124
+#define ICL_PORT_COMP_DW9(port)_MMIO((port == PORT_A) ?
\
+ _ICL_PORT_COMP_DW9_A :\
+ _ICL_PORT_COMP_DW9_B)
+#define _ICL_PORT_COMP_DW10_A  0x162128
+#define _ICL_PORT_COMP_DW10_B  0x6C128
+#define ICL_PORT_COMP_DW10(port)   _MMIO((port == PORT_A) ?\
+ _ICL_PORT_COMP_DW10_A :   \
+ _ICL_PORT_COMP_DW10_B)
+
 /* BXT PHY Ref registers */
 #define _PORT_REF_DW3_A0x16218C
 #define _PORT_REF_DW3_BC   0x6C18C
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 5b1aa4b9c72c..73dd525d241a 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2758,12 +2758,19 @@ static const struct cnl_procmon {
{ .dw1 = 0x0044, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
 };
 
-static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv)
+/*
+ * CNL has just one set of registers, while ICL has two sets: one for port A 
and
+ * the other for port B. The CNL registers are equivalent to the ICL port A
+ * registers, that's why we call the ICL macros even though the function has 
CNL
+ * on its name.
+ */
+static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
+  enum port port)
 {
const struct cnl_procmon *procmon;
u32 val;
 
-   val = I915_READ(CNL_PORT_COMP_DW3);
+   val = I915_READ(ICL_PORT_COMP_DW3(port));
switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
default:
MISSING_CASE(val);
@@ -2784,13 +2791,13 @@ static void cnl_set_procmon_ref_values(struct 
drm_i915_private *dev_priv)
break;
}
 
-   val = I915_READ(CNL_PORT_COMP_DW1);
+   val = I915_READ(ICL_PORT_COMP_DW1(port));
val &= ~((0xff << 16) | 0xff);
val |= procmon->dw1;
-   I915_WRITE(CNL_PORT_COMP_DW1, val);
+   I915_WRITE(ICL_PORT_COMP_DW1(port), val);
 
-   I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9);
-   I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10);
+   I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);
+   I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
 }
 
 static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool 
resume)
@@ -2811,7 +2818,7 @@ static void cnl_display_core_init(struct drm_i915_private 
*dev_priv, bool resume
val &= ~CNL_COMP_PWR_DOWN;
I915_WRITE(CHICKEN_MISC_2, val);
 
-   cnl_set_procmon_ref_values(dev_priv);
+   cnl_set_procmon_ref_values(dev_priv, PORT_A);
 
val = I915_READ(CNL_PORT_COMP_DW0);
val |= COMP_INIT;
-- 

[Intel-gfx] [PATCH 00/17] ICL display initialization and some plane bits

[Paulo Zanoni]

Hi

Here's another ICL series. This one includes the very basic steps of display
initialization (although missing quite a few pieces) and some patches related to
planes (dbuf, mbus, bit field changes). Nothing special.

Again, as explained in the other series, the R-B tags in these patches were
given to earlier versions, so they need to be re-confirmed since upstream has
moved quite a bit since then.

Thanks,
Paulo

James Ausmus (1):
  drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field

Mahesh Kumar (12):
  drm/i915/icl: Enable both DBuf slices during init
  drm/i915/icl: Don't allocate fixed bypass path blocks for ICL
  drm/i915/icl: Do not fix dbuf block size to 512
  drm/i915/icl: Fail flip if ddb allocated are less than min display
buffer needed
  drm/i915/icl: NV12 y-plane ddb is not in same plane
  drm/i915/icl: Introduce MBus related registers
  drm/i915/icl: initialize MBus during display init
  drm/i915/icl: program mbus during pipe enable
  drm/i915/icl: track dbuf slice-2 status
  drm/i915/icl: Enable 2nd DBuf slice only when needed
  drm/i915/icl: update ddb entry start/end mask during hw ddb readout
  drm/i915/icl: enable SAGV for ICL platform

Paulo Zanoni (4):
  drm/i915/icl: add the main CDCLK functions
  drm/i915/icl: add ICL support to cnl_set_procmon_ref_values
  drm/i915/icl: implement the display init/uninit sequences
  drm/i915/gen11: fix the SAGV block time for gen11

 drivers/gpu/drm/i915/i915_drv.h |   2 +
 drivers/gpu/drm/i915/i915_reg.h |  85 ++-
 drivers/gpu/drm/i915/intel_cdclk.c  | 253 +++-
 drivers/gpu/drm/i915/intel_display.c|  42 +-
 drivers/gpu/drm/i915/intel_drv.h|   8 +
 drivers/gpu/drm/i915/intel_pm.c | 173 ++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 188 ++--
 7 files changed, 706 insertions(+), 45 deletions(-)

-- 
2.14.3

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 01/17] drm/i915/icl: add the main CDCLK functions

[Paulo Zanoni]

This commit adds the basic CDCLK functions, but it's still missing
pieces of the display initialization sequence.

v2:
 - Implement the voltage levels.
 - Rebase.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_reg.h|  10 +-
 drivers/gpu/drm/i915/intel_cdclk.c | 253 -
 drivers/gpu/drm/i915/intel_drv.h   |   2 +
 3 files changed, 261 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index abd9ee876186..d72e206b2b9f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7113,8 +7113,12 @@ enum {
 #define SKL_DFSM_PIPE_B_DISABLE(1 << 21)
 #define SKL_DFSM_PIPE_C_DISABLE(1 << 28)
 
-#define SKL_DSSM   _MMIO(0x51004)
-#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz(1 << 31)
+#define SKL_DSSM   _MMIO(0x51004)
+#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz(1 << 31)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz(0 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz  (1 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz  (2 << 29)
 
 #define GEN7_FF_SLICE_CS_CHICKEN1  _MMIO(0x20e0)
 #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL(1<<14)
@@ -8760,6 +8764,8 @@ enum skl_power_gate {
 #define  BXT_CDCLK_CD2X_PIPE_NONE  BXT_CDCLK_CD2X_PIPE(3)
 #define  BXT_CDCLK_SSA_PRECHARGE_ENABLE(1<<16)
 #define  CDCLK_FREQ_DECIMAL_MASK   (0x7ff)
+#define  ICL_CDCLK_CD2X_PIPE(pipe) ((pipe) << 19)
+#define  ICL_CDCLK_CD2X_PIPE_NONE  ICL_CDCLK_CD2X_PIPE(7)
 
 /* LCPLL_CTL */
 #define LCPLL1_CTL _MMIO(0x46010)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
b/drivers/gpu/drm/i915/intel_cdclk.c
index c4392ea34a3d..d867956d5a9f 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1766,6 +1766,215 @@ static void cnl_sanitize_cdclk(struct drm_i915_private 
*dev_priv)
dev_priv->cdclk.hw.vco = -1;
 }
 
+static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
+{
+   int ranges_24[] = { 312000, 552000, 648000 };
+   int ranges_19_38[] = { 307200, 556800, 652800 };
+   int *ranges;
+
+   switch (ref) {
+   default:
+   MISSING_CASE(ref);
+   case 24000:
+   ranges = ranges_24;
+   break;
+   case 19200:
+   case 38400:
+   ranges = ranges_19_38;
+   break;
+   }
+
+   if (min_cdclk > ranges[1])
+   return ranges[2];
+   else if (min_cdclk > ranges[0])
+   return ranges[1];
+   else
+   return ranges[0];
+}
+
+static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
+{
+   int ratio;
+
+   /* 50MHz == CDCLK PLL disabled. */
+   if (cdclk == 5)
+   return 0;
+
+   switch (cdclk) {
+   default:
+   MISSING_CASE(cdclk);
+   case 307200:
+   case 556800:
+   case 652800:
+   WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
+   dev_priv->cdclk.hw.ref != 38400);
+   break;
+   case 312000:
+   case 552000:
+   case 648000:
+   WARN_ON(dev_priv->cdclk.hw.ref != 24000);
+   }
+
+   ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
+
+   return dev_priv->cdclk.hw.ref * ratio;
+}
+
+static void icl_set_cdclk(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_state *cdclk_state)
+{
+   unsigned int cdclk = cdclk_state->cdclk;
+   unsigned int vco = cdclk_state->vco;
+   int ret;
+   u32 voltage_level;
+
+   mutex_lock(_priv->pcu_lock);
+   ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+   SKL_CDCLK_PREPARE_FOR_CHANGE,
+   SKL_CDCLK_READY_FOR_CHANGE,
+   SKL_CDCLK_READY_FOR_CHANGE, 3);
+   mutex_unlock(_priv->pcu_lock);
+   if (ret) {
+   DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
+ ret);
+   return;
+   }
+
+   /* FIXME: We should also consider the DDI clock here. */
+   switch (cdclk) {
+   case 307200:
+   case 312000:
+   voltage_level = 0;
+   break;
+   case 556800:
+   case 552000:
+   voltage_level = 1;
+   break;
+   default:
+   MISSING_CASE(cdclk);
+   case 652800:
+   case 648000:
+   voltage_level = 2;
+   break;
+   }
+
+   if (dev_priv->cdclk.hw.vco != 0 &&
+   dev_priv->cdclk.hw.vco != vco)
+   cnl_cdclk_pll_disable(dev_priv);
+
+   if (dev_priv->cdclk.hw.vco != vco)
+   cnl_cdclk_pll_enable(dev_priv, vco);
+
+   I915_WRITE(CDCLK_CTL, 

[Intel-gfx] [PATCH 05/17] drm/i915/icl: Don't allocate fixed bypass path blocks for ICL

[Paulo Zanoni]

From: Mahesh Kumar 

GEN9 onwards bypass path allocation of 4 blocks was needed, as per
hardware design. ICL doesn't require bypass path allocation of 4 DDB
blocks, handling the same in this patch.

v2 (from Paulo):
  - No need for a comment that says what the code already says.

Reviewed-by: Paulo Zanoni 
Signed-off-by: Mahesh Kumar 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_pm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0b92ea1dbd40..11aac65d1543 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3778,7 +3778,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
ddb_size = INTEL_INFO(dev_priv)->ddb_size;
WARN_ON(ddb_size == 0);
 
-   ddb_size -= 4; /* 4 blocks for bypass path allocation */
+   if (INTEL_GEN(dev_priv) < 11)
+   ddb_size -= 4; /* 4 blocks for bypass path allocation */
 
/*
 * If the state doesn't change the active CRTC's, then there's
-- 
2.14.3

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 03/17] drm/i915/icl: implement the display init/uninit sequences

[Paulo Zanoni]

This code is similar enough to the CNL code that I considered just
adding ICL support to the CNL function, but I think it's still
different enough, and having a function specific to ICL allows us to
more easily adapt code in case the spec changes more later.

We're still missing the power wells and the mbus code, so leave those
pieces with a FIXME comment while they're not here yet.

v2: Don't use _PICK, don't WARN_ON(1), don't forget the chicken bits.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_reg.h | 16 ++-
 drivers/gpu/drm/i915/intel_runtime_pm.c | 82 -
 2 files changed, 94 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ebf6261d30fd..979bc06a59f4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1904,6 +1904,11 @@ enum i915_power_well_id {
 #define   CL_POWER_DOWN_ENABLE (1 << 4)
 #define   SUS_CLOCK_CONFIG (3 << 0)
 
+#define _ICL_PORT_CL_DW5_A 0x162014
+#define _ICL_PORT_CL_DW5_B 0x6C014
+#define ICL_PORT_CL_DW5(port)  _MMIO((port == PORT_A) ? \
+ _ICL_PORT_CL_DW5_A : _ICL_PORT_CL_DW5_B)
+
 #define _PORT_CL1CM_DW9_A  0x162024
 #define _PORT_CL1CM_DW9_BC 0x6C024
 #define   IREF0RC_OFFSET_SHIFT 8
@@ -7126,8 +7131,9 @@ enum {
 #define  RESET_PCH_HANDSHAKE_ENABLE(1<<4)
 
 #define GEN8_CHICKEN_DCPR_1_MMIO(0x46430)
-#define   SKL_SELECT_ALTERNATE_DC_EXIT (1<<30)
-#define   MASK_WAKEMEM (1<<13)
+#define   SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30)
+#define   MASK_WAKEMEM (1 << 13)
+#define   CNL_DDI_CLOCK_REG_ACCESS_ON  (1 << 7)
 
 #define SKL_DFSM   _MMIO(0x51000)
 #define SKL_DFSM_CDCLK_LIMIT_MASK  (3 << 23)
@@ -9696,4 +9702,10 @@ enum skl_power_gate {
 #define  MMCD_PCLA (1 << 31)
 #define  MMCD_HOTSPOT_EN   (1 << 27)
 
+#define _ICL_PHY_MISC_A0x64C00
+#define _ICL_PHY_MISC_B0x64C04
+#define ICL_PHY_MISC(port) _MMIO((port == PORT_A) ? \
+ _ICL_PHY_MISC_A : _ICL_PHY_MISC_B)
+#define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN  (1 << 23)
+
 #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 73dd525d241a..2556db16c76a 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2882,6 +2882,80 @@ static void cnl_display_core_uninit(struct 
drm_i915_private *dev_priv)
I915_WRITE(CHICKEN_MISC_2, val);
 }
 
+static void icl_display_core_init(struct drm_i915_private *dev_priv,
+ bool resume)
+{
+   enum port port;
+   u32 val;
+
+   gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+
+   /* 1. Enable PCH reset handshake. */
+   val = I915_READ(HSW_NDE_RSTWRN_OPT);
+   val |= RESET_PCH_HANDSHAKE_ENABLE;
+   I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+
+   for (port = PORT_A; port <= PORT_B; port++) {
+   /* 2. Enable DDI combo PHY comp. */
+   val = I915_READ(ICL_PHY_MISC(port));
+   val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
+   I915_WRITE(ICL_PHY_MISC(port), val);
+
+   cnl_set_procmon_ref_values(dev_priv, port);
+
+   val = I915_READ(ICL_PORT_COMP_DW0(port));
+   val |= COMP_INIT;
+   I915_WRITE(ICL_PORT_COMP_DW0(port), val);
+
+   /* 3. Set power down enable. */
+   val = I915_READ(ICL_PORT_CL_DW5(port));
+   val |= CL_POWER_DOWN_ENABLE;
+   I915_WRITE(ICL_PORT_CL_DW5(port), val);
+   }
+
+   /* 4. Enable power well 1 (PG1) and aux IO power. */
+   /* FIXME: ICL power wells code not here yet. */
+
+   /* 5. Enable CDCLK. */
+   icl_init_cdclk(dev_priv);
+
+   /* 6. Enable DBUF. */
+   gen9_dbuf_enable(dev_priv);
+
+   /* 7. Setup MBUS. */
+   /* FIXME: MBUS code not here yet. */
+
+   /* 8. CHICKEN_DCPR_1 */
+   I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
+   CNL_DDI_CLOCK_REG_ACCESS_ON);
+}
+
+static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
+{
+   enum port port;
+   u32 val;
+
+   gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+
+   /* 1. Disable all display engine functions -> aready done */
+
+   /* 2. Disable DBUF */
+   gen9_dbuf_disable(dev_priv);
+
+   /* 3. Disable CD clock */
+   icl_uninit_cdclk(dev_priv);
+
+   /* 4. Disable Power Well 1 (PG1) and Aux IO Power */
+   /* FIXME: ICL power wells code not here yet. */
+
+   /* 5. Disable Comp */
+   for (port = PORT_A; port <= PORT_B; port++) {
+   val = I915_READ(ICL_PHY_MISC(port));
+   val |= 

Re: [Intel-gfx] [igt-dev] [PATCH igt] tests: Add a random load generator

[Antonio Argenziano]

On 21/01/18 12:20, Chris Wilson wrote:

Apply a random load to one or all engines in order to apply stress to
RPS as it tries to constantly adjust the GPU frequency to meet the
changing workload.

Signed-off-by: Chris Wilson 
---
  tests/Makefile.sources |   1 +
  tests/gem_exec_load.c  | 124 +
  2 files changed, 125 insertions(+)
  create mode 100644 tests/gem_exec_load.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 6d3857949..5c6242bca 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -83,6 +83,7 @@ TESTS_progs = \
gem_exec_gttfill \
gem_exec_latency \
gem_exec_lut_handle \
+   gem_exec_load \
gem_exec_nop \
gem_exec_parallel \
gem_exec_params \
diff --git a/tests/gem_exec_load.c b/tests/gem_exec_load.c
new file mode 100644
index 0..d3618f6c0
--- /dev/null
+++ b/tests/gem_exec_load.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include "igt_rand.h"
+#include "igt_sysfs.h"
+
+IGT_TEST_DESCRIPTION("Apply a random load to each engine");
+
+static inline uint32_t randmax(uint32_t *state, uint32_t ep_ro)
+{
+   return (uint64_t)hars_petruska_f54_1_random(state) * ep_ro >> 32;
+}
+
+static void one(int fd, unsigned int engine, int scale, unsigned int timeout)
+{
+   struct timespec tv = {};
+   uint32_t prng = engine;
+   igt_spin_t *spin[2] = {};
+   unsigned int max;
+   int sysfs;
+
+   sysfs = igt_sysfs_open(fd, NULL);
+
+   max = sysfs < 0 ? 1 : igt_sysfs_get_u32(sysfs, "gt_max_freq_mhz");
+
+   do {
+   /*
+* For every second, we randomly assign a desire % busyness
+* and the frequency with which to submit a batch, defining
+* a pulse-width modulation (pwm).
+*/
+   unsigned int pwm = randmax(, 1000);
+   unsigned int load = randmax(, pwm / scale);
+   const unsigned int interval = 1e6 / pwm;
+   unsigned int cur =
+   sysfs < 0 ? 1 : igt_sysfs_get_u32(sysfs, 
"gt_cur_freq_mhz");
+
+   while (pwm--) {
+   if (randmax(, pwm * cur) <= load * max) {
+   spin[1] = __igt_spin_batch_new(fd, 0, engine, 
0);
+   load--;
+   }
+   igt_spin_batch_free(fd, spin[0]);
+   spin[0] = spin[1];
+   spin[1] = NULL;
+
+   usleep(interval);
+   }
+   } while (igt_seconds_elapsed() < timeout);


Why not igt_until_timeout()?

-Antonio
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Use enum plane_id for frontbuffer tracking

[Patchwork]

== Series Details ==

Series: drm/i915: Use enum plane_id for frontbuffer tracking
URL   : https://patchwork.freedesktop.org/series/36991/
State : success

== Summary ==

Series 36991v1 drm/i915: Use enum plane_id for frontbuffer tracking
https://patchwork.freedesktop.org/api/1.0/series/36991/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
dmesg-fail -> DMESG-WARN (fi-elk-e7500) fdo#103989
pass   -> DMESG-WARN (fi-bdw-gvtdvm) fdo#103938 +1

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#103938 https://bugs.freedesktop.org/show_bug.cgi?id=103938

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:422s
fi-bdw-gvtdvmtotal:288  pass:262  dwarn:2   dfail:0   fail:0   skip:24  
time:425s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:370s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:482s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:280s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:477s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:487s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:470s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:458s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:277s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:510s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:389s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:405s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:410s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:463s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:417s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:469s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:500s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:451s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:501s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:586s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:440s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:509s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:528s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:493s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:484s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:416s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:518s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:394s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:566s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:469s
fi-skl-gvtdvm failed to collect. IGT log at Patchwork_7755/fi-skl-gvtdvm/igt.log

5e022f5f329c7909cb9aa938364072329f694fb2 drm-tip: 2018y-01m-23d-17h-29m-20s UTC 
integration manifest
923110da5f60 drm/i915: Use enum plane_id for frontbuffer tracking

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7755/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/pmu: Fix sysfs exported counter config

[Patchwork]

== Series Details ==

Series: drm/i915/pmu: Fix sysfs exported counter config
URL   : https://patchwork.freedesktop.org/series/36973/
State : success

== Summary ==

Test drv_suspend:
Subgroup fence-restore-untiled-hibernate:
fail   -> SKIP   (shard-snb) fdo#103375
Test kms_vblank:
Subgroup query-busy:
skip   -> PASS   (shard-snb)
Subgroup query-forked-busy:
skip   -> PASS   (shard-snb)
Test kms_busy:
Subgroup extended-pageflip-hang-newfb-render-b:
skip   -> PASS   (shard-snb)
Test kms_sysfs_edid_timing:
warn   -> PASS   (shard-apl) fdo#100047
Test kms_flip:
Subgroup vblank-vs-dpms-suspend:
incomplete -> PASS   (shard-hsw) fdo#103540 +1

fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540

shard-apltotal:2753 pass:1717 dwarn:1   dfail:0   fail:22  skip:1013 
time:13978s
shard-hswtotal:2753 pass:1724 dwarn:1   dfail:0   fail:12  skip:1015 
time:15481s
shard-snbtotal:2753 pass:1319 dwarn:1   dfail:0   fail:9   skip:1424 
time:7933s
Blacklisted hosts:
shard-kbltotal:2753 pass:1839 dwarn:1   dfail:1   fail:24  skip:888 
time:10997s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7751/shards.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Inhibit context save/restore for the fake preempt context

[Michel Thierry]

On 1/23/2018 9:05 AM, Chris Wilson wrote:

We only use the preempt context to inject an idle point into execlists.
We never need to reference its logical state, so tell the GPU never to
load it or save it.

Suggested-by: Daniele Ceraolo Spurio 
Signed-off-by: Chris Wilson 
Cc: Michal Winiarski 
Cc: Michel Thierry 
Cc: Michal Wajdeczko 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
---
Please check the register definition. I know the save-inhibit bit used
to exist, I don't know if it is BIT(1) in RING_CONTEXT_CONTROL -- it
feels like it should be, and the numbers indicate that it does
something beneficial.


Hi,


-Chris
---
  drivers/gpu/drm/i915/intel_lrc.c | 4 
  drivers/gpu/drm/i915/intel_lrc.h | 1 +
  2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 22d471a4228d..c28f267a8417 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2285,6 +2285,10 @@ populate_lr_context(struct i915_gem_context *ctx,
if (!engine->default_state)
regs[CTX_CONTEXT_CONTROL + 1] |=
_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
+   if (ctx->hw_id == PREEMPT_ID)
+   regs[CTX_CONTEXT_CONTROL + 1] |=
+   _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
+  CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT);
  
  	i915_gem_object_unpin_map(ctx_obj);
  
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h

index 6d4f9b995a11..e6e2c1774600 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -36,6 +36,7 @@
  #define RING_CONTEXT_CONTROL(engine)  _MMIO((engine)->mmio_base + 
0x244)
  #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH   (1 << 3)
  #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT   (1 << 0)
+#define  CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT  (1 << 1)
  #define   CTX_CTRL_RS_CTX_ENABLE(1 << 1)


BIT(0) is Engine Context Restore Inhibit,
BIT(1) is Resource Streamer Context Enable (in RCS), and
BIT(2) is Context Save Inhibit.



  #define RING_CONTEXT_STATUS_BUF_BASE(engine)  _MMIO((engine)->mmio_base + 
0x370)
  #define RING_CONTEXT_STATUS_BUF_LO(engine, i) _MMIO((engine)->mmio_base + 
0x370 + (i) * 8)


___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Add AUX-F support

[Runyan, Arthur J]

Good question.  We forgot that one.  It's 0x162A90.

-Original Message-
From: Vivi, Rodrigo 
Sent: Tuesday, 23 January, 2018 8:30 AM
To: Pandiyan, Dhinakaran 
Cc: intel-gfx@lists.freedesktop.org; De Marchi, Lucas 
; Runyan, Arthur J 
Subject: Re: [Intel-gfx] [PATCH] drm/i915/cnl: Add AUX-F support

On Tue, Jan 23, 2018 at 04:53:55AM +, Pandiyan, Dhinakaran wrote:
> 
> On Tue, 2018-01-23 at 02:43 +, Pandiyan, Dhinakaran wrote:
> > 
> > 
> > On Mon, 2018-01-22 at 15:59 -0800, Rodrigo Vivi wrote:
> > > On some Cannonlake SKUs we have a dedicated Aux for port F,
> > > that is only the full split between port A and port E.
> > > 
> > > There is still no Aux E for Port E, as in previous platforms,
> > > because port_E still means shared lanes with port A.
> > > 
> 
> 
> Lucas,
> 
> 
> Should "drm/i915/cnl: apply Display WA #1178 to fix type C dongles" be
> extended to AUX F ?
> 

This is a very good question. Art?
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm/i915: Use enum plane_id for frontbuffer tracking

[Ville Syrjala]

From: Ville Syrjälä 

Replace the ad-hoc plane indexing scheme used by the frontbuffer
tracking with enum plane_id.

The old video overlay not being part of the plane_id namespace
will just be given the high bit.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_drv.h  | 11 +++
 drivers/gpu/drm/i915/intel_display.c |  4 ++--
 drivers/gpu/drm/i915/intel_fbc.c |  2 +-
 drivers/gpu/drm/i915/intel_sprite.c  |  4 +++-
 4 files changed, 9 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8333692dac5a..bd545b1c9546 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2404,16 +2404,11 @@ enum hdmi_force_audio {
  *
  * We have one bit per pipe and per scanout plane type.
  */
-#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
-#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
-   (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
-#define INTEL_FRONTBUFFER_CURSOR(pipe) \
-   (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe
-#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
-   (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe
+#define INTEL_FRONTBUFFER(pipe, plane_id) \
+   (1 << ((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
-   (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + 
(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe
+   (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + 
INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
 
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index d585ce4c8732..3cc35add362f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13168,7 +13168,7 @@ intel_primary_plane_create(struct drm_i915_private 
*dev_priv, enum pipe pipe)
else
primary->i9xx_plane = (enum i9xx_plane_id) pipe;
primary->id = PLANE_PRIMARY;
-   primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
+   primary->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, primary->id);
primary->check_plane = intel_check_primary_plane;
 
if (INTEL_GEN(dev_priv) >= 9) {
@@ -13289,7 +13289,7 @@ intel_cursor_plane_create(struct drm_i915_private 
*dev_priv,
cursor->pipe = pipe;
cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
cursor->id = PLANE_CURSOR;
-   cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
+   cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
 
if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
cursor->update_plane = i845_update_cursor;
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 9dc2b8b5f2db..a8a8a80497a8 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -1373,7 +1373,7 @@ void intel_fbc_init(struct drm_i915_private *dev_priv)
 
for_each_pipe(dev_priv, pipe) {
fbc->possible_framebuffer_bits |=
-   INTEL_FRONTBUFFER_PRIMARY(pipe);
+   INTEL_FRONTBUFFER(pipe, PLANE_PRIMARY);
 
if (fbc_on_pipe_a_only(dev_priv))
break;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index a92c748ca8ab..18ef0392362e 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -345,6 +345,8 @@ skl_plane_get_hw_state(struct intel_plane *plane)
return ret;
 }
 
+
+
 static void
 chv_update_csc(struct intel_plane *plane, uint32_t format)
 {
@@ -1427,7 +1429,7 @@ intel_sprite_plane_create(struct drm_i915_private 
*dev_priv,
intel_plane->pipe = pipe;
intel_plane->i9xx_plane = plane;
intel_plane->id = PLANE_SPRITE0 + plane;
-   intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
+   intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, intel_plane->id);
intel_plane->check_plane = intel_check_sprite_plane;
 
possible_crtcs = (1 << pipe);
-- 
2.13.6

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnp: Ignore VBT request for know invalid DDC pin.

[Patchwork]

== Series Details ==

Series: drm/i915/cnp: Ignore VBT request for know invalid DDC pin.
URL   : https://patchwork.freedesktop.org/series/36988/
State : success

== Summary ==

Series 36988v1 drm/i915/cnp: Ignore VBT request for know invalid DDC pin.
https://patchwork.freedesktop.org/api/1.0/series/36988/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
dmesg-fail -> DMESG-WARN (fi-elk-e7500) fdo#103989 +2
Test gem_ringfill:
Subgroup basic-default-hang:
dmesg-warn -> PASS   (fi-pnv-d510) fdo#101600

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:419s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:426s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:373s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:492s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:281s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:489s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:486s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:466s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:462s
fi-elk-e7500 total:229  pass:172  dwarn:10  dfail:0   fail:0   skip:46 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:280s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:511s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:390s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:401s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:412s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:449s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:416s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:456s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:496s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:451s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:500s
fi-pnv-d510  total:288  pass:223  dwarn:0   dfail:0   fail:0   skip:65  
time:563s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:429s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:507s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:527s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:492s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:485s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:416s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:530s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:397s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:568s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:472s

5e022f5f329c7909cb9aa938364072329f694fb2 drm-tip: 2018y-01m-23d-17h-29m-20s UTC 
integration manifest
e8a94473f3e0 drm/i915/cnp: Ignore VBT request for know invalid DDC pin.

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7754/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm/i915/cnp: Ignore VBT request for know invalid DDC pin.

[Rodrigo Vivi]

Let's ignore VBT request if the pin is clearly wrong.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104139
Cc: Kai Heng Feng 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_bios.c | 11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index b0668202dc7e..95f0b310d656 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1115,9 +1115,14 @@ static const u8 cnp_ddc_pin_map[] = {
 
 static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
 {
-   if (HAS_PCH_CNP(dev_priv) &&
-   vbt_pin > 0 && vbt_pin < ARRAY_SIZE(cnp_ddc_pin_map))
-   return cnp_ddc_pin_map[vbt_pin];
+   if (HAS_PCH_CNP(dev_priv)) {
+   if (vbt_pin > 0 && vbt_pin < ARRAY_SIZE(cnp_ddc_pin_map))
+   return cnp_ddc_pin_map[vbt_pin];
+   if (vbt_pin > GMBUS_PIN_4_CNP) {
+   DRM_DEBUG_KMS("Ignoring alternate pin: VBT claims DDC 
pin %d, which is not valid for this platform\n", vbt_pin);
+   return 0;
+   }
+   }
 
return vbt_pin;
 }
-- 
2.13.6

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Inhibit context save/restore for the fake preempt context

[Patchwork]

== Series Details ==

Series: drm/i915/execlists: Inhibit context save/restore for the fake preempt 
context
URL   : https://patchwork.freedesktop.org/series/36984/
State : success

== Summary ==

Series 36984v1 drm/i915/execlists: Inhibit context save/restore for the fake 
preempt context
https://patchwork.freedesktop.org/api/1.0/series/36984/revisions/1/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:423s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:425s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:371s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:486s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:280s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:483s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:484s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:471s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:454s
fi-elk-e7500 total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:279s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:513s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:390s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:400s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:410s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:457s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:411s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:455s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:499s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:451s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:502s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:580s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:430s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:513s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:528s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:484s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:475s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:415s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:430s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:401s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:573s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:470s

8fd56cdd15ca72f60bd2af50c786e4c386258c73 drm-tip: 2018y-01m-23d-16h-08m-56s UTC 
integration manifest
9297ea19f525 drm/i915/execlists: Inhibit context save/restore for the fake 
preempt context

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7753/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm/i915/execlists: Inhibit context save/restore for the fake preempt context

[Chris Wilson]

We only use the preempt context to inject an idle point into execlists.
We never need to reference its logical state, so tell the GPU never to
load it or save it.

Suggested-by: Daniele Ceraolo Spurio 
Signed-off-by: Chris Wilson 
Cc: Michal Winiarski 
Cc: Michel Thierry 
Cc: Michal Wajdeczko 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
---
Please check the register definition. I know the save-inhibit bit used
to exist, I don't know if it is BIT(1) in RING_CONTEXT_CONTROL -- it
feels like it should be, and the numbers indicate that it does
something beneficial.
-Chris
---
 drivers/gpu/drm/i915/intel_lrc.c | 4 
 drivers/gpu/drm/i915/intel_lrc.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 22d471a4228d..c28f267a8417 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2285,6 +2285,10 @@ populate_lr_context(struct i915_gem_context *ctx,
if (!engine->default_state)
regs[CTX_CONTEXT_CONTROL + 1] |=
_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
+   if (ctx->hw_id == PREEMPT_ID)
+   regs[CTX_CONTEXT_CONTROL + 1] |=
+   _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
+  CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT);
 
i915_gem_object_unpin_map(ctx_obj);
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 6d4f9b995a11..e6e2c1774600 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -36,6 +36,7 @@
 #define RING_CONTEXT_CONTROL(engine)   _MMIO((engine)->mmio_base + 
0x244)
 #define  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH   (1 << 3)
 #define  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT   (1 << 0)
+#define  CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT  (1 << 1)
 #define   CTX_CTRL_RS_CTX_ENABLE(1 << 1)
 #define RING_CONTEXT_STATUS_BUF_BASE(engine)   _MMIO((engine)->mmio_base + 
0x370)
 #define RING_CONTEXT_STATUS_BUF_LO(engine, i)  _MMIO((engine)->mmio_base + 
0x370 + (i) * 8)
-- 
2.15.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/guc: Fix lockdep due to log relay channel handling under struct_mutex

[Chris Wilson]

Quoting Michal Wajdeczko (2018-01-23 16:44:33)
> On Tue, 23 Jan 2018 16:42:17 +0100, Sagar Arun Kamble  
> > @@ -605,7 +681,11 @@ int i915_guc_log_control(struct drm_i915_private  
> > *dev_priv, u64 control_val)
> >   }
> >   /* GuC logging is currently the only user of Guc2Host 
> > interrupts */
> > + mutex_lock(_priv->drm.struct_mutex);
> > + intel_runtime_pm_get(dev_priv);
> >   gen9_enable_guc_interrupts(dev_priv);
> > + intel_runtime_pm_put(dev_priv);
> > + mutex_unlock(_priv->drm.struct_mutex);
> 
> Maybe pm_get/lock/xxx/unlock/pm_put would be better order ?

There's no strong reason to prefer one nesting or the other. So pick a
pattern for guc_interrupts and stick to it :)
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/guc: Fix lockdep due to log relay channel handling under struct_mutex

[Michal Wajdeczko]

On Tue, 23 Jan 2018 16:42:17 +0100, Sagar Arun Kamble  
 wrote:



This patch fixes lockdep issue due to circular locking dependency of
struct_mutex, i_mutex_key, mmap_sem, relay_channels_mutex.
For GuC log relay channel we create debugfs file that requires  
i_mutex_key

lock and we are doing that under struct_mutex. So we introduced newer
dependency as:
>struct_mutex --> >s_type->i_mutex_key#3 --> >mmap_sem
However, there is dependency from mmap_sem to struct_mutex. Hence we
separate the relay create/destroy operation from under struct_mutex.



... 

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c  
b/drivers/gpu/drm/i915/i915_debugfs.c

index 80dc679..b45be0d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2467,7 +2467,6 @@ static int i915_guc_log_control_get(void *data,  
u64 *val)

 static int i915_guc_log_control_set(void *data, u64 val)
 {
struct drm_i915_private *dev_priv = data;
-   int ret;
if (!HAS_GUC(dev_priv))
return -ENODEV;
@@ -2475,16 +2474,7 @@ static int i915_guc_log_control_set(void *data,  
u64 val)

if (!dev_priv->guc.log.vma)
return -EINVAL;
-   ret = mutex_lock_interruptible(_priv->drm.struct_mutex);
-   if (ret)
-   return ret;
-
-   intel_runtime_pm_get(dev_priv);
-   ret = i915_guc_log_control(dev_priv, val);
-   intel_runtime_pm_put(dev_priv);
-
-   mutex_unlock(_priv->drm.struct_mutex);
-   return ret;
+   return i915_guc_log_control(dev_priv, val);


I hope that one day we change signature of this function to

int intel_guc_log_control(struct intel_guc *guc, u64 control);

... 

diff --git a/drivers/gpu/drm/i915/intel_guc.c  
b/drivers/gpu/drm/i915/intel_guc.c

index ea30e7c..cab3c98 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -66,6 +66,7 @@ void intel_guc_init_early(struct intel_guc *guc)
intel_guc_ct_init_early(>ct);
mutex_init(>send_mutex);
+   mutex_init(>log.runtime.relay_lock);


Maybe this can be done in intel_guc_loc.c (or .h) as

void intel_guc_log_init_early() { }


guc->send = intel_guc_send_nop;
guc->notify = gen8_guc_raise_irq;
 }
@@ -87,8 +88,10 @@ int intel_guc_init_wq(struct intel_guc *guc)
 */
guc->log.runtime.flush_wq = alloc_ordered_workqueue("i915-guc_log",
WQ_HIGHPRI | WQ_FREEZABLE);
-   if (!guc->log.runtime.flush_wq)
+   if (!guc->log.runtime.flush_wq) {
+   DRM_ERROR("Couldn't allocate workqueue for GuC log\n");
return -ENOMEM;
+   }
/*
 * Even though both sending GuC action, and adding a new workitem to
@@ -109,6 +112,8 @@ int intel_guc_init_wq(struct intel_guc *guc)
  WQ_HIGHPRI);
if (!guc->preempt_wq) {
destroy_workqueue(guc->log.runtime.flush_wq);
+   DRM_ERROR("Couldn't allocate workqueue for GuC "
+ "preemption\n");
return -ENOMEM;
}
}


... 



static void capture_logs_work(struct work_struct *work)
@@ -363,12 +377,12 @@ static int guc_log_runtime_create(struct intel_guc  
*guc)

 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
void *vaddr;
-   struct rchan *guc_log_relay_chan;
-   size_t n_subbufs, subbuf_size;
int ret;
lockdep_assert_held(_priv->drm.struct_mutex);
+   GEM_BUG_ON(!guc_log_has_relay(guc));
+


Do we need this line?


GEM_BUG_ON(guc_log_has_runtime(guc));
ret = i915_gem_object_set_to_wc_domain(guc->log.vma->obj, true);
@@ -387,8 +401,40 @@ static int guc_log_runtime_create(struct intel_guc  
*guc)

guc->log.runtime.buf_addr = vaddr;
+   INIT_WORK(>log.runtime.flush_work, capture_logs_work);


I'm not sure about other BKMs, but I prefer to not delay such  
initialization

and perform them in functions like init_early


+
+   return 0;
+}
+
+static void guc_log_runtime_destroy(struct intel_guc *guc)
+{
+   /*
+* It's possible that the runtime stuff was never allocated because
+* GuC log was disabled at the boot time.
+**/


Is this correct comment style ?


+   if (!guc_log_has_runtime(guc))
+   return;
+
+   i915_gem_object_unpin_map(guc->log.vma->obj);
+   guc->log.runtime.buf_addr = NULL;
+}
+


... 

@@ -605,7 +681,11 @@ int i915_guc_log_control(struct drm_i915_private  
*dev_priv, u64 control_val)

}
/* GuC logging is currently the only user of Guc2Host 
interrupts */
+   mutex_lock(_priv->drm.struct_mutex);
+   intel_runtime_pm_get(dev_priv);
gen9_enable_guc_interrupts(dev_priv);
+   intel_runtime_pm_put(dev_priv);
+   

Re: [Intel-gfx] [PATCH v2 4/4] Revert "drm/i915/guc: Keep GuC log disabled by default"

[Sagar Arun Kamble]

On 1/23/2018 9:36 PM, Michal Wajdeczko wrote:
On Tue, 23 Jan 2018 16:42:20 +0100, Sagar Arun Kamble 
 wrote:



Comment DRM_ERROR_RATELIMIT outputs as log capturer won't be
running.

This reverts commit bd724318b682587ad2f989ab8e0f7b3d4486ced5.
---
 drivers/gpu/drm/i915/i915_params.h   | 2 +-
 drivers/gpu/drm/i915/intel_guc_log.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h

index 430f5f9..c963603 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -48,7 +48,7 @@
 param(int, enable_ips, 1) \
 param(int, invert_brightness, 0) \
 param(int, enable_guc, 0) \
-    param(int, guc_log_level, 0) \
+    param(int, guc_log_level, -1) \


If this is HAX for CI then OK, but otherwise maybe we
should leave log disabled(0) to match disabled(0) GuC ;)

Then in the future we can change both to auto(-1)


Yes. This is HAX. Missed tag in this rev.

 param(char *, guc_firmware_path, NULL) \
 param(char *, huc_firmware_path, NULL) \
 param(int, mmio_debug, 0) \
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c

index be9f2ca..7604451 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -238,7 +238,7 @@ static bool guc_check_log_buf_overflow(struct 
intel_guc *guc,

 /* buffer_full_cnt is a 4 bit counter */
 guc->log.total_overflow_count[type] += 16;
 }
-    DRM_ERROR_RATELIMITED("GuC log buffer overflow\n");
+    //DRM_ERROR_RATELIMITED("GuC log buffer overflow\n");


I'm not sure that we should leave dead code
And using C++ style comments is not good too
(unless this patch is just a HAX)


 }
return overflow;
@@ -354,7 +354,7 @@ static void guc_read_update_log_buffer(struct 
intel_guc *guc)

 /* Used rate limited to avoid deluge of messages, logs might be
  * getting consumed by User at a slow rate.
  */
-    DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n");
+    //DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n");
 guc->log.capture_miss_count++;
 }
 mutex_unlock(>log.runtime.relay_lock);


--
Thanks,
Sagar

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Add AUX-F support

[Rodrigo Vivi]

On Tue, Jan 23, 2018 at 04:53:55AM +, Pandiyan, Dhinakaran wrote:
> 
> On Tue, 2018-01-23 at 02:43 +, Pandiyan, Dhinakaran wrote:
> > 
> > 
> > On Mon, 2018-01-22 at 15:59 -0800, Rodrigo Vivi wrote:
> > > On some Cannonlake SKUs we have a dedicated Aux for port F,
> > > that is only the full split between port A and port E.
> > > 
> > > There is still no Aux E for Port E, as in previous platforms,
> > > because port_E still means shared lanes with port A.
> > > 
> 
> 
> Lucas,
> 
> 
> Should "drm/i915/cnl: apply Display WA #1178 to fix type C dongles" be
> extended to AUX F ?
> 

This is a very good question. Art?
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 08/10] drm/i915/cnl: Enable DDI-F on Cannonlake.

[Rodrigo Vivi]

On Tue, Jan 23, 2018 at 03:12:52AM +, Pandiyan, Dhinakaran wrote:
> 
> 
> 
> On Fri, 2018-01-19 at 16:05 -0800, Rodrigo Vivi wrote:
> > Now let's finish the Port-F support by adding the
> > proper port F detection, irq and power well support.
> > 
> > v2: Rebase
> > v3: Use BIT_ULL
> > v4: Cover missed case on ddi init.
> > v5: Update commit message.
> > v6: Rebase on top of display headers rework.
> > 
> > Cc: Manasi Navare 
> > Cc: Ville Syrjälä 
> > Signed-off-by: Rodrigo Vivi 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h |  2 ++
> >  drivers/gpu/drm/i915/intel_ddi.c|  4 
> >  drivers/gpu/drm/i915/intel_display.c|  6 +-
> >  drivers/gpu/drm/i915/intel_display.h|  2 ++
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 13 +
> >  5 files changed, 26 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 861a7d5a27af..32ec64eb2c5a 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1304,6 +1304,7 @@ enum i915_power_well_id {
> > SKL_DISP_PW_DDI_B,
> > SKL_DISP_PW_DDI_C,
> > SKL_DISP_PW_DDI_D,
> 
> This looks suspicious, why isn't there a DDI_E here for CNL? I see that
> bit 10 and 11 correspond to CNL port E in the spec.

because spec likes being contradictory ;)

There is no port E on CNL.
SKUs without port F has only ports A to D.
SKU with full port split has ports A to D and F.

> 
> > +   CNL_DISP_PW_DDI_F = 6,
> >  
> > GLK_DISP_PW_AUX_A = 8,
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v2] drm/i915: Move LRC register offsets to a header file

[Chris Wilson]

Quoting Lucas De Marchi (2018-01-23 16:06:16)
> On Tue, Jan 23, 2018 at 08:48:01AM +, Chris Wilson wrote:
> > Quoting Michel Thierry (2018-01-23 00:41:07)
> > > On 1/22/2018 4:31 PM, Lucas De Marchi wrote:
> > > > So for this file what I understand is that it should be:
> > > > 
> > > >   // SPDX-License-Identifier: MIT
> > > >   // Copyright (C) 2014-2018 Intel Corporation
> > > 
> > > So be it.
> > 
> > Oh no, we don't do C++ comments.
> 
> We drm or we kernel devs?
> 
> $ git grep "// SPDX"| wc -l 
> 4487
> 
> The suggestion was actually from Linus in the thread I linked. Quoting
> here:
> 
> > So in general, the _hope_ is that we can just end up replacing
> > existing boilerplate comments with that single line SPDX comment
> > (using "//" in *.[ch] files, but obviously some other kinds of files
> > end up having a different comment character, typically '#').
> ...
> > And yes, feel free to replace block comments with // while at it.
> ...
> > We already have something like 700 different versions of the same
> > silly copyright license boiler-plate due to typos, whitespace
> > differences, comment style choices, yadda yadda. Let's avoid that mess
> > by just picking _one_ single format and placement for the SPDX line.
> 
> Which I agree with, hence my suggestion. Let me know if it should be
> different in drm/

Being consistent is far more important.
Documentation/process/coding-style.rst is what we follow, breaking the
rule and being inconsistent for copyright headers doesn't make any sense.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Don't try to manage Port F power wells on all CNL.

[Rodrigo Vivi]

On Tue, Jan 23, 2018 at 03:03:28AM +, Pandiyan, Dhinakaran wrote:
> 
> 
> 
> On Mon, 2018-01-22 at 15:48 -0800, Rodrigo Vivi wrote:
> > SKUs that lacks on the full port F split will just time out
> > when touching this power well bits, causing a noisy warn.
> > 
> > v2: Suggested-by: Imre. Temporarily remove the aux pw id after setting
> > it instead of duplicating and redefining everything.
> > 
> > Cc: Lucas De Marchi 
> > Cc: Imre Deak 
> > Signed-off-by: Rodrigo Vivi 
> > ---
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 25 +++--
> >  1 file changed, 19 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 433048ffa5c6..7cee63860a7b 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -1861,18 +1861,20 @@ void intel_display_power_put(struct 
> > drm_i915_private *dev_priv,
> >  #define CNL_DISPLAY_AUX_D_POWER_DOMAINS (  \
> > BIT_ULL(POWER_DOMAIN_AUX_D) |   \
> > BIT_ULL(POWER_DOMAIN_INIT))
> > -#define CNL_DISPLAY_AUX_F_POWER_DOMAINS (  \
> > -   BIT_ULL(POWER_DOMAIN_AUX_F) |   \
> > -   BIT_ULL(POWER_DOMAIN_INIT))
> > -#define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS (   \
> > -   BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) |   \
> > -   BIT_ULL(POWER_DOMAIN_INIT))
> >  #define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> > BIT_ULL(POWER_DOMAIN_GT_IRQ) |  \
> > BIT_ULL(POWER_DOMAIN_MODESET) | \
> > BIT_ULL(POWER_DOMAIN_AUX_A) |   \
> > BIT_ULL(POWER_DOMAIN_INIT))
> > +/* Power wells for CNL with port F after this */
> > +#define CNL_FIRST_PORT_F_PW CNL_DISP_PW_AUX_F
> > +#define CNL_DISPLAY_AUX_F_POWER_DOMAINS (  \
> > +   BIT_ULL(POWER_DOMAIN_AUX_F) |   \
> > +   BIT_ULL(POWER_DOMAIN_INIT))
> > +#define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS (   \
> > +   BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) |   \
> > +   BIT_ULL(POWER_DOMAIN_INIT))
> >  
> >  static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> > .sync_hw = i9xx_power_well_sync_hw_noop,
> > @@ -2544,6 +2546,17 @@ int intel_power_domains_init(struct drm_i915_private 
> > *dev_priv)
> > set_power_wells(power_domains, skl_power_wells);
> > } else if (IS_CANNONLAKE(dev_priv)) {
> > set_power_wells(power_domains, cnl_power_wells);
> > +
> > +   if (!IS_CNL_WITH_PORT_F(dev_priv)) {
> > +   int i;
> > +
> > +   for (i = 0; i < power_domains->power_well_count; i++)
> > +   if (power_domains->power_wells[i].id ==
> > +   CNL_FIRST_PORT_F_PW)
> > +   break;
> > +   WARN_ON(power_domains->power_well_count == i - 1);
> > +   power_domains->power_well_count = i - 1;
> Shouldn't this be
>   WARN_ON(power_domains->power_well_count == i);

oh yeap... c from below without thinking. :/

>   power_domains->power_well_count = i; ?

this is also what Imre suggested, but I don't think so.

The first-of-non-port-f - 1 is the last of non-port-f.

> 
>
> > +   }
> > } else if (IS_BROXTON(dev_priv)) {
> > set_power_wells(power_domains, bxt_power_wells);
> > } else if (IS_GEMINILAKE(dev_priv)) {
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v2] drm/i915: Move LRC register offsets to a header file

[Lucas De Marchi]

On Tue, Jan 23, 2018 at 05:18:36PM +0100, Michal Wajdeczko wrote:
> On Tue, 23 Jan 2018 17:06:16 +0100, Lucas De Marchi
>  wrote:
> 
> > On Tue, Jan 23, 2018 at 08:48:01AM +, Chris Wilson wrote:
> > > Quoting Michel Thierry (2018-01-23 00:41:07)
> > > > On 1/22/2018 4:31 PM, Lucas De Marchi wrote:
> > > > > So for this file what I understand is that it should be:
> > > > >
> > > > >   // SPDX-License-Identifier: MIT
> > > > >   // Copyright (C) 2014-2018 Intel Corporation
> > > >
> > > > So be it.
> > > 
> > > Oh no, we don't do C++ comments.
> > 
> > We drm or we kernel devs?
> > 
> > $ git grep "// SPDX"| wc -l
> > 4487
> > 
> 
> But on the other hand:
> 
> $ git grep "/* SPDX" | wc -l
> 14087

Yes, because initially during the conversion it was thought // couldn't
be in headers, but in the end it was actually a build system bug.

Lucas De Marchi
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v2] drm/i915: Move LRC register offsets to a header file

[Michal Wajdeczko]

On Tue, 23 Jan 2018 17:06:16 +0100, Lucas De Marchi  
 wrote:



On Tue, Jan 23, 2018 at 08:48:01AM +, Chris Wilson wrote:

Quoting Michel Thierry (2018-01-23 00:41:07)
> On 1/22/2018 4:31 PM, Lucas De Marchi wrote:
> > So for this file what I understand is that it should be:
> >
> >   // SPDX-License-Identifier: MIT
> >   // Copyright (C) 2014-2018 Intel Corporation
>
> So be it.

Oh no, we don't do C++ comments.


We drm or we kernel devs?

$ git grep "// SPDX"| wc -l
4487



But on the other hand:

$ git grep "/* SPDX" | wc -l
14087


The suggestion was actually from Linus in the thread I linked. Quoting
here:


So in general, the _hope_ is that we can just end up replacing
existing boilerplate comments with that single line SPDX comment
(using "//" in *.[ch] files, but obviously some other kinds of files
end up having a different comment character, typically '#').

...

And yes, feel free to replace block comments with // while at it.

...

We already have something like 700 different versions of the same
silly copyright license boiler-plate due to typos, whitespace
differences, comment style choices, yadda yadda. Let's avoid that mess
by just picking _one_ single format and placement for the SPDX line.


Which I agree with, hence my suggestion. Let me know if it should be
different in drm/


Lucas De Marchi
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 00/15] drm: More plane clipping polish

[Ville Syrjälä]

On Thu, Nov 23, 2017 at 09:04:47PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> This series first unifies all users of drm_atomic_helper_check_plane_state()
> to populate the clip rectangle with drm_mode_get_hv_timing(), and once
> everything is unified the clip rectangle handling is sucked into
> drm_atomic_helper_check_plane_state() away from driver code.
> 
> Entire series available here:
> git://github.com/vsyrjala/linux.git atomic_plane_helper_clip
> 
> Cc: Archit Taneja 
> Cc: Ben Skeggs 
> Cc: Brian Starkey 
> Cc: CK Hu 
> Cc: Daniel Vetter 
> Cc: freedr...@lists.freedesktop.org
> Cc: Laurent Pinchart 
> Cc: linux-amlo...@lists.infradead.org
> Cc: linux-arm-...@vger.kernel.org
> Cc: linux-te...@vger.kernel.org
> Cc: Liviu Dudau 
> Cc: Mali DP Maintainers 
> Cc: Mark Yao 
> Cc: Neil Armstrong 
> Cc: Noralf Trønnes 
> Cc: nouv...@lists.freedesktop.org
> Cc: Philipp Zabel 
> Cc: Rob Clark 
> Cc: Shawn Guo 
> Cc: Sinclair Yeh 
> Cc: Thierry Reding 
> Cc: Thomas Hellstrom 
> Cc: VMware Graphics 
> 
> Ville Syrjälä (15):
>   drm/i915: Reject odd pipe source width with double wide/dual link
>   drm/i915: Use drm_mode_get_hv_timing() to populate plane clip
> rectangle
>   drm/arm/hdlcd: Use drm_mode_get_hv_timing() to populate plane clip
> rectangle
>   drm/arm/mali-dp: Use drm_mode_get_hv_timing() to populate plane clip
> rectangle
>   drm/simple_kms_helper: Use drm_mode_get_hv_timing() to populate plane
> clip rectangle
>   drm/imx: Use drm_mode_get_hv_timing() to populate plane clip rectangle
>   drm/mediatek: Use drm_mode_get_hv_timing() to populate plane clip
> rectangle
>   drm/meson: Use drm_mode_get_hv_timing() to populate plane clip
> rectangle
>   drm/msm/mdp5: Use drm_mode_get_hv_timing() to populate plane clip
> rectangle
>   drm/nouveau/kms/nv50: Use drm_mode_get_hv_timing() to populate plane
> clip rectangle
>   drm/rockchip: Use drm_mode_get_hv_timing() to populate plane clip
> rectangle
>   drm/tegra/dc: Use drm_mode_get_hv_timing() to populate plane clip
> rectangle
>   drm/vmwgfx: Use drm_mode_get_hv_timing() to populate plane clip
> rectangle
>   drm/zte: Use drm_mode_get_hv_timing() to populate plane clip rectangle

Everything up to here pushed to drm-misc-next. Thanks for the reviews.

There have been a few new users of the clip helper so I'll have to
take care of those and respin the final patch.

Also armada looks broken to me since it has started to use the
atomic version of the helper without actually being an atomic
driver. So I'll have to figure out what's going on there as well.

>   drm: Don't pass clip to drm_atomic_helper_check_plane_state()
> 
>  drivers/gpu/drm/arm/hdlcd_crtc.c|  6 +-
>  drivers/gpu/drm/arm/malidp_planes.c |  5 +
>  drivers/gpu/drm/armada/armada_overlay.c |  2 +-
>  drivers/gpu/drm/drm_atomic_helper.c | 12 +++-
>  drivers/gpu/drm/drm_plane_helper.c  | 11 +++
>  drivers/gpu/drm/drm_simple_kms_helper.c |  5 -
>  drivers/gpu/drm/i915/intel_atomic_plane.c   |  8 
>  drivers/gpu/drm/i915/intel_display.c| 12 +++-
>  drivers/gpu/drm/i915/intel_drv.h|  1 -
>  drivers/gpu/drm/i915/intel_sprite.c |  8 ++--
>  drivers/gpu/drm/imx/ipuv3-plane.c   |  7 +--
>  drivers/gpu/drm/mediatek/mtk_drm_plane.c|  6 +-
>  drivers/gpu/drm/meson/meson_plane.c |  6 +-
>  drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c   | 14 ++
>  drivers/gpu/drm/nouveau/nv50_display.c  |  8 
>  drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  8 +---
>  drivers/gpu/drm/tegra/dc.c  |  8 +---
>  drivers/gpu/drm/vmwgfx/vmwgfx_kms.c |  8 +---
>  drivers/gpu/drm/zte/zx_plane.c  | 15 +--
>  include/drm/drm_atomic_helper.h |  1 -
>  include/drm/drm_plane_helper.h  |  1 -
>  21 files changed, 35 insertions(+), 117 deletions(-)
> 
> -- 
> 2.13.6

-- 
Ville Syrjälä
Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Add AUX-F support

[Lucas De Marchi]

On Tue, Jan 23, 2018 at 02:53:55AM -0200, Pandiyan, Dhinakaran wrote:
> 
> On Tue, 2018-01-23 at 02:43 +, Pandiyan, Dhinakaran wrote:
> > 
> > 
> > On Mon, 2018-01-22 at 15:59 -0800, Rodrigo Vivi wrote:
> > > On some Cannonlake SKUs we have a dedicated Aux for port F,
> > > that is only the full split between port A and port E.
> > > 
> > > There is still no Aux E for Port E, as in previous platforms,
> > > because port_E still means shared lanes with port A.
> > > 
> 
> 
> Lucas,
> 
> 
> Should "drm/i915/cnl: apply Display WA #1178 to fix type C dongles" be
> extended to AUX F ?

No, on CNL it only applies to AUX B-D according to w/a
documentation (and since it doesn't apply to AUX A, I don't think it's
something missing there).

Lucas De Marchi
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v2 4/4] Revert "drm/i915/guc: Keep GuC log disabled by default"

[Michal Wajdeczko]

On Tue, 23 Jan 2018 16:42:20 +0100, Sagar Arun Kamble  
 wrote:



Comment DRM_ERROR_RATELIMIT outputs as log capturer won't be
running.

This reverts commit bd724318b682587ad2f989ab8e0f7b3d4486ced5.
---
 drivers/gpu/drm/i915/i915_params.h   | 2 +-
 drivers/gpu/drm/i915/intel_guc_log.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h  
b/drivers/gpu/drm/i915/i915_params.h

index 430f5f9..c963603 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -48,7 +48,7 @@
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
param(int, enable_guc, 0) \
-   param(int, guc_log_level, 0) \
+   param(int, guc_log_level, -1) \


If this is HAX for CI then OK, but otherwise maybe we
should leave log disabled(0) to match disabled(0) GuC ;)

Then in the future we can change both to auto(-1)


param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
param(int, mmio_debug, 0) \
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c  
b/drivers/gpu/drm/i915/intel_guc_log.c

index be9f2ca..7604451 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -238,7 +238,7 @@ static bool guc_check_log_buf_overflow(struct  
intel_guc *guc,

/* buffer_full_cnt is a 4 bit counter */
guc->log.total_overflow_count[type] += 16;
}
-   DRM_ERROR_RATELIMITED("GuC log buffer overflow\n");
+   //DRM_ERROR_RATELIMITED("GuC log buffer overflow\n");


I'm not sure that we should leave dead code
And using C++ style comments is not good too
(unless this patch is just a HAX)


}
return overflow;
@@ -354,7 +354,7 @@ static void guc_read_update_log_buffer(struct  
intel_guc *guc)

/* Used rate limited to avoid deluge of messages, logs might be
 * getting consumed by User at a slow rate.
 */
-   DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n");
+   //DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n");
guc->log.capture_miss_count++;
}
mutex_unlock(>log.runtime.relay_lock);

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v2] drm/i915: Move LRC register offsets to a header file

[Lucas De Marchi]

On Tue, Jan 23, 2018 at 08:48:01AM +, Chris Wilson wrote:
> Quoting Michel Thierry (2018-01-23 00:41:07)
> > On 1/22/2018 4:31 PM, Lucas De Marchi wrote:
> > > So for this file what I understand is that it should be:
> > > 
> > >   // SPDX-License-Identifier: MIT
> > >   // Copyright (C) 2014-2018 Intel Corporation
> > 
> > So be it.
> 
> Oh no, we don't do C++ comments.

We drm or we kernel devs?

$ git grep "// SPDX"| wc -l 
4487

The suggestion was actually from Linus in the thread I linked. Quoting
here:

> So in general, the _hope_ is that we can just end up replacing
> existing boilerplate comments with that single line SPDX comment
> (using "//" in *.[ch] files, but obviously some other kinds of files
> end up having a different comment character, typically '#').
...
> And yes, feel free to replace block comments with // while at it.
...
> We already have something like 700 different versions of the same
> silly copyright license boiler-plate due to typos, whitespace
> differences, comment style choices, yadda yadda. Let's avoid that mess
> by just picking _one_ single format and placement for the SPDX line.

Which I agree with, hence my suggestion. Let me know if it should be
different in drm/


Lucas De Marchi
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [v2,1/4] drm/i915/guc: Fix lockdep due to log relay channel handling under struct_mutex

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/4] drm/i915/guc: Fix lockdep due to log 
relay channel handling under struct_mutex
URL   : https://patchwork.freedesktop.org/series/36980/
State : warning

== Summary ==

Series 36980v1 series starting with [v2,1/4] drm/i915/guc: Fix lockdep due to 
log relay channel handling under struct_mutex
https://patchwork.freedesktop.org/api/1.0/series/36980/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
dmesg-fail -> PASS   (fi-elk-e7500) fdo#103989 +2
Test drv_module_reload:
Subgroup basic-reload:
pass   -> DMESG-WARN (fi-skl-guc)
Subgroup basic-no-display:
pass   -> DMESG-WARN (fi-skl-guc)
Subgroup basic-reload-inject:
pass   -> DMESG-WARN (fi-skl-guc)

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:421s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:429s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:380s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:494s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:282s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:487s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:489s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:474s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:455s
fi-elk-e7500 total:224  pass:169  dwarn:9   dfail:0   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:284s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:516s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:394s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:400s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:415s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:448s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:412s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:462s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:498s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:502s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:584s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:428s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:509s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:529s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:494s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:491s
fi-skl-guc   total:288  pass:257  dwarn:3   dfail:0   fail:0   skip:28  
time:420s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:432s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:527s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:403s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:577s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:475s

cbdcbeb1eb0965d3b9afc88561e9da7e11ce1d82 drm-tip: 2018y-01m-23d-13h-00m-40s UTC 
integration manifest
a6ff60a6b193 Revert "drm/i915/guc: Keep GuC log disabled by default"
5a10169f1ca1 drm/i915/guc: Enable interrupts before resuming GuC during runtime 
resume
aaf3f3a257bf drm/i915/guc: Grab RPM wakelock while disabling GuC interrupts
95958514665d drm/i915/guc: Fix lockdep due to log relay channel handling under 
struct_mutex

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7752/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v2 2/4] drm/i915/guc: Grab RPM wakelock while disabling GuC interrupts

[Chris Wilson]

Quoting Sagar Arun Kamble (2018-01-23 15:42:18)
> Disabling GuC interrupts involves access to GuC IRQ control registers
> hence ensure device is RPM awake.
> 
> v2: Add comment about need to synchronize flush work and log runtime
> destroy
> 
> v3: Moved patch earlier in the series and removed comment about future
> work. (Tvrtko)
> 
> v4-v5: Rebase.
> 
> v6: Added assert_rpm_wakelock_held() to gen9_*_guc_interrupts. (Chris)
> 
> Signed-off-by: Sagar Arun Kamble 
> Cc: Michal Wajdeczko 
> Cc: Daniele Ceraolo Spurio 
> Cc: Tvrtko Ursulin 
> Cc: Chris Wilson 
> Cc: Joonas Lahtinen 

Looks self-consistent, so let's hope it doesn't generate any warnings ;)
Reviewed-by: Chris Wilson 
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/guc: Fix lockdep due to log relay channel handling under struct_mutex

[Chris Wilson]

Quoting Sagar Arun Kamble (2018-01-23 15:42:17)
>  static void *guc_get_write_buffer(struct intel_guc *guc)
>  {
> -   if (!guc->log.runtime.relay_chan)
> +   if (!guc_log_has_relay(guc))
> return NULL;
>  
> /* Just get the base address of a new sub buffer and copy data into it
> @@ -266,7 +276,9 @@ static void guc_read_update_log_buffer(struct intel_guc 
> *guc)
> log_buf_state = src_data = guc->log.runtime.buf_addr;
>  
> /* Get the pointer to local buffer to store the logs */
> +   mutex_lock(>log.runtime.relay_lock);
> log_buf_snapshot_state = dst_data = guc_get_write_buffer(guc);
> +   mutex_unlock(>log.runtime.relay_lock);

Since dst_data/log_buf_snapshot_state are pointing into the relay_chan
they are only valid underneath the relay_lock (we don't have any
references or whatnot).

> /* Actual logs are present from the 2nd page */
> src_data += PAGE_SIZE;
> @@ -335,6 +347,7 @@ static void guc_read_update_log_buffer(struct intel_guc 
> *guc)
> dst_data += buffer_size;
> }
>  
> +   mutex_lock(>log.runtime.relay_lock);
> if (log_buf_snapshot_state)
> guc_move_to_next_buf(guc);
> else {
> @@ -344,6 +357,7 @@ static void guc_read_update_log_buffer(struct intel_guc 
> *guc)
> DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n");
> guc->log.capture_miss_count++;
> }
> +   mutex_unlock(>log.runtime.relay_lock);

I.e. it's no good just reacquiring the lock as the state may have
perished in between.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v2 1/4] drm/i915/guc: Fix lockdep due to log relay channel handling under struct_mutex

[Sagar Arun Kamble]

This patch fixes lockdep issue due to circular locking dependency of
struct_mutex, i_mutex_key, mmap_sem, relay_channels_mutex.
For GuC log relay channel we create debugfs file that requires i_mutex_key
lock and we are doing that under struct_mutex. So we introduced newer
dependency as:
>struct_mutex --> >s_type->i_mutex_key#3 --> >mmap_sem
However, there is dependency from mmap_sem to struct_mutex. Hence we
separate the relay create/destroy operation from under struct_mutex.

==
WARNING: possible circular locking dependency detected
4.15.0-rc6-CI-Patchwork_7614+ #1 Not tainted
--
debugfs_test/1388 is trying to acquire lock:
 (>struct_mutex){+.+.}, at: [] 
i915_mutex_lock_interruptible+0x47/0x130 [i915]

but task is already holding lock:
 (>mmap_sem){}, at: [<29a9c131>] __do_page_fault+0x106/0x560

which lock already depends on the new lock.

the existing dependency chain (in reverse order) is:

-> #3 (>mmap_sem){}:
   _copy_to_user+0x1e/0x70
   filldir+0x8c/0xf0
   dcache_readdir+0xeb/0x160
   iterate_dir+0xdc/0x140
   SyS_getdents+0xa0/0x130
   entry_SYSCALL_64_fastpath+0x1c/0x89

-> #2 (>s_type->i_mutex_key#3){}:
   start_creating+0x59/0x110
   __debugfs_create_file+0x2e/0xe0
   relay_create_buf_file+0x62/0x80
   relay_late_setup_files+0x84/0x250
   guc_log_late_setup+0x4f/0x110 [i915]
   i915_guc_log_register+0x32/0x40 [i915]
   i915_driver_load+0x7b6/0x1720 [i915]
   i915_pci_probe+0x2e/0x90 [i915]
   pci_device_probe+0x9c/0x120
   driver_probe_device+0x2a3/0x480
   __driver_attach+0xd9/0xe0
   bus_for_each_dev+0x57/0x90
   bus_add_driver+0x168/0x260
   driver_register+0x52/0xc0
   do_one_initcall+0x39/0x150
   do_init_module+0x56/0x1ef
   load_module+0x231c/0x2d70
   SyS_finit_module+0xa5/0xe0
   entry_SYSCALL_64_fastpath+0x1c/0x89

-> #1 (relay_channels_mutex){+.+.}:
   relay_open+0x12c/0x2b0
   intel_guc_log_runtime_create+0xab/0x230 [i915]
   intel_guc_init+0x81/0x120 [i915]
   intel_uc_init+0x29/0xa0 [i915]
   i915_gem_init+0x182/0x530 [i915]
   i915_driver_load+0xaa9/0x1720 [i915]
   i915_pci_probe+0x2e/0x90 [i915]
   pci_device_probe+0x9c/0x120
   driver_probe_device+0x2a3/0x480
   __driver_attach+0xd9/0xe0
   bus_for_each_dev+0x57/0x90
   bus_add_driver+0x168/0x260
   driver_register+0x52/0xc0
   do_one_initcall+0x39/0x150
   do_init_module+0x56/0x1ef
   load_module+0x231c/0x2d70
   SyS_finit_module+0xa5/0xe0
   entry_SYSCALL_64_fastpath+0x1c/0x89

-> #0 (>struct_mutex){+.+.}:
   __mutex_lock+0x81/0x9b0
   i915_mutex_lock_interruptible+0x47/0x130 [i915]
   i915_gem_fault+0x201/0x790 [i915]
   __do_fault+0x15/0x70
   __handle_mm_fault+0x677/0xdc0
   handle_mm_fault+0x14f/0x2f0
   __do_page_fault+0x2d1/0x560
   page_fault+0x4c/0x60

other info that might help us debug this:

Chain exists of:
  >struct_mutex --> >s_type->i_mutex_key#3 --> >mmap_sem

 Possible unsafe locking scenario:

   CPU0CPU1
   
  lock(>mmap_sem);
   lock(>s_type->i_mutex_key#3);
   lock(>mmap_sem);
  lock(>struct_mutex);

 *** DEADLOCK ***

1 lock held by debugfs_test/1388:
 #0:  (>mmap_sem){}, at: [<29a9c131>] 
__do_page_fault+0x106/0x560

stack backtrace:
CPU: 2 PID: 1388 Comm: debugfs_test Not tainted 4.15.0-rc6-CI-Patchwork_7614+ #1
Hardware name: To Be Filled By O.E.M. To Be Filled By O.E.M./J4205-ITX, BIOS 
P1.10 09/29/2016
Call Trace:
 dump_stack+0x5f/0x86
 print_circular_bug.isra.18+0x1d0/0x2c0
 __lock_acquire+0x14ae/0x1b60
 ? lock_acquire+0xaf/0x200
 lock_acquire+0xaf/0x200
 ? i915_mutex_lock_interruptible+0x47/0x130 [i915]
 __mutex_lock+0x81/0x9b0
 ? i915_mutex_lock_interruptible+0x47/0x130 [i915]
 ? i915_mutex_lock_interruptible+0x47/0x130 [i915]
 ? i915_mutex_lock_interruptible+0x47/0x130 [i915]
 i915_mutex_lock_interruptible+0x47/0x130 [i915]
 ? __pm_runtime_resume+0x4f/0x80
 i915_gem_fault+0x201/0x790 [i915]
 __do_fault+0x15/0x70
 ? _raw_spin_unlock+0x29/0x40
 __handle_mm_fault+0x677/0xdc0
 handle_mm_fault+0x14f/0x2f0
 __do_page_fault+0x2d1/0x560
 ? page_fault+0x36/0x60
 page_fault+0x4c/0x60

v2: Added lock protection to guc->log.runtime.relay_chan (Chris)
Fixed locking inside guc_flush_logs uncovered by new lockdep.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104693
Testcase: igt/debugfs_test/read_all_entries # with enable_guc=1 and 
guc_log_level=1
Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 

[Intel-gfx] [PATCH v2 3/4] drm/i915/guc: Enable interrupts before resuming GuC during runtime resume

[Sagar Arun Kamble]

GuC log streaming needs interrupts enabled prior to GuC resume but
runtime pm interrupt setup was happening post GuC resume. Fix it.
While at it, fix the unwinding of steps in the runtime suspend path.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104695
Signed-off-by: Sagar Arun Kamble 
Cc: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Cc: Joonas Lahtinen 
Cc: Marta Lofstedt 
Reviewed-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.c | 13 +
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 29048b9..1ec12ad 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2600,6 +2600,11 @@ static int intel_runtime_suspend(struct device *kdev)
 
intel_runtime_pm_enable_interrupts(dev_priv);
 
+   intel_guc_resume(dev_priv);
+
+   i915_gem_init_swizzling(dev_priv);
+   i915_gem_restore_fences(dev_priv);
+
enable_rpm_wakeref_asserts(dev_priv);
 
return ret;
@@ -2665,8 +2670,6 @@ static int intel_runtime_resume(struct device *kdev)
if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
 
-   intel_guc_resume(dev_priv);
-
if (IS_GEN9_LP(dev_priv)) {
bxt_disable_dc9(dev_priv);
bxt_display_core_init(dev_priv, true);
@@ -2681,6 +2684,10 @@ static int intel_runtime_resume(struct device *kdev)
 
intel_uncore_runtime_resume(dev_priv);
 
+   intel_runtime_pm_enable_interrupts(dev_priv);
+
+   intel_guc_resume(dev_priv);
+
/*
 * No point of rolling back things in case of an error, as the best
 * we can do is to hope that things will still work (and disable RPM).
@@ -2688,8 +2695,6 @@ static int intel_runtime_resume(struct device *kdev)
i915_gem_init_swizzling(dev_priv);
i915_gem_restore_fences(dev_priv);
 
-   intel_runtime_pm_enable_interrupts(dev_priv);
-
/*
 * On VLV/CHV display interrupts are part of the display
 * power well, so hpd is reinitialized from there. For
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v2 2/4] drm/i915/guc: Grab RPM wakelock while disabling GuC interrupts

[Sagar Arun Kamble]

Disabling GuC interrupts involves access to GuC IRQ control registers
hence ensure device is RPM awake.

v2: Add comment about need to synchronize flush work and log runtime
destroy

v3: Moved patch earlier in the series and removed comment about future
work. (Tvrtko)

v4-v5: Rebase.

v6: Added assert_rpm_wakelock_held() to gen9_*_guc_interrupts. (Chris)

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_irq.c  | 6 ++
 drivers/gpu/drm/i915/intel_guc_log.c | 3 +++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3517c65..85c46a2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -452,6 +452,8 @@ void gen6_disable_rps_interrupts(struct drm_i915_private 
*dev_priv)
 
 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
 {
+   assert_rpm_wakelock_held(dev_priv);
+
spin_lock_irq(_priv->irq_lock);
gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
spin_unlock_irq(_priv->irq_lock);
@@ -459,6 +461,8 @@ void gen9_reset_guc_interrupts(struct drm_i915_private 
*dev_priv)
 
 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
 {
+   assert_rpm_wakelock_held(dev_priv);
+
spin_lock_irq(_priv->irq_lock);
if (!dev_priv->guc.interrupts_enabled) {
WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
@@ -471,6 +475,8 @@ void gen9_enable_guc_interrupts(struct drm_i915_private 
*dev_priv)
 
 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
 {
+   assert_rpm_wakelock_held(dev_priv);
+
spin_lock_irq(_priv->irq_lock);
dev_priv->guc.interrupts_enabled = false;
 
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 573d96d..be9f2ca 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -719,7 +719,10 @@ void i915_guc_log_unregister(struct drm_i915_private 
*dev_priv)
 
mutex_lock(_priv->drm.struct_mutex);
/* GuC logging is currently the only user of Guc2Host interrupts */
+   intel_runtime_pm_get(dev_priv);
gen9_disable_guc_interrupts(dev_priv);
+   intel_runtime_pm_put(dev_priv);
+
guc_log_runtime_destroy(guc);
mutex_unlock(_priv->drm.struct_mutex);
 
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v2 4/4] Revert "drm/i915/guc: Keep GuC log disabled by default"

[Sagar Arun Kamble]

Comment DRM_ERROR_RATELIMIT outputs as log capturer won't be
running.

This reverts commit bd724318b682587ad2f989ab8e0f7b3d4486ced5.
---
 drivers/gpu/drm/i915/i915_params.h   | 2 +-
 drivers/gpu/drm/i915/intel_guc_log.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 430f5f9..c963603 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -48,7 +48,7 @@
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
param(int, enable_guc, 0) \
-   param(int, guc_log_level, 0) \
+   param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
param(int, mmio_debug, 0) \
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index be9f2ca..7604451 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -238,7 +238,7 @@ static bool guc_check_log_buf_overflow(struct intel_guc 
*guc,
/* buffer_full_cnt is a 4 bit counter */
guc->log.total_overflow_count[type] += 16;
}
-   DRM_ERROR_RATELIMITED("GuC log buffer overflow\n");
+   //DRM_ERROR_RATELIMITED("GuC log buffer overflow\n");
}
 
return overflow;
@@ -354,7 +354,7 @@ static void guc_read_update_log_buffer(struct intel_guc 
*guc)
/* Used rate limited to avoid deluge of messages, logs might be
 * getting consumed by User at a slow rate.
 */
-   DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n");
+   //DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n");
guc->log.capture_miss_count++;
}
mutex_unlock(>log.runtime.relay_lock);
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/2] drm/dp: Add HBR3 support in existing DRM DP helpers

[Harry Wentland]

On 2018-01-22 05:43 PM, Manasi Navare wrote:
> Existing helpers add support upto HBR2. This patch
> adds support for HBR3 rate (8.1 Gbps) introduced as
> part of DP 1.4 specification.
> 
> Cc: Rodrigo Vivi 
> Cc: Jani Nikula 
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Manasi Navare 

Both patches look right according to DP 1.4 spec.

Series is
Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/drm_dp_helper.c   | 4 
>  drivers/gpu/drm/drm_dp_mst_topology.c | 3 +++
>  include/drm/drm_dp_helper.h   | 1 +
>  3 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index adf79be..ffe14ec 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -146,6 +146,8 @@ u8 drm_dp_link_rate_to_bw_code(int link_rate)
>   return DP_LINK_BW_2_7;
>   case 54:
>   return DP_LINK_BW_5_4;
> + case 81:
> + return DP_LINK_BW_8_1;
>   }
>  }
>  EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
> @@ -161,6 +163,8 @@ int drm_dp_bw_code_to_link_rate(u8 link_bw)
>   return 27;
>   case DP_LINK_BW_5_4:
>   return 54;
> + case DP_LINK_BW_8_1:
> + return 81;
>   }
>  }
>  EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index 70dcfa5..36df7df 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -2087,6 +2087,9 @@ static bool drm_dp_get_vc_payload_bw(int dp_link_bw,
>   case DP_LINK_BW_5_4:
>   *out = 10 * dp_link_count;
>   break;
> + case DP_LINK_BW_8_1:
> + *out = 15 * dp_link_count;
> + break;
>   }
>   return true;
>  }
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 9d3ce3b..c80fa92 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -334,6 +334,7 @@
>  # define DP_LINK_BW_1_62 0x06
>  # define DP_LINK_BW_2_7  0x0a
>  # define DP_LINK_BW_5_4  0x14/* 1.2 */
> +# define DP_LINK_BW_8_1  0x1e/* 1.4 */
>  
>  #define DP_LANE_COUNT_SET0x101
>  # define DP_LANE_COUNT_MASK  0x0f
> 
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v11 5/6] drm/i915: add query uAPI

[Lionel Landwerlin]

Hi all,

I've been trying to expose some information to userspace about the fused 
parts of the GPU.
This is the 4th attempt at getting this upstream, here are the previous 
ones :

    https://patchwork.freedesktop.org/patch/185959/
    https://patchwork.freedesktop.org/series/33436/
    https://patchwork.freedesktop.org/series/33950/

This last iteration was based upon some direction by Daniel : 
https://lists.freedesktop.org/archives/dri-devel/2017-December/160162.html
There was, I think, a fair point about having this working in 
environments where sysfs (mechanism used in the 3rd iteration) is not 
available (containers).


Following some discussion on IRC, it seems Joonas would like this 
rewritten in a such way that we essentially drop the generic mechanism 
introduced in this patch, and instead go for an additional ioctl() on 
the drm fd just for querying the state of a fused part of 
slice/subslice/eus.

The proposal is to have a single struct like :

struct drm_i915_topology {
   /* All field are in/out */
   int slice;
   int subslice;
   int eu;

   int enabled;
};

You would let the slice field to -1 and then the kernel would fill it 
with the max slice value. Same for subslice (with a valid slice value) 
and eu.
When querying with slice = 0, and all other fields to -1, the kernel 
would fill the enabled value with 0 or 1.
Essentially that would mean that an application wanting to query the 
state of all of the EUs would have to go through them one by one (which 
would be about ~100 ioctl() on SKL GT4 for example).


Apart from the fact that we'll probably end up adding another ioctl() 
for engine discovery, I don't have any problem with what Joonas is 
proposing.

It's just a bit annoying this comes up on the 4th rewrite.
I really wouldn't like to rewrite this one more time and get turned down 
because this isn't to the taste of one of the reviewer.

So my question is : Is everybody happy with what Joonas is proposing?
Anybody in favor of having a generic mechanism?

Thanks a lot,

-
Lionel



On 22/01/18 08:21, Lionel Landwerlin wrote:

There are a number of information that are readable from hardware
registers and that we would like to make accessible to userspace. One
particular example is the topology of the execution units (how are
execution units grouped in subslices and slices and also which ones
have been fused off for die recovery).

At the moment the GET_PARAM ioctl covers some basic needs, but
generally is only able to return a single value for each defined
parameter. This is a bit problematic with topology descriptions which
are array/maps of available units.

This change introduces a new ioctl that can deal with requests to fill
structures of potentially variable lengths. The user is expected fill
a query with length fields set at 0 on the first call, the kernel then
sets the length fields to the their expected values. A second call to
the kernel with length fields at their expected values will trigger a
copy of the data to the pointed memory locations.

The scope of this uAPI is only to provide information to userspace,
not to allow configuration of the device.

v2: Simplify dispatcher code iteration (Tvrtko)
 Tweak uapi drm_i915_query_item structure (Tvrtko)

v3: Rename pad fields into flags (Chris)
 Return error on flags field != 0 (Chris)
 Only copy length back to userspace in drm_i915_query_item (Chris)

v4: Use array of functions instead of switch (Chris)

v5: More comments in uapi (Tvrtko)
 Return query item errors in length field (All)

v6: Tweak uapi comments style to match the coding style (Lionel)

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tvrtko Ursulin 
---
  drivers/gpu/drm/i915/Makefile |  1 +
  drivers/gpu/drm/i915/i915_drv.c   |  1 +
  drivers/gpu/drm/i915/i915_drv.h   |  3 ++
  drivers/gpu/drm/i915/i915_query.c | 67 +++
  include/uapi/drm/i915_drm.h   | 41 
  5 files changed, 113 insertions(+)
  create mode 100644 drivers/gpu/drm/i915/i915_query.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3bddd8a06806..b0415a3e2d59 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -69,6 +69,7 @@ i915-y += i915_cmd_parser.o \
  i915_gem_timeline.o \
  i915_gem_userptr.o \
  i915_gemfs.o \
+ i915_query.o \
  i915_trace_points.o \
  i915_vma.o \
  intel_breadcrumbs.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6d34bc1a7fff..c59be22f19ab 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2830,6 +2830,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, 
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Fix sysfs exported counter config

[Patchwork]

== Series Details ==

Series: drm/i915/pmu: Fix sysfs exported counter config
URL   : https://patchwork.freedesktop.org/series/36973/
State : success

== Summary ==

Series 36973v1 drm/i915/pmu: Fix sysfs exported counter config
https://patchwork.freedesktop.org/api/1.0/series/36973/revisions/1/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:424s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:431s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:374s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:496s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:284s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:492s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:486s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:484s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:461s
fi-elk-e7500 total:224  pass:168  dwarn:9   dfail:1   fail:0   skip:45 
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:283s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:515s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:392s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:408s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:416s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:455s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:420s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:461s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:496s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:504s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:587s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:433s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:509s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:534s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:500s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:486s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:418s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:430s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:403s
Blacklisted hosts:
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:572s
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:472s

cbdcbeb1eb0965d3b9afc88561e9da7e11ce1d82 drm-tip: 2018y-01m-23d-13h-00m-40s UTC 
integration manifest
f8d5cc44137d drm/i915/pmu: Fix sysfs exported counter config

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7751/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx