[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [01/10] drm/vblank: Data type fixes for 64-bit vblank sequences.

[Patchwork]

== Series Details ==

Series: series starting with [01/10] drm/vblank: Data type fixes for 64-bit 
vblank sequences.
URL   : https://patchwork.freedesktop.org/series/37598/
State : warning

== Summary ==

Series 37598v1 series starting with [01/10] drm/vblank: Data type fixes for 
64-bit vblank sequences.
https://patchwork.freedesktop.org/api/1.0/series/37598/revisions/1/mbox/

Test gem_sync:
Subgroup basic-all:
pass   -> SKIP   (fi-blb-e6850)
Subgroup basic-each:
pass   -> SKIP   (fi-blb-e6850)
Subgroup basic-many-each:
pass   -> SKIP   (fi-blb-e6850)
Subgroup basic-store-all:
pass   -> SKIP   (fi-blb-e6850)
Subgroup basic-store-each:
pass   -> SKIP   (fi-blb-e6850)
Test gem_tiled_blits:
Subgroup basic:
pass   -> SKIP   (fi-blb-e6850)
Test gem_tiled_fence_blits:
Subgroup basic:
pass   -> SKIP   (fi-blb-e6850)
Test gem_wait:
Subgroup basic-busy-all:
pass   -> SKIP   (fi-blb-e6850)
Subgroup basic-wait-all:
pass   -> SKIP   (fi-blb-e6850)
Subgroup basic-await-all:
pass   -> SKIP   (fi-blb-e6850)
Test kms_busy:
Subgroup basic-flip-a:
pass   -> SKIP   (fi-blb-e6850)
Subgroup basic-flip-b:
pass   -> SKIP   (fi-blb-e6850)
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
pass   -> SKIP   (fi-blb-e6850)
Test kms_frontbuffer_tracking:
Subgroup basic:
fail   -> PASS   (fi-glk-1) fdo#103167

fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:416s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:429s
fi-blb-e6850 total:288  pass:210  dwarn:1   dfail:0   fail:0   skip:77  
time:346s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:488s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:285s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:487s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:482s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:466s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:454s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:565s
fi-cnl-y3total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:580s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:414s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:280s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:511s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:388s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:410s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:447s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:414s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:461s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:500s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:450s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:500s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:590s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:434s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:507s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:527s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:486s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:477s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:418s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:427s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:516s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:393s
Blacklisted hosts:
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:470s

57bed53a064818de1d946bf7d432ca6e756f553e drm-tip: 2018y-02m-07d-05h-16m-20s UTC 
integration manifest
ca17e45f580b drm/i915: Estimate and update missed vblanks.
f8492dc84a20 drm/vblank: Restoring vblank counts after device PM events.
6ac7f096240e drm/vblank: Do not 

Re: [Intel-gfx] [PULL] gvt-next-fixes for 4.16

[Rodrigo Vivi]

Zhenyu Wang  writes:

> On 2018.02.06 11:45:04 -0800, Rodrigo Vivi wrote:
>> 
>> Hi Zhi,
>> 
>> Daniel asked few weeks ago about the scripts that you run there,
>> but I didn't see any follow-up.
>> 
>> I don't understand why yet, but apparently gvt pull request
>> is not going to patchwork so dim is not able to add the "Link:"
>> hence end up without mandatory patchwork links.
>>
>> Last round I by-pass dim and move forward even without the "Link:"
>> if the solution is easier I'd like to do the right thing this time.
>
> I think maybe previously Link tag was not mandatory? Or Daniel
> bypassed at that time too?

Hmm... That's strange.
I'm basing my comments on this reply from Daniel:
https://www.spinics.net/lists/intel-gfx/msg149862.html (4.15)

I don't believe Daniel or Jani ever bypassed the dim like I'm doing.
But also on 4.14 fixes I dind't have to bypass dim, so something is
strange but I don't fully understand because I lack on the previous
history here.

> To have patchwork set up for gvt would be
> good, as our QA's current infrastruture doesn't require that, so I
> didn't push the request for it. Who may we contact to setup for us
> now? Or open a fd.o bug?
>
>> 
>> Although I'm open to by-pass again,
>> I'd like to know if we are in sync to understand what is happening
>> again and get that fixed for next time
>> 
>> Cc: Daniel in case he know a quick fix or can at least provide more
>> info there on what could be failing.
>
> As we'd like to make those stable fixes in upstream soon, maybe better
> bypass for lacking Link tag at this time, we'll try to fix that from
> next pull. Sorry for any inconvenience.

No worries. Let's just try to understand and find the solution
for the next pull. For now I by pass and merged on dinf.
Now it is time to fix the drm-tip conflicts and wait for CI
to run. So, luckly, tomorrow morning I send out the pull request.

>
> thanks

thanks you!

>
> -- 
> Open Source Technology Center, Intel ltd.
>
> $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
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Re: [Intel-gfx] [PATCH v8 3/6] drm/i915/guc: Implement dynamic GuC WOPCM offset and size

[Yaodong Li]

On 02/06/2018 02:25 PM, Michal Wajdeczko wrote:



default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
  -    /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If 
GuC is not

+    /*
+ * GuC requires the ring to be placed above GuC WOPCM top. If 
GuC is not
   * present or not in use we still need a small bias as ring 
wraparound

   * at offset 0 sometimes hangs. No idea why.
   */
  if (USES_GUC(dev_priv))
-    ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
+    ctx->ggtt_offset_bias = dev_priv->guc.wopcm.top;


I know that Joonas was against using extra inline function to read
value of "guc.wopcm.top" but maybe we should discuss it again as
now we maybe using invalid/unset value since now we are not verifying
"guc->wopcm.valid" flag.

It should be fine in this case since we have early inited the value to 
the worst
case (using the size of all WOPCM). we could not use valid here since 
uc_init

has been called at this point.


+static inline int gen9_guc_wopcm_size_check(struct drm_i915_private 
*i915)


maybe it would be better to pass "wopcm" instead of "i915" ?

hmm, I think it's better to have an unified parameter list for all the 
check functions.

and it the same since we will have to get wopcm from i915 anyways.

+{
+    struct intel_guc_wopcm *wopcm = >guc.wopcm;

use variable name as guc_wopcm?

+    u32 guc_wopcm_start;
+    u32 delta;
+
+    /*
+ * GuC WOPCM size is at least 4 bytes larger than the offset 
from WOPCM


Either use 4B directly below (as you give explanation here) or move that
comment near the definition of GEN9_GUC_WOPCM_DELTA.

+ * base (GuC WOPCM offset from WOPCM base + 
GEN9_GUC_WOPCM_OFFSET) due

+ * to hardware limitation on Gen9.
+ */
+    guc_wopcm_start = wopcm->offset + GEN9_GUC_WOPCM_OFFSET;
+    if (unlikely(guc_wopcm_start > wopcm->size))
+    return -E2BIG;
+
+    delta = wopcm->size - guc_wopcm_start;
+    if (unlikely(delta < GEN9_GUC_WOPCM_DELTA))
+    return -E2BIG;
+
+    return 0;
+}
+
+static inline int guc_wopcm_check_hw_restrictions(struct intel_guc 
*guc)

+{
+    struct drm_i915_private *i915 = guc_to_i915(guc);
+
+    if (IS_GEN9(i915))
+    return gen9_guc_wopcm_size_check(i915);


please use function name that matches dispatcher function

guc_wopcm_check_hw_restrictions()
gen9_guc_wopcm_check_hw_restrictions()

or

guc_wopcm_size_check()
gen9_guc_wopcm_size_check()


+
+    return 0;
+}
+
+/**
+ * intel_guc_wopcm_init() - Initialize the GuC WOPCM..

remove extra "."

   * @guc: intel guc.
+ * @guc_fw_size: size of GuC firmware.
+ * @huc_fw_size: size of HuC firmware.
   *
- * Get the platform specific GuC WOPCM size.
+ * Calculate the GuC WOPCM offset and size based on GuC and HuC 
firmware sizes.
+ * This function will to set the GuC WOPCM size to the size of 
maximum WOPCM

remove "to"
+ * available for GuC. This function will also enforce platform 
dependent
+ * hardware restrictions on GuC WOPCM offset and size. It will fail 
the GuC
+ * WOPCM init if any of these checks were failed, so that the 
following GuC

+ * firmware uploading would be aborted.
   *
- * Return: size of the GuC WOPCM.
+ * Return: 0 on success, non-zero error code on failure.
   */
-u32 intel_guc_wopcm_size(struct intel_guc *guc)


Hmm, it looks that all your changes for this function from patch 2/6
are now lost ...


patch 1/6 & 2/6 are only for some code movings. but have to make it clean.
but I do not need this func anymore:o)

+int intel_guc_wopcm_init(struct intel_guc *guc, u32 guc_fw_size,
+ u32 huc_fw_size)
  {
-    struct drm_i915_private *i915 = guc_to_i915(guc);
-    u32 size = GUC_WOPCM_TOP;
+    u32 reserved = guc_reserved_wopcm_size(guc);
+    u32 offset, size, top;
+    int err;
  -    /* On BXT, the top of WOPCM is reserved for RC6 context */
-    if (IS_GEN9_LP(i915))
-    size -= BXT_GUC_WOPCM_RC6_RESERVED;
+    if (guc->wopcm.valid)
+    return 0;


Is there a scenario when this function will be called more than one?

You're right. we need not need such a check anymore.



+
+    if (!guc_fw_size)
+    return -EINVAL;


GEM_BUG_ON ?


+
+    if (reserved >= WOPCM_DEFAULT_SIZE)
+    return -E2BIG;


GEM_BUG_ON ?

Will give the control back to uc_init.?



+
+    offset = huc_fw_size + WOPCM_RESERVED_SIZE;


What's the difference between guc_reserved_wopcm_size and 
WOPCM_RESERVED_SIZE



WOPCM_RESERVED_SIZE is the reserved size in Non-GuC WOPCM.

+    guc->wopcm.offset = offset;
+    guc->wopcm.size = size;
+    guc->wopcm.top = top;
+
+    /* Check platform specific restrictions */
+    err = guc_wopcm_check_hw_restrictions(guc);


maybe you should check HW restrictions *before* initializing the 
structure?


err = check_hw_restrictions(i915, offset, size, top);
Actually, I was struggling on this a bit, but it's clearer to have to 
valid bit in this
struct instead of only checking offset/size/top. And now that we have 
valid bit
it would be better to init the 

Re: [Intel-gfx] [PATCH v8 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers

[Yaodong Li]

On 02/06/2018 02:56 PM, Michal Wajdeczko wrote:


+    /* Explicitly cast the return value to bool. */
+    return !!(I915_READ(reg) & GUC_WOPCM_REG_LOCKED);


you should avoid reusing bits defined for one register in others


it's a common bit. use BIT(0) instead?




+    offset &= DMA_GUC_WOPCM_OFFSET_MASK;


maybe like this for easier reading:

u32 reg;

reg = I915_READ(GUC_WOPCM_SIZE);
size = reg & PAGE_MASK;

reg = I915_READ(DMA_GUC_WOPCM_OFFSET);
offset = reg & DMA_GUC_WOPCM_OFFSET_MASK;

hmm, this will clear the HUC_LOADING_AGENT_GUC.

guc_loads_huc = reg & HUC_LOADING_AGENT_GUC;


+
+    return guc_loads_huc && (size == guc->wopcm.size) &&


what if we run in !USES_HUC() mode?


Do you mean the HUC_LOADING_AGENT bit?

this patch series is trying to align with the current driver logic. this bit
is current set regardless USES_HUC()

Are you suggest we should not set this bit for !USE_HUC() mode?

+    (offset == guc->wopcm.offset);
  #define GEN9_GUC_WOPCM_OFFSET    (0x24000)
  +/* GuC WOPCM flags */
+#define INTEL_GUC_WOPCM_VALID    BIT(0)
+#define INTEL_GUC_WOPCM_HW_UPDATED    BIT(1)


maybe just

bool valid:1;
bool hw_updated:1;

I was trying to avoid bool in struct (really struggling with it actual 
size), maybe

u32 valid:1;
u32 hw_updated:1

Regards,
-Jackie


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Re: [Intel-gfx] [PATCH v8 1/6] drm/i915/guc: Move GuC WOPCM related code into separate files

[Yaodong Li]

On 02/06/2018 01:11 PM, Michal Wajdeczko wrote:
On Tue, 06 Feb 2018 06:15:54 +0100, Sagar Arun Kamble 
 wrote:




On 2/6/2018 5:32 AM, Jackie Li wrote:

intel_guc_reg.h should only include definition for GuC registers and
related register bits. Non-register related GuC WOPCM macro definitions
should not be defined in intel_guc_reg.h

This patch creates a better file structure by moving non-register 
related
GuC WOPCM macro definitions into a new header intel_guc_wopcm.h and 
moving

GuC WOPCM related functions to a new source file intel_guc_wopcm.c as
future patches will increase the complexity of determining the GuC 
WOPCM

offset and size.


Hmm, I'm not sure that we need such low-details explanation that repeats
filenames listed below. Maybe it can like this:

"New file structure is needed as future patches will increase the
complexity of determining the GuC WOPCM offset and size."



v8:
  - Fixed naming, coding style issues and typo in commit message 
(Sagar)
  - Updated commit message to explain why we need create new file 
for GuC

    WOPCM related code (Chris)

Cc: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Sagar Arun Kamble  (v7)
Signed-off-by: Jackie Li 

Minor change in function comment needed below as per kernel-doc format.
Otherwise, change is good.
Reviewed-by: Sagar Arun Kamble 

---
  drivers/gpu/drm/i915/Makefile  |  1 +
  drivers/gpu/drm/i915/intel_guc.c   | 11 
  drivers/gpu/drm/i915/intel_guc.h   |  2 +-
  drivers/gpu/drm/i915/intel_guc_reg.h   |  4 ---
  drivers/gpu/drm/i915/intel_guc_wopcm.c | 46 
++
  drivers/gpu/drm/i915/intel_guc_wopcm.h | 39 


  drivers/gpu/drm/i915/intel_uc.c    |  2 +-
  drivers/gpu/drm/i915/intel_uc_fw.c |  2 +-
  8 files changed, 89 insertions(+), 18 deletions(-)
  create mode 100644 drivers/gpu/drm/i915/intel_guc_wopcm.c
  create mode 100644 drivers/gpu/drm/i915/intel_guc_wopcm.h

diff --git a/drivers/gpu/drm/i915/Makefile 
b/drivers/gpu/drm/i915/Makefile

index 3bddd8a..1dc9988 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -88,6 +88,7 @@ i915-y += intel_uc.o \
    intel_guc_fw.o \
    intel_guc_log.o \
    intel_guc_submission.o \
+  intel_guc_wopcm.o \
    intel_huc.o
    # autogenerated null render state
diff --git a/drivers/gpu/drm/i915/intel_guc.c 
b/drivers/gpu/drm/i915/intel_guc.c

index 21140cc..9f45e6d 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -509,14 +509,3 @@ struct i915_vma *intel_guc_allocate_vma(struct 
intel_guc *guc, u32 size)

  i915_gem_object_put(obj);
  return vma;
  }
-
-u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
-{
-    u32 wopcm_size = GUC_WOPCM_TOP;
-
-    /* On BXT, the top of WOPCM is reserved for RC6 context */
-    if (IS_GEN9_LP(dev_priv))
-    wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
-
-    return wopcm_size;
-}
diff --git a/drivers/gpu/drm/i915/intel_guc.h 
b/drivers/gpu/drm/i915/intel_guc.h

index 52856a9..9e0a97e 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -31,6 +31,7 @@
  #include "intel_guc_ct.h"
  #include "intel_guc_log.h"
  #include "intel_guc_reg.h"
+#include "intel_guc_wopcm.h"
  #include "intel_uc_fw.h"
  #include "i915_vma.h"
  @@ -130,6 +131,5 @@ int intel_guc_auth_huc(struct intel_guc *guc, 
u32 rsa_offset);

  int intel_guc_suspend(struct drm_i915_private *dev_priv);
  int intel_guc_resume(struct drm_i915_private *dev_priv);
  struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 
size);

-u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
    #endif
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h 
b/drivers/gpu/drm/i915/intel_guc_reg.h

index 19a9247..1f52fb8 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -68,7 +68,6 @@
  #define DMA_GUC_WOPCM_OFFSET    _MMIO(0xc340)
  #define   HUC_LOADING_AGENT_VCR  (0<<1)
  #define   HUC_LOADING_AGENT_GUC  (1<<1)
-#define   GUC_WOPCM_OFFSET_VALUE  0x8    /* 512KB */
  #define GUC_MAX_IDLE_COUNT    _MMIO(0xC3E4)
    #define HUC_STATUS2 _MMIO(0xD3B0)
@@ -76,9 +75,6 @@
    /* Defines WOPCM space available to GuC firmware */
  #define GUC_WOPCM_SIZE    _MMIO(0xc050)
-/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
-#define   GUC_WOPCM_TOP  (0x80 << 12)    /* 512KB */
-#define   BXT_GUC_WOPCM_RC6_RESERVED  (0x10 << 12)    /* 64KB  */
    /* GuC addresses above GUC_GGTT_TOP also don't map through the 
GTT */

  #define GUC_GGTT_TOP    0xFEE0
diff --git 

Re: [Intel-gfx] [PATCH v8 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers

[Yaodong Li]

On 02/05/2018 10:39 PM, Sagar Arun Kamble wrote:

+/**
+ * intel_guc_wopcm_init_hw() - Setup GuC WOPCM registers.
+ * @guc: intel guc.
+ *
+ * Setup the GuC WOPCM size and offset registers with the stored 
values. It will
+ * also check the registers locking status to determine whether 
these registers

+ * are unlocked and can be updated.
+ */
+void intel_guc_wopcm_init_hw(struct intel_guc *guc)
+{
+    bool locked = guc_wopcm_locked(guc);
+
+    GEM_BUG_ON(!(guc->wopcm.flags & INTEL_GUC_WOPCM_VALID));
+
+    /*
+ * Bug if driver hasn't updated the HW Registers and GuC WOPCM 
has been

+ * locked. Return directly if WOPCM was locked and we have updated
+ * the registers.
+ */
+    if (locked) {
+    /*
+ * Mark as updated if registers contained correct values.
+ * This will happen while reloading the driver module without
+ * rebooting the system.
+ */
+    if (guc_wopcm_regs_valid(guc))
+    goto out;
+
+    GEM_BUG_ON(!(guc->wopcm.flags & INTEL_GUC_WOPCM_HW_UPDATED));
We should not go ahead with uc_init_hw in this case so returning error 
from here or

checking wopcm.flags to abort uc_init_hw is needed with debug message.

In a second thought, I think we need do more work here to check whether the
locked values are sufficient for current fw sizes. if yes then return 
success else

fail the wopcm init.
I agree we only check the status and return the control to uc_init_hw.

Thanks & Regards,
-Jackie

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Re: [Intel-gfx] [PULL] gvt-next-fixes for 4.16

[Zhenyu Wang]

On 2018.02.06 11:45:04 -0800, Rodrigo Vivi wrote:
> 
> Hi Zhi,
> 
> Daniel asked few weeks ago about the scripts that you run there,
> but I didn't see any follow-up.
> 
> I don't understand why yet, but apparently gvt pull request
> is not going to patchwork so dim is not able to add the "Link:"
> hence end up without mandatory patchwork links.
>
> Last round I by-pass dim and move forward even without the "Link:"
> if the solution is easier I'd like to do the right thing this time.

I think maybe previously Link tag was not mandatory? Or Daniel
bypassed at that time too? To have patchwork set up for gvt would be
good, as our QA's current infrastruture doesn't require that, so I
didn't push the request for it. Who may we contact to setup for us
now? Or open a fd.o bug?

> 
> Although I'm open to by-pass again,
> I'd like to know if we are in sync to understand what is happening
> again and get that fixed for next time
> 
> Cc: Daniel in case he know a quick fix or can at least provide more
> info there on what could be failing.

As we'd like to make those stable fixes in upstream soon, maybe better
bypass for lacking Link tag at this time, we'll try to fix that from
next pull. Sorry for any inconvenience.

thanks

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Re: [Intel-gfx] [PATCH] drm/i915: Display WA #0827 for NV12 to RGB switch

[Srinivas, Vidya]

Hi Maarten

Sorry, my bad. This was a wrong push from my end. I have changed the tag to Not 
applicable.
Apologies.

Have sent out the NV12 series separately.

Regards
Vidya

> -Original Message-
> From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
> Sent: Tuesday, February 6, 2018 7:33 PM
> To: Srinivas, Vidya ; intel-
> g...@lists.freedesktop.org
> Cc: Kamath, Sunil ; Sharma, Shashank
> ; Shankar, Uma ;
> Konduru, Chandra 
> Subject: Re: [PATCH] drm/i915: Display WA #0827 for NV12 to RGB switch
> 
> Hey,
> 
> Op 06-02-18 om 12:06 schreef Vidya Srinivas:
> > From: Chandra Konduru 
> >
> > Display WA #0827:
> > Switching the plane format from NV12 to RGB and leaving system idle
> > results in display underrun and corruption. WA: Set the bit 15 & bit
> > 19 to 1b in the CLKGATE_DIS_PSL register for the pipe in which NV12 plane
> is enabled.
> >
> > Signed-off-by: Chandra Konduru 
> > Signed-off-by: Vidya Srinivas 
> 
> Is it required to leave the workaround enabled all the time? And how can I
> reproduce it? I tried to write a dumb testcase (below) to expose this issue,
> but didn't have much luck..
> ---
> diff --git a/tests/Makefile.sources b/tests/Makefile.sources index
> 870c9093550b..f536db0fa433 100644
> --- a/tests/Makefile.sources
> +++ b/tests/Makefile.sources
> @@ -192,6 +192,7 @@ TESTS_progs = \
>   kms_legacy_colorkey \
>   kms_mmap_write_crc \
>   kms_mmio_vs_cs_flip \
> + kms_nv12 \
>   kms_panel_fitting \
>   kms_pipe_b_c_ivb \
>   kms_pipe_crc_basic \
> diff --git a/tests/kms_nv12.c b/tests/kms_nv12.c new file mode 100644
> index ..384a15afde52
> --- /dev/null
> +++ b/tests/kms_nv12.c
> @@ -0,0 +1,195 @@
> +/*
> + * Permission is hereby granted, free of charge, to any person
> +obtaining a
> + * copy of this software and associated documentation files (the
> +"Software"),
> + * to deal in the Software without restriction, including without
> +limitation
> + * the rights to use, copy, modify, merge, publish, distribute,
> +sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom
> +the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> +included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND,
> +EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> +MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT
> +SHALL THE
> + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> DAMAGES OR
> +OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> OTHERWISE,
> +ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
> OR OTHER
> +DEALINGS
> + * IN THE SOFTWARE.
> + *
> + * Authors:
> + *Maarten Lankhorst
> + */
> +#include "config.h"
> +
> +#include "igt.h"
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +typedef struct {
> + igt_display_t display;
> +
> + igt_pipe_crc_t *pipe_crc;
> + struct igt_fb fb[4];
> +} data_t;
> +
> +static bool plane_supports_format(igt_plane_t *plane, uint32_t format)
> +{
> + int i;
> +
> + if (!igt_fb_supported_format(format))
> + return false;
> +
> + for (i = 0; i < plane->drm_plane->count_formats; i++)
> + if (plane->drm_plane->formats[i] == format)
> + return true;
> +
> + return false;
> +}
> +
> +static bool pipe_supports_format(igt_display_t *display, enum pipe
> +pipe, uint32_t format) {
> + igt_plane_t *plane;
> +
> + for_each_plane_on_pipe(display, pipe, plane)
> + if (plane_supports_format(plane, format))
> + return true;
> +
> + return false;
> +}
> +
> +static void remove_fbs(data_t *data)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(data->fb); i++)
> + igt_remove_fb(data->display.drm_fd, >fb[i]); }
> +
> +static void prepare_crtc(data_t *data, enum pipe pipe, igt_output_t
> +*output) {
> + igt_display_t *display = >display;
> +
> + remove_fbs(data);
> + igt_display_reset(display);
> + igt_output_set_pipe(output, pipe);
> + igt_display_commit2(display, COMMIT_ATOMIC);
> +
> + igt_pipe_crc_free(data->pipe_crc);
> + data->pipe_crc = igt_pipe_crc_new(display->drm_fd, pipe,
> +INTEL_PIPE_CRC_SOURCE_AUTO); }
> +
> +static void set_fb(igt_plane_t *plane, struct igt_fb *fb) {
> + igt_plane_set_fb(plane, fb);
> +
> + if (fb && fb->tiling == LOCAL_I915_FORMAT_MOD_Y_TILED) {
> + igt_plane_set_rotation(plane, IGT_ROTATION_90);
> + igt_plane_set_size(plane, fb->height, 

Re: [Intel-gfx] [PATCH 1/9] drm/i915/psr: Do not activate PSR on frontbuffer flush from fbdev.

[Pandiyan, Dhinakaran]

On Wed, 2018-01-31 at 22:56 -0800, Rodrigo Vivi wrote:
> On Sat, Jan 27, 2018 at 02:49:15AM +, Dhinakaran Pandiyan wrote:
> > There is no corresponding invalidate call before the buffer is written
> > to, this results in screen freezing sometime after switching to console
> > mode with PSR enabled. Invalidating the front buffer in the fbdev call
> > backs won't work either as some of them are called in atomic contexts and
> > {drrs, fbc, psr}_invalidate all sleep. So don't activate PSR for now.
> > 
> > Cc: Rodrigo Vivi 
> > Signed-off-by: Dhinakaran Pandiyan 
> > ---
> >  drivers/gpu/drm/i915/intel_psr.c | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index e9feffdea899..c12af1118647 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -881,6 +881,9 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> > if (!CAN_PSR(dev_priv))
> > return;
> >  
> > +   if (origin == ORIGIN_DIRTYFB)
> > +   return;
> > +
> 
> I'd like Paulo to take a look here.
> 
> What I'm confused now is who (what fbt bit) is actually blocking PSR to work
> on fbdev.

intel_psr_flush()->intel_psr_exit() does get called as expected, so it's
not the frontbuffer bit that is preventing PSR from exiting. I don't
fully understand why exactly intel_psr_flush() is insufficient (without
psr_invalidate()).

One thing that might be of interest is the gem object has write domain
as zero. I am wondering if we are missing some initialization. But, that
does not explain why the screen freezes only with PSR

> 
> And what would be the risks of other corner cases or the risk of this
> not getting psr re-enabled until next reboot...
> 


> > mutex_lock(_priv->psr.lock);
> > if (!dev_priv->psr.enabled) {
> > mutex_unlock(_priv->psr.lock);
> > -- 
> > 2.14.1
> > 
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Re: [Intel-gfx] [PATCH 06/10] drm/tegra: Handle 64-bit return from drm_crtc_vblank_count()

[Pandiyan, Dhinakaran]

On Fri, 2018-02-02 at 21:12 -0800, Dhinakaran Pandiyan wrote:
> 570e86963a51 ("drm: Widen vblank count to 64-bits [v3]") changed the
> return type for drm_crtc_vblank_count() to u64. This could cause
> potential problems if the return value is used in arithmetic operations
> with a 32-bit reference HW vblank count. Explicitly typecasting this
> down to u32 either fixes a potential problem or serves to add clarity in
> case the implicit typecasting was already correct.
> 
> Cc: Keith Packard 
> Cc: Thierry Reding 


Thierry, 

Can I get an Ack on this please? 

> Signed-off-by: Dhinakaran Pandiyan 
> ---
>  drivers/gpu/drm/tegra/dc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
> index b8403ed48285..49df2db2ad46 100644
> --- a/drivers/gpu/drm/tegra/dc.c
> +++ b/drivers/gpu/drm/tegra/dc.c
> @@ -1359,7 +1359,7 @@ static u32 tegra_dc_get_vblank_counter(struct drm_crtc 
> *crtc)
>   return host1x_syncpt_read(dc->syncpt);
>  
>   /* fallback to software emulated VBLANK counter */
> - return drm_crtc_vblank_count(>base);
> + return (u32)drm_crtc_vblank_count(>base);
>  }
>  
>  static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
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[Intel-gfx] [PATCH igt] igt/gem_eio: Use slow spinners to inject hangs

[Chris Wilson]

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104676
Signed-off-by: Chris Wilson 
---
 lib/igt_gt.c|  1 +
 tests/gem_eio.c | 77 +++--
 2 files changed, 43 insertions(+), 35 deletions(-)

diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index ad6e62053..f70fcb925 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -402,6 +402,7 @@ void igt_force_gpu_reset(int drm_fd)
igt_sysfs_scanf(dir, "i915_wedged", "%d", );
 
close(dir);
+   errno = 0;
 
igt_assert(!wedged);
 }
diff --git a/tests/gem_eio.c b/tests/gem_eio.c
index c941f3564..0b563bd0d 100644
--- a/tests/gem_eio.c
+++ b/tests/gem_eio.c
@@ -69,6 +69,8 @@ static void trigger_reset(int fd)
/* And just check the gpu is indeed running again */
igt_debug("Checking that the GPU recovered\n");
gem_test_engine(fd, -1);
+
+   gem_quiescent_gpu(fd);
 }
 
 static void wedge_gpu(int fd)
@@ -135,15 +137,17 @@ static void test_execbuf(int fd)
 
 static int __gem_wait(int fd, uint32_t handle, int64_t timeout)
 {
-   struct drm_i915_gem_wait wait;
-   int err = 0;
+   struct drm_i915_gem_wait wait = {
+   .bo_handle = handle,
+   .timeout_ns = timeout,
+   };
+   int err;
 
-   memset(, 0, sizeof(wait));
-   wait.bo_handle = handle;
-   wait.timeout_ns = timeout;
+   err = 0;
if (drmIoctl(fd, DRM_IOCTL_I915_GEM_WAIT, ))
err = -errno;
 
+   errno = 0;
return err;
 }
 
@@ -184,11 +188,9 @@ static void test_suspend(int fd, int state)
 
 static void test_inflight(int fd)
 {
-   struct drm_i915_gem_execbuffer2 execbuf;
+   const uint32_t bbe = MI_BATCH_BUFFER_END;
struct drm_i915_gem_exec_object2 obj[2];
-   uint32_t bbe = MI_BATCH_BUFFER_END;
unsigned int engine;
-   int fence[64]; /* conservative estimate of ring size */
 
igt_require(gem_has_exec_fence(fd));
 
@@ -198,13 +200,17 @@ static void test_inflight(int fd)
gem_write(fd, obj[1].handle, 0, , sizeof(bbe));
 
for_each_engine(fd, engine) {
-   igt_hang_t hang;
+   struct drm_i915_gem_execbuffer2 execbuf;
+   igt_spin_t *hang;
+   int fence[64]; /* conservative estimate of ring size */
+
+   gem_quiescent_gpu(fd);
 
igt_debug("Starting %s on engine '%s'\n", __func__, e__->name);
igt_require(i915_reset_control(false));
 
-   hang = igt_hang_ring(fd, engine);
-   obj[0].handle = hang.handle;
+   hang = igt_spin_batch_new(fd, 0, engine, 0);
+   obj[0].handle = hang->handle;
 
memset(, 0, sizeof(execbuf));
execbuf.buffers_ptr = to_user_pointer(obj);
@@ -217,14 +223,13 @@ static void test_inflight(int fd)
igt_assert(fence[n] != -1);
}
 
-   igt_post_hang_ring(fd, hang);
-
igt_assert_eq(__gem_wait(fd, obj[1].handle, -1), 0);
for (unsigned int n = 0; n < ARRAY_SIZE(fence); n++) {
igt_assert_eq(sync_fence_status(fence[n]), -EIO);
close(fence[n]);
}
 
+   igt_spin_batch_free(fd, hang);
igt_assert(i915_reset_control(true));
trigger_reset(fd);
}
@@ -236,7 +241,7 @@ static void test_inflight_suspend(int fd)
struct drm_i915_gem_exec_object2 obj[2];
uint32_t bbe = MI_BATCH_BUFFER_END;
int fence[64]; /* conservative estimate of ring size */
-   igt_hang_t hang;
+   igt_spin_t *hang;
 
igt_require(gem_has_exec_fence(fd));
igt_require(i915_reset_control(false));
@@ -246,8 +251,8 @@ static void test_inflight_suspend(int fd)
obj[1].handle = gem_create(fd, 4096);
gem_write(fd, obj[1].handle, 0, , sizeof(bbe));
 
-   hang = igt_hang_ring(fd, 0);
-   obj[0].handle = hang.handle;
+   hang = igt_spin_batch_new(fd, 0, 0, 0);
+   obj[0].handle = hang->handle;
 
memset(, 0, sizeof(execbuf));
execbuf.buffers_ptr = to_user_pointer(obj);
@@ -263,14 +268,13 @@ static void test_inflight_suspend(int fd)
igt_set_autoresume_delay(30);
igt_system_suspend_autoresume(SUSPEND_STATE_MEM, SUSPEND_TEST_NONE);
 
-   igt_post_hang_ring(fd, hang);
-
igt_assert_eq(__gem_wait(fd, obj[1].handle, -1), 0);
for (unsigned int n = 0; n < ARRAY_SIZE(fence); n++) {
igt_assert_eq(sync_fence_status(fence[n]), -EIO);
close(fence[n]);
}
 
+   igt_spin_batch_free(fd, hang);
igt_assert(i915_reset_control(true));
trigger_reset(fd);
 }
@@ -288,12 +292,10 @@ static uint32_t __gem_context_create(int fd)
 
 static void test_inflight_contexts(int fd)
 {
-   struct drm_i915_gem_execbuffer2 execbuf;
struct drm_i915_gem_exec_object2 obj[2];
- 

Re: [Intel-gfx] [PATCH v8 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers

[Michal Wajdeczko]

On Tue, 06 Feb 2018 07:39:27 +0100, Sagar Arun Kamble  
 wrote:





On 2/6/2018 5:32 AM, Jackie Li wrote:
GuC WOPCM registers are write-once registers. Current driver code  
accesses
these registers without checking the accessibility to these registers,  
this
will lead unpredictable driver behaviors if these registers were touch  
by

other components (such as faulty BIOS code).

This patch moves the GuC WOPCM register updating operations into
intel_guc_wopcm.c and adds checks before and after the write to GuC  
WOPCM

registers to make sure the driver is in a known state before and after
writing to these write-once registers.

v6:
  - Made sure module reloading won't bug the kernel while doing
locking status checking

v7:
  - Fixed patch format issues

v8:
  - Fixed coding style issue on register lock bit macro definition  
(Sagar)


Cc: Michal Wajdeczko 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Signed-off-by: Jackie Li 
---
  drivers/gpu/drm/i915/intel_guc.h   |  2 +-
  drivers/gpu/drm/i915/intel_guc_reg.h   |  2 +
  drivers/gpu/drm/i915/intel_guc_wopcm.c | 93  
--

  drivers/gpu/drm/i915/intel_guc_wopcm.h |  9 +++-
  drivers/gpu/drm/i915/intel_uc.c|  5 +-
  5 files changed, 101 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.h  
b/drivers/gpu/drm/i915/intel_guc.h

index 06f315e..cb1703b 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -122,7 +122,7 @@ static inline u32 intel_guc_ggtt_offset(struct  
intel_guc *guc,

  {
u32 offset = i915_ggtt_offset(vma);
  - GEM_BUG_ON(!guc->wopcm.valid);
+   GEM_BUG_ON(!(guc->wopcm.flags & INTEL_GUC_WOPCM_VALID));
GEM_BUG_ON(offset < guc->wopcm.top);
GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
  diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h  
b/drivers/gpu/drm/i915/intel_guc_reg.h

index de4f78b..18cb2ef 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -66,6 +66,7 @@
  #define   UOS_MOVE  (1<<4)
  #define   START_DMA (1<<0)
  #define DMA_GUC_WOPCM_OFFSET  _MMIO(0xc340)
+#define   DMA_GUC_WOPCM_OFFSET_MASK  (0xc000)


please define _SHIFT and use it in _MASK definition


  #define   HUC_LOADING_AGENT_VCR (0<<1)
  #define   HUC_LOADING_AGENT_GUC (1<<1)
  #define GUC_MAX_IDLE_COUNT_MMIO(0xC3E4)
@@ -75,6 +76,7 @@
/* Defines WOPCM space available to GuC firmware */
  #define GUC_WOPCM_SIZE_MMIO(0xc050)
+#define   GUC_WOPCM_REG_LOCKED   BIT(0)


use (1 << 0) instead


#define GEN8_GT_PM_CONFIG   _MMIO(0x138140)
  #define GEN9LP_GT_PM_CONFIG   _MMIO(0x138140)
diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.c  
b/drivers/gpu/drm/i915/intel_guc_wopcm.c

index 3cba9ac..8317d9e 100644
--- a/drivers/gpu/drm/i915/intel_guc_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c
@@ -89,6 +89,55 @@ static inline int  
guc_wopcm_check_hw_restrictions(struct intel_guc *guc)

return 0;
  }
  +static inline bool __reg_locked(struct drm_i915_private *dev_priv,
+   i915_reg_t reg)
+{
+   /* Explicitly cast the return value to bool. */
+   return !!(I915_READ(reg) & GUC_WOPCM_REG_LOCKED);


you should avoid reusing bits defined for one register in others


+}
+
+static inline bool guc_wopcm_locked(struct intel_guc *guc)
+{
+   struct drm_i915_private *i915 = guc_to_i915(guc);
+   bool size_reg_locked = __reg_locked(i915, GUC_WOPCM_SIZE);
+   bool offset_reg_locked = __reg_locked(i915, DMA_GUC_WOPCM_OFFSET);
+
+   return size_reg_locked && offset_reg_locked;
+}
+
+static inline void guc_wopcm_hw_update(struct intel_guc *guc)
+{
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+   /* GuC WOPCM registers should be unlocked at this point. */
+   GEM_BUG_ON(__reg_locked(dev_priv, GUC_WOPCM_SIZE));
+   GEM_BUG_ON(__reg_locked(dev_priv, DMA_GUC_WOPCM_OFFSET));
+
+   I915_WRITE(GUC_WOPCM_SIZE, guc->wopcm.size);
+   I915_WRITE(DMA_GUC_WOPCM_OFFSET,
+  guc->wopcm.offset | HUC_LOADING_AGENT_GUC);
+
+   GEM_BUG_ON(!__reg_locked(dev_priv, GUC_WOPCM_SIZE));
+   GEM_BUG_ON(!__reg_locked(dev_priv, DMA_GUC_WOPCM_OFFSET));
+}
+
+static inline bool guc_wopcm_regs_valid(struct intel_guc *guc)
+{
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+   u32 size, offset;
+   bool guc_loads_huc;
+
+   /* GuC WOPCM size should be always multiple of 4K pages. */
+   size = I915_READ(GUC_WOPCM_SIZE) & PAGE_MASK;
+   offset = I915_READ(DMA_GUC_WOPCM_OFFSET);
+
+   guc_loads_huc = !!(offset & HUC_LOADING_AGENT_GUC);


please follow Chris suggestions to avoid 

Re: [Intel-gfx] [PATCH v8 4/6] drm/i915/guc: Add dynamic GuC WOPCM offset and size support for CNL

[Michal Wajdeczko]

On Tue, 06 Feb 2018 07:31:06 +0100, Sagar Arun Kamble  
 wrote:





On 2/6/2018 5:32 AM, Jackie Li wrote:
CNL has its own specific reserved GuC WOPCM size and hardware  
restrictions
on GuC WOPCM size. On CNL A0 and Gen9, there's a hardware restriction  
that

requires the available GuC WOPCM size to be larger than or equal to HuC
firmware size.

This patch updates GuC WOPCM init code to return the CNL specific  
reserved
GuC WOPCM size and also adds new verfication code to ensure the  
available
GuC WOPCM size to be larger than or equal to HuC firmware size on both  
Gen9

and CNL A0.

v6:
  - Extended HuC FW size check against GuC WOPCM size to all
Gen9 and CNL A0 platforms

v7:
  - Fixed patch format issues

v8:
  - Renamed variables and functions to avoid ambiguity (Joonas)
  - Updated commit message and comments to be more comprehensive (Sagar)

Cc: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: John Spotswood 
Cc: Jeff McGee 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Signed-off-by: Jackie Li 
Need to update subject as "Update WOPCM restrictions for CNL and add HuC  
size related restriction for Gen9 and CNL A0"

Or else breaking into two patches would have been good idea.


+1 for split


But change looks good to me.
Reviewed-by: Sagar Arun Kamble 

---
  drivers/gpu/drm/i915/intel_guc_wopcm.c | 24 +++-
  drivers/gpu/drm/i915/intel_guc_wopcm.h |  2 ++
  2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.c  
b/drivers/gpu/drm/i915/intel_guc_wopcm.c

index 1555e79..3cba9ac 100644
--- a/drivers/gpu/drm/i915/intel_guc_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c
@@ -32,6 +32,25 @@ static inline u32 guc_reserved_wopcm_size(struct  
intel_guc *guc)

if (IS_GEN9_LP(i915))
return BXT_GUC_WOPCM_RC6_RESERVED;
  + if (IS_GEN10(i915))
+   return CNL_GUC_WOPCM_RESERVED;
+
+   return 0;
+}
+
+static inline int guc_wopcm_check_huc_fw_size(struct drm_i915_private  
*i915)

+{
+   struct intel_guc_wopcm *wopcm = >guc.wopcm;
+   u32 huc_fw_size = intel_uc_fw_get_size(>huc.fw);


HuC fw size was passed as param to intel_guc_wopcm_init() but here
you decided to read it directly ?


+
+   /*
+* On Gen9 & CNL A0, hardware requires the total available GuC WOPCM
+* size to be larger than or equal to HuC firmware size. Otherwise,
+* firmware uploading would fail.
+*/
+   if (unlikely(wopcm->size - GUC_WOPCM_RESERVED < huc_fw_size))
+   return -E2BIG;
+
return 0;
  }
  @@ -54,7 +73,7 @@ static inline int gen9_guc_wopcm_size_check(struct  
drm_i915_private *i915)

if (unlikely(delta < GEN9_GUC_WOPCM_DELTA))
return -E2BIG;
  - return 0;
+   return guc_wopcm_check_huc_fw_size(i915);
  }
static inline int guc_wopcm_check_hw_restrictions(struct intel_guc  
*guc)
@@ -64,6 +83,9 @@ static inline int  
guc_wopcm_check_hw_restrictions(struct intel_guc *guc)

if (IS_GEN9(i915))
return gen9_guc_wopcm_size_check(i915);
  + if (IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0))
+   return guc_wopcm_check_huc_fw_size(i915);
+
return 0;
  }
  diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.h  
b/drivers/gpu/drm/i915/intel_guc_wopcm.h

index 28e4103..8c71d20a 100644
--- a/drivers/gpu/drm/i915/intel_guc_wopcm.h
+++ b/drivers/gpu/drm/i915/intel_guc_wopcm.h
@@ -42,6 +42,8 @@ struct intel_guc;
  #define GUC_WOPCM_STACK_RESERVED  (0x2000)
  /* 24KB at the end of GuC WOPCM is reserved for RC6 CTX on BXT. */
  #define BXT_GUC_WOPCM_RC6_RESERVED(0x6000)
+/* 36KB WOPCM reserved at the end of GuC WOPCM on CNL */
+#define CNL_GUC_WOPCM_RESERVED (0x9000)
#define GEN9_GUC_WOPCM_DELTA4
  /**

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Re: [Intel-gfx] [PATCH v8 3/6] drm/i915/guc: Implement dynamic GuC WOPCM offset and size

[Michal Wajdeczko]

On Tue, 06 Feb 2018 07:20:41 +0100, Sagar Arun Kamble  
 wrote:



change looks good to me. minor updates suggested with r-b.


On 2/6/2018 5:32 AM, Jackie Li wrote:

Hardware may have specific restrictions on GuC WOPCM offset and size. On
Gen9, the value of the GuC WOPCM size register needs to be larger than  
the

value of GuC WOPCM offset register + a Gen9 specific offset (144KB) for
reserved GuC WOPCM. Fail to enforce such a restriction on GuC WOPCM size
will lead to GuC firmware execution failures.

Add below line here?

Second restriction is for Gen9 and Gen10 and it is w.r.t. HuC firmware  
size as per which "GuC WOPCM size - 16K" should

be greater than or equal to HuC firmware size.

So we need add code to verify
the GuC WOPCM offset and size to avoid any GuC failures. On the other  
hand,
with current static GuC WOPCM offset and size values (512KB for both  
offset
and size), the GuC WOPCM size verification will fail on Gen9 even if it  
can
be fixed by lowering the GuC WOPCM offset by calculating its value  
based on
HuC firmware size (which is likely less than 200KB on Gen9), so that we  
can

have a GuC WOPCM size value which is large enough to pass the GuC WOPCM
size check.

This patch updates the reserved GuC WOPCM size for RC6 context on Gen9  
to
24KB to strictly align with the Gen9 GuC WOPCM layout. It also adds  
support

to verify the GuC WOPCM size aganist the Gen9 hardware restrictions.
Meanwhile, it provides a common way to calculate GuC WOPCM offset and  
size

based on GuC and HuC firmware sizes for all GuC/HuC enabled platforms.
Currently, GuC WOPCM offset is calculated based on HuC firmware size +
reserved WOPCM size while GuC WOPCM size is set to total WOPCM size -  
GuC
WOPCM offset - reserved RC6CTX size. In this case, GuC WOPCM offset  
will be
updated based on the size of HuC firmware while GuC WOPCM size will be  
set

to use all the remaining WOPCM space.

v2:
  - Removed intel_wopcm_init (Ville/Sagar/Joonas)
  - Renamed and Moved the intel_wopcm_partition into intel_guc (Sagar)
  - Removed unnecessary function calls (Joonas)
  - Init GuC WOPCM partition as soon as firmware fetching is completed

v3:
  - Fixed indentation issues (Chris)
  - Removed layering violation code (Chris/Michal)
  - Created separat files for GuC wopcm code  (Michal)
  - Used inline function to avoid code duplication (Michal)

v4:
  - Preset the GuC WOPCM top during early GuC init (Chris)
  - Fail intel_uc_init_hw() as soon as GuC WOPCM partitioning failed

v5:
  - Moved GuC DMA WOPCM register updating code into intel_guc_wopcm.c
  - Took care of the locking status before writing to GuC DMA
Write-Once registers. (Joonas)

v6:
  - Made sure the GuC WOPCM size to be multiple of 4K (4K aligned)

v8:
  - Updated comments and fixed naming issues (Sagar/Joonas)
  - Updated commit message to include more description about the  
hardware

restriction on GuC WOPCM size (Sagar)

Cc: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Sujaritha Sundaresan 
Cc: Daniele Ceraolo Spurio 
Cc: John Spotswood 
Cc: Oscar Mateo 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Signed-off-by: Jackie Li 


Reviewed-by: Sagar Arun Kamble 

---
  drivers/gpu/drm/i915/i915_gem_context.c |   5 +-
  drivers/gpu/drm/i915/intel_guc.c|   5 +-
  drivers/gpu/drm/i915/intel_guc.h|  12 ++--
  drivers/gpu/drm/i915/intel_guc_wopcm.c  | 116  
+---

  drivers/gpu/drm/i915/intel_guc_wopcm.h  |  66 --
  drivers/gpu/drm/i915/intel_huc.c|   2 +-
  drivers/gpu/drm/i915/intel_uc.c |  11 ++-
  drivers/gpu/drm/i915/intel_uc_fw.c  |  11 ++-
  drivers/gpu/drm/i915/intel_uc_fw.h  |  16 +
  9 files changed, 213 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c  
b/drivers/gpu/drm/i915/i915_gem_context.c

index 648e753..546404e 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -312,12 +312,13 @@ __create_hw_context(struct drm_i915_private  
*dev_priv,

ctx->desc_template =
default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
  -	/* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC  
is not

+   /*
+	 * GuC requires the ring to be placed above GuC WOPCM top. If GuC is  
not
  	 * present or not in use we still need a small bias as ring  
wraparound

 * at offset 0 sometimes hangs. No idea why.
 */
if (USES_GUC(dev_priv))
-   ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
+   ctx->ggtt_offset_bias = dev_priv->guc.wopcm.top;


I know that Joonas was against using extra inline function to read
value of 

Re: [Intel-gfx] [PATCH v2] drm/i915/pmu: Fix sleep under atomic in RC6 readout

[Imre Deak]

Hi Rafael,

On Tue, Feb 06, 2018 at 09:11:02PM +, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2018-02-06 18:33:11)
> > From: Tvrtko Ursulin 
> > 
> > We are not allowed to call intel_runtime_pm_get from the PMU counter read
> > callback since the former can sleep, and the latter is running under IRQ
> > context.
> > 
> > To workaround this, we record the last known RC6 and while runtime
> > suspended estimate its increase by querying the runtime PM core
> > timestamps.
> > 
> > Downside of this approach is that we can temporarily lose a chunk of RC6
> > time, from the last PMU read-out to runtime suspend entry, but that will
> > eventually catch up, once device comes back online and in the presence of
> > PMU queries.
> > 
> > Also, we have to be careful not to overshoot the RC6 estimate, so once
> > resumed after a period of approximation, we only update the counter once
> > it catches up. With the observation that RC6 is increasing while the
> > device is suspended, this should not pose a problem and can only cause
> > slight inaccuracies due clock base differences.
> > 
> > v2: Simplify by estimating on top of PM core counters. (Imre)
> > 
> > Signed-off-by: Tvrtko Ursulin 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104943
> > Fixes: 6060b6aec03c ("drm/i915/pmu: Add RC6 residency metrics")
> > Testcase: igt/perf_pmu/rc6-runtime-pm
> > Cc: Tvrtko Ursulin 
> > Cc: Chris Wilson 
> > Cc: Imre Deak 
> > Cc: Jani Nikula 
> > Cc: Joonas Lahtinen 
> > Cc: Rodrigo Vivi 
> > Cc: David Airlie 
> > Cc: intel-gfx@lists.freedesktop.org
> > Cc: dri-de...@lists.freedesktop.org
> > ---
> >  drivers/gpu/drm/i915/i915_pmu.c | 93 
> > ++---
> >  drivers/gpu/drm/i915/i915_pmu.h |  6 +++
> >  2 files changed, 84 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_pmu.c 
> > b/drivers/gpu/drm/i915/i915_pmu.c
> > index 1c440460255d..bfc402d47609 100644
> > --- a/drivers/gpu/drm/i915/i915_pmu.c
> > +++ b/drivers/gpu/drm/i915/i915_pmu.c
> > @@ -415,7 +415,81 @@ static int i915_pmu_event_init(struct perf_event 
> > *event)
> > return 0;
> >  }
> >  
> > -static u64 __i915_pmu_event_read(struct perf_event *event)
> > +static u64 get_rc6(struct drm_i915_private *i915, bool locked)
> > +{
> > +   unsigned long flags;
> > +   u64 val;
> > +
> > +   if (intel_runtime_pm_get_if_in_use(i915)) {
> > +   val = intel_rc6_residency_ns(i915, IS_VALLEYVIEW(i915) ?
> > +  VLV_GT_RENDER_RC6 :
> > +  GEN6_GT_GFX_RC6);
> > +
> > +   if (HAS_RC6p(i915))
> > +   val += intel_rc6_residency_ns(i915, 
> > GEN6_GT_GFX_RC6p);
> > +
> > +   if (HAS_RC6pp(i915))
> > +   val += intel_rc6_residency_ns(i915, 
> > GEN6_GT_GFX_RC6pp);
> > +
> > +   intel_runtime_pm_put(i915);
> > +
> > +   /*
> > +* If we are coming back from being runtime suspended we 
> > must
> > +* be careful not to report a larger value than returned
> > +* previously.
> > +*/
> > +
> > +   if (!locked)
> > +   spin_lock_irqsave(>pmu.lock, flags);
> > +
> > +   if (val >= 
> > i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur) {
> > +   i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = 
> > 0;
> > +   i915->pmu.sample[__I915_SAMPLE_RC6].cur = val;
> > +   } else {
> > +   val = 
> > i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur;
> > +   }
> > +
> > +   if (!locked)
> > +   spin_unlock_irqrestore(>pmu.lock, flags);
> > +   } else {
> > +   struct pci_dev *pdev = i915->drm.pdev;
> > +   struct device *kdev = >dev;
> > +   unsigned long flags2;
> > +
> > +   /*
> > +* We are runtime suspended.
> > +*
> > +* Report the delta from when the device was suspended to 
> > now,
> > +* on top of the last known real value, as the approximated 
> > RC6
> > +* counter value.
> > +*/
> > +   if (!locked)
> > +   spin_lock_irqsave(>pmu.lock, flags);
> > +
> > +   spin_lock_irqsave(>power.lock, flags2);
> > +
> > +   if (!i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur)
> > +   i915->pmu.suspended_jiffies_last =
> > +   
> > kdev->power.suspended_jiffies;
> > +
> > +   val = 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Reject undefined colorkey flags

[Patchwork]

== Series Details ==

Series: drm/i915: Reject undefined colorkey flags
URL   : https://patchwork.freedesktop.org/series/37764/
State : success

== Summary ==

Test perf:
Subgroup enable-disable:
fail   -> PASS   (shard-apl) fdo#103715
Subgroup buffer-fill:
fail   -> PASS   (shard-apl) fdo#103755
Test kms_mmap_write_crc:
skip   -> PASS   (shard-apl)
Test gem_eio:
Subgroup in-flight-contexts:
pass   -> DMESG-WARN (shard-snb) fdo#104058
Test gem_exec_schedule:
Subgroup reorder-wide-vebox:
incomplete -> PASS   (shard-apl) fdo#102848

fdo#103715 https://bugs.freedesktop.org/show_bug.cgi?id=103715
fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755
fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058
fdo#102848 https://bugs.freedesktop.org/show_bug.cgi?id=102848

shard-apltotal:3383 pass:1753 dwarn:1   dfail:0   fail:20  skip:1608 
time:12195s
shard-hswtotal:3442 pass:1758 dwarn:1   dfail:0   fail:11  skip:1671 
time:11787s
shard-snbtotal:3442 pass:1350 dwarn:2   dfail:0   fail:10  skip:2080 
time:6558s
Blacklisted hosts:
shard-kbltotal:3442 pass:1898 dwarn:10  dfail:1   fail:23  skip:1510 
time:9658s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7914/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915: Reject undefined colorkey flags

[Chris Wilson]

Quoting Ville Syrjala (2018-02-06 20:43:33)
> From: Ville Syrjälä 
> 
> Check that userspace isn't passing in garbage in the colorkey
> ioctl flags.
> 
> Signed-off-by: Ville Syrjälä 

I think we can retrospectively apply this filter. Afaict, only the ddx
ever hooked up this interface.

Reviewed-by: Chris Wilson 
-Chris
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Re: [Intel-gfx] [PATCH v8 1/6] drm/i915/guc: Move GuC WOPCM related code into separate files

[Michal Wajdeczko]

On Tue, 06 Feb 2018 06:15:54 +0100, Sagar Arun Kamble  
 wrote:




On 2/6/2018 5:32 AM, Jackie Li wrote:

intel_guc_reg.h should only include definition for GuC registers and
related register bits. Non-register related GuC WOPCM macro definitions
should not be defined in intel_guc_reg.h

This patch creates a better file structure by moving non-register  
related
GuC WOPCM macro definitions into a new header intel_guc_wopcm.h and  
moving

GuC WOPCM related functions to a new source file intel_guc_wopcm.c as
future patches will increase the complexity of determining the GuC WOPCM
offset and size.


Hmm, I'm not sure that we need such low-details explanation that repeats
filenames listed below. Maybe it can like this:

"New file structure is needed as future patches will increase the
complexity of determining the GuC WOPCM offset and size."



v8:
  - Fixed naming, coding style issues and typo in commit message (Sagar)
  - Updated commit message to explain why we need create new file for  
GuC

WOPCM related code (Chris)

Cc: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Sagar Arun Kamble  (v7)
Signed-off-by: Jackie Li 

Minor change in function comment needed below as per kernel-doc format.
Otherwise, change is good.
Reviewed-by: Sagar Arun Kamble 

---
  drivers/gpu/drm/i915/Makefile  |  1 +
  drivers/gpu/drm/i915/intel_guc.c   | 11 
  drivers/gpu/drm/i915/intel_guc.h   |  2 +-
  drivers/gpu/drm/i915/intel_guc_reg.h   |  4 ---
  drivers/gpu/drm/i915/intel_guc_wopcm.c | 46  
++
  drivers/gpu/drm/i915/intel_guc_wopcm.h | 39  


  drivers/gpu/drm/i915/intel_uc.c|  2 +-
  drivers/gpu/drm/i915/intel_uc_fw.c |  2 +-
  8 files changed, 89 insertions(+), 18 deletions(-)
  create mode 100644 drivers/gpu/drm/i915/intel_guc_wopcm.c
  create mode 100644 drivers/gpu/drm/i915/intel_guc_wopcm.h

diff --git a/drivers/gpu/drm/i915/Makefile  
b/drivers/gpu/drm/i915/Makefile

index 3bddd8a..1dc9988 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -88,6 +88,7 @@ i915-y += intel_uc.o \
  intel_guc_fw.o \
  intel_guc_log.o \
  intel_guc_submission.o \
+ intel_guc_wopcm.o \
  intel_huc.o
# autogenerated null render state
diff --git a/drivers/gpu/drm/i915/intel_guc.c  
b/drivers/gpu/drm/i915/intel_guc.c

index 21140cc..9f45e6d 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -509,14 +509,3 @@ struct i915_vma *intel_guc_allocate_vma(struct  
intel_guc *guc, u32 size)

i915_gem_object_put(obj);
return vma;
  }
-
-u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
-{
-   u32 wopcm_size = GUC_WOPCM_TOP;
-
-   /* On BXT, the top of WOPCM is reserved for RC6 context */
-   if (IS_GEN9_LP(dev_priv))
-   wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
-
-   return wopcm_size;
-}
diff --git a/drivers/gpu/drm/i915/intel_guc.h  
b/drivers/gpu/drm/i915/intel_guc.h

index 52856a9..9e0a97e 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -31,6 +31,7 @@
  #include "intel_guc_ct.h"
  #include "intel_guc_log.h"
  #include "intel_guc_reg.h"
+#include "intel_guc_wopcm.h"
  #include "intel_uc_fw.h"
  #include "i915_vma.h"
  @@ -130,6 +131,5 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32  
rsa_offset);

  int intel_guc_suspend(struct drm_i915_private *dev_priv);
  int intel_guc_resume(struct drm_i915_private *dev_priv);
  struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32  
size);

-u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
#endif
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h  
b/drivers/gpu/drm/i915/intel_guc_reg.h

index 19a9247..1f52fb8 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -68,7 +68,6 @@
  #define DMA_GUC_WOPCM_OFFSET  _MMIO(0xc340)
  #define   HUC_LOADING_AGENT_VCR (0<<1)
  #define   HUC_LOADING_AGENT_GUC (1<<1)
-#define   GUC_WOPCM_OFFSET_VALUE 0x8   /* 512KB */
  #define GUC_MAX_IDLE_COUNT_MMIO(0xC3E4)
#define HUC_STATUS2 _MMIO(0xD3B0)
@@ -76,9 +75,6 @@
/* Defines WOPCM space available to GuC firmware */
  #define GUC_WOPCM_SIZE_MMIO(0xc050)
-/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
-#define   GUC_WOPCM_TOP  (0x80 << 12)/* 512KB */
-#define   BXT_GUC_WOPCM_RC6_RESERVED (0x10 << 12)/* 64KB  */
/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT  
*/

  #define GUC_GGTT_TOP  

Re: [Intel-gfx] [PATCH v2] drm/i915/pmu: Fix sleep under atomic in RC6 readout

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-06 18:33:11)
> From: Tvrtko Ursulin 
> 
> We are not allowed to call intel_runtime_pm_get from the PMU counter read
> callback since the former can sleep, and the latter is running under IRQ
> context.
> 
> To workaround this, we record the last known RC6 and while runtime
> suspended estimate its increase by querying the runtime PM core
> timestamps.
> 
> Downside of this approach is that we can temporarily lose a chunk of RC6
> time, from the last PMU read-out to runtime suspend entry, but that will
> eventually catch up, once device comes back online and in the presence of
> PMU queries.
> 
> Also, we have to be careful not to overshoot the RC6 estimate, so once
> resumed after a period of approximation, we only update the counter once
> it catches up. With the observation that RC6 is increasing while the
> device is suspended, this should not pose a problem and can only cause
> slight inaccuracies due clock base differences.
> 
> v2: Simplify by estimating on top of PM core counters. (Imre)
> 
> Signed-off-by: Tvrtko Ursulin 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104943
> Fixes: 6060b6aec03c ("drm/i915/pmu: Add RC6 residency metrics")
> Testcase: igt/perf_pmu/rc6-runtime-pm
> Cc: Tvrtko Ursulin 
> Cc: Chris Wilson 
> Cc: Imre Deak 
> Cc: Jani Nikula 
> Cc: Joonas Lahtinen 
> Cc: Rodrigo Vivi 
> Cc: David Airlie 
> Cc: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> ---
>  drivers/gpu/drm/i915/i915_pmu.c | 93 
> ++---
>  drivers/gpu/drm/i915/i915_pmu.h |  6 +++
>  2 files changed, 84 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> index 1c440460255d..bfc402d47609 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -415,7 +415,81 @@ static int i915_pmu_event_init(struct perf_event *event)
> return 0;
>  }
>  
> -static u64 __i915_pmu_event_read(struct perf_event *event)
> +static u64 get_rc6(struct drm_i915_private *i915, bool locked)
> +{
> +   unsigned long flags;
> +   u64 val;
> +
> +   if (intel_runtime_pm_get_if_in_use(i915)) {
> +   val = intel_rc6_residency_ns(i915, IS_VALLEYVIEW(i915) ?
> +  VLV_GT_RENDER_RC6 :
> +  GEN6_GT_GFX_RC6);
> +
> +   if (HAS_RC6p(i915))
> +   val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
> +
> +   if (HAS_RC6pp(i915))
> +   val += intel_rc6_residency_ns(i915, 
> GEN6_GT_GFX_RC6pp);
> +
> +   intel_runtime_pm_put(i915);
> +
> +   /*
> +* If we are coming back from being runtime suspended we must
> +* be careful not to report a larger value than returned
> +* previously.
> +*/
> +
> +   if (!locked)
> +   spin_lock_irqsave(>pmu.lock, flags);
> +
> +   if (val >= i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur) 
> {
> +   i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = 0;
> +   i915->pmu.sample[__I915_SAMPLE_RC6].cur = val;
> +   } else {
> +   val = 
> i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur;
> +   }
> +
> +   if (!locked)
> +   spin_unlock_irqrestore(>pmu.lock, flags);
> +   } else {
> +   struct pci_dev *pdev = i915->drm.pdev;
> +   struct device *kdev = >dev;
> +   unsigned long flags2;
> +
> +   /*
> +* We are runtime suspended.
> +*
> +* Report the delta from when the device was suspended to now,
> +* on top of the last known real value, as the approximated 
> RC6
> +* counter value.
> +*/
> +   if (!locked)
> +   spin_lock_irqsave(>pmu.lock, flags);
> +
> +   spin_lock_irqsave(>power.lock, flags2);
> +
> +   if (!i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur)
> +   i915->pmu.suspended_jiffies_last =
> +   kdev->power.suspended_jiffies;
> +
> +   val = kdev->power.suspended_jiffies -
> + i915->pmu.suspended_jiffies_last;
> +   val += jiffies - kdev->power.accounting_timestamp;
> +
> +   spin_unlock_irqrestore(>power.lock, flags2);
> +
> +   val = jiffies_to_nsecs(val);
> +   val += i915->pmu.sample[__I915_SAMPLE_RC6].cur;
> 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Reject undefined colorkey flags

[Patchwork]

== Series Details ==

Series: drm/i915: Reject undefined colorkey flags
URL   : https://patchwork.freedesktop.org/series/37764/
State : success

== Summary ==

Series 37764v1 drm/i915: Reject undefined colorkey flags
https://patchwork.freedesktop.org/api/1.0/series/37764/revisions/1/mbox/

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:417s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:422s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:379s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:488s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:480s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:483s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:467s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:454s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:566s
fi-cnl-y3total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:565s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:409s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:282s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:512s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:390s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:404s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:409s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:457s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:415s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:454s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:492s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:450s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:499s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:590s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:428s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:507s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:527s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:488s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:479s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:414s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:429s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:513s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:393s
Blacklisted hosts:
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:471s

078873da383505cf8d6940229007115b31f1d5e0 drm-tip: 2018y-02m-06d-11h-21m-36s UTC 
integration manifest
868a33e89cff drm/i915: Reject undefined colorkey flags

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7914/issues.html
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[Intel-gfx] [PATCH] drm/i915: Reject undefined colorkey flags

[Ville Syrjala]

From: Ville Syrjälä 

Check that userspace isn't passing in garbage in the colorkey
ioctl flags.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_sprite.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 3be22c0fcfb5..12a9536d7b7a 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1077,6 +1077,9 @@ int intel_sprite_set_colorkey(struct drm_device *dev, 
void *data,
/* ignore the pointless "none" flag */
set->flags &= ~I915_SET_COLORKEY_NONE;
 
+   if (set->flags & ~(I915_SET_COLORKEY_DESTINATION | 
I915_SET_COLORKEY_SOURCE))
+   return -EINVAL;
+
/* Make sure we don't try to enable both src & dest simultaneously */
if ((set->flags & (I915_SET_COLORKEY_DESTINATION | 
I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | 
I915_SET_COLORKEY_SOURCE))
return -EINVAL;
-- 
2.13.6

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Re: [Intel-gfx] [PATCH] drm/i915/ivb+: Use the correct render forcewake ACK register

[Chris Wilson]

Quoting Imre Deak (2018-02-06 18:20:07)
> FORCEWAKE_ACK is depricated by BSpec at least starting from BDW,
> referring to the multi-threaded version of it instead. Accessing
> FORCEWAKE_ACK triggers an unclaimed register access error - at
> least on GLK - see the Reference: below.
> 
> As opposed to this debugfs file we normally use the MT version on IVB
> (if supported) and HSW/BDW, whereas we use FORCEWAKE_ACK_RENDER_GEN9
> starting from SKL. Fix the problem by using these same registers on
> each platform in the debugfs file too.
> 
> Cc: Ville Syrjälä 
> Cc: Chris Wilson 
> Cc: Mika Kuoppala 
> Reference: https://bugs.freedesktop.org/show_bug.cgi?id=103337
> Signed-off-by: Imre Deak 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 7 +--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 3849ded354e3..8a019cb0980d 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1458,18 +1458,21 @@ static int vlv_drpc_info(struct seq_file *m)
>  static int gen6_drpc_info(struct seq_file *m)
>  {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> +   struct intel_uncore_forcewake_domain *render_domain =
> +   _priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER];
> u32 gt_core_status, rcctl1, rc6vids = 0;
> u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
> unsigned forcewake_count;
> int count = 0;
>  
> -   forcewake_count = 
> READ_ONCE(dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count);
> +   forcewake_count = READ_ONCE(render_domain->wake_count);
> if (forcewake_count) {
> seq_puts(m, "RC information inaccurate because somebody "
> "holds a forcewake reference \n");
> } else {
> /* NB: we cannot use forcewake, else we read the wrong values 
> */
> -   while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
> +   while (count++ < 50 &&
> +  (I915_READ_NOTRACE(render_domain->reg_ack) & 1))
> udelay(10);
> seq_printf(m, "RC information accurate: %s\n", yesno(count < 
> 51));

I remember having a rant about this being absolutely meaningless. We can
just delete it imo.
-Chris
> 
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[Intel-gfx] ✗ Fi.CI.BAT: warning for ICL display initialization, selected patches (rev3)

[Patchwork]

== Series Details ==

Series: ICL display initialization, selected patches (rev3)
URL   : https://patchwork.freedesktop.org/series/37668/
State : warning

== Summary ==

Series 37668v3 ICL display initialization, selected patches
https://patchwork.freedesktop.org/api/1.0/series/37668/revisions/3/mbox/

Test gem_sync:
Subgroup basic-all:
pass   -> SKIP   (fi-pnv-d510)
Subgroup basic-each:
pass   -> SKIP   (fi-pnv-d510)
Subgroup basic-many-each:
pass   -> SKIP   (fi-pnv-d510)
Subgroup basic-store-all:
pass   -> SKIP   (fi-pnv-d510)
Subgroup basic-store-each:
pass   -> SKIP   (fi-pnv-d510)
Test gem_tiled_blits:
Subgroup basic:
pass   -> SKIP   (fi-pnv-d510)
Test gem_tiled_fence_blits:
Subgroup basic:
pass   -> SKIP   (fi-pnv-d510)
Test gem_wait:
Subgroup basic-busy-all:
pass   -> SKIP   (fi-pnv-d510)
Subgroup basic-wait-all:
pass   -> SKIP   (fi-pnv-d510)
Subgroup basic-await-all:
pass   -> SKIP   (fi-pnv-d510)
Test kms_busy:
Subgroup basic-flip-a:
pass   -> SKIP   (fi-pnv-d510)
Subgroup basic-flip-b:
pass   -> SKIP   (fi-pnv-d510)
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
pass   -> SKIP   (fi-pnv-d510)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:417s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:421s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:374s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:480s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:481s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:484s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:468s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:453s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:563s
fi-cnl-y3total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:576s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:413s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:288s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:511s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:389s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:400s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:412s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:456s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:416s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:455s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:493s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:455s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:498s
fi-pnv-d510  total:288  pass:209  dwarn:1   dfail:0   fail:0   skip:78  
time:566s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:429s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:504s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:530s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:490s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:468s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:415s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:427s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:401s
Blacklisted hosts:
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:467s

078873da383505cf8d6940229007115b31f1d5e0 drm-tip: 2018y-02m-06d-11h-21m-36s UTC 
integration manifest
bc7626231687 drm/i915/icl: program mbus during pipe enable
c5685a5e3c0a drm/i915/icl: initialize MBus during display init
1e49c3e1a31d drm/i915/icl: Enable both DBuf slices during init
997836294f3f drm/i915/icl: implement the display init/uninit 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/ivb+: Use the correct render forcewake ACK register

[Patchwork]

== Series Details ==

Series: drm/i915/ivb+: Use the correct render forcewake ACK register
URL   : https://patchwork.freedesktop.org/series/37753/
State : success

== Summary ==

Test gem_exec_schedule:
Subgroup reorder-wide-vebox:
incomplete -> PASS   (shard-apl) fdo#102848
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-apl) fdo#99912
Test perf:
Subgroup enable-disable:
fail   -> PASS   (shard-apl) fdo#103715
Subgroup buffer-fill:
fail   -> PASS   (shard-apl) fdo#103755

fdo#102848 https://bugs.freedesktop.org/show_bug.cgi?id=102848
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#103715 https://bugs.freedesktop.org/show_bug.cgi?id=103715
fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755

shard-apltotal:3383 pass:1753 dwarn:1   dfail:0   fail:19  skip:1609 
time:12156s
shard-hswtotal:3442 pass:1758 dwarn:1   dfail:0   fail:11  skip:1671 
time:11756s
shard-snbtotal:3442 pass:1351 dwarn:1   dfail:0   fail:10  skip:2080 
time:6621s
Blacklisted hosts:
shard-kbltotal:3442 pass:1909 dwarn:1   dfail:0   fail:21  skip:1511 
time:9635s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7911/shards.html
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Re: [Intel-gfx] [PULL] gvt-next-fixes for 4.16

[Rodrigo Vivi]

Hi Zhi,

Daniel asked few weeks ago about the scripts that you run there,
but I didn't see any follow-up.

I don't understand why yet, but apparently gvt pull request
is not going to patchwork so dim is not able to add the "Link:"
hence end up without mandatory patchwork links.

Last round I by-pass dim and move forward even without the "Link:"
if the solution is easier I'd like to do the right thing this time.

Although I'm open to by-pass again,
I'd like to know if we are in sync to understand what is happening
again and get that fixed for next time

Cc: Daniel in case he know a quick fix or can at least provide more
info there on what could be failing.

Thanks,
Rodrigo.


On Tue, Feb 06, 2018 at 08:36:49AM +, Zhi Wang wrote:
> Hi guys:
> Here are the latest gvt-next-fixes pull. It contains vGPU reset
> enhancement, which refines vGPU reset flow and the support of virtual
> aperture read/write when x-no-mmap=on is set in KVM, which is required by a
> test case from Redhat and also another fix for virtual OpRegion.
> 
> Thanks,
> Zhi.
> 
> The following changes since commit 751b01cb07ebf0dbbe4a4fbfeaa509388e4a2b0a:
> 
>   drm/i915/ppgtt: Pin page directories before allocation (2018-02-01
> 07:33:04 -0800)
> 
> are available in the git repository at:
> 
>   http://github.com/intel/gvt-linux.git tags/gvt-next-fixes-2018-02-04
> 
> for you to fetch changes up to 47419494f216812b42f5d1c5a2984cd46253b4cc:
> 
>   drm/i915/gvt: Use KVM r/w to access guest opregion (2018-02-06 13:14:47
> +0800)
> 
> 
> - vGPU reset refinement. (Weinan)
> - Support aperture read/write emulation when x-no-mmap=on. (Changbin)
> - Use guest memory read/write in GVT MPT to access OpRegion. (Tina)
> 
> 
> Changbin Du (1):
>   drm/i915/gvt: Fix aperture read/write emulation when enable
> x-no-mmap=on
> 
> Tina Zhang (1):
>   drm/i915/gvt: Use KVM r/w to access guest opregion
> 
> Weinan Li (2):
>   drm/i915/gvt: refine intel_vgpu_submission_ops as per engine ops
>   drm/i915/gvt: only reset execlist state of one engine during VM engine
> reset
> 
>  drivers/gpu/drm/i915/gvt/cfg_space.c| 15 +
>  drivers/gpu/drm/i915/gvt/execlist.c | 22 
>  drivers/gpu/drm/i915/gvt/gvt.h  |  6 +-
>  drivers/gpu/drm/i915/gvt/handlers.c |  7 +--
>  drivers/gpu/drm/i915/gvt/kvmgt.c| 36 +++-
>  drivers/gpu/drm/i915/gvt/mmio.c | 42 --
>  drivers/gpu/drm/i915/gvt/opregion.c | 98
> +++--
>  drivers/gpu/drm/i915/gvt/sched_policy.c | 14 -
>  drivers/gpu/drm/i915/gvt/scheduler.c| 19 ---
>  drivers/gpu/drm/i915/gvt/scheduler.h|  1 +
>  drivers/gpu/drm/i915/gvt/vgpu.c |  3 +-
>  11 files changed, 144 insertions(+), 119 deletions(-)
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[Intel-gfx] [PATCH 2/6] drm/i915/icl: add the main CDCLK functions

[Paulo Zanoni]

This commit adds the basic CDCLK functions, but it's still missing
pieces of the display initialization sequence.

v2:
 - Implement the voltage levels.
 - Rebase.
v3:
 - Adjust to the new "bypass" clock (Imre).
 - Call intel_dump_cdclk_state() too.
 - Rename a variable to avoid confusion.
 - Simplify the DVFS part.
v4:
 - Remove wrong bit definition (James).
 - Also drive-by fix the coding style for the register definition we
   touched.
v5:
 - Comment style (checkpatch).

Cc: James Ausmus 
Cc: Imre Deak 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_reg.h|  35 +++---
 drivers/gpu/drm/i915/intel_cdclk.c | 237 -
 drivers/gpu/drm/i915/intel_drv.h   |   2 +
 3 files changed, 257 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 58057affa133..023ecb844328 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7182,8 +7182,12 @@ enum {
 #define SKL_DFSM_PIPE_B_DISABLE(1 << 21)
 #define SKL_DFSM_PIPE_C_DISABLE(1 << 28)
 
-#define SKL_DSSM   _MMIO(0x51004)
-#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz(1 << 31)
+#define SKL_DSSM   _MMIO(0x51004)
+#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz(1 << 31)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz(0 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz  (1 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz  (2 << 29)
 
 #define GEN7_FF_SLICE_CS_CHICKEN1  _MMIO(0x20e0)
 #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL(1<<14)
@@ -8816,20 +8820,21 @@ enum skl_power_gate {
 
 /* CDCLK_CTL */
 #define CDCLK_CTL  _MMIO(0x46000)
-#define  CDCLK_FREQ_SEL_MASK   (3<<26)
-#define  CDCLK_FREQ_450_432(0<<26)
-#define  CDCLK_FREQ_540(1<<26)
-#define  CDCLK_FREQ_337_308(2<<26)
-#define  CDCLK_FREQ_675_617(3<<26)
-#define  BXT_CDCLK_CD2X_DIV_SEL_MASK   (3<<22)
-#define  BXT_CDCLK_CD2X_DIV_SEL_1  (0<<22)
-#define  BXT_CDCLK_CD2X_DIV_SEL_1_5(1<<22)
-#define  BXT_CDCLK_CD2X_DIV_SEL_2  (2<<22)
-#define  BXT_CDCLK_CD2X_DIV_SEL_4  (3<<22)
-#define  BXT_CDCLK_CD2X_PIPE(pipe) ((pipe)<<20)
-#define  CDCLK_DIVMUX_CD_OVERRIDE  (1<<19)
+#define  CDCLK_FREQ_SEL_MASK   (3 << 26)
+#define  CDCLK_FREQ_450_432(0 << 26)
+#define  CDCLK_FREQ_540(1 << 26)
+#define  CDCLK_FREQ_337_308(2 << 26)
+#define  CDCLK_FREQ_675_617(3 << 26)
+#define  BXT_CDCLK_CD2X_DIV_SEL_MASK   (3 << 22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_1  (0 << 22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_1_5(1 << 22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_2  (2 << 22)
+#define  BXT_CDCLK_CD2X_DIV_SEL_4  (3 << 22)
+#define  BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
+#define  CDCLK_DIVMUX_CD_OVERRIDE  (1 << 19)
 #define  BXT_CDCLK_CD2X_PIPE_NONE  BXT_CDCLK_CD2X_PIPE(3)
-#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE(1<<16)
+#define  ICL_CDCLK_CD2X_PIPE_NONE  (7 << 19)
+#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE(1 << 16)
 #define  CDCLK_FREQ_DECIMAL_MASK   (0x7ff)
 
 /* LCPLL_CTL */
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
b/drivers/gpu/drm/i915/intel_cdclk.c
index ee788d5be5e3..0256198c7519 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1778,6 +1778,199 @@ static void cnl_sanitize_cdclk(struct drm_i915_private 
*dev_priv)
dev_priv->cdclk.hw.vco = -1;
 }
 
+static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
+{
+   int ranges_24[] = { 312000, 552000, 648000 };
+   int ranges_19_38[] = { 307200, 556800, 652800 };
+   int *ranges;
+
+   switch (ref) {
+   default:
+   MISSING_CASE(ref);
+   case 24000:
+   ranges = ranges_24;
+   break;
+   case 19200:
+   case 38400:
+   ranges = ranges_19_38;
+   break;
+   }
+
+   if (min_cdclk > ranges[1])
+   return ranges[2];
+   else if (min_cdclk > ranges[0])
+   return ranges[1];
+   else
+   return ranges[0];
+}
+
+static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
+{
+   int ratio;
+
+   if (cdclk == dev_priv->cdclk.hw.bypass)
+   return 0;
+
+   switch (cdclk) {
+   default:
+   MISSING_CASE(cdclk);
+   case 307200:
+   case 556800:
+   case 652800:
+   WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
+   dev_priv->cdclk.hw.ref != 38400);
+   break;
+   case 312000:
+   case 552000:
+   case 648000:
+   WARN_ON(dev_priv->cdclk.hw.ref != 24000);
+   }
+
+  

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Fix sleep under atomic in RC6 readout (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/pmu: Fix sleep under atomic in RC6 readout (rev2)
URL   : https://patchwork.freedesktop.org/series/37742/
State : success

== Summary ==

Series 37742v2 drm/i915/pmu: Fix sleep under atomic in RC6 readout
https://patchwork.freedesktop.org/api/1.0/series/37742/revisions/2/mbox/

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:418s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:433s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:373s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:483s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:483s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:467s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:458s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:562s
fi-cnl-y3total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:580s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:409s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:281s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:518s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:390s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:396s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:412s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:455s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:425s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:455s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:496s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:458s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:501s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:602s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:430s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:502s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:526s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:485s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:479s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:421s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:429s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:523s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:395s
Blacklisted hosts:
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:468s

078873da383505cf8d6940229007115b31f1d5e0 drm-tip: 2018y-02m-06d-11h-21m-36s UTC 
integration manifest
f25697778bd9 drm/i915/pmu: Fix sleep under atomic in RC6 readout

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7912/issues.html
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ivb+: Use the correct render forcewake ACK register

[Patchwork]

== Series Details ==

Series: drm/i915/ivb+: Use the correct render forcewake ACK register
URL   : https://patchwork.freedesktop.org/series/37753/
State : success

== Summary ==

Series 37753v1 drm/i915/ivb+: Use the correct render forcewake ACK register
https://patchwork.freedesktop.org/api/1.0/series/37753/revisions/1/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:421s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:426s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:373s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:485s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:483s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:481s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:467s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:456s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:574s
fi-cnl-y3total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:585s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:413s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:282s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:514s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:387s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:397s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:412s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:450s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:419s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:459s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:497s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:455s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:498s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:595s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:426s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:507s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:528s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:491s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:491s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:415s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:426s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:393s
Blacklisted hosts:
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:471s

078873da383505cf8d6940229007115b31f1d5e0 drm-tip: 2018y-02m-06d-11h-21m-36s UTC 
integration manifest
65ce7e1ae597 drm/i915/ivb+: Use the correct render forcewake ACK register

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7911/issues.html
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Re: [Intel-gfx] [PATCH] sna: CustomEDID fix

[dom . constant]

> Quoting dom.const...@free.fr (2018-02-02 18:37:12)
> > Hello,
> > 
> > For my HTPC setup, I'm using the option "CustomEDID".
> > With this option, output attaching and destroying events leads to
> > crashes.
> > 
> > The following sequence leads to a crash:
> > - In xorg.conf: Option "CustomEDID" "HDMI2:/etc/my_edid.bin"
> > - Starting Xorg
> > - Connect HDMI2
> > - Disconnect HDMI2
> > - Reconnect HDMI2
> >   -> Crash
> > 
> > 
> > The crash happens in xf86OutputSetEDID
> > (xorg/xserver/hw/xfree86/modes/xf86Crtc.c)
> > at "free(output->MonInfo)". MonInfo is assigned with
> > sna_output->fake_edid_mon
> > which is allocated by intel driver in sna_output_load_fake_edid
> > (src/sna/sna_display.c).
> > 
> > 
> > Sequence details:
> > - Starting Xorg
> >-> fake_edid_mon is initialized
> > 
> > - Connect HDMI2
> >-> xf86OutputSetEDID is called:
> >- MonInfo is NULL
> >- MonInfo is assigned with fake_edid_mon pointer
> >- MonInfo is read by Xorg
> > 
> > - Disconnect HDMI2
> > 
> > - Reconnect HDMI2
> >-> xf86OutputSetEDID is called:
> >- MonInfo is freed thus also fake_edid_mon
> >- MonInfo is assigned with fake_edid_mon
> >- MonInfo is read but it was freed -> CRASH
> > 
> > 
> > The fix consists of a new instance of xf86MonPtr for each calls of
> > xf86OutputSetEDID.
> > This instance is initialized with fake_edid_raw which render
> > fake_edid_mon useless.
> > With this proposal, the behaviour of an EDID override is similar to
> > a "real" EDID.
> > 
> > Regards,
> > 
> > 
> > Signed-off-by: Dominique Constant 
> > To: Chris Wilson 
> 
> Apologies if this is a resend, but could you send me this patch using
> "git send-email" (or attach the output of "git format-patch"). git am
> is not happy with it.
> -Chris
> 


Hello,
Thank you for taking into consideration this patch.

Regards,

Dominique CONSTANT

Signed-off-by: Dominique Constant 
---
 src/sna/sna_display.c | 28 
 1 file changed, 12 insertions(+), 16 deletions(-)

diff --git a/src/sna/sna_display.c b/src/sna/sna_display.c
index ea2f148d..ad805c2f 100644
--- a/src/sna/sna_display.c
+++ b/src/sna/sna_display.c
@@ -263,7 +263,6 @@ struct sna_output {
uint32_t edid_blob_id;
uint32_t edid_len;
void *edid_raw;
-   xf86MonPtr fake_edid_mon;
void *fake_edid_raw;
 
bool has_panel_limits;
@@ -4102,13 +4101,21 @@ static DisplayModePtr
 sna_output_override_edid(xf86OutputPtr output)
 {
struct sna_output *sna_output = output->driver_private;
+   xf86MonPtr mon = NULL;
+
+   if (sna_output->fake_edid_raw == NULL)
+   return NULL;
 
-   if (sna_output->fake_edid_mon == NULL)
+   mon = xf86InterpretEDID(output->scrn->scrnIndex, 
sna_output->fake_edid_raw);
+   if (mon == NULL) {
return NULL;
+   }
+
+   mon->flags |= MONITOR_EDID_COMPLETE_RAWDATA;
+
+   xf86OutputSetEDID(output, mon);
 
-   xf86OutputSetEDID(output, sna_output->fake_edid_mon);
-   return xf86DDCGetModes(output->scrn->scrnIndex,
-  sna_output->fake_edid_mon);
+   return xf86DDCGetModes(output->scrn->scrnIndex, mon);
 }
 
 static DisplayModePtr
@@ -4896,7 +4903,6 @@ sna_output_load_fake_edid(xf86OutputPtr output)
FILE *file;
void *raw;
int size;
-   xf86MonPtr mon;
 
filename = fake_edid_name(output);
if (filename == NULL)
@@ -4928,16 +4934,6 @@ sna_output_load_fake_edid(xf86OutputPtr output)
}
fclose(file);
 
-   mon = xf86InterpretEDID(output->scrn->scrnIndex, raw);
-   if (mon == NULL) {
-   free(raw);
-   goto err;
-   }
-
-   if (mon && size > 128)
-   mon->flags |= MONITOR_EDID_COMPLETE_RAWDATA;
-
-   sna_output->fake_edid_mon = mon;
sna_output->fake_edid_raw = raw;
 
xf86DrvMsg(output->scrn->scrnIndex, X_CONFIG,
-- 
2.15.1


___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/10] drm/vblank: Data type fixes for 64-bit vblank sequences.

[Patchwork]

== Series Details ==

Series: series starting with [01/10] drm/vblank: Data type fixes for 64-bit 
vblank sequences.
URL   : https://patchwork.freedesktop.org/series/37598/
State : success

== Summary ==

Series 37598v1 series starting with [01/10] drm/vblank: Data type fixes for 
64-bit vblank sequences.
https://patchwork.freedesktop.org/api/1.0/series/37598/revisions/1/mbox/

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:420s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:427s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:376s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:492s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:487s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:486s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:471s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:459s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:564s
fi-cnl-y3total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:575s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:412s
fi-gdg-551   total:288  pass:180  dwarn:0   dfail:0   fail:0   skip:108 
time:283s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:515s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:390s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:405s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:413s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:449s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:429s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:456s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:500s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:457s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:501s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:598s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:429s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:509s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:531s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:486s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:480s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:415s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:429s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:527s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:399s
Blacklisted hosts:
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:473s

078873da383505cf8d6940229007115b31f1d5e0 drm-tip: 2018y-02m-06d-11h-21m-36s UTC 
integration manifest
1fbe766c4e29 drm/i915: Estimate and update missed vblanks.
93f6ed7165be drm/vblank: Restoring vblank counts after device PM events.
9dcfd30f84de drm/vblank: Do not update vblank count if interrupts are already 
disabled.
f5009e90de2e drm/atomic: Handle 64-bit return from drm_crtc_vblank_count()
24fe6af8f870 drm/tegra: Handle 64-bit return from drm_crtc_vblank_count()
4f811089d445 drm/radeon: Handle 64-bit return from drm_crtc_vblank_count()
51f4675db99e drm/amdgpu: Handle 64-bit return from drm_crtc_vblank_count()
abc0899cc109 drm/i915: Handle 64-bit return from drm_crtc_vblank_count()
42824daf49fe drm/i915/vblank: Make the vblank counter u64 -> u32 typecast 
explicit
5f830a5a47dc drm/vblank: Data type fixes for 64-bit vblank sequences.

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7910/issues.html
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Re: [Intel-gfx] [PATCH] drm/i915/audio: do not set Maud/Naud values manually on KBL

[Rodrigo Vivi]

On Tue, Feb 06, 2018 at 11:49:18AM +, Jani Nikula wrote:
> Apparently using the manual Maud/Naud mode does not work on KBL. The
> details on the failure mode are scarce, except that there's no audio,
> and there is obviously no idea on the root cause either. It is also
> unknown whether the failure can be reproduced on newer platforms in some
> scenarios.
> 
> The problem was introduced when switching from automatic mode to manual
> mode in commit 6014ac122ed0 ("drm/i915/audio: set proper N/M in
> modeset"). Instead of reverting that, disable the feature on KBL as a
> workaround.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104093
> Reported-by: Quanxian Wang 
> Fixes: 6014ac122ed0 ("drm/i915/audio: set proper N/M in modeset")
> Cc:  # v4.10+
> Cc: Keqiao Zhang 
> Cc: Ville Syrjälä 
> Cc: Mengdong Lin 
> Cc: Libin Yang 
> Cc: Rodrigo Vivi 
> Cc: Quanxian Wang 
> Cc: Wang Zhijun 
> Cc: Cui Yueping 
> Cc: Alice Liu 
> Cc: intel-gfx@lists.freedesktop.org
> Signed-off-by: Jani Nikula 
> 
> ---
> 
> UNTESTED. Please provide Tested-by's on the affected KBLs, but *also* on
> CFL, CNL, etc.
> ---
>  drivers/gpu/drm/i915/intel_audio.c | 11 +--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_audio.c 
> b/drivers/gpu/drm/i915/intel_audio.c
> index 522d54fecb53..b7634cff12b6 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -294,12 +294,19 @@ hsw_dp_audio_config_update(struct intel_encoder 
> *encoder,
>   struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>   enum port port = encoder->port;
>   enum pipe pipe = crtc->pipe;
> - const struct dp_aud_n_m *nm;
> + const struct dp_aud_n_m *nm = NULL;
>   int rate;
>   u32 tmp;
>  
>   rate = acomp ? acomp->aud_sample_rate[port] : 0;
> - nm = audio_config_dp_get_n_m(crtc_state, rate);
> +
> + /*
> +  * FIXME: For reasons still unknown, there seem to be issues with the
> +  * manual Maud/Naud mode on KBL.
> +  */
> + if (!IS_KABYLAKE(dev_priv))

Hmm... not much visibility on the audio gap between KBL and CFL.
But on our side I believe we should also apply it for CFL.

I wonder if some bugs audio guys are hunting now on CNL and ICL could
also be related to it.

Isn't revert the original an option?

> + nm = audio_config_dp_get_n_m(crtc_state, rate);
> +
>   if (nm)
>   DRM_DEBUG_KMS("using Maud %u, Naud %u\n", nm->m, nm->n);
>   else
> -- 
> 2.11.0
> 
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[Intel-gfx] [PATCH v2] drm/i915/pmu: Fix sleep under atomic in RC6 readout

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

We are not allowed to call intel_runtime_pm_get from the PMU counter read
callback since the former can sleep, and the latter is running under IRQ
context.

To workaround this, we record the last known RC6 and while runtime
suspended estimate its increase by querying the runtime PM core
timestamps.

Downside of this approach is that we can temporarily lose a chunk of RC6
time, from the last PMU read-out to runtime suspend entry, but that will
eventually catch up, once device comes back online and in the presence of
PMU queries.

Also, we have to be careful not to overshoot the RC6 estimate, so once
resumed after a period of approximation, we only update the counter once
it catches up. With the observation that RC6 is increasing while the
device is suspended, this should not pose a problem and can only cause
slight inaccuracies due clock base differences.

v2: Simplify by estimating on top of PM core counters. (Imre)

Signed-off-by: Tvrtko Ursulin 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104943
Fixes: 6060b6aec03c ("drm/i915/pmu: Add RC6 residency metrics")
Testcase: igt/perf_pmu/rc6-runtime-pm
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Imre Deak 
Cc: Jani Nikula 
Cc: Joonas Lahtinen 
Cc: Rodrigo Vivi 
Cc: David Airlie 
Cc: intel-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
---
 drivers/gpu/drm/i915/i915_pmu.c | 93 ++---
 drivers/gpu/drm/i915/i915_pmu.h |  6 +++
 2 files changed, 84 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 1c440460255d..bfc402d47609 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -415,7 +415,81 @@ static int i915_pmu_event_init(struct perf_event *event)
return 0;
 }
 
-static u64 __i915_pmu_event_read(struct perf_event *event)
+static u64 get_rc6(struct drm_i915_private *i915, bool locked)
+{
+   unsigned long flags;
+   u64 val;
+
+   if (intel_runtime_pm_get_if_in_use(i915)) {
+   val = intel_rc6_residency_ns(i915, IS_VALLEYVIEW(i915) ?
+  VLV_GT_RENDER_RC6 :
+  GEN6_GT_GFX_RC6);
+
+   if (HAS_RC6p(i915))
+   val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
+
+   if (HAS_RC6pp(i915))
+   val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);
+
+   intel_runtime_pm_put(i915);
+
+   /*
+* If we are coming back from being runtime suspended we must
+* be careful not to report a larger value than returned
+* previously.
+*/
+
+   if (!locked)
+   spin_lock_irqsave(>pmu.lock, flags);
+
+   if (val >= i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur) {
+   i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = 0;
+   i915->pmu.sample[__I915_SAMPLE_RC6].cur = val;
+   } else {
+   val = i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur;
+   }
+
+   if (!locked)
+   spin_unlock_irqrestore(>pmu.lock, flags);
+   } else {
+   struct pci_dev *pdev = i915->drm.pdev;
+   struct device *kdev = >dev;
+   unsigned long flags2;
+
+   /*
+* We are runtime suspended.
+*
+* Report the delta from when the device was suspended to now,
+* on top of the last known real value, as the approximated RC6
+* counter value.
+*/
+   if (!locked)
+   spin_lock_irqsave(>pmu.lock, flags);
+
+   spin_lock_irqsave(>power.lock, flags2);
+
+   if (!i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur)
+   i915->pmu.suspended_jiffies_last =
+   kdev->power.suspended_jiffies;
+
+   val = kdev->power.suspended_jiffies -
+ i915->pmu.suspended_jiffies_last;
+   val += jiffies - kdev->power.accounting_timestamp;
+
+   spin_unlock_irqrestore(>power.lock, flags2);
+
+   val = jiffies_to_nsecs(val);
+   val += i915->pmu.sample[__I915_SAMPLE_RC6].cur;
+   i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = val;
+
+   if (!locked)
+   spin_unlock_irqrestore(>pmu.lock, flags);
+   }
+
+   return val;
+}
+
+static u64 __i915_pmu_event_read(struct perf_event *event, bool locked)
 {

[Intel-gfx] [PATCH] drm/i915/ivb+: Use the correct render forcewake ACK register

[Imre Deak]

FORCEWAKE_ACK is depricated by BSpec at least starting from BDW,
referring to the multi-threaded version of it instead. Accessing
FORCEWAKE_ACK triggers an unclaimed register access error - at
least on GLK - see the Reference: below.

As opposed to this debugfs file we normally use the MT version on IVB
(if supported) and HSW/BDW, whereas we use FORCEWAKE_ACK_RENDER_GEN9
starting from SKL. Fix the problem by using these same registers on
each platform in the debugfs file too.

Cc: Ville Syrjälä 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
Reference: https://bugs.freedesktop.org/show_bug.cgi?id=103337
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 3849ded354e3..8a019cb0980d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1458,18 +1458,21 @@ static int vlv_drpc_info(struct seq_file *m)
 static int gen6_drpc_info(struct seq_file *m)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
+   struct intel_uncore_forcewake_domain *render_domain =
+   _priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER];
u32 gt_core_status, rcctl1, rc6vids = 0;
u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
unsigned forcewake_count;
int count = 0;
 
-   forcewake_count = 
READ_ONCE(dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count);
+   forcewake_count = READ_ONCE(render_domain->wake_count);
if (forcewake_count) {
seq_puts(m, "RC information inaccurate because somebody "
"holds a forcewake reference \n");
} else {
/* NB: we cannot use forcewake, else we read the wrong values */
-   while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
+   while (count++ < 50 &&
+  (I915_READ_NOTRACE(render_domain->reg_ack) & 1))
udelay(10);
seq_printf(m, "RC information accurate: %s\n", yesno(count < 
51));
}
-- 
2.13.2

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Re: [Intel-gfx] [PATCH] drm/i915/breadcrumbs: Ignore unsubmitted signalers

[Chris Wilson]

Quoting Chris Wilson (2018-02-06 09:46:33)
> When a request is preempted, it is unsubmitted from the HW queue and
> removed from the active list of breadcrumbs. In the process, this
> however triggers the signaler and it may see the clear rbtree with the
> old, and still valid, seqno. This confuses the signaler into action and
> signaling the fence.
> 
> Fixes: d6a2289d9d6b ("drm/i915: Remove the preempted request from the 
> execution queue")
> Signed-off-by: Chris Wilson 
> Cc: Tvrtko Ursulin 
> Cc: Joonas Lahtinen 
> Cc:  # v4.12+

Any takers for this brown paper bug?

> ---
>  drivers/gpu/drm/i915/intel_breadcrumbs.c | 20 
>  1 file changed, 4 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c 
> b/drivers/gpu/drm/i915/intel_breadcrumbs.c
> index efbc627a2a25..b955f7d7bd0f 100644
> --- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
> +++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
> @@ -588,29 +588,16 @@ void intel_engine_remove_wait(struct intel_engine_cs 
> *engine,
> spin_unlock_irq(>rb_lock);
>  }
>  
> -static bool signal_valid(const struct drm_i915_gem_request *request)
> -{
> -   return intel_wait_check_request(>signaling.wait, request);
> -}
> -
>  static bool signal_complete(const struct drm_i915_gem_request *request)
>  {
> if (!request)
> return false;
>  
> -   /* If another process served as the bottom-half it may have already
> -* signalled that this wait is already completed.
> -*/
> -   if (intel_wait_complete(>signaling.wait))
> -   return signal_valid(request);
> -
> -   /* Carefully check if the request is complete, giving time for the
> +   /*
> +* Carefully check if the request is complete, giving time for the
>  * seqno to be visible or if the GPU hung.
>  */
> -   if (__i915_request_irq_complete(request))
> -   return true;
> -
> -   return false;
> +   return __i915_request_irq_complete(request);
>  }
>  
>  static struct drm_i915_gem_request *to_signaler(struct rb_node *rb)
> @@ -712,6 +699,7 @@ static int intel_breadcrumbs_signaler(void *arg)
>   >fence.flags)) {
> local_bh_disable();
> dma_fence_signal(>fence);
> +   
> GEM_BUG_ON(!i915_gem_request_completed(request));
> local_bh_enable(); /* kick start the tasklets 
> */
> }
>  
> -- 
> 2.15.1
> 
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Re: [Intel-gfx] [PATCH] drm/i915/pmu: Fix sleep under atomic in RC6 readout

[Tvrtko Ursulin]

On 06/02/2018 16:10, Imre Deak wrote:

On Tue, Feb 06, 2018 at 04:04:10PM +, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2018-02-06 14:31:07)

+static u64 read_rc6_residency(struct drm_i915_private *i915)
+{
+   u64 val;
+
+   val = intel_rc6_residency_ns(i915, IS_VALLEYVIEW(i915) ?
+  VLV_GT_RENDER_RC6 : GEN6_GT_GFX_RC6);
+   if (HAS_RC6p(i915))
+   val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
+   if (HAS_RC6pp(i915))
+   val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);


We really should mention that these may produce interesting results
every 53 minutes. Switching to a timer will allow us to notice the
wraparound in each counter.


+
+   return val;
+}
+
+static void
+update_rc6_sample(struct drm_i915_private *i915, u64 val, bool locked)
+{
+   unsigned long flags;
+
+   if (!locked)
+   spin_lock_irqsave(>pmu.lock, flags);
+
+   /*
+* Update stored RC6 counter only if it is greater than the current
+* value. This deals with periods of runtime suspend during which we are
+* estimating the RC6 residency, so do not want to overshoot the real
+* value read once the device is woken up.
+*/
+   if (val > i915->pmu.sample[__I915_SAMPLE_RC6].cur)
+   i915->pmu.sample[__I915_SAMPLE_RC6].cur = val;


64b wraparound? Maybe not today, maybe not tomorrow... ;)


But in 585 years we're in trouble? :))




+
+   /* We don't need to sample RC6 from the timer any more. */
+   i915->pmu.timer_enabled =
+   __pmu_needs_timer(i915,
+ i915->pmu.enable & 
~config_enabled_mask(I915_PMU_RC6_RESIDENCY),
+ READ_ONCE(i915->gt.awake));


But we do... :)
One thing I had in mind was to hook into runtime suspend/resume to read
the counters there and compensate, but the more I think about it, we may
as well solve the lack of resolution in the rc6 counters whilst we are
here. https://bugs.freedesktop.org/show_bug.cgi?id=94852.


How about using dev->power.suspended_jiffies?


This sounds promising and I hope it ends up with a much nicer fix so 
I'll give it a go.


RC6 wraparound issue I hope we can leave for a different patch. I hope 
it will be possible without a timer, as long as someone is not taking 
samples every 54 minutes only. (Don't mention VLV.) :)


Regards,

Tvrtko
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Remove superfluous worker wakeups when RPS is already boosted

[Patchwork]

== Series Details ==

Series: drm/i915: Remove superfluous worker wakeups when RPS is already boosted
URL   : https://patchwork.freedesktop.org/series/37743/
State : success

== Summary ==

Test perf:
Subgroup oa-exponents:
pass   -> FAIL   (shard-apl) fdo#102254
Subgroup enable-disable:
fail   -> PASS   (shard-apl) fdo#103715
Subgroup buffer-fill:
fail   -> PASS   (shard-apl) fdo#103755
Test gem_eio:
Subgroup in-flight-contexts:
pass   -> DMESG-WARN (shard-snb) fdo#104058
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-spr-indfb-fullscreen:
pass   -> FAIL   (shard-snb) fdo#101623
Test kms_mmap_write_crc:
skip   -> PASS   (shard-apl)
Test gem_exec_schedule:
Subgroup reorder-wide-vebox:
incomplete -> PASS   (shard-apl) fdo#102848
Test kms_cursor_legacy:
Subgroup short-flip-before-cursor-atomic-transitions:
pass   -> FAIL   (shard-apl) fdo#103792

fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#103715 https://bugs.freedesktop.org/show_bug.cgi?id=103715
fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755
fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#102848 https://bugs.freedesktop.org/show_bug.cgi?id=102848
fdo#103792 https://bugs.freedesktop.org/show_bug.cgi?id=103792

shard-apltotal:3383 pass:1751 dwarn:1   dfail:0   fail:22  skip:1608 
time:12242s
shard-hswtotal:3442 pass:1758 dwarn:1   dfail:0   fail:11  skip:1671 
time:11822s
shard-snbtotal:3442 pass:1349 dwarn:2   dfail:0   fail:11  skip:2080 
time:6593s
Blacklisted hosts:
shard-kbltotal:3442 pass:1911 dwarn:1   dfail:0   fail:21  skip:1509 
time:9601s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7909/shards.html
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Re: [Intel-gfx] [PATCH igt v2] tests: Add a random load generator

[Antonio Argenziano]

On 03/02/18 02:33, Chris Wilson wrote:

Apply a random load to one or all engines in order to apply stress to
RPS as it tries to constantly adjust the GPU frequency to meet the
changing workload.

This can be used to reproduce the byt (j1900) system hang.

v2: igt_until_timeout

Signed-off-by: Chris Wilson 


Acked-by: Antonio Argenziano 


---
  tests/Makefile.sources |   1 +
  tests/gem_exec_load.c  | 176 +
  2 files changed, 177 insertions(+)
  create mode 100644 tests/gem_exec_load.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 870c90935..8b5a18680 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -79,6 +79,7 @@ TESTS_progs = \
gem_exec_gttfill \
gem_exec_latency \
gem_exec_lut_handle \
+   gem_exec_load \
gem_exec_nop \
gem_exec_parallel \
gem_exec_params \
diff --git a/tests/gem_exec_load.c b/tests/gem_exec_load.c
new file mode 100644
index 0..ba88466a9
--- /dev/null
+++ b/tests/gem_exec_load.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include "igt_rand.h"
+#include "igt_sysfs.h"
+
+IGT_TEST_DESCRIPTION("Apply a random load to each engine");
+
+static inline uint32_t randmax(uint32_t *state, uint32_t ep_ro)
+{
+   return (uint64_t)hars_petruska_f54_1_random(state) * ep_ro >> 32;
+}
+
+static void one(int fd, unsigned int engine, int scale, unsigned int timeout)
+{
+   uint32_t prng = engine;
+   igt_spin_t *spin[2] = {};
+   unsigned int max;
+   int sysfs;
+
+   sysfs = igt_sysfs_open(fd, NULL);
+
+   max = sysfs < 0 ? 1 : igt_sysfs_get_u32(sysfs, "gt_max_freq_mhz");
+
+   igt_until_timeout(timeout) {
+   /*
+* For every second, we randomly assign a desire % busyness
+* and the frequency with which to submit a batch, defining
+* a pulse-width modulation (pwm).
+*/
+   unsigned int pwm = randmax(, 1000);
+   unsigned int load = randmax(, pwm / scale);
+   const unsigned int interval = 1e6 / pwm;
+   unsigned int cur =
+   max > 1 ? igt_sysfs_get_u32(sysfs, "gt_cur_freq_mhz") : 
1;
+
+   while (pwm--) {
+   if (randmax(, pwm * cur) <= load * max) {
+   spin[1] = __igt_spin_batch_new(fd, 0, engine, 
0);
+   load--;
+   }
+   igt_spin_batch_free(fd, spin[0]);
+   spin[0] = spin[1];
+   spin[1] = NULL;
+
+   usleep(interval);
+   }
+   }
+   igt_spin_batch_free(fd, spin[0]);
+
+   close(sysfs);
+}
+
+static void all(int fd, unsigned int timeout)
+{
+   unsigned int engines[16];
+   unsigned int nengine;
+   unsigned int engine;
+
+   nengine = 0;
+   for_each_engine(fd, engine)
+   engines[nengine++] = engine;
+   igt_require(nengine > 1);
+
+   for (unsigned int n = 0; n < nengine; n++)
+   igt_fork(child, 1)
+   one(fd, engines[n], nengine/2, timeout);
+   igt_waitchildren();
+}
+
+static void pulse(int fd, unsigned int timeout)
+{
+   const uint32_t bbe = MI_BATCH_BUFFER_END;
+   struct drm_i915_gem_exec_object2 obj[2] = {
+   { .flags = EXEC_OBJECT_WRITE },
+   };
+   unsigned int engines[16];
+   unsigned int nengine;
+   unsigned int engine;
+
+   nengine = 0;
+   for_each_engine(fd, engine) {
+   if (engine == 0)
+   continue;
+
+   engines[nengine++] = engine;
+   }
+   

Re: [Intel-gfx] [PATCH] drm/i915/pmu: Fix sleep under atomic in RC6 readout

[Imre Deak]

On Tue, Feb 06, 2018 at 04:04:10PM +, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2018-02-06 14:31:07)
> > +static u64 read_rc6_residency(struct drm_i915_private *i915)
> > +{
> > +   u64 val;
> > +
> > +   val = intel_rc6_residency_ns(i915, IS_VALLEYVIEW(i915) ?
> > +  VLV_GT_RENDER_RC6 : 
> > GEN6_GT_GFX_RC6);
> > +   if (HAS_RC6p(i915))
> > +   val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
> > +   if (HAS_RC6pp(i915))
> > +   val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);
> 
> We really should mention that these may produce interesting results
> every 53 minutes. Switching to a timer will allow us to notice the
> wraparound in each counter.
> 
> > +
> > +   return val;
> > +}
> > +
> > +static void
> > +update_rc6_sample(struct drm_i915_private *i915, u64 val, bool locked)
> > +{
> > +   unsigned long flags;
> > +
> > +   if (!locked)
> > +   spin_lock_irqsave(>pmu.lock, flags);
> > +
> > +   /*
> > +* Update stored RC6 counter only if it is greater than the current
> > +* value. This deals with periods of runtime suspend during which 
> > we are
> > +* estimating the RC6 residency, so do not want to overshoot the 
> > real
> > +* value read once the device is woken up.
> > +*/
> > +   if (val > i915->pmu.sample[__I915_SAMPLE_RC6].cur)
> > +   i915->pmu.sample[__I915_SAMPLE_RC6].cur = val;
> 
> 64b wraparound? Maybe not today, maybe not tomorrow... ;)
> 
> > +
> > +   /* We don't need to sample RC6 from the timer any more. */
> > +   i915->pmu.timer_enabled =
> > +   __pmu_needs_timer(i915,
> > + i915->pmu.enable & 
> > ~config_enabled_mask(I915_PMU_RC6_RESIDENCY),
> > + READ_ONCE(i915->gt.awake));
> 
> But we do... :)
> One thing I had in mind was to hook into runtime suspend/resume to read
> the counters there and compensate, but the more I think about it, we may
> as well solve the lack of resolution in the rc6 counters whilst we are
> here. https://bugs.freedesktop.org/show_bug.cgi?id=94852.

How about using dev->power.suspended_jiffies?

--Imre
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Re: [Intel-gfx] [PATCH] drm/i915/pmu: Fix sleep under atomic in RC6 readout

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-06 14:31:07)
> +static u64 read_rc6_residency(struct drm_i915_private *i915)
> +{
> +   u64 val;
> +
> +   val = intel_rc6_residency_ns(i915, IS_VALLEYVIEW(i915) ?
> +  VLV_GT_RENDER_RC6 : 
> GEN6_GT_GFX_RC6);
> +   if (HAS_RC6p(i915))
> +   val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
> +   if (HAS_RC6pp(i915))
> +   val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);

We really should mention that these may produce interesting results
every 53 minutes. Switching to a timer will allow us to notice the
wraparound in each counter.

> +
> +   return val;
> +}
> +
> +static void
> +update_rc6_sample(struct drm_i915_private *i915, u64 val, bool locked)
> +{
> +   unsigned long flags;
> +
> +   if (!locked)
> +   spin_lock_irqsave(>pmu.lock, flags);
> +
> +   /*
> +* Update stored RC6 counter only if it is greater than the current
> +* value. This deals with periods of runtime suspend during which we 
> are
> +* estimating the RC6 residency, so do not want to overshoot the real
> +* value read once the device is woken up.
> +*/
> +   if (val > i915->pmu.sample[__I915_SAMPLE_RC6].cur)
> +   i915->pmu.sample[__I915_SAMPLE_RC6].cur = val;

64b wraparound? Maybe not today, maybe not tomorrow... ;)

> +
> +   /* We don't need to sample RC6 from the timer any more. */
> +   i915->pmu.timer_enabled =
> +   __pmu_needs_timer(i915,
> + i915->pmu.enable & 
> ~config_enabled_mask(I915_PMU_RC6_RESIDENCY),
> + READ_ONCE(i915->gt.awake));

But we do... :)
One thing I had in mind was to hook into runtime suspend/resume to read
the counters there and compensate, but the more I think about it, we may
as well solve the lack of resolution in the rc6 counters whilst we are
here. https://bugs.freedesktop.org/show_bug.cgi?id=94852.
-Chris
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Re: [Intel-gfx] [PATCH] sna: CustomEDID fix

[Chris Wilson]

Quoting dom.const...@free.fr (2018-02-02 18:37:12)
> Hello, 
> 
> For my HTPC setup, I'm using the option "CustomEDID".
> With this option, output attaching and destroying events leads to crashes.
> 
> The following sequence leads to a crash:
> - In xorg.conf: Option "CustomEDID" "HDMI2:/etc/my_edid.bin"
> - Starting Xorg
> - Connect HDMI2
> - Disconnect HDMI2
> - Reconnect HDMI2
>   -> Crash
> 
> 
> The crash happens in xf86OutputSetEDID 
> (xorg/xserver/hw/xfree86/modes/xf86Crtc.c) 
> at "free(output->MonInfo)". MonInfo is assigned with 
> sna_output->fake_edid_mon 
> which is allocated by intel driver in sna_output_load_fake_edid 
> (src/sna/sna_display.c). 
> 
> 
> Sequence details:
> - Starting Xorg
>-> fake_edid_mon is initialized
> 
> - Connect HDMI2
>-> xf86OutputSetEDID is called: 
>- MonInfo is NULL
>- MonInfo is assigned with fake_edid_mon pointer
>- MonInfo is read by Xorg
> 
> - Disconnect HDMI2
> 
> - Reconnect HDMI2
>-> xf86OutputSetEDID is called:
>- MonInfo is freed thus also fake_edid_mon
>- MonInfo is assigned with fake_edid_mon
>- MonInfo is read but it was freed -> CRASH
> 
> 
> The fix consists of a new instance of xf86MonPtr for each calls of 
> xf86OutputSetEDID. 
> This instance is initialized with fake_edid_raw which render fake_edid_mon 
> useless. 
> With this proposal, the behaviour of an EDID override is similar to a "real" 
> EDID. 
> 
> Regards,
> 
> 
> Signed-off-by: Dominique Constant 
> To: Chris Wilson 

Apologies if this is a resend, but could you send me this patch using
"git send-email" (or attach the output of "git format-patch"). git am
is not happy with it.
-Chris
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[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [v4,1/3] drm/i915: Add intel_bios_cleanup() function

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/3] drm/i915: Add intel_bios_cleanup() 
function
URL   : https://patchwork.freedesktop.org/series/37741/
State : warning

== Summary ==

Test gem_exec_schedule:
Subgroup reorder-wide-vebox:
incomplete -> PASS   (shard-apl) fdo#102848
Test perf:
Subgroup buffer-fill:
fail   -> PASS   (shard-apl) fdo#103755
Subgroup blocking:
pass   -> FAIL   (shard-hsw) fdo#102252
Subgroup enable-disable:
fail   -> PASS   (shard-apl) fdo#103715
Subgroup oa-exponents:
pass   -> FAIL   (shard-apl) fdo#102254
Test kms_rmfb:
Subgroup close-fd:
pass   -> DMESG-WARN (shard-hsw)
Test kms_cursor_crc:
Subgroup cursor-128x128-suspend:
pass   -> INCOMPLETE (shard-hsw) fdo#103540
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912
Test kms_mmap_write_crc:
skip   -> PASS   (shard-apl)

fdo#102848 https://bugs.freedesktop.org/show_bug.cgi?id=102848
fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#103715 https://bugs.freedesktop.org/show_bug.cgi?id=103715
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-apltotal:3383 pass:1752 dwarn:1   dfail:0   fail:21  skip:1608 
time:12174s
shard-hswtotal:3420 pass:1744 dwarn:2   dfail:0   fail:11  skip:1661 
time:11329s
shard-snbtotal:3442 pass:1351 dwarn:1   dfail:0   fail:10  skip:2080 
time:6629s
Blacklisted hosts:
shard-kbltotal:3442 pass:1909 dwarn:1   dfail:0   fail:21  skip:1511 
time:9611s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7907/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Remove superfluous worker wakeups when RPS is already boosted

[Patchwork]

== Series Details ==

Series: drm/i915: Remove superfluous worker wakeups when RPS is already boosted
URL   : https://patchwork.freedesktop.org/series/37743/
State : success

== Summary ==

Series 37743v1 drm/i915: Remove superfluous worker wakeups when RPS is already 
boosted
https://patchwork.freedesktop.org/api/1.0/series/37743/revisions/1/mbox/

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:417s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:422s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:374s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:489s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:482s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:487s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:468s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:454s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:566s
fi-cnl-y3total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:575s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:414s
fi-gdg-551   total:288  pass:180  dwarn:0   dfail:0   fail:0   skip:108 
time:280s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:510s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:388s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:399s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:410s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:445s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:418s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:460s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:497s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:455s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:499s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:595s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:431s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:506s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:528s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:488s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:472s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:417s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:426s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:526s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:397s
Blacklisted hosts:
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:470s

078873da383505cf8d6940229007115b31f1d5e0 drm-tip: 2018y-02m-06d-11h-21m-36s UTC 
integration manifest
5b4911bc6d6f drm/i915: Remove superfluous worker wakeups when RPS is already 
boosted

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7909/issues.html
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Re: [Intel-gfx] [PATCH 2/6] drm/i915/icl: add the main CDCLK functions

[Paulo Zanoni]

Em Seg, 2018-02-05 às 15:13 -0800, Ausmus, James escreveu:
> On Mon, Feb 05, 2018 at 01:40:42PM -0200, Paulo Zanoni wrote:
> > This commit adds the basic CDCLK functions, but it's still missing
> > pieces of the display initialization sequence.
> > 
> > v2:
> >  - Implement the voltage levels.
> >  - Rebase.
> > v3:
> >  - Adjust to the new "bypass" clock (Imre).
> >  - Call intel_dump_cdclk_state() too.
> >  - Rename a variable to avoid confusion.
> >  - Simplify the DVFS part.
> 
>  ^^^
> Shouldn't this be something more like
> 
> "Drop DVFS part and replace with a TODO"?
> 
> "Simplify" makes it sound like it's still there, but it's not, unless
> I'm missing something?

We now always set the voltage to maximum (2) instead of picking a
possibly wrong value (due to not considering the DDI clocks), so in a
way we do the DVFS thing, just always with the safest value.

The patch that picks the best value will come later.

> 
> 
> > v4:
> >  - Remove wrong bit definition (James).
> >  - Also drive-by fix the coding style for the register definition
> > we
> >touched.
> > 
> > Cc: James Ausmus 
> > Cc: Imre Deak 
> > Signed-off-by: Paulo Zanoni 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h|  35 +++---
> >  drivers/gpu/drm/i915/intel_cdclk.c | 235
> > -
> >  drivers/gpu/drm/i915/intel_drv.h   |   2 +
> >  3 files changed, 255 insertions(+), 17 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index f6e1677e8211..2b6a908056d6 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7182,8 +7182,12 @@ enum {
> >  #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
> >  #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
> >  
> > -#define SKL_DSSM _MMIO(0x51004)
> > -#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
> > +#define SKL_DSSM _MMIO(0x51004)
> > +#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
> > +#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
> > +#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
> > +#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
> > +#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
> >  
> >  #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
> >  #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14)
> > @@ -8816,20 +8820,21 @@ enum skl_power_gate {
> >  
> >  /* CDCLK_CTL */
> >  #define CDCLK_CTL _MMIO(0x46000)
> > -#define  CDCLK_FREQ_SEL_MASK (3<<26)
> > -#define  CDCLK_FREQ_450_432 (0<<26)
> > -#define  CDCLK_FREQ_540 (1<<26)
> > -#define  CDCLK_FREQ_337_308 (2<<26)
> > -#define  CDCLK_FREQ_675_617 (3<<26)
> > -#define  BXT_CDCLK_CD2X_DIV_SEL_MASK (3<<22)
> > -#define  BXT_CDCLK_CD2X_DIV_SEL_1 (0<<22)
> > -#define  BXT_CDCLK_CD2X_DIV_SEL_1_5 (1<<22)
> > -#define  BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22)
> > -#define  BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22)
> > -#define  BXT_CDCLK_CD2X_PIPE(pipe) ((pipe)<<20)
> > -#define  CDCLK_DIVMUX_CD_OVERRIDE (1<<19)
> > +#define  CDCLK_FREQ_SEL_MASK (3 << 26)
> > +#define  CDCLK_FREQ_450_432 (0 << 26)
> > +#define  CDCLK_FREQ_540 (1 << 26)
> > +#define  CDCLK_FREQ_337_308 (2 << 26)
> > +#define  CDCLK_FREQ_675_617 (3 << 26)
> > +#define  BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22)
> > +#define  BXT_CDCLK_CD2X_DIV_SEL_1 (0 << 22)
> > +#define  BXT_CDCLK_CD2X_DIV_SEL_1_5 (1 << 22)
> > +#define  BXT_CDCLK_CD2X_DIV_SEL_2 (2 << 22)
> > +#define  BXT_CDCLK_CD2X_DIV_SEL_4 (3 << 22)
> > +#define  BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
> > +#define  CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
> >  #define  BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
> > -#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
> > +#define  ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
> > +#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
> >  #define  CDCLK_FREQ_DECIMAL_MASK (0x7ff)
> >  
> >  /* LCPLL_CTL */
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > b/drivers/gpu/drm/i915/intel_cdclk.c
> > index ee788d5be5e3..52a15d0eaae9 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -1778,6 +1778,197 @@ static void cnl_sanitize_cdclk(struct
> > drm_i915_private *dev_priv)
> >   dev_priv->cdclk.hw.vco = -1;
> >  }
> >  
> > +static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
> > +{
> > + int ranges_24[] = { 312000, 552000, 648000 };
> > + int ranges_19_38[] = { 307200, 556800, 652800 };
> > + int *ranges;
> > +
> > + switch (ref) {
> > + default:
> > + MISSING_CASE(ref);
> > + case 24000:
> > + ranges = ranges_24;
> > + break;
> > + case 19200:
> > + case 38400:
> > + ranges = ranges_19_38;
> > + break;
> > + }
> > +
> > + if (min_cdclk > ranges[1])
> > + return ranges[2];
> > + else if (min_cdclk > ranges[0])
> > + return ranges[1];
> > + else
> > + return ranges[0];
> > +}
> > +
> > +static int icl_calc_cdclk_pll_vco(struct drm_i915_private
> > *dev_priv, int cdclk)
> > +{
> > + int ratio;
> > +
> > + if (cdclk == 

[Intel-gfx] Thinkpad X1 Carbon 3rd - Reducing the compressed framebuffer size

[Pali Rohár]

Hi! I'm periodically getting following message in dmesg on Lenovo
Thinkpad X1 Carbon 3rd generation:

[drm] Reducing the compressed framebuffer size. This may lead to less power 
savings than a non-reduced-size. Try to increase stolen memory size if 
available in BIOS.

In BIOS I already set GPU size to 512M, but this did not help. Also
update to last BIOS version did not help.

So why this message is periodically print in dmesg? And what can I do
with this problem?

And why cannot Linux kernel allocate itself more memory for GPU (if BIOS
can/could do that)? Is not 512MB for GPU enough?

-- 
Pali Rohár
pali.ro...@gmail.com
___
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[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/pmu: Fix sleep under atomic in RC6 readout

[Patchwork]

== Series Details ==

Series: drm/i915/pmu: Fix sleep under atomic in RC6 readout
URL   : https://patchwork.freedesktop.org/series/37742/
State : warning

== Summary ==

Series 37742v1 drm/i915/pmu: Fix sleep under atomic in RC6 readout
https://patchwork.freedesktop.org/api/1.0/series/37742/revisions/1/mbox/

Test gem_ctx_create:
Subgroup basic-files:
pass   -> DMESG-WARN (fi-skl-6700k2)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:415s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:422s
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time:377s
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fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
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time:454s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:496s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:592s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:427s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:508s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:536s
fi-skl-6700k2total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:474s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:502s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:413s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:430s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:397s
Blacklisted hosts:
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:470s

078873da383505cf8d6940229007115b31f1d5e0 drm-tip: 2018y-02m-06d-11h-21m-36s UTC 
integration manifest
a20dd79efd67 drm/i915/pmu: Fix sleep under atomic in RC6 readout

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7908/issues.html
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/3] drm/i915: Add intel_bios_cleanup() function

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/3] drm/i915: Add intel_bios_cleanup() 
function
URL   : https://patchwork.freedesktop.org/series/37741/
State : success

== Summary ==

Series 37741v1 series starting with [v4,1/3] drm/i915: Add intel_bios_cleanup() 
function
https://patchwork.freedesktop.org/api/1.0/series/37741/revisions/1/mbox/

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:421s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:424s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:371s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:489s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:480s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:486s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:474s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:460s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:568s
fi-cnl-y3total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:584s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:412s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:286s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:517s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:398s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:398s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:413s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:462s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:426s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:458s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:495s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:449s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:500s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:594s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:431s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:510s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:526s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:489s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:489s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:419s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:430s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:526s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:408s
Blacklisted hosts:
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:465s

078873da383505cf8d6940229007115b31f1d5e0 drm-tip: 2018y-02m-06d-11h-21m-36s UTC 
integration manifest
1f3e7871638c drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT 
sequence v3
dcf004ec7001 drm/i915: Free memdup-ed DSI VBT data structures on driver_unload
595a5c38746a drm/i915: Add intel_bios_cleanup() function

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7907/issues.html
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm/i915: Remove superfluous worker wakeups when RPS is already boosted

[Chris Wilson]

We only need to wake up the RPS worker once when initially enabling the
client boost, it remains in effect then until the last client no longer
requires the boost.

References: https://bugs.freedesktop.org/show_bug.cgi?id=102250
References: 7b92c1bd0540 ("drm/i915: Avoid keeping waitboost active for 
signaling threads")
Signed-off-by: Chris Wilson 
Cc: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_gem_request.c | 6 --
 drivers/gpu/drm/i915/intel_pm.c | 9 ++---
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 8efa9e7a9e46..794263421aa0 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -443,12 +443,14 @@ static void i915_gem_request_retire(struct 
drm_i915_gem_request *request)
engine->last_retired_context = request->ctx;
 
spin_lock_irq(>lock);
-   if (request->waitboost)
-   atomic_dec(>i915->gt_pm.rps.num_waiters);
if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >fence.flags))
dma_fence_signal_locked(>fence);
if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, >fence.flags))
intel_engine_cancel_signaling(request);
+   if (request->waitboost) {
+   GEM_BUG_ON(!atomic_read(>i915->gt_pm.rps.num_waiters));
+   atomic_dec(>i915->gt_pm.rps.num_waiters);
+   }
spin_unlock_irq(>lock);
 
i915_priotree_fini(request->i915, >priotree);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index eb68abf6a8e9..5b36166976e3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6372,12 +6372,15 @@ void gen6_rps_boost(struct drm_i915_gem_request *rq,
if (!rps->enabled)
return;
 
+   if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >fence.flags))
+   return;
+
+   /* Serializes with i915_gem_request_retire() */
boost = false;
spin_lock_irqsave(>lock, flags);
-   if (!rq->waitboost && !i915_gem_request_completed(rq)) {
-   atomic_inc(>num_waiters);
+   if (!rq->waitboost && !dma_fence_is_signaled_locked(>fence)) {
+   boost = !atomic_fetch_inc(>num_waiters);
rq->waitboost = true;
-   boost = true;
}
spin_unlock_irqrestore(>lock, flags);
if (!boost)
-- 
2.16.1

___
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[Intel-gfx] [PATCH] drm/i915/pmu: Fix sleep under atomic in RC6 readout

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

We are not allowed to call intel_runtime_pm_get from the PMU counter read
callback since the former can sleep, and the latter is running under IRQ
context.

To workaround this, we start our timer when we detect that we have failed
to obtain a runtime PM reference during read, and approximate the growing
RC6 counter from the timer.

Once the timer manages to obtain the runtime PM reference, we stop the
timer and go back to the above described behaviour.

We have to be careful not to overshoot the RC6 estimate, so once resumed
after a period of approximation, we only update the counter once it
catches up. With the observation that RC6 is increasing while the device
is suspended, this should not pose a problem and can only cause
slight inaccuracies due clock base differences.

Signed-off-by: Tvrtko Ursulin 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104943
Fixes: 6060b6aec03c ("drm/i915/pmu: Add RC6 residency metrics")
Testcase: igt/perf_pmu/rc6-runtime-pm
Cc: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Imre Deak 
Cc: Jani Nikula 
Cc: Joonas Lahtinen 
Cc: Rodrigo Vivi 
Cc: David Airlie 
Cc: intel-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
---
 drivers/gpu/drm/i915/i915_pmu.c | 149 ++--
 drivers/gpu/drm/i915/i915_pmu.h |   1 +
 2 files changed, 114 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 1c440460255d..dca41c072a7c 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -90,23 +90,16 @@ static unsigned int event_enabled_bit(struct perf_event 
*event)
return config_enabled_bit(event->attr.config);
 }
 
-static bool pmu_needs_timer(struct drm_i915_private *i915, bool gpu_active)
+static bool
+__pmu_needs_timer(struct drm_i915_private *i915, u64 enable, bool gpu_active)
 {
-   u64 enable;
-
-   /*
-* Only some counters need the sampling timer.
-*
-* We start with a bitmask of all currently enabled events.
-*/
-   enable = i915->pmu.enable;
-
/*
-* Mask out all the ones which do not need the timer, or in
+* Mask out all events which do not need the timer, or in
 * other words keep all the ones that could need the timer.
 */
enable &= config_enabled_mask(I915_PMU_ACTUAL_FREQUENCY) |
  config_enabled_mask(I915_PMU_REQUESTED_FREQUENCY) |
+ config_enabled_mask(I915_PMU_RC6_RESIDENCY) |
  ENGINE_SAMPLE_MASK;
 
/*
@@ -130,6 +123,11 @@ static bool pmu_needs_timer(struct drm_i915_private *i915, 
bool gpu_active)
return enable;
 }
 
+static bool pmu_needs_timer(struct drm_i915_private *i915, bool gpu_active)
+{
+   return __pmu_needs_timer(i915, i915->pmu.enable, gpu_active);
+}
+
 void i915_pmu_gt_parked(struct drm_i915_private *i915)
 {
if (!i915->pmu.base.event_init)
@@ -181,20 +179,20 @@ update_sample(struct i915_pmu_sample *sample, u32 unit, 
u32 val)
sample->cur += mul_u32_u32(val, unit);
 }
 
-static void engines_sample(struct drm_i915_private *dev_priv)
+static bool engines_sample(struct drm_i915_private *dev_priv)
 {
struct intel_engine_cs *engine;
enum intel_engine_id id;
bool fw = false;
 
if ((dev_priv->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
-   return;
+   return false;
 
if (!dev_priv->gt.awake)
-   return;
+   return false;
 
if (!intel_runtime_pm_get_if_in_use(dev_priv))
-   return;
+   return false;
 
for_each_engine(engine, dev_priv, id) {
u32 current_seqno = intel_engine_get_seqno(engine);
@@ -225,10 +223,51 @@ static void engines_sample(struct drm_i915_private 
*dev_priv)
if (fw)
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 
-   intel_runtime_pm_put(dev_priv);
+   return true;
+}
+
+static u64 read_rc6_residency(struct drm_i915_private *i915)
+{
+   u64 val;
+
+   val = intel_rc6_residency_ns(i915, IS_VALLEYVIEW(i915) ?
+  VLV_GT_RENDER_RC6 : GEN6_GT_GFX_RC6);
+   if (HAS_RC6p(i915))
+   val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
+   if (HAS_RC6pp(i915))
+   val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);
+
+   return val;
+}
+
+static void
+update_rc6_sample(struct drm_i915_private *i915, u64 val, bool locked)
+{
+   unsigned long flags;
+
+   if (!locked)
+   spin_lock_irqsave(>pmu.lock, flags);
+
+   /*
+* Update stored RC6 counter only if it is greater than the current
+* value. This 

[Intel-gfx] [PATCH v4 1/3] drm/i915: Add intel_bios_cleanup() function

[Hans de Goede]

Add an intel_bios_cleanup() function to act as counterpart of
intel_bios_init() and move the cleanup of vbt related resources there,
putting it in the same file as the allocation.

Signed-off-by: Hans de Goede 
---
 drivers/gpu/drm/i915/i915_drv.c   | 14 +-
 drivers/gpu/drm/i915/i915_drv.h   |  1 +
 drivers/gpu/drm/i915/intel_bios.c | 21 +
 3 files changed, 23 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e9f1daf258fe..7f094bbc2a7f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1446,19 +1446,7 @@ void i915_driver_unload(struct drm_device *dev)
 
intel_modeset_cleanup(dev);
 
-   /*
-* free the memory space allocated for the child device
-* config parsed from VBT
-*/
-   if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
-   kfree(dev_priv->vbt.child_dev);
-   dev_priv->vbt.child_dev = NULL;
-   dev_priv->vbt.child_dev_num = 0;
-   }
-   kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
-   dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
-   kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
-   dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
+   intel_bios_cleanup(dev_priv);
 
vga_switcheroo_unregister_client(pdev);
vga_client_register(pdev, NULL, NULL, NULL);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d6b5ac2a563d..1cccea1b87bc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3675,6 +3675,7 @@ extern void intel_i2c_reset(struct drm_i915_private 
*dev_priv);
 
 /* intel_bios.c */
 void intel_bios_init(struct drm_i915_private *dev_priv);
+void intel_bios_cleanup(struct drm_i915_private *dev_priv);
 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 
*i2c_pin);
diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index 4e74aa2f16bc..f9550507bb9f 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1610,6 +1610,27 @@ void intel_bios_init(struct drm_i915_private *dev_priv)
pci_unmap_rom(pdev, bios);
 }
 
+/**
+ * intel_bios_cleanup - Free any resources allocated by intel_bios_init()
+ * @dev_priv: i915 device instance
+ */
+void intel_bios_cleanup(struct drm_i915_private *dev_priv)
+{
+   /*
+* free the memory space allocated for the child device
+* config parsed from VBT
+*/
+   if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
+   kfree(dev_priv->vbt.child_dev);
+   dev_priv->vbt.child_dev = NULL;
+   dev_priv->vbt.child_dev_num = 0;
+   }
+   kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
+   dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
+   kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
+   dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
+}
+
 /**
  * intel_bios_is_tv_present - is integrated TV present in VBT
  * @dev_priv:  i915 device instance
-- 
2.14.3

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[Intel-gfx] [PATCH v4 2/3] drm/i915: Free memdup-ed DSI VBT data structures on driver_unload

[Hans de Goede]

Make intel_bios_cleanup function free the DSI VBT data structures which
are memdup-ed by parse_mipi_config() and parse_mipi_sequence().

Signed-off-by: Hans de Goede 
---
 drivers/gpu/drm/i915/intel_bios.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index f9550507bb9f..18110bbd9ee2 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1629,6 +1629,12 @@ void intel_bios_cleanup(struct drm_i915_private 
*dev_priv)
dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
+   kfree(dev_priv->vbt.dsi.data);
+   dev_priv->vbt.dsi.data = NULL;
+   kfree(dev_priv->vbt.dsi.pps);
+   dev_priv->vbt.dsi.pps = NULL;
+   kfree(dev_priv->vbt.dsi.config);
+   dev_priv->vbt.dsi.config = NULL;
 }
 
 /**
-- 
2.14.3

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[Intel-gfx] [PATCH v4 3/3] drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT sequence v3

[Hans de Goede]

So far models of the Dell Venue 8 Pro, with a panel with MIPI panel
index = 3, one of which has been kindly provided to me by Jan Brummer,
where not working with the i915 driver, giving a black screen on the
first modeset.

The problem with at least these Dells is that their VBT defines a MIPI
ASSERT sequence, but not a DEASSERT sequence. Instead they DEASSERT the
reset in their INIT_OTP sequence, but the deassert must be done before
calling intel_dsi_device_ready(), so that is too late.

Simply doing the INIT_OTP sequence earlier is not enough to fix this,
because the INIT_OTP sequence also sends various MIPI packets to the
panel, which can only happen after calling intel_dsi_device_ready().

This commit fixes this by splitting the INIT_OTP sequence into everything
before the first DSI packet and everything else, including the first DSI
packet. The first part (everything before the first DSI packet) is then
used as deassert sequence.

Changed in v2:
-Split the init OTP sequence into a deassert reset and the actual init
 OTP sequence, instead of calling it earlier and then having the first
 mipi_exec_send_packet() call call intel_dsi_device_ready().

Changes in v3:
-Move the whole shebang to intel_bios.c

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82880
References: https://bugs.freedesktop.org/show_bug.cgi?id=101205
Cc: Jan-Michael Brummer 
Reported-by: Jan-Michael Brummer 
Tested-by: Hans de Goede 
Reviewed-by: Ville Syrjälä 
Acked-by: Jani Nikula 
Signed-off-by: Hans de Goede 
---
 drivers/gpu/drm/i915/i915_drv.h   |  1 +
 drivers/gpu/drm/i915/intel_bios.c | 84 +++
 2 files changed, 85 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1cccea1b87bc..b3c4fde600eb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1356,6 +1356,7 @@ struct intel_vbt_data {
u32 size;
u8 *data;
const u8 *sequence[MIPI_SEQ_MAX];
+   u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
} dsi;
 
int crt_ddc_pin;
diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index 18110bbd9ee2..797d1aecda03 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -947,6 +947,86 @@ static int goto_next_sequence_v3(const u8 *data, int 
index, int total)
return 0;
 }
 
+/*
+ * Get len of pre-fixed deassert fragment from a v1 init OTP sequence,
+ * skip all delay + gpio operands and stop at the first DSI packet op.
+ */
+static int get_init_otp_deassert_fragment_len(struct drm_i915_private 
*dev_priv)
+{
+   const u8 *data = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
+   int index, len;
+
+   if (WARN_ON(!data || dev_priv->vbt.dsi.seq_version != 1))
+   return 0;
+
+   /* index = 1 to skip sequence byte */
+   for (index = 1; data[index] != MIPI_SEQ_ELEM_END; index += len) {
+   switch (data[index]) {
+   case MIPI_SEQ_ELEM_SEND_PKT:
+   return index == 1 ? 0 : index;
+   case MIPI_SEQ_ELEM_DELAY:
+   len = 5; /* 1 byte for operand + uint32 */
+   break;
+   case MIPI_SEQ_ELEM_GPIO:
+   len = 3; /* 1 byte for op, 1 for gpio_nr, 1 for value */
+   break;
+   default:
+   return 0;
+   }
+   }
+
+   return 0;
+}
+
+/*
+ * Some v1 VBT MIPI sequences do the deassert in the init OTP sequence.
+ * The deassert must be done before calling intel_dsi_device_ready, so for
+ * these devices we split the init OTP sequence into a deassert sequence and
+ * the actual init OTP part.
+ */
+static void fixup_mipi_sequences(struct drm_i915_private *dev_priv)
+{
+   u8 *init_otp;
+   int len;
+
+   /* Limit this to VLV for now. */
+   if (!IS_VALLEYVIEW(dev_priv))
+   return;
+
+   /* Limit this to v1 vid-mode sequences */
+   if (dev_priv->vbt.dsi.config->is_cmd_mode ||
+   dev_priv->vbt.dsi.seq_version != 1)
+   return;
+
+   /* Only do this if there are otp and assert seqs and no deassert seq */
+   if (!dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] ||
+   !dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET] ||
+   dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET])
+   return;
+
+   /* The deassert-sequence ends at the first DSI packet */
+   len = get_init_otp_deassert_fragment_len(dev_priv);
+   if (!len)
+   return;
+
+   DRM_DEBUG_KMS("Using init OTP fragment to deassert reset\n");
+
+   /* Copy the fragment, update seq byte and terminate it */
+   init_otp = (u8 

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/breadcrumbs: Ignore unsubmitted signalers

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/breadcrumbs: Ignore unsubmitted 
signalers
URL   : https://patchwork.freedesktop.org/series/37725/
State : success

== Summary ==

Test perf:
Subgroup buffer-fill:
fail   -> PASS   (shard-apl) fdo#103755
Subgroup oa-exponents:
pass   -> FAIL   (shard-apl) fdo#102254
Subgroup enable-disable:
fail   -> PASS   (shard-apl) fdo#103715
Test kms_mmap_write_crc:
skip   -> PASS   (shard-apl)
Test gem_exec_schedule:
Subgroup reorder-wide-vebox:
incomplete -> PASS   (shard-apl) fdo#102848
Test gem_eio:
Subgroup suspend:
pass   -> INCOMPLETE (shard-snb) fdo#103880
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
pass   -> FAIL   (shard-hsw) fdo#102887
Test kms_cursor_crc:
Subgroup cursor-256x256-suspend:
pass   -> INCOMPLETE (shard-hsw) fdo#103375

fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#103715 https://bugs.freedesktop.org/show_bug.cgi?id=103715
fdo#102848 https://bugs.freedesktop.org/show_bug.cgi?id=102848
fdo#103880 https://bugs.freedesktop.org/show_bug.cgi?id=103880
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375

shard-apltotal:3383 pass:1752 dwarn:1   dfail:0   fail:21  skip:1608 
time:12237s
shard-hswtotal:3382 pass:1721 dwarn:1   dfail:0   fail:12  skip:1646 
time:11288s
shard-snbtotal:3389 pass:1327 dwarn:1   dfail:0   fail:10  skip:2050 
time:6449s
Blacklisted hosts:
shard-kbltotal:3442 pass:1912 dwarn:1   dfail:0   fail:22  skip:1507 
time:9549s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7905/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915: Display WA #0827 for NV12 to RGB switch

[Maarten Lankhorst]

Hey,

Op 06-02-18 om 12:06 schreef Vidya Srinivas:
> From: Chandra Konduru 
>
> Display WA #0827:
> Switching the plane format from NV12 to RGB and leaving system idle results
> in display underrun and corruption. WA: Set the bit 15 & bit 19 to 1b
> in the CLKGATE_DIS_PSL register for the pipe in which NV12 plane is enabled.
>
> Signed-off-by: Chandra Konduru 
> Signed-off-by: Vidya Srinivas 

Is it required to leave the workaround enabled all the time? And how can I 
reproduce it? I tried to write a
dumb testcase (below) to expose this issue, but didn't have much luck..
---
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 870c9093550b..f536db0fa433 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -192,6 +192,7 @@ TESTS_progs = \
kms_legacy_colorkey \
kms_mmap_write_crc \
kms_mmio_vs_cs_flip \
+   kms_nv12 \
kms_panel_fitting \
kms_pipe_b_c_ivb \
kms_pipe_crc_basic \
diff --git a/tests/kms_nv12.c b/tests/kms_nv12.c
new file mode 100644
index ..384a15afde52
--- /dev/null
+++ b/tests/kms_nv12.c
@@ -0,0 +1,195 @@
+/*
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *Maarten Lankhorst 
+ */
+#include "config.h"
+
+#include "igt.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+
+typedef struct {
+   igt_display_t display;
+
+   igt_pipe_crc_t *pipe_crc;
+   struct igt_fb fb[4];
+} data_t;
+
+static bool plane_supports_format(igt_plane_t *plane, uint32_t format)
+{
+   int i;
+
+   if (!igt_fb_supported_format(format))
+   return false;
+
+   for (i = 0; i < plane->drm_plane->count_formats; i++)
+   if (plane->drm_plane->formats[i] == format)
+   return true;
+
+   return false;
+}
+
+static bool pipe_supports_format(igt_display_t *display, enum pipe pipe, 
uint32_t format)
+{
+   igt_plane_t *plane;
+
+   for_each_plane_on_pipe(display, pipe, plane)
+   if (plane_supports_format(plane, format))
+   return true;
+
+   return false;
+}
+
+static void remove_fbs(data_t *data)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(data->fb); i++)
+   igt_remove_fb(data->display.drm_fd, >fb[i]);
+}
+
+static void prepare_crtc(data_t *data, enum pipe pipe, igt_output_t *output)
+{
+   igt_display_t *display = >display;
+
+   remove_fbs(data);
+   igt_display_reset(display);
+   igt_output_set_pipe(output, pipe);
+   igt_display_commit2(display, COMMIT_ATOMIC);
+
+   igt_pipe_crc_free(data->pipe_crc);
+   data->pipe_crc = igt_pipe_crc_new(display->drm_fd, pipe, 
INTEL_PIPE_CRC_SOURCE_AUTO);
+}
+
+static void set_fb(igt_plane_t *plane, struct igt_fb *fb)
+{
+   igt_plane_set_fb(plane, fb);
+
+   if (fb && fb->tiling == LOCAL_I915_FORMAT_MOD_Y_TILED) {
+   igt_plane_set_rotation(plane, IGT_ROTATION_90);
+   igt_plane_set_size(plane, fb->height, fb->width);
+   } else
+   igt_plane_set_rotation(plane, IGT_ROTATION_0);
+}
+
+static void nv12_rgb_switch(data_t *data, enum pipe pipe, igt_output_t *output)
+{
+   drmModeModeInfo *mode = igt_output_get_mode(output);
+   igt_display_t *display = >display;
+   igt_plane_t *plane;
+   int i;
+   igt_crc_t ref_crc[4], crc;
+
+   prepare_crtc(data, pipe, output);
+
+   igt_create_pattern_fb(display->drm_fd, mode->hdisplay, mode->vdisplay,
+ DRM_FORMAT_NV12, LOCAL_I915_FORMAT_MOD_X_TILED,
+ >fb[0]);
+
+   igt_create_pattern_fb(display->drm_fd, mode->vdisplay, mode->hdisplay,
+ DRM_FORMAT_NV12, LOCAL_I915_FORMAT_MOD_Y_TILED,
+ >fb[1]);
+
+   igt_create_pattern_fb(display->drm_fd, mode->hdisplay, 

[Intel-gfx] ✗ Fi.CI.BAT: warning for Adding NV12 support (rev8)

[Patchwork]

== Series Details ==

Series: Adding NV12 support (rev8)
URL   : https://patchwork.freedesktop.org/series/28103/
State : warning

== Summary ==

Series 28103v8 Adding NV12 support
https://patchwork.freedesktop.org/api/1.0/series/28103/revisions/8/mbox/

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test gem_sync:
Subgroup basic-all:
pass   -> SKIP   (fi-blb-e6850)
Subgroup basic-each:
pass   -> SKIP   (fi-blb-e6850)
Subgroup basic-many-each:
pass   -> SKIP   (fi-blb-e6850)
Subgroup basic-store-all:
pass   -> SKIP   (fi-blb-e6850)
Subgroup basic-store-each:
pass   -> SKIP   (fi-blb-e6850)
Test gem_tiled_blits:
Subgroup basic:
pass   -> SKIP   (fi-blb-e6850)
Test gem_tiled_fence_blits:
Subgroup basic:
pass   -> SKIP   (fi-blb-e6850)
Test gem_wait:
Subgroup basic-busy-all:
pass   -> SKIP   (fi-blb-e6850)
Subgroup basic-wait-all:
pass   -> SKIP   (fi-blb-e6850)
Subgroup basic-await-all:
pass   -> SKIP   (fi-blb-e6850)
Test kms_busy:
Subgroup basic-flip-a:
pass   -> SKIP   (fi-blb-e6850)
Subgroup basic-flip-b:
pass   -> SKIP   (fi-blb-e6850)
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
pass   -> SKIP   (fi-blb-e6850)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (fi-cnl-y3)
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713
Subgroup suspend-read-crc-pipe-c:
pass   -> FAIL   (fi-ivb-3520m) k.org#198519

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
k.org#198519 https://bugzilla.kernel.org/show_bug.cgi?id=198519

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:420s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:423s
fi-blb-e6850 total:288  pass:210  dwarn:1   dfail:0   fail:0   skip:77  
time:344s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:485s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:492s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:490s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:466s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:465s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:566s
fi-cnl-y3total:288  pass:261  dwarn:1   dfail:0   fail:0   skip:26  
time:574s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:419s
fi-gdg-551   total:288  pass:180  dwarn:0   dfail:0   fail:0   skip:108 
time:281s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:512s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:391s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:398s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:416s
fi-ivb-3520m total:288  pass:258  dwarn:0   dfail:0   fail:1   skip:29  
time:435s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:416s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:453s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:498s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:455s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:498s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:590s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:426s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:505s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:528s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:487s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:477s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:411s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:426s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:393s
Blacklisted hosts:
fi-glk-dsi   

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/audio: do not set Maud/Naud values manually on KBL

[Patchwork]

== Series Details ==

Series: drm/i915/audio: do not set Maud/Naud values manually on KBL
URL   : https://patchwork.freedesktop.org/series/37730/
State : success

== Summary ==

Test perf:
Subgroup enable-disable:
fail   -> PASS   (shard-apl) fdo#103715
Subgroup buffer-fill:
fail   -> PASS   (shard-apl) fdo#103755
Subgroup oa-exponents:
pass   -> FAIL   (shard-apl) fdo#102254
Test kms_mmap_write_crc:
skip   -> PASS   (shard-apl)
Test kms_flip:
Subgroup flip-vs-panning-vs-hang:
pass   -> DMESG-WARN (shard-snb) fdo#103821
Test gem_exec_schedule:
Subgroup reorder-wide-vebox:
incomplete -> PASS   (shard-apl) fdo#102848

fdo#103715 https://bugs.freedesktop.org/show_bug.cgi?id=103715
fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#103821 https://bugs.freedesktop.org/show_bug.cgi?id=103821
fdo#102848 https://bugs.freedesktop.org/show_bug.cgi?id=102848

shard-apltotal:3383 pass:1752 dwarn:1   dfail:0   fail:21  skip:1608 
time:12177s
shard-hswtotal:3442 pass:1758 dwarn:1   dfail:0   fail:11  skip:1671 
time:11764s
shard-snbtotal:3442 pass:1350 dwarn:2   dfail:0   fail:10  skip:2080 
time:6520s
Blacklisted hosts:
shard-kbltotal:3442 pass:1906 dwarn:4   dfail:1   fail:22  skip:1509 
time:9640s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7904/shards.html
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Free memdup-ed bios data structures on driver_unload

[Hans de Goede]

Hi,

On 02-02-18 17:13, Ville Syrjälä wrote:

On Mon, Jan 29, 2018 at 03:47:34PM +0100, Hans de Goede wrote:

Add a new intel_bios_cleanup function to free memdup-ed bios data
structures and call it from i915_driver_unload().

Signed-off-by: Hans de Goede 
---
  drivers/gpu/drm/i915/i915_drv.c   |  2 ++
  drivers/gpu/drm/i915/i915_drv.h   |  1 +
  drivers/gpu/drm/i915/intel_bios.c | 11 +++
  3 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1ec12add34b2..4ecf41724183 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1437,6 +1437,8 @@ void i915_driver_unload(struct drm_device *dev)
  
  	intel_modeset_cleanup(dev);
  
+	intel_bios_cleanup(dev_priv);

+
/*
 * free the memory space allocated for the child device
 * config parsed from VBT


Looks like there's already a bunch of VBT related cleanup just below.
Maybe that should be sucked into the new cleanup function as well?


Ah, I somehow missed that, yes that is a good idea. I will send a v3 of
the series with that changed.

Regards,

Hans





diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 454d8f937fae..081190da0818 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3663,6 +3663,7 @@ extern void intel_i2c_reset(struct drm_i915_private 
*dev_priv);
  
  /* intel_bios.c */

  void intel_bios_init(struct drm_i915_private *dev_priv);
+void intel_bios_cleanup(struct drm_i915_private *dev_priv);
  bool intel_bios_is_valid_vbt(const void *buf, size_t size);
  bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
  bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 
*i2c_pin);
diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index 95f0b310d656..64a0d55df28e 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1588,6 +1588,17 @@ void intel_bios_init(struct drm_i915_private *dev_priv)
pci_unmap_rom(pdev, bios);
  }
  
+/**

+ * intel_bios_cleanup - Free any resources allocated by intel_bios_init()
+ * @dev_priv: i915 device instance
+ */
+void intel_bios_cleanup(struct drm_i915_private *dev_priv)
+{
+   kfree(dev_priv->vbt.dsi.data);
+   kfree(dev_priv->vbt.dsi.pps);
+   kfree(dev_priv->vbt.dsi.config);
+}
+
  /**
   * intel_bios_is_tv_present - is integrated TV present in VBT
   * @dev_priv: i915 device instance
--
2.14.3



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Re: [Intel-gfx] [PATCH] drm/i915: Display WA #0827 for NV12 to RGB switch

[Srinivas, Vidya]

Sorry, my bad. This was a wrong push from my end. I have changed the tag to Not 
applicable.
Apologies.

Have sent out the NV12 series separately.

Regards
Vidya

> -Original Message-
> From: David Weinehall [mailto:david.weineh...@linux.intel.com]
> Sent: Tuesday, February 6, 2018 5:34 PM
> To: Srinivas, Vidya 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Display WA #0827 for NV12 to
> RGB switch
> 
> On Tue, Feb 06, 2018 at 04:36:42PM +0530, Vidya Srinivas wrote:
> > From: Chandra Konduru 
> >
> > Display WA #0827:
> > Switching the plane format from NV12 to RGB and leaving system idle
> > results in display underrun and corruption. WA: Set the bit 15 & bit
> > 19 to 1b in the CLKGATE_DIS_PSL register for the pipe in which NV12 plane
> is enabled.
> >
> > Signed-off-by: Chandra Konduru 
> > Signed-off-by: Vidya Srinivas 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  |  3 +++
> >  drivers/gpu/drm/i915/intel_display.c | 16 
> >  2 files changed, 19 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 8f36023..c4af05e 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3822,6 +3822,9 @@ enum {
> >  #define _CLKGATE_DIS_PSL_A 0x46520
> >  #define _CLKGATE_DIS_PSL_B 0x46524
> >  #define _CLKGATE_DIS_PSL_C 0x46528
> > +#define DUPS1_GATING_DIS   (1 << 15)
> > +#define DUPS2_GATING_DIS   (1 << 19)
> > +#define DUPS3_GATING_DIS   (1 << 23)
> >  #define   DPF_GATING_DIS   (1 << 10)
> >  #define   DPF_RAM_GATING_DIS   (1 << 9)
> >  #define   DPFR_GATING_DIS  (1 << 8)
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 551c970..94faf3e 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5495,6 +5495,20 @@ static void
> glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
> > I915_WRITE(CLKGATE_DIS_PSL(pipe), val);  }
> >
> > +static void skl_wa_clkgate(struct drm_i915_private *dev_priv,
> > +   int pipe, int enable)
> > +{
> > +   if (pipe == PIPE_A || pipe == PIPE_B) {
> > +   if (enable)
> > +   I915_WRITE(CLKGATE_DIS_PSL(pipe),
> > +   DUPS1_GATING_DIS | DUPS2_GATING_DIS);
> > +   else
> > +   I915_WRITE(CLKGATE_DIS_PSL(pipe),
> > +   I915_READ(CLKGATE_DIS_PSL(pipe)) &
> > +   ~(DUPS1_GATING_DIS|DUPS2_GATING_DIS));
> > +   }
> > +}
> > +
> >  static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> > struct drm_atomic_state *old_state)  { @@
> -5599,6 +5613,7 @@
> > static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> > intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
> > intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
> > }
> > +   skl_wa_clkgate(dev_priv, pipe, 1);
> >  }
> >
> >  static void ironlake_pfit_disable(struct intel_crtc *crtc, bool
> > force) @@ -5709,6 +5724,7 @@ static void haswell_crtc_disable(struct
> intel_crtc_state *old_crtc_state,
> > intel_ddi_disable_pipe_clock(intel_crtc->config);
> >
> > intel_encoders_post_disable(crtc, old_crtc_state, old_state);
> > +   skl_wa_clkgate(dev_priv, intel_crtc->pipe, 0);
> >  }
> 
> Unless I'm misreading the context of this patch you're applying a
> workaround, that by name seems to be for Skylake only, to: Haswell,
> Broadwell, and gen9+.
> 
> Either the name is incorrect, or the application of it.
> 
> As per BSpec the workaround seems to be for all of gen9 and only A-
> stepping of gen10.
> I don't see it listed for Haswell or Broadwell.
> 
> Cross-referencing the WA-database with Bspec, based on the HSD link, it
> seems that this issue *might* be
> WaDups1GatingDisableClockGatingForMPO; if this is the case it might make
> sense to include that WA name too. At the very least there should always be
> a comment mentioning the workaround name/number and the platform(s)
> it applies to.
> 
> Also, according to the WA database, if the above mentioned issue really is
> the same, the WA is *NOT* necessary on GLK (seeing as GLK uses gen10
> display this might make sense, though the WA database sometimes
> contains mistakes).
> 
> 
> Regards, David
> 
> >  static void i9xx_pfit_enable(struct intel_crtc *crtc)
> > --
> > 1.9.1
> >
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> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/breadcrumbs: Ignore unsubmitted signalers

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/breadcrumbs: Ignore unsubmitted 
signalers
URL   : https://patchwork.freedesktop.org/series/37725/
State : success

== Summary ==

Series 37725v1 series starting with [1/3] drm/i915/breadcrumbs: Ignore 
unsubmitted signalers
https://patchwork.freedesktop.org/api/1.0/series/37725/revisions/1/mbox/

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:418s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:422s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:372s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:485s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:483s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:486s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
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fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:454s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:570s
fi-cnl-y3total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:586s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:415s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:280s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:512s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:395s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:397s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:411s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:456s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:414s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:455s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:498s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:456s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:500s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:593s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:432s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:511s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:528s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:491s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:493s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:414s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:431s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:523s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:394s
Blacklisted hosts:
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:469s

078873da383505cf8d6940229007115b31f1d5e0 drm-tip: 2018y-02m-06d-11h-21m-36s UTC 
integration manifest
06cce83ed7fa drm/i915/breadcrumbs: Assert all missed breadcrumbs were signaled
3a037acef6dd drm/i915/breadcrumbs: Reduce signaler rbtree to a sorted list
400fe69d6f7c drm/i915/breadcrumbs: Ignore unsubmitted signalers

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7905/issues.html
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Re: [Intel-gfx] [PATCH xf86-video-intel] sna/video: Try to use hw scaling with SKL+ sprites

[Chris Wilson]

Quoting Chris Wilson (2018-02-02 21:15:09)
> Quoting Ville Syrjala (2018-02-02 20:42:52)
> > From: Ville Syrjälä 
> > 
> > SKL reintroduced plane scaling once more. Let's try to make use of it.
> > 
> > The one annoying caveat is that you can't do colorkeying and scaling at
> > the same time :(  For now we'll leave the choice of colorkey vs.
> > scaling to the user via that XV_ALWAYS_ON_TOP attribute.
> 
> Fair enough, that attribute is fairly magic to force the plane to act as
> an overlay plane and keep X's grubby hands off. Having it autoscale
> would be fun :)
>  
> > One possible idea for improving the situation would be to add support
> > for autopaint colorkey, and automatically disable the colorkey whenever
> > the window is not obscured by anything and autopaint colorkey is enabled.
> 
> Ok, the way you've written it, it should allow us to extend support as
> desired. Lgtm, thanks.

And pushed, thanks.
-Chris
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[Intel-gfx] [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

[Vidya Srinivas]

If the fb format is YUV, enable the plane CSC mode bits
for the conversion.

Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/i915_reg.h  | 6 ++
 drivers/gpu/drm/i915/intel_display.c | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 18be7be..f813406 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6426,6 +6426,12 @@ enum {
 #define _PLANE_COLOR_CTL_3_A   0x703CC /* GLK+ */
 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30)
 #define   PLANE_COLOR_PIPE_CSC_ENABLE  (1 << 23)
+#define PLANE_COLOR_CSC_MASK   (0x7 << 17)
+#define PLANE_COLOR_CSC_MODE_BYPASS(0 << 17)
+#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709  (1 << 17)
+#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709  (2 << 17)
+#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020(3 << 17)
+#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
 #define   PLANE_COLOR_PLANE_GAMMA_DISABLE  (1 << 13)
 #define   PLANE_COLOR_ALPHA_MASK   (0x3 << 4)
 #define   PLANE_COLOR_ALPHA_DISABLE(0 << 4)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index b4a5e05..d34adda 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3577,6 +3577,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state 
*crtc_state,
plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
+   if (intel_format_is_yuv(fb->format->format))
+   plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
 
return plane_color_ctl;
 }
-- 
2.7.4

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[Intel-gfx] [PATCH 11/16] drm/i915: Update format_is_yuv() to include NV12

[Vidya Srinivas]

From: Chandra Konduru 

This patch adds NV12 to format_is_yuv() function
for sprite planes.

v2:
-Use intel_ prefix for format_is_yuv (Ville)

v3: Rebased (me)

v4: Rebased and addressed review comments from Clinton A Taylor.
"static function in intel_sprite.c is not available
to the primary plane functions".
Changed commit message - function modified for
sprite planes.

v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v6: Rebased (me)

v7: Rebased (me)

v8: Rebased (me)

v9: Rebased (me)

v10: Changed intel_format_is_yuv function from
static to non-static. We need to use it later from
other files for check.

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_drv.h| 1 +
 drivers/gpu/drm/i915/intel_sprite.c | 8 
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 65dac21..d4c027a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2032,6 +2032,7 @@ void skl_disable_plane(struct intel_plane *plane, struct 
intel_crtc *crtc);
 bool skl_plane_get_hw_state(struct intel_plane *plane);
 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
   enum pipe pipe, enum plane_id plane_id);
+bool intel_format_is_yuv(uint32_t format);
 
 /* intel_tv.c */
 void intel_tv_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 3be22c0..9e31be2 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -41,14 +41,14 @@
 #include 
 #include "i915_drv.h"
 
-static bool
-format_is_yuv(uint32_t format)
+bool intel_format_is_yuv(uint32_t format)
 {
switch (format) {
case DRM_FORMAT_YUYV:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_YVYU:
+   case DRM_FORMAT_NV12:
return true;
default:
return false;
@@ -352,7 +352,7 @@ chv_update_csc(struct intel_plane *plane, uint32_t format)
enum plane_id plane_id = plane->id;
 
/* Seems RGB data bypasses the CSC always */
-   if (!format_is_yuv(format))
+   if (!intel_format_is_yuv(format))
return;
 
/*
@@ -979,7 +979,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
src_y = src->y1 >> 16;
src_h = drm_rect_height(src) >> 16;
 
-   if (format_is_yuv(fb->format->format)) {
+   if (intel_format_is_yuv(fb->format->format)) {
src_x &= ~1;
src_w &= ~1;
 
-- 
2.7.4

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[Intel-gfx] [PATCH 15/16] drm/i915: Add NV12 support to intel_framebuffer_init

[Vidya Srinivas]

From: Chandra Konduru 

This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.

v2:
-Fix an issue in checks added (Chandra Konduru)

v3: rebased (me)

v4: Review comments by Ville addressed
Added platform check for NV12 in intel_framebuffer_init
Removed offset checks for NV12 case

v5: Addressed review comments by Clinton A Taylor
This NV12 support only correctly works on SKL.
Plane color space conversion is different on GLK and later platforms
causing the colors to display incorrectly.
Ville's plane color space property patch series
in review will fix this issue.
- Restricted the NV12 case in intel_framebuffer_init to
SKL and BXT only.

v6: Rebased (me)

v7: Addressed review comments by Ville
Restricting the NV12 to BXT for now.

v8: Rebased (me)
Restricting the NV12 changes to BXT and KBL for now.

v9: Rebased (me)

v10: NV12 supported by all GEN >= 9.
Making this change in intel_framebuffer_init. This is
part of addressing Maarten's review comments.
Comment under v8 no longer applicable

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_display.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 24248c7..b4a5e05 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14040,6 +14040,14 @@ static int intel_framebuffer_init(struct 
intel_framebuffer *intel_fb,
goto err;
}
break;
+   case DRM_FORMAT_NV12:
+   if (INTEL_GEN(dev_priv) < 9) {
+   DRM_DEBUG_KMS("unsupported pixel format: %s\n",
+ drm_get_format_name(mode_cmd->pixel_format,
+   _name));
+   goto err;
+   }
+   break;
default:
DRM_DEBUG_KMS("unsupported pixel format: %s\n",
  drm_get_format_name(mode_cmd->pixel_format, 
_name));
-- 
2.7.4

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[Intel-gfx] [PATCH 08/16] drm/i915/skl+: nv12 workaround disable WM level 1-7

[Vidya Srinivas]

From: Mahesh Kumar 

Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A)
Hardware sometimes fails to wake memory from pkg C states fetching the
last few lines of planar YUV 420 (NV12) planes. This causes
intermittent underflow and corruption.
WA: Disable package C states or do not enable latency levels 1 through 7
(WM1 - WM7) on NV12 planes.

v2: Addressed review comments by Maarten.

Reviewed-by: Maarten Lankhorst 
Signed-off-by: Mahesh Kumar 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_pm.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d9801bf..c37d014 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4654,6 +4654,17 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
}
}
 
+   /*
+* Display WA #826 (SKL:ALL, BXT:ALL) & #1059 (CNL:A)
+* disable wm level 1-7 on NV12 planes
+*/
+   if (wp->is_nv12 && (level >= 1) &&
+   (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
+IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {
+   result->plane_en = false;
+   return 0;
+   }
+
result->plane_res_b = res_blocks;
result->plane_res_l = res_lines;
result->plane_en = true;
-- 
2.7.4

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[Intel-gfx] [PATCH 09/16] drm/i915/skl: split skl_compute_ddb function

[Vidya Srinivas]

From: Mahesh Kumar 

This patch splits skl_compute_wm/ddb functions into two parts.
One adds all affected pipes after the commit to atomic_state structure
and second part does compute the DDB.

Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/intel_pm.c | 157 ++--
 1 file changed, 88 insertions(+), 69 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c37d014..477eaea 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5058,69 +5058,16 @@ skl_ddb_add_affected_planes(struct intel_crtc_state 
*cstate)
 static int
 skl_compute_ddb(struct drm_atomic_state *state)
 {
-   struct drm_device *dev = state->dev;
-   struct drm_i915_private *dev_priv = to_i915(dev);
+   const struct drm_i915_private *dev_priv = to_i915(state->dev);
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-   struct intel_crtc *intel_crtc;
struct skl_ddb_allocation *ddb = _state->wm_results.ddb;
-   uint32_t realloc_pipes = pipes_modified(state);
-   int ret;
-
-   /*
-* If this is our first atomic update following hardware readout,
-* we can't trust the DDB that the BIOS programmed for us.  Let's
-* pretend that all pipes switched active status so that we'll
-* ensure a full DDB recompute.
-*/
-   if (dev_priv->wm.distrust_bios_wm) {
-   ret = drm_modeset_lock(>mode_config.connection_mutex,
-  state->acquire_ctx);
-   if (ret)
-   return ret;
-
-   intel_state->active_pipe_changes = ~0;
-
-   /*
-* We usually only initialize intel_state->active_crtcs if we
-* we're doing a modeset; make sure this field is always
-* initialized during the sanitization process that happens
-* on the first commit too.
-*/
-   if (!intel_state->modeset)
-   intel_state->active_crtcs = dev_priv->active_crtcs;
-   }
-
-   /*
-* If the modeset changes which CRTC's are active, we need to
-* recompute the DDB allocation for *all* active pipes, even
-* those that weren't otherwise being modified in any way by this
-* atomic commit.  Due to the shrinking of the per-pipe allocations
-* when new active CRTC's are added, it's possible for a pipe that
-* we were already using and aren't changing at all here to suddenly
-* become invalid if its DDB needs exceeds its new allocation.
-*
-* Note that if we wind up doing a full DDB recompute, we can't let
-* any other display updates race with this transaction, so we need
-* to grab the lock on *all* CRTC's.
-*/
-   if (intel_state->active_pipe_changes) {
-   realloc_pipes = ~0;
-   intel_state->wm_results.dirty_pipes = ~0;
-   }
+   struct intel_crtc *crtc;
+   struct intel_crtc_state *cstate;
+   int ret, i;
 
-   /*
-* We're not recomputing for the pipes not included in the commit, so
-* make sure we start with the current state.
-*/
memcpy(ddb, _priv->wm.skl_hw.ddb, sizeof(*ddb));
 
-   for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
-   struct intel_crtc_state *cstate;
-
-   cstate = intel_atomic_get_crtc_state(state, intel_crtc);
-   if (IS_ERR(cstate))
-   return PTR_ERR(cstate);
-
+   for_each_new_intel_crtc_in_state(intel_state, crtc, cstate, i) {
ret = skl_allocate_pipe_ddb(cstate, ddb);
if (ret)
return ret;
@@ -5182,23 +5129,23 @@ skl_print_wm_changes(const struct drm_atomic_state 
*state)
 }
 
 static int
-skl_compute_wm(struct drm_atomic_state *state)
+skl_ddb_add_affected_pipes(struct drm_atomic_state *state, bool *changed)
 {
-   struct drm_crtc *crtc;
-   struct drm_crtc_state *cstate;
-   struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-   struct skl_ddb_values *results = _state->wm_results;
struct drm_device *dev = state->dev;
-   struct skl_pipe_wm *pipe_wm;
-   bool changed = false;
+   const struct drm_i915_private *dev_priv = to_i915(dev);
+   const struct drm_crtc *crtc;
+   const struct drm_crtc_state *cstate;
+   struct intel_crtc *intel_crtc;
+   struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+   uint32_t realloc_pipes = pipes_modified(state);
int ret, i;
 
/*
 * When we distrust bios wm we always need to recompute to set the
 * expected DDB allocations for each CRTC.
 */
-   if (to_i915(dev)->wm.distrust_bios_wm)
-   changed = true;
+   if 

[Intel-gfx] [PATCH 10/16] drm/i915: Set scaler mode for NV12

[Vidya Srinivas]

From: Chandra Konduru 

This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling

v2: Review comments from Ville addressed
NV12 case to be checked first for setting
the scaler

v3: Rebased (me)

v4: Rebased (me)

v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v6: Rebased (me)

v7: Rebased (me)

v8: Rebased (me)
Restricting the NV12 change for scaler to BXT and KBL
in this series.

v9: Rebased (me)

v10: As of now, NV12 has been tested on Gen9 and Gen10. However,
code is applicable to all GEN >= 9. Hence making
that change to keep it generic.
Comments under v8 is not valid anymore.

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_atomic.c | 8 ++--
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e9c79b5..18be7be 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6705,6 +6705,7 @@ enum {
 #define PS_SCALER_MODE_MASK (3 << 28)
 #define PS_SCALER_MODE_DYN  (0 << 28)
 #define PS_SCALER_MODE_HQ  (1 << 28)
+#define PS_SCALER_MODE_NV12 (2 << 28)
 #define PS_PLANE_SEL_MASK  (7 << 25)
 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
 #define PS_FILTER_MASK (3 << 23)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c 
b/drivers/gpu/drm/i915/intel_atomic.c
index d452c32..196427a 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -327,8 +327,12 @@ int intel_atomic_setup_scalers(struct drm_i915_private 
*dev_priv,
}
 
/* set scaler mode */
-   if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
-   scaler_state->scalers[*scaler_id].mode = 0;
+   if ((INTEL_GEN(dev_priv) >= 9) &&
+   plane_state && plane_state->base.fb &&
+   plane_state->base.fb->format->format ==
+   DRM_FORMAT_NV12) {
+   scaler_state->scalers[*scaler_id].mode =
+   PS_SCALER_MODE_NV12;
} else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) 
{
/*
 * when only 1 scaler is in use on either pipe A or B,
-- 
2.7.4

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[Intel-gfx] [PATCH 14/16] drm/i915: Add NV12 as supported format for sprite plane

[Vidya Srinivas]

From: Chandra Konduru 

This patch adds NV12 to list of supported formats for sprite plane.

v2: Rebased (me)

v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_formats
- Added the 10bpc RGB formats

v4: Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Removed 10bit RGB formats added previously with NV12 series

v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Previous version has 10bit RGB format removed from VLV formats
by mistake. Fixing that in this version.
Removed 10bit RGB formats added previously with NV12 series
for SKL.

v6: Addressed review comments by Ville
Restricting the NV12 to BXT and PIPE A and B

v7: Rebased (me)

v8: Rebased (me)
Restricting NV12 changes to BXT and KBL
Restricting NV12 changes for plane 0 (overlay)

v9: Rebased (me)

v10: Addressed review comments from Maarten.
Adding NV12 to skl_plane_formats itself.

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_sprite.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index f2e144b..f359b22 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1168,6 +1168,7 @@ static uint32_t skl_plane_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+   DRM_FORMAT_NV12,
 };
 
 static const uint64_t skl_plane_format_modifiers_noccs[] = {
@@ -1366,6 +1367,10 @@ intel_sprite_plane_create(struct drm_i915_private 
*dev_priv,
plane_formats = skl_plane_formats;
num_plane_formats = ARRAY_SIZE(skl_plane_formats);
 
+   if (INTEL_GEN(dev_priv) <= 10 && ((plane != 0) ||
+   (pipe == PIPE_C)))
+   num_plane_formats -= 1;
+
if (skl_plane_has_ccs(dev_priv, pipe, PLANE_SPRITE0 + plane))
modifiers = skl_plane_format_modifiers_ccs;
else
-- 
2.7.4

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[Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane

[Vidya Srinivas]

From: Chandra Konduru 

This patch adds NV12 to list of supported formats for
primary plane

v2: Rebased (Chandra Konduru)

v3: Rebased (me)

v4: Review comments by Ville addressed
Removed the skl_primary_formats_with_nv12 and
added NV12 case in existing skl_primary_formats

v5: Rebased (me)

v6: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v7: Review comments by Ville addressed
Restricting the NV12 for BXT and on PIPE A and B
Rebased (me)

v8: Rebased (me)
Modified restricting the NV12 support for both BXT and KBL.

v9: Rebased (me)

v10: Addressed review comments from Maarten.
Adding NV12 inside skl_primary_formats itself.

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_display.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 74757d0..24248c7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+   DRM_FORMAT_NV12,
 };
 
 static const uint64_t skl_format_modifiers_noccs[] = {
@@ -13233,6 +13234,9 @@ intel_primary_plane_create(struct drm_i915_private 
*dev_priv, enum pipe pipe)
intel_primary_formats = skl_primary_formats;
num_formats = ARRAY_SIZE(skl_primary_formats);
 
+   if (INTEL_GEN(dev_priv) == 9 && (pipe == PIPE_C))
+   num_formats -= 1;
+
if (skl_plane_has_ccs(dev_priv, pipe, PLANE_PRIMARY))
modifiers = skl_format_modifiers_ccs;
else
-- 
2.7.4

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[Intel-gfx] [PATCH 12/16] drm/i915: Upscale scaler max scale for NV12

[Vidya Srinivas]

From: Chandra Konduru 

This patch updates scaler max limit support for NV12

v2: Rebased (me)

v3: Rebased (me)

v4: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v5: Addressed review comments from Ville and rebased
- calculation of max_scale to be made
less convoluted by splitting it up a bit
- Indentation errors to be fixed in the series

v6: Rebased (me)
Fixed review comments from Paauwe, Bob J
Previous version, where a split of calculation
was done, was wrong. Fixed that issue here.

v7: Rebased (me)

v8: Rebased (me)

v9: Rebased (me)

v10: Rebased (me)

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_display.c | 33 +++--
 drivers/gpu/drm/i915/intel_drv.h |  3 ++-
 drivers/gpu/drm/i915/intel_sprite.c  |  3 ++-
 3 files changed, 27 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 5fc9255..74757d0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3435,6 +3435,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
case DRM_FORMAT_VYUY:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
+   case DRM_FORMAT_NV12:
+   return PLANE_CTL_FORMAT_NV12;
default:
MISSING_CASE(pixel_format);
}
@@ -4658,7 +4660,8 @@ static void cpt_verify_modeset(struct drm_device *dev, 
int pipe)
 static int
 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
  unsigned int scaler_user, int *scaler_id,
- int src_w, int src_h, int dst_w, int dst_h)
+ int src_w, int src_h, int dst_w, int dst_h,
+ uint32_t pixel_format)
 {
struct intel_crtc_scaler_state *scaler_state =
_state->scaler_state;
@@ -4674,7 +4677,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, 
bool force_detach,
 * the 90/270 degree plane rotation cases (to match the
 * GTT mapping), hence no need to account for rotation here.
 */
-   need_scaling = src_w != dst_w || src_h != dst_h;
+   need_scaling = src_w != dst_w || src_h != dst_h ||
+  (pixel_format == DRM_FORMAT_NV12);
 
if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
need_scaling = true;
@@ -4753,7 +4757,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state)
return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
>scaler_state.scaler_id,
state->pipe_src_w, state->pipe_src_h,
-   adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
+   adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay, 0);
 }
 
 /**
@@ -4783,7 +4787,8 @@ static int skl_update_scaler_plane(struct 
intel_crtc_state *crtc_state,
drm_rect_width(_state->base.src) >> 16,
drm_rect_height(_state->base.src) >> 16,
drm_rect_width(_state->base.dst),
-   drm_rect_height(_state->base.dst));
+   drm_rect_height(_state->base.dst),
+   fb ? fb->format->format : 0);
 
if (ret || plane_state->scaler_id < 0)
return ret;
@@ -4809,6 +4814,7 @@ static int skl_update_scaler_plane(struct 
intel_crtc_state *crtc_state,
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+   case DRM_FORMAT_NV12:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 
0x%x\n",
@@ -12758,11 +12764,12 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
 }
 
 int
-skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state 
*crtc_state)
+skl_max_scale(struct intel_crtc *intel_crtc,
+   struct intel_crtc_state *crtc_state, uint32_t pixel_format)
 {
struct drm_i915_private *dev_priv;
-   int max_scale;
-   int crtc_clock, max_dotclk;
+   int max_scale, mult;
+   int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
 
if (!intel_crtc || !crtc_state->base.enable)
return DRM_PLANE_HELPER_NO_SCALING;
@@ -12784,8 +12791,10 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct 
intel_crtc_state *crtc_state
 *or
 *cdclk/crtc_clock
 */
-   max_scale = min((1 << 16) * 3 - 1,
-   (1 << 8) * ((max_dotclk << 

[Intel-gfx] [PATCH 07/16] drm/i915/skl+: make sure higher latency level has higher wm value

[Vidya Srinivas]

From: Mahesh Kumar 

DDB allocation optimization algorithm requires/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below.
Render decompression requires level WM to be as high as wm level-0.
This patch fulfils both the requirements.

Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/intel_pm.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 07fc084..d9801bf 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4531,6 +4531,7 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
uint16_t ddb_allocation,
int level,
const struct skl_wm_params *wp,
+   const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */)
 {
const struct drm_plane_state *pstate = _pstate->base;
@@ -4598,6 +4599,15 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
} else {
res_blocks++;
}
+
+   /*
+* Make sure result blocks for higher latency levels are atleast
+* as high as level below.
+* Assumption in DDB algorithm optimization for special cases.
+* Also covers Display WA #1125 for RC.
+*/
+   if (result_prev->plane_res_b > res_blocks)
+   res_blocks = result_prev->plane_res_b;
}
 
if (INTEL_GEN(dev_priv) >= 11) {
@@ -4680,6 +4690,13 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = plane_num ? >uv_wm[level] :
  >wm[level];
+   struct skl_wm_level *result_prev;
+
+   if (level)
+   result_prev = plane_num ? >uv_wm[level - 1] :
+ >wm[level - 1];
+   else
+   result_prev = plane_num ? >uv_wm[0] : >wm[0];
 
ret = skl_compute_plane_wm(dev_priv,
   cstate,
@@ -4687,6 +4704,7 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
   ddb_blocks,
   level,
   wm_params,
+  result_prev,
   result);
if (ret)
return ret;
-- 
2.7.4

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[Intel-gfx] [PATCH 02/16] drm/i915/skl+: refactor WM calculation for NV12

[Vidya Srinivas]

From: Mahesh Kumar 

Current code calculates DDB for planar formats in such a way that we
store DDB of plane-0 in plane 1 & vice-versa.
In order to make this clean this patch refactors WM/DDB calculation for
NV12 planar formats.

v2: Addressed review comments by Maarten

v3: Rebased and addressed review comments by Maarten

Reviewed-by: Maarten Lankhorst 
Signed-off-by: Mahesh Kumar 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/i915_drv.h  |   5 +-
 drivers/gpu/drm/i915/intel_drv.h |   1 +
 drivers/gpu/drm/i915/intel_pm.c  | 121 ---
 3 files changed, 66 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d73e0a2..35d1663 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1440,8 +1440,9 @@ static inline bool skl_ddb_entry_equal(const struct 
skl_ddb_entry *e1,
 }
 
 struct skl_ddb_allocation {
-   struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* 
packed/uv */
-   struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
+   /* packed/y */
+   struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
+   struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
 };
 
 struct skl_ddb_values {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 61d9946..35ee715 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -595,6 +595,7 @@ struct intel_pipe_wm {
 struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level trans_wm;
+   bool is_nv12;
 };
 
 struct skl_pipe_wm {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0cd5e95..1546bc8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4012,9 +4012,9 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc 
*intel_crtc,
 static unsigned int
 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
 const struct drm_plane_state *pstate,
-int y)
+const int plane)
 {
-   struct intel_plane *plane = to_intel_plane(pstate->plane);
+   struct intel_plane *intel_plane = to_intel_plane(pstate->plane);
struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
uint32_t data_rate;
uint32_t width = 0, height = 0;
@@ -4028,9 +4028,9 @@ skl_plane_relative_data_rate(const struct 
intel_crtc_state *cstate,
fb = pstate->fb;
format = fb->format->format;
 
-   if (plane->id == PLANE_CURSOR)
+   if (intel_plane->id == PLANE_CURSOR)
return 0;
-   if (y && format != DRM_FORMAT_NV12)
+   if (plane == 1 && format != DRM_FORMAT_NV12)
return 0;
 
/*
@@ -4041,19 +4041,14 @@ skl_plane_relative_data_rate(const struct 
intel_crtc_state *cstate,
width = drm_rect_width(_pstate->base.src) >> 16;
height = drm_rect_height(_pstate->base.src) >> 16;
 
-   /* for planar format */
-   if (format == DRM_FORMAT_NV12) {
-   if (y)  /* y-plane data rate */
-   data_rate = width * height *
-   fb->format->cpp[0];
-   else/* uv-plane data rate */
-   data_rate = (width / 2) * (height / 2) *
-   fb->format->cpp[1];
-   } else {
-   /* for packed formats */
-   data_rate = width * height * fb->format->cpp[0];
+   /* UV plane does 1/2 pixel sub-sampling */
+   if (plane == 1 && format == DRM_FORMAT_NV12) {
+   width /= 2;
+   height /= 2;
}
 
+   data_rate = width * height * fb->format->cpp[plane];
+
down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
 
return mul_round_up_u32_fixed16(data_rate, down_scale_amount);
@@ -4066,8 +4061,8 @@ skl_plane_relative_data_rate(const struct 
intel_crtc_state *cstate,
  */
 static unsigned int
 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
-unsigned *plane_data_rate,
-unsigned *plane_y_data_rate)
+unsigned int *plane_data_rate,
+unsigned int *uv_plane_data_rate)
 {
struct drm_crtc_state *cstate = _cstate->base;
struct drm_atomic_state *state = cstate->state;
@@ -4083,17 +4078,17 @@ skl_get_total_relative_data_rate(struct 
intel_crtc_state *intel_cstate,
enum plane_id plane_id = to_intel_plane(plane)->id;
unsigned int rate;
 
-   /* packed/uv */
+   /* packed/y */
rate = 

[Intel-gfx] [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM

[Vidya Srinivas]

From: Mahesh Kumar 

NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.

Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c  | 54 
 3 files changed, 45 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cca5414..778dc5a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1459,6 +1459,7 @@ struct skl_wm_level {
 struct skl_wm_params {
bool x_tiled, y_tiled;
bool rc_surface;
+   bool is_nv12;
uint32_t width;
uint8_t cpp;
uint32_t plane_pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ed33840..65dac21 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -594,6 +594,7 @@ struct intel_pipe_wm {
 
 struct skl_plane_wm {
struct skl_wm_level wm[8];
+   struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
bool is_nv12;
 };
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4c9a811..b3d1bf7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4421,7 +4421,7 @@ static int
 skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
struct intel_crtc_state *cstate,
const struct intel_plane_state *intel_pstate,
-   struct skl_wm_params *wp)
+   struct skl_wm_params *wp, int plane_num)
 {
struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
const struct drm_plane_state *pstate = _pstate->base;
@@ -4434,6 +4434,12 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
if (!intel_wm_plane_visible(cstate, intel_pstate))
return 0;
 
+   /* only NV12 format has two planes */
+   if (plane_num == 1 && fb->format->format != DRM_FORMAT_NV12) {
+   DRM_DEBUG_KMS("Non NV12 format have single plane\n");
+   return -EINVAL;
+   }
+
wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
  fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
  fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
@@ -4441,6 +4447,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private 
*dev_priv,
wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+   wp->is_nv12 = fb->format->format == DRM_FORMAT_NV12;
 
if (plane->id == PLANE_CURSOR) {
wp->width = intel_pstate->base.crtc_w;
@@ -4453,7 +4460,10 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
wp->width = drm_rect_width(_pstate->base.src) >> 16;
}
 
-   wp->cpp = fb->format->cpp[0];
+   if (plane_num == 1 && wp->is_nv12)
+   wp->width /= 2;
+
+   wp->cpp = fb->format->cpp[plane_num];
wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
 intel_pstate);
 
@@ -4649,7 +4659,8 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
  struct intel_crtc_state *cstate,
  const struct intel_plane_state *intel_pstate,
  const struct skl_wm_params *wm_params,
- struct skl_plane_wm *wm)
+ struct skl_plane_wm *wm,
+ int plane_num)
 {
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_plane *plane = intel_pstate->base.plane;
@@ -4657,15 +4668,20 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
uint16_t ddb_blocks;
enum pipe pipe = intel_crtc->pipe;
int level, max_level = ilk_wm_max_level(dev_priv);
+   enum plane_id plane_id = intel_plane->id;
int ret;
 
if (WARN_ON(!intel_pstate->base.fb))
return -EINVAL;
 
-   ddb_blocks = skl_ddb_entry_size(>plane[pipe][intel_plane->id]);
+   if (plane_num == 0)
+   ddb_blocks = skl_ddb_entry_size(>plane[pipe][plane_id]);
+   else
+   ddb_blocks = skl_ddb_entry_size(>uv_plane[pipe][plane_id]);
 
for (level = 0; level <= max_level; level++) {
-   struct skl_wm_level *result = >wm[level];
+   struct skl_wm_level *result = plane_num ? >uv_wm[level] :
+ >wm[level];
 
ret = skl_compute_plane_wm(dev_priv,
  

[Intel-gfx] [PATCH 01/16] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

[Vidya Srinivas]

From: Mahesh Kumar 

skl_wm_values struct contains values of pipe/plane DDB only.
so rename it for better readability of code. Similarly
skl_copy_wm_for_pipe copies DDB values.

s/skl_wm_values/skl_ddb_values
s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe

Changes since V1:
 - also change name of skl_copy_wm_for_pipe

Reviewed-by: Maarten Lankhorst 
Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/i915_drv.h  |  4 ++--
 drivers/gpu/drm/i915/intel_drv.h |  2 +-
 drivers/gpu/drm/i915/intel_pm.c  | 14 +++---
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d6b5ac2..d73e0a2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1444,7 +1444,7 @@ struct skl_ddb_allocation {
struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
 };
 
-struct skl_wm_values {
+struct skl_ddb_values {
unsigned dirty_pipes;
struct skl_ddb_allocation ddb;
 };
@@ -2139,7 +2139,7 @@ struct drm_i915_private {
/* current hardware state */
union {
struct ilk_wm_values hw;
-   struct skl_wm_values skl_hw;
+   struct skl_ddb_values skl_hw;
struct vlv_wm_values vlv;
struct g4x_wm_values g4x;
};
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 468ec1e..61d9946 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -480,7 +480,7 @@ struct intel_atomic_state {
bool skip_intermediate_wm;
 
/* Gen9+ only */
-   struct skl_wm_values wm_results;
+   struct skl_ddb_values wm_results;
 
struct i915_sw_fence commit_ready;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index eb68abf..0cd5e95 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5042,8 +5042,8 @@ skl_compute_ddb(struct drm_atomic_state *state)
 }
 
 static void
-skl_copy_wm_for_pipe(struct skl_wm_values *dst,
-struct skl_wm_values *src,
+skl_copy_ddb_for_pipe(struct skl_ddb_values *dst,
+struct skl_ddb_values *src,
 enum pipe pipe)
 {
memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
@@ -5095,7 +5095,7 @@ skl_compute_wm(struct drm_atomic_state *state)
struct drm_crtc *crtc;
struct drm_crtc_state *cstate;
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-   struct skl_wm_values *results = _state->wm_results;
+   struct skl_ddb_values *results = _state->wm_results;
struct drm_device *dev = state->dev;
struct skl_pipe_wm *pipe_wm;
bool changed = false;
@@ -5197,8 +5197,8 @@ static void skl_initial_wm(struct intel_atomic_state 
*state,
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_device *dev = intel_crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
-   struct skl_wm_values *results = >wm_results;
-   struct skl_wm_values *hw_vals = _priv->wm.skl_hw;
+   struct skl_ddb_values *results = >wm_results;
+   struct skl_ddb_values *hw_vals = _priv->wm.skl_hw;
enum pipe pipe = intel_crtc->pipe;
 
if ((results->dirty_pipes & drm_crtc_mask(_crtc->base)) == 0)
@@ -5209,7 +5209,7 @@ static void skl_initial_wm(struct intel_atomic_state 
*state,
if (cstate->base.active_changed)
skl_atomic_update_crtc_wm(state, cstate);
 
-   skl_copy_wm_for_pipe(hw_vals, results, pipe);
+   skl_copy_ddb_for_pipe(hw_vals, results, pipe);
 
mutex_unlock(_priv->wm.wm_mutex);
 }
@@ -5341,7 +5341,7 @@ void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
 void skl_wm_get_hw_state(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = to_i915(dev);
-   struct skl_wm_values *hw = _priv->wm.skl_hw;
+   struct skl_ddb_values *hw = _priv->wm.skl_hw;
struct skl_ddb_allocation *ddb = _priv->wm.skl_hw.ddb;
struct drm_crtc *crtc;
struct intel_crtc *intel_crtc;
-- 
2.7.4

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[Intel-gfx] [PATCH 00/16] Adding NV12 support

[Vidya Srinivas]

This patch series is adding NV12 support for Broxton display after rebasing on
latest drm-tip.
Initial series of the patches can be found here:
https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html

Previous revision history:
The first version of patches were reviewed when floated by Chandra in 2015
but currently there was a design change with respect to
- the way fb offset is handled
- the way rotation is handled
Current NV12 patch series has been ported as per the
current changes on drm-tip

Review comments from Ville (12th June 2017) have been addressed Review
comments from Clinton A Taylor (7th July 2017) have been addressed

Review comments from Clinton A Taylor (10th July 2017)
have been addressed. Had missed out tested-by/reviewed-by in the 
patches.

Fixed that error in this series.
Review comments from Ville (11th July 2017) addressed.
Review comments from Paauwe, Bob (29th July 2017) addressed.

Update from rev 28 Aug 2017
Rebased the series.
Tested with IGT for rotation, sprite and tiling combinations.
IGT Links:
https://patchwork.kernel.org/patch/9995943/
https://patchwork.kernel.org/patch/9995945/

Update from last rev:
Rebased the series.
Review comments by Maarten are addressed in this series.
NV12 enabled for Gen10.

Chandra Konduru (6):
  drm/i915: Set scaler mode for NV12
  drm/i915: Update format_is_yuv() to include NV12
  drm/i915: Upscale scaler max scale for NV12
  drm/i915: Add NV12 as supported format for primary plane
  drm/i915: Add NV12 as supported format for sprite plane
  drm/i915: Add NV12 support to intel_framebuffer_init

Mahesh Kumar (9):
  drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
  drm/i915/skl+: refactor WM calculation for NV12
  drm/i915/skl+: add NV12 in skl_format_to_fourcc
  drm/i915/skl+: support verification of DDB HW state for NV12
  drm/i915/skl+: NV12 related changes for WM
  drm/i915/skl+: pass skl_wm_level struct to wm compute func
  drm/i915/skl+: make sure higher latency level has higher wm value
  drm/i915/skl+: nv12 workaround disable WM level 1-7
  drm/i915/skl: split skl_compute_ddb function

Vidya Srinivas (1):
  drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

 drivers/gpu/drm/i915/i915_drv.h  |   9 +-
 drivers/gpu/drm/i915/i915_reg.h  |   7 +
 drivers/gpu/drm/i915/intel_atomic.c  |   8 +-
 drivers/gpu/drm/i915/intel_display.c |  51 +++-
 drivers/gpu/drm/i915/intel_drv.h |   9 +-
 drivers/gpu/drm/i915/intel_pm.c  | 435 ++-
 drivers/gpu/drm/i915/intel_sprite.c  |  16 +-
 7 files changed, 349 insertions(+), 186 deletions(-)

-- 
2.7.4

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[Intel-gfx] [PATCH 06/16] drm/i915/skl+: pass skl_wm_level struct to wm compute func

[Vidya Srinivas]

From: Mahesh Kumar 

This will reduce number of arguments required to be passed in
skl_compute_plane_wm function.

Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/intel_pm.c | 18 +++---
 1 file changed, 7 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b3d1bf7..07fc084 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4531,9 +4531,7 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
uint16_t ddb_allocation,
int level,
const struct skl_wm_params *wp,
-   uint16_t *out_blocks, /* out */
-   uint8_t *out_lines, /* out */
-   bool *enabled /* out */)
+   struct skl_wm_level *result /* out */)
 {
const struct drm_plane_state *pstate = _pstate->base;
uint32_t latency = dev_priv->wm.skl_latency[level];
@@ -4547,7 +4545,7 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
 
if (latency == 0 ||
!intel_wm_plane_visible(cstate, intel_pstate)) {
-   *enabled = false;
+   result->plane_en = false;
return 0;
}
 
@@ -4627,7 +4625,7 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
 
if (res_blocks >= ddb_allocation || res_lines > 31 ||
min_disp_buf_needed >= ddb_allocation) {
-   *enabled = false;
+   result->plane_en = false;
 
/*
 * If there are no valid level 0 watermarks, then we can't
@@ -4646,9 +4644,9 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
}
}
 
-   *out_blocks = res_blocks;
-   *out_lines = res_lines;
-   *enabled = true;
+   result->plane_res_b = res_blocks;
+   result->plane_res_l = res_lines;
+   result->plane_en = true;
 
return 0;
 }
@@ -4689,9 +4687,7 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
   ddb_blocks,
   level,
   wm_params,
-  >plane_res_b,
-  >plane_res_l,
-  >plane_en);
+  result);
if (ret)
return ret;
}
-- 
2.7.4

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[Intel-gfx] [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12

[Vidya Srinivas]

From: Mahesh Kumar 

NV12 formats have two registers for DDB. Verify both the registers for
NV12 during verify_wm_state.

v2: Addressed review comments by Maarten.

Signed-off-by: Mahesh Kumar 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_display.c |  2 +-
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c  | 50 
 3 files changed, 42 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index e3a6a7f..5fc9255 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2621,7 +2621,7 @@ static int i9xx_format_to_fourcc(int format)
}
 }
 
-static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
+int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
 {
switch (format) {
case PLANE_CTL_FORMAT_RGB_565:
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 35ee715..ed33840 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1595,6 +1595,7 @@ u32 skl_plane_stride(const struct drm_framebuffer *fb, 
int plane,
 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state);
 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
+int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
 
 /* intel_csr.c */
 void intel_csr_ucode_init(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5bff004..4c9a811 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3828,6 +3828,43 @@ static void skl_ddb_entry_init_from_hw(struct 
skl_ddb_entry *entry, u32 reg)
entry->end += 1;
 }
 
+static void
+skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
+  const enum pipe pipe,
+  const enum plane_id plane_id,
+  struct skl_ddb_allocation *ddb /* out */)
+{
+   u32 val, val2 = 0;
+   int fourcc, pixel_format;
+
+   /* Cursor doesn't support NV12, so no extra calculation needed */
+   if (plane_id == PLANE_CURSOR) {
+   val = I915_READ(CUR_BUF_CFG(pipe));
+   skl_ddb_entry_init_from_hw(>plane[pipe][plane_id], val);
+   return;
+   }
+
+   val = I915_READ(PLANE_CTL(pipe, plane_id));
+
+   /* No DDB allocated for disabled planes */
+   if (!(val & PLANE_CTL_ENABLE))
+   return;
+
+   pixel_format = val & PLANE_CTL_FORMAT_MASK;
+   fourcc = skl_format_to_fourcc(pixel_format,
+ val & PLANE_CTL_ORDER_RGBX,
+ val & PLANE_CTL_ALPHA_MASK);
+
+   val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
+   val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
+
+   if (fourcc == DRM_FORMAT_NV12) {
+   skl_ddb_entry_init_from_hw(>plane[pipe][plane_id], val2);
+   skl_ddb_entry_init_from_hw(>uv_plane[pipe][plane_id], val);
+   } else
+   skl_ddb_entry_init_from_hw(>plane[pipe][plane_id], val);
+}
+
 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
  struct skl_ddb_allocation *ddb /* out */)
 {
@@ -3844,16 +3881,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private 
*dev_priv,
if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
continue;
 
-   for_each_plane_id_on_crtc(crtc, plane_id) {
-   u32 val;
-
-   if (plane_id != PLANE_CURSOR)
-   val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
-   else
-   val = I915_READ(CUR_BUF_CFG(pipe));
-
-   skl_ddb_entry_init_from_hw(>plane[pipe][plane_id], 
val);
-   }
+   for_each_plane_id_on_crtc(crtc, plane_id)
+   skl_ddb_get_hw_plane_state(dev_priv, pipe,
+  plane_id, ddb);
 
intel_display_power_put(dev_priv, power_domain);
}
-- 
2.7.4

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[Intel-gfx] [PATCH 03/16] drm/i915/skl+: add NV12 in skl_format_to_fourcc

[Vidya Srinivas]

From: Mahesh Kumar 

Add support of recognizing DRM_FORMAT_NV12 from plane_format
register value.

Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/intel_display.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 60ba5bb..e3a6a7f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2626,6 +2626,8 @@ static int skl_format_to_fourcc(int format, bool 
rgb_order, bool alpha)
switch (format) {
case PLANE_CTL_FORMAT_RGB_565:
return DRM_FORMAT_RGB565;
+   case PLANE_CTL_FORMAT_NV12:
+   return DRM_FORMAT_NV12;
default:
case PLANE_CTL_FORMAT_XRGB_:
if (rgb_order) {
-- 
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[Intel-gfx] [PATCH 11/16] drm/i915: Update format_is_yuv() to include NV12

[Vidya Srinivas]

From: Chandra Konduru 

This patch adds NV12 to format_is_yuv() function
for sprite planes.

v2:
-Use intel_ prefix for format_is_yuv (Ville)

v3: Rebased (me)

v4: Rebased and addressed review comments from Clinton A Taylor.
"static function in intel_sprite.c is not available
to the primary plane functions".
Changed commit message - function modified for
sprite planes.

v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v6: Rebased (me)

v7: Rebased (me)

v8: Rebased (me)

v9: Rebased (me)

v10: Changed intel_format_is_yuv function from
static to non-static. We need to use it later from
other files for check.

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_drv.h| 1 +
 drivers/gpu/drm/i915/intel_sprite.c | 8 
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 65dac21..d4c027a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2032,6 +2032,7 @@ void skl_disable_plane(struct intel_plane *plane, struct 
intel_crtc *crtc);
 bool skl_plane_get_hw_state(struct intel_plane *plane);
 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
   enum pipe pipe, enum plane_id plane_id);
+bool intel_format_is_yuv(uint32_t format);
 
 /* intel_tv.c */
 void intel_tv_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 3be22c0..9e31be2 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -41,14 +41,14 @@
 #include 
 #include "i915_drv.h"
 
-static bool
-format_is_yuv(uint32_t format)
+bool intel_format_is_yuv(uint32_t format)
 {
switch (format) {
case DRM_FORMAT_YUYV:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_YVYU:
+   case DRM_FORMAT_NV12:
return true;
default:
return false;
@@ -352,7 +352,7 @@ chv_update_csc(struct intel_plane *plane, uint32_t format)
enum plane_id plane_id = plane->id;
 
/* Seems RGB data bypasses the CSC always */
-   if (!format_is_yuv(format))
+   if (!intel_format_is_yuv(format))
return;
 
/*
@@ -979,7 +979,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
src_y = src->y1 >> 16;
src_h = drm_rect_height(src) >> 16;
 
-   if (format_is_yuv(fb->format->format)) {
+   if (intel_format_is_yuv(fb->format->format)) {
src_x &= ~1;
src_w &= ~1;
 
-- 
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[Intel-gfx] [PATCH 15/16] drm/i915: Add NV12 support to intel_framebuffer_init

[Vidya Srinivas]

From: Chandra Konduru 

This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.

v2:
-Fix an issue in checks added (Chandra Konduru)

v3: rebased (me)

v4: Review comments by Ville addressed
Added platform check for NV12 in intel_framebuffer_init
Removed offset checks for NV12 case

v5: Addressed review comments by Clinton A Taylor
This NV12 support only correctly works on SKL.
Plane color space conversion is different on GLK and later platforms
causing the colors to display incorrectly.
Ville's plane color space property patch series
in review will fix this issue.
- Restricted the NV12 case in intel_framebuffer_init to
SKL and BXT only.

v6: Rebased (me)

v7: Addressed review comments by Ville
Restricting the NV12 to BXT for now.

v8: Rebased (me)
Restricting the NV12 changes to BXT and KBL for now.

v9: Rebased (me)

v10: NV12 supported by all GEN >= 9.
Making this change in intel_framebuffer_init. This is
part of addressing Maarten's review comments.
Comment under v8 no longer applicable

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_display.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 24248c7..b4a5e05 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14040,6 +14040,14 @@ static int intel_framebuffer_init(struct 
intel_framebuffer *intel_fb,
goto err;
}
break;
+   case DRM_FORMAT_NV12:
+   if (INTEL_GEN(dev_priv) < 9) {
+   DRM_DEBUG_KMS("unsupported pixel format: %s\n",
+ drm_get_format_name(mode_cmd->pixel_format,
+   _name));
+   goto err;
+   }
+   break;
default:
DRM_DEBUG_KMS("unsupported pixel format: %s\n",
  drm_get_format_name(mode_cmd->pixel_format, 
_name));
-- 
2.7.4

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[Intel-gfx] [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

[Vidya Srinivas]

If the fb format is YUV, enable the plane CSC mode bits
for the conversion.

Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/i915_reg.h  | 6 ++
 drivers/gpu/drm/i915/intel_display.c | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 18be7be..f813406 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6426,6 +6426,12 @@ enum {
 #define _PLANE_COLOR_CTL_3_A   0x703CC /* GLK+ */
 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30)
 #define   PLANE_COLOR_PIPE_CSC_ENABLE  (1 << 23)
+#define PLANE_COLOR_CSC_MASK   (0x7 << 17)
+#define PLANE_COLOR_CSC_MODE_BYPASS(0 << 17)
+#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709  (1 << 17)
+#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709  (2 << 17)
+#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020(3 << 17)
+#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
 #define   PLANE_COLOR_PLANE_GAMMA_DISABLE  (1 << 13)
 #define   PLANE_COLOR_ALPHA_MASK   (0x3 << 4)
 #define   PLANE_COLOR_ALPHA_DISABLE(0 << 4)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index b4a5e05..d34adda 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3577,6 +3577,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state 
*crtc_state,
plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
+   if (intel_format_is_yuv(fb->format->format))
+   plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
 
return plane_color_ctl;
 }
-- 
2.7.4

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[Intel-gfx] [PATCH 10/16] drm/i915: Set scaler mode for NV12

[Vidya Srinivas]

From: Chandra Konduru 

This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling

v2: Review comments from Ville addressed
NV12 case to be checked first for setting
the scaler

v3: Rebased (me)

v4: Rebased (me)

v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v6: Rebased (me)

v7: Rebased (me)

v8: Rebased (me)
Restricting the NV12 change for scaler to BXT and KBL
in this series.

v9: Rebased (me)

v10: As of now, NV12 has been tested on Gen9 and Gen10. However,
code is applicable to all GEN >= 9. Hence making
that change to keep it generic.
Comments under v8 is not valid anymore.

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_atomic.c | 8 ++--
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e9c79b5..18be7be 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6705,6 +6705,7 @@ enum {
 #define PS_SCALER_MODE_MASK (3 << 28)
 #define PS_SCALER_MODE_DYN  (0 << 28)
 #define PS_SCALER_MODE_HQ  (1 << 28)
+#define PS_SCALER_MODE_NV12 (2 << 28)
 #define PS_PLANE_SEL_MASK  (7 << 25)
 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
 #define PS_FILTER_MASK (3 << 23)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c 
b/drivers/gpu/drm/i915/intel_atomic.c
index d452c32..196427a 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -327,8 +327,12 @@ int intel_atomic_setup_scalers(struct drm_i915_private 
*dev_priv,
}
 
/* set scaler mode */
-   if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
-   scaler_state->scalers[*scaler_id].mode = 0;
+   if ((INTEL_GEN(dev_priv) >= 9) &&
+   plane_state && plane_state->base.fb &&
+   plane_state->base.fb->format->format ==
+   DRM_FORMAT_NV12) {
+   scaler_state->scalers[*scaler_id].mode =
+   PS_SCALER_MODE_NV12;
} else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) 
{
/*
 * when only 1 scaler is in use on either pipe A or B,
-- 
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[Intel-gfx] [PATCH 12/16] drm/i915: Upscale scaler max scale for NV12

[Vidya Srinivas]

From: Chandra Konduru 

This patch updates scaler max limit support for NV12

v2: Rebased (me)

v3: Rebased (me)

v4: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v5: Addressed review comments from Ville and rebased
- calculation of max_scale to be made
less convoluted by splitting it up a bit
- Indentation errors to be fixed in the series

v6: Rebased (me)
Fixed review comments from Paauwe, Bob J
Previous version, where a split of calculation
was done, was wrong. Fixed that issue here.

v7: Rebased (me)

v8: Rebased (me)

v9: Rebased (me)

v10: Rebased (me)

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_display.c | 33 +++--
 drivers/gpu/drm/i915/intel_drv.h |  3 ++-
 drivers/gpu/drm/i915/intel_sprite.c  |  3 ++-
 3 files changed, 27 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 5fc9255..74757d0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3435,6 +3435,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
case DRM_FORMAT_VYUY:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
+   case DRM_FORMAT_NV12:
+   return PLANE_CTL_FORMAT_NV12;
default:
MISSING_CASE(pixel_format);
}
@@ -4658,7 +4660,8 @@ static void cpt_verify_modeset(struct drm_device *dev, 
int pipe)
 static int
 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
  unsigned int scaler_user, int *scaler_id,
- int src_w, int src_h, int dst_w, int dst_h)
+ int src_w, int src_h, int dst_w, int dst_h,
+ uint32_t pixel_format)
 {
struct intel_crtc_scaler_state *scaler_state =
_state->scaler_state;
@@ -4674,7 +4677,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, 
bool force_detach,
 * the 90/270 degree plane rotation cases (to match the
 * GTT mapping), hence no need to account for rotation here.
 */
-   need_scaling = src_w != dst_w || src_h != dst_h;
+   need_scaling = src_w != dst_w || src_h != dst_h ||
+  (pixel_format == DRM_FORMAT_NV12);
 
if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
need_scaling = true;
@@ -4753,7 +4757,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state)
return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
>scaler_state.scaler_id,
state->pipe_src_w, state->pipe_src_h,
-   adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
+   adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay, 0);
 }
 
 /**
@@ -4783,7 +4787,8 @@ static int skl_update_scaler_plane(struct 
intel_crtc_state *crtc_state,
drm_rect_width(_state->base.src) >> 16,
drm_rect_height(_state->base.src) >> 16,
drm_rect_width(_state->base.dst),
-   drm_rect_height(_state->base.dst));
+   drm_rect_height(_state->base.dst),
+   fb ? fb->format->format : 0);
 
if (ret || plane_state->scaler_id < 0)
return ret;
@@ -4809,6 +4814,7 @@ static int skl_update_scaler_plane(struct 
intel_crtc_state *crtc_state,
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+   case DRM_FORMAT_NV12:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 
0x%x\n",
@@ -12758,11 +12764,12 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
 }
 
 int
-skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state 
*crtc_state)
+skl_max_scale(struct intel_crtc *intel_crtc,
+   struct intel_crtc_state *crtc_state, uint32_t pixel_format)
 {
struct drm_i915_private *dev_priv;
-   int max_scale;
-   int crtc_clock, max_dotclk;
+   int max_scale, mult;
+   int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
 
if (!intel_crtc || !crtc_state->base.enable)
return DRM_PLANE_HELPER_NO_SCALING;
@@ -12784,8 +12791,10 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct 
intel_crtc_state *crtc_state
 *or
 *cdclk/crtc_clock
 */
-   max_scale = min((1 << 16) * 3 - 1,
-   (1 << 8) * ((max_dotclk << 

[Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane

[Vidya Srinivas]

From: Chandra Konduru 

This patch adds NV12 to list of supported formats for
primary plane

v2: Rebased (Chandra Konduru)

v3: Rebased (me)

v4: Review comments by Ville addressed
Removed the skl_primary_formats_with_nv12 and
added NV12 case in existing skl_primary_formats

v5: Rebased (me)

v6: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v7: Review comments by Ville addressed
Restricting the NV12 for BXT and on PIPE A and B
Rebased (me)

v8: Rebased (me)
Modified restricting the NV12 support for both BXT and KBL.

v9: Rebased (me)

v10: Addressed review comments from Maarten.
Adding NV12 inside skl_primary_formats itself.

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_display.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 74757d0..24248c7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+   DRM_FORMAT_NV12,
 };
 
 static const uint64_t skl_format_modifiers_noccs[] = {
@@ -13233,6 +13234,9 @@ intel_primary_plane_create(struct drm_i915_private 
*dev_priv, enum pipe pipe)
intel_primary_formats = skl_primary_formats;
num_formats = ARRAY_SIZE(skl_primary_formats);
 
+   if (INTEL_GEN(dev_priv) == 9 && (pipe == PIPE_C))
+   num_formats -= 1;
+
if (skl_plane_has_ccs(dev_priv, pipe, PLANE_PRIMARY))
modifiers = skl_format_modifiers_ccs;
else
-- 
2.7.4

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[Intel-gfx] [PATCH 14/16] drm/i915: Add NV12 as supported format for sprite plane

[Vidya Srinivas]

From: Chandra Konduru 

This patch adds NV12 to list of supported formats for sprite plane.

v2: Rebased (me)

v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_formats
- Added the 10bpc RGB formats

v4: Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Removed 10bit RGB formats added previously with NV12 series

v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Previous version has 10bit RGB format removed from VLV formats
by mistake. Fixing that in this version.
Removed 10bit RGB formats added previously with NV12 series
for SKL.

v6: Addressed review comments by Ville
Restricting the NV12 to BXT and PIPE A and B

v7: Rebased (me)

v8: Rebased (me)
Restricting NV12 changes to BXT and KBL
Restricting NV12 changes for plane 0 (overlay)

v9: Rebased (me)

v10: Addressed review comments from Maarten.
Adding NV12 to skl_plane_formats itself.

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_sprite.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index f2e144b..f359b22 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1168,6 +1168,7 @@ static uint32_t skl_plane_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+   DRM_FORMAT_NV12,
 };
 
 static const uint64_t skl_plane_format_modifiers_noccs[] = {
@@ -1366,6 +1367,10 @@ intel_sprite_plane_create(struct drm_i915_private 
*dev_priv,
plane_formats = skl_plane_formats;
num_plane_formats = ARRAY_SIZE(skl_plane_formats);
 
+   if (INTEL_GEN(dev_priv) <= 10 && ((plane != 0) ||
+   (pipe == PIPE_C)))
+   num_plane_formats -= 1;
+
if (skl_plane_has_ccs(dev_priv, pipe, PLANE_SPRITE0 + plane))
modifiers = skl_plane_format_modifiers_ccs;
else
-- 
2.7.4

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[Intel-gfx] [PATCH 09/16] drm/i915/skl: split skl_compute_ddb function

[Vidya Srinivas]

From: Mahesh Kumar 

This patch splits skl_compute_wm/ddb functions into two parts.
One adds all affected pipes after the commit to atomic_state structure
and second part does compute the DDB.

Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/intel_pm.c | 157 ++--
 1 file changed, 88 insertions(+), 69 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c37d014..477eaea 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5058,69 +5058,16 @@ skl_ddb_add_affected_planes(struct intel_crtc_state 
*cstate)
 static int
 skl_compute_ddb(struct drm_atomic_state *state)
 {
-   struct drm_device *dev = state->dev;
-   struct drm_i915_private *dev_priv = to_i915(dev);
+   const struct drm_i915_private *dev_priv = to_i915(state->dev);
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-   struct intel_crtc *intel_crtc;
struct skl_ddb_allocation *ddb = _state->wm_results.ddb;
-   uint32_t realloc_pipes = pipes_modified(state);
-   int ret;
-
-   /*
-* If this is our first atomic update following hardware readout,
-* we can't trust the DDB that the BIOS programmed for us.  Let's
-* pretend that all pipes switched active status so that we'll
-* ensure a full DDB recompute.
-*/
-   if (dev_priv->wm.distrust_bios_wm) {
-   ret = drm_modeset_lock(>mode_config.connection_mutex,
-  state->acquire_ctx);
-   if (ret)
-   return ret;
-
-   intel_state->active_pipe_changes = ~0;
-
-   /*
-* We usually only initialize intel_state->active_crtcs if we
-* we're doing a modeset; make sure this field is always
-* initialized during the sanitization process that happens
-* on the first commit too.
-*/
-   if (!intel_state->modeset)
-   intel_state->active_crtcs = dev_priv->active_crtcs;
-   }
-
-   /*
-* If the modeset changes which CRTC's are active, we need to
-* recompute the DDB allocation for *all* active pipes, even
-* those that weren't otherwise being modified in any way by this
-* atomic commit.  Due to the shrinking of the per-pipe allocations
-* when new active CRTC's are added, it's possible for a pipe that
-* we were already using and aren't changing at all here to suddenly
-* become invalid if its DDB needs exceeds its new allocation.
-*
-* Note that if we wind up doing a full DDB recompute, we can't let
-* any other display updates race with this transaction, so we need
-* to grab the lock on *all* CRTC's.
-*/
-   if (intel_state->active_pipe_changes) {
-   realloc_pipes = ~0;
-   intel_state->wm_results.dirty_pipes = ~0;
-   }
+   struct intel_crtc *crtc;
+   struct intel_crtc_state *cstate;
+   int ret, i;
 
-   /*
-* We're not recomputing for the pipes not included in the commit, so
-* make sure we start with the current state.
-*/
memcpy(ddb, _priv->wm.skl_hw.ddb, sizeof(*ddb));
 
-   for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
-   struct intel_crtc_state *cstate;
-
-   cstate = intel_atomic_get_crtc_state(state, intel_crtc);
-   if (IS_ERR(cstate))
-   return PTR_ERR(cstate);
-
+   for_each_new_intel_crtc_in_state(intel_state, crtc, cstate, i) {
ret = skl_allocate_pipe_ddb(cstate, ddb);
if (ret)
return ret;
@@ -5182,23 +5129,23 @@ skl_print_wm_changes(const struct drm_atomic_state 
*state)
 }
 
 static int
-skl_compute_wm(struct drm_atomic_state *state)
+skl_ddb_add_affected_pipes(struct drm_atomic_state *state, bool *changed)
 {
-   struct drm_crtc *crtc;
-   struct drm_crtc_state *cstate;
-   struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-   struct skl_ddb_values *results = _state->wm_results;
struct drm_device *dev = state->dev;
-   struct skl_pipe_wm *pipe_wm;
-   bool changed = false;
+   const struct drm_i915_private *dev_priv = to_i915(dev);
+   const struct drm_crtc *crtc;
+   const struct drm_crtc_state *cstate;
+   struct intel_crtc *intel_crtc;
+   struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+   uint32_t realloc_pipes = pipes_modified(state);
int ret, i;
 
/*
 * When we distrust bios wm we always need to recompute to set the
 * expected DDB allocations for each CRTC.
 */
-   if (to_i915(dev)->wm.distrust_bios_wm)
-   changed = true;
+   if 

[Intel-gfx] [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM

[Vidya Srinivas]

From: Mahesh Kumar 

NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.

Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c  | 54 
 3 files changed, 45 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cca5414..778dc5a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1459,6 +1459,7 @@ struct skl_wm_level {
 struct skl_wm_params {
bool x_tiled, y_tiled;
bool rc_surface;
+   bool is_nv12;
uint32_t width;
uint8_t cpp;
uint32_t plane_pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ed33840..65dac21 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -594,6 +594,7 @@ struct intel_pipe_wm {
 
 struct skl_plane_wm {
struct skl_wm_level wm[8];
+   struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
bool is_nv12;
 };
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4c9a811..b3d1bf7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4421,7 +4421,7 @@ static int
 skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
struct intel_crtc_state *cstate,
const struct intel_plane_state *intel_pstate,
-   struct skl_wm_params *wp)
+   struct skl_wm_params *wp, int plane_num)
 {
struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
const struct drm_plane_state *pstate = _pstate->base;
@@ -4434,6 +4434,12 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
if (!intel_wm_plane_visible(cstate, intel_pstate))
return 0;
 
+   /* only NV12 format has two planes */
+   if (plane_num == 1 && fb->format->format != DRM_FORMAT_NV12) {
+   DRM_DEBUG_KMS("Non NV12 format have single plane\n");
+   return -EINVAL;
+   }
+
wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
  fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
  fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
@@ -4441,6 +4447,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private 
*dev_priv,
wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+   wp->is_nv12 = fb->format->format == DRM_FORMAT_NV12;
 
if (plane->id == PLANE_CURSOR) {
wp->width = intel_pstate->base.crtc_w;
@@ -4453,7 +4460,10 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
wp->width = drm_rect_width(_pstate->base.src) >> 16;
}
 
-   wp->cpp = fb->format->cpp[0];
+   if (plane_num == 1 && wp->is_nv12)
+   wp->width /= 2;
+
+   wp->cpp = fb->format->cpp[plane_num];
wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
 intel_pstate);
 
@@ -4649,7 +4659,8 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
  struct intel_crtc_state *cstate,
  const struct intel_plane_state *intel_pstate,
  const struct skl_wm_params *wm_params,
- struct skl_plane_wm *wm)
+ struct skl_plane_wm *wm,
+ int plane_num)
 {
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_plane *plane = intel_pstate->base.plane;
@@ -4657,15 +4668,20 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
uint16_t ddb_blocks;
enum pipe pipe = intel_crtc->pipe;
int level, max_level = ilk_wm_max_level(dev_priv);
+   enum plane_id plane_id = intel_plane->id;
int ret;
 
if (WARN_ON(!intel_pstate->base.fb))
return -EINVAL;
 
-   ddb_blocks = skl_ddb_entry_size(>plane[pipe][intel_plane->id]);
+   if (plane_num == 0)
+   ddb_blocks = skl_ddb_entry_size(>plane[pipe][plane_id]);
+   else
+   ddb_blocks = skl_ddb_entry_size(>uv_plane[pipe][plane_id]);
 
for (level = 0; level <= max_level; level++) {
-   struct skl_wm_level *result = >wm[level];
+   struct skl_wm_level *result = plane_num ? >uv_wm[level] :
+ >wm[level];
 
ret = skl_compute_plane_wm(dev_priv,
  

[Intel-gfx] [PATCH 00/16] Adding NV12 support

[Vidya Srinivas]

This patch series is adding NV12 support for Broxton display after rebasing on
latest drm-tip.
Initial series of the patches can be found here:
https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html

Previous revision history:
The first version of patches were reviewed when floated by Chandra in 2015
but currently there was a design change with respect to
- the way fb offset is handled
- the way rotation is handled
Current NV12 patch series has been ported as per the
current changes on drm-tip

Review comments from Ville (12th June 2017) have been addressed Review
comments from Clinton A Taylor (7th July 2017) have been addressed

Review comments from Clinton A Taylor (10th July 2017)
have been addressed. Had missed out tested-by/reviewed-by in the 
patches.

Fixed that error in this series.
Review comments from Ville (11th July 2017) addressed.
Review comments from Paauwe, Bob (29th July 2017) addressed.

Update from rev 28 Aug 2017
Rebased the series.
Tested with IGT for rotation, sprite and tiling combinations.
IGT Links:
https://patchwork.kernel.org/patch/9995943/
https://patchwork.kernel.org/patch/9995945/

Update from last rev:
Rebased the series.
Review comments by Maarten are addressed in this series.
NV12 enabled for Gen10.

Chandra Konduru (6):
  drm/i915: Set scaler mode for NV12
  drm/i915: Update format_is_yuv() to include NV12
  drm/i915: Upscale scaler max scale for NV12
  drm/i915: Add NV12 as supported format for primary plane
  drm/i915: Add NV12 as supported format for sprite plane
  drm/i915: Add NV12 support to intel_framebuffer_init

Mahesh Kumar (9):
  drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
  drm/i915/skl+: refactor WM calculation for NV12
  drm/i915/skl+: add NV12 in skl_format_to_fourcc
  drm/i915/skl+: support verification of DDB HW state for NV12
  drm/i915/skl+: NV12 related changes for WM
  drm/i915/skl+: pass skl_wm_level struct to wm compute func
  drm/i915/skl+: make sure higher latency level has higher wm value
  drm/i915/skl+: nv12 workaround disable WM level 1-7
  drm/i915/skl: split skl_compute_ddb function

Vidya Srinivas (1):
  drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

 drivers/gpu/drm/i915/i915_drv.h  |   9 +-
 drivers/gpu/drm/i915/i915_reg.h  |   7 +
 drivers/gpu/drm/i915/intel_atomic.c  |   8 +-
 drivers/gpu/drm/i915/intel_display.c |  51 +++-
 drivers/gpu/drm/i915/intel_drv.h |   9 +-
 drivers/gpu/drm/i915/intel_pm.c  | 435 ++-
 drivers/gpu/drm/i915/intel_sprite.c  |  16 +-
 7 files changed, 349 insertions(+), 186 deletions(-)

-- 
2.7.4

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[Intel-gfx] [PATCH 08/16] drm/i915/skl+: nv12 workaround disable WM level 1-7

[Vidya Srinivas]

From: Mahesh Kumar 

Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A)
Hardware sometimes fails to wake memory from pkg C states fetching the
last few lines of planar YUV 420 (NV12) planes. This causes
intermittent underflow and corruption.
WA: Disable package C states or do not enable latency levels 1 through 7
(WM1 - WM7) on NV12 planes.

v2: Addressed review comments by Maarten.

Reviewed-by: Maarten Lankhorst 
Signed-off-by: Mahesh Kumar 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_pm.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d9801bf..c37d014 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4654,6 +4654,17 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
}
}
 
+   /*
+* Display WA #826 (SKL:ALL, BXT:ALL) & #1059 (CNL:A)
+* disable wm level 1-7 on NV12 planes
+*/
+   if (wp->is_nv12 && (level >= 1) &&
+   (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
+IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {
+   result->plane_en = false;
+   return 0;
+   }
+
result->plane_res_b = res_blocks;
result->plane_res_l = res_lines;
result->plane_en = true;
-- 
2.7.4

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[Intel-gfx] [PATCH 01/16] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

[Vidya Srinivas]

From: Mahesh Kumar 

skl_wm_values struct contains values of pipe/plane DDB only.
so rename it for better readability of code. Similarly
skl_copy_wm_for_pipe copies DDB values.

s/skl_wm_values/skl_ddb_values
s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe

Changes since V1:
 - also change name of skl_copy_wm_for_pipe

Reviewed-by: Maarten Lankhorst 
Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/i915_drv.h  |  4 ++--
 drivers/gpu/drm/i915/intel_drv.h |  2 +-
 drivers/gpu/drm/i915/intel_pm.c  | 14 +++---
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d6b5ac2..d73e0a2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1444,7 +1444,7 @@ struct skl_ddb_allocation {
struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
 };
 
-struct skl_wm_values {
+struct skl_ddb_values {
unsigned dirty_pipes;
struct skl_ddb_allocation ddb;
 };
@@ -2139,7 +2139,7 @@ struct drm_i915_private {
/* current hardware state */
union {
struct ilk_wm_values hw;
-   struct skl_wm_values skl_hw;
+   struct skl_ddb_values skl_hw;
struct vlv_wm_values vlv;
struct g4x_wm_values g4x;
};
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 468ec1e..61d9946 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -480,7 +480,7 @@ struct intel_atomic_state {
bool skip_intermediate_wm;
 
/* Gen9+ only */
-   struct skl_wm_values wm_results;
+   struct skl_ddb_values wm_results;
 
struct i915_sw_fence commit_ready;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index eb68abf..0cd5e95 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5042,8 +5042,8 @@ skl_compute_ddb(struct drm_atomic_state *state)
 }
 
 static void
-skl_copy_wm_for_pipe(struct skl_wm_values *dst,
-struct skl_wm_values *src,
+skl_copy_ddb_for_pipe(struct skl_ddb_values *dst,
+struct skl_ddb_values *src,
 enum pipe pipe)
 {
memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
@@ -5095,7 +5095,7 @@ skl_compute_wm(struct drm_atomic_state *state)
struct drm_crtc *crtc;
struct drm_crtc_state *cstate;
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-   struct skl_wm_values *results = _state->wm_results;
+   struct skl_ddb_values *results = _state->wm_results;
struct drm_device *dev = state->dev;
struct skl_pipe_wm *pipe_wm;
bool changed = false;
@@ -5197,8 +5197,8 @@ static void skl_initial_wm(struct intel_atomic_state 
*state,
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_device *dev = intel_crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
-   struct skl_wm_values *results = >wm_results;
-   struct skl_wm_values *hw_vals = _priv->wm.skl_hw;
+   struct skl_ddb_values *results = >wm_results;
+   struct skl_ddb_values *hw_vals = _priv->wm.skl_hw;
enum pipe pipe = intel_crtc->pipe;
 
if ((results->dirty_pipes & drm_crtc_mask(_crtc->base)) == 0)
@@ -5209,7 +5209,7 @@ static void skl_initial_wm(struct intel_atomic_state 
*state,
if (cstate->base.active_changed)
skl_atomic_update_crtc_wm(state, cstate);
 
-   skl_copy_wm_for_pipe(hw_vals, results, pipe);
+   skl_copy_ddb_for_pipe(hw_vals, results, pipe);
 
mutex_unlock(_priv->wm.wm_mutex);
 }
@@ -5341,7 +5341,7 @@ void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
 void skl_wm_get_hw_state(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = to_i915(dev);
-   struct skl_wm_values *hw = _priv->wm.skl_hw;
+   struct skl_ddb_values *hw = _priv->wm.skl_hw;
struct skl_ddb_allocation *ddb = _priv->wm.skl_hw.ddb;
struct drm_crtc *crtc;
struct intel_crtc *intel_crtc;
-- 
2.7.4

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[Intel-gfx] [PATCH 07/16] drm/i915/skl+: make sure higher latency level has higher wm value

[Vidya Srinivas]

From: Mahesh Kumar 

DDB allocation optimization algorithm requires/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below.
Render decompression requires level WM to be as high as wm level-0.
This patch fulfils both the requirements.

Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/intel_pm.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 07fc084..d9801bf 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4531,6 +4531,7 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
uint16_t ddb_allocation,
int level,
const struct skl_wm_params *wp,
+   const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */)
 {
const struct drm_plane_state *pstate = _pstate->base;
@@ -4598,6 +4599,15 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
} else {
res_blocks++;
}
+
+   /*
+* Make sure result blocks for higher latency levels are atleast
+* as high as level below.
+* Assumption in DDB algorithm optimization for special cases.
+* Also covers Display WA #1125 for RC.
+*/
+   if (result_prev->plane_res_b > res_blocks)
+   res_blocks = result_prev->plane_res_b;
}
 
if (INTEL_GEN(dev_priv) >= 11) {
@@ -4680,6 +4690,13 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = plane_num ? >uv_wm[level] :
  >wm[level];
+   struct skl_wm_level *result_prev;
+
+   if (level)
+   result_prev = plane_num ? >uv_wm[level - 1] :
+ >wm[level - 1];
+   else
+   result_prev = plane_num ? >uv_wm[0] : >wm[0];
 
ret = skl_compute_plane_wm(dev_priv,
   cstate,
@@ -4687,6 +4704,7 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
   ddb_blocks,
   level,
   wm_params,
+  result_prev,
   result);
if (ret)
return ret;
-- 
2.7.4

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[Intel-gfx] [PATCH] drm/i915/skl+: refactor WM calculation for NV12

[Vidya Srinivas]

From: Mahesh Kumar 

Current code calculates DDB for planar formats in such a way that we
store DDB of plane-0 in plane 1 & vice-versa.
In order to make this clean this patch refactors WM/DDB calculation for
NV12 planar formats.

v2: Addressed review comments by Maarten

v3: Rebased and addressed review comments by Maarten

Reviewed-by: Maarten Lankhorst 
Signed-off-by: Mahesh Kumar 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/i915_drv.h  |   5 +-
 drivers/gpu/drm/i915/intel_drv.h |   1 +
 drivers/gpu/drm/i915/intel_pm.c  | 121 ---
 3 files changed, 66 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d73e0a2..35d1663 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1440,8 +1440,9 @@ static inline bool skl_ddb_entry_equal(const struct 
skl_ddb_entry *e1,
 }
 
 struct skl_ddb_allocation {
-   struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* 
packed/uv */
-   struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
+   /* packed/y */
+   struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
+   struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
 };
 
 struct skl_ddb_values {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 61d9946..35ee715 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -595,6 +595,7 @@ struct intel_pipe_wm {
 struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level trans_wm;
+   bool is_nv12;
 };
 
 struct skl_pipe_wm {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0cd5e95..1546bc8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4012,9 +4012,9 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc 
*intel_crtc,
 static unsigned int
 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
 const struct drm_plane_state *pstate,
-int y)
+const int plane)
 {
-   struct intel_plane *plane = to_intel_plane(pstate->plane);
+   struct intel_plane *intel_plane = to_intel_plane(pstate->plane);
struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
uint32_t data_rate;
uint32_t width = 0, height = 0;
@@ -4028,9 +4028,9 @@ skl_plane_relative_data_rate(const struct 
intel_crtc_state *cstate,
fb = pstate->fb;
format = fb->format->format;
 
-   if (plane->id == PLANE_CURSOR)
+   if (intel_plane->id == PLANE_CURSOR)
return 0;
-   if (y && format != DRM_FORMAT_NV12)
+   if (plane == 1 && format != DRM_FORMAT_NV12)
return 0;
 
/*
@@ -4041,19 +4041,14 @@ skl_plane_relative_data_rate(const struct 
intel_crtc_state *cstate,
width = drm_rect_width(_pstate->base.src) >> 16;
height = drm_rect_height(_pstate->base.src) >> 16;
 
-   /* for planar format */
-   if (format == DRM_FORMAT_NV12) {
-   if (y)  /* y-plane data rate */
-   data_rate = width * height *
-   fb->format->cpp[0];
-   else/* uv-plane data rate */
-   data_rate = (width / 2) * (height / 2) *
-   fb->format->cpp[1];
-   } else {
-   /* for packed formats */
-   data_rate = width * height * fb->format->cpp[0];
+   /* UV plane does 1/2 pixel sub-sampling */
+   if (plane == 1 && format == DRM_FORMAT_NV12) {
+   width /= 2;
+   height /= 2;
}
 
+   data_rate = width * height * fb->format->cpp[plane];
+
down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
 
return mul_round_up_u32_fixed16(data_rate, down_scale_amount);
@@ -4066,8 +4061,8 @@ skl_plane_relative_data_rate(const struct 
intel_crtc_state *cstate,
  */
 static unsigned int
 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
-unsigned *plane_data_rate,
-unsigned *plane_y_data_rate)
+unsigned int *plane_data_rate,
+unsigned int *uv_plane_data_rate)
 {
struct drm_crtc_state *cstate = _cstate->base;
struct drm_atomic_state *state = cstate->state;
@@ -4083,17 +4078,17 @@ skl_get_total_relative_data_rate(struct 
intel_crtc_state *intel_cstate,
enum plane_id plane_id = to_intel_plane(plane)->id;
unsigned int rate;
 
-   /* packed/uv */
+   /* packed/y */
rate = 

[Intel-gfx] [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12

[Vidya Srinivas]

From: Mahesh Kumar 

NV12 formats have two registers for DDB. Verify both the registers for
NV12 during verify_wm_state.

v2: Addressed review comments by Maarten.

Signed-off-by: Mahesh Kumar 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_display.c |  2 +-
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c  | 50 
 3 files changed, 42 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index e3a6a7f..5fc9255 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2621,7 +2621,7 @@ static int i9xx_format_to_fourcc(int format)
}
 }
 
-static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
+int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
 {
switch (format) {
case PLANE_CTL_FORMAT_RGB_565:
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 35ee715..ed33840 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1595,6 +1595,7 @@ u32 skl_plane_stride(const struct drm_framebuffer *fb, 
int plane,
 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state);
 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
+int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
 
 /* intel_csr.c */
 void intel_csr_ucode_init(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5bff004..4c9a811 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3828,6 +3828,43 @@ static void skl_ddb_entry_init_from_hw(struct 
skl_ddb_entry *entry, u32 reg)
entry->end += 1;
 }
 
+static void
+skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
+  const enum pipe pipe,
+  const enum plane_id plane_id,
+  struct skl_ddb_allocation *ddb /* out */)
+{
+   u32 val, val2 = 0;
+   int fourcc, pixel_format;
+
+   /* Cursor doesn't support NV12, so no extra calculation needed */
+   if (plane_id == PLANE_CURSOR) {
+   val = I915_READ(CUR_BUF_CFG(pipe));
+   skl_ddb_entry_init_from_hw(>plane[pipe][plane_id], val);
+   return;
+   }
+
+   val = I915_READ(PLANE_CTL(pipe, plane_id));
+
+   /* No DDB allocated for disabled planes */
+   if (!(val & PLANE_CTL_ENABLE))
+   return;
+
+   pixel_format = val & PLANE_CTL_FORMAT_MASK;
+   fourcc = skl_format_to_fourcc(pixel_format,
+ val & PLANE_CTL_ORDER_RGBX,
+ val & PLANE_CTL_ALPHA_MASK);
+
+   val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
+   val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
+
+   if (fourcc == DRM_FORMAT_NV12) {
+   skl_ddb_entry_init_from_hw(>plane[pipe][plane_id], val2);
+   skl_ddb_entry_init_from_hw(>uv_plane[pipe][plane_id], val);
+   } else
+   skl_ddb_entry_init_from_hw(>plane[pipe][plane_id], val);
+}
+
 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
  struct skl_ddb_allocation *ddb /* out */)
 {
@@ -3844,16 +3881,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private 
*dev_priv,
if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
continue;
 
-   for_each_plane_id_on_crtc(crtc, plane_id) {
-   u32 val;
-
-   if (plane_id != PLANE_CURSOR)
-   val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
-   else
-   val = I915_READ(CUR_BUF_CFG(pipe));
-
-   skl_ddb_entry_init_from_hw(>plane[pipe][plane_id], 
val);
-   }
+   for_each_plane_id_on_crtc(crtc, plane_id)
+   skl_ddb_get_hw_plane_state(dev_priv, pipe,
+  plane_id, ddb);
 
intel_display_power_put(dev_priv, power_domain);
}
-- 
2.7.4

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[Intel-gfx] [PATCH 06/16] drm/i915/skl+: pass skl_wm_level struct to wm compute func

[Vidya Srinivas]

From: Mahesh Kumar 

This will reduce number of arguments required to be passed in
skl_compute_plane_wm function.

Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/intel_pm.c | 18 +++---
 1 file changed, 7 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b3d1bf7..07fc084 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4531,9 +4531,7 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
uint16_t ddb_allocation,
int level,
const struct skl_wm_params *wp,
-   uint16_t *out_blocks, /* out */
-   uint8_t *out_lines, /* out */
-   bool *enabled /* out */)
+   struct skl_wm_level *result /* out */)
 {
const struct drm_plane_state *pstate = _pstate->base;
uint32_t latency = dev_priv->wm.skl_latency[level];
@@ -4547,7 +4545,7 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
 
if (latency == 0 ||
!intel_wm_plane_visible(cstate, intel_pstate)) {
-   *enabled = false;
+   result->plane_en = false;
return 0;
}
 
@@ -4627,7 +4625,7 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
 
if (res_blocks >= ddb_allocation || res_lines > 31 ||
min_disp_buf_needed >= ddb_allocation) {
-   *enabled = false;
+   result->plane_en = false;
 
/*
 * If there are no valid level 0 watermarks, then we can't
@@ -4646,9 +4644,9 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
}
}
 
-   *out_blocks = res_blocks;
-   *out_lines = res_lines;
-   *enabled = true;
+   result->plane_res_b = res_blocks;
+   result->plane_res_l = res_lines;
+   result->plane_en = true;
 
return 0;
 }
@@ -4689,9 +4687,7 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
   ddb_blocks,
   level,
   wm_params,
-  >plane_res_b,
-  >plane_res_l,
-  >plane_en);
+  result);
if (ret)
return ret;
}
-- 
2.7.4

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[Intel-gfx] [PATCH 03/16] drm/i915/skl+: add NV12 in skl_format_to_fourcc

[Vidya Srinivas]

From: Mahesh Kumar 

Add support of recognizing DRM_FORMAT_NV12 from plane_format
register value.

Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/intel_display.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 60ba5bb..e3a6a7f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2626,6 +2626,8 @@ static int skl_format_to_fourcc(int format, bool 
rgb_order, bool alpha)
switch (format) {
case PLANE_CTL_FORMAT_RGB_565:
return DRM_FORMAT_RGB565;
+   case PLANE_CTL_FORMAT_NV12:
+   return DRM_FORMAT_NV12;
default:
case PLANE_CTL_FORMAT_XRGB_:
if (rgb_order) {
-- 
2.7.4

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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/breadcrumbs: Ignore unsubmitted signalers

[Patchwork]

== Series Details ==

Series: drm/i915/breadcrumbs: Ignore unsubmitted signalers
URL   : https://patchwork.freedesktop.org/series/37724/
State : warning

== Summary ==

Test gem_eio:
Subgroup in-flight:
dmesg-warn -> PASS   (shard-snb) fdo#104058
Test kms_flip:
Subgroup modeset-vs-vblank-race:
fail   -> PASS   (shard-apl) fdo#103060
Subgroup flip-vs-expired-vblank:
pass   -> FAIL   (shard-apl) fdo#102887
Subgroup 2x-flip-vs-wf_vblank:
fail   -> PASS   (shard-hsw) fdo#100368
Test kms_vblank:
Subgroup pipe-b-ts-continuation-dpms-suspend:
pass   -> SKIP   (shard-hsw)
Test kms_cursor_crc:
Subgroup cursor-128x128-suspend:
pass   -> SKIP   (shard-snb) fdo#103880
Test kms_sysfs_edid_timing:
pass   -> WARN   (shard-apl) fdo#100047
Test kms_frontbuffer_tracking:
Subgroup fbc-2p-scndscrn-cur-indfb-move:
skip   -> PASS   (shard-hsw)
Test kms_atomic_interruptible:
Subgroup legacy-setmode:
pass   -> SKIP   (shard-snb)

fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103880 https://bugs.freedesktop.org/show_bug.cgi?id=103880
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047

shard-apltotal:3379 pass:1744 dwarn:1   dfail:0   fail:22  skip:1610 
time:12444s
shard-hswtotal:3442 pass:1757 dwarn:1   dfail:0   fail:11  skip:1672 
time:11707s
shard-snbtotal:3442 pass:1349 dwarn:1   dfail:0   fail:10  skip:2082 
time:6608s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7900/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/audio: do not set Maud/Naud values manually on KBL

[Patchwork]

== Series Details ==

Series: drm/i915/audio: do not set Maud/Naud values manually on KBL
URL   : https://patchwork.freedesktop.org/series/37730/
State : success

== Summary ==

Series 37730v1 drm/i915/audio: do not set Maud/Naud values manually on KBL
https://patchwork.freedesktop.org/api/1.0/series/37730/revisions/1/mbox/

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:417s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:425s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:373s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:484s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:483s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:484s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:467s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:455s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:575s
fi-cnl-y3total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:576s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:413s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:282s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:510s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:392s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:398s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:417s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:462s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:414s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:461s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:498s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:455s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:501s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:595s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:427s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:511s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:523s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:493s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:487s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:414s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:430s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:530s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:393s
Blacklisted hosts:
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:470s

078873da383505cf8d6940229007115b31f1d5e0 drm-tip: 2018y-02m-06d-11h-21m-36s UTC 
integration manifest
f1edb5c775e2 drm/i915/audio: do not set Maud/Naud values manually on KBL

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7904/issues.html
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Re: [Intel-gfx] [PATCH] drm/i915: Display WA #0827 for NV12 to RGB switch

[David Weinehall]

On Tue, Feb 06, 2018 at 04:36:42PM +0530, Vidya Srinivas wrote:
> From: Chandra Konduru 
> 
> Display WA #0827:
> Switching the plane format from NV12 to RGB and leaving system idle results
> in display underrun and corruption. WA: Set the bit 15 & bit 19 to 1b
> in the CLKGATE_DIS_PSL register for the pipe in which NV12 plane is enabled.
> 
> Signed-off-by: Chandra Konduru 
> Signed-off-by: Vidya Srinivas 
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  3 +++
>  drivers/gpu/drm/i915/intel_display.c | 16 
>  2 files changed, 19 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8f36023..c4af05e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3822,6 +3822,9 @@ enum {
>  #define _CLKGATE_DIS_PSL_A   0x46520
>  #define _CLKGATE_DIS_PSL_B   0x46524
>  #define _CLKGATE_DIS_PSL_C   0x46528
> +#define DUPS1_GATING_DIS (1 << 15)
> +#define DUPS2_GATING_DIS (1 << 19)
> +#define DUPS3_GATING_DIS (1 << 23)
>  #define   DPF_GATING_DIS (1 << 10)
>  #define   DPF_RAM_GATING_DIS (1 << 9)
>  #define   DPFR_GATING_DIS(1 << 8)
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 551c970..94faf3e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5495,6 +5495,20 @@ static void glk_pipe_scaler_clock_gating_wa(struct 
> drm_i915_private *dev_priv,
>   I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
>  }
>  
> +static void skl_wa_clkgate(struct drm_i915_private *dev_priv,
> + int pipe, int enable)
> +{
> + if (pipe == PIPE_A || pipe == PIPE_B) {
> + if (enable)
> + I915_WRITE(CLKGATE_DIS_PSL(pipe),
> + DUPS1_GATING_DIS | DUPS2_GATING_DIS);
> + else
> + I915_WRITE(CLKGATE_DIS_PSL(pipe),
> + I915_READ(CLKGATE_DIS_PSL(pipe)) &
> + ~(DUPS1_GATING_DIS|DUPS2_GATING_DIS));
> + }
> +}
> +
>  static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>   struct drm_atomic_state *old_state)
>  {
> @@ -5599,6 +5613,7 @@ static void haswell_crtc_enable(struct intel_crtc_state 
> *pipe_config,
>   intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
>   intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
>   }
> + skl_wa_clkgate(dev_priv, pipe, 1);
>  }
>  
>  static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
> @@ -5709,6 +5724,7 @@ static void haswell_crtc_disable(struct 
> intel_crtc_state *old_crtc_state,
>   intel_ddi_disable_pipe_clock(intel_crtc->config);
>  
>   intel_encoders_post_disable(crtc, old_crtc_state, old_state);
> + skl_wa_clkgate(dev_priv, intel_crtc->pipe, 0);
>  }

Unless I'm misreading the context of this patch you're applying a workaround,
that by name seems to be for Skylake only, to: Haswell, Broadwell, and gen9+.

Either the name is incorrect, or the application of it.

As per BSpec the workaround seems to be for all of gen9 and only A-stepping of 
gen10.
I don't see it listed for Haswell or Broadwell.

Cross-referencing the WA-database with Bspec, based on the HSD
link, it seems that this issue *might* be
WaDups1GatingDisableClockGatingForMPO; if this is the case it might
make sense to include that WA name too. At the very least
there should always be a comment mentioning the workaround name/number
and the platform(s) it applies to.

Also, according to the WA database, if the above mentioned issue really
is the same, the WA is *NOT* necessary on GLK (seeing as GLK uses gen10
display this might make sense, though the WA database sometimes contains
mistakes).


Regards, David

>  static void i9xx_pfit_enable(struct intel_crtc *crtc)
> -- 
> 1.9.1
> 
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[Intel-gfx] [PATCH] drm/i915/audio: do not set Maud/Naud values manually on KBL

[Jani Nikula]

Apparently using the manual Maud/Naud mode does not work on KBL. The
details on the failure mode are scarce, except that there's no audio,
and there is obviously no idea on the root cause either. It is also
unknown whether the failure can be reproduced on newer platforms in some
scenarios.

The problem was introduced when switching from automatic mode to manual
mode in commit 6014ac122ed0 ("drm/i915/audio: set proper N/M in
modeset"). Instead of reverting that, disable the feature on KBL as a
workaround.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104093
Reported-by: Quanxian Wang 
Fixes: 6014ac122ed0 ("drm/i915/audio: set proper N/M in modeset")
Cc:  # v4.10+
Cc: Keqiao Zhang 
Cc: Ville Syrjälä 
Cc: Mengdong Lin 
Cc: Libin Yang 
Cc: Rodrigo Vivi 
Cc: Quanxian Wang 
Cc: Wang Zhijun 
Cc: Cui Yueping 
Cc: Alice Liu 
Cc: intel-gfx@lists.freedesktop.org
Signed-off-by: Jani Nikula 

---

UNTESTED. Please provide Tested-by's on the affected KBLs, but *also* on
CFL, CNL, etc.
---
 drivers/gpu/drm/i915/intel_audio.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index 522d54fecb53..b7634cff12b6 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -294,12 +294,19 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
enum port port = encoder->port;
enum pipe pipe = crtc->pipe;
-   const struct dp_aud_n_m *nm;
+   const struct dp_aud_n_m *nm = NULL;
int rate;
u32 tmp;
 
rate = acomp ? acomp->aud_sample_rate[port] : 0;
-   nm = audio_config_dp_get_n_m(crtc_state, rate);
+
+   /*
+* FIXME: For reasons still unknown, there seem to be issues with the
+* manual Maud/Naud mode on KBL.
+*/
+   if (!IS_KABYLAKE(dev_priv))
+   nm = audio_config_dp_get_n_m(crtc_state, rate);
+
if (nm)
DRM_DEBUG_KMS("using Maud %u, Naud %u\n", nm->m, nm->n);
else
-- 
2.11.0

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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Display WA #0827 for NV12 to RGB switch (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Display WA #0827 for NV12 to RGB switch (rev4)
URL   : https://patchwork.freedesktop.org/series/37729/
State : failure

== Summary ==

Applying: YUV444 10/12/16 bit declarations and additions
error: Failed to merge in the changes.
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/drm_fourcc.c
M   drivers/gpu/drm/i915/i915_reg.h
M   drivers/gpu/drm/i915/intel_display.c
M   drivers/gpu/drm/i915/intel_sprite.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_sprite.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_sprite.c
Auto-merging drivers/gpu/drm/i915/intel_display.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_display.c
Auto-merging drivers/gpu/drm/i915/i915_reg.h
Auto-merging drivers/gpu/drm/drm_fourcc.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/drm_fourcc.c
Patch failed at 0001 YUV444 10/12/16 bit declarations and additions
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Fix PMU enable vs execlists tasklet race (rev4)

[Tvrtko Ursulin]

On 06/02/2018 09:51, Patchwork wrote:

== Series Details ==

Series: drm/i915/pmu: Fix PMU enable vs execlists tasklet race (rev4)
URL   : https://patchwork.freedesktop.org/series/37575/
State : success

== Summary ==

Series 37575v4 drm/i915/pmu: Fix PMU enable vs execlists tasklet race
https://patchwork.freedesktop.org/api/1.0/series/37575/revisions/4/mbox/

Test kms_pipe_crc_basic:
 Subgroup suspend-read-crc-pipe-b:
 pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:419s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:428s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:374s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:482s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:482s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:484s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:468s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:465s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:564s
fi-cnl-y3total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:595s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:416s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:278s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:508s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:390s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:396s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:411s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:454s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:415s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:458s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:495s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:455s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:504s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:591s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:433s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:509s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:529s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:490s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:494s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:414s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:428s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:396s
Blacklisted hosts:
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:472s
fi-bwr-2160 failed to collect. IGT log at Patchwork_7899/fi-bwr-2160/igt.log

5883e1383ed69b4bd7a537ceafeeabbc61cdf55e drm-tip: 2018y-02m-06d-09h-04m-49s UTC 
integration manifest
842452bceaec drm/i915/pmu: Fix PMU enable vs execlists tasklet race


Pushed, finally, after shards reported A-OK. Onto the next one..

Regards,

Tvrtko
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/pmu: Fix PMU enable vs execlists tasklet race (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/pmu: Fix PMU enable vs execlists tasklet race (rev4)
URL   : https://patchwork.freedesktop.org/series/37575/
State : success

== Summary ==

Test kms_frontbuffer_tracking:
Subgroup fbc-2p-scndscrn-cur-indfb-move:
skip   -> PASS   (shard-hsw)
Test gem_eio:
Subgroup in-flight:
dmesg-warn -> PASS   (shard-snb) fdo#104058
Test kms_flip:
Subgroup 2x-flip-vs-wf_vblank:
fail   -> PASS   (shard-hsw) fdo#100368
Subgroup modeset-vs-vblank-race:
fail   -> PASS   (shard-apl) fdo#103060
Test kms_sysfs_edid_timing:
pass   -> WARN   (shard-apl) fdo#100047
Test kms_cursor_crc:
Subgroup cursor-128x128-suspend:
pass   -> SKIP   (shard-snb) fdo#103880

fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#103880 https://bugs.freedesktop.org/show_bug.cgi?id=103880

shard-apltotal:3379 pass:1745 dwarn:1   dfail:0   fail:21  skip:1610 
time:12314s
shard-hswtotal:3442 pass:1758 dwarn:1   dfail:0   fail:11  skip:1671 
time:11777s
shard-snbtotal:3442 pass:1350 dwarn:1   dfail:0   fail:10  skip:2081 
time:6620s
Blacklisted hosts:
shard-kbltotal:3442 pass:1909 dwarn:1   dfail:0   fail:22  skip:1510 
time:9654s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7899/shards.html
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