[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Track GT interrupt handling using the master iir

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Track GT interrupt handling using 
the master iir
URL   : https://patchwork.freedesktop.org/series/38314/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
a62345821ea6 drm/i915: Track GT interrupt handling using the master iir
f67401a8f891 drm/i915: Prune gen8_gt_irq_handler
-:46: WARNING: line over 80 characters
#46: FILE: drivers/gpu/drm/i915/i915_irq.c:1432:
+   writel(gt_iir[0], regs + 
i915_mmio_reg_offset(GEN8_GT_IIR(0)));

-:55: WARNING: line over 80 characters
#55: FILE: drivers/gpu/drm/i915/i915_irq.c:1438:
+   writel(gt_iir[1], regs + 
i915_mmio_reg_offset(GEN8_GT_IIR(1)));

-:64: WARNING: line over 80 characters
#64: FILE: drivers/gpu/drm/i915/i915_irq.c:1443:
+   if (likely(gt_iir[2] & (i915->pm_rps_events | 
i915->pm_guc_events)))

-:81: WARNING: line over 80 characters
#81: FILE: drivers/gpu/drm/i915/i915_irq.c:1452:
+   writel(gt_iir[3], regs + 
i915_mmio_reg_offset(GEN8_GT_IIR(3)));

total: 0 errors, 4 warnings, 0 checks, 98 lines checked

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Re: [Intel-gfx] [PATCH 3/4] drm/i915: Store platform_mask inside the static device info

[Chris Wilson]

Quoting Rodrigo Vivi (2018-02-14 22:45:33)
> Chris Wilson  writes:
> 
> > Rather than deriving the platform_mask from the
> > intel_device_static_info->platform at runtime, prefill it in the static
> > data.
> >
> >  baseline.ko drivers/gpu/drm/i915/i915.ko
> > add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-20 (-20)
> > Function old new   delta
> > i915_driver_load50275007 -20
> > Total: Before=1331200, After=1331180, chg -0.00%
> >
> > Signed-off-by: Chris Wilson 
> > ---
> >  static const struct intel_device_info intel_cherryview_info = {
> > + PLATFORM(INTEL_CHERRYVIEW),
> >   GEN(8),
> 
> The order seems a bit strange... here it comes before the GEN
> and in other cases it comes after the GEN_FEATURES which includes GEN...
> 
> probably we could make PLATFORM the very first thing on any case
> but up to you...

I was trying to have PLATFORM be the first non-inherited value in each
device_info. So the pattern I had in mind was 
[GENx_FEATURES,]
PLATFORM(foo)
I was tempted to add feature defines for the atoms as well just so it
looked more consistent. Later on it was looking more like
static const PLATFORM_INFO(cherryview) = {
PLATFORM(INTEL_CHERRYVIEW),
...
};
where the repetition is more obvious (and easier to check)
-Chris
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Re: [Intel-gfx] please do *NOT* backport 9965db26ac05 ("drm/i915: Check for fused or unused pipes")

[Greg KH]

On Wed, Feb 14, 2018 at 06:22:56PM +0200, Jani Nikula wrote:
> 
> Stable team,
> 
> commit 9965db26ac05 ("drm/i915: Check for fused or unused pipes")
> 
> with Cc: stable is broken, please do not backport.

Ok, now dropped from my "to-apply" queue, thanks.

greg k-h
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[Intel-gfx] ✓ Fi.CI.BAT: success for Adding NV12 support (rev11)

[Patchwork]

== Series Details ==

Series: Adding NV12 support (rev11)
URL   : https://patchwork.freedesktop.org/series/28103/
State : success

== Summary ==

Series 28103v11 Adding NV12 support
https://patchwork.freedesktop.org/api/1.0/series/28103/revisions/11/mbox/

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:421s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:437s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:377s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:493s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:290s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:482s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:490s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:474s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:460s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:562s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:425s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:284s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:512s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:392s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:418s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:462s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:459s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:501s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:499s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:429s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:510s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:527s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:491s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:503s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:421s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:433s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:534s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:402s
Blacklisted hosts:
fi-glk-dsi   total:288  pass:257  dwarn:0   dfail:0   fail:1   skip:30  
time:471s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:453s

bd16af128e78b302b3034fa85626cd15dcf5f038 drm-tip: 2018y-02m-15d-00h-22m-40s UTC 
integration manifest
73fc8d1b6c6d drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
89079bc4387f drm/i915: Add NV12 support to intel_framebuffer_init
8af57462c087 drm/i915: Add NV12 as supported format for sprite plane
d0963cca44dc drm/i915: Add NV12 as supported format for primary plane
324f59e963ba drm/i915: Upscale scaler max scale for NV12
dd3dd77c470f drm/i915: Update format_is_yuv() to include NV12
84cdc8baa7b5 drm/i915: Set scaler mode for NV12
1597eed1bfce drm/i915/skl: split skl_compute_ddb function
ddeb5ee29a07 drm/i915/skl+: nv12 workaround disable WM level 1-7
d39c38f18583 drm/i915/skl+: make sure higher latency level has higher wm value
2b6dd34bd24d drm/i915/skl+: pass skl_wm_level struct to wm compute func
85e76858a77d drm/i915/skl+: NV12 related changes for WM
a99e0fac3589 drm/i915/skl+: support verification of DDB HW state for NV12
9e1c34f78b19 drm/i915/skl+: add NV12 in skl_format_to_fourcc
d2c46181e2bc drm/i915/skl+: refactor WM calculation for NV12
fdd5c40f60cb drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8037/issues.html
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Re: [Intel-gfx] [PATCH v3] drm/i915: Clean up ancient doc comments for i915_ioc32.c

[Chris Wilson]

Quoting Chris Wilson (2018-02-14 16:07:20)
> As befitting a file dedicated to the mistakes of the past,
> 
> drivers/gpu/drm/i915/i915_ioc32.c:2: warning: Cannot understand  * \file 
> i915_ioc32.c
>  on line 2 - I thought it was a doc line
> drivers/gpu/drm/i915/i915_ioc32.c:82: warning: Function parameter or member 
> 'filp' not described in 'i915_compat_ioctl'
> drivers/gpu/drm/i915/i915_ioc32.c:82: warning: Function parameter or member 
> 'cmd' not described in 'i915_compat_ioctl'
> drivers/gpu/drm/i915/i915_ioc32.c:82: warning: Function parameter or member 
> 'arg' not described in 'i915_compat_ioctl'
> 
> Signed-off-by: Chris Wilson 
> ---
> Don't drop the fixes this time!

Are we happy with this no-nonsense version?

> ---
>  drivers/gpu/drm/i915/i915_ioc32.c | 27 ---
>  1 file changed, 12 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_ioc32.c 
> b/drivers/gpu/drm/i915/i915_ioc32.c
> index 97f3a5640289..0e5c580d117c 100644
> --- a/drivers/gpu/drm/i915/i915_ioc32.c
> +++ b/drivers/gpu/drm/i915/i915_ioc32.c
> @@ -1,11 +1,6 @@
> -/**
> - * \file i915_ioc32.c
> - *
> +/*
>   * 32-bit ioctl compatibility routines for the i915 DRM.
>   *
> - * \author Alan Hourihane 
> - *
> - *
>   * Copyright (C) Paul Mackerras 2005
>   * Copyright (C) Alan Hourihane 2005
>   * All Rights Reserved.
> @@ -28,6 +23,8 @@
>   * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
>   * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>   * IN THE SOFTWARE.
> + *
> + * Author: Alan Hourihane 
>   */
>  #include 
>  
> @@ -55,10 +52,10 @@ static int compat_i915_getparam(struct file *file, 
> unsigned int cmd,
> return -EFAULT;
>  
> request = compat_alloc_user_space(sizeof(*request));
> -   if (!access_ok(VERIFY_WRITE, request, sizeof(*request))
> -   || __put_user(req32.param, >param)
> -   || __put_user((void __user *)(unsigned long)req32.value,
> - >value))
> +   if (!access_ok(VERIFY_WRITE, request, sizeof(*request)) ||
> +   __put_user(req32.param, >param) ||
> +   __put_user((void __user *)(unsigned long)req32.value,
> +  >value))
> return -EFAULT;
>  
> return drm_ioctl(file, DRM_IOCTL_I915_GETPARAM,
> @@ -70,13 +67,13 @@ static drm_ioctl_compat_t *i915_compat_ioctls[] = {
>  };
>  
>  /**
> + * i915_compat_ioctl - handle the mistakes of the past
> + * @filp: the file pointer
> + * @cmd: the ioctl command (and encoded flags)
> + * @arg: the ioctl argument (from userspace)
> + *
>   * Called whenever a 32-bit process running under a 64-bit kernel
>   * performs an ioctl on /dev/dri/card.
> - *
> - * \param filp file pointer.
> - * \param cmd command.
> - * \param arg user argument.
> - * \return zero on success or negative number on failure.
>   */
>  long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long 
> arg)
>  {
> -- 
> 2.16.1
> 
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Re: [Intel-gfx] [PATCH] drm/i915/audio: fix check for av_enc_map overflow

[Mika Kahola]

On Wed, 2018-02-14 at 19:38 +0200, Jani Nikula wrote:
> Turns out -1 >= ARRAY_SIZE() is always true. Move the bounds check
> where
> we know pipe >= 0 and next to the array indexing where it makes most
> sense.
> 
> Fixes: 9965db26ac05 ("drm/i915: Check for fused or unused pipes")
> Fixes: 0b7029b7e43f ("drm/i915: Check for fused or unused pipes")
> Cc:  # v4.10+
> Cc: Mika Kahola 
> Cc: Rodrigo Vivi 
> Cc: Jani Nikula 
> Cc: Joonas Lahtinen 
> Cc: intel-gfx@lists.freedesktop.org

Reviewed-by: Mika Kahola 

> Signed-off-by: Jani Nikula 
> ---
>  drivers/gpu/drm/i915/intel_audio.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_audio.c
> b/drivers/gpu/drm/i915/intel_audio.c
> index ff455c724775..709d6ca68074 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -779,11 +779,11 @@ static struct intel_encoder
> *get_saved_enc(struct drm_i915_private *dev_priv,
>  {
>   struct intel_encoder *encoder;
>  
> - if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map)))
> - return NULL;
> -
>   /* MST */
>   if (pipe >= 0) {
> + if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv-
> >av_enc_map)))
> + return NULL;
> +
>   encoder = dev_priv->av_enc_map[pipe];
>   /*
>    * when bootup, audio driver may not know it is
-- 
Mika Kahola - Intel OTC

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Adding NV12 support (rev11)

[Patchwork]

== Series Details ==

Series: Adding NV12 support (rev11)
URL   : https://patchwork.freedesktop.org/series/28103/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
fdd5c40f60cb drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
-:65: CHECK: Alignment should match open parenthesis
#65: FILE: drivers/gpu/drm/i915/intel_pm.c:5049:
+skl_copy_ddb_for_pipe(struct skl_ddb_values *dst,
+struct skl_ddb_values *src,

total: 0 errors, 0 warnings, 1 checks, 68 lines checked
d2c46181e2bc drm/i915/skl+: refactor WM calculation for NV12
-:180: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#180: FILE: drivers/gpu/drm/i915/intel_pm.c:4165:
+uint16_t *minimum, uint16_t *uv_minimum)

-:198: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#198: FILE: drivers/gpu/drm/i915/intel_pm.c:4198:
+   uint16_t uv_minimum[I915_MAX_PLANES] = {};

-:247: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#247: FILE: drivers/gpu/drm/i915/intel_pm.c:4262:
+   uint16_t plane_blocks, uv_plane_blocks;

total: 0 errors, 0 warnings, 3 checks, 293 lines checked
9e1c34f78b19 drm/i915/skl+: add NV12 in skl_format_to_fourcc
a99e0fac3589 drm/i915/skl+: support verification of DDB HW state for NV12
85e76858a77d drm/i915/skl+: NV12 related changes for WM
2b6dd34bd24d drm/i915/skl+: pass skl_wm_level struct to wm compute func
d39c38f18583 drm/i915/skl+: make sure higher latency level has higher wm value
ddeb5ee29a07 drm/i915/skl+: nv12 workaround disable WM level 1-7
-:34: CHECK: Unnecessary parentheses around 'level >= 1'
#34: FILE: drivers/gpu/drm/i915/intel_pm.c:4664:
+   if (wp->is_planar && (level >= 1) &&
+   (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
+IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {

-:35: CHECK: Alignment should match open parenthesis
#35: FILE: drivers/gpu/drm/i915/intel_pm.c:4665:
+   if (wp->is_planar && (level >= 1) &&
+   (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||

total: 0 errors, 0 warnings, 2 checks, 17 lines checked
1597eed1bfce drm/i915/skl: split skl_compute_ddb function
-:113: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#113: FILE: drivers/gpu/drm/i915/intel_pm.c:5144:
+   uint32_t realloc_pipes = pipes_modified(state);

-:132: CHECK: spaces preferred around that '*' (ctx:ExV)
#132: FILE: drivers/gpu/drm/i915/intel_pm.c:5163:
+   *changed = true;
^

total: 0 errors, 0 warnings, 2 checks, 194 lines checked
84cdc8baa7b5 drm/i915: Set scaler mode for NV12
-:55: CHECK: Prefer using the BIT macro
#55: FILE: drivers/gpu/drm/i915/i915_reg.h:6735:
+#define PS_SCALER_MODE_PLANAR (1 << 29)

total: 0 errors, 0 warnings, 1 checks, 21 lines checked
dd3dd77c470f drm/i915: Update format_is_yuv() to include NV12
324f59e963ba drm/i915: Upscale scaler max scale for NV12
-:146: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#146: FILE: drivers/gpu/drm/i915/intel_display.c:12836:
+   uint32_t pixel_format = 0;

total: 0 errors, 0 warnings, 1 checks, 119 lines checked
d0963cca44dc drm/i915: Add NV12 as supported format for primary plane
-:57: CHECK: Unnecessary parentheses around 'pipe == PIPE_C'
#57: FILE: drivers/gpu/drm/i915/intel_display.c:13259:
+   if ((INTEL_GEN(dev_priv) == 9 && (pipe == PIPE_C)) &&
+   !IS_GEMINILAKE(dev_priv))

-:58: CHECK: Alignment should match open parenthesis
#58: FILE: drivers/gpu/drm/i915/intel_display.c:13260:
+   if ((INTEL_GEN(dev_priv) == 9 && (pipe == PIPE_C)) &&
+   !IS_GEMINILAKE(dev_priv))

total: 0 errors, 0 warnings, 2 checks, 17 lines checked
8af57462c087 drm/i915: Add NV12 as supported format for sprite plane
-:71: CHECK: Alignment should match open parenthesis
#71: FILE: drivers/gpu/drm/i915/intel_sprite.c:1374:
+   if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) &&
+   (plane != 0 || pipe == PIPE_C)) ||

total: 0 errors, 0 warnings, 1 checks, 19 lines checked
89079bc4387f drm/i915: Add NV12 support to intel_framebuffer_init
-:61: WARNING: line over 80 characters
#61: FILE: drivers/gpu/drm/i915/intel_display.c:14069:
+ 
drm_get_format_name(mode_cmd->pixel_format,

-:62: CHECK: Alignment should match open parenthesis
#62: FILE: drivers/gpu/drm/i915/intel_display.c:14070:
+ 
drm_get_format_name(mode_cmd->pixel_format,
+ _name));

total: 0 errors, 1 warnings, 1 checks, 14 lines checked
73fc8d1b6c6d drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
-:21: CHECK: Prefer using the BIT macro
#21: FILE: drivers/gpu/drm/i915/i915_reg.h:6458:
+#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709  (1 << 17)

total: 0 errors, 0 warnings, 1 checks, 20 lines checked

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[Intel-gfx] [PATCH 2/2] drm/i915: Prune gen8_gt_irq_handler

[Chris Wilson]

The compiler is not automatically caching the i915->regs address inside
a register and emitting a load for every mmio access. For simple
functions like gen8_gt_irq_handler that are already using the raw
accessors, we can open-code them for substantial savings:

add/remove: 0/0 grow/shrink: 0/2 up/down: 0/-83 (-83)
Function old new   delta
gen8_gt_irq_handler  290 266 -24
gen8_gt_irq_ack  181 122 -59
Total: Before=954637, After=954554, chg -0.01%

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
And so begins the long haul of de-I915_READ/WRITE-ing the driver...
---
 drivers/gpu/drm/i915/i915_irq.c | 57 +++--
 1 file changed, 27 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b7b377ba7b6e..10d62b33cb13 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1413,9 +1413,11 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 
iir, int test_shift)
tasklet_hi_schedule(>tasklet);
 }
 
-static void gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
+static void gen8_gt_irq_ack(struct drm_i915_private *i915,
u32 master_ctl, u32 gt_iir[4])
 {
+   void __iomem * const regs = i915->regs;
+
 #define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
  GEN8_GT_BCS_IRQ | \
  GEN8_GT_VCS1_IRQ | \
@@ -1425,62 +1427,57 @@ static void gen8_gt_irq_ack(struct drm_i915_private 
*dev_priv,
  GEN8_GT_GUC_IRQ)
 
if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
-   gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
-   if (gt_iir[0])
-   I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
+   gt_iir[0] = readl(regs + i915_mmio_reg_offset(GEN8_GT_IIR(0)));
+   if (likely(gt_iir[0]))
+   writel(gt_iir[0], regs + 
i915_mmio_reg_offset(GEN8_GT_IIR(0)));
}
 
if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
-   gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
-   if (gt_iir[1])
-   I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
+   gt_iir[1] = readl(regs + i915_mmio_reg_offset(GEN8_GT_IIR(1)));
+   if (likely(gt_iir[1]))
+   writel(gt_iir[1], regs + 
i915_mmio_reg_offset(GEN8_GT_IIR(1)));
}
 
-   if (master_ctl & GEN8_GT_VECS_IRQ) {
-   gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
-   if (gt_iir[3])
-   I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
+   if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
+   gt_iir[2] = readl(regs + i915_mmio_reg_offset(GEN8_GT_IIR(2)));
+   if (likely(gt_iir[2] & (i915->pm_rps_events | 
i915->pm_guc_events)))
+   writel(gt_iir[2] & (i915->pm_rps_events |
+   i915->pm_guc_events),
+  regs + i915_mmio_reg_offset(GEN8_GT_IIR(2)));
}
 
-   if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
-   gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
-   if (gt_iir[2] & (dev_priv->pm_rps_events |
-dev_priv->pm_guc_events)) {
-   I915_WRITE_FW(GEN8_GT_IIR(2),
- gt_iir[2] & (dev_priv->pm_rps_events |
-  dev_priv->pm_guc_events));
-   }
+   if (master_ctl & GEN8_GT_VECS_IRQ) {
+   gt_iir[3] = readl(regs + i915_mmio_reg_offset(GEN8_GT_IIR(3)));
+   if (likely(gt_iir[3]))
+   writel(gt_iir[3], regs + 
i915_mmio_reg_offset(GEN8_GT_IIR(3)));
}
 }
 
-static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
+static void gen8_gt_irq_handler(struct drm_i915_private *i915,
u32 master_ctl, u32 gt_iir[4])
 {
if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
-   gen8_cs_irq_handler(dev_priv->engine[RCS],
+   gen8_cs_irq_handler(i915->engine[RCS],
gt_iir[0], GEN8_RCS_IRQ_SHIFT);
-   gen8_cs_irq_handler(dev_priv->engine[BCS],
+   gen8_cs_irq_handler(i915->engine[BCS],
gt_iir[0], GEN8_BCS_IRQ_SHIFT);
}
 
if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
-   gen8_cs_irq_handler(dev_priv->engine[VCS],
+   gen8_cs_irq_handler(i915->engine[VCS],
gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
-   gen8_cs_irq_handler(dev_priv->engine[VCS2],
+   gen8_cs_irq_handler(i915->engine[VCS2],
 

[Intel-gfx] [PATCH 1/2] drm/i915: Track GT interrupt handling using the master iir

[Chris Wilson]

Keep the master iir and use it to reduce the number of reads and writes
to the GT iir array, i.e. only the bits marked as set by the master iir
are valid inside GT iir array and will be handled during the interrupt.

Signed-off-by: Chris Wilson 
Cc: Ville Syrjala 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_irq.c | 51 +
 1 file changed, 31 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b886bd459acc..b7b377ba7b6e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1416,6 +1416,14 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 
iir, int test_shift)
 static void gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
u32 master_ctl, u32 gt_iir[4])
 {
+#define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
+ GEN8_GT_BCS_IRQ | \
+ GEN8_GT_VCS1_IRQ | \
+ GEN8_GT_VCS2_IRQ | \
+ GEN8_GT_VECS_IRQ | \
+ GEN8_GT_PM_IRQ | \
+ GEN8_GT_GUC_IRQ)
+
if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
if (gt_iir[0])
@@ -1446,31 +1454,34 @@ static void gen8_gt_irq_ack(struct drm_i915_private 
*dev_priv,
 }
 
 static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
-   u32 gt_iir[4])
+   u32 master_ctl, u32 gt_iir[4])
 {
-   if (gt_iir[0]) {
+   if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
gen8_cs_irq_handler(dev_priv->engine[RCS],
gt_iir[0], GEN8_RCS_IRQ_SHIFT);
gen8_cs_irq_handler(dev_priv->engine[BCS],
gt_iir[0], GEN8_BCS_IRQ_SHIFT);
}
 
-   if (gt_iir[1]) {
+   if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
gen8_cs_irq_handler(dev_priv->engine[VCS],
gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
gen8_cs_irq_handler(dev_priv->engine[VCS2],
gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
}
 
-   if (gt_iir[3])
+   if (master_ctl & GEN8_GT_VECS_IRQ) {
gen8_cs_irq_handler(dev_priv->engine[VECS],
gt_iir[3], GEN8_VECS_IRQ_SHIFT);
+   }
 
-   if (gt_iir[2] & dev_priv->pm_rps_events)
-   gen6_rps_irq_handler(dev_priv, gt_iir[2]);
+   if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
+   if (gt_iir[2] & dev_priv->pm_rps_events)
+   gen6_rps_irq_handler(dev_priv, gt_iir[2]);
 
-   if (gt_iir[2] & dev_priv->pm_guc_events)
-   gen9_guc_irq_handler(dev_priv, gt_iir[2]);
+   if (gt_iir[2] & dev_priv->pm_guc_events)
+   gen9_guc_irq_handler(dev_priv, gt_iir[2]);
+   }
 }
 
 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
@@ -2085,9 +2096,9 @@ static irqreturn_t cherryview_irq_handler(int irq, void 
*arg)
 
do {
u32 master_ctl, iir;
-   u32 gt_iir[4] = {};
u32 pipe_stats[I915_MAX_PIPES] = {};
u32 hotplug_status = 0;
+   u32 gt_iir[4];
u32 ier = 0;
 
master_ctl = I915_READ(GEN8_MASTER_IRQ) & 
~GEN8_MASTER_IRQ_CONTROL;
@@ -2140,7 +2151,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void 
*arg)
I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
POSTING_READ(GEN8_MASTER_IRQ);
 
-   gen8_gt_irq_handler(dev_priv, gt_iir);
+   gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
 
if (hotplug_status)
i9xx_hpd_irq_handler(dev_priv, hotplug_status);
@@ -2675,10 +2686,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, 
u32 master_ctl)
 
 static irqreturn_t gen8_irq_handler(int irq, void *arg)
 {
-   struct drm_device *dev = arg;
-   struct drm_i915_private *dev_priv = to_i915(dev);
+   struct drm_i915_private *dev_priv = to_i915(arg);
u32 master_ctl;
-   u32 gt_iir[4] = {};
+   u32 gt_iir[4];
 
if (!intel_irqs_enabled(dev_priv))
return IRQ_NONE;
@@ -2690,18 +2700,19 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 
I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
 
-   /* IRQs are synced during runtime_suspend, we don't require a wakeref */
-   disable_rpm_wakeref_asserts(dev_priv);
-
/* Find, clear, then process each source of interrupt */
gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
-   gen8_gt_irq_handler(dev_priv, gt_iir);
-   gen8_de_irq_handler(dev_priv, master_ctl);
+
+   /* IRQs are 

Re: [Intel-gfx] [PATCH v1] i915: Re-use DEFINE_SHOW_ATTRIBUTE() macro

[Chris Wilson]

Quoting Andy Shevchenko (2018-02-14 15:41:57)
> ...instead of open coding file operations followed by custom ->open()
> callbacks per each attribute.
> 
> Signed-off-by: Andy Shevchenko 

Reviewed-by: Chris Wilson 

Note depends on rc1 backmerge.
-Chris
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm: Add DPCD definitions for DP 1.4 FEC feature (rev5)

[Patchwork]

== Series Details ==

Series: drm: Add DPCD definitions for DP 1.4 FEC feature (rev5)
URL   : https://patchwork.freedesktop.org/series/34259/
State : failure

== Summary ==

Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-apl) fdo#99912
Test perf_pmu:
Subgroup busy-idle-rcs0:
pass   -> FAIL   (shard-apl)
Test perf:
Subgroup buffer-fill:
fail   -> PASS   (shard-apl) fdo#103755
Test pm_rpm:
Subgroup system-suspend:
pass   -> SKIP   (shard-hsw) fdo#103375
Test pm_rps:
Subgroup min-max-config-loaded:
pass   -> FAIL   (shard-apl) fdo#104060
Test kms_flip:
Subgroup flip-vs-expired-vblank:
pass   -> FAIL   (shard-apl) fdo#102887
Test drv_selftest:
Subgroup live_gtt:
pass   -> INCOMPLETE (shard-apl) fdo#103927
Test kms_rotation_crc:
Subgroup sprite-rotation-180:
fail   -> PASS   (shard-hsw)

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#104060 https://bugs.freedesktop.org/show_bug.cgi?id=104060
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927

shard-apltotal:3392 pass:1747 dwarn:1   dfail:0   fail:23  skip:1618 
time:13316s
shard-hswtotal:3427 pass:1758 dwarn:1   dfail:0   fail:10  skip:1657 
time:14612s
shard-snbtotal:3427 pass:1348 dwarn:1   dfail:0   fail:11  skip:2067 
time:7648s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8031/shards.html
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Re: [Intel-gfx] [PATCH 11/16] drm/i915: Update format_is_yuv() to include NV12

[Sharma, Shashank]

My previous review comments is neither acknowledged nor addressed.

Regards
Shashank
On 2/14/2018 10:27 AM, Vidya Srinivas wrote:

From: Chandra Konduru 

This patch adds NV12 to format_is_yuv() function
for sprite planes.

v2:
-Use intel_ prefix for format_is_yuv (Ville)

v3: Rebased (me)

v4: Rebased and addressed review comments from Clinton A Taylor.
"static function in intel_sprite.c is not available
to the primary plane functions".
Changed commit message - function modified for
sprite planes.

v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v6: Rebased (me)

v7: Rebased (me)

v8: Rebased (me)

v9: Rebased (me)

v10: Changed intel_format_is_yuv function from
static to non-static. We need to use it later from
other files for check.

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Reviewed-by: Shashank Sharma 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
  drivers/gpu/drm/i915/intel_drv.h| 1 +
  drivers/gpu/drm/i915/intel_sprite.c | 8 
  2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6402d6d..8d4988b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2034,6 +2034,7 @@ void skl_disable_plane(struct intel_plane *plane, struct 
intel_crtc *crtc);
  bool skl_plane_get_hw_state(struct intel_plane *plane);
  bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
   enum pipe pipe, enum plane_id plane_id);
+bool intel_format_is_yuv(uint32_t format);
  
  /* intel_tv.c */

  void intel_tv_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index e098e4b..2c51d8a 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -41,14 +41,14 @@
  #include 
  #include "i915_drv.h"
  
-static bool

-format_is_yuv(uint32_t format)
+bool intel_format_is_yuv(uint32_t format)
  {
switch (format) {
case DRM_FORMAT_YUYV:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_YVYU:
+   case DRM_FORMAT_NV12:
return true;
default:
return false;
@@ -352,7 +352,7 @@ chv_update_csc(struct intel_plane *plane, uint32_t format)
enum plane_id plane_id = plane->id;
  
  	/* Seems RGB data bypasses the CSC always */

-   if (!format_is_yuv(format))
+   if (!intel_format_is_yuv(format))
return;
  
  	/*

@@ -979,7 +979,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
src_y = src->y1 >> 16;
src_h = drm_rect_height(src) >> 16;
  
-		if (format_is_yuv(fb->format->format)) {

+   if (intel_format_is_yuv(fb->format->format)) {
src_x &= ~1;
src_w &= ~1;
  


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Re: [Intel-gfx] [PATCH 10/16] drm/i915: Set scaler mode for NV12

[Sharma, Shashank]

My previous review comments are not addressed on this patch.

I made a comment which is about programming bits *29:28* on *PS_CTRL for 
(GEN>=9) *blindly*.

*

This is not valid for all GEN9 and above, in fact bit 29:28 as scalar 
mode is only valid for SKL.


Bit 28 is not supported for GLK, bspec clearly mentions do not program 
this.


Also from GEN10 onward bit 28 is NOT for scaler mode, its for adaptive 
filtering.


Regards
Shashank
On 2/14/2018 10:27 AM, Vidya Srinivas wrote:

From: Chandra Konduru 

This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling

v2: Review comments from Ville addressed
NV12 case to be checked first for setting
the scaler

v3: Rebased (me)

v4: Rebased (me)

v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v6: Rebased (me)

v7: Rebased (me)

v8: Rebased (me)
Restricting the NV12 change for scaler to BXT and KBL
in this series.

v9: Rebased (me)

v10: As of now, NV12 has been tested on Gen9 and Gen10. However,
code is applicable to all GEN >= 9. Hence making
that change to keep it generic.
Comments under v8 is not valid anymore.

v11: Addressed review comments by Shashank Sharma.
For Gen10+, the scaler mode to be set it planar or normal
(single bit). Changed the code to be applicable to all
Gen.

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
  drivers/gpu/drm/i915/i915_reg.h | 1 +
  drivers/gpu/drm/i915/intel_atomic.c | 8 ++--
  2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f6afa5e..10edacc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6732,6 +6732,7 @@ enum {
  #define PS_SCALER_MODE_MASK (3 << 28)
  #define PS_SCALER_MODE_DYN  (0 << 28)
  #define PS_SCALER_MODE_HQ  (1 << 28)
+#define PS_SCALER_MODE_PLANAR (1 << 29)
  #define PS_PLANE_SEL_MASK  (7 << 25)
  #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
  #define PS_FILTER_MASK (3 << 23)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c 
b/drivers/gpu/drm/i915/intel_atomic.c
index d452c32..7ae4f48 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -327,8 +327,12 @@ int intel_atomic_setup_scalers(struct drm_i915_private 
*dev_priv,
}
  
  		/* set scaler mode */

-   if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
-   scaler_state->scalers[*scaler_id].mode = 0;
+   if ((INTEL_GEN(dev_priv) >= 9) &&
+   plane_state && plane_state->base.fb &&
+   plane_state->base.fb->format->format ==
+   DRM_FORMAT_NV12) {
+   scaler_state->scalers[*scaler_id].mode =
+   PS_SCALER_MODE_PLANAR;
} else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) 
{
/*
 * when only 1 scaler is in use on either pipe A or B,


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Re: [Intel-gfx] [PATCH 0/5] Fix deadlock on runtime suspend in DRM drivers

[Lukas Wunner]

On Wed, Feb 14, 2018 at 09:58:43AM -0500, Sean Paul wrote:
> On Wed, Feb 14, 2018 at 03:43:56PM +0100, Michel Dänzer wrote:
> > On 2018-02-14 03:08 PM, Sean Paul wrote:
> > > On Wed, Feb 14, 2018 at 10:26:35AM +0100, Maarten Lankhorst wrote:
> > >> Op 14-02-18 om 09:46 schreef Lukas Wunner:
> > >>> On Sun, Feb 11, 2018 at 10:38:28AM +0100, Lukas Wunner wrote:
> >  Fix a deadlock on hybrid graphics laptops that's been present since 
> >  2013:
> > >>> This series has been reviewed, consent has been expressed by the most
> > >>> interested parties, patch [1/5] which touches files outside drivers/gpu
> > >>> has been acked and I've just out a v2 addressing the only objection
> > >>> raised.  My plan is thus to wait another two days for comments and,
> > >>> barring further objections, push to drm-misc this weekend.
> > >>>
> > >>> However I'm struggling with the decision whether to push to next or
> > >>> fixes.  The series is marked for stable, however the number of
> > >>> affected machines is limited and for an issue that's been present
> > >>> for 5 years it probably doesn't matter if it soaks another two months
> > >>> in linux-next befor it gets backported.  Hence I tend to err on the
> > >>> side of caution and push to next, however a case could be made that
> > >>> fixes is more appropriate.
> > >>>
> > >>> I'm lacking experience making such decisions and would be interested
> > >>> to learn how you'd handle this.
> > >>
> > >> I would say fixes, it doesn't look particularly scary. :)
> > > 
> > > Agreed. If it's good enough for stable, it's good enough for -fixes!
> > 
> > It's not that simple, is it? Fast-tracking patches (some of which appear
> > to be untested) to stable without an immediate cause for urgency seems
> > risky to me.
> 
> /me should be more careful what he says
> 
> Given where we are in the release cycle, it's barely a fast track.
> If these go in -fixes, they'll get in -rc2 and will have plenty of
> time to bake. If we were at rc5, it might be a different story.

The patches are marked for stable though, so if they go in through
drm-misc-fixes, they may appear in stable kernels before 4.16-final
is out.  Greg picks up patches once they're in Linus' tree, though
often with a delay of a few days or weeks.  If they go in through
drm-misc-next, they're guaranteed not to appear in *any* release
before 4.16-final is out.

This allows for differentiation between no-brainer stable fixes that
can be sent immediately and scarier, but similarly important stable
fixes that should soak for a while.  I'm not sure which category
this series belongs to, though it's true what Maarten says, it's
not *that* grave a change.

Thanks,

Lukas
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm: Add COLOR_ENCODING and COLOR_RANGE plane properties

[Patchwork]

== Series Details ==

Series: drm: Add COLOR_ENCODING and COLOR_RANGE plane properties
URL   : https://patchwork.freedesktop.org/series/38286/
State : success

== Summary ==

Test gem_eio:
Subgroup hibernate:
incomplete -> PASS   (shard-hsw) fdo#103540
Test kms_flip:
Subgroup flip-vs-expired-vblank:
fail   -> PASS   (shard-apl) fdo#102887
Subgroup plain-flip-ts-check-interruptible:
fail   -> PASS   (shard-hsw) fdo#100368
Test kms_sysfs_edid_timing:
warn   -> PASS   (shard-apl) fdo#100047
Test kms_fbcon_fbt:
Subgroup fbc-suspend:
pass   -> SKIP   (shard-hsw) fdo#105087

fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#105087 https://bugs.freedesktop.org/show_bug.cgi?id=105087

shard-apltotal:3414 pass:1774 dwarn:1   dfail:0   fail:20  skip:1618 
time:13764s
shard-hswtotal:3427 pass:1758 dwarn:1   dfail:0   fail:10  skip:1657 
time:14560s
shard-snbtotal:3427 pass:1347 dwarn:1   dfail:0   fail:11  skip:2068 
time:7587s
Blacklisted hosts:
shard-kbltotal:3377 pass:1852 dwarn:23  dfail:1   fail:21  skip:1479 
time:10765s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8030/shards.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: fix rsvd2 mask when out-fence is returned

[Patchwork]

== Series Details ==

Series: drm/i915: fix rsvd2 mask when out-fence is returned
URL   : https://patchwork.freedesktop.org/series/38284/
State : success

== Summary ==

Test kms_flip:
Subgroup plain-flip-ts-check-interruptible:
fail   -> PASS   (shard-hsw) fdo#100368
Subgroup flip-vs-expired-vblank:
fail   -> PASS   (shard-apl) fdo#102887
Test gem_eio:
Subgroup hibernate:
incomplete -> PASS   (shard-hsw) fdo#103540
Test pm_rpm:
Subgroup system-suspend-execbuf:
pass   -> SKIP   (shard-hsw) fdo#103375
Test perf:
Subgroup oa-exponents:
pass   -> FAIL   (shard-apl) fdo#102254
Test kms_cursor_legacy:
Subgroup 2x-long-flip-vs-cursor-legacy:
pass   -> FAIL   (shard-hsw) fdo#104873
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-pri-indfb-multidraw:
pass   -> FAIL   (shard-snb) fdo#103167

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167

shard-apltotal:3414 pass:1772 dwarn:1   dfail:0   fail:21  skip:1618 
time:13728s
shard-hswtotal:3427 pass:1757 dwarn:1   dfail:0   fail:11  skip:1657 
time:14495s
shard-snbtotal:3427 pass:1346 dwarn:1   dfail:0   fail:12  skip:2068 
time:7518s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8029/shards.html
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Adding NV12 support (rev11)

[Patchwork]

== Series Details ==

Series: Adding NV12 support (rev11)
URL   : https://patchwork.freedesktop.org/series/28103/
State : failure

== Summary ==

Series 28103v11 Adding NV12 support
https://patchwork.freedesktop.org/api/1.0/series/28103/revisions/11/mbox/

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
pass   -> INCOMPLETE (fi-bxt-dsi)

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:421s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:426s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:376s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:497s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:289s
fi-bxt-dsi   total:246  pass:219  dwarn:0   dfail:0   fail:0   skip:26 
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:475s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:461s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:574s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:424s
fi-gdg-551   total:288  pass:180  dwarn:0   dfail:0   fail:0   skip:108 
time:285s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:510s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:401s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:423s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:461s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:461s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:498s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:501s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:584s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:434s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:508s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:529s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:497s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:485s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:417s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:432s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:530s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:404s
Blacklisted hosts:
fi-glk-dsi   total:288  pass:257  dwarn:0   dfail:0   fail:1   skip:30  
time:465s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:461s

bd16af128e78b302b3034fa85626cd15dcf5f038 drm-tip: 2018y-02m-15d-00h-22m-40s UTC 
integration manifest
f716c88bee62 drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
7558353b0351 drm/i915: Add NV12 support to intel_framebuffer_init
afe83893650a drm/i915: Add NV12 as supported format for sprite plane
62adeaa74a33 drm/i915: Add NV12 as supported format for primary plane
d1c743d06870 drm/i915: Upscale scaler max scale for NV12
0ae0b2729b35 drm/i915: Update format_is_yuv() to include NV12
9d1fa6c655c9 drm/i915: Set scaler mode for NV12
f708ecd83f9a drm/i915/skl: split skl_compute_ddb function
a82f7ae342b3 drm/i915/skl+: nv12 workaround disable WM level 1-7
080ae278ef65 drm/i915/skl+: make sure higher latency level has higher wm value
238d40b3ef30 drm/i915/skl+: pass skl_wm_level struct to wm compute func
f2afa54b0be2 drm/i915/skl+: NV12 related changes for WM
b8121b942b13 drm/i915/skl+: support verification of DDB HW state for NV12
f4e98e5d8417 drm/i915/skl+: add NV12 in skl_format_to_fourcc
c3472e45a098 drm/i915/skl+: refactor WM calculation for NV12
37fc44abdbe1 drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8036/issues.html
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Adding NV12 support (rev11)

[Patchwork]

== Series Details ==

Series: Adding NV12 support (rev11)
URL   : https://patchwork.freedesktop.org/series/28103/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
37fc44abdbe1 drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
-:65: CHECK: Alignment should match open parenthesis
#65: FILE: drivers/gpu/drm/i915/intel_pm.c:5049:
+skl_copy_ddb_for_pipe(struct skl_ddb_values *dst,
+struct skl_ddb_values *src,

total: 0 errors, 0 warnings, 1 checks, 68 lines checked
c3472e45a098 drm/i915/skl+: refactor WM calculation for NV12
-:180: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#180: FILE: drivers/gpu/drm/i915/intel_pm.c:4165:
+uint16_t *minimum, uint16_t *uv_minimum)

-:198: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#198: FILE: drivers/gpu/drm/i915/intel_pm.c:4198:
+   uint16_t uv_minimum[I915_MAX_PLANES] = {};

-:247: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#247: FILE: drivers/gpu/drm/i915/intel_pm.c:4262:
+   uint16_t plane_blocks, uv_plane_blocks;

total: 0 errors, 0 warnings, 3 checks, 293 lines checked
f4e98e5d8417 drm/i915/skl+: add NV12 in skl_format_to_fourcc
b8121b942b13 drm/i915/skl+: support verification of DDB HW state for NV12
f2afa54b0be2 drm/i915/skl+: NV12 related changes for WM
238d40b3ef30 drm/i915/skl+: pass skl_wm_level struct to wm compute func
080ae278ef65 drm/i915/skl+: make sure higher latency level has higher wm value
a82f7ae342b3 drm/i915/skl+: nv12 workaround disable WM level 1-7
-:34: CHECK: Unnecessary parentheses around 'level >= 1'
#34: FILE: drivers/gpu/drm/i915/intel_pm.c:4664:
+   if (wp->is_planar && (level >= 1) &&
+   (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
+IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {

-:35: CHECK: Alignment should match open parenthesis
#35: FILE: drivers/gpu/drm/i915/intel_pm.c:4665:
+   if (wp->is_planar && (level >= 1) &&
+   (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||

total: 0 errors, 0 warnings, 2 checks, 17 lines checked
f708ecd83f9a drm/i915/skl: split skl_compute_ddb function
-:113: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#113: FILE: drivers/gpu/drm/i915/intel_pm.c:5144:
+   uint32_t realloc_pipes = pipes_modified(state);

-:132: CHECK: spaces preferred around that '*' (ctx:ExV)
#132: FILE: drivers/gpu/drm/i915/intel_pm.c:5163:
+   *changed = true;
^

total: 0 errors, 0 warnings, 2 checks, 194 lines checked
9d1fa6c655c9 drm/i915: Set scaler mode for NV12
-:55: CHECK: Prefer using the BIT macro
#55: FILE: drivers/gpu/drm/i915/i915_reg.h:6735:
+#define PS_SCALER_MODE_PLANAR (1 << 29)

total: 0 errors, 0 warnings, 1 checks, 21 lines checked
0ae0b2729b35 drm/i915: Update format_is_yuv() to include NV12
d1c743d06870 drm/i915: Upscale scaler max scale for NV12
-:146: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#146: FILE: drivers/gpu/drm/i915/intel_display.c:12836:
+   uint32_t pixel_format = 0;

total: 0 errors, 0 warnings, 1 checks, 119 lines checked
62adeaa74a33 drm/i915: Add NV12 as supported format for primary plane
-:57: CHECK: Unnecessary parentheses around 'pipe == PIPE_C'
#57: FILE: drivers/gpu/drm/i915/intel_display.c:13259:
+   if ((INTEL_GEN(dev_priv) == 9 && (pipe == PIPE_C)) &&
+   !IS_GEMINILAKE(dev_priv))

-:58: CHECK: Alignment should match open parenthesis
#58: FILE: drivers/gpu/drm/i915/intel_display.c:13260:
+   if ((INTEL_GEN(dev_priv) == 9 && (pipe == PIPE_C)) &&
+   !IS_GEMINILAKE(dev_priv))

total: 0 errors, 0 warnings, 2 checks, 17 lines checked
afe83893650a drm/i915: Add NV12 as supported format for sprite plane
-:71: CHECK: Alignment should match open parenthesis
#71: FILE: drivers/gpu/drm/i915/intel_sprite.c:1374:
+   if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) &&
+   (plane != 0 || pipe == PIPE_C)) ||

total: 0 errors, 0 warnings, 1 checks, 19 lines checked
7558353b0351 drm/i915: Add NV12 support to intel_framebuffer_init
-:61: WARNING: line over 80 characters
#61: FILE: drivers/gpu/drm/i915/intel_display.c:14069:
+ 
drm_get_format_name(mode_cmd->pixel_format,

-:62: CHECK: Alignment should match open parenthesis
#62: FILE: drivers/gpu/drm/i915/intel_display.c:14070:
+ 
drm_get_format_name(mode_cmd->pixel_format,
+ _name));

total: 0 errors, 1 warnings, 1 checks, 14 lines checked
f716c88bee62 drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
-:21: CHECK: Prefer using the BIT macro
#21: FILE: drivers/gpu/drm/i915/i915_reg.h:6458:
+#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709  (1 << 17)

total: 0 errors, 0 warnings, 1 checks, 20 lines checked

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[Intel-gfx] [PATCH 15/16] drm/i915: Add NV12 support to intel_framebuffer_init

[Vidya Srinivas]

From: Chandra Konduru 

This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.

v2:
-Fix an issue in checks added (Chandra Konduru)

v3: rebased (me)

v4: Review comments by Ville addressed
Added platform check for NV12 in intel_framebuffer_init
Removed offset checks for NV12 case

v5: Addressed review comments by Clinton A Taylor
This NV12 support only correctly works on SKL.
Plane color space conversion is different on GLK and later platforms
causing the colors to display incorrectly.
Ville's plane color space property patch series
in review will fix this issue.
- Restricted the NV12 case in intel_framebuffer_init to
SKL and BXT only.

v6: Rebased (me)

v7: Addressed review comments by Ville
Restricting the NV12 to BXT for now.

v8: Rebased (me)
Restricting the NV12 changes to BXT and KBL for now.

v9: Rebased (me)

v10: NV12 supported by all GEN >= 9.
Making this change in intel_framebuffer_init. This is
part of addressing Maarten's review comments.
Comment under v8 no longer applicable

v11: Addressed review comments from Shashank Sharma

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_display.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 6f43d72..42ec089 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14063,6 +14063,14 @@ static int intel_framebuffer_init(struct 
intel_framebuffer *intel_fb,
goto err;
}
break;
+   case DRM_FORMAT_NV12:
+   if (INTEL_GEN(dev_priv) < 9) {
+   DRM_DEBUG_KMS("unsupported pixel format: %s\n",
+ 
drm_get_format_name(mode_cmd->pixel_format,
+ _name));
+   goto err;
+   }
+   break;
default:
DRM_DEBUG_KMS("unsupported pixel format: %s\n",
  drm_get_format_name(mode_cmd->pixel_format, 
_name));
-- 
2.7.4

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[Intel-gfx] [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

[Vidya Srinivas]

If the fb format is YUV, enable the plane CSC mode bits
for the conversion.

Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/i915_reg.h  | 6 ++
 drivers/gpu/drm/i915/intel_display.c | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 10edacc..baf197b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6453,6 +6453,12 @@ enum {
 #define _PLANE_COLOR_CTL_3_A   0x703CC /* GLK+ */
 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30)
 #define   PLANE_COLOR_PIPE_CSC_ENABLE  (1 << 23)
+#define PLANE_COLOR_CSC_MASK   (0x7 << 17)
+#define PLANE_COLOR_CSC_MODE_BYPASS(0 << 17)
+#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709  (1 << 17)
+#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709  (2 << 17)
+#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020(3 << 17)
+#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
 #define   PLANE_COLOR_PLANE_GAMMA_DISABLE  (1 << 13)
 #define   PLANE_COLOR_ALPHA_MASK   (0x3 << 4)
 #define   PLANE_COLOR_ALPHA_DISABLE(0 << 4)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 42ec089..6c43eef 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3577,6 +3577,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state 
*crtc_state,
plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
+   if (fb && intel_format_is_yuv(fb->format->format))
+   plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
 
return plane_color_ctl;
 }
-- 
2.7.4

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[Intel-gfx] [PATCH 12/16] drm/i915: Upscale scaler max scale for NV12

[Vidya Srinivas]

From: Chandra Konduru 

This patch updates scaler max limit support for NV12

v2: Rebased (me)

v3: Rebased (me)

v4: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v5: Addressed review comments from Ville and rebased
- calculation of max_scale to be made
less convoluted by splitting it up a bit
- Indentation errors to be fixed in the series

v6: Rebased (me)
Fixed review comments from Paauwe, Bob J
Previous version, where a split of calculation
was done, was wrong. Fixed that issue here.

v7: Rebased (me)

v8: Rebased (me)

v9: Rebased (me)

v10: Rebased (me)

v11: Addressed review comments from Shashank Sharma

v12: Fixed failure in IGT debugfs_test.
fb is NULL in skl_update_scaler_plane
Due to this, accessing fb->format caused failure.
Patch checks fb before using.

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_display.c | 40 ++--
 drivers/gpu/drm/i915/intel_drv.h |  3 ++-
 drivers/gpu/drm/i915/intel_sprite.c  |  3 ++-
 3 files changed, 33 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 971bd04..ac8279a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3435,6 +3435,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
case DRM_FORMAT_VYUY:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
+   case DRM_FORMAT_NV12:
+   return PLANE_CTL_FORMAT_NV12;
default:
MISSING_CASE(pixel_format);
}
@@ -4658,7 +4660,9 @@ static void cpt_verify_modeset(struct drm_device *dev, 
int pipe)
 static int
 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
  unsigned int scaler_user, int *scaler_id,
- int src_w, int src_h, int dst_w, int dst_h)
+ int src_w, int src_h, int dst_w, int dst_h,
+ bool plane_scaler_check,
+ uint32_t pixel_format)
 {
struct intel_crtc_scaler_state *scaler_state =
_state->scaler_state;
@@ -4676,6 +4680,9 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, 
bool force_detach,
 */
need_scaling = src_w != dst_w || src_h != dst_h;
 
+   if (plane_scaler_check)
+   need_scaling = pixel_format == DRM_FORMAT_NV12;
+
if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
need_scaling = true;
 
@@ -4751,9 +4758,10 @@ int skl_update_scaler_crtc(struct intel_crtc_state 
*state)
const struct drm_display_mode *adjusted_mode = 
>base.adjusted_mode;
 
return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
-   >scaler_state.scaler_id,
-   state->pipe_src_w, state->pipe_src_h,
-   adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
+>scaler_state.scaler_id,
+state->pipe_src_w, state->pipe_src_h,
+adjusted_mode->crtc_hdisplay,
+adjusted_mode->crtc_vdisplay, false, 0);
 }
 
 /**
@@ -4783,7 +4791,8 @@ static int skl_update_scaler_plane(struct 
intel_crtc_state *crtc_state,
drm_rect_width(_state->base.src) >> 16,
drm_rect_height(_state->base.src) >> 16,
drm_rect_width(_state->base.dst),
-   drm_rect_height(_state->base.dst));
+   drm_rect_height(_state->base.dst),
+   fb ? true : false, fb ? fb->format->format : 0);
 
if (ret || plane_state->scaler_id < 0)
return ret;
@@ -4809,6 +4818,7 @@ static int skl_update_scaler_plane(struct 
intel_crtc_state *crtc_state,
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+   case DRM_FORMAT_NV12:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 
0x%x\n",
@@ -12775,11 +12785,13 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
 }
 
 int
-skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state 
*crtc_state)
+skl_max_scale(struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *crtc_state,
+ uint32_t pixel_format)
 {
struct drm_i915_private *dev_priv;
-   int max_scale;
-   int crtc_clock, max_dotclk;
+   int max_scale, mult;
+   int crtc_clock, 

[Intel-gfx] [PATCH 07/16] drm/i915/skl+: make sure higher latency level has higher wm value

[Vidya Srinivas]

From: Mahesh Kumar 

DDB allocation optimization algorithm requires/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below the
current level. Render decompression requires level WM to be as high as
wm level-0. This patch fulfils both the requirements.

v2: Changed plane_num to plane_id in skl_compute_wm_levels

Signed-off-by: Mahesh Kumar 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_pm.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5154ce3..77c268f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4532,6 +4532,7 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
uint16_t ddb_allocation,
int level,
const struct skl_wm_params *wp,
+   const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */)
 {
const struct drm_plane_state *pstate = _pstate->base;
@@ -4599,6 +4600,15 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
} else {
res_blocks++;
}
+
+   /*
+* Make sure result blocks for higher latency levels are atleast
+* as high as level below the current level.
+* Assumption in DDB algorithm optimization for special cases.
+* Also covers Display WA #1125 for RC.
+*/
+   if (result_prev->plane_res_b > res_blocks)
+   res_blocks = result_prev->plane_res_b;
}
 
if (INTEL_GEN(dev_priv) >= 11) {
@@ -4682,6 +4692,13 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = plane_id ? >uv_wm[level] :
  >wm[level];
+   struct skl_wm_level *result_prev;
+
+   if (level)
+   result_prev = plane_id ? >uv_wm[level - 1] :
+ >wm[level - 1];
+   else
+   result_prev = plane_id ? >uv_wm[0] : >wm[0];
 
ret = skl_compute_plane_wm(dev_priv,
   cstate,
@@ -4689,6 +4706,7 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
   ddb_blocks,
   level,
   wm_params,
+  result_prev,
   result);
if (ret)
return ret;
-- 
2.7.4

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[Intel-gfx] [PATCH 09/16] drm/i915/skl: split skl_compute_ddb function

[Vidya Srinivas]

From: Mahesh Kumar 

This patch splits skl_compute_wm/ddb functions into two parts.
One adds all affected pipes after the commit to atomic_state structure
and second part does compute the DDB.

v2: Added reviewed by tag from Shashank Sharma

Reviewed-by: Shashank Sharma 
Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/intel_pm.c | 157 ++--
 1 file changed, 88 insertions(+), 69 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b575991..513804b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5061,69 +5061,16 @@ skl_ddb_add_affected_planes(struct intel_crtc_state 
*cstate)
 static int
 skl_compute_ddb(struct drm_atomic_state *state)
 {
-   struct drm_device *dev = state->dev;
-   struct drm_i915_private *dev_priv = to_i915(dev);
+   const struct drm_i915_private *dev_priv = to_i915(state->dev);
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-   struct intel_crtc *intel_crtc;
struct skl_ddb_allocation *ddb = _state->wm_results.ddb;
-   uint32_t realloc_pipes = pipes_modified(state);
-   int ret;
-
-   /*
-* If this is our first atomic update following hardware readout,
-* we can't trust the DDB that the BIOS programmed for us.  Let's
-* pretend that all pipes switched active status so that we'll
-* ensure a full DDB recompute.
-*/
-   if (dev_priv->wm.distrust_bios_wm) {
-   ret = drm_modeset_lock(>mode_config.connection_mutex,
-  state->acquire_ctx);
-   if (ret)
-   return ret;
-
-   intel_state->active_pipe_changes = ~0;
-
-   /*
-* We usually only initialize intel_state->active_crtcs if we
-* we're doing a modeset; make sure this field is always
-* initialized during the sanitization process that happens
-* on the first commit too.
-*/
-   if (!intel_state->modeset)
-   intel_state->active_crtcs = dev_priv->active_crtcs;
-   }
-
-   /*
-* If the modeset changes which CRTC's are active, we need to
-* recompute the DDB allocation for *all* active pipes, even
-* those that weren't otherwise being modified in any way by this
-* atomic commit.  Due to the shrinking of the per-pipe allocations
-* when new active CRTC's are added, it's possible for a pipe that
-* we were already using and aren't changing at all here to suddenly
-* become invalid if its DDB needs exceeds its new allocation.
-*
-* Note that if we wind up doing a full DDB recompute, we can't let
-* any other display updates race with this transaction, so we need
-* to grab the lock on *all* CRTC's.
-*/
-   if (intel_state->active_pipe_changes) {
-   realloc_pipes = ~0;
-   intel_state->wm_results.dirty_pipes = ~0;
-   }
+   struct intel_crtc *crtc;
+   struct intel_crtc_state *cstate;
+   int ret, i;
 
-   /*
-* We're not recomputing for the pipes not included in the commit, so
-* make sure we start with the current state.
-*/
memcpy(ddb, _priv->wm.skl_hw.ddb, sizeof(*ddb));
 
-   for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
-   struct intel_crtc_state *cstate;
-
-   cstate = intel_atomic_get_crtc_state(state, intel_crtc);
-   if (IS_ERR(cstate))
-   return PTR_ERR(cstate);
-
+   for_each_new_intel_crtc_in_state(intel_state, crtc, cstate, i) {
ret = skl_allocate_pipe_ddb(cstate, ddb);
if (ret)
return ret;
@@ -5185,23 +5132,23 @@ skl_print_wm_changes(const struct drm_atomic_state 
*state)
 }
 
 static int
-skl_compute_wm(struct drm_atomic_state *state)
+skl_ddb_add_affected_pipes(struct drm_atomic_state *state, bool *changed)
 {
-   struct drm_crtc *crtc;
-   struct drm_crtc_state *cstate;
-   struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-   struct skl_ddb_values *results = _state->wm_results;
struct drm_device *dev = state->dev;
-   struct skl_pipe_wm *pipe_wm;
-   bool changed = false;
+   const struct drm_i915_private *dev_priv = to_i915(dev);
+   const struct drm_crtc *crtc;
+   const struct drm_crtc_state *cstate;
+   struct intel_crtc *intel_crtc;
+   struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+   uint32_t realloc_pipes = pipes_modified(state);
int ret, i;
 
/*
 * When we distrust bios wm we always need to recompute to set the
 * expected DDB allocations for each 

[Intel-gfx] [PATCH 00/16] Adding NV12 support

[Vidya Srinivas]

This patch series is adding NV12 support for Broxton display after rebasing on
latest drm-tip.
Initial series of the patches can be found here:
https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html

Previous revision history:
The first version of patches were reviewed when floated by Chandra in 2015
but currently there was a design change with respect to
- the way fb offset is handled
- the way rotation is handled
Current NV12 patch series has been ported as per the
current changes on drm-tip

Review comments from Ville (12th June 2017) have been addressed Review
comments from Clinton A Taylor (7th July 2017) have been addressed

Review comments from Clinton A Taylor (10th July 2017)
have been addressed. Had missed out tested-by/reviewed-by in the 
patches.

Fixed that error in this series.
Review comments from Ville (11th July 2017) addressed.
Review comments from Paauwe, Bob (29th July 2017) addressed.

Update from rev 28 Aug 2017
Rebased the series.
Tested with IGT for rotation, sprite and tiling combinations.
IGT Links:
https://patchwork.kernel.org/patch/9995943/
https://patchwork.kernel.org/patch/9995945/
Review comments by Maarten are addressed in this series.
NV12 enabled for Gen10.
Review comments from Shashank Sharma are addressed.
IGT debug_fs test failure fixed.

Update from last rev:
Addressed review comments from Shashank Sharma and Maarten

Chandra Konduru (6):
  drm/i915: Set scaler mode for NV12
  drm/i915: Update format_is_yuv() to include NV12
  drm/i915: Upscale scaler max scale for NV12
  drm/i915: Add NV12 as supported format for primary plane
  drm/i915: Add NV12 as supported format for sprite plane
  drm/i915: Add NV12 support to intel_framebuffer_init

Mahesh Kumar (9):
  drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
  drm/i915/skl+: refactor WM calculation for NV12
  drm/i915/skl+: add NV12 in skl_format_to_fourcc
  drm/i915/skl+: support verification of DDB HW state for NV12
  drm/i915/skl+: NV12 related changes for WM
  drm/i915/skl+: pass skl_wm_level struct to wm compute func
  drm/i915/skl+: make sure higher latency level has higher wm value
  drm/i915/skl+: nv12 workaround disable WM level 1-7
  drm/i915/skl: split skl_compute_ddb function

Vidya Srinivas (1):
  drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

 drivers/gpu/drm/i915/i915_drv.h  |  10 +-
 drivers/gpu/drm/i915/i915_reg.h  |   7 +
 drivers/gpu/drm/i915/intel_atomic.c  |   8 +-
 drivers/gpu/drm/i915/intel_display.c |  59 -
 drivers/gpu/drm/i915/intel_drv.h |   9 +-
 drivers/gpu/drm/i915/intel_pm.c  | 436 ++-
 drivers/gpu/drm/i915/intel_sprite.c  |  18 +-
 7 files changed, 360 insertions(+), 187 deletions(-)

-- 
2.7.4

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[Intel-gfx] [PATCH 10/16] drm/i915: Set scaler mode for NV12

[Vidya Srinivas]

From: Chandra Konduru 

This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling

v2: Review comments from Ville addressed
NV12 case to be checked first for setting
the scaler

v3: Rebased (me)

v4: Rebased (me)

v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v6: Rebased (me)

v7: Rebased (me)

v8: Rebased (me)
Restricting the NV12 change for scaler to BXT and KBL
in this series.

v9: Rebased (me)

v10: As of now, NV12 has been tested on Gen9 and Gen10. However,
code is applicable to all GEN >= 9. Hence making
that change to keep it generic.
Comments under v8 is not valid anymore.

v11: Addressed review comments by Shashank Sharma.
For Gen10+, the scaler mode to be set it planar or normal
(single bit). Changed the code to be applicable to all
Gen.

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_atomic.c | 8 ++--
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f6afa5e..10edacc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6732,6 +6732,7 @@ enum {
 #define PS_SCALER_MODE_MASK (3 << 28)
 #define PS_SCALER_MODE_DYN  (0 << 28)
 #define PS_SCALER_MODE_HQ  (1 << 28)
+#define PS_SCALER_MODE_PLANAR (1 << 29)
 #define PS_PLANE_SEL_MASK  (7 << 25)
 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
 #define PS_FILTER_MASK (3 << 23)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c 
b/drivers/gpu/drm/i915/intel_atomic.c
index d452c32..7ae4f48 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -327,8 +327,12 @@ int intel_atomic_setup_scalers(struct drm_i915_private 
*dev_priv,
}
 
/* set scaler mode */
-   if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
-   scaler_state->scalers[*scaler_id].mode = 0;
+   if ((INTEL_GEN(dev_priv) >= 9) &&
+   plane_state && plane_state->base.fb &&
+   plane_state->base.fb->format->format ==
+   DRM_FORMAT_NV12) {
+   scaler_state->scalers[*scaler_id].mode =
+   PS_SCALER_MODE_PLANAR;
} else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) 
{
/*
 * when only 1 scaler is in use on either pipe A or B,
-- 
2.7.4

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[Intel-gfx] [PATCH 02/16] drm/i915/skl+: refactor WM calculation for NV12

[Vidya Srinivas]

From: Mahesh Kumar 

Current code calculates DDB for planar formats in such a way that we
store DDB of plane-0 in plane 1 & vice-versa.
In order to make this clean this patch refactors WM/DDB calculation for
NV12 planar formats.

v2: Addressed review comments by Maarten

v3: Rebased and addressed review comments by Maarten

v4: Fixed a compilation issue of string replacement is_nv12 to
is_planar

Reviewed-by: Maarten Lankhorst 
Signed-off-by: Mahesh Kumar 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/i915_drv.h  |   5 +-
 drivers/gpu/drm/i915/intel_drv.h |   1 +
 drivers/gpu/drm/i915/intel_pm.c  | 121 ---
 3 files changed, 66 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9377bd9..8967cc1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1444,8 +1444,9 @@ static inline bool skl_ddb_entry_equal(const struct 
skl_ddb_entry *e1,
 }
 
 struct skl_ddb_allocation {
-   struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* 
packed/uv */
-   struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
+   /* packed/y */
+   struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
+   struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
 };
 
 struct skl_ddb_values {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e74efb4..70447c6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -595,6 +595,7 @@ struct intel_pipe_wm {
 struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level trans_wm;
+   bool is_planar;
 };
 
 struct skl_pipe_wm {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6fec748..cf861a9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4012,9 +4012,9 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc 
*intel_crtc,
 static unsigned int
 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
 const struct drm_plane_state *pstate,
-int y)
+const int plane)
 {
-   struct intel_plane *plane = to_intel_plane(pstate->plane);
+   struct intel_plane *intel_plane = to_intel_plane(pstate->plane);
struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
uint32_t data_rate;
uint32_t width = 0, height = 0;
@@ -4028,9 +4028,9 @@ skl_plane_relative_data_rate(const struct 
intel_crtc_state *cstate,
fb = pstate->fb;
format = fb->format->format;
 
-   if (plane->id == PLANE_CURSOR)
+   if (intel_plane->id == PLANE_CURSOR)
return 0;
-   if (y && format != DRM_FORMAT_NV12)
+   if (plane == 1 && format != DRM_FORMAT_NV12)
return 0;
 
/*
@@ -4041,19 +4041,14 @@ skl_plane_relative_data_rate(const struct 
intel_crtc_state *cstate,
width = drm_rect_width(_pstate->base.src) >> 16;
height = drm_rect_height(_pstate->base.src) >> 16;
 
-   /* for planar format */
-   if (format == DRM_FORMAT_NV12) {
-   if (y)  /* y-plane data rate */
-   data_rate = width * height *
-   fb->format->cpp[0];
-   else/* uv-plane data rate */
-   data_rate = (width / 2) * (height / 2) *
-   fb->format->cpp[1];
-   } else {
-   /* for packed formats */
-   data_rate = width * height * fb->format->cpp[0];
+   /* UV plane does 1/2 pixel sub-sampling */
+   if (plane == 1 && format == DRM_FORMAT_NV12) {
+   width /= 2;
+   height /= 2;
}
 
+   data_rate = width * height * fb->format->cpp[plane];
+
down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
 
return mul_round_up_u32_fixed16(data_rate, down_scale_amount);
@@ -4066,8 +4061,8 @@ skl_plane_relative_data_rate(const struct 
intel_crtc_state *cstate,
  */
 static unsigned int
 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
-unsigned *plane_data_rate,
-unsigned *plane_y_data_rate)
+unsigned int *plane_data_rate,
+unsigned int *uv_plane_data_rate)
 {
struct drm_crtc_state *cstate = _cstate->base;
struct drm_atomic_state *state = cstate->state;
@@ -4083,17 +4078,17 @@ skl_get_total_relative_data_rate(struct 
intel_crtc_state *intel_cstate,
enum plane_id plane_id = to_intel_plane(plane)->id;
unsigned int rate;
 
-   /* packed/uv */
+   /* 

[Intel-gfx] [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM

[Vidya Srinivas]

From: Mahesh Kumar 

NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.

v2: Addressed review comments from Shashank Sharma.

v3: Addressed review comments from Shashank Sharma
Changed plane_num to plane_id in skl_compute_plane_wm_params
and skl_compute_plane_wm.
Adding reviewed by tag from Shashank Sharma

Reviewed-by: Shashank Sharma 
Signed-off-by: Mahesh Kumar 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c  | 50 +---
 3 files changed, 44 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8967cc1..590e5f5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1464,6 +1464,7 @@ struct skl_wm_level {
 struct skl_wm_params {
bool x_tiled, y_tiled;
bool rc_surface;
+   bool is_planar;
uint32_t width;
uint8_t cpp;
uint32_t plane_pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f13decc..6402d6d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -594,6 +594,7 @@ struct intel_pipe_wm {
 
 struct skl_plane_wm {
struct skl_wm_level wm[8];
+   struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
bool is_planar;
 };
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3eeb66d..bfe64a9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4422,7 +4422,7 @@ static int
 skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
struct intel_crtc_state *cstate,
const struct intel_plane_state *intel_pstate,
-   struct skl_wm_params *wp)
+   struct skl_wm_params *wp, int plane_id)
 {
struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
const struct drm_plane_state *pstate = _pstate->base;
@@ -4435,6 +4435,12 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
if (!intel_wm_plane_visible(cstate, intel_pstate))
return 0;
 
+   /* only NV12 format has two planes */
+   if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
+   DRM_DEBUG_KMS("Non NV12 format have single plane\n");
+   return -EINVAL;
+   }
+
wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
  fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
  fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
@@ -4442,6 +4448,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private 
*dev_priv,
wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+   wp->is_planar = fb->format->format == DRM_FORMAT_NV12;
 
if (plane->id == PLANE_CURSOR) {
wp->width = intel_pstate->base.crtc_w;
@@ -4454,7 +4461,10 @@ skl_compute_plane_wm_params(const struct 
drm_i915_private *dev_priv,
wp->width = drm_rect_width(_pstate->base.src) >> 16;
}
 
-   wp->cpp = fb->format->cpp[0];
+   if (plane_id == 1 && wp->is_planar)
+   wp->width /= 2;
+
+   wp->cpp = fb->format->cpp[plane_id];
wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
 intel_pstate);
 
@@ -4652,7 +4662,8 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
  struct intel_crtc_state *cstate,
  const struct intel_plane_state *intel_pstate,
  const struct skl_wm_params *wm_params,
- struct skl_plane_wm *wm)
+ struct skl_plane_wm *wm,
+ int plane_id)
 {
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_plane *plane = intel_pstate->base.plane;
@@ -4660,15 +4671,19 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
uint16_t ddb_blocks;
enum pipe pipe = intel_crtc->pipe;
int level, max_level = ilk_wm_max_level(dev_priv);
+   enum plane_id intel_plane_id = intel_plane->id;
int ret;
 
if (WARN_ON(!intel_pstate->base.fb))
return -EINVAL;
 
-   ddb_blocks = skl_ddb_entry_size(>plane[pipe][intel_plane->id]);
+   ddb_blocks = plane_id ?
+skl_ddb_entry_size(>uv_plane[pipe][intel_plane_id]) :
+skl_ddb_entry_size(>plane[pipe][intel_plane_id]);
 

[Intel-gfx] [PATCH 06/16] drm/i915/skl+: pass skl_wm_level struct to wm compute func

[Vidya Srinivas]

From: Mahesh Kumar 

This patch passes skl_wm_level structure itself to watermark
computation function skl_compute_plane_wm function (instead
of its internal parameters). It reduces number of arguments
required to be passed.

v2: Addressed review comments by Shashank Sharma

Reviewed-by: Shashank Sharma 
Signed-off-by: Mahesh Kumar 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_pm.c | 18 +++---
 1 file changed, 7 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bfe64a9..5154ce3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4532,9 +4532,7 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
uint16_t ddb_allocation,
int level,
const struct skl_wm_params *wp,
-   uint16_t *out_blocks, /* out */
-   uint8_t *out_lines, /* out */
-   bool *enabled /* out */)
+   struct skl_wm_level *result /* out */)
 {
const struct drm_plane_state *pstate = _pstate->base;
uint32_t latency = dev_priv->wm.skl_latency[level];
@@ -4548,7 +4546,7 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
 
if (latency == 0 ||
!intel_wm_plane_visible(cstate, intel_pstate)) {
-   *enabled = false;
+   result->plane_en = false;
return 0;
}
 
@@ -4629,7 +4627,7 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
if ((level > 0 && res_lines > 31) ||
res_blocks >= ddb_allocation ||
min_disp_buf_needed >= ddb_allocation) {
-   *enabled = false;
+   result->plane_en = false;
 
/*
 * If there are no valid level 0 watermarks, then we can't
@@ -4649,9 +4647,9 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
}
 
/* The number of lines are ignored for the level 0 watermark. */
-   *out_lines = level ? res_lines : 0;
-   *out_blocks = res_blocks;
-   *enabled = true;
+   result->plane_res_b = res_blocks;
+   result->plane_res_l = res_lines;
+   result->plane_en = true;
 
return 0;
 }
@@ -4691,9 +4689,7 @@ skl_compute_wm_levels(const struct drm_i915_private 
*dev_priv,
   ddb_blocks,
   level,
   wm_params,
-  >plane_res_b,
-  >plane_res_l,
-  >plane_en);
+  result);
if (ret)
return ret;
}
-- 
2.7.4

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[Intel-gfx] [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12

[Vidya Srinivas]

From: Mahesh Kumar 

For YUV 420 Planar formats like NV12,
buffer allocation is done for Y and UV surfaces separately.
For NV12 plane formats, the UV buffer
allocation must be programmed in the Plane Buffer Config register
and the Y buffer allocation must be programmed in the
Plane NV12 Buffer Config register. Both register values
should be verified during verify_wm_state.

v2: Addressed review comments by Maarten.

v3: Addressed review comments by Shashank Sharma.

v4: Adding reviewed by tag from Shashank Sharma

Reviewed-by: Shashank Sharma 
Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/intel_display.c |  2 +-
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c  | 51 +---
 3 files changed, 43 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 1617692..971bd04 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2621,7 +2621,7 @@ static int i9xx_format_to_fourcc(int format)
}
 }
 
-static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
+int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
 {
switch (format) {
case PLANE_CTL_FORMAT_RGB_565:
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 70447c6..f13decc 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1597,6 +1597,7 @@ u32 skl_plane_stride(const struct drm_framebuffer *fb, 
int plane,
 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state);
 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
+int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
 
 /* intel_csr.c */
 void intel_csr_ucode_init(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cf861a9..3eeb66d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3828,6 +3828,44 @@ static void skl_ddb_entry_init_from_hw(struct 
skl_ddb_entry *entry, u32 reg)
entry->end += 1;
 }
 
+static void
+skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
+  const enum pipe pipe,
+  const enum plane_id plane_id,
+  struct skl_ddb_allocation *ddb /* out */)
+{
+   u32 val, val2 = 0;
+   int fourcc, pixel_format;
+
+   /* Cursor doesn't support NV12/planar, so no extra calculation needed */
+   if (plane_id == PLANE_CURSOR) {
+   val = I915_READ(CUR_BUF_CFG(pipe));
+   skl_ddb_entry_init_from_hw(>plane[pipe][plane_id], val);
+   return;
+   }
+
+   val = I915_READ(PLANE_CTL(pipe, plane_id));
+
+   /* No DDB allocated for disabled planes */
+   if (!(val & PLANE_CTL_ENABLE))
+   return;
+
+   pixel_format = val & PLANE_CTL_FORMAT_MASK;
+   fourcc = skl_format_to_fourcc(pixel_format,
+ val & PLANE_CTL_ORDER_RGBX,
+ val & PLANE_CTL_ALPHA_MASK);
+
+   val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
+   val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
+
+   if (fourcc == DRM_FORMAT_NV12) {
+   skl_ddb_entry_init_from_hw(>plane[pipe][plane_id], val2);
+   skl_ddb_entry_init_from_hw(>uv_plane[pipe][plane_id], val);
+   } else {
+   skl_ddb_entry_init_from_hw(>plane[pipe][plane_id], val);
+   }
+}
+
 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
  struct skl_ddb_allocation *ddb /* out */)
 {
@@ -3844,16 +3882,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private 
*dev_priv,
if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
continue;
 
-   for_each_plane_id_on_crtc(crtc, plane_id) {
-   u32 val;
-
-   if (plane_id != PLANE_CURSOR)
-   val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
-   else
-   val = I915_READ(CUR_BUF_CFG(pipe));
-
-   skl_ddb_entry_init_from_hw(>plane[pipe][plane_id], 
val);
-   }
+   for_each_plane_id_on_crtc(crtc, plane_id)
+   skl_ddb_get_hw_plane_state(dev_priv, pipe,
+  plane_id, ddb);
 
intel_display_power_put(dev_priv, power_domain);
}
-- 
2.7.4

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[Intel-gfx] [PATCH 08/16] drm/i915/skl+: nv12 workaround disable WM level 1-7

[Vidya Srinivas]

From: Mahesh Kumar 

Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A)
Hardware sometimes fails to wake memory from pkg C states fetching the
last few lines of planar YUV 420 (NV12) planes. This causes
intermittent underflow and corruption.
WA: Disable package C states or do not enable latency levels 1 through 7
(WM1 - WM7) on NV12 planes.

v2: Addressed review comments by Maarten.

v3: Adding reviewed by tag from Shashank Sharma

Reviewed-by: Shashank Sharma 
Reviewed-by: Maarten Lankhorst 
Signed-off-by: Mahesh Kumar 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_pm.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 77c268f..b575991 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4656,6 +4656,17 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
}
}
 
+   /*
+* Display WA #826 (SKL:ALL, BXT:ALL) & #1059 (CNL:A)
+* disable wm level 1-7 on NV12 planes
+*/
+   if (wp->is_planar && (level >= 1) &&
+   (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
+IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {
+   result->plane_en = false;
+   return 0;
+   }
+
/* The number of lines are ignored for the level 0 watermark. */
result->plane_res_b = res_blocks;
result->plane_res_l = res_lines;
-- 
2.7.4

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[Intel-gfx] [PATCH 14/16] drm/i915: Add NV12 as supported format for sprite plane

[Vidya Srinivas]

From: Chandra Konduru 

This patch adds NV12 to list of supported formats for sprite plane.

v2: Rebased (me)

v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_formats
- Added the 10bpc RGB formats

v4: Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Removed 10bit RGB formats added previously with NV12 series

v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Previous version has 10bit RGB format removed from VLV formats
by mistake. Fixing that in this version.
Removed 10bit RGB formats added previously with NV12 series
for SKL.

v6: Addressed review comments by Ville
Restricting the NV12 to BXT and PIPE A and B

v7: Rebased (me)

v8: Rebased (me)
Restricting NV12 changes to BXT and KBL
Restricting NV12 changes for plane 0 (overlay)

v9: Rebased (me)

v10: Addressed review comments from Maarten.
Adding NV12 to skl_plane_formats itself.

v11: Addressed review comments from Shashank Sharma

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_sprite.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 77a5433..4290a23 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1171,6 +1171,7 @@ static uint32_t skl_plane_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+   DRM_FORMAT_NV12,
 };
 
 static const uint64_t skl_plane_format_modifiers_noccs[] = {
@@ -1369,6 +1370,12 @@ intel_sprite_plane_create(struct drm_i915_private 
*dev_priv,
plane_formats = skl_plane_formats;
num_plane_formats = ARRAY_SIZE(skl_plane_formats);
 
+   if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) &&
+   (plane != 0 || pipe == PIPE_C)) ||
+   ((INTEL_GEN(dev_priv) == 10 ||
+   IS_GEMINILAKE(dev_priv)) && plane != 0))
+   num_plane_formats -= 1;
+
if (skl_plane_has_ccs(dev_priv, pipe, PLANE_SPRITE0 + plane))
modifiers = skl_plane_format_modifiers_ccs;
else
-- 
2.7.4

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[Intel-gfx] [PATCH 11/16] drm/i915: Update format_is_yuv() to include NV12

[Vidya Srinivas]

From: Chandra Konduru 

This patch adds NV12 to format_is_yuv() function
for sprite planes.

v2:
-Use intel_ prefix for format_is_yuv (Ville)

v3: Rebased (me)

v4: Rebased and addressed review comments from Clinton A Taylor.
"static function in intel_sprite.c is not available
to the primary plane functions".
Changed commit message - function modified for
sprite planes.

v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v6: Rebased (me)

v7: Rebased (me)

v8: Rebased (me)

v9: Rebased (me)

v10: Changed intel_format_is_yuv function from
static to non-static. We need to use it later from
other files for check.

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Reviewed-by: Shashank Sharma 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_drv.h| 1 +
 drivers/gpu/drm/i915/intel_sprite.c | 8 
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6402d6d..8d4988b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2034,6 +2034,7 @@ void skl_disable_plane(struct intel_plane *plane, struct 
intel_crtc *crtc);
 bool skl_plane_get_hw_state(struct intel_plane *plane);
 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
   enum pipe pipe, enum plane_id plane_id);
+bool intel_format_is_yuv(uint32_t format);
 
 /* intel_tv.c */
 void intel_tv_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index e098e4b..2c51d8a 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -41,14 +41,14 @@
 #include 
 #include "i915_drv.h"
 
-static bool
-format_is_yuv(uint32_t format)
+bool intel_format_is_yuv(uint32_t format)
 {
switch (format) {
case DRM_FORMAT_YUYV:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_YVYU:
+   case DRM_FORMAT_NV12:
return true;
default:
return false;
@@ -352,7 +352,7 @@ chv_update_csc(struct intel_plane *plane, uint32_t format)
enum plane_id plane_id = plane->id;
 
/* Seems RGB data bypasses the CSC always */
-   if (!format_is_yuv(format))
+   if (!intel_format_is_yuv(format))
return;
 
/*
@@ -979,7 +979,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
src_y = src->y1 >> 16;
src_h = drm_rect_height(src) >> 16;
 
-   if (format_is_yuv(fb->format->format)) {
+   if (intel_format_is_yuv(fb->format->format)) {
src_x &= ~1;
src_w &= ~1;
 
-- 
2.7.4

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[Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane

[Vidya Srinivas]

From: Chandra Konduru 

This patch adds NV12 to list of supported formats for
primary plane

v2: Rebased (Chandra Konduru)

v3: Rebased (me)

v4: Review comments by Ville addressed
Removed the skl_primary_formats_with_nv12 and
added NV12 case in existing skl_primary_formats

v5: Rebased (me)

v6: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v7: Review comments by Ville addressed
Restricting the NV12 for BXT and on PIPE A and B
Rebased (me)

v8: Rebased (me)
Modified restricting the NV12 support for both BXT and KBL.

v9: Rebased (me)

v10: Addressed review comments from Maarten.
Adding NV12 inside skl_primary_formats itself.

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 
Reviewed-by: Shashank Sharma 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_display.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index ac8279a..6f43d72 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+   DRM_FORMAT_NV12,
 };
 
 static const uint64_t skl_format_modifiers_noccs[] = {
@@ -13255,6 +13256,10 @@ intel_primary_plane_create(struct drm_i915_private 
*dev_priv, enum pipe pipe)
intel_primary_formats = skl_primary_formats;
num_formats = ARRAY_SIZE(skl_primary_formats);
 
+   if ((INTEL_GEN(dev_priv) == 9 && (pipe == PIPE_C)) &&
+   !IS_GEMINILAKE(dev_priv))
+   num_formats -= 1;
+
if (skl_plane_has_ccs(dev_priv, pipe, PLANE_PRIMARY))
modifiers = skl_format_modifiers_ccs;
else
-- 
2.7.4

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[Intel-gfx] [PATCH 01/16] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

[Vidya Srinivas]

From: Mahesh Kumar 

skl_wm_values struct contains values of pipe/plane DDB only.
so rename it for better readability of code. Similarly
skl_copy_wm_for_pipe copies DDB values.

s/skl_wm_values/skl_ddb_values
s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe

Changes since V1:
 - also change name of skl_copy_wm_for_pipe

Reviewed-by: Maarten Lankhorst 
Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/i915_drv.h  |  4 ++--
 drivers/gpu/drm/i915/intel_drv.h |  2 +-
 drivers/gpu/drm/i915/intel_pm.c  | 14 +++---
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 90eca42..9377bd9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1448,7 +1448,7 @@ struct skl_ddb_allocation {
struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
 };
 
-struct skl_wm_values {
+struct skl_ddb_values {
unsigned dirty_pipes;
struct skl_ddb_allocation ddb;
 };
@@ -2144,7 +2144,7 @@ struct drm_i915_private {
/* current hardware state */
union {
struct ilk_wm_values hw;
-   struct skl_wm_values skl_hw;
+   struct skl_ddb_values skl_hw;
struct vlv_wm_values vlv;
struct g4x_wm_values g4x;
};
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 898064e..e74efb4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -480,7 +480,7 @@ struct intel_atomic_state {
bool skip_intermediate_wm;
 
/* Gen9+ only */
-   struct skl_wm_values wm_results;
+   struct skl_ddb_values wm_results;
 
struct i915_sw_fence commit_ready;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7e15b26..6fec748 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5044,8 +5044,8 @@ skl_compute_ddb(struct drm_atomic_state *state)
 }
 
 static void
-skl_copy_wm_for_pipe(struct skl_wm_values *dst,
-struct skl_wm_values *src,
+skl_copy_ddb_for_pipe(struct skl_ddb_values *dst,
+struct skl_ddb_values *src,
 enum pipe pipe)
 {
memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
@@ -5097,7 +5097,7 @@ skl_compute_wm(struct drm_atomic_state *state)
struct drm_crtc *crtc;
struct drm_crtc_state *cstate;
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-   struct skl_wm_values *results = _state->wm_results;
+   struct skl_ddb_values *results = _state->wm_results;
struct drm_device *dev = state->dev;
struct skl_pipe_wm *pipe_wm;
bool changed = false;
@@ -5199,8 +5199,8 @@ static void skl_initial_wm(struct intel_atomic_state 
*state,
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_device *dev = intel_crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
-   struct skl_wm_values *results = >wm_results;
-   struct skl_wm_values *hw_vals = _priv->wm.skl_hw;
+   struct skl_ddb_values *results = >wm_results;
+   struct skl_ddb_values *hw_vals = _priv->wm.skl_hw;
enum pipe pipe = intel_crtc->pipe;
 
if ((results->dirty_pipes & drm_crtc_mask(_crtc->base)) == 0)
@@ -5211,7 +5211,7 @@ static void skl_initial_wm(struct intel_atomic_state 
*state,
if (cstate->base.active_changed)
skl_atomic_update_crtc_wm(state, cstate);
 
-   skl_copy_wm_for_pipe(hw_vals, results, pipe);
+   skl_copy_ddb_for_pipe(hw_vals, results, pipe);
 
mutex_unlock(_priv->wm.wm_mutex);
 }
@@ -5343,7 +5343,7 @@ void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
 void skl_wm_get_hw_state(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = to_i915(dev);
-   struct skl_wm_values *hw = _priv->wm.skl_hw;
+   struct skl_ddb_values *hw = _priv->wm.skl_hw;
struct skl_ddb_allocation *ddb = _priv->wm.skl_hw.ddb;
struct drm_crtc *crtc;
struct intel_crtc *intel_crtc;
-- 
2.7.4

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[Intel-gfx] [PATCH 03/16] drm/i915/skl+: add NV12 in skl_format_to_fourcc

[Vidya Srinivas]

From: Mahesh Kumar 

Add support of recognizing DRM_FORMAT_NV12 from plane_format
register value.

Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/intel_display.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 30e38cb..1617692 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2626,6 +2626,8 @@ static int skl_format_to_fourcc(int format, bool 
rgb_order, bool alpha)
switch (format) {
case PLANE_CTL_FORMAT_RGB_565:
return DRM_FORMAT_RGB565;
+   case PLANE_CTL_FORMAT_NV12:
+   return DRM_FORMAT_NV12;
default:
case PLANE_CTL_FORMAT_XRGB_:
if (rgb_order) {
-- 
2.7.4

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[Intel-gfx] ✓ Fi.CI.IGT: success for Per-client engine stats

[Patchwork]

== Series Details ==

Series: Per-client engine stats
URL   : https://patchwork.freedesktop.org/series/38281/
State : success

== Summary ==

Test kms_flip:
Subgroup plain-flip-fb-recreate:
pass   -> FAIL   (shard-hsw) fdo#100368
Subgroup dpms-vs-vblank-race-interruptible:
pass   -> FAIL   (shard-hsw) fdo#103060
Test kms_vblank:
Subgroup crtc-id:
skip   -> PASS   (shard-snb)
Subgroup pipe-a-ts-continuation-modeset:
skip   -> PASS   (shard-snb)
Test gem_softpin:
Subgroup noreloc-s3:
incomplete -> PASS   (shard-hsw) fdo#103540
Test kms_cursor_legacy:
Subgroup flip-vs-cursor-crc-atomic:
pass   -> FAIL   (shard-apl) fdo#102670
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-pwrite:
pass   -> FAIL   (shard-apl) fdo#101623

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623

shard-apltotal:3346 pass:1735 dwarn:1   dfail:0   fail:23  skip:1586 
time:12696s
shard-hswtotal:3427 pass:1756 dwarn:1   dfail:0   fail:13  skip:1656 
time:14314s
shard-snbtotal:3427 pass:1349 dwarn:1   dfail:0   fail:10  skip:2067 
time:7284s
Blacklisted hosts:
shard-kbltotal:3409 pass:1891 dwarn:1   dfail:0   fail:23  skip:1493 
time:10485s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8028/shards.html
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[Intel-gfx] [PULL] drm-intel-fixes

[Rodrigo Vivi]

Hi Dave,

Here goes drm-intel-fixes-2018-02-14-1:

There are important fixes for VLV with MIPI/DSI panels,
2 clean-up patches needed for this MIPI/DSI fix,
and many fixes for GEM including fixes for Perf OA and PMU,
and fixes on scheduler and preemption.

This also includes GVT fixes: "This has one to fix GTT mmio 8b
access from guest and two simple ones for mmio switch and typo fix"

Thanks,
Rodrigo.

The following changes since commit 7928b2cbe55b2a410a0f5c1f154610059c57b1b2:

  Linux 4.16-rc1 (2018-02-11 15:04:29 -0800)

are available in the git repository at:

  git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2018-02-14-1

for you to fetch changes up to ee622fe757f6de612dad0f01805eea815a5b3025:

  drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT sequence 
v3 (2018-02-14 11:43:31 -0800)


There are important fixes for VLV with MIPI/DSI panels,
2 clean-up patches needed for this MIPI/DSI fix,
and many fixes for GEM including fixes for Perf OA and PMU,
and fixes on scheduler and preemption.

This also includes GVT fixes: "This has one to fix GTT mmio 8b
access from guest and two simple ones for mmio switch and typo fix"


Chris Wilson (7):
  drm/i915/perf: Fix compiler warning for string truncation
  drm/i915/perf: Fix compiler warning for string truncation
  drm/i915: Avoid truncation before clamping userspace's priority value
  drm/i915: Don't wake the device up to check if the engine is asleep
  drm/i915/breadcrumbs: Ignore unsubmitted signalers
  drm/i915: Lock out execlist tasklet while peeking inside for busy-stats
  drm/i915/pmu: Fix building without CONFIG_PM

Hans de Goede (4):
  drm/i915/vlv: Add cdclk workaround for DSI
  drm/i915: Add intel_bios_cleanup() function
  drm/i915: Free memdup-ed DSI VBT data structures on driver_unload
  drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT 
sequence v3

Rodrigo Vivi (1):
  Merge tag 'gvt-fixes-2018-02-14' of https://github.com/intel/gvt-linux 
into drm-intel-fixes

Tina Zhang (1):
  drm/i915/gvt: Support BAR0 8-byte reads/writes

Tvrtko Ursulin (2):
  drm/i915/pmu: Fix PMU enable vs execlists tasklet race
  drm/i915/pmu: Fix sleep under atomic in RC6 readout

Weinan Li (2):
  drm/i915/gvt: add 0xe4f0 into gen9 render list
  drm/i915/gvt: fix one typo of render_mmio trace

 drivers/gpu/drm/i915/gvt/kvmgt.c |  51 ++-
 drivers/gpu/drm/i915/gvt/mmio_context.c  |   1 +
 drivers/gpu/drm/i915/gvt/trace.h |   2 +-
 drivers/gpu/drm/i915/i915_drv.c  |  14 +-
 drivers/gpu/drm/i915/i915_drv.h  |   2 +
 drivers/gpu/drm/i915/i915_gem_context.c  |   2 +-
 drivers/gpu/drm/i915/i915_oa_cflgt3.c|   4 +-
 drivers/gpu/drm/i915/i915_oa_cnl.c   |   4 +-
 drivers/gpu/drm/i915/i915_pmu.c  | 231 +++
 drivers/gpu/drm/i915/i915_pmu.h  |   6 +
 drivers/gpu/drm/i915/intel_bios.c| 105 ++
 drivers/gpu/drm/i915/intel_breadcrumbs.c |  29 ++--
 drivers/gpu/drm/i915/intel_cdclk.c   |   8 ++
 drivers/gpu/drm/i915/intel_engine_cs.c   |  24 ++--
 drivers/gpu/drm/i915/intel_ringbuffer.h  |  14 --
 15 files changed, 346 insertions(+), 151 deletions(-)
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/audio: fix check for av_enc_map overflow

[Patchwork]

== Series Details ==

Series: drm/i915/audio: fix check for av_enc_map overflow
URL   : https://patchwork.freedesktop.org/series/38271/
State : success

== Summary ==

Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank-interruptible:
pass   -> FAIL   (shard-hsw) fdo#102887
Test kms_sysfs_edid_timing:
pass   -> WARN   (shard-apl) fdo#100047
Test perf:
Subgroup buffer-fill:
pass   -> FAIL   (shard-apl) fdo#103755
Subgroup oa-exponents:
pass   -> FAIL   (shard-hsw) fdo#102254 +1
Test gem_softpin:
Subgroup noreloc-s3:
incomplete -> PASS   (shard-hsw) fdo#103540
Test kms_vblank:
Subgroup crtc-id:
skip   -> PASS   (shard-snb)
Subgroup pipe-a-ts-continuation-modeset:
skip   -> PASS   (shard-snb)

fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540

shard-apltotal:3346 pass:1736 dwarn:1   dfail:0   fail:21  skip:1586 
time:13984s
shard-hswtotal:3427 pass:1756 dwarn:1   dfail:0   fail:13  skip:1656 
time:14646s
shard-snbtotal:3427 pass:1349 dwarn:1   dfail:0   fail:10  skip:2067 
time:7629s
Blacklisted hosts:
shard-kbltotal:3427 pass:1908 dwarn:1   dfail:0   fail:20  skip:1498 
time:11133s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8027/shards.html
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[Intel-gfx] ✗ Fi.CI.IGT: failure for i915: Re-use DEFINE_SHOW_ATTRIBUTE() macro

[Patchwork]

== Series Details ==

Series: i915: Re-use DEFINE_SHOW_ATTRIBUTE() macro
URL   : https://patchwork.freedesktop.org/series/38263/
State : failure

== Summary ==

Test gem_softpin:
Subgroup noreloc-s3:
pass   -> SKIP   (shard-snb) fdo#103375 +1
incomplete -> PASS   (shard-hsw) fdo#103540 +1
Test kms_rotation_crc:
Subgroup cursor-rotation-180:
pass   -> FAIL   (shard-hsw) fdo#102614
Test perf:
Subgroup oa-exponents:
fail   -> PASS   (shard-apl) fdo#102254
Test kms_vblank:
Subgroup crtc-id:
skip   -> PASS   (shard-snb)
Subgroup pipe-a-ts-continuation-modeset:
skip   -> PASS   (shard-snb)
Test kms_cursor_crc:
Subgroup cursor-256x256-dpms:
pass   -> FAIL   (shard-apl)

fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254

shard-apltotal:3346 pass:1737 dwarn:1   dfail:0   fail:21  skip:1586 
time:14017s
shard-hswtotal:3427 pass:1755 dwarn:1   dfail:0   fail:14  skip:1656 
time:14734s
shard-snbtotal:3427 pass:1348 dwarn:1   dfail:0   fail:10  skip:2068 
time:7614s
Blacklisted hosts:
shard-kbltotal:3427 pass:1903 dwarn:1   dfail:0   fail:22  skip:1501 
time:11120s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8026/shards.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Clean up ancient doc comments for i915_ioc32.c (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Clean up ancient doc comments for i915_ioc32.c (rev3)
URL   : https://patchwork.freedesktop.org/series/38261/
State : success

== Summary ==

Test kms_vblank:
Subgroup crtc-id:
skip   -> PASS   (shard-snb)
Subgroup pipe-a-ts-continuation-modeset:
skip   -> PASS   (shard-snb)
Test gem_softpin:
Subgroup noreloc-s3:
pass   -> SKIP   (shard-snb) fdo#103375
incomplete -> PASS   (shard-hsw) fdo#103540
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank-interruptible:
pass   -> FAIL   (shard-hsw) fdo#102887
Subgroup modeset-vs-vblank-race:
pass   -> FAIL   (shard-hsw) fdo#103060
Subgroup 2x-flip-vs-absolute-wf_vblank-interruptible:
pass   -> FAIL   (shard-hsw) fdo#100368

fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368

shard-apltotal:3346 pass:1737 dwarn:1   dfail:0   fail:21  skip:1586 
time:14026s
shard-hswtotal:3427 pass:1755 dwarn:1   dfail:0   fail:14  skip:1656 
time:14591s
shard-snbtotal:3427 pass:1348 dwarn:1   dfail:0   fail:10  skip:2068 
time:7623s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8025/shards.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/psr2: Fix max resolution supported. (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/psr2: Fix max resolution supported. 
(rev2)
URL   : https://patchwork.freedesktop.org/series/38200/
State : success

== Summary ==

Test gem_softpin:
Subgroup noreloc-s3:
pass   -> SKIP   (shard-snb) fdo#103375
incomplete -> PASS   (shard-hsw) fdo#103540
Test kms_frontbuffer_tracking:
Subgroup fbc-rgb101010-draw-mmap-wc:
pass   -> SKIP   (shard-snb) fdo#103167
Test perf:
Subgroup polling:
pass   -> FAIL   (shard-hsw) fdo#102252
Subgroup oa-exponents:
fail   -> PASS   (shard-apl) fdo#102254
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912
Test kms_vblank:
Subgroup crtc-id:
skip   -> PASS   (shard-snb)
Subgroup pipe-a-ts-continuation-modeset:
skip   -> PASS   (shard-snb)

fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-apltotal:3346 pass:1738 dwarn:1   dfail:0   fail:20  skip:1586 
time:14080s
shard-hswtotal:3427 pass:1758 dwarn:1   dfail:0   fail:11  skip:1656 
time:14677s
shard-snbtotal:3427 pass:1347 dwarn:1   dfail:0   fail:10  skip:2069 
time:7539s
Blacklisted hosts:
shard-kbltotal:3427 pass:1906 dwarn:1   dfail:0   fail:21  skip:1499 
time:4s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8024/shards.html
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[Intel-gfx] ✗ Fi.CI.BAT: failure for ICL GEM enabling (v2) (rev4)

[Patchwork]

== Series Details ==

Series: ICL GEM enabling (v2) (rev4)
URL   : https://patchwork.freedesktop.org/series/38174/
State : failure

== Summary ==

Applying: drm/i915/icl: Add the ICL PCI IDs
Applying: drm/i915/icl: add icelake_init_clock_gating()
Applying: drm/i915/icl: Show interrupt registers in debugfs
Applying: drm/i915/icl: Prepare for more rings
Applying: drm/i915/icl: Interrupt handling
Applying: drm/i915/icl: Ringbuffer interrupt handling
Applying: drm/i915/icl: Correctly initialize the Gen11 engines
Applying: drm/i915/icl: new context descriptor support
Applying: drm/i915/icl: Enhanced execution list support
Applying: drm/i915/icl: Add Indirect Context Offset for Gen11
Applying: drm/i915/icl: Gen11 forcewake support
Applying: drm/i915/icl: Check for fused-off VDBOX and VEBOX instances
Applying: drm/i915/icl: Enable the extra video decode and enhancement boxes for 
Icelake 11
Applying: drm/i915/icl: Update subslice define for ICL 11
Applying: drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection
Applying: drm/i915/icl: Add reset control register changes
Applying: drm/i915/icl: Add configuring MOCS in new Icelake engines
Applying: drm/i915/icl: Split out the servicing of the Selector and Shared IIR 
registers
error: Failed to merge in the changes.
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/i915_irq.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_irq.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_irq.c
Patch failed at 0018 drm/i915/icl: Split out the servicing of the Selector and 
Shared IIR registers
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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[Intel-gfx] [PATCH v5] drm/i915/icl: new context descriptor support

[Daniele Ceraolo Spurio]

Starting from Gen11 the context descriptor format has been updated in
the HW. The hw_id field has been considerably reduced in size and engine
class and instance fields have been added.

There is a slight name clashing issue because the field that we call
hw_id is actually called SW Context ID in the specs for Gen11+.

With the current size of the hw_id field we can have a maximum of 2k
contexts at any time, but we could use the sw_counter field (which is sw
defined) to increase that because the HW requirement is that
engine_id + sw id + sw_counter is a unique number.
GuC uses a similar method to support more contexts but does its tracking
at lrc level. To avoid doing an implementation that will need to be
reworked once GuC support lands, defer it for now and mark it as TODO.

v2: rebased, add documentation, fix GEN11_ENGINE_INSTANCE_SHIFT
v3: rebased, bring back lost code from i915_gem_context.c
v4: make TODO comment more generic
v5: be consistent with bit ordering, add extra checks (Chris)

Cc: Oscar Mateo 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
Signed-off-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_gem_context.c | 11 --
 drivers/gpu/drm/i915/i915_reg.h |  6 ++
 drivers/gpu/drm/i915/intel_engine_cs.c  |  3 +++
 drivers/gpu/drm/i915/intel_lrc.c| 36 +++--
 5 files changed, 53 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7db3557b945c..acaa63f8237d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2093,6 +2093,7 @@ struct drm_i915_private {
 */
struct ida hw_ida;
 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
+#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
} contexts;
 
u32 fdi_rx_config;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 3d75f484f6e5..45b0b78aca3f 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -211,9 +211,15 @@ static void context_close(struct i915_gem_context *ctx)
 static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
 {
int ret;
+   unsigned int max;
+
+   if (INTEL_GEN(dev_priv) >= 11)
+   max = GEN11_MAX_CONTEXT_HW_ID;
+   else
+   max = MAX_CONTEXT_HW_ID;
 
ret = ida_simple_get(_priv->contexts.hw_ida,
-0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
+0, max, GFP_KERNEL);
if (ret < 0) {
/* Contexts are only released when no longer active.
 * Flush any pending retires to hopefully release some
@@ -221,7 +227,7 @@ static int assign_hw_id(struct drm_i915_private *dev_priv, 
unsigned *out)
 */
i915_gem_retire_requests(dev_priv);
ret = ida_simple_get(_priv->contexts.hw_ida,
-0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
+0, max, GFP_KERNEL);
if (ret < 0)
return ret;
}
@@ -463,6 +469,7 @@ int i915_gem_contexts_init(struct drm_i915_private 
*dev_priv)
 
/* Using the simple ida interface, the max is limited by sizeof(int) */
BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX);
+   BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > INT_MAX);
ida_init(_priv->contexts.hw_ida);
 
/* lowest priority; idle task */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e9c79b560823..789ec1e16058 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3869,6 +3869,12 @@ enum {
 
 #define GEN8_CTX_ID_SHIFT 32
 #define GEN8_CTX_ID_WIDTH 21
+#define GEN11_SW_CTX_ID_SHIFT 37
+#define GEN11_SW_CTX_ID_WIDTH 11
+#define GEN11_ENGINE_CLASS_SHIFT 61
+#define GEN11_ENGINE_CLASS_WIDTH 3
+#define GEN11_ENGINE_INSTANCE_SHIFT 48
+#define GEN11_ENGINE_INSTANCE_WIDTH 6
 
 #define CHV_CLK_CTL1   _MMIO(0x101100)
 #define VLV_CLK_CTL2   _MMIO(0x101104)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 0ad9184eba97..c21903bf0fd8 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -210,6 +210,9 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
GEM_BUG_ON(info->class >= ARRAY_SIZE(intel_engine_classes));
class_info = _engine_classes[info->class];
 
+   BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
+   BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
+
if (GEM_WARN_ON(info->class > MAX_ENGINE_CLASS))
return -EINVAL;
 
diff 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Remove alpha_support protection (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: Remove alpha_support protection (rev2)
URL   : https://patchwork.freedesktop.org/series/38264/
State : success

== Summary ==

Series 38264v2 drm/i915/cnl: Remove alpha_support protection
https://patchwork.freedesktop.org/api/1.0/series/38264/revisions/2/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:420s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:427s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:373s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:487s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:289s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:486s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:482s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:469s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:457s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:577s
fi-cnl-y3total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:567s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:417s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:282s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:511s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:391s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:410s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:450s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:416s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:456s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:497s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:501s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:590s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:432s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:506s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:526s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:496s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:490s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:413s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:431s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:395s
Blacklisted hosts:
fi-glk-dsi   total:117  pass:105  dwarn:0   dfail:0   fail:0   skip:12 
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:453s

c552bd1bdbff57717814c72748f1351d9b2019d5 drm-tip: 2018y-02m-14d-20h-59m-41s UTC 
integration manifest
41fbdfe6096f drm/i915/cnl: Remove alpha_support protection

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8034/issues.html
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: Sync PCI ID with Spec.

[James Ausmus]

On Wed, Feb 07, 2018 at 11:32:19PM -0800, Rodrigo Vivi wrote:
> Add one missing PCI ID and sort them in a way
> that gets easier to review and compare against spec's
> table.
> 
> When trying to sync libdrm and mesa id list with kernel
> and spec I noticed something was wrong and we were missing
> a pci id. So to make our lives easier when checking against
> spec let's simplify and sort like spec does.
> 
> BSpec: 13621
> 
> Cc: Lucas De Marchi 
> Cc: James Ausmus 
> Signed-off-by: Rodrigo Vivi 

Matches BSpec.

Reviewed-by: James Ausmus 

> ---
>  include/drm/i915_pciids.h | 15 ---
>  1 file changed, 8 insertions(+), 7 deletions(-)
> 
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 9e1fe6634424..0b2ba46fa00b 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -416,18 +416,19 @@
>  
>  /* CNL */
>  #define INTEL_CNL_IDS(info) \
> - INTEL_VGA_DEVICE(0x5A52, info), \
> - INTEL_VGA_DEVICE(0x5A5A, info), \
> - INTEL_VGA_DEVICE(0x5A42, info), \
> - INTEL_VGA_DEVICE(0x5A4A, info), \
>   INTEL_VGA_DEVICE(0x5A51, info), \
>   INTEL_VGA_DEVICE(0x5A59, info), \
>   INTEL_VGA_DEVICE(0x5A41, info), \
>   INTEL_VGA_DEVICE(0x5A49, info), \
> - INTEL_VGA_DEVICE(0x5A71, info), \
> - INTEL_VGA_DEVICE(0x5A79, info), \
> + INTEL_VGA_DEVICE(0x5A52, info), \
> + INTEL_VGA_DEVICE(0x5A5A, info), \
> + INTEL_VGA_DEVICE(0x5A42, info), \
> + INTEL_VGA_DEVICE(0x5A4A, info), \
> + INTEL_VGA_DEVICE(0x5A50, info), \
> + INTEL_VGA_DEVICE(0x5A40, info), \
>   INTEL_VGA_DEVICE(0x5A54, info), \
>   INTEL_VGA_DEVICE(0x5A5C, info), \
> - INTEL_VGA_DEVICE(0x5A44, info)
> + INTEL_VGA_DEVICE(0x5A44, info), \
> + INTEL_VGA_DEVICE(0x5A4C, info)
>  
>  #endif /* _I915_PCIIDS_H */
> -- 
> 2.13.6
> 
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[Intel-gfx] ✓ Fi.CI.IGT: success for i915: Re-use DEFINE_SHOW_ATTRIBUTE() macro

[Patchwork]

== Series Details ==

Series: i915: Re-use DEFINE_SHOW_ATTRIBUTE() macro
URL   : https://patchwork.freedesktop.org/series/38263/
State : success

== Summary ==

Test drv_hangman:
Subgroup error-state-capture-blt:
pass   -> DMESG-WARN (shard-snb) fdo#104058
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-pri-indfb-draw-mmap-gtt:
pass   -> FAIL   (shard-snb) fdo#101623
Test gem_softpin:
Subgroup noreloc-s3:
pass   -> SKIP   (shard-snb) fdo#103375
incomplete -> PASS   (shard-hsw) fdo#103540
Test perf:
Subgroup oa-exponents:
fail   -> PASS   (shard-apl) fdo#102254
Test kms_vblank:
Subgroup crtc-id:
skip   -> PASS   (shard-snb)
Subgroup pipe-a-ts-continuation-modeset:
skip   -> PASS   (shard-snb)

fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254

shard-apltotal:3346 pass:1738 dwarn:1   dfail:0   fail:20  skip:1586 
time:13993s
shard-hswtotal:3427 pass:1758 dwarn:1   dfail:0   fail:11  skip:1656 
time:14639s
shard-snbtotal:3427 pass:1346 dwarn:2   dfail:0   fail:11  skip:2068 
time:7669s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8022/shards.html
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[Intel-gfx] ✗ Fi.CI.BAT: failure for tests/gem_exec_fence: test that in-fence is not overwritten

[Patchwork]

== Series Details ==

Series: tests/gem_exec_fence: test that in-fence is not overwritten
URL   : https://patchwork.freedesktop.org/series/38283/
State : failure

== Summary ==

Applying: tests/gem_exec_fence: test that in-fence is not overwritten
Using index info to reconstruct a base tree...
M   tests/gem_exec_fence.c
Falling back to patching base and 3-way merge...
Auto-merging tests/gem_exec_fence.c
CONFLICT (content): Merge conflict in tests/gem_exec_fence.c
Patch failed at 0001 tests/gem_exec_fence: test that in-fence is not overwritten
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Track GT interrupt handling using the master iir

[Patchwork]

== Series Details ==

Series: drm/i915: Track GT interrupt handling using the master iir
URL   : https://patchwork.freedesktop.org/series/38297/
State : success

== Summary ==

Series 38297v1 drm/i915: Track GT interrupt handling using the master iir
https://patchwork.freedesktop.org/api/1.0/series/38297/revisions/1/mbox/

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:427s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:424s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:382s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:485s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:286s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:483s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:484s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:468s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:462s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:568s
fi-cnl-y3total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:575s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:416s
fi-gdg-551   total:288  pass:180  dwarn:0   dfail:0   fail:0   skip:108 
time:283s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:510s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:389s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:411s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:463s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:413s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:454s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:491s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:502s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:600s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:429s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:507s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:524s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:485s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:476s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:420s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:430s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:402s
Blacklisted hosts:
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:469s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:451s

c552bd1bdbff57717814c72748f1351d9b2019d5 drm-tip: 2018y-02m-14d-20h-59m-41s UTC 
integration manifest
48db85eb1d27 drm/i915: Track GT interrupt handling using the master iir

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8033/issues.html
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Re: [Intel-gfx] [PATCH 3/4] drm/i915: Store platform_mask inside the static device info

[Rodrigo Vivi]

Chris Wilson  writes:

> Rather than deriving the platform_mask from the
> intel_device_static_info->platform at runtime, prefill it in the static
> data.
>
>  baseline.ko drivers/gpu/drm/i915/i915.ko
> add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-20 (-20)
> Function old new   delta
> i915_driver_load50275007 -20
> Total: Before=1331200, After=1331180, chg -0.00%
>
> Signed-off-by: Chris Wilson 
> ---
>  drivers/gpu/drm/i915/i915_drv.c |  2 --
>  drivers/gpu/drm/i915/i915_pci.c | 69 
> ++---
>  2 files changed, 37 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 90f4adbbff28..a81be8506797 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -899,8 +899,6 @@ static int i915_driver_init_early(struct drm_i915_private 
> *dev_priv,
>  
>   BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
>sizeof(device_info->platform_mask) * BITS_PER_BYTE);
> - device_info->platform_mask = BIT(device_info->platform);
> -
>   BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * 
> BITS_PER_BYTE);
>   spin_lock_init(_priv->irq_lock);
>   spin_lock_init(_priv->gpu_error.lock);
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 364d3b41f816..a10404686710 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -30,6 +30,7 @@
>  #include "i915_selftest.h"
>  
>  #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
> +#define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
>  
>  #define GEN_DEFAULT_PIPEOFFSETS \
>   .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
> @@ -79,19 +80,20 @@
>  
>  static const struct intel_device_info intel_i830_info = {
>   GEN2_FEATURES,
> - .platform = INTEL_I830,
> + PLATFORM(INTEL_I830),
>   .is_mobile = 1, .cursor_needs_physical = 1,
>   .num_pipes = 2, /* legal, last one wins */
>  };
>  
>  static const struct intel_device_info intel_i845g_info = {
>   GEN2_FEATURES,
> - .platform = INTEL_I845G,
> + PLATFORM(INTEL_I845G),
>  };
>  
>  static const struct intel_device_info intel_i85x_info = {
>   GEN2_FEATURES,
> - .platform = INTEL_I85X, .is_mobile = 1,
> + PLATFORM(INTEL_I85X),
> + .is_mobile = 1,
>   .num_pipes = 2, /* legal, last one wins */
>   .cursor_needs_physical = 1,
>   .has_fbc = 1,
> @@ -99,7 +101,7 @@ static const struct intel_device_info intel_i85x_info = {
>  
>  static const struct intel_device_info intel_i865g_info = {
>   GEN2_FEATURES,
> - .platform = INTEL_I865G,
> + PLATFORM(INTEL_I865G),
>  };
>  
>  #define GEN3_FEATURES \
> @@ -114,7 +116,8 @@ static const struct intel_device_info intel_i865g_info = {
>  
>  static const struct intel_device_info intel_i915g_info = {
>   GEN3_FEATURES,
> - .platform = INTEL_I915G, .cursor_needs_physical = 1,
> + PLATFORM(INTEL_I915G),
> + .cursor_needs_physical = 1,
>   .has_overlay = 1, .overlay_needs_physical = 1,
>   .hws_needs_physical = 1,
>   .unfenced_needs_alignment = 1,
> @@ -122,7 +125,7 @@ static const struct intel_device_info intel_i915g_info = {
>  
>  static const struct intel_device_info intel_i915gm_info = {
>   GEN3_FEATURES,
> - .platform = INTEL_I915GM,
> + PLATFORM(INTEL_I915GM),
>   .is_mobile = 1,
>   .cursor_needs_physical = 1,
>   .has_overlay = 1, .overlay_needs_physical = 1,
> @@ -134,7 +137,7 @@ static const struct intel_device_info intel_i915gm_info = 
> {
>  
>  static const struct intel_device_info intel_i945g_info = {
>   GEN3_FEATURES,
> - .platform = INTEL_I945G,
> + PLATFORM(INTEL_I945G),
>   .has_hotplug = 1, .cursor_needs_physical = 1,
>   .has_overlay = 1, .overlay_needs_physical = 1,
>   .hws_needs_physical = 1,
> @@ -143,7 +146,8 @@ static const struct intel_device_info intel_i945g_info = {
>  
>  static const struct intel_device_info intel_i945gm_info = {
>   GEN3_FEATURES,
> - .platform = INTEL_I945GM, .is_mobile = 1,
> + PLATFORM(INTEL_I945GM),
> + .is_mobile = 1,
>   .has_hotplug = 1, .cursor_needs_physical = 1,
>   .has_overlay = 1, .overlay_needs_physical = 1,
>   .supports_tv = 1,
> @@ -154,14 +158,15 @@ static const struct intel_device_info intel_i945gm_info 
> = {
>  
>  static const struct intel_device_info intel_g33_info = {
>   GEN3_FEATURES,
> - .platform = INTEL_G33,
> + PLATFORM(INTEL_G33),
>   .has_hotplug = 1,
>   .has_overlay = 1,
>  };
>  
>  static const struct intel_device_info intel_pineview_info = {
>   GEN3_FEATURES,
> - .platform = INTEL_PINEVIEW, .is_mobile = 1,
> + PLATFORM(INTEL_PINEVIEW),
> + .is_mobile = 1,
>   .has_hotplug = 1,
>   .has_overlay = 1,
>  };
> @@ -179,7 

Re: [Intel-gfx] [PATCH 2/4] drm/i915: Always define GEN as part of GENx_FEATURES

[Rodrigo Vivi]

Chris Wilson  writes:

> Be consistent and define the device's GEN as part of the GENx_FEATURE.
> It will be overridden by the next gen upon inheriting, as per usual.
>
> Signed-off-by: Chris Wilson 

Reviewed-by: Rodrigo Vivi 

> ---
>  drivers/gpu/drm/i915/i915_pci.c | 8 +++-
>  1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 3b4516d7f9a4..364d3b41f816 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -383,6 +383,7 @@ static const struct intel_device_info 
> intel_haswell_gt3_info = {
>  
>  #define GEN8_FEATURES \
>   G75_FEATURES, \
> + GEN(8), \
>   BDW_COLORS, \
>   .page_sizes = I915_GTT_PAGE_SIZE_4K | \
> I915_GTT_PAGE_SIZE_2M, \
> @@ -393,7 +394,6 @@ static const struct intel_device_info 
> intel_haswell_gt3_info = {
>  
>  #define BDW_PLATFORM \
>   GEN8_FEATURES, \
> - GEN(8), \
>   .platform = INTEL_BROADWELL
>  
>  static const struct intel_device_info intel_broadwell_gt1_info = {
> @@ -452,6 +452,7 @@ static const struct intel_device_info 
> intel_cherryview_info = {
>  
>  #define GEN9_FEATURES \
>   GEN8_FEATURES, \
> + GEN(9), \
>   GEN9_DEFAULT_PAGE_SIZES, \
>   .has_logical_ring_preemption = 1, \
>   .has_csr = 1, \
> @@ -461,7 +462,6 @@ static const struct intel_device_info 
> intel_cherryview_info = {
>  
>  #define SKL_PLATFORM \
>   GEN9_FEATURES, \
> - GEN(9), \
>   .platform = INTEL_SKYLAKE
>  
>  static const struct intel_device_info intel_skylake_gt1_info = {
> @@ -535,7 +535,6 @@ static const struct intel_device_info 
> intel_geminilake_info = {
>  
>  #define KBL_PLATFORM \
>   GEN9_FEATURES, \
> - GEN(9),  \
>   .platform = INTEL_KABYLAKE
>  
>  static const struct intel_device_info intel_kabylake_gt1_info = {
> @@ -556,7 +555,6 @@ static const struct intel_device_info 
> intel_kabylake_gt3_info = {
>  
>  #define CFL_PLATFORM \
>   GEN9_FEATURES, \
> - GEN(9), \
>   .platform = INTEL_COFFEELAKE
>  
>  static const struct intel_device_info intel_coffeelake_gt1_info = {
> @@ -577,12 +575,12 @@ static const struct intel_device_info 
> intel_coffeelake_gt3_info = {
>  
>  #define GEN10_FEATURES \
>   GEN9_FEATURES, \
> + GEN(10), \
>   .ddb_size = 1024, \
>   GLK_COLORS
>  
>  static const struct intel_device_info intel_cannonlake_info = {
>   GEN10_FEATURES,
> - GEN(10),
>   .is_alpha_support = 1,
>   .platform = INTEL_CANNONLAKE,
>   .gt = 2,
> -- 
> 2.16.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/4] drm/i915: Store gen_mask inside the static device info

[Rodrigo Vivi]

Chris Wilson  writes:

> Rather than deriving the gen_mask from the static intel_device_info->gen
> at runtime, prefill it in the static data.
>
> Signed-off-by: Chris Wilson 

Reviewed-by: Rodrigo Vivi 

> ---
>  drivers/gpu/drm/i915/i915_drv.c |  2 --
>  drivers/gpu/drm/i915/i915_pci.c | 39 ---
>  2 files changed, 24 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index daa9060bdfcb..90f4adbbff28 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -902,8 +902,6 @@ static int i915_driver_init_early(struct drm_i915_private 
> *dev_priv,
>   device_info->platform_mask = BIT(device_info->platform);
>  
>   BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * 
> BITS_PER_BYTE);
> - device_info->gen_mask = BIT(device_info->gen - 1);
> -
>   spin_lock_init(_priv->irq_lock);
>   spin_lock_init(_priv->gpu_error.lock);
>   mutex_init(_priv->backlight_lock);
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 4e7a10c89782..3b4516d7f9a4 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -29,6 +29,8 @@
>  #include "i915_drv.h"
>  #include "i915_selftest.h"
>  
> +#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
> +
>  #define GEN_DEFAULT_PIPEOFFSETS \
>   .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
> PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
> @@ -63,7 +65,8 @@
>   .page_sizes = I915_GTT_PAGE_SIZE_4K
>  
>  #define GEN2_FEATURES \
> - .gen = 2, .num_pipes = 1, \
> + GEN(2), \
> + .num_pipes = 1, \
>   .has_overlay = 1, .overlay_needs_physical = 1, \
>   .has_gmch_display = 1, \
>   .hws_needs_physical = 1, \
> @@ -100,7 +103,8 @@ static const struct intel_device_info intel_i865g_info = {
>  };
>  
>  #define GEN3_FEATURES \
> - .gen = 3, .num_pipes = 2, \
> + GEN(3), \
> + .num_pipes = 2, \
>   .has_gmch_display = 1, \
>   .ring_mask = RENDER_RING, \
>   .has_snoop = true, \
> @@ -163,7 +167,8 @@ static const struct intel_device_info intel_pineview_info 
> = {
>  };
>  
>  #define GEN4_FEATURES \
> - .gen = 4, .num_pipes = 2, \
> + GEN(4), \
> + .num_pipes = 2, \
>   .has_hotplug = 1, \
>   .has_gmch_display = 1, \
>   .ring_mask = RENDER_RING, \
> @@ -205,7 +210,8 @@ static const struct intel_device_info intel_gm45_info = {
>  };
>  
>  #define GEN5_FEATURES \
> - .gen = 5, .num_pipes = 2, \
> + GEN(5), \
> + .num_pipes = 2, \
>   .has_hotplug = 1, \
>   .ring_mask = RENDER_RING | BSD_RING, \
>   .has_snoop = true, \
> @@ -227,7 +233,8 @@ static const struct intel_device_info 
> intel_ironlake_m_info = {
>  };
>  
>  #define GEN6_FEATURES \
> - .gen = 6, .num_pipes = 2, \
> + GEN(6), \
> + .num_pipes = 2, \
>   .has_hotplug = 1, \
>   .has_fbc = 1, \
>   .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
> @@ -270,7 +277,8 @@ static const struct intel_device_info 
> intel_sandybridge_m_gt2_info = {
>  };
>  
>  #define GEN7_FEATURES  \
> - .gen = 7, .num_pipes = 3, \
> + GEN(7), \
> + .num_pipes = 3, \
>   .has_hotplug = 1, \
>   .has_fbc = 1, \
>   .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
> @@ -324,7 +332,7 @@ static const struct intel_device_info 
> intel_ivybridge_q_info = {
>  
>  static const struct intel_device_info intel_valleyview_info = {
>   .platform = INTEL_VALLEYVIEW,
> - .gen = 7,
> + GEN(7),
>   .is_lp = 1,
>   .num_pipes = 2,
>   .has_psr = 1,
> @@ -385,7 +393,7 @@ static const struct intel_device_info 
> intel_haswell_gt3_info = {
>  
>  #define BDW_PLATFORM \
>   GEN8_FEATURES, \
> - .gen = 8, \
> + GEN(8), \
>   .platform = INTEL_BROADWELL
>  
>  static const struct intel_device_info intel_broadwell_gt1_info = {
> @@ -413,7 +421,8 @@ static const struct intel_device_info 
> intel_broadwell_gt3_info = {
>  };
>  
>  static const struct intel_device_info intel_cherryview_info = {
> - .gen = 8, .num_pipes = 3,
> + GEN(8),
> + .num_pipes = 3,
>   .has_hotplug = 1,
>   .is_lp = 1,
>   .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
> @@ -452,7 +461,7 @@ static const struct intel_device_info 
> intel_cherryview_info = {
>  
>  #define SKL_PLATFORM \
>   GEN9_FEATURES, \
> - .gen = 9, \
> + GEN(9), \
>   .platform = INTEL_SKYLAKE
>  
>  static const struct intel_device_info intel_skylake_gt1_info = {
> @@ -481,7 +490,7 @@ static const struct intel_device_info 
> intel_skylake_gt4_info = {
>  };
>  
>  #define GEN9_LP_FEATURES \
> - .gen = 9, \
> + GEN(9), \
>   .is_lp = 1, \
>   .has_hotplug = 1, \
>   .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
> @@ -526,7 +535,7 @@ 

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/cnl: Remove alpha_support protection (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: Remove alpha_support protection (rev2)
URL   : https://patchwork.freedesktop.org/series/38264/
State : failure

== Summary ==

Series 38264v2 drm/i915/cnl: Remove alpha_support protection
https://patchwork.freedesktop.org/api/1.0/series/38264/revisions/2/mbox/

Test kms_addfb_basic:
Subgroup tile-pitch-mismatch:
pass   -> INCOMPLETE (fi-bxt-dsi)

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:423s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:429s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:375s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:500s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:290s
fi-bxt-dsi   total:189  pass:175  dwarn:0   dfail:0   fail:0   skip:13 
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:489s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:474s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:460s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:559s
fi-cnl-y3total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:577s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:419s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:299s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:514s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:392s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:420s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:464s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:415s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:459s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:494s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:499s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:591s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:430s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:508s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:525s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:496s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:482s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:417s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:431s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:549s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:401s
Blacklisted hosts:
fi-glk-dsi   total:288  pass:257  dwarn:0   dfail:0   fail:1   skip:30  
time:487s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:454s

c552bd1bdbff57717814c72748f1351d9b2019d5 drm-tip: 2018y-02m-14d-20h-59m-41s UTC 
integration manifest
8166b110c896 drm/i915/cnl: Remove alpha_support protection

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8032/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm/i915: Track GT interrupt handling using the master iir

[Chris Wilson]

Keep the master iir and use it to reduce the number of reads and writes
to the GT iir array, i.e. only the bits marked as set by the master iir
are valid inside GT iir array and will be handled during the interrupt.

Signed-off-by: Chris Wilson 
Cc: Ville Syrjala 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_irq.c | 51 +
 1 file changed, 31 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b886bd459acc..b7b377ba7b6e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1416,6 +1416,14 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 
iir, int test_shift)
 static void gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
u32 master_ctl, u32 gt_iir[4])
 {
+#define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
+ GEN8_GT_BCS_IRQ | \
+ GEN8_GT_VCS1_IRQ | \
+ GEN8_GT_VCS2_IRQ | \
+ GEN8_GT_VECS_IRQ | \
+ GEN8_GT_PM_IRQ | \
+ GEN8_GT_GUC_IRQ)
+
if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
if (gt_iir[0])
@@ -1446,31 +1454,34 @@ static void gen8_gt_irq_ack(struct drm_i915_private 
*dev_priv,
 }
 
 static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
-   u32 gt_iir[4])
+   u32 master_ctl, u32 gt_iir[4])
 {
-   if (gt_iir[0]) {
+   if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
gen8_cs_irq_handler(dev_priv->engine[RCS],
gt_iir[0], GEN8_RCS_IRQ_SHIFT);
gen8_cs_irq_handler(dev_priv->engine[BCS],
gt_iir[0], GEN8_BCS_IRQ_SHIFT);
}
 
-   if (gt_iir[1]) {
+   if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
gen8_cs_irq_handler(dev_priv->engine[VCS],
gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
gen8_cs_irq_handler(dev_priv->engine[VCS2],
gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
}
 
-   if (gt_iir[3])
+   if (master_ctl & GEN8_GT_VECS_IRQ) {
gen8_cs_irq_handler(dev_priv->engine[VECS],
gt_iir[3], GEN8_VECS_IRQ_SHIFT);
+   }
 
-   if (gt_iir[2] & dev_priv->pm_rps_events)
-   gen6_rps_irq_handler(dev_priv, gt_iir[2]);
+   if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
+   if (gt_iir[2] & dev_priv->pm_rps_events)
+   gen6_rps_irq_handler(dev_priv, gt_iir[2]);
 
-   if (gt_iir[2] & dev_priv->pm_guc_events)
-   gen9_guc_irq_handler(dev_priv, gt_iir[2]);
+   if (gt_iir[2] & dev_priv->pm_guc_events)
+   gen9_guc_irq_handler(dev_priv, gt_iir[2]);
+   }
 }
 
 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
@@ -2085,9 +2096,9 @@ static irqreturn_t cherryview_irq_handler(int irq, void 
*arg)
 
do {
u32 master_ctl, iir;
-   u32 gt_iir[4] = {};
u32 pipe_stats[I915_MAX_PIPES] = {};
u32 hotplug_status = 0;
+   u32 gt_iir[4];
u32 ier = 0;
 
master_ctl = I915_READ(GEN8_MASTER_IRQ) & 
~GEN8_MASTER_IRQ_CONTROL;
@@ -2140,7 +2151,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void 
*arg)
I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
POSTING_READ(GEN8_MASTER_IRQ);
 
-   gen8_gt_irq_handler(dev_priv, gt_iir);
+   gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
 
if (hotplug_status)
i9xx_hpd_irq_handler(dev_priv, hotplug_status);
@@ -2675,10 +2686,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, 
u32 master_ctl)
 
 static irqreturn_t gen8_irq_handler(int irq, void *arg)
 {
-   struct drm_device *dev = arg;
-   struct drm_i915_private *dev_priv = to_i915(dev);
+   struct drm_i915_private *dev_priv = to_i915(arg);
u32 master_ctl;
-   u32 gt_iir[4] = {};
+   u32 gt_iir[4];
 
if (!intel_irqs_enabled(dev_priv))
return IRQ_NONE;
@@ -2690,18 +2700,19 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 
I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
 
-   /* IRQs are synced during runtime_suspend, we don't require a wakeref */
-   disable_rpm_wakeref_asserts(dev_priv);
-
/* Find, clear, then process each source of interrupt */
gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
-   gen8_gt_irq_handler(dev_priv, gt_iir);
-   gen8_de_irq_handler(dev_priv, master_ctl);
+
+   /* IRQs are 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Add DPCD definitions for DP 1.4 FEC feature (rev5)

[Patchwork]

== Series Details ==

Series: drm: Add DPCD definitions for DP 1.4 FEC feature (rev5)
URL   : https://patchwork.freedesktop.org/series/34259/
State : success

== Summary ==

Series 34259v5 drm: Add DPCD definitions for DP 1.4 FEC feature
https://patchwork.freedesktop.org/api/1.0/series/34259/revisions/5/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713
pass   -> DMESG-FAIL (fi-cnl-y3) fdo#104951

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:424s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:432s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:375s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:487s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:285s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:480s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:490s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:467s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:455s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:570s
fi-cnl-y3total:288  pass:261  dwarn:0   dfail:1   fail:0   skip:26  
time:574s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:419s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:283s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:512s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:390s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:408s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:460s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:412s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:457s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:498s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:501s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:592s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:433s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:507s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:528s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:487s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:480s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:414s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:434s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:394s
Blacklisted hosts:
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:472s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:451s

c552bd1bdbff57717814c72748f1351d9b2019d5 drm-tip: 2018y-02m-14d-20h-59m-41s UTC 
integration manifest
a2efb7357012 drm: Add DPCD definitions for DP 1.4 FEC feature

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8031/issues.html
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Re: [Intel-gfx] [PATCH] drm/i915: fix rsvd2 mask when out-fence is returned

[Chris Wilson]

Quoting Daniele Ceraolo Spurio (2018-02-14 19:18:25)
> GENMASK_ULL wants the high bit of the mask first. The current value
> cancels the in-fence when an out-fence is returned
> 
> Fixes: fec0445caa273 ("drm/i915: Support explicit fencing for execbuf")
> Cc: Chris Wilson 
> Signed-off-by: Daniele Ceraolo Spurio 

Pushed, thanks for the fix and the test case.
-Chris
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: Add DPCD definitions for DP 1.4 FEC feature (rev5)

[Patchwork]

== Series Details ==

Series: drm: Add DPCD definitions for DP 1.4 FEC feature (rev5)
URL   : https://patchwork.freedesktop.org/series/34259/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
a2efb7357012 drm: Add DPCD definitions for DP 1.4 FEC feature
-:37: CHECK: Prefer using the BIT macro
#37: FILE: include/drm/drm_dp_helper.h:334:
+# define DP_FEC_CAPABLE(1 << 0)

-:38: CHECK: Prefer using the BIT macro
#38: FILE: include/drm/drm_dp_helper.h:335:
+# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP  (1 << 1)

-:39: CHECK: Prefer using the BIT macro
#39: FILE: include/drm/drm_dp_helper.h:336:
+# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP(1 << 2)

-:40: CHECK: Prefer using the BIT macro
#40: FILE: include/drm/drm_dp_helper.h:337:
+# define DP_FEC_BIT_ERROR_COUNT_CAP(1 << 3)

-:50: CHECK: Prefer using the BIT macro
#50: FILE: include/drm/drm_dp_helper.h:456:
+# define DP_FEC_READY  (1 << 0)

-:53: CHECK: Prefer using the BIT macro
#53: FILE: include/drm/drm_dp_helper.h:459:
+# define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1)

-:58: CHECK: Prefer using the BIT macro
#58: FILE: include/drm/drm_dp_helper.h:464:
+# define DP_FEC_LANE_1_SELECT  (1 << 4)

-:70: CHECK: Prefer using the BIT macro
#70: FILE: include/drm/drm_dp_helper.h:644:
+# define DP_FEC_DECODE_EN_DETECTED (1 << 0)

-:71: CHECK: Prefer using the BIT macro
#71: FILE: include/drm/drm_dp_helper.h:645:
+# define DP_FEC_DECODE_DIS_DETECTED(1 << 1)

-:77: CHECK: Prefer using the BIT macro
#77: FILE: include/drm/drm_dp_helper.h:651:
+# define DP_FEC_ERR_COUNT_VALID(1 << 7)

total: 0 errors, 0 warnings, 10 checks, 48 lines checked

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Add COLOR_ENCODING and COLOR_RANGE plane properties

[Patchwork]

== Series Details ==

Series: drm: Add COLOR_ENCODING and COLOR_RANGE plane properties
URL   : https://patchwork.freedesktop.org/series/38286/
State : success

== Summary ==

Series 38286v1 drm: Add COLOR_ENCODING and COLOR_RANGE plane properties
https://patchwork.freedesktop.org/api/1.0/series/38286/revisions/1/mbox/

Test kms_force_connector_basic:
Subgroup force-connector-state:
skip   -> PASS   (fi-snb-2520m)
Subgroup force-edid:
skip   -> PASS   (fi-snb-2520m)
Subgroup force-load-detect:
skip   -> PASS   (fi-snb-2520m)
Subgroup prune-stale-modes:
skip   -> PASS   (fi-snb-2520m)

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:420s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:425s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:379s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:495s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:287s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:482s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:484s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:475s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:456s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:571s
fi-cnl-y3total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:582s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:417s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:282s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:508s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:390s
fi-ilk-650   total:288  pass:227  dwarn:0   dfail:0   fail:1   skip:60  
time:410s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:459s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:415s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:458s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:494s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:497s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:590s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:433s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:511s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:526s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:492s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:481s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:415s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:430s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:516s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:394s
Blacklisted hosts:
fi-glk-dsi   total:288  pass:180  dwarn:1   dfail:4   fail:0   skip:103 
time:771s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:453s

1cf237a2160af1a670d75523e073ff8614780b99 drm-tip: 2018y-02m-14d-19h-43m-47s UTC 
integration manifest
b9af44b33bda drm/i915: Add support for the YCbCr COLOR_RANGE property
e2c49a51ad72 drm/i915: Change the COLOR_ENCODING prop default value to BT.709
19bc29ea8f95 drm/i915: Add support for the YCbCr COLOR_ENCODING property
956e75f5dfb0 drm/i915: Fix plane YCbCr->RGB conversion for GLK
c9445dd9d6eb drm/i915: Correctly handle limited range YCbCr data on VLV/CHV
d286b7a4cbb9 drm/atomic: Include color encoding/range in plane state dump
970627907fcd drm: Add BT.2020 constant luminance enum value for the 
COLOR_ENCODING property
fe775e9df8ef drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to 
drm_plane

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8030/issues.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fixup kerneldoc for intel_pm.c

[Patchwork]

== Series Details ==

Series: drm/i915: Fixup kerneldoc for intel_pm.c
URL   : https://patchwork.freedesktop.org/series/38251/
State : success

== Summary ==

Test kms_plane_lowres:
Subgroup pipe-a-tiling-yf:
fail   -> PASS   (shard-apl)
Test kms_sysfs_edid_timing:
warn   -> PASS   (shard-apl) fdo#100047
Test perf:
Subgroup buffer-fill:
fail   -> PASS   (shard-apl) fdo#103755
Subgroup oa-exponents:
fail   -> PASS   (shard-apl) fdo#102254
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test perf_pmu:
Subgroup busy-start-vcs0:
fail   -> PASS   (shard-snb)

fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-apltotal:3346 pass:1738 dwarn:1   dfail:0   fail:20  skip:1586 
time:14039s
shard-hswtotal:3427 pass:1758 dwarn:1   dfail:0   fail:11  skip:1656 
time:14719s
shard-snbtotal:3427 pass:1348 dwarn:1   dfail:0   fail:10  skip:2068 
time:7581s
Blacklisted hosts:
shard-kbltotal:3427 pass:1906 dwarn:1   dfail:0   fail:21  skip:1499 
time:5s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8019/shards.html
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm: Add COLOR_ENCODING and COLOR_RANGE plane properties

[Patchwork]

== Series Details ==

Series: drm: Add COLOR_ENCODING and COLOR_RANGE plane properties
URL   : https://patchwork.freedesktop.org/series/38286/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to drm_plane
+drivers/gpu/drm/drm_color_mgmt.c:388:45: warning: Variable length array is 
used.

Commit: drm: Add BT.2020 constant luminance enum value for the COLOR_ENCODING 
property
Okay!

Commit: drm/atomic: Include color encoding/range in plane state dump
Okay!

Commit: drm/i915: Correctly handle limited range YCbCr data on VLV/CHV
Okay!

Commit: drm/i915: Fix plane YCbCr->RGB conversion for GLK
Okay!

Commit: drm/i915: Add support for the YCbCr COLOR_ENCODING property
Okay!

Commit: drm/i915: Change the COLOR_ENCODING prop default value to BT.709
Okay!

Commit: drm/i915: Add support for the YCbCr COLOR_RANGE property
Okay!


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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: Add COLOR_ENCODING and COLOR_RANGE plane properties

[Patchwork]

== Series Details ==

Series: drm: Add COLOR_ENCODING and COLOR_RANGE plane properties
URL   : https://patchwork.freedesktop.org/series/38286/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
fe775e9df8ef drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to 
drm_plane
-:67: WARNING: please, no space before tabs
#67: FILE: drivers/gpu/drm/drm_color_mgmt.c:96:
+ * ^IOptional plane enum property to support different non RGB$

-:68: WARNING: please, no space before tabs
#68: FILE: drivers/gpu/drm/drm_color_mgmt.c:97:
+ * ^Icolor encodings. The driver can provide a subset of standard$

-:69: WARNING: please, no space before tabs
#69: FILE: drivers/gpu/drm/drm_color_mgmt.c:98:
+ * ^Ienum values supported by the DRM plane.$

-:72: WARNING: please, no space before tabs
#72: FILE: drivers/gpu/drm/drm_color_mgmt.c:101:
+ * ^IOptional plane enum property to support different non RGB$

-:73: WARNING: please, no space before tabs
#73: FILE: drivers/gpu/drm/drm_color_mgmt.c:102:
+ * ^Icolor parameter ranges. The driver can provide a subset of$

-:74: WARNING: please, no space before tabs
#74: FILE: drivers/gpu/drm/drm_color_mgmt.c:103:
+ * ^Istandard enum values supported by the DRM plane.$

total: 0 errors, 6 warnings, 0 checks, 175 lines checked
970627907fcd drm: Add BT.2020 constant luminance enum value for the 
COLOR_ENCODING property
-:34: WARNING: line over 80 characters
#34: FILE: drivers/gpu/drm/drm_color_mgmt.c:360:
+   [DRM_COLOR_YCBCR_BT2020_CONST] = "ITU-R BT.2020 YCbCr constant 
luminance",

total: 0 errors, 1 warnings, 0 checks, 16 lines checked
d286b7a4cbb9 drm/atomic: Include color encoding/range in plane state dump
c9445dd9d6eb drm/i915: Correctly handle limited range YCbCr data on VLV/CHV
-:81: WARNING: line over 80 characters
#81: FILE: drivers/gpu/drm/i915/i915_reg.h:6345:
+#define SPCLRC0(pipe, plane_id)_MMIO_VLV_SPR((pipe), 
(plane_id), _SPACLRC0, _SPBCLRC0)

-:82: WARNING: line over 80 characters
#82: FILE: drivers/gpu/drm/i915/i915_reg.h:6346:
+#define SPCLRC1(pipe, plane_id)_MMIO_VLV_SPR((pipe), 
(plane_id), _SPACLRC1, _SPBCLRC1)

-:142: WARNING: line over 80 characters
#142: FILE: drivers/gpu/drm/i915/intel_sprite.c:380:
+   I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | 
SPCSC_IMIN(0));

-:143: WARNING: line over 80 characters
#143: FILE: drivers/gpu/drm/i915/intel_sprite.c:381:
+   I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | 
SPCSC_IMIN(-512));

-:144: WARNING: line over 80 characters
#144: FILE: drivers/gpu/drm/i915/intel_sprite.c:382:
+   I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | 
SPCSC_IMIN(-512));

total: 0 errors, 5 warnings, 0 checks, 143 lines checked
956e75f5dfb0 drm/i915: Fix plane YCbCr->RGB conversion for GLK
-:36: CHECK: Prefer using the BIT macro
#36: FILE: drivers/gpu/drm/i915/i915_reg.h:6467:
+#define   PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709(1 << 17)

total: 0 errors, 0 warnings, 1 checks, 74 lines checked
19bc29ea8f95 drm/i915: Add support for the YCbCr COLOR_ENCODING property
-:42: CHECK: spaces preferred around that '<<' (ctx:VxV)
#42: FILE: drivers/gpu/drm/i915/i915_reg.h:6143:
+#define   DVS_YUV_FORMAT_BT709 (1<<18)
  ^

-:42: CHECK: Prefer using the BIT macro
#42: FILE: drivers/gpu/drm/i915/i915_reg.h:6143:
+#define   DVS_YUV_FORMAT_BT709 (1<<18)

-:51: CHECK: spaces preferred around that '<<' (ctx:VxV)
#51: FILE: drivers/gpu/drm/i915/i915_reg.h:6214:
+#define   SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709   (1<<18) /* 0 is BT601 */
  ^

-:51: CHECK: Prefer using the BIT macro
#51: FILE: drivers/gpu/drm/i915/i915_reg.h:6214:
+#define   SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709   (1<<18) /* 0 is BT601 */

-:59: CHECK: spaces preferred around that '<<' (ctx:VxV)
#59: FILE: drivers/gpu/drm/i915/i915_reg.h:6290:
+#define   SP_YUV_FORMAT_BT709  (1<<18)
  ^

-:59: CHECK: Prefer using the BIT macro
#59: FILE: drivers/gpu/drm/i915/i915_reg.h:6290:
+#define   SP_YUV_FORMAT_BT709  (1<<18)

-:67: CHECK: Prefer using the BIT macro
#67: FILE: drivers/gpu/drm/i915/i915_reg.h:6415:
+#define   PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709(1 << 18)

-:93: WARNING: line over 80 characters
#93: FILE: drivers/gpu/drm/i915/intel_display.c:3581:
+   plane_color_ctl |= 
PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;

-:95: WARNING: line over 80 characters
#95: FILE: drivers/gpu/drm/i915/intel_display.c:3583:
+   plane_color_ctl |= 
PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;

-:108: WARNING: line over 80 characters
#108: FILE: drivers/gpu/drm/i915/intel_display.c:13328:
+ 
BIT(DRM_COLOR_YCBCR_LIMITED_RANGE),

-:110: WARNING: line over 80 characters
#110: FILE: drivers/gpu/drm/i915/intel_display.c:13330:
+ 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: fix rsvd2 mask when out-fence is returned

[Patchwork]

== Series Details ==

Series: drm/i915: fix rsvd2 mask when out-fence is returned
URL   : https://patchwork.freedesktop.org/series/38284/
State : success

== Summary ==

Series 38284v1 drm/i915: fix rsvd2 mask when out-fence is returned
https://patchwork.freedesktop.org/api/1.0/series/38284/revisions/1/mbox/

Test kms_force_connector_basic:
Subgroup force-connector-state:
skip   -> PASS   (fi-snb-2520m)
Subgroup force-edid:
skip   -> PASS   (fi-snb-2520m)
Subgroup force-load-detect:
skip   -> PASS   (fi-snb-2520m)
Subgroup prune-stale-modes:
skip   -> PASS   (fi-snb-2520m)
Test prime_vgem:
Subgroup basic-fence-flip:
fail   -> PASS   (fi-ilk-650) fdo#104008

fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:421s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:423s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:374s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:485s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:287s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:469s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:456s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:568s
fi-cnl-y3total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:587s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:417s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:283s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:511s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:390s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:418s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:460s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:415s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:455s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:491s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:497s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:585s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:428s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:509s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:528s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:489s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:473s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:416s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:429s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:520s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:398s
Blacklisted hosts:
fi-glk-dsi   total:246  pass:219  dwarn:0   dfail:0   fail:0   skip:26 
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:462s
fi-bxt-dsi failed to collect. IGT log at Patchwork_8029/fi-bxt-dsi/run0.log

1cf237a2160af1a670d75523e073ff8614780b99 drm-tip: 2018y-02m-14d-19h-43m-47s UTC 
integration manifest
4a48bcdaa057 drm/i915: fix rsvd2 mask when out-fence is returned

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8029/issues.html
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Re: [Intel-gfx] [PATCH xf86-video-intel] sna/video: Actually use the NV12 shader on gen8

[Chris Wilson]

Quoting Ville Syrjala (2018-02-14 20:27:06)
> From: Ville Syrjälä 
> 
> Oops. We never actually select the NV12 shader on gen8, causing
> us to render garbage. Looks like this is the only one I somehow
> missed.
> 
> Signed-off-by: Ville Syrjälä 

Not much of an excuse to say I tested on skl. Thanks,
-Chris
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[Intel-gfx] [PATCH igt v2] igt/gem_exec_fence: Test that the in-fence is not overwritten

[Chris Wilson]

From: Daniele Ceraolo Spurio 

When an out-fence is returned we expect that the in-fence is not
overwritten. Add a test to check for that.

Cc: Chris Wilson 
Signed-off-by: Daniele Ceraolo Spurio 
Reviewed-by: Chris Wilson 
Signed-off-by: Chris Wilson 
---
 tests/gem_exec_fence.c | 98 +-
 1 file changed, 97 insertions(+), 1 deletion(-)

diff --git a/tests/gem_exec_fence.c b/tests/gem_exec_fence.c
index bd7b1263..e680c7aa 100644
--- a/tests/gem_exec_fence.c
+++ b/tests/gem_exec_fence.c
@@ -357,7 +357,14 @@ static void alarm_handler(int sig)
 
 static int __execbuf(int fd, struct drm_i915_gem_execbuffer2 *execbuf)
 {
-   return ioctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, execbuf);
+   int err;
+
+   err = 0;
+   if (ioctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2_WR, execbuf))
+   err = -errno;
+
+   errno = 0;
+   return err;
 }
 
 static unsigned int measure_ring_size(int fd)
@@ -586,6 +593,92 @@ static void test_parallel(int fd, unsigned int master)
gem_close(fd, handle[0]);
 }
 
+static uint32_t batch_create(int fd)
+{
+   const uint32_t bbe = MI_BATCH_BUFFER_END;
+   uint32_t handle;
+
+   handle = gem_create(fd, 4096);
+   gem_write(fd, handle, 0, , sizeof(bbe));
+
+   return handle;
+}
+
+static uint32_t lower_32_bits(uint64_t x)
+{
+   return x & 0x;
+}
+
+static uint32_t upper_32_bits(uint64_t x)
+{
+   return x >> 32;
+}
+
+static void test_keep_in_fence(int fd, unsigned int engine, unsigned int flags)
+{
+   struct sigaction sa = { .sa_handler = alarm_handler };
+   struct drm_i915_gem_exec_object2 obj = {
+   .handle = batch_create(fd),
+   };
+   struct drm_i915_gem_execbuffer2 execbuf = {
+   .buffers_ptr = to_user_pointer(),
+   .buffer_count = 1,
+   .flags = engine | LOCAL_EXEC_FENCE_OUT,
+   };
+   unsigned long count, last;
+   struct itimerval itv;
+   igt_spin_t *spin;
+   int fence;
+
+   spin = igt_spin_batch_new(fd, 0, engine, 0);
+
+   gem_execbuf_wr(fd, );
+   fence = upper_32_bits(execbuf.rsvd2);
+
+   sigaction(SIGALRM, , NULL);
+   itv.it_interval.tv_sec = 0;
+   itv.it_interval.tv_usec = 100;
+   itv.it_value.tv_sec = 0;
+   itv.it_value.tv_usec = 1000;
+   setitimer(ITIMER_REAL, , NULL);
+
+   execbuf.flags |= LOCAL_EXEC_FENCE_IN;
+   execbuf.rsvd2 = fence;
+
+   last = -1;
+   count = 0;
+   do {
+   int err = __execbuf(fd, );
+
+   igt_assert_eq(lower_32_bits(execbuf.rsvd2), fence);
+
+   if (err == 0) {
+   close(fence);
+
+   fence = upper_32_bits(execbuf.rsvd2);
+   execbuf.rsvd2 = fence;
+
+   count++;
+   continue;
+   }
+
+   igt_assert_eq(err, -EINTR);
+
+   if (last == count)
+   break;
+
+   last = count;
+   } while (1);
+
+   memset(, 0, sizeof(itv));
+   setitimer(ITIMER_REAL, , NULL);
+
+   gem_close(fd, obj.handle);
+   close(fence);
+
+   igt_spin_batch_free(fd, spin);
+}
+
 #define EXPIRED 0x1
 static void test_long_history(int fd, long ring_size, unsigned flags)
 {
@@ -1490,6 +1583,9 @@ igt_main
igt_subtest_f("nb-await-%s", e->name)
test_fence_await(i915, e->exec_id | 
e->flags, NONBLOCK);
 
+   igt_subtest_f("keep-in-fence-%s", e->name)
+   test_keep_in_fence(i915, e->exec_id | 
e->flags, 0);
+
if (e->exec_id &&
!(e->exec_id == I915_EXEC_BSD && 
!e->flags)) {
igt_subtest_f("parallel-%s", e->name) {
-- 
2.16.1

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[Intel-gfx] [PATCH] drm/i915/cnl: Remove alpha_support protection

[Rodrigo Vivi]

We now have a stable cnl on our CI and it seems mostly
green without big risks of blank screen or anything
blowing up on linux installations in the future.

As a reminder i915.alpha_support was created to protect
future linux installation's iso images that might contain a
kernel from the enabling time of the new platform. Without this
protection most of linux installation was recommending
nomodeset option during installation that was getting stick
there after installation.

Specifically, alpha support says nothing about the development
state of the hardware, and everything about the state of the
driver in a kernel release.

This is semantically no different from the old
preliminary_hw_support flag, but the old one was all too often
interpreted as (preliminary hw) support instead of the intended
(preliminary) hw support, and it was misleading for everyone.
Hence the rename.

v2: Fix the typos and include more history about the parameter
rename on commit message. (Jani)

Reference: https://intel-gfx-ci.01.org/tree/drm-tip/fi-cnl-y3.html
Cc: James Ausmus 
Cc: Lucas De Marchi 
Cc: Jani Saarinen 
Cc: Jani Nikula 
Cc: Joonas Lahtinen 
Signed-off-by: Rodrigo Vivi 
Acked-by: Jani Nikula 
---
 drivers/gpu/drm/i915/i915_pci.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 4e7a10c89782..49cef20594b3 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -573,7 +573,6 @@ static const struct intel_device_info 
intel_coffeelake_gt3_info = {
 
 static const struct intel_device_info intel_cannonlake_info = {
GEN10_FEATURES,
-   .is_alpha_support = 1,
.platform = INTEL_CANNONLAKE,
.gen = 10,
.gt = 2,
-- 
2.13.6

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[Intel-gfx] [PATCH xf86-video-intel] sna/video: Actually use the NV12 shader on gen8

[Ville Syrjala]

From: Ville Syrjälä 

Oops. We never actually select the NV12 shader on gen8, causing
us to render garbage. Looks like this is the only one I somehow
missed.

Signed-off-by: Ville Syrjälä 
---
 src/sna/gen8_render.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/sna/gen8_render.c b/src/sna/gen8_render.c
index f7a797b37c56..46369d6b1193 100644
--- a/src/sna/gen8_render.c
+++ b/src/sna/gen8_render.c
@@ -3798,6 +3798,9 @@ static unsigned select_video_kernel(const struct 
sna_video_frame *frame)
case FOURCC_XVMC:
return GEN8_WM_KERNEL_VIDEO_PLANAR;
 
+   case FOURCC_NV12:
+   return GEN8_WM_KERNEL_VIDEO_NV12;
+
case FOURCC_RGB888:
case FOURCC_RGB565:
return GEN8_WM_KERNEL_VIDEO_RGB;
-- 
2.13.6

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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/atomic: Fixup kerneldoc

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/atomic: Fixup kerneldoc
URL   : https://patchwork.freedesktop.org/series/38249/
State : success

== Summary ==

Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test kms_plane_lowres:
Subgroup pipe-a-tiling-yf:
fail   -> PASS   (shard-apl)
Test kms_flip_tiling:
Subgroup flip-yf-tiled:
pass   -> FAIL   (shard-apl) fdo#103822
Test perf:
Subgroup buffer-fill:
fail   -> PASS   (shard-apl) fdo#103755
Subgroup oa-exponents:
fail   -> PASS   (shard-apl) fdo#102254
Test perf_pmu:
Subgroup busy-start-vcs0:
fail   -> PASS   (shard-snb)
Test kms_cursor_legacy:
Subgroup flip-vs-cursor-legacy:
pass   -> FAIL   (shard-hsw) fdo#102670
Test kms_flip:
Subgroup 2x-dpms-vs-vblank-race:
pass   -> FAIL   (shard-hsw) fdo#103060
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-pri-shrfb-draw-render:
pass   -> DMESG-FAIL (shard-apl) fdo#103167

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167

shard-apltotal:3346 pass:1735 dwarn:1   dfail:1   fail:21  skip:1586 
time:13994s
shard-hswtotal:3427 pass:1756 dwarn:1   dfail:0   fail:13  skip:1656 
time:14656s
shard-snbtotal:3427 pass:1348 dwarn:1   dfail:0   fail:10  skip:2068 
time:7599s
Blacklisted hosts:
shard-kbltotal:3427 pass:1907 dwarn:1   dfail:0   fail:21  skip:1498 
time:11083s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8018/shards.html
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Re: [Intel-gfx] [PATCH xf86-video-intel] sna: Add XV_COLORSPACE attribute support for sprite Xv adaptors

[Chris Wilson]

Quoting Ville Syrjälä (2018-02-14 20:06:17)
> On Wed, Feb 14, 2018 at 07:42:59PM +, Chris Wilson wrote:
> > Quoting Ville Syrjala (2018-02-14 19:21:08)
> > > From: Ville Syrjälä 
> > > 
> > > Use the new "COLOR_ENCODING" plane property to implement the
> > > XV_COLORSPACE port attribute for sprite Xv adaptors.
> > > 
> > > Cc: Jyri Sarha 
> > > Cc: Chris Wilson 
> > > Signed-off-by: Ville Syrjälä 
> > > ---
> > > +void sna_crtc_set_sprite_colorspace(xf86CrtcPtr crtc,
> > > +   unsigned idx, int colorspace)
> > > +{
> > > +   struct plane *p;
> > > +
> > > +   assert(to_sna_crtc(crtc));
> > 
> > assert(colorspace < ARRAY_SIZE(p->color_encoding.values));
> > 
> > > +
> > > +   p = lookup_sprite(to_sna_crtc(crtc), idx);
> > > +
> > > +   if (!p->color_encoding.prop)
> > > +   return;
> > > +
> > > +   drmModeObjectSetProperty(to_sna(crtc->scrn)->kgem.fd,
> > > +p->id, DRM_MODE_OBJECT_PLANE,
> > > +p->color_encoding.prop,
> > > +p->color_encoding.values[colorspace]);
> > 
> > Does changing the property trigger an immediate update, or is that
> > deferred until the next SetPlane (or atomic update)?
> 
> Legacy setprop so it'll trigger an update. So if the plane is
> already enabled I suppose we'll get an extra frame of lag here.
> Same deal as for the colorkey ioctl actually.
> 
> I think generally one can assume the the attribute won't be changed
> very often with the plane already enabled. Generally I'd expect the
> client to set this up before the first putimage.

Agreed.

> Converting this to atomic would avoid that extra lag. But we'd need
> to convert the colorkey ioctl to properties as well. And the next step
> after that would tearfree+atomic for making it actually nice :)

If we wanted nice, we wouldn't start with the X11 protocol! Oh well, if
all the shiny new features are going to be hidden being atomic, probably
going to have to bite the bullet sooner or later.

> > It makes no difference to this patch, except we might redisplay the
> > image immediately rather than wait for the client?
> 
> We call this from the putimage hook, so we need the client to
> actually repaint before anything happens. And since we don't have
> reputimage manipulating the window/clipping won't update the
> sprite unless the client repaints (which eg. mplayer won't do
> when paused unless it gets expose events).

I knew you were going to mention the lack of ReputImage! :)
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/audio: fix check for av_enc_map overflow

[Pandiyan, Dhinakaran]

z

On Wed, 2018-02-14 at 19:38 +0200, Jani Nikula wrote:
> Turns out -1 >= ARRAY_SIZE() is always true. Move the bounds check where
> we know pipe >= 0 and next to the array indexing where it makes most
> sense.
> 
> Fixes: 9965db26ac05 ("drm/i915: Check for fused or unused pipes")
> Fixes: 0b7029b7e43f ("drm/i915: Check for fused or unused pipes")
> Cc:  # v4.10+
> Cc: Mika Kahola 
> Cc: Rodrigo Vivi 
> Cc: Jani Nikula 
> Cc: Joonas Lahtinen 
> Cc: intel-gfx@lists.freedesktop.org
> Signed-off-by: Jani Nikula 

Reviewed-by: Dhinakaran Pandiyan 
> ---
>  drivers/gpu/drm/i915/intel_audio.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_audio.c 
> b/drivers/gpu/drm/i915/intel_audio.c
> index ff455c724775..709d6ca68074 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -779,11 +779,11 @@ static struct intel_encoder *get_saved_enc(struct 
> drm_i915_private *dev_priv,
>  {
>   struct intel_encoder *encoder;
>  
> - if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map)))
> - return NULL;
> -
>   /* MST */
>   if (pipe >= 0) {
> + if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map)))
> + return NULL;
> +
>   encoder = dev_priv->av_enc_map[pipe];
>   /*
>* when bootup, audio driver may not know it is
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Re: [Intel-gfx] [PATCH xf86-video-intel] sna: Add XV_COLORSPACE attribute support for sprite Xv adaptors

[Ville Syrjälä]

On Wed, Feb 14, 2018 at 07:42:59PM +, Chris Wilson wrote:
> Quoting Ville Syrjala (2018-02-14 19:21:08)
> > From: Ville Syrjälä 
> > 
> > Use the new "COLOR_ENCODING" plane property to implement the
> > XV_COLORSPACE port attribute for sprite Xv adaptors.
> > 
> > Cc: Jyri Sarha 
> > Cc: Chris Wilson 
> > Signed-off-by: Ville Syrjälä 
> > ---
> > +void sna_crtc_set_sprite_colorspace(xf86CrtcPtr crtc,
> > +   unsigned idx, int colorspace)
> > +{
> > +   struct plane *p;
> > +
> > +   assert(to_sna_crtc(crtc));
> 
> assert(colorspace < ARRAY_SIZE(p->color_encoding.values));
> 
> > +
> > +   p = lookup_sprite(to_sna_crtc(crtc), idx);
> > +
> > +   if (!p->color_encoding.prop)
> > +   return;
> > +
> > +   drmModeObjectSetProperty(to_sna(crtc->scrn)->kgem.fd,
> > +p->id, DRM_MODE_OBJECT_PLANE,
> > +p->color_encoding.prop,
> > +p->color_encoding.values[colorspace]);
> 
> Does changing the property trigger an immediate update, or is that
> deferred until the next SetPlane (or atomic update)?

Legacy setprop so it'll trigger an update. So if the plane is
already enabled I suppose we'll get an extra frame of lag here.
Same deal as for the colorkey ioctl actually.

I think generally one can assume the the attribute won't be changed
very often with the plane already enabled. Generally I'd expect the
client to set this up before the first putimage.

Converting this to atomic would avoid that extra lag. But we'd need
to convert the colorkey ioctl to properties as well. And the next step
after that would tearfree+atomic for making it actually nice :)

> 
> It makes no difference to this patch, except we might redisplay the
> image immediately rather than wait for the client?

We call this from the putimage hook, so we need the client to
actually repaint before anything happens. And since we don't have
reputimage manipulating the window/clipping won't update the
sprite unless the client repaints (which eg. mplayer won't do
when paused unless it gets expose events).

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] ✗ Fi.CI.IGT: warning for Adding NV12 support (rev10)

[Patchwork]

== Series Details ==

Series: Adding NV12 support (rev10)
URL   : https://patchwork.freedesktop.org/series/28103/
State : warning

== Summary ==

Test kms_color:
Subgroup pipe-a-degamma:
pass   -> FAIL   (shard-apl) fdo#104782
Test kms_plane_scaling:
Subgroup pipe-b-scaler-with-rotation:
pass   -> DMESG-WARN (shard-apl)
Subgroup pipe-a-scaler-with-rotation:
pass   -> DMESG-WARN (shard-apl)
Test kms_flip:
Subgroup plain-flip-ts-check:
pass   -> FAIL   (shard-snb) fdo#100368
Test kms_plane_lowres:
Subgroup pipe-a-tiling-yf:
fail   -> PASS   (shard-apl)
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test perf:
Subgroup oa-exponents:
fail   -> PASS   (shard-apl) fdo#102254
Subgroup polling:
pass   -> FAIL   (shard-hsw) fdo#102252
Test perf_pmu:
Subgroup busy-start-vcs0:
fail   -> PASS   (shard-snb)
Test kms_sysfs_edid_timing:
warn   -> PASS   (shard-apl) fdo#100047

fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047

shard-apltotal:3346 pass:1734 dwarn:3   dfail:0   fail:22  skip:1586 
time:13990s
shard-hswtotal:3427 pass:1757 dwarn:1   dfail:0   fail:12  skip:1656 
time:14635s
shard-snbtotal:3427 pass:1347 dwarn:1   dfail:0   fail:11  skip:2068 
time:7595s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8017/shards.html
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Re: [Intel-gfx] Adding a couple of DSI panel fixes to drm-intel-fixes

[Rodrigo Vivi]

Hans de Goede  writes:

> Hi,
>
> On 14-02-18 13:35, Jani Nikula wrote:
>> On Wed, 14 Feb 2018, Hans de Goede  wrote:
>>> Hi All,
>>>
>>> I would like to a add a couple of DSI panel fixes from
>>> dinq to drm-intel-fixes (with the purpose of getting them
>>> into 4.16).
>>>
>>> What is the correct way to do this?  Should I just do:
>>>
>>> dim checkout-branch drm-intel-fixes
>>> git pull
>>> git cherry-pick 
>>> git cherry-pick 
>>> dim push-branch drm-intel-fixes
>>>
>>> And that is it, or is there something special which
>>> I need to do, or ask someone who is taking care of this?
>> 
>> The maintainers take care of drm-intel-fixes and
>> drm-intel-next-fixes. In general, this mostly works automagically if you
>> add Fixes: or Cc: stable tags to the original commits.
>> 
>> Lacking those, please just send email to i915 maintainers with the
>> commit ids and we'll take of them.
>
> Ok, in that case can you please add the following commits from dinq
> to drm-intel-fixes:
>
> c8dae55a8ced ("drm/i915/vlv: Add cdclk workaround for DSI")
> 785f076b3ba7 ("drm/i915: Add intel_bios_cleanup() function")
> e1b86c85f6c2 ("drm/i915: Free memdup-ed DSI VBT data structures on 
> driver_unload")
> fb38e7ade9af ("drm/i915: Fix DSI panels with v1 MIPI sequences without
> a DEASSERT sequence v3")

All applyed to drm-intel-fixes. Probably going out in a pull request to
Dave tonight after CI run.

>
> The first and the fourth are the actual fixes, the middle 2 are
> cleanup / preparation patches.

Thanks for explaining... I should've read this before... I end up
figuring it out when trying to skip 2 middle ones ;)

>
> Regards,
>
> Hans
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Re: [Intel-gfx] [PATCH xf86-video-intel] sna: Add XV_COLORSPACE attribute support for sprite Xv adaptors

[Chris Wilson]

Quoting Ville Syrjala (2018-02-14 19:21:08)
> From: Ville Syrjälä 
> 
> Use the new "COLOR_ENCODING" plane property to implement the
> XV_COLORSPACE port attribute for sprite Xv adaptors.
> 
> Cc: Jyri Sarha 
> Cc: Chris Wilson 
> Signed-off-by: Ville Syrjälä 
> ---
> +void sna_crtc_set_sprite_colorspace(xf86CrtcPtr crtc,
> +   unsigned idx, int colorspace)
> +{
> +   struct plane *p;
> +
> +   assert(to_sna_crtc(crtc));

assert(colorspace < ARRAY_SIZE(p->color_encoding.values));

> +
> +   p = lookup_sprite(to_sna_crtc(crtc), idx);
> +
> +   if (!p->color_encoding.prop)
> +   return;
> +
> +   drmModeObjectSetProperty(to_sna(crtc->scrn)->kgem.fd,
> +p->id, DRM_MODE_OBJECT_PLANE,
> +p->color_encoding.prop,
> +p->color_encoding.values[colorspace]);

Does changing the property trigger an immediate update, or is that
deferred until the next SetPlane (or atomic update)?

It makes no difference to this patch, except we might redisplay the
image immediately rather than wait for the client?
-Chris
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Re: [Intel-gfx] [PATCH 01/43] drm: hdcp2.2 authentication msg definitions

[Jani Nikula]

On Wed, 14 Feb 2018, "Winkler, Tomas"  wrote:
>> 
>> This patch defines the hdcp2.2 protocol messages for the
>> HDCP2.2 authentication.
>> 
>> Signed-off-by: Ramalingam C 
>> ---
>>  include/drm/drm_hdcp.h | 226
>> +
>>  1 file changed, 226 insertions(+)
>> 
>> diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h index
>> 562fa7df2637..9661c700cebb 100644
>> --- a/include/drm/drm_hdcp.h
>> +++ b/include/drm/drm_hdcp.h
>> @@ -38,4 +38,230 @@
>>  #define DRM_HDCP_DDC_BSTATUS0x41
>>  #define DRM_HDCP_DDC_KSV_FIFO   0x43
>> 
>> +#define DRM_HDCP_1_4_SRM_ID 0x8
>> +#define DRM_HDCP_1_4_VRL_LENGTH_SIZE3
>> +#define DRM_HDCP_1_4_DCP_SIG_SIZE   40
>> +
>> +struct cp_srm_header {
>> +struct {
>> +uint8_t reserved_hi:4;
>> +uint8_t srm_id:4;
>> +uint8_t reserved_lo;
>> +} spec_indicator;
> Do you really want to work with bit fields?  I mean in all the all structures.

We *can't* use bitfields in drm core for (un)marshalling. They depend on
endianness. (Thanks to folks on #dri-devel for confirming.) We use them
at places in i915 where we can be pretty sure about running on
little-endian machines, but that doesn't hold here.

Packed structs are fine otherwise though, just not bitfields.

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH i-g-t] tests/gem_exec_fence: test that in-fence is not overwritten

[Chris Wilson]

Quoting Chris Wilson (2018-02-14 19:29:29)
> Quoting Daniele Ceraolo Spurio (2018-02-14 19:18:26)
> > When an out-fence is returned we expect that the in-fence is not
> > overwritten. Add a test to check for that.
> > 
> > Cc: Chris Wilson 
> > Signed-off-by: Daniele Ceraolo Spurio 
> > ---
> >  tests/gem_exec_fence.c | 39 +++
> >  1 file changed, 39 insertions(+)
> > 
> > diff --git a/tests/gem_exec_fence.c b/tests/gem_exec_fence.c
> > index bd7b1263..f7478c55 100644
> > --- a/tests/gem_exec_fence.c
> > +++ b/tests/gem_exec_fence.c
> > @@ -586,6 +586,42 @@ static void test_parallel(int fd, unsigned int master)
> > gem_close(fd, handle[0]);
> >  }
> >  
> > +/* check that a fence in doesn't get clobbered when a fence out is 
> > returned */
> > +static void test_keep_fence_in(int fd, unsigned int engine)
> > +{
> > +   struct drm_i915_gem_execbuffer2 execbuf;
> > +   struct drm_i915_gem_exec_object2 obj;
> > +   const uint32_t bbe = MI_BATCH_BUFFER_END;
> > +   int fence;
> > +
> > +   memset(, 0, sizeof(obj));
> > +   memset(, 0, sizeof(execbuf));
> > +
> > +   obj.handle = gem_create(fd, 4096);
> > +   gem_write(fd, obj.handle, 0, , sizeof(bbe));
> > +
> > +   execbuf.buffers_ptr = to_user_pointer();
> > +   execbuf.buffer_count = 1;
> > +   execbuf.flags = engine | LOCAL_EXEC_FENCE_OUT;
> > +
> > +   gem_execbuf_wr(fd, );
> > +   fence = execbuf.rsvd2 >> 32;
> > +
> > +   gem_close(fd, obj.handle);
> > +   obj.handle = gem_create(fd, 4096);
> > +   gem_write(fd, obj.handle, 0, , sizeof(bbe));
> 
> You don't need to recreate the batch here; just reusing the same handle
> will do (and avoid the extra complication).
> 
> > +
> > +   execbuf.flags |= LOCAL_EXEC_FENCE_IN;
> > +   execbuf.rsvd2 = fence;
> > +
> > +   gem_execbuf_wr(fd, );
> > +   igt_assert_eq(fence, execbuf.rsvd2 & 0x);
> 
> This would be a good one to throw to the interruptible wolves.

Of course to actually interrupt it, we need to hit a wait. Hmm. I'd use
a variant of the measure ring size approach, scrap the second test, and
then repeatedly re-submit until it hit an EINTR. (Obviously requires a
timer, and updating/checking the fences on each pass).
-Chris
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Re: [Intel-gfx] [PULL] git-fixes for 4.16-rc2

[Rodrigo Vivi]

Zhenyu Wang  writes:

> Hi, here's current gvt-fixes pull for 4.16-rc2, as it is close for
> chinese new year, team would take one week off at least, so like to
> send this out before vacation. This has one to fix GTT mmio 8b access
> from guest and two simple ones for mmio switch and typo fix.

Applied already. Thanks.

> And sorry
> that patchwork link is still not there yet, using dim to pull should
> be ok but might need direct push to skip dim push check for now.

It was funny, but dim didn't complained this time about signatures or
links. Just went through cleanly without any bypass.

I'm not sure what we have specially on next-fixes apply pull that end up
needing my signature and complaining about links that doesn't happen
here. I will check later

>
> thanks
> --
> The following changes since commit 4b8b41d15d9db54703958fbd2928a2fd319563f6:
>
>   drm/i915/pmu: Fix building without CONFIG_PM (2018-02-13 16:56:06 -0800)
>
> are available in the Git repository at:
>
>   https://github.com/intel/gvt-linux.git tags/gvt-fixes-2018-02-14
>
> for you to fetch changes up to 3cc7644e4af179e79153b1fd60f9dd937ee32684:
>
>   drm/i915/gvt: fix one typo of render_mmio trace (2018-02-14 10:35:00 +0800)
>
> 
> gvt-fixes-2018-02-14
>
> - gtt mmio 8b access fix (Tina)
> - one KBL required mmio reg for switch (Weinan)
> - one trace log typo fix (Weinan)
>
> 
> Tina Zhang (1):
>   drm/i915/gvt: Support BAR0 8-byte reads/writes
>
> Weinan Li (2):
>   drm/i915/gvt: add 0xe4f0 into gen9 render list
>   drm/i915/gvt: fix one typo of render_mmio trace
>
>  drivers/gpu/drm/i915/gvt/kvmgt.c| 51 
> +++--
>  drivers/gpu/drm/i915/gvt/mmio_context.c |  1 +
>  drivers/gpu/drm/i915/gvt/trace.h|  2 +-
>  3 files changed, 51 insertions(+), 3 deletions(-)
>
> -- 
> Open Source Technology Center, Intel ltd.
>
> $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
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[Intel-gfx] ✓ Fi.CI.BAT: success for New intel-gpu-top

[Patchwork]

== Series Details ==

Series: New intel-gpu-top
URL   : https://patchwork.freedesktop.org/series/38282/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
1d227a47223d2ff5c6745c0d82e96e70d456d5de lib/kms: Clear unused fields for 
getproperty ioctl

with latest DRM-Tip kernel build CI_DRM_3774
5ad7866768dc drm-tip: 2018y-02m-14d-15h-14m-50s UTC integration manifest

No testlist changes.

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:421s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:426s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:377s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:489s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:290s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:483s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:489s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:473s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:459s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:567s
fi-cnl-y3total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:578s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:426s
fi-gdg-551   total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 
time:284s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:512s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:391s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:413s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:463s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:420s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:467s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:498s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:501s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:591s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:424s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:510s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:525s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:497s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:475s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:414s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:433s
fi-snb-2520m total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:541s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:398s
Blacklisted hosts:
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:470s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:457s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_915/issues.html
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Re: [Intel-gfx] [PATCH i-g-t] tests/gem_exec_fence: test that in-fence is not overwritten

[Chris Wilson]

Quoting Daniele Ceraolo Spurio (2018-02-14 19:18:26)
> When an out-fence is returned we expect that the in-fence is not
> overwritten. Add a test to check for that.
> 
> Cc: Chris Wilson 
> Signed-off-by: Daniele Ceraolo Spurio 
> ---
>  tests/gem_exec_fence.c | 39 +++
>  1 file changed, 39 insertions(+)
> 
> diff --git a/tests/gem_exec_fence.c b/tests/gem_exec_fence.c
> index bd7b1263..f7478c55 100644
> --- a/tests/gem_exec_fence.c
> +++ b/tests/gem_exec_fence.c
> @@ -586,6 +586,42 @@ static void test_parallel(int fd, unsigned int master)
> gem_close(fd, handle[0]);
>  }
>  
> +/* check that a fence in doesn't get clobbered when a fence out is returned 
> */
> +static void test_keep_fence_in(int fd, unsigned int engine)
> +{
> +   struct drm_i915_gem_execbuffer2 execbuf;
> +   struct drm_i915_gem_exec_object2 obj;
> +   const uint32_t bbe = MI_BATCH_BUFFER_END;
> +   int fence;
> +
> +   memset(, 0, sizeof(obj));
> +   memset(, 0, sizeof(execbuf));
> +
> +   obj.handle = gem_create(fd, 4096);
> +   gem_write(fd, obj.handle, 0, , sizeof(bbe));
> +
> +   execbuf.buffers_ptr = to_user_pointer();
> +   execbuf.buffer_count = 1;
> +   execbuf.flags = engine | LOCAL_EXEC_FENCE_OUT;
> +
> +   gem_execbuf_wr(fd, );
> +   fence = execbuf.rsvd2 >> 32;
> +
> +   gem_close(fd, obj.handle);
> +   obj.handle = gem_create(fd, 4096);
> +   gem_write(fd, obj.handle, 0, , sizeof(bbe));

You don't need to recreate the batch here; just reusing the same handle
will do (and avoid the extra complication).

> +
> +   execbuf.flags |= LOCAL_EXEC_FENCE_IN;
> +   execbuf.rsvd2 = fence;
> +
> +   gem_execbuf_wr(fd, );
> +   igt_assert_eq(fence, execbuf.rsvd2 & 0x);

This would be a good one to throw to the interruptible wolves.

static void test_keep_fence_in(int fd, unsigned int engine, unsigned int flags)
#define INTR 0x1

...
igt_while_interruptible(flags & INTR)
gem_execbuf_wr(fd, );
igt_assert_eq(fence, lower_32_bits(execbuf.rsvd2));

igt_subtest_f("keep-fence-in-%s", e->name)
test_keep_fence_in(i915, e->exec_id | e->flags, 0);

igt_subtest_f("keep-fence-in-%s-interruptible", e->name)
test_keep_fence_in(i915, e->exec_id | e->flags, INTR);

> +
> +   gem_close(fd, obj.handle);
> +   close(fence);
> +   close(execbuf.rsvd2 >> 32);
> +}
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[Intel-gfx] [PATCH] drm: Add DPCD definitions for DP 1.4 FEC feature

[Anusha Srivatsa]

Forward Error Correction is supported on DP 1.4.
This patch adds corresponding DPCD register definitions.

v2: Add dri-devel mailing list to the CC list(Jani)

v3: Change names, add missing masks (Manasi)

v4: Add missing shifts to mask (Manasi)

v5: Arrange the definitions in ascending order
of the address (Jani)

v6: remove unnecessary definitions. Add missing masks,
add "/* 1.4 */" to offset definitions. (Jani)

Cc: dri-de...@lists.freedesktop.org
Cc: Ville Syrjala 
Cc: Jani Nikula 
Cc: Manasi Navare 
Signed-off-by: Anusha Srivatsa 
---
 include/drm/drm_dp_helper.h | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index c239e6e..4de97e9 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -329,6 +329,13 @@
 # define DP_DS_12BPC   2
 # define DP_DS_16BPC   3
 
+/* DP Forward error Correction Registers */
+#define DP_FEC_CAPABILITY  0x090/* 1.4 */
+# define DP_FEC_CAPABLE(1 << 0)
+# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP  (1 << 1)
+# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP(1 << 2)
+# define DP_FEC_BIT_ERROR_COUNT_CAP(1 << 3)
+
 /* link configuration */
 #defineDP_LINK_BW_SET  0x100
 # define DP_LINK_RATE_TABLE0x00/* eDP 1.4 */
@@ -445,6 +452,19 @@
 #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118   /* 1.2 */
 # define DP_PWR_NOT_NEEDED (1 << 0)
 
+#define DP_FEC_CONFIGURATION   0x120/* 1.4 */
+# define DP_FEC_READY  (1 << 0)
+# define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1)
+# define DP_FEC_ERR_COUNT_DIS  (0 << 1)
+# define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1)
+# define DP_FEC_CORR_BLK_ERROR_COUNT   (2 << 1)
+# define DP_FEC_BIT_ERROR_COUNT(3 << 1)
+# define DP_FEC_LANE_SELECT_MASK   (3 << 4)
+# define DP_FEC_LANE_0_SELECT  (0 << 4)
+# define DP_FEC_LANE_1_SELECT  (1 << 4)
+# define DP_FEC_LANE_2_SELECT  (2 << 4)
+# define DP_FEC_LANE_3_SELECT  (3 << 4)
+
 #define DP_AUX_FRAME_SYNC_VALUE0x15c   /* eDP 1.4 */
 # define DP_AUX_FRAME_SYNC_VALID   (1 << 0)
 
@@ -620,6 +640,16 @@
 #define DP_TEST_SINK   0x270
 # define DP_TEST_SINK_START(1 << 0)
 
+#define DP_FEC_STATUS  0x280/* 1.4 */
+# define DP_FEC_DECODE_EN_DETECTED (1 << 0)
+# define DP_FEC_DECODE_DIS_DETECTED(1 << 1)
+
+#define DP_FEC_ERROR_COUNT_LSB 0x0281/* 1.4 */
+
+#define DP_FEC_ERROR_COUNT_MSB 0x0282/* 1.4 */
+# define DP_FEC_ERROR_COUNT_MASK   0x7F
+# define DP_FEC_ERR_COUNT_VALID(1 << 7)
+
 #define DP_PAYLOAD_TABLE_UPDATE_STATUS  0x2c0   /* 1.2 MST */
 # define DP_PAYLOAD_TABLE_UPDATED   (1 << 0)
 # define DP_PAYLOAD_ACT_HANDLED (1 << 1)
-- 
2.7.4

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Re: [Intel-gfx] [PATCH] drm/i915: fix rsvd2 mask when out-fence is returned

[Chris Wilson]

Quoting Daniele Ceraolo Spurio (2018-02-14 19:18:25)
> GENMASK_ULL wants the high bit of the mask first. The current value
> cancels the in-fence when an out-fence is returned
> 
> Fixes: fec0445caa273 ("drm/i915: Support explicit fencing for execbuf")

Testcase: igt/gem_exec_fence/whatever-you-called-it

> Cc: Chris Wilson 
> Signed-off-by: Daniele Ceraolo Spurio 
> ---
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
> b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index b15305f2fb76..ed6e9db51e67 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -2410,7 +2410,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
> if (out_fence) {
> if (err == 0) {
> fd_install(out_fence_fd, out_fence->file);
> -   args->rsvd2 &= GENMASK_ULL(0, 31); /* keep in-fence */
> +   args->rsvd2 &= GENMASK_ULL(31, 0); /* keep in-fence */

OMG.

Reviewed-by: Chris Wilson 
-Chris
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[Intel-gfx] [PATCH 7/8] drm/i915: Change the COLOR_ENCODING prop default value to BT.709

[Ville Syrjala]

From: Ville Syrjälä 

Bring us forward from the stone age and switch our default YCbCr->RGB
conversion matrix to BT.709 from BT.601. I would expect most matrial
to be BT.709 these days.

Cc: Harry Wentland 
Cc: Daniel Vetter 
Cc: Daniel Stone 
Cc: Russell King - ARM Linux 
Cc: Ilia Mirkin 
Cc: Hans Verkuil 
Cc: Uma Shankar 
Cc: Shashank Sharma 
Cc: Jyri Sarha 
Acked-by: Shashank Sharma 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 drivers/gpu/drm/i915/intel_sprite.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 8c11d2a993a8..89c4bda91ecb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13326,7 +13326,7 @@ intel_primary_plane_create(struct drm_i915_private 
*dev_priv, enum pipe pipe)
  BIT(DRM_COLOR_YCBCR_BT601) |
  BIT(DRM_COLOR_YCBCR_BT709),
  
BIT(DRM_COLOR_YCBCR_LIMITED_RANGE),
- DRM_COLOR_YCBCR_BT601,
+ DRM_COLOR_YCBCR_BT709,
  
DRM_COLOR_YCBCR_LIMITED_RANGE);
 
drm_plane_helper_add(>base, _plane_helper_funcs);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 3a79a641a343..49969b2f3494 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1532,7 +1532,7 @@ intel_sprite_plane_create(struct drm_i915_private 
*dev_priv,
  BIT(DRM_COLOR_YCBCR_BT601) |
  BIT(DRM_COLOR_YCBCR_BT709),
  BIT(DRM_COLOR_YCBCR_LIMITED_RANGE),
- DRM_COLOR_YCBCR_BT601,
+ DRM_COLOR_YCBCR_BT709,
  DRM_COLOR_YCBCR_LIMITED_RANGE);
 
drm_plane_helper_add(_plane->base, _plane_helper_funcs);
-- 
2.13.6

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[Intel-gfx] [PATCH 8/8] drm/i915: Add support for the YCbCr COLOR_RANGE property

[Ville Syrjala]

From: Ville Syrjälä 

Add support for the COLOR_RANGE property on planes. This property
selects whether the input YCbCr data is to treated as limited range
or full range.

On most platforms this is a matter of setting the "YUV range correction
disable" bit, and on VLV/CHV we'll just have to program the color
correction logic to pass the data through unmodified.

v2: Rebase

Cc: Harry Wentland 
Cc: Daniel Vetter 
Cc: Daniel Stone 
Cc: Russell King - ARM Linux 
Cc: Ilia Mirkin 
Cc: Hans Verkuil 
Cc: Uma Shankar 
Cc: Shashank Sharma 
Cc: Jyri Sarha 
Reviewed-by: Shashank Sharma 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  |  4 
 drivers/gpu/drm/i915/intel_display.c |  9 -
 drivers/gpu/drm/i915/intel_sprite.c  | 12 ++--
 3 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6061f418c88d..405a651eea11 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6132,6 +6132,7 @@ enum {
 #define _DVSACNTR  0x72180
 #define   DVS_ENABLE   (1<<31)
 #define   DVS_GAMMA_ENABLE (1<<30)
+#define   DVS_YUV_RANGE_CORRECTION_DISABLE (1<<27)
 #define   DVS_PIXFORMAT_MASK   (3<<25)
 #define   DVS_FORMAT_YUV422(0<<25)
 #define   DVS_FORMAT_RGBX101010(1<<25)
@@ -6200,6 +6201,7 @@ enum {
 #define _SPRA_CTL  0x70280
 #define   SPRITE_ENABLE(1<<31)
 #define   SPRITE_GAMMA_ENABLE  (1<<30)
+#define   SPRITE_YUV_RANGE_CORRECTION_DISABLE  (1<<28)
 #define   SPRITE_PIXFORMAT_MASK(7<<25)
 #define   SPRITE_FORMAT_YUV422 (0<<25)
 #define   SPRITE_FORMAT_RGBX101010 (1<<25)
@@ -6391,6 +6393,7 @@ enum {
 #define _PLANE_CTL_3_A 0x70380
 #define   PLANE_CTL_ENABLE (1 << 31)
 #define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)   /* Pre-GLK */
+#define   PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE   (1 << 28)
 /*
  * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
  * expanded to include bit 23 as well. However, the shift-24 based values
@@ -6465,6 +6468,7 @@ enum {
 #define _PLANE_COLOR_CTL_2_A   0x702CC /* GLK+ */
 #define _PLANE_COLOR_CTL_3_A   0x703CC /* GLK+ */
 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30)
+#define   PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
 #define   PLANE_COLOR_PIPE_CSC_ENABLE  (1 << 23)
 #define   PLANE_COLOR_CSC_MODE_BYPASS  (0 << 17)
 #define   PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709(1 << 17)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 89c4bda91ecb..3d21eca18602 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3547,6 +3547,9 @@ u32 skl_plane_ctl(const struct intel_crtc_state 
*crtc_state,
 
if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
+
+   if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
+   plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
}
 
plane_ctl |= skl_plane_ctl_format(fb->format->format);
@@ -3581,6 +3584,9 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state 
*crtc_state,
plane_color_ctl |= 
PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
else
plane_color_ctl |= 
PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
+
+   if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
+   plane_color_ctl |= 
PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
}
 
return plane_color_ctl;
@@ -13325,7 +13331,8 @@ intel_primary_plane_create(struct drm_i915_private 
*dev_priv, enum pipe pipe)
drm_plane_create_color_properties(>base,
  BIT(DRM_COLOR_YCBCR_BT601) |
  BIT(DRM_COLOR_YCBCR_BT709),
- 
BIT(DRM_COLOR_YCBCR_LIMITED_RANGE),
+ 
BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
+ 
BIT(DRM_COLOR_YCBCR_FULL_RANGE),
  DRM_COLOR_YCBCR_BT709,
  
DRM_COLOR_YCBCR_LIMITED_RANGE);
 
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 49969b2f3494..dbdcf85032df 100644
--- 

[Intel-gfx] [PATCH 6/8] drm/i915: Add support for the YCbCr COLOR_ENCODING property

[Ville Syrjala]

From: Ville Syrjälä 

Add support for the COLOR_ENCODING plane property which selects
the matrix coefficients used for the YCbCr->RGB conversion. Our
hardware can generally handle BT.601 and BT.709.

CHV pipe B sprites have a fully programmable matrix, so in theory
we could handle anything, but it doesn't seem all that useful to
expose anything beyond BT.601 and BT.709 at this time.

GLK can supposedly do BT.2020, but let's leave enabling that for
the future as well.

v2: Rename bit defines to match the spec more closely (Shashank)

Cc: Harry Wentland 
Cc: Daniel Vetter 
Cc: Daniel Stone 
Cc: Russell King - ARM Linux 
Cc: Ilia Mirkin 
Cc: Hans Verkuil 
Cc: Uma Shankar 
Cc: Shashank Sharma 
Cc: Jyri Sarha 
Reviewed-by: Shashank Sharma 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  |  5 ++-
 drivers/gpu/drm/i915/intel_display.c | 19 +--
 drivers/gpu/drm/i915/intel_sprite.c  | 61 +++-
 3 files changed, 67 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6abeaf64c2d2..6061f418c88d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6140,6 +6140,7 @@ enum {
 #define   DVS_PIPE_CSC_ENABLE   (1<<24)
 #define   DVS_SOURCE_KEY   (1<<22)
 #define   DVS_RGB_ORDER_XBGR   (1<<20)
+#define   DVS_YUV_FORMAT_BT709 (1<<18)
 #define   DVS_YUV_BYTE_ORDER_MASK (3<<16)
 #define   DVS_YUV_ORDER_YUYV   (0<<16)
 #define   DVS_YUV_ORDER_UYVY   (1<<16)
@@ -6210,7 +6211,7 @@ enum {
 #define   SPRITE_SOURCE_KEY(1<<22)
 #define   SPRITE_RGB_ORDER_RGBX(1<<20) /* only for 888 and 
161616 */
 #define   SPRITE_YUV_TO_RGB_CSC_DISABLE(1<<19)
-#define   SPRITE_YUV_CSC_FORMAT_BT709  (1<<18) /* 0 is BT601 */
+#define   SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709   (1<<18) /* 0 is BT601 */
 #define   SPRITE_YUV_BYTE_ORDER_MASK   (3<<16)
 #define   SPRITE_YUV_ORDER_YUYV(0<<16)
 #define   SPRITE_YUV_ORDER_UYVY(1<<16)
@@ -6286,6 +6287,7 @@ enum {
 #define   SP_FORMAT_RGBA   (0xf<<26)
 #define   SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */
 #define   SP_SOURCE_KEY(1<<22)
+#define   SP_YUV_FORMAT_BT709  (1<<18)
 #define   SP_YUV_BYTE_ORDER_MASK   (3<<16)
 #define   SP_YUV_ORDER_YUYV(0<<16)
 #define   SP_YUV_ORDER_UYVY(1<<16)
@@ -6410,6 +6412,7 @@ enum {
 #define   PLANE_CTL_KEY_ENABLE_DESTINATION (  2 << 21)
 #define   PLANE_CTL_ORDER_BGRX (0 << 20)
 #define   PLANE_CTL_ORDER_RGBX (1 << 20)
+#define   PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709(1 << 18)
 #define   PLANE_CTL_YUV422_ORDER_MASK  (0x3 << 16)
 #define   PLANE_CTL_YUV422_YUYV(  0 << 16)
 #define   PLANE_CTL_YUV422_UYVY(  1 << 16)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index a22b583838f7..8c11d2a993a8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3544,6 +3544,9 @@ u32 skl_plane_ctl(const struct intel_crtc_state 
*crtc_state,
PLANE_CTL_PIPE_GAMMA_ENABLE |
PLANE_CTL_PIPE_CSC_ENABLE |
PLANE_CTL_PLANE_GAMMA_DISABLE;
+
+   if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
+   plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
}
 
plane_ctl |= skl_plane_ctl_format(fb->format->format);
@@ -3573,8 +3576,12 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state 
*crtc_state,
plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
 
-   if (intel_format_is_yuv(fb->format->format))
-   plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
+   if (intel_format_is_yuv(fb->format->format)) {
+   if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
+   plane_color_ctl |= 
PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
+   else
+   plane_color_ctl |= 
PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
+   }
 
return plane_color_ctl;
 }
@@ -13314,6 +13321,14 @@ intel_primary_plane_create(struct drm_i915_private 
*dev_priv, enum pipe pipe)
   DRM_MODE_ROTATE_0,
   supported_rotations);
 
+   if (INTEL_GEN(dev_priv) >= 9)
+   drm_plane_create_color_properties(>base,
+ 

[Intel-gfx] [PATCH 5/8] drm/i915: Fix plane YCbCr->RGB conversion for GLK

[Ville Syrjala]

From: Ville Syrjälä 

On GLK the plane CSC controls moved into the COLOR_CTL register.
Update the code to progam the YCbCr->RGB CSC mode correctly when
faced with an YCbCr framebuffer.

The spec is rather confusing as it calls the mode "YUV601 to RGB709".
I'm going to assume that just means it's going to use the YCbCr->RGB
matrix as specified in BT.601 and doesn't actually change the gamut.

Cc: Harry Wentland 
Cc: Daniel Vetter 
Cc: Daniel Stone 
Cc: Russell King - ARM Linux 
Cc: Ilia Mirkin 
Cc: Hans Verkuil 
Cc: Uma Shankar 
Cc: Shashank Sharma 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  |  5 +
 drivers/gpu/drm/i915/intel_display.c |  3 +++
 drivers/gpu/drm/i915/intel_drv.h |  2 ++
 drivers/gpu/drm/i915/intel_sprite.c  | 10 +-
 4 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 28b36eac064e..6abeaf64c2d2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6463,6 +6463,11 @@ enum {
 #define _PLANE_COLOR_CTL_3_A   0x703CC /* GLK+ */
 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30)
 #define   PLANE_COLOR_PIPE_CSC_ENABLE  (1 << 23)
+#define   PLANE_COLOR_CSC_MODE_BYPASS  (0 << 17)
+#define   PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709(1 << 17)
+#define   PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709(2 << 17)
+#define   PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020  (3 << 17)
+#define   PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020   (4 << 17)
 #define   PLANE_COLOR_PLANE_GAMMA_DISABLE  (1 << 13)
 #define   PLANE_COLOR_ALPHA_MASK   (0x3 << 4)
 #define   PLANE_COLOR_ALPHA_DISABLE(0 << 4)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 286a9591d179..a22b583838f7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3573,6 +3573,9 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state 
*crtc_state,
plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
 
+   if (intel_format_is_yuv(fb->format->format))
+   plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
+
return plane_color_ctl;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 898064e8bea7..6e43da40c859 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1591,6 +1591,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state 
*crtc_state,
const struct intel_plane_state *plane_state);
 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
  const struct intel_plane_state *plane_state);
+u32 glk_color_ctl(const struct intel_plane_state *plane_state);
 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
 unsigned int rotation);
 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
@@ -2016,6 +2017,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,
 
 
 /* intel_sprite.c */
+bool intel_format_is_yuv(u32 format);
 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
 int usecs);
 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private 
*dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index fac9e01b4795..b4acde2058fe 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -41,8 +41,7 @@
 #include 
 #include "i915_drv.h"
 
-static bool
-format_is_yuv(uint32_t format)
+bool intel_format_is_yuv(u32 format)
 {
switch (format) {
case DRM_FORMAT_YUYV:
@@ -266,6 +265,7 @@ skl_update_plane(struct intel_plane *plane,
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
  plane_state->color_ctl);
+
if (key->flags) {
I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
@@ -354,7 +354,7 @@ chv_update_csc(const struct intel_plane_state *plane_state)
enum plane_id plane_id = plane->id;
 
/* Seems RGB data bypasses the CSC always */
-   if (!format_is_yuv(fb->format->format))
+   if (!intel_format_is_yuv(fb->format->format))
return;
 
/*
@@ -399,7 +399,7 @@ vlv_update_clrc(const struct intel_plane_state *plane_state)
enum plane_id plane_id = plane->id;
int 

[Intel-gfx] [PATCH 3/8] drm/atomic: Include color encoding/range in plane state dump

[Ville Syrjala]

From: Ville Syrjälä 

Include color_enconding and color_range in the plane state dump.

Cc: Harry Wentland 
Cc: Daniel Vetter 
Cc: Daniel Stone 
Cc: Russell King - ARM Linux 
Cc: Ilia Mirkin 
Cc: Hans Verkuil 
Cc: Uma Shankar 
Cc: Shashank Sharma 
Cc: Jyri Sarha 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/drm_atomic.c|  4 
 drivers/gpu/drm/drm_color_mgmt.c| 16 
 drivers/gpu/drm/drm_crtc_internal.h |  2 ++
 3 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 452a0b0bafbc..9552052ed31a 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -952,6 +952,10 @@ static void drm_atomic_plane_print_state(struct 
drm_printer *p,
drm_printf(p, "\tcrtc-pos=" DRM_RECT_FMT "\n", DRM_RECT_ARG());
drm_printf(p, "\tsrc-pos=" DRM_RECT_FP_FMT "\n", DRM_RECT_FP_ARG());
drm_printf(p, "\trotation=%x\n", state->rotation);
+   drm_printf(p, "\tcolor-encoding=%s\n",
+  drm_get_color_encoding_name(state->color_encoding));
+   drm_printf(p, "\tcolor-range=%s\n",
+  drm_get_color_range_name(state->color_range));
 
if (plane->funcs->atomic_print_state)
plane->funcs->atomic_print_state(p, state);
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index 061d342f9d96..06851d575f14 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -365,6 +365,22 @@ static const char * const color_range_name[] = {
[DRM_COLOR_YCBCR_LIMITED_RANGE] = "YCbCr limited range",
 };
 
+const char *drm_get_color_encoding_name(enum drm_color_encoding encoding)
+{
+   if (WARN_ON(encoding >= ARRAY_SIZE(color_encoding_name)))
+   return "unknown";
+
+   return color_encoding_name[encoding];
+}
+
+const char *drm_get_color_range_name(enum drm_color_range range)
+{
+   if (WARN_ON(range >= ARRAY_SIZE(color_range_name)))
+   return "unknown";
+
+   return color_range_name[range];
+}
+
 /**
  * drm_plane_create_color_properties - color encoding related plane properties
  * @supported_encodings: bitfield indicating supported color encodings
diff --git a/drivers/gpu/drm/drm_crtc_internal.h 
b/drivers/gpu/drm/drm_crtc_internal.h
index af00f42ba269..8ca2ffef6231 100644
--- a/drivers/gpu/drm/drm_crtc_internal.h
+++ b/drivers/gpu/drm/drm_crtc_internal.h
@@ -71,6 +71,8 @@ int drm_mode_destroy_dumb_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv);
 
 /* drm_color_mgmt.c */
+const char *drm_get_color_encoding_name(enum drm_color_encoding encoding);
+const char *drm_get_color_range_name(enum drm_color_range range);
 
 /* IOCTLs */
 int drm_mode_gamma_get_ioctl(struct drm_device *dev,
-- 
2.13.6

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[Intel-gfx] [PATCH 4/8] drm/i915: Correctly handle limited range YCbCr data on VLV/CHV

[Ville Syrjala]

From: Ville Syrjälä 

Turns out the VLV/CHV fixed function sprite CSC expects full range
data as input. We've been feeding it limited range data to it all
along. To expand the data out to full range we'll use the color
correction registers (brightness, contrast, and saturation).

On CHV pipe B we were actually doing the right thing already because we
progammed the custom CSC matrix to do expect limited range input. Now
that well pre-expand the data out with the color correction unit, we
need to change the CSC matrix to operate with full range input instead.

This should make the sprite output of the other pipes match the sprite
output of pipe B reasonably well. Looking at the resulting pipe CRCs,
there can be a slight difference in the output, but as I don't know
the formula used by the fixed function CSC of the other pipes, I don't
think it's worth the effort to try to match the output exactly. It
might not even be possible due to difference in internal precision etc.

One slight caveat here is that the color correction registers are single
bufferred, so we should really be updating them during vblank, but we
still don't have a mechanism for that, so just toss in another FIXME.

v2: Rebase
v3: s/bri/brightness/ s/con/contrast/ (Shashank)
v4: Clarify the constants and math (Shashank)

Cc: Harry Wentland 
Cc: Daniel Vetter 
Cc: Daniel Stone 
Cc: Russell King - ARM Linux 
Cc: Ilia Mirkin 
Cc: Hans Verkuil 
Cc: Shashank Sharma 
Cc: Uma Shankar 
Cc: Jyri Sarha 
Cc: "Tang, Jun" 
Reported-by: "Tang, Jun" 
Cc: sta...@vger.kernel.org
Fixes: 7f1f3851feb0 ("drm/i915: sprite support for ValleyView v4")
Reviewed-by: Shashank Sharma 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h | 10 +
 drivers/gpu/drm/i915/intel_sprite.c | 81 -
 2 files changed, 73 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f6afa5e5e7c1..28b36eac064e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6305,6 +6305,12 @@ enum {
 #define _SPATILEOFF(VLV_DISPLAY_BASE + 0x721a4)
 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
 #define   SP_CONST_ALPHA_ENABLE(1<<31)
+#define _SPACLRC0  (VLV_DISPLAY_BASE + 0x721d0)
+#define   SP_CONTRAST(x)   ((x) << 18) /* u3.6 */
+#define   SP_BRIGHTNESS(x) ((x) & 0xff) /* s8 */
+#define _SPACLRC1  (VLV_DISPLAY_BASE + 0x721d4)
+#define   SP_SH_SIN(x) (((x) & 0x7ff) << 16) /* s4.7 */
+#define   SP_SH_COS(x) (x) /* u3.7 */
 #define _SPAGAMC   (VLV_DISPLAY_BASE + 0x721f4)
 
 #define _SPBCNTR   (VLV_DISPLAY_BASE + 0x72280)
@@ -6318,6 +6324,8 @@ enum {
 #define _SPBKEYMAXVAL  (VLV_DISPLAY_BASE + 0x722a0)
 #define _SPBTILEOFF(VLV_DISPLAY_BASE + 0x722a4)
 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
+#define _SPBCLRC0  (VLV_DISPLAY_BASE + 0x722d0)
+#define _SPBCLRC1  (VLV_DISPLAY_BASE + 0x722d4)
 #define _SPBGAMC   (VLV_DISPLAY_BASE + 0x722f4)
 
 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
@@ -6334,6 +6342,8 @@ enum {
 #define SPKEYMAXVAL(pipe, plane_id)_MMIO_VLV_SPR((pipe), (plane_id), 
_SPAKEYMAXVAL, _SPBKEYMAXVAL)
 #define SPTILEOFF(pipe, plane_id)  _MMIO_VLV_SPR((pipe), (plane_id), 
_SPATILEOFF, _SPBTILEOFF)
 #define SPCONSTALPHA(pipe, plane_id)   _MMIO_VLV_SPR((pipe), (plane_id), 
_SPACONSTALPHA, _SPBCONSTALPHA)
+#define SPCLRC0(pipe, plane_id)_MMIO_VLV_SPR((pipe), 
(plane_id), _SPACLRC0, _SPBCLRC0)
+#define SPCLRC1(pipe, plane_id)_MMIO_VLV_SPR((pipe), 
(plane_id), _SPACLRC1, _SPBCLRC1)
 #define SPGAMC(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), 
_SPAGAMC, _SPBGAMC)
 
 /*
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index e098e4b2c85c..fac9e01b4795 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -346,44 +346,87 @@ skl_plane_get_hw_state(struct intel_plane *plane)
 }
 
 static void
-chv_update_csc(struct intel_plane *plane, uint32_t format)
+chv_update_csc(const struct intel_plane_state *plane_state)
 {
+   struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+   const struct drm_framebuffer *fb = plane_state->base.fb;
enum plane_id plane_id = plane->id;
 
/* Seems RGB data bypasses the CSC always */
-   if (!format_is_yuv(format))
+   if 

[Intel-gfx] [PATCH 0/8] drm: Add COLOR_ENCODING and COLOR_RANGE plane properties

[Ville Syrjala]

From: Ville Syrjälä 

Here's a refresh of Jyri's COLOR_ENCODING and COLOR_RANGE properties,
and the i915 implementation I did on top. I tossed in a few core
updates as well: plane state dump, and the BT.2020 constant luminance
variant.

Apparently nouveau is already exposing a "iturbt_709" bool property
which allows one to choose between BT.601 and BT.709 encodings, but
given that we want at least BT.2020 in addition I don't think that
property is good enough. Trying to implement it, and somehow extend
it beyond BT.601 vs. BT.709 seems like wasted effort. Hence I think
we should just ignore it and move on.

My userspace implementation in the form of intel ddx
XV_COLORSPACE attribute:
https://patchwork.freedesktop.org/patch/204696/

Cc: Harry Wentland 
Cc: Daniel Vetter 
Cc: Daniel Stone 
Cc: Russell King - ARM Linux 
Cc: Ilia Mirkin 
Cc: Hans Verkuil 
Cc: Uma Shankar 
Cc: Shashank Sharma 

Jyri Sarha (1):
  drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to
drm_plane

Ville Syrjälä (7):
  drm: Add BT.2020 constant luminance enum value for the COLOR_ENCODING
property
  drm/atomic: Include color encoding/range in plane state dump
  drm/i915: Correctly handle limited range YCbCr data on VLV/CHV
  drm/i915: Fix plane YCbCr->RGB conversion for GLK
  drm/i915: Add support for the YCbCr COLOR_ENCODING property
  drm/i915: Change the COLOR_ENCODING prop default value to BT.709
  drm/i915: Add support for the YCbCr COLOR_RANGE property

 drivers/gpu/drm/drm_atomic.c |  12 
 drivers/gpu/drm/drm_color_mgmt.c | 108 
 drivers/gpu/drm/drm_crtc_internal.h  |   2 +
 drivers/gpu/drm/i915/i915_reg.h  |  24 ++-
 drivers/gpu/drm/i915/intel_display.c |  25 +++
 drivers/gpu/drm/i915/intel_drv.h |   2 +
 drivers/gpu/drm/i915/intel_sprite.c  | 134 ---
 include/drm/drm_color_mgmt.h |  20 ++
 include/drm/drm_plane.h  |   8 +++
 9 files changed, 309 insertions(+), 26 deletions(-)

-- 
2.13.6

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[Intel-gfx] [PATCH 1/8] drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to drm_plane

[Ville Syrjala]

From: Jyri Sarha 

Add a standard optional properties to support different non RGB color
encodings in DRM planes. COLOR_ENCODING select the supported non RGB
color encoding, for instance ITU-R BT.709 YCbCr. COLOR_RANGE selects
the value ranges within the selected color encoding. The properties
are stored to drm_plane object to allow different set of supported
encoding for different planes on the device.

Cc: Harry Wentland 
Cc: Daniel Vetter 
Cc: Daniel Stone 
Cc: Russell King - ARM Linux 
Cc: Ilia Mirkin 
Cc: Hans Verkuil 
Cc: Uma Shankar 
Cc: Shashank Sharma 
Reviewed-by: Ville Syrjälä 
Signed-off-by: Jyri Sarha 
---
 drivers/gpu/drm/drm_atomic.c |  8 
 drivers/gpu/drm/drm_color_mgmt.c | 91 
 include/drm/drm_color_mgmt.h | 19 +
 include/drm/drm_plane.h  |  8 
 4 files changed, 126 insertions(+)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 46733d534587..452a0b0bafbc 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -759,6 +759,10 @@ static int drm_atomic_plane_set_property(struct drm_plane 
*plane,
state->rotation = val;
} else if (property == plane->zpos_property) {
state->zpos = val;
+   } else if (property == plane->color_encoding_property) {
+   state->color_encoding = val;
+   } else if (property == plane->color_range_property) {
+   state->color_range = val;
} else if (plane->funcs->atomic_set_property) {
return plane->funcs->atomic_set_property(plane, state,
property, val);
@@ -818,6 +822,10 @@ drm_atomic_plane_get_property(struct drm_plane *plane,
*val = state->rotation;
} else if (property == plane->zpos_property) {
*val = state->zpos;
+   } else if (property == plane->color_encoding_property) {
+   *val = state->color_encoding;
+   } else if (property == plane->color_range_property) {
+   *val = state->color_range;
} else if (plane->funcs->atomic_get_property) {
return plane->funcs->atomic_get_property(plane, state, 
property, val);
} else {
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index 0d002b045bd2..a84fc861e406 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -88,6 +88,19 @@
  * drm_mode_crtc_set_gamma_size(). Drivers which support both should use
  * drm_atomic_helper_legacy_gamma_set() to alias the legacy gamma ramp with the
  * "GAMMA_LUT" property above.
+ *
+ * Support for different non RGB color encodings is controlled through
+ * _plane specific COLOR_ENCODING and COLOR_RANGE properties:
+ *
+ * "COLOR_ENCODING"
+ * Optional plane enum property to support different non RGB
+ * color encodings. The driver can provide a subset of standard
+ * enum values supported by the DRM plane.
+ *
+ * "COLOR_RANGE"
+ * Optional plane enum property to support different non RGB
+ * color parameter ranges. The driver can provide a subset of
+ * standard enum values supported by the DRM plane.
  */
 
 /**
@@ -339,3 +352,81 @@ int drm_mode_gamma_get_ioctl(struct drm_device *dev,
drm_modeset_unlock(>mutex);
return ret;
 }
+
+static const char * const color_encoding_name[] = {
+   [DRM_COLOR_YCBCR_BT601] = "ITU-R BT.601 YCbCr",
+   [DRM_COLOR_YCBCR_BT709] = "ITU-R BT.709 YCbCr",
+   [DRM_COLOR_YCBCR_BT2020] = "ITU-R BT.2020 YCbCr",
+};
+
+static const char * const color_range_name[] = {
+   [DRM_COLOR_YCBCR_FULL_RANGE] = "YCbCr full range",
+   [DRM_COLOR_YCBCR_LIMITED_RANGE] = "YCbCr limited range",
+};
+
+/**
+ * drm_plane_create_color_properties - color encoding related plane properties
+ * @supported_encodings: bitfield indicating supported color encodings
+ * @supported_ranges: bitfileld indicating supported color ranges
+ * @default_encoding: default color encoding
+ * @default_range: default color range
+ *
+ * Create and attach plane specific COLOR_ENCODING and COLOR_RANGE
+ * properties to to the drm_plane object. The supported encodings and
+ * ranges should be provided in supported_encodings and
+ * supported_ranges bitmasks. Each bit set in the bitmask indicates
+ * the its number as enum value being supported.
+ */
+int drm_plane_create_color_properties(struct drm_plane *plane,
+ u32 supported_encodings,
+ u32 supported_ranges,
+ enum drm_color_encoding default_encoding,
+ enum drm_color_range default_range)
+{
+   

[Intel-gfx] [PATCH 2/8] drm: Add BT.2020 constant luminance enum value for the COLOR_ENCODING property

[Ville Syrjala]

From: Ville Syrjälä 

BT.2020 specifies two YCbCr<->RGB conversion formulas. The more
traditional non-constant luminance and a more complicate one constant
luminance one. Add an enum value for the constant luminance variant
as well in case someone has hardware supporting it.

Cc: Harry Wentland 
Cc: Daniel Vetter 
Cc: Daniel Stone 
Cc: Russell King - ARM Linux 
Cc: Ilia Mirkin 
Cc: Hans Verkuil 
CC: Uma Shankar 
Cc: Shashank Sharma 
Cc: Jyri Sarha 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/drm_color_mgmt.c | 1 +
 include/drm/drm_color_mgmt.h | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index a84fc861e406..061d342f9d96 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -357,6 +357,7 @@ static const char * const color_encoding_name[] = {
[DRM_COLOR_YCBCR_BT601] = "ITU-R BT.601 YCbCr",
[DRM_COLOR_YCBCR_BT709] = "ITU-R BT.709 YCbCr",
[DRM_COLOR_YCBCR_BT2020] = "ITU-R BT.2020 YCbCr",
+   [DRM_COLOR_YCBCR_BT2020_CONST] = "ITU-R BT.2020 YCbCr constant 
luminance",
 };
 
 static const char * const color_range_name[] = {
diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
index b3b6d302ca8c..175943c87d5b 100644
--- a/include/drm/drm_color_mgmt.h
+++ b/include/drm/drm_color_mgmt.h
@@ -41,7 +41,8 @@ int drm_mode_crtc_set_gamma_size(struct drm_crtc *crtc,
 enum drm_color_encoding {
DRM_COLOR_YCBCR_BT601,
DRM_COLOR_YCBCR_BT709,
-   DRM_COLOR_YCBCR_BT2020,
+   DRM_COLOR_YCBCR_BT2020, /* non-constant luminance */
+   DRM_COLOR_YCBCR_BT2020_CONST, /* constant luminance */
DRM_COLOR_ENCODING_MAX,
 };
 
-- 
2.13.6

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[Intel-gfx] [PATCH xf86-video-intel] sna: Add XV_COLORSPACE attribute support for sprite Xv adaptors

[Ville Syrjala]

From: Ville Syrjälä 

Use the new "COLOR_ENCODING" plane property to implement the
XV_COLORSPACE port attribute for sprite Xv adaptors.

Cc: Jyri Sarha 
Cc: Chris Wilson 
Signed-off-by: Ville Syrjälä 
---
 src/sna/sna.h  |   1 +
 src/sna/sna_display.c  | 148 +++--
 src/sna/sna_video.h|   3 +
 src/sna/sna_video_sprite.c |  22 ++-
 4 files changed, 142 insertions(+), 32 deletions(-)

diff --git a/src/sna/sna.h b/src/sna/sna.h
index 5283ce436a3b..c9097d3db158 100644
--- a/src/sna/sna.h
+++ b/src/sna/sna.h
@@ -634,6 +634,7 @@ static inline void sna_present_cancel_flip(struct sna *sna) 
{ }
 
 extern unsigned sna_crtc_count_sprites(xf86CrtcPtr crtc);
 extern bool sna_crtc_set_sprite_rotation(xf86CrtcPtr crtc, unsigned idx, 
uint32_t rotation);
+extern void sna_crtc_set_sprite_colorspace(xf86CrtcPtr crtc, unsigned idx, int 
colorspace);
 extern uint32_t sna_crtc_to_sprite(xf86CrtcPtr crtc, unsigned idx);
 extern bool sna_crtc_is_transformed(xf86CrtcPtr crtc);
 
diff --git a/src/sna/sna_display.c b/src/sna/sna_display.c
index ea2f148d213c..86aa711f886d 100644
--- a/src/sna/sna_display.c
+++ b/src/sna/sna_display.c
@@ -222,6 +222,10 @@ struct sna_crtc {
uint32_t supported;
uint32_t current;
} rotation;
+   struct {
+   uint32_t prop;
+   uint64_t values[2];
+   } color_encoding;
struct list link;
} primary;
struct list sprites;
@@ -3293,17 +3297,124 @@ static const xf86CrtcFuncsRec sna_crtc_funcs = {
 #endif
 };
 
-inline static bool prop_is_rotation(struct drm_mode_get_property *prop)
+inline static bool prop_has_type_and_name(const struct drm_mode_get_property 
*prop,
+ unsigned int type, const char *name)
 {
-   if ((prop->flags & (1 << 5)) == 0)
+   if ((prop->flags & (1 << type)) == 0)
return false;
 
-   if (strcmp(prop->name, "rotation"))
+   if (strcmp(prop->name, name))
return false;
 
return true;
 }
 
+inline static bool prop_is_rotation(const struct drm_mode_get_property *prop)
+{
+   return prop_has_type_and_name(prop, 5, "rotation");
+}
+
+static void parse_rotation_prop(struct sna *sna, struct plane *p,
+   struct drm_mode_get_property *prop,
+   uint64_t value)
+{
+   struct drm_mode_property_enum *enums;
+   int j;
+
+   p->rotation.prop = prop->prop_id;
+   p->rotation.current = value;
+
+   DBG(("%s: found rotation property .id=%d, value=%ld, num_enums=%d\n",
+__FUNCTION__, prop->prop_id, value, prop->count_enum_blobs));
+
+   enums = malloc(prop->count_enum_blobs * sizeof(struct 
drm_mode_property_enum));
+   if (!enums)
+   return;
+
+   prop->count_values = 0;
+   prop->enum_blob_ptr = (uintptr_t)enums;
+
+   if (drmIoctl(sna->kgem.fd, DRM_IOCTL_MODE_GETPROPERTY, prop)) {
+   free(enums);
+   return;
+   }
+
+   /* XXX we assume that the mapping between kernel enum and
+* RandR remains fixed for our lifetimes.
+*/
+   VG(VALGRIND_MAKE_MEM_DEFINED(enums, 
sizeof(*enums)*prop->count_enum_blobs));
+   for (j = 0; j < prop->count_enum_blobs; j++) {
+   DBG(("%s: rotation[%d] = %s [%lx]\n", __FUNCTION__,
+j, enums[j].name, (long)enums[j].value));
+   p->rotation.supported |= 1 << enums[j].value;
+   }
+
+   free(enums);
+}
+
+inline static bool prop_is_color_encoding(const struct drm_mode_get_property 
*prop)
+{
+   return prop_has_type_and_name(prop, 3, "COLOR_ENCODING");
+}
+
+static void parse_color_encoding_prop(struct sna *sna, struct plane *p,
+ struct drm_mode_get_property *prop,
+ uint64_t value)
+{
+   struct drm_mode_property_enum *enums;
+   unsigned int supported = 0;
+   int j;
+
+   DBG(("%s: found color encoding property .id=%d, value=%ld, 
num_enums=%d\n",
+__FUNCTION__, prop->prop_id, (long)value, prop->count_enum_blobs));
+
+   enums = malloc(prop->count_enum_blobs * sizeof(struct 
drm_mode_property_enum));
+   if (!enums)
+   return;
+
+   prop->count_values = 0;
+   prop->enum_blob_ptr = (uintptr_t)enums;
+
+   if (drmIoctl(sna->kgem.fd, DRM_IOCTL_MODE_GETPROPERTY, prop)) {
+   free(enums);
+   return;
+   }
+
+   VG(VALGRIND_MAKE_MEM_DEFINED(enums, 
sizeof(*enums)*prop->count_enum_blobs));
+   for (j = 0; j < prop->count_enum_blobs; j++) {
+   if (!strcmp(enums[j].name, "ITU-R BT.601 YCbCr")) {
+   p->color_encoding.values[0] = 

Re: [Intel-gfx] [RFC 0/5] Per-client engine stats

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-14 18:50:30)
> From: Tvrtko Ursulin 
> 
> Another re-post of my earlier, now slightly updated work, to expose a DRM 
> client
> hierarchy in sysfs in order to enable a top like tool:

So what I don't like about it is that it is a new interface in sysfs. We
already have a PMU interface for statistics and would rather see that
extended than abandoned. If perf can handle new processes coming and
going, surely we can handle new clients? :|
-Chris
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[Intel-gfx] [PATCH i-g-t] tests/gem_exec_fence: test that in-fence is not overwritten

[Daniele Ceraolo Spurio]

When an out-fence is returned we expect that the in-fence is not
overwritten. Add a test to check for that.

Cc: Chris Wilson 
Signed-off-by: Daniele Ceraolo Spurio 
---
 tests/gem_exec_fence.c | 39 +++
 1 file changed, 39 insertions(+)

diff --git a/tests/gem_exec_fence.c b/tests/gem_exec_fence.c
index bd7b1263..f7478c55 100644
--- a/tests/gem_exec_fence.c
+++ b/tests/gem_exec_fence.c
@@ -586,6 +586,42 @@ static void test_parallel(int fd, unsigned int master)
gem_close(fd, handle[0]);
 }
 
+/* check that a fence in doesn't get clobbered when a fence out is returned */
+static void test_keep_fence_in(int fd, unsigned int engine)
+{
+   struct drm_i915_gem_execbuffer2 execbuf;
+   struct drm_i915_gem_exec_object2 obj;
+   const uint32_t bbe = MI_BATCH_BUFFER_END;
+   int fence;
+
+   memset(, 0, sizeof(obj));
+   memset(, 0, sizeof(execbuf));
+
+   obj.handle = gem_create(fd, 4096);
+   gem_write(fd, obj.handle, 0, , sizeof(bbe));
+
+   execbuf.buffers_ptr = to_user_pointer();
+   execbuf.buffer_count = 1;
+   execbuf.flags = engine | LOCAL_EXEC_FENCE_OUT;
+
+   gem_execbuf_wr(fd, );
+   fence = execbuf.rsvd2 >> 32;
+
+   gem_close(fd, obj.handle);
+   obj.handle = gem_create(fd, 4096);
+   gem_write(fd, obj.handle, 0, , sizeof(bbe));
+
+   execbuf.flags |= LOCAL_EXEC_FENCE_IN;
+   execbuf.rsvd2 = fence;
+
+   gem_execbuf_wr(fd, );
+   igt_assert_eq(fence, execbuf.rsvd2 & 0x);
+
+   gem_close(fd, obj.handle);
+   close(fence);
+   close(execbuf.rsvd2 >> 32);
+}
+
 #define EXPIRED 0x1
 static void test_long_history(int fd, long ring_size, unsigned flags)
 {
@@ -1499,6 +1535,9 @@ igt_main
}
}
 
+   igt_subtest_f("keep-fence-in-%s", e->name)
+   test_keep_fence_in(i915, e->exec_id | 
e->flags);
+
igt_fixture {
igt_stop_hang_detector();
}
-- 
2.16.1

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[Intel-gfx] [PATCH] drm/i915: fix rsvd2 mask when out-fence is returned

[Daniele Ceraolo Spurio]

GENMASK_ULL wants the high bit of the mask first. The current value
cancels the in-fence when an out-fence is returned

Fixes: fec0445caa273 ("drm/i915: Support explicit fencing for execbuf")
Cc: Chris Wilson 
Signed-off-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index b15305f2fb76..ed6e9db51e67 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -2410,7 +2410,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (out_fence) {
if (err == 0) {
fd_install(out_fence_fd, out_fence->file);
-   args->rsvd2 &= GENMASK_ULL(0, 31); /* keep in-fence */
+   args->rsvd2 &= GENMASK_ULL(31, 0); /* keep in-fence */
args->rsvd2 |= (u64)out_fence_fd << 32;
out_fence_fd = -1;
} else {
-- 
2.16.1

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Re: [Intel-gfx] [RFC 4/5] drm/i915: Expose per-engine client busyness

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-14 18:50:34)
> From: Tvrtko Ursulin 
> 
> Expose per-client and per-engine busyness under the previously added sysfs
> client root.
> 
> The new files are one per-engine instance and located under the 'busy'
> directory.
> 
> Each contains a monotonically increasing nano-second resolution times each
> client's jobs were executing on the GPU.
> 
> $ cat /sys/class/drm/card0/clients/5/busy/rcs0
> 32516602
> 
> This data can serve as an interface to implement a top like utility for
> GPU jobs. For instance I have prototyped a tool in IGT which produces
> periodic output like:
> 
> neverball[  6011]:  rcs0:  41.01%  bcs0:   0.00%  vcs0:   0.00%  vecs0:   
> 0.00%
>  Xorg[  5664]:  rcs0:  31.16%  bcs0:   0.00%  vcs0:   0.00%  vecs0:   
> 0.00%
> xfwm4[  5727]:  rcs0:   0.00%  bcs0:   0.00%  vcs0:   0.00%  vecs0:   
> 0.00%
> 
> This tools can also be extended to use the i915 PMU and show overall engine
> busyness, and engine loads using the queue depth metric.
> 
> v2: Use intel_context_engine_get_busy_time.
> v3: New directory structure.
> 
> Signed-off-by: Tvrtko Ursulin 
> ---
>  drivers/gpu/drm/i915/i915_drv.h |  8 
>  drivers/gpu/drm/i915/i915_gem.c | 86 
> +++--
>  2 files changed, 91 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 372d13cb2472..d6b2883b42fe 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -315,6 +315,12 @@ struct drm_i915_private;
>  struct i915_mm_struct;
>  struct i915_mmu_object;
>  
> +struct i915_engine_busy_attribute {
> +   struct device_attribute attr;
> +   struct drm_i915_file_private *file_priv;
> +   struct intel_engine_cs *engine;
> +};
> +
>  struct drm_i915_file_private {
> struct drm_i915_private *dev_priv;
> struct drm_file *file;
> @@ -350,10 +356,12 @@ struct drm_i915_file_private {
> unsigned int client_pid;
> char *client_name;
> struct kobject *client_root;
> +   struct kobject *busy_root;
>  
> struct {
> struct device_attribute pid;
> struct device_attribute name;
> +   struct i915_engine_busy_attribute busy[I915_NUM_ENGINES];
> } attr;
>  };
>  
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 46ac7b3ca348..01298d924524 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -5631,6 +5631,45 @@ show_client_pid(struct device *kdev, struct 
> device_attribute *attr, char *buf)
> return snprintf(buf, PAGE_SIZE, "%u", file_priv->client_pid);
>  }
>  
> +struct busy_ctx {
> +   struct intel_engine_cs *engine;
> +   u64 total;
> +};
> +
> +static int busy_add(int _id, void *p, void *data)
> +{
> +   struct i915_gem_context *ctx = p;
> +   struct busy_ctx *bc = data;
> +
> +   bc->total +=
> +   ktime_to_ns(intel_context_engine_get_busy_time(ctx,
> +  bc->engine));
> +
> +   return 0;
> +}
> +
> +static ssize_t
> +show_client_busy(struct device *kdev, struct device_attribute *attr, char 
> *buf)
> +{
> +   struct i915_engine_busy_attribute *i915_attr =
> +   container_of(attr, typeof(*i915_attr), attr);
> +   struct drm_i915_file_private *file_priv = i915_attr->file_priv;
> +   struct intel_engine_cs *engine = i915_attr->engine;
> +   struct drm_i915_private *i915 = engine->i915;
> +   struct busy_ctx bc = { .engine = engine };
> +   int ret;
> +
> +   ret = i915_mutex_lock_interruptible(>drm);
> +   if (ret)
> +   return ret;
> +

Doesn't need struct_mutex, just rcu_read_lock() will suffice.

Neither the context nor idr will be freed too soon, and the data is
involatile when the context is unreffed (and contexts don't have the
nasty zombie/undead status of requests). So the busy-time will be
stable.
-Chris
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Re: [Intel-gfx] [RFC 2/5] drm/i915: Expose list of clients in sysfs

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-14 18:50:32)
> From: Tvrtko Ursulin 
> 
> Expose a list of clients with open file handles in sysfs.
> 
> This will be a basis for a top-like utility showing per-client and per-
> engine GPU load.
> 
> Currently we only expose each client's pid and name under opaque numbered
> directories in /sys/class/drm/card0/clients/.
> 
> For instance:
> 
> /sys/class/drm/card0/clients/3/name: Xorg
> /sys/class/drm/card0/clients/3/pid: 5664
> 
> Signed-off-by: Tvrtko Ursulin 
> ---
>  drivers/gpu/drm/i915/i915_drv.h   |  13 +
>  drivers/gpu/drm/i915/i915_gem.c   | 112 
> +++---
>  drivers/gpu/drm/i915/i915_sysfs.c |   8 +++
>  3 files changed, 126 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 70cf289855af..2133e67f5fbc 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -345,6 +345,16 @@ struct drm_i915_file_private {
>   */
>  #define I915_MAX_CLIENT_CONTEXT_BANS 3
> atomic_t context_bans;
> +

struct {

> +   unsigned int client_sysfs_id;
> +   unsigned int client_pid;
> +   char *client_name;
> +   struct kobject *client_root;

} client;

> +
> +   struct {
> +   struct device_attribute pid;
> +   struct device_attribute name;
> +   } attr;

sysfs_attr?

>  };
>  
>  /* Interface history:
> @@ -2365,6 +2375,9 @@ struct drm_i915_private {
>  
> struct i915_pmu pmu;
>  
> +   struct kobject *clients_root;
> +   atomic_t client_serial;

I'd start a new substruct { } clients;

> /*
>  * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your 
> patch
>  * will be rejected. Instead look for a better place.
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index fc68b35854df..24607bce2efe 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -5613,6 +5613,89 @@ int i915_gem_freeze_late(struct drm_i915_private 
> *dev_priv)
> return 0;
>  }
>  
> +static ssize_t
> +show_client_name(struct device *kdev, struct device_attribute *attr, char 
> *buf)
> +{
> +   struct drm_i915_file_private *file_priv =
> +   container_of(attr, struct drm_i915_file_private, attr.name);
> +
> +   return snprintf(buf, PAGE_SIZE, "%s", file_priv->client_name);
> +}
> +
> +static ssize_t
> +show_client_pid(struct device *kdev, struct device_attribute *attr, char 
> *buf)
> +{
> +   struct drm_i915_file_private *file_priv =
> +   container_of(attr, struct drm_i915_file_private, attr.pid);
> +
> +   return snprintf(buf, PAGE_SIZE, "%u", file_priv->client_pid);
> +}
> +
> +static int
> +i915_gem_add_client(struct drm_i915_private *i915,
> +   struct drm_i915_file_private *file_priv,
> +   struct task_struct *task,
> +   unsigned int serial)
> +{
> +   int ret = -ENOMEM;
> +   struct device_attribute *attr;
> +   char id[32];
> +
> +   file_priv->client_name = kstrdup(task->comm, GFP_KERNEL);
> +   if (!file_priv->client_name)
> +   goto err_name;
> +
> +   snprintf(id, sizeof(id), "%u", serial);
> +   file_priv->client_root = kobject_create_and_add(id,
> +   i915->clients_root);

Do we have to care about i915->clients_root being NULL here?

> +   if (!file_priv->client_root)
> +   goto err_client;
> +
> +   attr = _priv->attr.name;
> +   attr->attr.name = "name";
> +   attr->attr.mode = 0444;
> +   attr->show = show_client_name;
> +
> +   ret = sysfs_create_file(file_priv->client_root,
> +   (struct attribute *)attr);
> +   if (ret)
> +   goto err_attr_name;
> +
> +   attr = _priv->attr.pid;
> +   attr->attr.name = "pid";
> +   attr->attr.mode = 0444;
> +   attr->show = show_client_pid;
> +
> +   ret = sysfs_create_file(file_priv->client_root,
> +   (struct attribute *)attr);
> +   if (ret)
> +   goto err_attr_pid;
> +
> +   file_priv->client_pid = pid_nr(get_task_pid(task, PIDTYPE_PID));

Are we before or after the "create_context get new pid"? Just wondering
aloud how that's going to tie in.

> +
> +   return 0;
> +
> +err_attr_pid:
> +   sysfs_remove_file(file_priv->client_root,
> + (struct attribute *)_priv->attr.name);
> +err_attr_name:
> +   kobject_put(file_priv->client_root);
> +err_client:
> +   kfree(file_priv->client_name);
> +err_name:
> +   return ret;
> +}
> +
> +static void i915_gem_remove_client(struct drm_i915_file_private *file_priv)
> +{
> +   sysfs_remove_file(file_priv->client_root,
> + (struct attribute *)_priv->attr.pid);
> +   

[Intel-gfx] ✓ Fi.CI.BAT: success for Per-client engine stats

[Patchwork]

== Series Details ==

Series: Per-client engine stats
URL   : https://patchwork.freedesktop.org/series/38281/
State : success

== Summary ==

Series 38281v1 Per-client engine stats
https://patchwork.freedesktop.org/api/1.0/series/38281/revisions/1/mbox/

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (fi-cnl-y3) fdo#105058
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#105058 https://bugs.freedesktop.org/show_bug.cgi?id=105058
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  
time:431s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:420s
fi-blb-e6850 total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:365s
fi-bsw-n3050 total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  
time:491s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 
time:274s
fi-bxt-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:503s
fi-bxt-j4205 total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:506s
fi-byt-j1900 total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  
time:514s
fi-byt-n2820 total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  
time:463s
fi-cfl-s2total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:623s
fi-cnl-y3total:288  pass:261  dwarn:1   dfail:0   fail:0   skip:26  
time:599s
fi-elk-e7500 total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:409s
fi-gdg-551   total:288  pass:180  dwarn:0   dfail:0   fail:0   skip:108 
time:263s
fi-glk-1 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:533s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:414s
fi-ilk-650   total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  
time:402s
fi-ivb-3520m total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  
time:490s
fi-ivb-3770  total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  
time:441s
fi-kbl-7500u total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  
time:464s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:498s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:537s
fi-pnv-d510  total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  
time:496s
fi-skl-6260u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:438s
fi-skl-6600u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:517s
fi-skl-6700hqtotal:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  
time:566s
fi-skl-6700k2total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  
time:503s
fi-skl-6770hqtotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:496s
fi-skl-guc   total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:437s
fi-skl-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:427s
fi-snb-2520m total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  
time:438s
Blacklisted hosts:
fi-glk-dsi   total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  
time:490s
fi-kbl-7567u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:456s

5ad7866768dcc5d993f1bba687a80fced1070635 drm-tip: 2018y-02m-14d-15h-14m-50s UTC 
integration manifest
deb4b442c974 drm/i915: Add sysfs toggle to enable per-client engine stats
5f54047b452c drm/i915: Expose per-engine client busyness
431e3341d2bc drm/i915: Update client name on context create
eb22b6934bda drm/i915: Expose list of clients in sysfs
f4e5fd1ffe1f drm/i915: Track per-context engine busyness

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8028/issues.html
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Re: [Intel-gfx] [PATCH v2] drm: Allow determining if current task is output poll worker

[Lyude Paul]

I think your idea of having the extra kerneldoc as a seperate patch to make
this easier to backport should work fine :). Thanks for the good work!

Reviewed-by: Lyude Paul 

On Wed, 2018-02-14 at 08:41 +0100, Lukas Wunner wrote:
> Introduce a helper to determine if the current task is an output poll
> worker.
> 
> This allows us to fix a long-standing deadlock in several DRM drivers
> wherein the ->runtime_suspend callback waits for the output poll worker
> to finish and the worker in turn calls a ->detect callback which waits
> for runtime suspend to finish.  The ->detect callback is invoked from
> multiple call sites and waiting for runtime suspend to finish is the
> correct thing to do except if it's executing in the context of the
> worker.
> 
> v2: Expand kerneldoc to specifically mention deadlock between
> output poll worker and autosuspend worker as use case. (Lyude)
> 
> Cc: Dave Airlie 
> Cc: Ben Skeggs 
> Cc: Alex Deucher 
> Reviewed-by: Lyude Paul 
> Signed-off-by: Lukas Wunner 
> ---
>  drivers/gpu/drm/drm_probe_helper.c | 20 
>  include/drm/drm_crtc_helper.h  |  1 +
>  2 files changed, 21 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_probe_helper.c
> b/drivers/gpu/drm/drm_probe_helper.c
> index 6dc2dde5b672..7a6b2dc08913 100644
> --- a/drivers/gpu/drm/drm_probe_helper.c
> +++ b/drivers/gpu/drm/drm_probe_helper.c
> @@ -654,6 +654,26 @@ static void output_poll_execute(struct work_struct
> *work)
>   schedule_delayed_work(delayed_work,
> DRM_OUTPUT_POLL_PERIOD);
>  }
>  
> +/**
> + * drm_kms_helper_is_poll_worker - is %current task an output poll worker?
> + *
> + * Determine if %current task is an output poll worker.  This can be used
> + * to select distinct code paths for output polling versus other contexts.
> + *
> + * One use case is to avoid a deadlock between the output poll worker and
> + * the autosuspend worker wherein the latter waits for polling to finish
> + * upon calling drm_kms_helper_poll_disable(), while the former waits for
> + * runtime suspend to finish upon calling pm_runtime_get_sync() in a
> + * connector ->detect hook.
> + */
> +bool drm_kms_helper_is_poll_worker(void)
> +{
> + struct work_struct *work = current_work();
> +
> + return work && work->func == output_poll_execute;
> +}
> +EXPORT_SYMBOL(drm_kms_helper_is_poll_worker);
> +
>  /**
>   * drm_kms_helper_poll_disable - disable output polling
>   * @dev: drm_device
> diff --git a/include/drm/drm_crtc_helper.h b/include/drm/drm_crtc_helper.h
> index 76e237bd989b..6914633037a5 100644
> --- a/include/drm/drm_crtc_helper.h
> +++ b/include/drm/drm_crtc_helper.h
> @@ -77,5 +77,6 @@ void drm_kms_helper_hotplug_event(struct drm_device *dev);
>  
>  void drm_kms_helper_poll_disable(struct drm_device *dev);
>  void drm_kms_helper_poll_enable(struct drm_device *dev);
> +bool drm_kms_helper_is_poll_worker(void);
>  
>  #endif
-- 
Cheers,
Lyude Paul
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Re: [Intel-gfx] [RFC 1/5] drm/i915: Track per-context engine busyness

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-14 18:50:31)
> +ktime_t intel_context_engine_get_busy_time(struct i915_gem_context *ctx,
> +  struct intel_engine_cs *engine)
> +{
> +   struct intel_context *ce = >engine[engine->id];
> +   ktime_t total;
> +
> +   spin_lock_irq(>stats.lock);
> +
> +   total = ce->stats.total;
> +
> +   if (ce->stats.active)
> +   total = ktime_add(total,
> + ktime_sub(ktime_get(), ce->stats.start));
> +
> +   spin_unlock_irq(>stats.lock);

Looks like we can just use a seqlock here.
-Chris
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fixup kerneldoc for intel_uc_fw_upload() (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Fixup kerneldoc for intel_uc_fw_upload() (rev2)
URL   : https://patchwork.freedesktop.org/series/38236/
State : success

== Summary ==

Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-apl) fdo#99912
Test gem_softpin:
Subgroup noreloc-s3:
skip   -> PASS   (shard-snb) fdo#103375
Test kms_flip:
Subgroup 2x-dpms-vs-vblank-race-interruptible:
fail   -> PASS   (shard-hsw) fdo#103060
Test kms_cursor_legacy:
Subgroup 2x-long-flip-vs-cursor-legacy:
fail   -> PASS   (shard-hsw) fdo#104873
Test perf:
Subgroup buffer-fill:
fail   -> PASS   (shard-apl) fdo#103755
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-pri-indfb-multidraw:
pass   -> FAIL   (shard-snb) fdo#103167

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873
fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167

shard-apltotal:3346 pass:1739 dwarn:1   dfail:0   fail:19  skip:1586 
time:13968s
shard-hswtotal:3427 pass:1758 dwarn:1   dfail:0   fail:11  skip:1656 
time:14697s
shard-snbtotal:3427 pass:1348 dwarn:1   dfail:0   fail:11  skip:2067 
time:7607s
Blacklisted hosts:
shard-kbltotal:3427 pass:1909 dwarn:1   dfail:0   fail:21  skip:1496 
time:2s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8015/shards.html
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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: Add missing kerneldoc parameters for huc_ucode_xfer

[Patchwork]

== Series Details ==

Series: drm/i915: Add missing kerneldoc parameters for huc_ucode_xfer
URL   : https://patchwork.freedesktop.org/series/38235/
State : warning

== Summary ==

Test kms_draw_crc:
Subgroup draw-method-rgb565-mmap-gtt-xtiled:
pass   -> SKIP   (shard-snb)
Test perf:
Subgroup buffer-fill:
fail   -> PASS   (shard-apl) fdo#103755
Test gem_softpin:
Subgroup noreloc-s3:
pass   -> INCOMPLETE (shard-hsw) fdo#103540
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912
Test kms_cursor_legacy:
Subgroup 2x-long-flip-vs-cursor-legacy:
fail   -> PASS   (shard-hsw) fdo#104873
Test kms_flip:
Subgroup 2x-dpms-vs-vblank-race-interruptible:
fail   -> PASS   (shard-hsw) fdo#103060

fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060

shard-apltotal:3346 pass:1738 dwarn:1   dfail:0   fail:20  skip:1586 
time:14003s
shard-hswtotal: pass:1709 dwarn:1   dfail:0   fail:10  skip:1611 
time:13824s
shard-snbtotal:3427 pass:1347 dwarn:1   dfail:0   fail:10  skip:2069 
time:7624s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8014/shards.html
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Per-client engine stats

[Patchwork]

== Series Details ==

Series: Per-client engine stats
URL   : https://patchwork.freedesktop.org/series/38281/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
f4e5fd1ffe1f drm/i915: Track per-context engine busyness
-:65: CHECK: spinlock_t definition without comment
#65: FILE: drivers/gpu/drm/i915/i915_gem_context.h:165:
+   spinlock_t lock;

total: 0 errors, 0 warnings, 1 checks, 228 lines checked
eb22b6934bda drm/i915: Expose list of clients in sysfs
-:80: CHECK: Alignment should match open parenthesis
#80: FILE: drivers/gpu/drm/i915/i915_gem.c:5636:
+i915_gem_add_client(struct drm_i915_private *i915,
+   struct drm_i915_file_private *file_priv,

total: 0 errors, 0 warnings, 1 checks, 186 lines checked
431e3341d2bc drm/i915: Update client name on context create
-:24: CHECK: Alignment should match open parenthesis
#24: FILE: drivers/gpu/drm/i915/i915_drv.h:3428:
+i915_gem_add_client(struct drm_i915_private *i915,
+   struct drm_i915_file_private *file_priv,

total: 0 errors, 0 warnings, 1 checks, 63 lines checked
5f54047b452c drm/i915: Expose per-engine client busyness
-:22: WARNING: Possible unwrapped commit description (prefer a maximum 75 chars 
per line)
#22: 
neverball[  6011]:  rcs0:  41.01%  bcs0:   0.00%  vcs0:   0.00%  vecs0:   0.00%

-:153: ERROR: code indent should use tabs where possible
#153: FILE: drivers/gpu/drm/i915/i915_gem.c:5729:
+^I^I^I^I(struct attribute *)attr);$

-:153: CHECK: Alignment should match open parenthesis
#153: FILE: drivers/gpu/drm/i915/i915_gem.c:5729:
+   ret = sysfs_create_file(file_priv->busy_root,
+   (struct attribute *)attr);

-:168: WARNING: line over 80 characters
#168: FILE: drivers/gpu/drm/i915/i915_gem.c:5744:
+ (struct attribute 
*)_priv->attr.busy[id2]);

-:186: WARNING: line over 80 characters
#186: FILE: drivers/gpu/drm/i915/i915_gem.c:5768:
+ (struct attribute 
*)_priv->attr.busy[id]);

total: 1 errors, 3 warnings, 1 checks, 144 lines checked
deb4b442c974 drm/i915: Add sysfs toggle to enable per-client engine stats

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