Re: [Intel-gfx] [PATCH 15/36] drm/i915: Mark up Ironlake ips with rpm wakerefs

On 3/14/2018 3:07 PM, Chris Wilson wrote: Currently Ironlake operates under the assumption that rpm awake (and its error checking is disabled). As such, we have missed a few places where we access registers without taking the rpm wakeref and thus trigger warnings. intel_ips being one culprit.

Re: [Intel-gfx] [PATCH 12/36] drm/i915: Merge sbi read/write into a single accessor

On 3/14/2018 3:07 PM, Chris Wilson wrote: Since intel_sideband_read and intel_sideband_write differ by only a couple of lines (depending on whether we feed the value in or out), merge the two into a single common accessor. Signed-off-by: Chris Wilson -u32

[Intel-gfx] [PATCH xf86-video-intel 1/2] Add Coffeelake PCI IDs for H Skus

Add the Coffeelake PCI IDs based on the following kernel patches: commit ccfd13215fd25a0e8c28221f3acc0dcaec11cd15 Author: Anusha Srivatsa Date: Thu Jun 8 16:41:06 2017 -0700 drm/i915/cfl: Add Coffee Lake PCI IDs for H Sku. Signed-off-by: Liwei Song

Re: [Intel-gfx] [PATCH 5/6] drm/i915/psr: Rename intel_crtc_state has_psr to can_psr

On Wed, 2018-03-14 at 15:36 -0700, José Roberto de Souza wrote: > This value is a match of hardware and sink has PSR + if it can be > enabled by the requested state, see intel_psr_compute_config(). > > Cc: Dhinakaran Pandiyan > Cc: Rodrigo Vivi

Re: [Intel-gfx] [PATCH 6/6] drm/i915/psr: Enable aux frame sync in source

On Wed, 2018-03-14 at 15:36 -0700, José Roberto de Souza wrote: > Even with GTC not enabled lets send the aux frame sync. If this was never enabled on the source side, why do we place a requirement on the sink to support aux frame sync? > Hardware is going to send dummy values but this way we

Re: [Intel-gfx] [PATCH 3/6] drm/i915/psr: Enable Y-coordinate support in source

On Thu, 2018-03-15 at 17:28 -0700, Rodrigo Vivi wrote: > drm/i915/cnl: > > On Wed, Mar 14, 2018 at 03:36:14PM -0700, José Roberto de Souza wrote: > > We are requiring that sink requires Y-coordinate but we are not > > sending it in the main-link. > > Also add on CNL here > > > Even if

[Intel-gfx] [PATCH libdrm 2/5] intel: reorganize internal function

From: "Xiong, James" split drm_intel_gem_bo_alloc_internal, and add a function to search for a suitable buffer for given size for reuse. Signed-off-by: Xiong, James --- intel/intel_bufmgr_gem.c | 141 ---

[Intel-gfx] [PATCH libdrm 1/5] drm: add a macro DRMLISTFOREACHENTRYREVERSE

From: "Xiong, James" it goes through DRMLIST in a reverse order Signed-off-by: Xiong, James --- libdrm_lists.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/libdrm_lists.h b/libdrm_lists.h index 8926d8d..400c731 100644 ---

[Intel-gfx] [PATCH libdrm 0/5] improve reuse implementation

From: "Xiong, James" With gem_reuse enabled, when a buffer size is different than the sizes of buckets, it is aligned to the next bucket's size, which means about 25% more memory than the requested is allocated in the worst senario. For example: Orignal sizeActual

[Intel-gfx] [PATCH libdrm 4/5] intel: get a cached buffer by size for reuse

From: "Xiong, James" Previously all cached buffers in a given bucket were same sized, when reusing, the MRU buffer at the tail was poped out. With the new implementation, we go through the buffer list in a reverse order to search for a MRU buffer with a suitable size.

[Intel-gfx] [PATCH libdrm 5/5] intel: purge cached bucket when its cached buffer is evicted

From: "Xiong, James" Previously when a cached MRU buffer was found to be evicted by kernel, the bucket was emptied. The new implementation purged these buffers that were freed before the evicted one. Signed-off-by: Xiong, James ---

[Intel-gfx] [PATCH libdrm 3/5] intel: get a cached bucket by size

From: "Xiong, James" cached buckets are sorted by size in increasing order, each now contains cached buffers with different sizes. A buffer with size >= buckets[n].size and < buckets[n+1].size is put in bucket n for future reuse. Signed-off-by: Xiong, James

Re: [Intel-gfx] [PATCH 2/6] drm/i915/psr: Tie PSR2 support to Y coordinate requirement in intel_psr_init_dpcd()

On Thu, Mar 15, 2018 at 06:04:27PM -0700, Souza, Jose wrote: > On Thu, 2018-03-15 at 17:35 -0700, Rodrigo Vivi wrote: > > On Wed, Mar 14, 2018 at 03:36:13PM -0700, José Roberto de Souza > > wrote: > > > Move to only one place the sink requirements that the actual driver > > > needs to enable PSR2.

Re: [Intel-gfx] [PATCH 2/6] drm/i915/psr: Tie PSR2 support to Y coordinate requirement in intel_psr_init_dpcd()

On Thu, 2018-03-15 at 17:35 -0700, Rodrigo Vivi wrote: > On Wed, Mar 14, 2018 at 03:36:13PM -0700, José Roberto de Souza > wrote: > > Move to only one place the sink requirements that the actual driver > > needs to enable PSR2. > > > > Also intel_psr2_config_valid() is called every time the crtc

[Intel-gfx] ✓ Fi.CI.IGT: success for Guc and HuC for Cannonlake (rev2)

== Series Details == Series: Guc and HuC for Cannonlake (rev2) URL : https://patchwork.freedesktop.org/series/40064/ State : success == Summary == Known issues: Test gem_eio: Subgroup in-flight-external: pass -> INCOMPLETE (shard-apl) fdo#105341 Test

Re: [Intel-gfx] [PATCH] drm/i915: Show dmc debug registers on CFL and GLK

On Thu, Mar 15, 2018 at 03:35:02PM +0200, David Weinehall wrote: > Since Coffee Lake uses the Kaby Lake DMC it's a safe > bet that the debug registers are the same. I haven't > double-checked that the GLK DMC uses the same registers > as BXT, but it seems as good of a guess as any. It would be

Re: [Intel-gfx] [PATCH] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4

On Thu, Mar 15, 2018 at 02:08:51PM -0700, matthew.s.atw...@intel.com wrote: > From: Matt Atwood > > DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8 > bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended > receiver capabilities.

Re: [Intel-gfx] [PATCH 2/6] drm/i915/psr: Tie PSR2 support to Y coordinate requirement in intel_psr_init_dpcd()

On Wed, Mar 14, 2018 at 03:36:13PM -0700, José Roberto de Souza wrote: > Move to only one place the sink requirements that the actual driver > needs to enable PSR2. > > Also intel_psr2_config_valid() is called every time the crtc config > is computed, wasting some time every time it was checking

Re: [Intel-gfx] [PATCH 6/6] drm/i915/psr: Enable aux frame sync in source

On Wed, Mar 14, 2018 at 03:36:17PM -0700, José Roberto de Souza wrote: > Even with GTC not enabled lets send the aux frame sync. > Hardware is going to send dummy values but this way we can get rid of > this workarround in PSR exit: 'drm/i915/psr: disable aux_frame_sync > on psr2 exit'. > Also

Re: [Intel-gfx] [PATCH 1/6] drm/i915/psr: Nuke aux_frame_sync

On Wed, Mar 14, 2018 at 03:36:12PM -0700, José Roberto de Souza wrote: > PSR2 selective update requires aux frame sync(even though we don't > support it in i915) and do not makes sense active PSR2 to only do > full screen updates aka PSR1. > Having aux_frame_sync flag could cause it be set to true

Re: [Intel-gfx] [PATCH 3/6] drm/i915/psr: Enable Y-coordinate support in source

drm/i915/cnl: On Wed, Mar 14, 2018 at 03:36:14PM -0700, José Roberto de Souza wrote: > We are requiring that sink requires Y-coordinate but we are not > sending it in the main-link. Also add on CNL here > Even if hardware tracking isn't good enough it will not cause > any more issues

Re: [Intel-gfx] [PATCH 0/3] PSR lag fixes

On Wed, Mar 14, 2018 at 04:35:55PM -0700, Pandiyan, Dhinakaran wrote: > > > > On Wed, 2018-03-14 at 23:09 +0100, Hans de Goede wrote: > > Hi, > > > > On 14-03-18 21:49, Pandiyan, Dhinakaran wrote: > > > > > > On Wed, 2018-02-14 at 09:25 +0100, Hans de Goede wrote: > > >> Hi, > > >> > > >> On

Re: [Intel-gfx] [PATCH] drm/i915: Don't initialize plane_to_crtc_mapping[] on SKL+

On Mon, 2018-03-05 at 19:41 +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > We don't use the enum i9xx_plane_id namespace on SKL+ anymore, so > do not initialize the related plane_to_crtc_mapping[] table either. > > Actually the only remaining user of

[Intel-gfx] [PULL] drm-intel-fixes

Hi Dave, Sorry for the last minute and for sending 2 pull requests in a short time, but we just got a pull request from GVT. It passes our CI-fast-feedback and the full run is still running. Please if we still have time please consider pulling it, otherwise this will be part of next regular

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/6] Revert "drm: Use a flexible array member for blob property data" (rev4)

== Series Details == Series: series starting with [1/6] Revert "drm: Use a flexible array member for blob property data" (rev4) URL : https://patchwork.freedesktop.org/series/38886/ State : failure == Summary == Possible new issues: Test kms_cursor_crc: Subgroup

Re: [Intel-gfx] [PATCH] sna/uxa: Fix colormap handling at screen depth 30.

Oops, didn't reply yet, sorry! On Thu, Mar 15, 2018 at 5:14 PM, Chris Wilson wrote: > Quoting Ville Syrjälä (2018-03-15 16:02:42) >> On Thu, Mar 15, 2018 at 03:28:18PM +, Chris Wilson wrote: >> > Quoting Ville Syrjälä (2018-03-01 11:12:53) >> > > On Thu, Mar 01,

Re: [Intel-gfx] [PULL] more gvt-fixes for 4.16

On Thu, Mar 15, 2018 at 06:00:23PM +0800, Zhenyu Wang wrote: > > Hi, > > Here's more gvt-fixes for final 4.16. Sorry it's a little late, > as Zhi had two days off this week and more regression tests > have been done for this. pulled to drm-intel-fixes and leaving CI run on it right now... I

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Use correct reST syntax for WOPCM and GuC kernel-doc diagrams (rev3)

== Series Details == Series: drm/i915: Use correct reST syntax for WOPCM and GuC kernel-doc diagrams (rev3) URL : https://patchwork.freedesktop.org/series/39979/ State : success == Summary == Known issues: Test kms_cursor_crc: Subgroup cursor-256x256-suspend:

[Intel-gfx] ✓ Fi.CI.BAT: success for Guc and HuC for Cannonlake (rev2)

== Series Details == Series: Guc and HuC for Cannonlake (rev2) URL : https://patchwork.freedesktop.org/series/40064/ State : success == Summary == Series 40064v2 Guc and HuC for Cannonlake https://patchwork.freedesktop.org/api/1.0/series/40064/revisions/2/mbox/ Known issues: Test

[Intel-gfx] [PATCH] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4

From: Matt Atwood DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8 bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended receiver capabilities. For panels that use this new feature wait interval would be increased by 512 ms, when

[Intel-gfx] [PATCH 1/2] linux-firmware/guc/cnl: Load GuC on Cannonlake

GuC is now available for Cannonlake. Load GuC v11.102 on Cannonlake. Cc: Tomi Sarvela Cc: Jani Saarinen Cc: Rodrigo vivi Signed-off-by: Anusha Srivatsa ---

[Intel-gfx] [PATCH 2/2] linux-firmware/huc/cnl: Load HuC on Cannonlake

Huc is available now for cannonlake. Load v9.01.2678 on Cannonlake Cc: Tomi Sarvela Cc: Jani Saarinen Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_huc_fw.c

[Intel-gfx] [PATCH 0/2] Guc and HuC for Cannonlake

Adding the Pull request: The following changes since commit 4c0bf113a55975d702673e57c5542f150807ad66: linux-firmware: intel: Update Kabylake audio firmware (2018-03-14 16:23:08 +0530) are available in the git repository at: ssh://git.freedesktop.org/git/drm/drm-firmware master for you to

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Fix build break on config without DEBUG_FS

== Series Details == Series: drm/i915/guc: Fix build break on config without DEBUG_FS URL : https://patchwork.freedesktop.org/series/40041/ State : success == Summary == Known issues: Test gem_eio: Subgroup in-flight-external: incomplete -> PASS (shard-apl)

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] Revert "drm: Use a flexible array member for blob property data" (rev4)

== Series Details == Series: series starting with [1/6] Revert "drm: Use a flexible array member for blob property data" (rev4) URL : https://patchwork.freedesktop.org/series/38886/ State : success == Summary == Series 38886v4 series starting with [1/6] Revert "drm: Use a flexible array

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Trace GEM steps between submit and wedging (rev3)

== Series Details == Series: series starting with [1/2] drm/i915: Trace GEM steps between submit and wedging (rev3) URL : https://patchwork.freedesktop.org/series/40029/ State : success == Summary == Known issues: Test gem_eio: Subgroup in-flight-contexts:

Re: [Intel-gfx] [PATCH 2/3] drm: Make sure at least one plane supports the fb format

On Thu, Mar 15, 2018 at 08:03:44PM +0200, Ville Syrjälä wrote: > On Thu, Mar 15, 2018 at 07:48:02PM +0200, Ville Syrjälä wrote: > > On Thu, Mar 15, 2018 at 10:42:17AM -0700, Eric Anholt wrote: > > > Ville Syrjala writes: > > > > > > > From: Ville Syrjälä

Re: [Intel-gfx] [maintainer-tools PATCH] doc: how to become a drm-intel committer

On Thu, Mar 15, 2018 at 4:32 PM, Jani Nikula wrote: > On Thu, 15 Mar 2018, Daniel Vetter wrote: >> On Wed, Mar 14, 2018 at 05:11:02PM +0200, Jani Nikula wrote: >>> Until now, the drm-intel commit access have been handed out ad hoc, >>> without

Re: [Intel-gfx] [PATCH] drm/i915: Remove hole and padding from intel_shared_dpll

On Thu, Mar 15, 2018 at 11:07:04AM -0700, Lucas De Marchi wrote: > On Thu, Mar 15, 2018 at 11:54:19AM +0200, Ville Syrjälä wrote: > > > We can even (or alternatively) make dpll_info part of intel_shared_dpll. > > > > You mean something like? > > > > struct intel_shared_dpll { > > ... > > -

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/6] Revert "drm: Use a flexible array member for blob property data" (rev4)

== Series Details == Series: series starting with [1/6] Revert "drm: Use a flexible array member for blob property data" (rev4) URL : https://patchwork.freedesktop.org/series/38886/ State : failure == Summary == Series 38886v4 series starting with [1/6] Revert "drm: Use a flexible array

Re: [Intel-gfx] [PATCH] drm/i915: Remove hole and padding from intel_shared_dpll

On Thu, Mar 15, 2018 at 11:54:19AM +0200, Ville Syrjälä wrote: > > We can even (or alternatively) make dpll_info part of intel_shared_dpll. > > You mean something like? > > struct intel_shared_dpll { > ... > - id; > - name; > - flags; > + const struct dpll_info *info; >

Re: [Intel-gfx] [PATCH 2/3] drm: Make sure at least one plane supports the fb format

On Thu, Mar 15, 2018 at 07:48:02PM +0200, Ville Syrjälä wrote: > On Thu, Mar 15, 2018 at 10:42:17AM -0700, Eric Anholt wrote: > > Ville Syrjala writes: > > > > > From: Ville Syrjälä > > > > > > To make life easier for drivers, let's

Re: [Intel-gfx] [PATCH] drm/i915: Remove hole and padding from intel_shared_dpll

On Thu, Mar 15, 2018 at 08:16:32AM -0300, Jani Nikula wrote: > On Wed, 14 Mar 2018, Lucas De Marchi wrote: > > Reorder fields so we save 8 bytes per instance: this removes a 4-bytes > > hole after enum intel_dpll_id and a 4-bytes padding. > > Does GCC have anything like

Re: [Intel-gfx] [PATCH 2/3] drm: Make sure at least one plane supports the fb format

On Thu, Mar 15, 2018 at 10:42:17AM -0700, Eric Anholt wrote: > Ville Syrjala writes: > > > From: Ville Syrjälä > > > > To make life easier for drivers, let's have the core check that the > > requested pixel format is supported by at

Re: [Intel-gfx] [PATCH igt 6/8] lib/igt_pm: turn absence of autosuspend_delay_ms from fail to skip

On Thu, Mar 15, 2018 at 03:45:42PM +0100, Ulrich Hecht wrote: > Fixes false negatives on everything that doesn't happen to be at a > specific hard-coded sysfs path... > > Signed-off-by: Ulrich Hecht > --- > lib/igt_pm.c | 2 +- > 1 file changed, 1 insertion(+), 1

Re: [Intel-gfx] [PATCH 2/3] drm: Make sure at least one plane supports the fb format

Ville Syrjala writes: > From: Ville Syrjälä > > To make life easier for drivers, let's have the core check that the > requested pixel format is supported by at least one plane when creating > a new framebuffer. > > This eases the

Re: [Intel-gfx] [PATCH igt 5/8] tests/kms_plane_lowres: skip i915-specific tests on other platforms

On Thu, Mar 15, 2018 at 03:45:41PM +0100, Ulrich Hecht wrote: > Add is_i915_device() requirement to tests using Intel-specific APIs. > > Signed-off-by: Ulrich Hecht > --- > tests/kms_plane_lowres.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git

Re: [Intel-gfx] [PATCH igt 3/8] lib/igt_gt: has_gpu_reset(): fix failed assertion on non-i915 platforms

On Thu, Mar 15, 2018 at 03:45:39PM +0100, Ulrich Hecht wrote: > Checks if we have an i915 device before using intel_get_drm_devid(). > > Signed-off-by: Ulrich Hecht > --- > lib/igt_gt.c | 19 +++ > 1 file changed, 11 insertions(+), 8 deletions(-)

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Use correct reST syntax for WOPCM and GuC kernel-doc diagrams (rev3)

== Series Details == Series: drm/i915: Use correct reST syntax for WOPCM and GuC kernel-doc diagrams (rev3) URL : https://patchwork.freedesktop.org/series/39979/ State : success == Summary == Series 39979v3 drm/i915: Use correct reST syntax for WOPCM and GuC kernel-doc diagrams

[Intel-gfx] [PATCH v2 5/6] drm/i915: Remove the blob->data casts

From: Ville Syrjälä Now that blob->data is void* again we don't need to cast it. v2: Rebase Signed-off-by: Ville Syrjälä Reviewed-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_color.c | 18

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Show dmc debug registers on CFL and GLK (rev2)

== Series Details == Series: drm/i915: Show dmc debug registers on CFL and GLK (rev2) URL : https://patchwork.freedesktop.org/series/40031/ State : failure == Summary == Possible new issues: Test kms_frontbuffer_tracking: Subgroup fbc-modesetfrombusy: pass

[Intel-gfx] [PATCH v3] drm/i915: Use correct reST syntax for WOPCM and GuC kernel-doc diagrams

GuC Address Space and WOPCM Layout diagrams won't be generated correctly by sphinx build if not using proper reST syntax. This patch uses reST literal blocks to make sure GuC Address Space and WOPCM Layout diagrams to be generated correctly, and it also corrects some errors in the diagram

Re: [Intel-gfx] [PATCH] drm/i915/guc: Unify naming of private GuC action functions

On Thu, Mar 15, 2018 at 05:19:27PM +0100, Michal Wajdeczko wrote: > On Thu, 15 Mar 2018 16:57:26 +0100, Michał Winiarski > wrote: > > > On Wed, Mar 14, 2018 at 06:37:15PM +, Michal Wajdeczko wrote: > > > We should avoid using guc_log prefix for functions that

Re: [Intel-gfx] [PATCH v2] drm/i915: Use correct reST syntax for WOPCM and GuC kernel-doc diagrams

On 03/14/2018 11:54 PM, Sagar Arun Kamble wrote: Are we required to add reference to intel_guc.c and intel_wopcm.c in Documentation/gpu/i915.rst? hmm, I have the same question too:-). Can I modify the i915.rst to include kernel-doc from WOPCM and GuC WOPCM related changes? or someone would

Re: [Intel-gfx] [PATCH] drm: Reduce object size of DRM_ERROR and DRM_DEBUG uses

On Thu, 2018-03-15 at 18:14 +0200, Ville Syrjälä wrote: > > There's no trade-off in this patch for faster/larger. > > This patch is simply smaller. Smaller is better. > > This feels a bit like saying pink is better than red because it's > more pink. Silly. If you can't say smaller total object

Re: [Intel-gfx] [PATCH 1/1] intel: align reuse buffer's size on page size instead

Thanks for the review, Chris. Sorry for the late response. >-Original Message- >From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of >Chris Wilson >Sent: Saturday, March 3, 2018 1:46 AM >To: Xiong, James ; dri-de...@lists.freedesktop.org;

Re: [Intel-gfx] [PATCH] drm/i915/guc: Unify naming of private GuC action functions

On Thu, 15 Mar 2018 16:57:26 +0100, Michał Winiarski wrote: On Wed, Mar 14, 2018 at 06:37:15PM +, Michal Wajdeczko wrote: We should avoid using guc_log prefix for functions that don't operate on GuC log, but rather request action from the GuC. Better to use

Re: [Intel-gfx] [PATCH] drm: Reduce object size of DRM_ERROR and DRM_DEBUG uses

On Thu, Mar 15, 2018 at 08:44:05AM -0700, Joe Perches wrote: > On Thu, 2018-03-15 at 17:37 +0200, Ville Syrjälä wrote: > > On Thu, Mar 15, 2018 at 08:17:53AM -0700, Joe Perches wrote: > > > On Thu, 2018-03-15 at 17:05 +0200, Ville Syrjälä wrote: > > > > On Thu, Mar 15, 2018 at 03:04:52PM +0100,

Re: [Intel-gfx] [PATCH] sna/uxa: Fix colormap handling at screen depth 30.

Quoting Ville Syrjälä (2018-03-15 16:02:42) > On Thu, Mar 15, 2018 at 03:28:18PM +, Chris Wilson wrote: > > Quoting Ville Syrjälä (2018-03-01 11:12:53) > > > On Thu, Mar 01, 2018 at 02:20:48AM +0100, Mario Kleiner wrote: > > > > The various clut handling functions like a setup > > > >

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Fix build break on config without DEBUG_FS

== Series Details == Series: drm/i915/guc: Fix build break on config without DEBUG_FS URL : https://patchwork.freedesktop.org/series/40041/ State : success == Summary == Series 40041v1 drm/i915/guc: Fix build break on config without DEBUG_FS

Re: [Intel-gfx] [PATCH] sna/uxa: Fix colormap handling at screen depth 30.

On Thu, Mar 15, 2018 at 03:28:18PM +, Chris Wilson wrote: > Quoting Ville Syrjälä (2018-03-01 11:12:53) > > On Thu, Mar 01, 2018 at 02:20:48AM +0100, Mario Kleiner wrote: > > > The various clut handling functions like a setup > > > consistent with the x-screen color depth. Otherwise > > > we

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t v2] tests/perf_pmu: Improve accuracy by waiting on spinner to start

Quoting Tvrtko Ursulin (2018-03-15 15:46:00) > static void > -__submit_spin_batch(int gem_fd, > - struct drm_i915_gem_exec_object2 *obj, > +__submit_spin_batch(int gem_fd, igt_spin_t *spin, > const struct intel_execution_engine2 *e) > { > - struct

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Trace GEM steps between submit and wedging (rev2)

== Series Details == Series: series starting with [1/2] drm/i915: Trace GEM steps between submit and wedging (rev2) URL : https://patchwork.freedesktop.org/series/40029/ State : success == Summary == Known issues: Test gem_eio: Subgroup in-flight-external:

Re: [Intel-gfx] [PATCH] drm/i915/guc: Unify naming of private GuC action functions

On Wed, Mar 14, 2018 at 06:37:15PM +, Michal Wajdeczko wrote: > We should avoid using guc_log prefix for functions that don't > operate on GuC log, but rather request action from the GuC. > Better to use guc_action prefix. > > Signed-off-by: Michal Wajdeczko > Cc:

Re: [Intel-gfx] [PATCH] drm/i915: Stop engines when declaring the machine wedged

Chris Wilson writes: > If we fail to reset the GPU, we declare the machine wedged. However, the > GPU may well still be running in the background with an in-flight > request. So despite our efforts in cleaning up the request queue and > faking the breadcrumb in the

Re: [Intel-gfx] [PATCH] drm/i915/guc: Fix build break on config without DEBUG_FS

On Thu, Mar 15, 2018 at 03:28:47PM +, Michal Wajdeczko wrote: > In commit 56b9a8b08387 ("drm/i915/guc: Update syntax of GuC > log functions") we accidentally removed debugfs.h header > where needed stub functions were defined. > > Reported-by: Mike Lothian >

[Intel-gfx] [PATCH i-g-t v2] tests/perf_pmu: Improve accuracy by waiting on spinner to start

From: Tvrtko Ursulin More than one test assumes that the spinner is running pretty much immediately after we have create or submitted it. In actuality there is a variable delay, especially on execlists platforms, between submission and spin batch starting to run on the

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/6] Revert "drm: Use a flexible array member for blob property data" (rev3)

== Series Details == Series: series starting with [1/6] Revert "drm: Use a flexible array member for blob property data" (rev3) URL : https://patchwork.freedesktop.org/series/38886/ State : failure == Summary == Applying: Revert "drm: Use a flexible array member for blob property data"

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Trace GEM steps between submit and wedging (rev3)

== Series Details == Series: series starting with [1/2] drm/i915: Trace GEM steps between submit and wedging (rev3) URL : https://patchwork.freedesktop.org/series/40029/ State : success == Summary == Series 40029v3 series starting with [1/2] drm/i915: Trace GEM steps between submit and

Re: [Intel-gfx] [PATCH] drm: Reduce object size of DRM_ERROR and DRM_DEBUG uses

On Thu, 2018-03-15 at 17:37 +0200, Ville Syrjälä wrote: > On Thu, Mar 15, 2018 at 08:17:53AM -0700, Joe Perches wrote: > > On Thu, 2018-03-15 at 17:05 +0200, Ville Syrjälä wrote: > > > On Thu, Mar 15, 2018 at 03:04:52PM +0100, Maarten Lankhorst wrote: > > > > Op 15-03-18 om 14:30 schreef Ville

Re: [Intel-gfx] [PATCH] drm: Reduce object size of DRM_ERROR and DRM_DEBUG uses

On Thu, Mar 15, 2018 at 08:17:53AM -0700, Joe Perches wrote: > On Thu, 2018-03-15 at 17:05 +0200, Ville Syrjälä wrote: > > On Thu, Mar 15, 2018 at 03:04:52PM +0100, Maarten Lankhorst wrote: > > > Op 15-03-18 om 14:30 schreef Ville Syrjälä: > > > > On Tue, Mar 13, 2018 at 03:02:15PM -0700, Joe

Re: [Intel-gfx] [maintainer-tools PATCH] doc: how to become a drm-intel committer

On Thu, 15 Mar 2018, Daniel Vetter wrote: > On Wed, Mar 14, 2018 at 05:11:02PM +0200, Jani Nikula wrote: >> Until now, the drm-intel commit access have been handed out ad hoc, >> without transparency, consistency, or fairness. With pressure to add >> more committers, this is no

[Intel-gfx] [PATCH] drm/i915/guc: Fix build break on config without DEBUG_FS

In commit 56b9a8b08387 ("drm/i915/guc: Update syntax of GuC log functions") we accidentally removed debugfs.h header where needed stub functions were defined. Reported-by: Mike Lothian Signed-off-by: Michal Wajdeczko Cc: Mike Lothian

Re: [Intel-gfx] [PATCH] sna/uxa: Fix colormap handling at screen depth 30.

Quoting Ville Syrjälä (2018-03-01 11:12:53) > On Thu, Mar 01, 2018 at 02:20:48AM +0100, Mario Kleiner wrote: > > The various clut handling functions like a setup > > consistent with the x-screen color depth. Otherwise > > we observe improper sampling in the gamma tables > > at depth 30. > > > >

[Intel-gfx] [PATCH v2 4/6] drm: Introduce drm_color_lut_size()

From: Ville Syrjälä Provide a small helper to convert the blob length in bytes to the number of LUT entries. v2: Add kerneldoc (Daniel) Cc: Daniel Vetter Signed-off-by: Ville Syrjälä Reviewed-by: Daniel

[Intel-gfx] [PATCH v2 3/6] drm: Verify gamma/degamma LUT size

From: Ville Syrjälä While we want to potentially support multiple different gamma/degamma LUT sizes we can (and should) at least check that the blob length is a multiple of the LUT entry size. v2: s/expected_size_mod/expected_elem_size/ (Daniel) Add kernel doc

Re: [Intel-gfx] [PATCH] drm: Reduce object size of DRM_ERROR and DRM_DEBUG uses

On Thu, 2018-03-15 at 17:05 +0200, Ville Syrjälä wrote: > On Thu, Mar 15, 2018 at 03:04:52PM +0100, Maarten Lankhorst wrote: > > Op 15-03-18 om 14:30 schreef Ville Syrjälä: > > > On Tue, Mar 13, 2018 at 03:02:15PM -0700, Joe Perches wrote: > > > > drm_printk is used for both DRM_ERROR and

[Intel-gfx] [PATCH v2] drm/i915: Stop engines when declaring the machine wedged

If we fail to reset the GPU, we declare the machine wedged. However, the GPU may well still be running in the background with an in-flight request. So despite our efforts in cleaning up the request queue and faking the breadcrumb in the HWSP, the GPU may eventually write the in-flght seqno there

Re: [Intel-gfx] [PATCH] drm: Reduce object size of DRM_ERROR and DRM_DEBUG uses

On Thu, Mar 15, 2018 at 03:04:52PM +0100, Maarten Lankhorst wrote: > Op 15-03-18 om 14:30 schreef Ville Syrjälä: > > On Tue, Mar 13, 2018 at 03:02:15PM -0700, Joe Perches wrote: > >> drm_printk is used for both DRM_ERROR and DRM_DEBUG with unnecessary > >> arguments that can be removed by creating

[Intel-gfx] ✗ Fi.CI.BAT: failure for Non-Intel test suite fixes

== Series Details == Series: Non-Intel test suite fixes URL : https://patchwork.freedesktop.org/series/40038/ State : failure == Summary == Applying: tests/kms_addfb_basic: skip i915-specific tests on other platforms Applying: tests/kms_panel_fitting: check for i915 before checking version

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] tests/perf_pmu: Improve accuracy by waiting on spinner to start

Quoting Tvrtko Ursulin (2018-03-15 14:53:08) > > On 15/03/2018 14:46, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2018-03-15 14:37:59) > >> > >> On 15/03/2018 13:45, Chris Wilson wrote: > >>> As we are making changes to igt_spin_t, one of the ideas was that we put > >>> the obj[] array there

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] tests/perf_pmu: Improve accuracy by waiting on spinner to start

On 15/03/2018 14:46, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-03-15 14:37:59) On 15/03/2018 13:45, Chris Wilson wrote: As we are making changes to igt_spin_t, one of the ideas was that we put the obj[] array there (with the offsets and flags setup correctly) so that we could just

Re: [Intel-gfx] [PATCH] drm: Reduce object size of DRM_ERROR and DRM_DEBUG uses

On Thu, 2018-03-15 at 14:22 +0100, Maarten Lankhorst wrote: > Op 13-03-18 om 23:02 schreef Joe Perches: > > drm_printk is used for both DRM_ERROR and DRM_DEBUG with unnecessary > > arguments that can be removed by creating separate functins. > > > > Create specific functions for these calls to

[Intel-gfx] [PATCH igt 8/8] test/kms_addfb_basic: tolerate absence of 8-bit format

Ignores failure to add DRM_FORMAT_C8 frame buffer; some devices do not support any 8-bit format. Signed-off-by: Ulrich Hecht --- tests/kms_addfb_basic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/kms_addfb_basic.c

[Intel-gfx] [PATCH igt 1/8] tests/kms_addfb_basic: skip i915-specific tests on other platforms

Add is_i915_device() requirement to tests using Intel-specific APIs. Signed-off-by: Ulrich Hecht --- tests/kms_addfb_basic.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/kms_addfb_basic.c b/tests/kms_addfb_basic.c index 7d8852f..cf9ba37 100644 ---

[Intel-gfx] [PATCH igt 3/8] lib/igt_gt: has_gpu_reset(): fix failed assertion on non-i915 platforms

Checks if we have an i915 device before using intel_get_drm_devid(). Signed-off-by: Ulrich Hecht --- lib/igt_gt.c | 19 +++ 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/lib/igt_gt.c b/lib/igt_gt.c index e630550..9cb07c2 100644

[Intel-gfx] [PATCH igt 0/8] Non-Intel test suite fixes

Hi! I have run the tests on a Renesas R-Car M3-W's DU device, and have found a number of false negatives that mostly stem from use of Intel-specifics without checking if that makes sense first. So here's a bunch of fixes for those, hope they are generic enough for upstreaming. CU Uli Ulrich

[Intel-gfx] [PATCH igt 7/8] tests/kms_addfb_basic: size_tests(): reduce test buffer size

Fixes fails on low-memory devices. Signed-off-by: Ulrich Hecht --- tests/kms_addfb_basic.c | 26 +- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/tests/kms_addfb_basic.c b/tests/kms_addfb_basic.c index cf9ba37..d1da718

[Intel-gfx] [PATCH igt 5/8] tests/kms_plane_lowres: skip i915-specific tests on other platforms

Add is_i915_device() requirement to tests using Intel-specific APIs. Signed-off-by: Ulrich Hecht --- tests/kms_plane_lowres.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/kms_plane_lowres.c b/tests/kms_plane_lowres.c index d1e4b3c..8fc7654 100644 ---

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] tests/perf_pmu: Improve accuracy by waiting on spinner to start

Quoting Tvrtko Ursulin (2018-03-15 14:37:59) > > On 15/03/2018 13:45, Chris Wilson wrote: > > As we are making changes to igt_spin_t, one of the ideas was that we put > > the obj[] array there (with the offsets and flags setup correctly) so > > that we could just feed that in again later without

[Intel-gfx] [PATCH igt 2/8] tests/kms_panel_fitting: check for i915 before checking version

Fixes false negatives on non-i915 platforms. Signed-off-by: Ulrich Hecht --- tests/kms_panel_fitting.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/kms_panel_fitting.c b/tests/kms_panel_fitting.c index b3cee22..6d0be50 100644 ---

[Intel-gfx] [PATCH igt 4/8] lib/igt_gt: check for presence of GPU reset before using it

Fixes failed assertion on non-i915 devices. Signed-off-by: Ulrich Hecht --- lib/igt_gt.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/lib/igt_gt.c b/lib/igt_gt.c index 9cb07c2..825ea52 100644 --- a/lib/igt_gt.c +++ b/lib/igt_gt.c @@

[Intel-gfx] [PATCH igt 6/8] lib/igt_pm: turn absence of autosuspend_delay_ms from fail to skip

Fixes false negatives on everything that doesn't happen to be at a specific hard-coded sysfs path... Signed-off-by: Ulrich Hecht --- lib/igt_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/igt_pm.c b/lib/igt_pm.c index

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] tests/perf_pmu: Improve accuracy by waiting on spinner to start

On 15/03/2018 13:45, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-03-15 13:36:26) On 15/03/2018 13:14, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-03-15 12:56:17) From: Tvrtko Ursulin More than one test assumes that the spinner is running pretty much

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Show dmc debug registers on CFL and GLK (rev2)

== Series Details == Series: drm/i915: Show dmc debug registers on CFL and GLK (rev2) URL : https://patchwork.freedesktop.org/series/40031/ State : success == Summary == Series 40031v2 drm/i915: Show dmc debug registers on CFL and GLK

[Intel-gfx] ✗ Fi.CI.IGT: failure for Add NV12 support (rev2)

== Series Details == Series: Add NV12 support (rev2) URL : https://patchwork.freedesktop.org/series/39670/ State : failure == Summary == Possible new issues: Test gem_exec_capture: Subgroup capture-vebox: pass -> FAIL (shard-apl) Test

Re: [Intel-gfx] [PATCH] drm: Reduce object size of DRM_ERROR and DRM_DEBUG uses

Op 15-03-18 om 14:30 schreef Ville Syrjälä: > On Tue, Mar 13, 2018 at 03:02:15PM -0700, Joe Perches wrote: >> drm_printk is used for both DRM_ERROR and DRM_DEBUG with unnecessary >> arguments that can be removed by creating separate functins. >> >> Create specific functions for these calls to

Re: [Intel-gfx] [maintainer-tools PATCH] doc: how to become a drm-intel committer

On Wed, Mar 14, 2018 at 05:11:02PM +0200, Jani Nikula wrote: > Until now, the drm-intel commit access have been handed out ad hoc, > without transparency, consistency, or fairness. With pressure to add > more committers, this is no longer tenable, if it ever was. Document the > requirements and

[Intel-gfx] [PATCH] drm/i915: Show dmc debug registers on CFL and GLK

Since Coffee Lake uses the Kaby Lake DMC it's a safe bet that the debug registers are the same. I haven't double-checked that the GLK DMC uses the same registers as BXT, but it seems as good of a guess as any. v2: Add parentheses to silence warning Signed-off-by: David Weinehall

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] tests/perf_pmu: Improve accuracy by waiting on spinner to start

Quoting Tvrtko Ursulin (2018-03-15 13:36:26) > > On 15/03/2018 13:14, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2018-03-15 12:56:17) > >> From: Tvrtko Ursulin > >> > >> More than one test assumes that the spinner is running pretty much > >> immediately after we

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