[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: Send DPCD ON for MST before phy_up (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Send DPCD ON for MST before phy_up (rev2)
URL   : https://patchwork.freedesktop.org/series/41297/
State : success

== Summary ==

 Possible new issues:

Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
fail   -> PASS   (shard-snb)
Test kms_cursor_crc:
Subgroup cursor-256x256-dpms:
fail   -> PASS   (shard-snb)
Subgroup cursor-256x256-offscreen:
fail   -> PASS   (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-pwrite:
fail   -> PASS   (shard-snb)
Subgroup fbc-1p-primscrn-shrfb-pgflip-blt:
fail   -> PASS   (shard-snb)
Subgroup fbc-modesetfrombusy:
fail   -> PASS   (shard-snb)
Subgroup fbcpsr-1p-offscren-pri-indfb-draw-blt:
fail   -> SKIP   (shard-snb)
Subgroup fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt:
fail   -> SKIP   (shard-snb)
Subgroup fbcpsr-1p-primscrn-pri-shrfb-draw-render:
fail   -> SKIP   (shard-snb)
Subgroup fbcpsr-2p-scndscrn-spr-indfb-fullscreen:
fail   -> SKIP   (shard-snb)
Subgroup psr-1p-primscrn-spr-indfb-onoff:
fail   -> SKIP   (shard-snb)
Subgroup psr-2p-scndscrn-cur-indfb-draw-mmap-wc:
fail   -> SKIP   (shard-snb)
Test kms_mmap_write_crc:
fail   -> PASS   (shard-snb)
Test kms_vblank:
Subgroup pipe-b-query-forked-busy-hang:
fail   -> PASS   (shard-snb)

 Known issues:

Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
pass   -> FAIL   (shard-hsw) fdo#102887
Subgroup plain-flip-fb-recreate:
fail   -> PASS   (shard-hsw) fdo#100368 +3
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-pri-shrfb-draw-render:
pass   -> FAIL   (shard-snb) fdo#105798
Subgroup fbc-2p-primscrn-shrfb-pgflip-blt:
fail   -> SKIP   (shard-snb) fdo#103167
Test perf:
Subgroup blocking:
pass   -> FAIL   (shard-hsw) fdo#102252 +1

fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#105798 https://bugs.freedesktop.org/show_bug.cgi?id=105798
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apltotal:2680 pass:1835 dwarn:1   dfail:0   fail:7   skip:836 
time:12676s
shard-hswtotal:2680 pass:1782 dwarn:1   dfail:0   fail:5   skip:891 
time:11388s
shard-snbtotal:2680 pass:1376 dwarn:1   dfail:0   fail:4   skip:1299 
time:6935s
Blacklisted hosts:
shard-kbltotal:2680 pass:1962 dwarn:1   dfail:0   fail:8   skip:709 
time:9262s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8633/shards.html
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds

[Patchwork]

== Series Details ==

Series: series starting with [01/22] drm/i915/icl: Introduce initial Icelake 
Workarounds
URL   : https://patchwork.freedesktop.org/series/41311/
State : failure

== Summary ==

 Possible new issues:

Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
fail   -> PASS   (shard-snb)
Test kms_chv_cursor_fail:
Subgroup pipe-c-256x256-top-edge:
pass   -> FAIL   (shard-apl)
Test kms_cursor_crc:
Subgroup cursor-256x256-dpms:
fail   -> PASS   (shard-snb)
Subgroup cursor-256x256-offscreen:
fail   -> PASS   (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-pwrite:
fail   -> PASS   (shard-snb)
Subgroup fbc-1p-primscrn-shrfb-pgflip-blt:
fail   -> PASS   (shard-snb)
Subgroup fbc-modesetfrombusy:
fail   -> PASS   (shard-snb)
Subgroup fbcpsr-1p-offscren-pri-indfb-draw-blt:
fail   -> SKIP   (shard-snb)
Subgroup fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt:
fail   -> SKIP   (shard-snb)
Subgroup fbcpsr-1p-primscrn-pri-shrfb-draw-render:
fail   -> SKIP   (shard-snb)
Subgroup fbcpsr-2p-scndscrn-spr-indfb-fullscreen:
fail   -> SKIP   (shard-snb)
Subgroup psr-1p-primscrn-spr-indfb-onoff:
fail   -> SKIP   (shard-snb)
Subgroup psr-2p-scndscrn-cur-indfb-draw-mmap-wc:
fail   -> SKIP   (shard-snb)
Test kms_mmap_write_crc:
fail   -> PASS   (shard-snb)
Test kms_vblank:
Subgroup pipe-b-query-forked-busy-hang:
fail   -> PASS   (shard-snb)

 Known issues:

Test kms_flip:
Subgroup plain-flip-fb-recreate:
fail   -> PASS   (shard-hsw) fdo#100368 +1
Test kms_frontbuffer_tracking:
Subgroup fbc-2p-primscrn-shrfb-pgflip-blt:
fail   -> SKIP   (shard-snb) fdo#103167
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912
Test kms_sysfs_edid_timing:
warn   -> PASS   (shard-apl) fdo#100047
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apltotal:2680 pass:1835 dwarn:1   dfail:0   fail:8   skip:836 
time:12719s
shard-hswtotal:2680 pass:1787 dwarn:1   dfail:0   fail:0   skip:891 
time:11531s
shard-snbtotal:2680 pass:1377 dwarn:1   dfail:0   fail:3   skip:1299 
time:6900s
Blacklisted hosts:
shard-kbltotal:2680 pass:1954 dwarn:10  dfail:0   fail:6   skip:710 
time:9048s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8632/shards.html
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: Treat i915_reset_engine() as guilty until proven innocent

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Treat i915_reset_engine() as 
guilty until proven innocent
URL   : https://patchwork.freedesktop.org/series/41308/
State : failure

== Summary ==

 Possible new issues:

Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
fail   -> PASS   (shard-snb)
Test kms_cursor_crc:
Subgroup cursor-256x256-dpms:
fail   -> PASS   (shard-snb)
Subgroup cursor-256x256-offscreen:
fail   -> PASS   (shard-snb)
Test kms_cursor_legacy:
Subgroup long-nonblocking-modeset-vs-cursor-atomic:
pass   -> FAIL   (shard-snb)
Test kms_draw_crc:
Subgroup draw-method-xrgb2101010-mmap-wc-untiled:
pass   -> SKIP   (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-pwrite:
fail   -> PASS   (shard-snb)
Subgroup fbc-1p-primscrn-shrfb-pgflip-blt:
fail   -> PASS   (shard-snb)
Subgroup fbc-2p-scndscrn-spr-indfb-onoff:
skip   -> FAIL   (shard-snb)
Subgroup fbc-modesetfrombusy:
fail   -> PASS   (shard-snb)
Subgroup fbcpsr-1p-offscren-pri-indfb-draw-blt:
fail   -> SKIP   (shard-snb)
Subgroup fbcpsr-1p-primscrn-indfb-pgflip-blt:
skip   -> FAIL   (shard-snb)
Subgroup fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt:
fail   -> SKIP   (shard-snb)
Subgroup fbcpsr-1p-primscrn-pri-shrfb-draw-render:
fail   -> SKIP   (shard-snb)
Subgroup fbcpsr-2p-scndscrn-spr-indfb-fullscreen:
fail   -> SKIP   (shard-snb)
Subgroup psr-1p-primscrn-spr-indfb-onoff:
fail   -> SKIP   (shard-snb)
Subgroup psr-2p-scndscrn-cur-indfb-draw-mmap-wc:
fail   -> SKIP   (shard-snb)
Test kms_mmap_write_crc:
fail   -> PASS   (shard-snb)
Test kms_vblank:
Subgroup pipe-b-query-forked-busy-hang:
fail   -> PASS   (shard-snb)

 Known issues:

Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank-interruptible:
pass   -> FAIL   (shard-hsw) fdo#102887
Subgroup 2x-plain-flip-ts-check-interruptible:
pass   -> FAIL   (shard-hsw) fdo#100368 +4
Test kms_frontbuffer_tracking:
Subgroup fbc-2p-primscrn-shrfb-pgflip-blt:
fail   -> SKIP   (shard-snb) fdo#103167
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252

fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apltotal:2680 pass:1835 dwarn:1   dfail:0   fail:7   skip:836 
time:12678s
shard-hswtotal:2680 pass:1782 dwarn:1   dfail:0   fail:5   skip:891 
time:11365s
shard-snbtotal:2680 pass:1375 dwarn:1   dfail:0   fail:6   skip:1298 
time:6900s
Blacklisted hosts:
shard-kbltotal:2680 pass:1958 dwarn:4   dfail:0   fail:7   skip:711 
time:9262s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8631/shards.html
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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: Treat i915_reset_engine() as guilty until proven innocent

[Patchwork]

== Series Details ==

Series: drm/i915: Treat i915_reset_engine() as guilty until proven innocent
URL   : https://patchwork.freedesktop.org/series/41305/
State : warning

== Summary ==

 Possible new issues:

Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
fail   -> PASS   (shard-snb)
Test kms_cursor_crc:
Subgroup cursor-256x256-dpms:
fail   -> PASS   (shard-snb)
Subgroup cursor-256x256-offscreen:
fail   -> PASS   (shard-snb)
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> DMESG-WARN (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-pwrite:
fail   -> PASS   (shard-snb)
Subgroup fbc-1p-primscrn-shrfb-pgflip-blt:
fail   -> PASS   (shard-snb)
Subgroup fbc-modesetfrombusy:
fail   -> PASS   (shard-snb)
Subgroup fbcpsr-1p-offscren-pri-indfb-draw-blt:
fail   -> SKIP   (shard-snb)
Subgroup fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt:
fail   -> SKIP   (shard-snb)
Subgroup fbcpsr-1p-primscrn-pri-shrfb-draw-render:
fail   -> SKIP   (shard-snb)
Subgroup fbcpsr-2p-scndscrn-spr-indfb-fullscreen:
fail   -> SKIP   (shard-snb)
Subgroup psr-1p-primscrn-spr-indfb-onoff:
fail   -> SKIP   (shard-snb)
Subgroup psr-2p-scndscrn-cur-indfb-draw-mmap-wc:
fail   -> SKIP   (shard-snb)
Test kms_mmap_write_crc:
fail   -> PASS   (shard-snb)
Test kms_vblank:
Subgroup pipe-b-query-forked-busy-hang:
fail   -> PASS   (shard-snb)

 Known issues:

Test kms_flip:
Subgroup blocking-wf_vblank:
pass   -> FAIL   (shard-hsw) fdo#100368 +2
Test kms_frontbuffer_tracking:
Subgroup fbc-2p-primscrn-shrfb-pgflip-blt:
fail   -> SKIP   (shard-snb) fdo#103167
Test kms_sysfs_edid_timing:
warn   -> PASS   (shard-apl) fdo#100047
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apltotal:2680 pass:1836 dwarn:1   dfail:0   fail:7   skip:836 
time:12649s
shard-hswtotal:2680 pass:1782 dwarn:2   dfail:0   fail:4   skip:891 
time:11372s
shard-snbtotal:2680 pass:1377 dwarn:1   dfail:0   fail:3   skip:1299 
time:6920s
Blacklisted hosts:
shard-kbltotal:2680 pass:1961 dwarn:1   dfail:0   fail:7   skip:711 
time:9270s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8630/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: Send DPCD ON for MST before phy_up (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Send DPCD ON for MST before phy_up (rev2)
URL   : https://patchwork.freedesktop.org/series/41297/
State : success

== Summary ==

Series 41297v2 drm/i915/dp: Send DPCD ON for MST before phy_up
https://patchwork.freedesktop.org/api/1.0/series/41297/revisions/2/mbox/

 Known issues:

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
pass   -> FAIL   (fi-skl-6770hq) fdo#100368
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (fi-skl-6700k2) fdo#103191
Subgroup suspend-read-crc-pipe-c:
pass   -> FAIL   (fi-skl-guc) fdo#104108

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:432s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:442s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:381s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:541s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:297s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:513s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:510s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:517s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:510s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:412s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:562s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:513s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:585s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:425s
fi-gdg-551   total:285  pass:177  dwarn:0   dfail:0   fail:0   skip:108 
time:314s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:544s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:488s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:407s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:420s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:470s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:432s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:471s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:464s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:510s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:665s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:438s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:532s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:502s
fi-skl-6770hqtotal:285  pass:264  dwarn:0   dfail:0   fail:1   skip:20  
time:508s
fi-skl-guc   total:285  pass:256  dwarn:0   dfail:0   fail:1   skip:28  
time:429s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:441s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:582s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:399s

e023242a3ebab3e7a4e5d7647d7b08c0d2be5d4c drm-tip: 2018y-04m-06d-19h-07m-27s UTC 
integration manifest
7c0d355a8411 drm/i915/dp: Send DPCD ON for MST before phy_up

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8633/issues.html
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Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/debugfs: Print sink PSR status

[Dhinakaran Pandiyan]

On Sat, 2018-04-07 at 00:49 +, Souza, Jose wrote:
> On Fri, 2018-04-06 at 16:36 -0700, José Roberto de Souza wrote:
> > On Mon, 2018-04-02 at 15:38 -0700, Pandiyan, Dhinakaran wrote:
> > > On Mon, 2018-04-02 at 13:51 -0700, José Roberto de Souza wrote:
> > > > IGT tests could be improved with sink status, knowing for sure
> > > > that
> > > > hardware have activate or exit PSR.
> > > > 
> > > > Reviewed-by: Dhinakaran Pandiyan 
> > > 
> > > 
> > > Please don't merge this patch yet. While the patch itself is
> > > correct,
> > > testing it brings up an interesting problem.
> > > 
> > > Printing the sink_status() leads to power_get(aux_domain) which
> > > wakes
> > > up
> > > the display engine from DC5/6. This results in a HW triggered PSR
> > > exit,
> > > effectively altering the state that we are trying to read. I would
> > > like
> > > to understand the problem fully before merging the patch.
> > 
> > In my tests(PSR1 only) with DMC loaded, I can see HW trigerring PSR
> > exit when reading i915_edp_psr_status with or without this patch, the
> > event that caused is 'SRD Mask Reg Write'.
> > After masking EDP_PSR_DEBUG_MASK_DISP_REG_WRITE in EDP_PSR_DEBUG it
> > do
> > not happens with or without this patch.
> > 

Reads causing PSR exit is a concern, but I have seen edp_psr_status
showing PSR live status as active. If reads triggered exit, then it
should always be inactive. Unless the exit happens after the status is
read.

> > Masking this event did not bring more IGT errors than we have now,
> > what
> > do you think Dhinakaran? Should we mask it?
> 

We'll need PSR to exit on some register writes, example flips or cursor
moves. 

> Another information missed:
> 
> When doing a dpcd(I did not look at what exacly is causing it)
> transaction it is causing the HW to be awaken from DC6 with or without
> masking EDP_PSR_DEBUG_MASK_DISP_REG_WRITE 

This is expected, AUX_A is in the DC_OFF power domain, so the driver
forces a DC6 exit.

> but when masking it do not
> cause a PSR exit.
> Reading i915_sr_status also cause HW to be awaken from DC6.
> 

What hardware are you testing on? And is this a PSR2 panel?



> > 
> > > 
> > > 
> > > > Cc: Rodrigo Vivi 
> > > > Signed-off-by: José Roberto de Souza 
> > > > ---
> > > >  drivers/gpu/drm/i915/i915_debugfs.c | 29
> > > > +
> > > >  1 file changed, 29 insertions(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > index 1dba2c451255..c9ac946b62c9 100644
> > > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > @@ -2603,6 +2603,26 @@ static const char *psr2_live_status(u32
> > > > val)
> > > > return "unknown";
> > > >  }
> > > >  
> > > > +static const char *psr_sink_status(u8 val)
> > > > +{
> > > > +   static const char * const sink_status[] = {
> > > > +   "inactive",
> > > > +   "transition to active, capture and display",
> > > > +   "active, display from RFB",
> > > > +   "active, capture and display on sink device
> > > > timings",
> > > > +   "transition to inactive, capture and display,
> > > > timing re-sync",
> > > > +   "reserved",
> > > > +   "reserved",
> > > > +   "sink internal error"
> > > > +   };
> > > > +
> > > > +   val &= DP_PSR_SINK_STATE_MASK;
> > > > +   if (val < ARRAY_SIZE(sink_status))
> > > > +   return sink_status[val];
> > > > +
> > > > +   return "unknown";
> > > > +}
> > > > +
> > > >  static int i915_edp_psr_status(struct seq_file *m, void *data)
> > > >  {
> > > > struct drm_i915_private *dev_priv = node_to_i915(m-
> > > > > private);
> > > > 
> > > > @@ -2684,6 +2704,15 @@ static int i915_edp_psr_status(struct
> > > > seq_file *m, void *data)
> > > > seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
> > > >psr2, psr2_live_status(psr2));
> > > > }
> > > > +
> > > > +   if (dev_priv->psr.enabled) {
> > > > +   struct drm_dp_aux *aux = _priv->psr.enabled-
> > > > > aux;
> > > > 
> > > > +   u8 val;
> > > > +
> > > > +   if (drm_dp_dpcd_readb(aux, DP_PSR_STATUS, )
> > > > ==
> > > > 1)
> > > > +   seq_printf(m, "Sink PSR status: 0x%x
> > > > [%s]\n", val,
> > > > +  psr_sink_status(val));
> > > > +   }
> > > > mutex_unlock(_priv->psr.lock);
> > > >  
> > > > intel_runtime_pm_put(dev_priv);
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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[Intel-gfx] [PATCH v5] drm/i915/dp: Send DPCD ON for MST before phy_up

[Lyude Paul]

When doing a modeset where the sink is transitioning from D3 to D0 , it
would sometimes be possible for the initial power_up_phy() to start
timing out. This would only be observed in the last action before the
sink went into D3 mode was intel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We
originally thought this might be an issue with us accidentally shutting
off the aux block when putting the sink into D3, but since the DP spec
mandates that sinks must wake up within 1ms while we have 100ms to
respond to an ESI irq, this didn't really add up. Turns out that the
problem is more subtle then that:

It turns out that the timeout is from us not enabling DPMS on the MST
hub before actually trying to initiate sideband communications. This
would cause the first sideband communication (power_up_phy()), to start
timing out because the sink wasn't ready to respond. Afterwards, we
would call intel_dp_sink_dpms(DRM_MODE_DPMS_ON) in
intel_ddi_pre_enable_dp(), which would actually result in waking up the
sink so that sideband requests would work again.

Since DPMS is what lets us actually bring the hub up into a state where
sideband communications become functional again, we just need to make
sure to enable DPMS on the display before attempting to perform sideband
communications.

Changes since v1:
- Remove comment above if (!intel_dp->is_mst) - vsryjala
- Move intel_dp_sink_dpms() for MST into intel_dp_post_disable_mst() to
  keep enable/disable paths symmetrical
- Improve commit message - dhnkrn
Changes since v2:
- Only send DPMS off when we're disabling the last sink, and only send
  DPMS on when we're enabling the first sink - dhnkrn
Changes since v3:
- Check against is_mst, not intel_dp->is_mst - dhnkrn/vsyrjala

Signed-off-by: Lyude Paul 
Reviewed-by: Dhinakaran Pandiyan 
Reviewed-by: Ville Syrjälä 
Tested-by: Laura Abbott 
Cc: sta...@vger.kernel.org
Fixes: ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.")
---
No actual changes other than t-b and r-bs. Resending because I don't
have access to the "test latest revision again" button and I'm very much
sure these CI results are bogus.

 drivers/gpu/drm/i915/intel_ddi.c| 8 ++--
 drivers/gpu/drm/i915/intel_dp_mst.c | 8 +++-
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index a6672a9abd85..92cb26b18a9b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2324,7 +2324,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder 
*encoder,
intel_prepare_dp_ddi_buffers(encoder, crtc_state);
 
intel_ddi_init_dp_buf_reg(encoder);
-   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+   if (!is_mst)
+   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
@@ -2422,12 +2423,15 @@ static void intel_ddi_post_disable_dp(struct 
intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port = enc_to_dig_port(>base);
struct intel_dp *intel_dp = _port->dp;
+   bool is_mst = intel_crtc_has_type(old_crtc_state,
+ INTEL_OUTPUT_DP_MST);
 
/*
 * Power down sink before disabling the port, otherwise we end
 * up getting interrupts from the sink on detecting link loss.
 */
-   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
+   if (!is_mst)
+   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
 
intel_disable_ddi_buf(encoder);
 
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
b/drivers/gpu/drm/i915/intel_dp_mst.c
index c3de0918ee13..9e6956c08688 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -180,9 +180,11 @@ static void intel_mst_post_disable_dp(struct intel_encoder 
*encoder,
intel_dp->active_mst_links--;
 
intel_mst->connector = NULL;
-   if (intel_dp->active_mst_links == 0)
+   if (intel_dp->active_mst_links == 0) {
+   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
intel_dig_port->base.post_disable(_dig_port->base,
  old_crtc_state, NULL);
+   }
 
DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
 }
@@ -223,7 +225,11 @@ static void intel_mst_pre_enable_dp(struct intel_encoder 
*encoder,
 
DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
 
+   if (intel_dp->active_mst_links == 0)
+   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+
drm_dp_send_power_updown_phy(_dp->mst_mgr, connector->port, true);
+
if (intel_dp->active_mst_links == 0)
 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dp: Send DPCD ON for MST before phy_up

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Send DPCD ON for MST before phy_up
URL   : https://patchwork.freedesktop.org/series/41297/
State : failure

== Summary ==

 Possible new issues:

Test gem_pwrite:
Subgroup big-gtt-backwards:
pass   -> SKIP   (shard-apl)
Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
fail   -> PASS   (shard-snb)
Test kms_chv_cursor_fail:
Subgroup pipe-a-256x256-left-edge:
pass   -> FAIL   (shard-snb)
Subgroup pipe-b-256x256-right-edge:
pass   -> FAIL   (shard-snb)
Test kms_cursor_crc:
Subgroup cursor-256x256-dpms:
fail   -> PASS   (shard-snb)
Subgroup cursor-256x256-offscreen:
fail   -> PASS   (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-pwrite:
fail   -> PASS   (shard-snb)
Subgroup fbc-1p-primscrn-shrfb-pgflip-blt:
fail   -> PASS   (shard-snb)
Subgroup fbc-2p-scndscrn-indfb-msflip-blt:
skip   -> FAIL   (shard-snb)
Subgroup fbc-modesetfrombusy:
fail   -> PASS   (shard-snb)
Subgroup fbcpsr-1p-offscren-pri-indfb-draw-blt:
fail   -> SKIP   (shard-snb)
Subgroup fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt:
fail   -> SKIP   (shard-snb)
Subgroup fbcpsr-1p-primscrn-pri-shrfb-draw-render:
fail   -> SKIP   (shard-snb)
Subgroup fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc:
skip   -> FAIL   (shard-snb)
Subgroup fbcpsr-2p-scndscrn-spr-indfb-fullscreen:
fail   -> SKIP   (shard-snb)
Subgroup fbcpsr-rgb101010-draw-pwrite:
skip   -> FAIL   (shard-snb)
Subgroup psr-1p-offscren-pri-shrfb-draw-mmap-gtt:
skip   -> FAIL   (shard-snb)
Subgroup psr-1p-primscrn-spr-indfb-draw-mmap-cpu:
skip   -> FAIL   (shard-snb)
Subgroup psr-1p-primscrn-spr-indfb-onoff:
fail   -> SKIP   (shard-snb)
Subgroup psr-2p-primscrn-pri-shrfb-draw-blt:
skip   -> FAIL   (shard-snb)
Subgroup psr-2p-scndscrn-cur-indfb-draw-mmap-wc:
fail   -> SKIP   (shard-snb)
Test kms_mmap_write_crc:
fail   -> PASS   (shard-snb)
Test kms_vblank:
Subgroup pipe-b-query-forked-busy-hang:
fail   -> PASS   (shard-snb)

 Known issues:

Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
fail   -> PASS   (shard-hsw) fdo#100368 +1
Test kms_frontbuffer_tracking:
Subgroup fbc-2p-primscrn-shrfb-pgflip-blt:
fail   -> SKIP   (shard-snb) fdo#103167 +1
Test kms_sysfs_edid_timing:
warn   -> PASS   (shard-apl) fdo#100047
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apltotal:2680 pass:1835 dwarn:1   dfail:0   fail:7   skip:837 
time:12615s
shard-hswtotal:2680 pass:1786 dwarn:1   dfail:0   fail:1   skip:891 
time:11464s
shard-snbtotal:2680 pass:1375 dwarn:1   dfail:0   fail:12  skip:1292 
time:6944s
Blacklisted hosts:
shard-kbltotal:2680 pass:1950 dwarn:10  dfail:0   fail:8   skip:712 
time:9043s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8628/shards.html
___
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Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/debugfs: Print sink PSR status

[Souza, Jose]

On Fri, 2018-04-06 at 16:36 -0700, José Roberto de Souza wrote:
> On Mon, 2018-04-02 at 15:38 -0700, Pandiyan, Dhinakaran wrote:
> > On Mon, 2018-04-02 at 13:51 -0700, José Roberto de Souza wrote:
> > > IGT tests could be improved with sink status, knowing for sure
> > > that
> > > hardware have activate or exit PSR.
> > > 
> > > Reviewed-by: Dhinakaran Pandiyan 
> > 
> > 
> > Please don't merge this patch yet. While the patch itself is
> > correct,
> > testing it brings up an interesting problem.
> > 
> > Printing the sink_status() leads to power_get(aux_domain) which
> > wakes
> > up
> > the display engine from DC5/6. This results in a HW triggered PSR
> > exit,
> > effectively altering the state that we are trying to read. I would
> > like
> > to understand the problem fully before merging the patch.
> 
> In my tests(PSR1 only) with DMC loaded, I can see HW trigerring PSR
> exit when reading i915_edp_psr_status with or without this patch, the
> event that caused is 'SRD Mask Reg Write'.
> After masking EDP_PSR_DEBUG_MASK_DISP_REG_WRITE in EDP_PSR_DEBUG it
> do
> not happens with or without this patch.
> 
> Masking this event did not bring more IGT errors than we have now,
> what
> do you think Dhinakaran? Should we mask it?

Another information missed:

When doing a dpcd(I did not look at what exacly is causing it)
transaction it is causing the HW to be awaken from DC6 with or without
masking EDP_PSR_DEBUG_MASK_DISP_REG_WRITE but when masking it do not
cause a PSR exit.
Reading i915_sr_status also cause HW to be awaken from DC6.

> 
> > 
> > 
> > > Cc: Rodrigo Vivi 
> > > Signed-off-by: José Roberto de Souza 
> > > ---
> > >  drivers/gpu/drm/i915/i915_debugfs.c | 29
> > > +
> > >  1 file changed, 29 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > > b/drivers/gpu/drm/i915/i915_debugfs.c
> > > index 1dba2c451255..c9ac946b62c9 100644
> > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > @@ -2603,6 +2603,26 @@ static const char *psr2_live_status(u32
> > > val)
> > >   return "unknown";
> > >  }
> > >  
> > > +static const char *psr_sink_status(u8 val)
> > > +{
> > > + static const char * const sink_status[] = {
> > > + "inactive",
> > > + "transition to active, capture and display",
> > > + "active, display from RFB",
> > > + "active, capture and display on sink device
> > > timings",
> > > + "transition to inactive, capture and display,
> > > timing re-sync",
> > > + "reserved",
> > > + "reserved",
> > > + "sink internal error"
> > > + };
> > > +
> > > + val &= DP_PSR_SINK_STATE_MASK;
> > > + if (val < ARRAY_SIZE(sink_status))
> > > + return sink_status[val];
> > > +
> > > + return "unknown";
> > > +}
> > > +
> > >  static int i915_edp_psr_status(struct seq_file *m, void *data)
> > >  {
> > >   struct drm_i915_private *dev_priv = node_to_i915(m-
> > > > private);
> > > 
> > > @@ -2684,6 +2704,15 @@ static int i915_edp_psr_status(struct
> > > seq_file *m, void *data)
> > >   seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
> > >  psr2, psr2_live_status(psr2));
> > >   }
> > > +
> > > + if (dev_priv->psr.enabled) {
> > > + struct drm_dp_aux *aux = _priv->psr.enabled-
> > > > aux;
> > > 
> > > + u8 val;
> > > +
> > > + if (drm_dp_dpcd_readb(aux, DP_PSR_STATUS, )
> > > ==
> > > 1)
> > > + seq_printf(m, "Sink PSR status: 0x%x
> > > [%s]\n", val,
> > > +psr_sink_status(val));
> > > + }
> > >   mutex_unlock(_priv->psr.lock);
> > >  
> > >   intel_runtime_pm_put(dev_priv);
___
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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/psr: enable psr1 on psr2 panels

[Patchwork]

== Series Details ==

Series: drm/i915/psr: enable psr1 on psr2 panels
URL   : https://patchwork.freedesktop.org/series/41294/
State : warning

== Summary ==

 Possible new issues:

Test gem_mmap_gtt:
Subgroup forked-medium-copy-odd:
dmesg-warn -> PASS   (shard-hsw)
Test gem_pwrite:
Subgroup big-gtt-backwards:
pass   -> SKIP   (shard-apl)
Test kms_frontbuffer_tracking:
Subgroup fbc-2p-pri-indfb-multidraw:
dmesg-fail -> PASS   (shard-hsw)

 Known issues:

Test kms_cursor_legacy:
Subgroup 2x-long-flip-vs-cursor-legacy:
fail   -> PASS   (shard-hsw) fdo#104873
Test kms_rotation_crc:
Subgroup primary-rotation-180:
pass   -> FAIL   (shard-snb) fdo#103925
Test perf:
Subgroup polling:
pass   -> FAIL   (shard-hsw) fdo#102252

fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apltotal:2680 pass:1834 dwarn:1   dfail:0   fail:7   skip:837 
time:12673s
shard-hswtotal:2680 pass:1784 dwarn:1   dfail:0   fail:3   skip:891 
time:11422s
shard-snbtotal:2680 pass:1377 dwarn:1   dfail:0   fail:3   skip:1299 
time:6945s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8627/shards.html
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Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/debugfs: Print sink PSR status

[Souza, Jose]

On Mon, 2018-04-02 at 15:38 -0700, Pandiyan, Dhinakaran wrote:
> On Mon, 2018-04-02 at 13:51 -0700, José Roberto de Souza wrote:
> > IGT tests could be improved with sink status, knowing for sure that
> > hardware have activate or exit PSR.
> > 
> > Reviewed-by: Dhinakaran Pandiyan 
> 
> 
> Please don't merge this patch yet. While the patch itself is correct,
> testing it brings up an interesting problem.
> 
> Printing the sink_status() leads to power_get(aux_domain) which wakes
> up
> the display engine from DC5/6. This results in a HW triggered PSR
> exit,
> effectively altering the state that we are trying to read. I would
> like
> to understand the problem fully before merging the patch.

In my tests(PSR1 only) with DMC loaded, I can see HW trigerring PSR
exit when reading i915_edp_psr_status with or without this patch, the
event that caused is 'SRD Mask Reg Write'.
After masking EDP_PSR_DEBUG_MASK_DISP_REG_WRITE in EDP_PSR_DEBUG it do
not happens with or without this patch.

Masking this event did not bring more IGT errors than we have now, what
do you think Dhinakaran? Should we mask it?

> 
> 
> > Cc: Rodrigo Vivi 
> > Signed-off-by: José Roberto de Souza 
> > ---
> >  drivers/gpu/drm/i915/i915_debugfs.c | 29
> > +
> >  1 file changed, 29 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 1dba2c451255..c9ac946b62c9 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -2603,6 +2603,26 @@ static const char *psr2_live_status(u32 val)
> > return "unknown";
> >  }
> >  
> > +static const char *psr_sink_status(u8 val)
> > +{
> > +   static const char * const sink_status[] = {
> > +   "inactive",
> > +   "transition to active, capture and display",
> > +   "active, display from RFB",
> > +   "active, capture and display on sink device
> > timings",
> > +   "transition to inactive, capture and display,
> > timing re-sync",
> > +   "reserved",
> > +   "reserved",
> > +   "sink internal error"
> > +   };
> > +
> > +   val &= DP_PSR_SINK_STATE_MASK;
> > +   if (val < ARRAY_SIZE(sink_status))
> > +   return sink_status[val];
> > +
> > +   return "unknown";
> > +}
> > +
> >  static int i915_edp_psr_status(struct seq_file *m, void *data)
> >  {
> > struct drm_i915_private *dev_priv = node_to_i915(m-
> > >private);
> > @@ -2684,6 +2704,15 @@ static int i915_edp_psr_status(struct
> > seq_file *m, void *data)
> > seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
> >psr2, psr2_live_status(psr2));
> > }
> > +
> > +   if (dev_priv->psr.enabled) {
> > +   struct drm_dp_aux *aux = _priv->psr.enabled-
> > >aux;
> > +   u8 val;
> > +
> > +   if (drm_dp_dpcd_readb(aux, DP_PSR_STATUS, ) ==
> > 1)
> > +   seq_printf(m, "Sink PSR status: 0x%x
> > [%s]\n", val,
> > +  psr_sink_status(val));
> > +   }
> > mutex_unlock(_priv->psr.lock);
> >  
> > intel_runtime_pm_put(dev_priv);
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds

[Patchwork]

== Series Details ==

Series: series starting with [01/22] drm/i915/icl: Introduce initial Icelake 
Workarounds
URL   : https://patchwork.freedesktop.org/series/41311/
State : success

== Summary ==

Series 41311v1 series starting with [01/22] drm/i915/icl: Introduce initial 
Icelake Workarounds
https://patchwork.freedesktop.org/api/1.0/series/41311/revisions/1/mbox/

 Known issues:

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (fi-skl-6700k2) fdo#103191
Subgroup suspend-read-crc-pipe-c:
pass   -> INCOMPLETE (fi-bxt-dsi) fdo#103927

fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:429s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:443s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:379s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:535s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:297s
fi-bxt-dsi   total:243  pass:216  dwarn:0   dfail:0   fail:0   skip:26 
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:514s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:522s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:510s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:408s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:560s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:512s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:585s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:424s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:314s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:542s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:487s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:404s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:420s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:469s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:433s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:474s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:462s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:511s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:680s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:438s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:539s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:501s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:516s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:430s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:445s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:603s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:399s

e023242a3ebab3e7a4e5d7647d7b08c0d2be5d4c drm-tip: 2018y-04m-06d-19h-07m-27s UTC 
integration manifest
89766d724bb6 drm/i915/icl: WaEnableFloatBlendOptimization
0c932d845446 drm/i915/icl: WaForwardProgressSoftReset
0d55385321e3 drm/i915/icl: Wa_1406838659
e02a3689a546 drm/i915/icl: Wa_2006665173
e745da174634 drm/i915/icl: Wa_1604302699
1adc09d57d75 drm/i915/icl: Wa_1406680159 and Wa_2201832410
569a254c2ba9 drm/i915/icl: Wa_1405779004
a131ad41470f drm/i915/icl: Enable Sampler DFR
81ff9ff8112e drm/i915/icl: WaEnableStateCacheRedirectToCS
1a1f183539f7 drm/i915/icl: WaAllowUMDToModifySamplerMode
b17203f3ce71 drm/i915/icl: WaAllowUmdWriteTRTTRootTable
dfbd6e5e21fe drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
18a761359036 drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
117d3028b83a drm/i915/icl: WaSendPushConstantsFromMMIO
3c456f385e81 drm/i915/icl: WaDisCtxReload
97c509b92d34 drm/i915/icl: WaCL2SFHalfMaxAlloc
1d0fa9e70616 drm/i915/icl: WaDisableImprovedTdlClkGating
f3018a4d2c5b drm/i915/icl: WaDisableCleanEvicts
6c99c36530dd drm/i915/icl: WaL3BankAddressHashing
6b5802730b5d drm/i915/icl: WaModifyGamTlbPartitioning
dfd92fa235cd drm/i915/icl: WaGAPZPriorityScheme
080bab08b911 drm/i915/icl: Introduce initial Icelake Workarounds

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8632/issues.html

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Pass the set of guilty engines to i915_reset()

[Chris Wilson]

Quoting Michel Thierry (2018-04-06 23:35:43)
> I would s/BIT()/ENGINE_MASK()/g, but it's not like we enforce it 
> (engine_struck has BIT(engine->id)).

Done. ENGINE_MASK looks more semantically consistent with calling it
"stalled_mask, the set of guilty engines".
-Chris
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds

[Patchwork]

== Series Details ==

Series: series starting with [01/22] drm/i915/icl: Introduce initial Icelake 
Workarounds
URL   : https://patchwork.freedesktop.org/series/41311/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
080bab08b911 drm/i915/icl: Introduce initial Icelake Workarounds
-:45: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#45: FILE: drivers/gpu/drm/i915/i915_drv.h:2467:
+#define IS_ICL_REVID(p, since, until) \
+   (IS_ICELAKE(p) && IS_REVID(p, since, until))

total: 0 errors, 0 warnings, 1 checks, 112 lines checked
dfd92fa235cd drm/i915/icl: WaGAPZPriorityScheme
6b5802730b5d drm/i915/icl: WaModifyGamTlbPartitioning
6c99c36530dd drm/i915/icl: WaL3BankAddressHashing
f3018a4d2c5b drm/i915/icl: WaDisableCleanEvicts
1d0fa9e70616 drm/i915/icl: WaDisableImprovedTdlClkGating
97c509b92d34 drm/i915/icl: WaCL2SFHalfMaxAlloc
3c456f385e81 drm/i915/icl: WaDisCtxReload
117d3028b83a drm/i915/icl: WaSendPushConstantsFromMMIO
18a761359036 drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
dfbd6e5e21fe drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
b17203f3ce71 drm/i915/icl: WaAllowUmdWriteTRTTRootTable
1a1f183539f7 drm/i915/icl: WaAllowUMDToModifySamplerMode
81ff9ff8112e drm/i915/icl: WaEnableStateCacheRedirectToCS
a131ad41470f drm/i915/icl: Enable Sampler DFR
569a254c2ba9 drm/i915/icl: Wa_1405779004
1adc09d57d75 drm/i915/icl: Wa_1406680159 and Wa_2201832410
e745da174634 drm/i915/icl: Wa_1604302699
e02a3689a546 drm/i915/icl: Wa_2006665173
0d55385321e3 drm/i915/icl: Wa_1406838659
0c932d845446 drm/i915/icl: WaForwardProgressSoftReset
89766d724bb6 drm/i915/icl: WaEnableFloatBlendOptimization

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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Pass the set of guilty engines to i915_reset()

[Chris Wilson]

Quoting Michel Thierry (2018-04-06 23:35:43)
> On 4/6/2018 3:03 PM, Chris Wilson wrote:
> > -static u32 fake_hangcheck(struct i915_request *rq)
> > +static u32 fake_hangcheck(struct i915_request *rq, u32 mask)
> >   {
> > - u32 reset_count;
> > + struct i915_gpu_error *error = >i915->gpu_error;
> > + u32 reset_count = i915_reset_count(error);
> >   
> > - rq->engine->hangcheck.stalled = true;
> > - rq->engine->hangcheck.seqno = intel_engine_get_seqno(rq->engine);
> > + error->stalled_mask = mask;
> >   
> > - reset_count = i915_reset_count(>i915->gpu_error);
> > + smp_mb__before_atomic();
> checkpatch is going to complain about the lack of comment

checkpatch is seeing mb where there is only a barrier(). ;)
/* No really, set_bit must be after setting stalled_mask */

The other side is handled via wake_up_all() being a full barrier between
us and the other process.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Treat i915_reset_engine() as guilty until proven innocent

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Treat i915_reset_engine() as 
guilty until proven innocent
URL   : https://patchwork.freedesktop.org/series/41308/
State : success

== Summary ==

Series 41308v1 series starting with [1/2] drm/i915: Treat i915_reset_engine() 
as guilty until proven innocent
https://patchwork.freedesktop.org/api/1.0/series/41308/revisions/1/mbox/

 Known issues:

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (fi-skl-6700k2) fdo#103191

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:433s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:448s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:380s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:541s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:299s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:517s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:512s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:519s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:507s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:413s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:558s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:511s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:581s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:424s
fi-gdg-551   total:285  pass:177  dwarn:0   dfail:0   fail:0   skip:108 
time:317s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:540s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:488s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:405s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:429s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:470s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:431s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:474s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:460s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:511s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:661s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:442s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:539s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:502s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:507s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:431s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:449s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:599s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:406s

e023242a3ebab3e7a4e5d7647d7b08c0d2be5d4c drm-tip: 2018y-04m-06d-19h-07m-27s UTC 
integration manifest
5f19bbd1e5af drm/i915: Pass the set of guilty engines to i915_reset()
2957aaafaf83 drm/i915: Treat i915_reset_engine() as guilty until proven innocent

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8631/issues.html
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Pass the set of guilty engines to i915_reset()

[Michel Thierry]

On 4/6/2018 3:03 PM, Chris Wilson wrote:

Currently, we rely on inspecting the hangcheck state from within the
i915_reset() routines to determine which engines were guilty of the
hang. This is problematic for cases where we want to run
i915_handle_error() and call i915_reset() independently of hangcheck.
Instead of relying on the indirect parameter passing, turn it into an
explicit parameter providing the set of stalled engines which then are
treated as guilty until proven innocent.

While we are removing the implicit stalled parameter, also make the
reason into an explicit paramter to i915_reset(). We still need a

  parameter

back-channel for i915_handle_error() to hand over the task to the locked
waiter, but let's keep that its own channel rather than incriminate
another.

This leaves stalled/seqno as being private to hangcheck, with no more
nefarious snooping by reset, be it whole-device or per-engine. \o/

The only real issue now is that this makes it crystal clear that we
don't actually do any testing of hangcheck per se in
drv_selftest/live_hangcheck, merely of resets!

Don't tell anyone



Signed-off-by: Chris Wilson 
Cc: Michel Thierry 
Cc: Jeff McGee 
Cc: Mika Kuoppala 
---
  drivers/gpu/drm/i915/i915_drv.c   | 13 ++
  drivers/gpu/drm/i915/i915_drv.h   | 10 +---
  drivers/gpu/drm/i915/i915_gem.c   |  5 ++--
  drivers/gpu/drm/i915/i915_gpu_error.h |  3 +++
  drivers/gpu/drm/i915/i915_irq.c   | 12 ++---
  drivers/gpu/drm/i915/i915_request.c   |  6 +++--
  .../gpu/drm/i915/selftests/intel_hangcheck.c  | 25 ---
  7 files changed, 44 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7ce229c6f424..f770be18b2d7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1866,6 +1866,8 @@ static int i915_resume_switcheroo(struct drm_device *dev)
  /**
   * i915_reset - reset chip after a hang
   * @i915: #drm_i915_private to reset
+ * @stalled_mask: mask of the stalled engines with the guilty requests
+ * @reason: user error message for why we are resetting
   *
   * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
   * on failure.
@@ -1880,7 +1882,9 @@ static int i915_resume_switcheroo(struct drm_device *dev)
   *   - re-init interrupt state
   *   - re-init display
   */
-void i915_reset(struct drm_i915_private *i915)
+void i915_reset(struct drm_i915_private *i915,
+   unsigned int stalled_mask,
+   const char *reason)
  {
struct i915_gpu_error *error = >gpu_error;
int ret;
@@ -1899,9 +1903,8 @@ void i915_reset(struct drm_i915_private *i915)
if (!i915_gem_unset_wedged(i915))
goto wakeup;
  
-	if (error->reason)

-   dev_notice(i915->drm.dev,
-  "Resetting chip for %s\n", error->reason);
+   if (reason)
+   dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason);
error->reset_count++;
  
  	disable_irq(i915->drm.irq);

@@ -1944,7 +1947,7 @@ void i915_reset(struct drm_i915_private *i915)
goto error;
}
  
-	i915_gem_reset(i915);

+   i915_gem_reset(i915, stalled_mask);
intel_overlay_reset(i915);
  
  	/*

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6b3f2f651def..9bca104c409e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2701,8 +2701,11 @@ extern void i915_driver_unload(struct drm_device *dev);
  extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 
engine_mask);
  extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
  
-extern void i915_reset(struct drm_i915_private *i915);

-extern int i915_reset_engine(struct intel_engine_cs *engine, const char *msg);
+extern void i915_reset(struct drm_i915_private *i915,
+  unsigned int stalled_mask,
+  const char *reason);
+extern int i915_reset_engine(struct intel_engine_cs *engine,
+const char *reason);
  
  extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);

  extern int intel_reset_guc(struct drm_i915_private *dev_priv);
@@ -3126,7 +3129,8 @@ static inline u32 i915_reset_engine_count(struct 
i915_gpu_error *error,
  struct i915_request *
  i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
  int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
-void i915_gem_reset(struct drm_i915_private *dev_priv);
+void i915_gem_reset(struct drm_i915_private *dev_priv,
+   unsigned int stalled_mask);
  void i915_gem_reset_finish_engine(struct intel_engine_cs *engine);
  void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
  void 

[Intel-gfx] [PATCH 14/22] drm/i915/icl: WaEnableStateCacheRedirectToCS

[Oscar Mateo]

Redirects the state cache to the CS Command buffer section for
performance reasons.

v2: Rebased

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h| 1 +
 drivers/gpu/drm/i915/intel_engine_cs.c | 4 
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f2ae3cf..3bec6b1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7150,6 +7150,7 @@ enum {
 #define  DISABLE_PIXEL_MASK_CAMMING(1<<14)
 
 #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
+#define   GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
 
 #define GEN7_L3SQCREG1 _MMIO(0xB010)
 #define  VLV_B0_WA_L3SQCREG1_VALUE 0x00D3
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 8337301..d0c382e 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1495,6 +1495,10 @@ static int icl_init_workarounds(struct intel_engine_cs 
*engine)
WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
  GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
 
+   /* WaEnableStateCacheRedirectToCS:icl */
+   WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
+ GEN11_STATE_CACHE_REDIRECT_TO_CS);
+
/* WaSendPushConstantsFromMMIO:icl */
ret = wa_ring_whitelist_reg(engine, COMMON_SLICE_CHICKEN2);
if (ret)
-- 
1.9.1

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[Intel-gfx] [PATCH 21/22] drm/i915/icl: WaForwardProgressSoftReset

[Oscar Mateo]

Avoids a hang during soft reset.

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h | 5 +
 drivers/gpu/drm/i915/intel_pm.c | 8 
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index af4fee2..408697b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9703,6 +9703,11 @@ enum skl_power_gate {
 #define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers 
*/
 #define GEN9_BLT_MOCS(i)   _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS 
registers */
 
+#define GEN10_SCRATCH_LNCF2_MMIO(0xb0a0)
+#define   PMFLUSHDONE_LNICRSDROP   (1 << 20)
+#define   PMFLUSH_GAPL3UNBLOCK (1 << 21)
+#define   PMFLUSHDONE_LNEBLK   (1 << 22)
+
 /* gamt regs */
 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for 
LRA1/2 */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1acc719..b1c00e5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8581,6 +8581,14 @@ static void icl_init_clock_gating(struct 
drm_i915_private *dev_priv)
I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
   (I915_READ(INF_UNIT_LEVEL_CLKGATE) |
CGPSF_CLKGATE_DIS));
+
+   /* WaForwardProgressSoftReset:icl (pre-prod) */
+   if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+   I915_WRITE(GEN10_SCRATCH_LNCF2,
+  (I915_READ(GEN10_SCRATCH_LNCF2) |
+   PMFLUSHDONE_LNICRSDROP |
+   PMFLUSH_GAPL3UNBLOCK |
+   PMFLUSHDONE_LNEBLK));
 }
 
 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing

[Oscar Mateo]

Revert to an L3 non-hash model, for performance reasons.

v2:
  - Place the WA name above the actual change
  - Improve the register naming
v3:
  - Rebased
  - Renamed to Wa_1604223664

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h |  6 ++
 drivers/gpu/drm/i915/intel_pm.c | 20 
 2 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 78abb49..10ed35f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8199,6 +8199,12 @@ enum {
 #define GEN8_GARBCNTL  _MMIO(0xB004)
 #define   GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
 #define   GEN11_ARBITRATION_PRIO_ORDER_MASK(0x3f << 22)
+#define   GEN11_HASH_CTRL_EXCL_MASK(0x7f << 0)
+#define   GEN11_HASH_CTRL_EXCL_BIT0(1 << 0)
+
+#define GEN11_GLBLINVL _MMIO(0xB404)
+#define   GEN11_BANK_HASH_ADDR_EXCL_BIT0   (1 << 0)
+#define   GEN11_BANK_HASH_ADDR_EXCL_MASK   (0x3f << 5)
 
 #define GEN11_GACB_PERF_CTRL   _MMIO(0x4B80)
 #define   GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 03c5de3..58974fa 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8513,11 +8513,23 @@ static void icl_init_clock_gating(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES));
 
-   /* Wa_1405543622:icl
-* Formerly known as WaGAPZPriorityScheme
+   I915_WRITE(GEN8_GARBCNTL,
+  /* Wa_1604223664:icl
+   * Formerly known as WaL3BankAddressHashing
+   */
+  ((I915_READ(GEN8_GARBCNTL) & ~GEN11_HASH_CTRL_EXCL_MASK) |
+   GEN11_HASH_CTRL_EXCL_BIT0 |
+   /* Wa_1405543622:icl
+* Formerly known as WaGAPZPriorityScheme
+*/
+   GEN11_ARBITRATION_PRIO_ORDER_MASK));
+
+   /* Wa_1604223664:icl
+* Formerly known as WaL3BankAddressHashing
 */
-   I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
-  GEN11_ARBITRATION_PRIO_ORDER_MASK));
+   I915_WRITE(GEN11_GLBLINVL,
+  ((I915_READ(GEN11_GLBLINVL) & 
~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
+   GEN11_BANK_HASH_ADDR_EXCL_BIT0));
 
/* WaModifyGamTlbPartitioning:icl */
I915_WRITE(GEN11_GACB_PERF_CTRL,
-- 
1.9.1

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[Intel-gfx] [PATCH 15/22] drm/i915/icl: Enable Sampler DFR

[Oscar Mateo]

Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
power by dynamically changing its clock frequency in low-throughput
conditions. This patches enables it by default on Gen11.

v2: Wrong operation to clear the bit (Praveen)

Cc: Sagar Arun Kamble 
Cc: Praveen Paneri 
Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_pm.c | 4 
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3bec6b1..f2a42a3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8220,6 +8220,9 @@ enum {
 #define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
 #define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE  (1 << 7)
 
+#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
+#define   DFR_DISABLE  (1 << 9)
+
 #define TR_VA_TTL3_PTR_DW0 _MMIO(0x4DE0)
 #define TR_VA_TTL3_PTR_DW1 _MMIO(0x4DE4)
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c5bf71b..8f1d028 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8505,6 +8505,10 @@ static void icl_init_clock_gating(struct 
drm_i915_private *dev_priv)
I915_WRITE(_3D_CHICKEN3,
   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
 
+   /* This is not an Wa. Enable to reduce Sampler power */
+   I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
+  (I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE));
+
/* WaInPlaceDecompressionHang:icl */
I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) 
|
 
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
-- 
1.9.1

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[Intel-gfx] [PATCH 10/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2

[Oscar Mateo]

Required to dinamically set 'Small PL Lossless Fix Enable'

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: For whatever reason, this ended up in KBL (??!!)

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 884df09..ada80c1 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1500,6 +1500,11 @@ static int icl_init_workarounds(struct intel_engine_cs 
*engine)
if (ret)
return ret;
 
+   /* WaAllowUMDToModifyHalfSliceChicken2:icl */
+   ret = wa_ring_whitelist_reg(engine, HALF_SLICE_CHICKEN2);
+   if (ret)
+   return ret;
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 19/22] drm/i915/icl: Wa_2006665173

[Oscar Mateo]

Disable blend embellishment in RCC.

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h| 18 +++---
 drivers/gpu/drm/i915/intel_engine_cs.c |  5 +
 2 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b1894f6..84e5a59 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7135,13 +7135,17 @@ enum {
 
 /* GEN7 chicken */
 #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
-# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
-# define GEN9_RHWO_OPTIMIZATION_DISABLE(1<<14)
-#define COMMON_SLICE_CHICKEN2  _MMIO(0x7014)
-# define GEN9_PBE_COMPRESSED_HASH_SELECTION(1<<13)
-# define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12)
-# define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
-# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE  (1<<0)
+  #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC((1 << 10) | (1 << 26))
+  #define GEN9_RHWO_OPTIMIZATION_DISABLE   (1 << 14)
+
+#define COMMON_SLICE_CHICKEN2  _MMIO(0x7014)
+  #define GEN9_PBE_COMPRESSED_HASH_SELECTION   (1 << 13)
+  #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE   (1 << 12)
+  #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8)
+  #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0)
+
+#define GEN11_COMMON_SLICE_CHICKEN3_MMIO(0x7304)
+  #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC   (1 << 11)
 
 #define HIZ_CHICKEN_MMIO(0x7018)
 # define CHV_HZ_8X8_MODE_IN_1X (1<<15)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index d0c382e..872dd15 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1499,6 +1499,11 @@ static int icl_init_workarounds(struct intel_engine_cs 
*engine)
WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
  GEN11_STATE_CACHE_REDIRECT_TO_CS);
 
+   /* Wa_2006665173:icl (pre-prod) */
+   if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+   WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
+ GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
+
/* WaSendPushConstantsFromMMIO:icl */
ret = wa_ring_whitelist_reg(engine, COMMON_SLICE_CHICKEN2);
if (ret)
-- 
1.9.1

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[Intel-gfx] [PATCH 12/22] drm/i915/icl: WaAllowUmdWriteTRTTRootTable

[Oscar Mateo]

Required for TR-TT (Tiled Resource Translation Table) support.

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: For whatever reason, this ended up in KBL (??!!)

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h| 3 +++
 drivers/gpu/drm/i915/intel_engine_cs.c | 8 
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 004a4db..04f2dd5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8219,6 +8219,9 @@ enum {
 #define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
 #define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE  (1 << 7)
 
+#define TR_VA_TTL3_PTR_DW0 _MMIO(0x4DE0)
+#define TR_VA_TTL3_PTR_DW1 _MMIO(0x4DE4)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 7fb7283..9400f4f 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1510,6 +1510,14 @@ static int icl_init_workarounds(struct intel_engine_cs 
*engine)
if (ret)
return ret;
 
+   /* WaAllowUmdWriteTRTTRootTable:icl */
+   ret = wa_ring_whitelist_reg(engine, TR_VA_TTL3_PTR_DW0);
+   if (ret)
+   return ret;
+   ret = wa_ring_whitelist_reg(engine, TR_VA_TTL3_PTR_DW1);
+   if (ret)
+   return ret;
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc

[Oscar Mateo]

This workarounds an issue with insufficient storage for the
CL2 and SF units.

v2: Renamed to Wa_1405766107
v3: Wrapped the commit message

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h | 4 
 drivers/gpu/drm/i915/intel_pm.c | 7 +++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 67664d0..cb5d117 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8212,6 +8212,10 @@ enum {
 #define   GEN11_HASH_CTRL_BIT0 (1 << 0)
 #define   GEN11_HASH_CTRL_BIT4 (1 << 12)
 
+#define GEN11_LSN_UNSLCVC  _MMIO(0xB43C)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC (1 << 9)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC  (1 << 7)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 84d9910..3843c28 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8541,6 +8541,13 @@ static void icl_init_clock_gating(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN11_GACB_PERF_CTRL,
   ((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4));
+
+   /* Wa_1405766107:icl
+* Formerly known as WaCL2SFHalfMaxAlloc
+*/
+   I915_WRITE(GEN11_LSN_UNSLCVC, (I915_READ(GEN11_LSN_UNSLCVC) |
+  GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
+  
GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC));
 }
 
 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 16/22] drm/i915/icl: Wa_1405779004

[Oscar Mateo]

Disable MSC clock gating to prevent data corruption.

BSpec: 19257

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 6 ++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f2a42a3..18f8c41 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3825,6 +3825,7 @@ enum {
 #define SLICE_UNIT_LEVEL_CLKGATE   _MMIO(0x94d4)
 #define  SARBUNIT_CLKGATE_DIS  (1 << 5)
 #define  RCCUNIT_CLKGATE_DIS   (1 << 7)
+#define  MSCUNIT_CLKGATE_DIS   (1 << 10)
 
 #define SUBSLICE_UNIT_LEVEL_CLKGATE_MMIO(0x9524)
 #define  GWUNIT_CLKGATE_DIS(1 << 16)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8f1d028..68f1b60 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8558,6 +8558,12 @@ static void icl_init_clock_gating(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN11_LSN_UNSLCVC, (I915_READ(GEN11_LSN_UNSLCVC) |
   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
   
GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC));
+
+   /* Wa_1405779004:icl (pre-prod) */
+   if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+   I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
+  (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
+   MSCUNIT_CLKGATE_DIS));
 }
 
 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 17/22] drm/i915/icl: Wa_1406680159 and Wa_2201832410

[Oscar Mateo]

Disable GWL clock gating to prevent two different issues that
might cause hangs.

Please notice that one of the issues is pre-production only.

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_pm.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 68f1b60..2b7b88b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8564,6 +8564,12 @@ static void icl_init_clock_gating(struct 
drm_i915_private *dev_priv)
I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
   (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
MSCUNIT_CLKGATE_DIS));
+
+   /* Wa_1406680159:icl */
+   /* Wa_2201832410:icl (pre-prod, only until C0) */
+   I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
+  (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
+   GWUNIT_CLKGATE_DIS));
 }
 
 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

[Oscar Mateo]

Inherit workarounds from previous platforms that are still valid for
Icelake.

v2: GEN7_ROW_CHICKEN2 is masked
v3:
  - Since it has been fixed already in upstream, removed the TODO
comment about WA_SET_BIT for WaInPlaceDecompressionHang.
  - Squashed with this patch:
  drm/i915/icl: add icelake_init_clock_gating()
from Paulo Zanoni 
  - Squashed with this patch:
  drm/i915/icl: WaForceEnableNonCoherent
from Oscar Mateo 
  - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
applies to B0 as well.
  - WaPipeControlBefore3DStateSamplePattern WABB was being applied
to ICL incorrectly.
v4:
  - Wrap the commit message
  - s/dev_priv/p to please checkpatch

Cc: Tomasz Lis 
Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_drv.h|  9 +
 drivers/gpu/drm/i915/i915_gem_gtt.c|  4 ++--
 drivers/gpu/drm/i915/i915_reg.h|  1 +
 drivers/gpu/drm/i915/intel_engine_cs.c | 25 +
 drivers/gpu/drm/i915/intel_lrc.c   |  2 ++
 drivers/gpu/drm/i915/intel_pm.c| 19 ++-
 6 files changed, 57 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5373b17..1a4801e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2458,6 +2458,15 @@ static inline unsigned int i915_sg_segment_size(void)
 #define IS_CNL_REVID(p, since, until) \
(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
 
+#define ICL_REVID_A0   0x0
+#define ICL_REVID_A2   0x1
+#define ICL_REVID_B0   0x3
+#define ICL_REVID_B2   0x4
+#define ICL_REVID_C0   0x5
+
+#define IS_ICL_REVID(p, since, until) \
+   (IS_ICELAKE(p) && IS_REVID(p, since, until))
+
 /*
  * The genX designation typically refers to the render engine, so render
  * capability related checks should use IS_GEN, while display and other checks
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 21d72f6..221b873 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct 
drm_i915_private *dev_priv)
 * called on driver load and after a GPU reset, so you can place
 * workarounds here even if they get overwritten by GPU reset.
 */
-   /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
+   /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
if (IS_BROADWELL(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
else if (IS_CHERRYVIEW(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
-   else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
+   else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || 
IS_GEN11(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
else if (IS_GEN9_LP(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 176dca6..6cd2f2a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7184,6 +7184,7 @@ enum {
 /* GEN8 chicken */
 #define HDC_CHICKEN0   _MMIO(0x7300)
 #define CNL_HDC_CHICKEN0   _MMIO(0xE5F0)
+#define ICL_HDC_CHICKEN0   _MMIO(0xE5F4)
 #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE(1<<15)
 #define  HDC_FENCE_DEST_SLM_DISABLE(1<<14)
 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED   (1<<11)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 12486d8..ba8c137 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1467,6 +1467,29 @@ static int cfl_init_workarounds(struct intel_engine_cs 
*engine)
return 0;
 }
 
+static int icl_init_workarounds(struct intel_engine_cs *engine)
+{
+   struct drm_i915_private *dev_priv = engine->i915;
+
+   /* Wa_1604370585:icl (pre-prod)
+* Formerly known as WaPushConstantDereferenceHoldDisable
+*/
+   if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+   WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ PUSH_CONSTANT_DEREF_DISABLE);
+
+   /* WaForceEnableNonCoherent:icl
+* This is not the same workaround as in early Gen9 platforms, where
+* lacking this could cause system hangs, but coherency performance
+* overhead is high and only a few compute workloads really need it
+* (the register is whitelisted in hardware now, so UMDs can opt in
+ 

[Intel-gfx] [PATCH 13/22] drm/i915/icl: WaAllowUMDToModifySamplerMode

[Oscar Mateo]

Required for Bindless samplers.

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h| 2 ++
 drivers/gpu/drm/i915/intel_engine_cs.c | 5 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 04f2dd5..f2ae3cf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8222,6 +8222,8 @@ enum {
 #define TR_VA_TTL3_PTR_DW0 _MMIO(0x4DE0)
 #define TR_VA_TTL3_PTR_DW1 _MMIO(0x4DE4)
 
+#define GEN10_SAMPLER_MODE _MMIO(0xE18C)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 9400f4f..8337301 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1518,6 +1518,11 @@ static int icl_init_workarounds(struct intel_engine_cs 
*engine)
if (ret)
return ret;
 
+   /* WaAllowUMDToModifySamplerMode:icl */
+   ret = wa_ring_whitelist_reg(engine, GEN10_SAMPLER_MODE);
+   if (ret)
+   return ret;
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 11/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7

[Oscar Mateo]

Required to dinamically set 'Trilinear Filter Quality Mode'

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: For whatever reason, this ended up in KBL (??!!)

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index ada80c1..7fb7283 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1505,6 +1505,11 @@ static int icl_init_workarounds(struct intel_engine_cs 
*engine)
if (ret)
return ret;
 
+   /* WaAllowUMDToModifyHalfSliceChicken7:icl */
+   ret = wa_ring_whitelist_reg(engine, GEN9_HALF_SLICE_CHICKEN7);
+   if (ret)
+   return ret;
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 02/22] drm/i915/icl: WaGAPZPriorityScheme

[Oscar Mateo]

The default GAPZ arbitrer priority value at power-on has been found
to be incorrect.

v2: Now renamed to Wa_1405543622

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h | 5 +++--
 drivers/gpu/drm/i915/intel_pm.c | 6 ++
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6cd2f2a..cd5da2b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8196,8 +8196,9 @@ enum {
 #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE   (1<<4)
 #define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6)
 
-#define GEN8_GARBCNTL   _MMIO(0xB004)
-#define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
+#define GEN8_GARBCNTL  _MMIO(0xB004)
+#define   GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
+#define   GEN11_ARBITRATION_PRIO_ORDER_MASK(0x3f << 22)
 
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4f4c7ae..d1b98ae 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8512,6 +8512,12 @@ static void icl_init_clock_gating(struct 
drm_i915_private *dev_priv)
/* WaPipelineFlushCoherentLines:icl */
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES));
+
+   /* Wa_1405543622:icl
+* Formerly known as WaGAPZPriorityScheme
+*/
+   I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
+  GEN11_ARBITRATION_PRIO_ORDER_MASK));
 }
 
 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 18/22] drm/i915/icl: Wa_1604302699

[Oscar Mateo]

Disable I2M Write for performance reasons.

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h | 4 +++-
 drivers/gpu/drm/i915/intel_pm.c | 5 +
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 18f8c41..b1894f6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7174,7 +7174,9 @@ enum {
 #define GEN7_L3CNTLREG3_MMIO(0xB024)
 
 #define GEN7_L3_CHICKEN_MODE_REGISTER  _MMIO(0xB030)
-#define  GEN7_WA_L3_CHICKEN_MODE   0x2000
+#define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xB114)
+#define  GEN7_WA_L3_CHICKEN_MODE   0x2000
+#define  GEN11_I2M_WRITE_DISABLE   (1 << 28)
 
 #define GEN7_L3SQCREG4 _MMIO(0xb034)
 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE   (1<<27)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2b7b88b..9771f56 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8570,6 +8570,11 @@ static void icl_init_clock_gating(struct 
drm_i915_private *dev_priv)
I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
   (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
GWUNIT_CLKGATE_DIS));
+
+   /* Wa_1604302699:icl */
+   I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER,
+  (I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) |
+   GEN11_I2M_WRITE_DISABLE));
 }
 
 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 20/22] drm/i915/icl: Wa_1406838659

[Oscar Mateo]

Disable CGPSF unit clock gating to prevent an issue.

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h | 13 -
 drivers/gpu/drm/i915/intel_pm.c |  6 ++
 2 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 84e5a59..af4fee2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3823,15 +3823,18 @@ enum {
  * GEN10 clock gating regs
  */
 #define SLICE_UNIT_LEVEL_CLKGATE   _MMIO(0x94d4)
-#define  SARBUNIT_CLKGATE_DIS  (1 << 5)
-#define  RCCUNIT_CLKGATE_DIS   (1 << 7)
-#define  MSCUNIT_CLKGATE_DIS   (1 << 10)
+#define   SARBUNIT_CLKGATE_DIS (1 << 5)
+#define   RCCUNIT_CLKGATE_DIS  (1 << 7)
+#define   MSCUNIT_CLKGATE_DIS  (1 << 10)
 
 #define SUBSLICE_UNIT_LEVEL_CLKGATE_MMIO(0x9524)
-#define  GWUNIT_CLKGATE_DIS(1 << 16)
+#define   GWUNIT_CLKGATE_DIS   (1 << 16)
 
 #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
-#define  VFUNIT_CLKGATE_DIS(1 << 20)
+#define   VFUNIT_CLKGATE_DIS   (1 << 20)
+
+#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
+#define   CGPSF_CLKGATE_DIS(1 << 3)
 
 /*
  * Display engine regs
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9771f56..1acc719 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8575,6 +8575,12 @@ static void icl_init_clock_gating(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER,
   (I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) |
GEN11_I2M_WRITE_DISABLE));
+
+   /* Wa_1406838659:icl (pre-prod) */
+   if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_C0))
+   I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
+  (I915_READ(INF_UNIT_LEVEL_CLKGATE) |
+   CGPSF_CLKGATE_DIS));
 }
 
 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 06/22] drm/i915/icl: WaDisableImprovedTdlClkGating

[Oscar Mateo]

Revert to the legacy implementation.

v2: GEN7_ROW_CHICKEN2 is masked
v3:
  - Rebased
  - Renamed to Wa_2006611047
  - A0 and B0 only
v4:
  - Add spaces around '<<' (and fix the surrounding code as well)
  - Mark the WA as pre-prod

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h| 5 +++--
 drivers/gpu/drm/i915/intel_engine_cs.c | 7 +++
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 699135b..67664d0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8249,8 +8249,9 @@ enum {
 
 #define GEN7_ROW_CHICKEN2  _MMIO(0xe4f4)
 #define GEN7_ROW_CHICKEN2_GT2  _MMIO(0xf4f4)
-#define   DOP_CLOCK_GATING_DISABLE (1<<0)
-#define   PUSH_CONSTANT_DEREF_DISABLE  (1<<8)
+#define   DOP_CLOCK_GATING_DISABLE (1 << 0)
+#define   PUSH_CONSTANT_DEREF_DISABLE  (1 << 8)
+#define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE   (1 << 1)
 
 #define HSW_ROW_CHICKEN3   _MMIO(0xe49c)
 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE(1 << 6)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index ba8c137..eb2f46e 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1487,6 +1487,13 @@ static int icl_init_workarounds(struct intel_engine_cs 
*engine)
 */
WA_SET_BIT_MASKED(ICL_HDC_CHICKEN0, HDC_FORCE_NON_COHERENT);
 
+   /* Wa_2006611047:icl (pre-prod)
+* Formerly known as WaDisableImprovedTdlClkGating
+*/
+   if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+   WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 22/22] drm/i915/icl: WaEnableFloatBlendOptimization

[Oscar Mateo]

Enables blend optimization for floating point RTs

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h| 3 +++
 drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 408697b..c5a1b18 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2651,6 +2651,9 @@ enum i915_power_well_id {
 #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE(1<<6)
 #define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE   (1<<1)
 
+#define GEN10_CACHE_MODE_SS_MMIO(0xe420)
+#define   FLOAT_BLEND_OPTIMIZATION_ENABLE  (1 << 4)
+
 #define GEN6_BLITTER_ECOSKPD   _MMIO(0x221d0)
 #define   GEN6_BLITTER_LOCK_SHIFT  16
 #define   GEN6_BLITTER_FBC_NOTIFY  (1<<3)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 872dd15..c35f40b 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1504,6 +1504,9 @@ static int icl_init_workarounds(struct intel_engine_cs 
*engine)
WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
  GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
 
+   /* WaEnableFloatBlendOptimization:icl */
+   WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS, FLOAT_BLEND_OPTIMIZATION_ENABLE);
+
/* WaSendPushConstantsFromMMIO:icl */
ret = wa_ring_whitelist_reg(engine, COMMON_SLICE_CHICKEN2);
if (ret)
-- 
1.9.1

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[Intel-gfx] [PATCH 09/22] drm/i915/icl: WaSendPushConstantsFromMMIO

[Oscar Mateo]

Allows UMDs to set 'Disable Gather at Set Shader Common Slice'.

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it...

v2: Rebased

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index eb2f46e..884df09 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1470,6 +1470,7 @@ static int cfl_init_workarounds(struct intel_engine_cs 
*engine)
 static int icl_init_workarounds(struct intel_engine_cs *engine)
 {
struct drm_i915_private *dev_priv = engine->i915;
+   int ret;
 
/* Wa_1604370585:icl (pre-prod)
 * Formerly known as WaPushConstantDereferenceHoldDisable
@@ -1494,6 +1495,11 @@ static int icl_init_workarounds(struct intel_engine_cs 
*engine)
WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
  GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
 
+   /* WaSendPushConstantsFromMMIO:icl */
+   ret = wa_ring_whitelist_reg(engine, COMMON_SLICE_CHICKEN2);
+   if (ret)
+   return ret;
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 03/22] drm/i915/icl: WaModifyGamTlbPartitioning

[Oscar Mateo]

Adjust default GAM TLB partitioning for performance reasons.

v2: Only touch the bits that we really need

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h | 5 +
 drivers/gpu/drm/i915/intel_pm.c | 5 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cd5da2b..78abb49 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8200,6 +8200,11 @@ enum {
 #define   GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
 #define   GEN11_ARBITRATION_PRIO_ORDER_MASK(0x3f << 22)
 
+#define GEN11_GACB_PERF_CTRL   _MMIO(0x4B80)
+#define   GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
+#define   GEN11_HASH_CTRL_BIT0 (1 << 0)
+#define   GEN11_HASH_CTRL_BIT4 (1 << 12)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d1b98ae..03c5de3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8518,6 +8518,11 @@ static void icl_init_clock_gating(struct 
drm_i915_private *dev_priv)
 */
I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
   GEN11_ARBITRATION_PRIO_ORDER_MASK));
+
+   /* WaModifyGamTlbPartitioning:icl */
+   I915_WRITE(GEN11_GACB_PERF_CTRL,
+  ((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
+   GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4));
 }
 
 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 08/22] drm/i915/icl: WaDisCtxReload

[Oscar Mateo]

Revert to the legacy implementation to avoid a system hang.

v2: Correct the address for GAMW_ECO_DEV_RW_IA_REG
v3: Renamed to Wa_220166154

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_pm.c | 6 ++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cb5d117..004a4db 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8216,6 +8216,9 @@ enum {
 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC (1 << 9)
 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC  (1 << 7)
 
+#define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
+#define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE  (1 << 7)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3843c28..c5bf71b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8519,6 +8519,12 @@ static void icl_init_clock_gating(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN11_LQSC_CLEAN_EVICT_DISABLE));
 
+   /* Wa_220166154:icl
+* Formerly known as WaDisCtxReload
+*/
+   I915_WRITE(GAMW_ECO_DEV_RW_IA_REG, (I915_READ(GAMW_ECO_DEV_RW_IA_REG) |
+   GAMW_ECO_DEV_CTX_RELOAD_DISABLE));
+
I915_WRITE(GEN8_GARBCNTL,
   /* Wa_1604223664:icl
* Formerly known as WaL3BankAddressHashing
-- 
1.9.1

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[Intel-gfx] [PATCH 05/22] drm/i915/icl: WaDisableCleanEvicts

[Oscar Mateo]

Avoids an undefined LLC behavior.

BSpec: 9613

v2: Renamed to Wa_1405733216
v3: Spaces around '<<' and fix surrounding code

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h | 5 +++--
 drivers/gpu/drm/i915/intel_pm.c | 6 ++
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 10ed35f..699135b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7178,8 +7178,9 @@ enum {
 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE   (1<<27)
 
 #define GEN8_L3SQCREG4 _MMIO(0xb118)
-#define  GEN8_LQSC_RO_PERF_DIS (1<<27)
-#define  GEN8_LQSC_FLUSH_COHERENT_LINES(1<<21)
+#define  GEN11_LQSC_CLEAN_EVICT_DISABLE(1 << 6)
+#define  GEN8_LQSC_RO_PERF_DIS (1 << 27)
+#define  GEN8_LQSC_FLUSH_COHERENT_LINES(1 << 21)
 
 /* GEN8 chicken */
 #define HDC_CHICKEN0   _MMIO(0x7300)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 58974fa..84d9910 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8513,6 +8513,12 @@ static void icl_init_clock_gating(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES));
 
+   /* Wa_1405733216:icl
+* Formerly known as WaDisableCleanEvicts
+*/
+   I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
+   GEN11_LQSC_CLEAN_EVICT_DISABLE));
+
I915_WRITE(GEN8_GARBCNTL,
   /* Wa_1604223664:icl
* Formerly known as WaL3BankAddressHashing
-- 
1.9.1

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Treat i915_reset_engine() as guilty until proven innocent

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Treat i915_reset_engine() as 
guilty until proven innocent
URL   : https://patchwork.freedesktop.org/series/41308/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
2957aaafaf83 drm/i915: Treat i915_reset_engine() as guilty until proven innocent
5f19bbd1e5af drm/i915: Pass the set of guilty engines to i915_reset()
-:15: WARNING:TYPO_SPELLING: 'paramter' may be misspelled - perhaps 'parameter'?
#15: 
reason into an explicit paramter to i915_reset(). We still need a

-:87: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files
#87: FILE: drivers/gpu/drm/i915/i915_drv.h:2704:
+extern void i915_reset(struct drm_i915_private *i915,

-:90: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files
#90: FILE: drivers/gpu/drm/i915/i915_drv.h:2707:
+extern int i915_reset_engine(struct intel_engine_cs *engine,

-:244: WARNING:MEMORY_BARRIER: memory barrier without comment
#244: FILE: drivers/gpu/drm/i915/selftests/intel_hangcheck.c:891:
+   smp_mb__before_atomic();

total: 0 errors, 2 warnings, 2 checks, 204 lines checked

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Re: [Intel-gfx] [PATCH] drm/i915/psr: Chase psr.enabled only under the psr.lock

[Rodrigo Vivi]

On Fri, Apr 06, 2018 at 11:12:27AM -0700, Souza, Jose wrote:
> On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote:
> > Inside the psr work function, we want to wait for PSR to idle first
> > and
> > wish to do so without blocking the normal modeset path, so we do so
> > without holding the PSR lock. However, we first have to find which
> > pipe
> > PSR was enabled on, which requires chasing into the PSR struct and
> > requires locking to prevent intel_psr_disable() from concurrently
> > setting our pointer to NULL.
> > 
> > Fixes: 995d30477496 ("drm/i915: VLV/CHV PSR Software timer mode")
> > Signed-off-by: Chris Wilson 
> > Cc: Durgadoss R 
> > Cc: Rodrigo Vivi 
> > Cc:  # v4.0+
> 
> Feel free to add:
> Reviewed-by: Jose Roberto de Souza 
> 
> > ---
> >  drivers/gpu/drm/i915/intel_psr.c | 82 +-
> > --
> >  1 file changed, 44 insertions(+), 38 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 2d53f7398a6d..69a5b276f4d8 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -775,53 +775,59 @@ void intel_psr_disable(struct intel_dp
> > *intel_dp,
> > cancel_delayed_work_sync(_priv->psr.work);
> >  }
> >  
> > -static void intel_psr_work(struct work_struct *work)
> > +static bool psr_wait_for_idle(struct drm_i915_private *dev_priv)
> >  {
> > -   struct drm_i915_private *dev_priv =
> > -   container_of(work, typeof(*dev_priv),
> > psr.work.work);
> > -   struct intel_dp *intel_dp = dev_priv->psr.enabled;
> > -   struct drm_crtc *crtc = dp_to_dig_port(intel_dp)-
> > >base.base.crtc;
> > -   enum pipe pipe = to_intel_crtc(crtc)->pipe;
> > +   struct intel_dp *intel_dp;
> 
> nitpick: Why not already set it?
> struct intel_dp *intel_dp = dev_priv->psr.enabled;
> 
> 
> > +   i915_reg_t reg;
> > +   u32 mask;
> > +   int err;
> > +
> > +   intel_dp = dev_priv->psr.enabled;
> > +   if (!intel_dp)
> > +   return false;
> >  
> > -   /* We have to make sure PSR is ready for re-enable
> > -* otherwise it keeps disabled until next full
> > enable/disable cycle.
> > -* PSR might take some time to get fully disabled
> > -* and be ready for re-enable.
> > -*/
> > if (HAS_DDI(dev_priv)) {
> 
> 
> nitpick: While on that you could replace this for:
> 
> if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) {
> 
> > if (dev_priv->psr.psr2_enabled) {
> > -   if (intel_wait_for_register(dev_priv,
> > -   EDP_PSR2_STATUS,
> > -   EDP_PSR2_STATUS_
> > STATE_MASK,
> > -   0,
> > -   50)) {
> > -   DRM_ERROR("Timed out waiting for
> > PSR2 Idle for re-enable\n");
> > -   return;
> > -   }
> > +   reg = EDP_PSR2_STATUS;
> > +   mask = EDP_PSR2_STATUS_STATE_MASK;
> > } else {
> > -   if (intel_wait_for_register(dev_priv,
> > -   EDP_PSR_STATUS,
> > -   EDP_PSR_STATUS_S
> > TATE_MASK,
> > -   0,
> > -   50)) {
> > -   DRM_ERROR("Timed out waiting for PSR
> > Idle for re-enable\n");
> > -   return;
> > -   }
> > +   reg = EDP_PSR_STATUS;
> > +   mask = EDP_PSR_STATUS_STATE_MASK;
> > }
> > } else {
> > -   if (intel_wait_for_register(dev_priv,
> > -   VLV_PSRSTAT(pipe),
> > -   VLV_EDP_PSR_IN_TRANS,
> > -   0,
> > -   1)) {
> > -   DRM_ERROR("Timed out waiting for PSR Idle
> > for re-enable\n");
> > -   return;
> > -   }
> > +   struct drm_crtc *crtc =
> > +   dp_to_dig_port(intel_dp)->base.base.crtc;

I'm afraid that the issue is this pointer here. So this will only mask
the issue.

Should we maybe stash the pipe? :/

> > +   enum pipe pipe = to_intel_crtc(crtc)->pipe;
> > +
> > +   reg = VLV_PSRSTAT(pipe);
> > +   mask = VLV_EDP_PSR_IN_TRANS;
> > }
> > +
> > +   mutex_unlock(_priv->psr.lock);
> > +
> > +   err = intel_wait_for_register(dev_priv, reg, mask, 0, 50);
> > +   if (err)
> > +   DRM_ERROR("Timed out waiting for PSR Idle for re-
> > enable\n");
> > +
> > +   /* After the unlocked wait, verify that PSR is still wanted!
> > */
> > mutex_lock(_priv->psr.lock);
> > 

Re: [Intel-gfx] [PATCH] drm/i915: Treat i915_reset_engine() as guilty until proven innocent

[Chris Wilson]

Quoting Michel Thierry (2018-04-06 22:44:34)
> On 4/6/2018 2:30 PM, Chris Wilson wrote:
> > Quoting Michel Thierry (2018-04-06 22:23:21)
> >> And I thought we believed in presumption of innocence...
> >>
> >> On 4/6/2018 2:00 PM, Chris Wilson wrote:
> >>> If we are resetting just one engine, we know it has stalled. So we can
> >>> pass the stalled parameter directly to i915_gem_reset_engine(), which
> >>> alleviates the necessity to poke at the generic engine->hangcheck.stalled
> >>> magic variable, leaving that under control of hangcheck as its name
> >>> implies. Other than simplifying by removing the indirect parameter along
> >>> this path, this allows us to introduce new reset mechanisms that run
> >>> independently of hangcheck.
>  Signed-off-by: Chris Wilson 
> >>> Cc: Michel Thierry 
> >>> Cc: Jeff McGee 
> >>> Cc: Mika Kuoppala 
> >>> ---
> >>>drivers/gpu/drm/i915/i915_drv.c   |  2 +-
> >>>drivers/gpu/drm/i915/i915_drv.h   |  3 +-
> >>>drivers/gpu/drm/i915/i915_gem.c   | 36 +--
> >>>.../gpu/drm/i915/selftests/intel_hangcheck.c  |  9 -
> >>>4 files changed, 20 insertions(+), 30 deletions(-)
> >>>
> >> ...
> >>> @@ -774,7 +766,6 @@ static int __igt_reset_engines(struct 
> >>> drm_i915_private *i915,
> >>>break;
> >>>}
> >>>
> >>> - engine->hangcheck.stalled = false;
> >>>count++;
> >>>
> >>>if (rq) {
> >>>
> >>
> >> Are the ones in igt_handle_error() still needed?
> >> hangcheck.stalled = true;
> >> hangcheck.seqno = intel_engine_get_seqno(engine);
> >>
> >> Because igt_handle_error is sending a real request.
> > 
> >> (I think the only ones remaining in the selftest should be in
> >> fake_hangcheck).
> > 
> > Right, fake_hangcheck definitely still needs it to behave like
> > hangcheck.
> > 
> > i915_handle_error() is still "odd". At the moment, yes we still need to
> > be poking where we shouldn't. If i915_handle_error() uses the
> > engine_mask to do per-engine resets, no, we don't need the magic
> > hangcheck.stalled. But, if it falls back to the full device level, we
> > loose the guilty reset.  So we do get a difference in behaviour, that
> > really hasn't been noticed before as the only real caller is from
> > hangcheck. (i915_wedged, I dare anyone to say what they expect ;)
> > 
> 
> Not the first time I forget about the full reset path.
> Thanks for explaining it.
> 
> > I think the answer will be to pass engine_mask to i915_reset. But I
> > haven't fleshed that out yet. I think it means we do away with
> > hangcheck.seqno as well, so bonus?

Wasn't quite as hairy as I feared... At least the selftests were easy
enough to convert over!
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[Intel-gfx] [PATCH 1/2] drm/i915: Treat i915_reset_engine() as guilty until proven innocent

[Chris Wilson]

If we are resetting just one engine, we know it has stalled. So we can
pass the stalled parameter directly to i915_gem_reset_engine(), which
alleviates the necessity to poke at the generic engine->hangcheck.stalled
magic variable, leaving that under control of hangcheck as its name
implies. Other than simplifying by removing the indirect parameter along
this path, this allows us to introduce new reset mechanisms that run
independently of hangcheck.

Signed-off-by: Chris Wilson 
Cc: Michel Thierry 
Cc: Jeff McGee 
Cc: Mika Kuoppala 
Reviewed-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_drv.c   |  2 +-
 drivers/gpu/drm/i915/i915_drv.h   |  3 +-
 drivers/gpu/drm/i915/i915_gem.c   | 36 +--
 .../gpu/drm/i915/selftests/intel_hangcheck.c  |  9 -
 4 files changed, 20 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 684060ed8db6..7ce229c6f424 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2050,7 +2050,7 @@ int i915_reset_engine(struct intel_engine_cs *engine, 
const char *msg)
 * active request and can drop it, adjust head to skip the offending
 * request to resume executing remaining requests in the queue.
 */
-   i915_gem_reset_engine(engine, active_request);
+   i915_gem_reset_engine(engine, active_request, true);
 
/*
 * The engine and its registers (and workarounds in case of render)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5373b171bb96..6b3f2f651def 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3132,7 +3132,8 @@ void i915_gem_reset_finish(struct drm_i915_private 
*dev_priv);
 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
 void i915_gem_reset_engine(struct intel_engine_cs *engine,
-  struct i915_request *request);
+  struct i915_request *request,
+  bool stalled);
 
 void i915_gem_init_mmio(struct drm_i915_private *i915);
 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a69dc19a0bdb..306d7a805eb7 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2990,20 +2990,6 @@ i915_gem_find_active_request(struct intel_engine_cs 
*engine)
return active;
 }
 
-static bool engine_stalled(struct intel_engine_cs *engine)
-{
-   if (!engine->hangcheck.stalled)
-   return false;
-
-   /* Check for possible seqno movement after hang declaration */
-   if (engine->hangcheck.seqno != intel_engine_get_seqno(engine)) {
-   DRM_DEBUG_DRIVER("%s pardoned\n", engine->name);
-   return false;
-   }
-
-   return true;
-}
-
 /*
  * Ensure irq handler finishes, and not run again.
  * Also return the active request so that we only search for it once.
@@ -3142,7 +3128,8 @@ static void engine_skip_context(struct i915_request 
*request)
 /* Returns the request if it was guilty of the hang */
 static struct i915_request *
 i915_gem_reset_request(struct intel_engine_cs *engine,
-  struct i915_request *request)
+  struct i915_request *request,
+  bool stalled)
 {
/* The guilty request will get skipped on a hung engine.
 *
@@ -3165,7 +3152,15 @@ i915_gem_reset_request(struct intel_engine_cs *engine,
 * subsequent hangs.
 */
 
-   if (engine_stalled(engine)) {
+   if (i915_request_completed(request)) {
+   GEM_TRACE("%s pardoned global=%d (fence %llx:%d), current %d\n",
+ engine->name, request->global_seqno,
+ request->fence.context, request->fence.seqno,
+ intel_engine_get_seqno(engine));
+   stalled = false;
+   }
+
+   if (stalled) {
i915_gem_context_mark_guilty(request->ctx);
skip_request(request);
 
@@ -3196,7 +3191,8 @@ i915_gem_reset_request(struct intel_engine_cs *engine,
 }
 
 void i915_gem_reset_engine(struct intel_engine_cs *engine,
-  struct i915_request *request)
+  struct i915_request *request,
+  bool stalled)
 {
/*
 * Make sure this write is visible before we re-enable the interrupt
@@ -3206,7 +3202,7 @@ void i915_gem_reset_engine(struct intel_engine_cs *engine,
smp_store_mb(engine->irq_posted, 0);
 
if (request)
-   request = i915_gem_reset_request(engine, request);
+   request = 

[Intel-gfx] [PATCH 2/2] drm/i915: Pass the set of guilty engines to i915_reset()

[Chris Wilson]

Currently, we rely on inspecting the hangcheck state from within the
i915_reset() routines to determine which engines were guilty of the
hang. This is problematic for cases where we want to run
i915_handle_error() and call i915_reset() independently of hangcheck.
Instead of relying on the indirect parameter passing, turn it into an
explicit parameter providing the set of stalled engines which then are
treated as guilty until proven innocent.

While we are removing the implicit stalled parameter, also make the
reason into an explicit paramter to i915_reset(). We still need a
back-channel for i915_handle_error() to hand over the task to the locked
waiter, but let's keep that its own channel rather than incriminate
another.

This leaves stalled/seqno as being private to hangcheck, with no more
nefarious snooping by reset, be it whole-device or per-engine. \o/

The only real issue now is that this makes it crystal clear that we
don't actually do any testing of hangcheck per se in
drv_selftest/live_hangcheck, merely of resets!

Signed-off-by: Chris Wilson 
Cc: Michel Thierry 
Cc: Jeff McGee 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_drv.c   | 13 ++
 drivers/gpu/drm/i915/i915_drv.h   | 10 +---
 drivers/gpu/drm/i915/i915_gem.c   |  5 ++--
 drivers/gpu/drm/i915/i915_gpu_error.h |  3 +++
 drivers/gpu/drm/i915/i915_irq.c   | 12 ++---
 drivers/gpu/drm/i915/i915_request.c   |  6 +++--
 .../gpu/drm/i915/selftests/intel_hangcheck.c  | 25 ---
 7 files changed, 44 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7ce229c6f424..f770be18b2d7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1866,6 +1866,8 @@ static int i915_resume_switcheroo(struct drm_device *dev)
 /**
  * i915_reset - reset chip after a hang
  * @i915: #drm_i915_private to reset
+ * @stalled_mask: mask of the stalled engines with the guilty requests
+ * @reason: user error message for why we are resetting
  *
  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
  * on failure.
@@ -1880,7 +1882,9 @@ static int i915_resume_switcheroo(struct drm_device *dev)
  *   - re-init interrupt state
  *   - re-init display
  */
-void i915_reset(struct drm_i915_private *i915)
+void i915_reset(struct drm_i915_private *i915,
+   unsigned int stalled_mask,
+   const char *reason)
 {
struct i915_gpu_error *error = >gpu_error;
int ret;
@@ -1899,9 +1903,8 @@ void i915_reset(struct drm_i915_private *i915)
if (!i915_gem_unset_wedged(i915))
goto wakeup;
 
-   if (error->reason)
-   dev_notice(i915->drm.dev,
-  "Resetting chip for %s\n", error->reason);
+   if (reason)
+   dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason);
error->reset_count++;
 
disable_irq(i915->drm.irq);
@@ -1944,7 +1947,7 @@ void i915_reset(struct drm_i915_private *i915)
goto error;
}
 
-   i915_gem_reset(i915);
+   i915_gem_reset(i915, stalled_mask);
intel_overlay_reset(i915);
 
/*
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6b3f2f651def..9bca104c409e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2701,8 +2701,11 @@ extern void i915_driver_unload(struct drm_device *dev);
 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
 
-extern void i915_reset(struct drm_i915_private *i915);
-extern int i915_reset_engine(struct intel_engine_cs *engine, const char *msg);
+extern void i915_reset(struct drm_i915_private *i915,
+  unsigned int stalled_mask,
+  const char *reason);
+extern int i915_reset_engine(struct intel_engine_cs *engine,
+const char *reason);
 
 extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
 extern int intel_reset_guc(struct drm_i915_private *dev_priv);
@@ -3126,7 +3129,8 @@ static inline u32 i915_reset_engine_count(struct 
i915_gpu_error *error,
 struct i915_request *
 i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
-void i915_gem_reset(struct drm_i915_private *dev_priv);
+void i915_gem_reset(struct drm_i915_private *dev_priv,
+   unsigned int stalled_mask);
 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine);
 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/psr: vbt change for psr

[Patchwork]

== Series Details ==

Series: drm/i915/psr: vbt change for psr
URL   : https://patchwork.freedesktop.org/series/41289/
State : failure

== Summary ==

 Possible new issues:

Test drm_read:
Subgroup invalid-buffer:
pass   -> FAIL   (shard-snb)
Test gem_mmap_gtt:
Subgroup forked-medium-copy-odd:
dmesg-warn -> PASS   (shard-hsw)
Test kms_busy:
Subgroup extended-modeset-hang-oldfb-with-reset-render-a:
pass   -> FAIL   (shard-snb)
Test kms_cursor_crc:
Subgroup cursor-256x85-random:
pass   -> DMESG-WARN (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup fbc-2p-pri-indfb-multidraw:
dmesg-fail -> PASS   (shard-hsw)
Subgroup fbc-2p-primscrn-pri-indfb-draw-pwrite:
skip   -> FAIL   (shard-snb)
Subgroup fbcpsr-1p-primscrn-cur-indfb-move:
skip   -> FAIL   (shard-snb)
Subgroup fbcpsr-2p-scndscrn-indfb-msflip-blt:
skip   -> FAIL   (shard-snb)
Subgroup psr-1p-primscrn-shrfb-msflip-blt:
skip   -> FAIL   (shard-snb)
Subgroup psr-2p-primscrn-spr-indfb-fullscreen:
skip   -> FAIL   (shard-snb)
Subgroup psr-2p-rte:
skip   -> FAIL   (shard-snb)
Test kms_vblank:
Subgroup pipe-a-query-forked-busy-hang:
pass   -> FAIL   (shard-snb)

 Known issues:

Test kms_cursor_legacy:
Subgroup 2x-long-flip-vs-cursor-legacy:
fail   -> PASS   (shard-hsw) fdo#104873
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
fail   -> PASS   (shard-hsw) fdo#102887
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu:
pass   -> FAIL   (shard-snb) fdo#103167 +1
Test kms_rotation_crc:
Subgroup primary-rotation-180:
pass   -> FAIL   (shard-snb) fdo#103925
Test kms_sysfs_edid_timing:
warn   -> PASS   (shard-apl) fdo#100047

fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047

shard-apltotal:2680 pass:1836 dwarn:1   dfail:0   fail:7   skip:836 
time:12652s
shard-hswtotal:2680 pass:1785 dwarn:2   dfail:0   fail:1   skip:891 
time:11288s
shard-snbtotal:2680 pass:1372 dwarn:1   dfail:0   fail:14  skip:1293 
time:6821s
Blacklisted hosts:
shard-kbltotal:2680 pass:1963 dwarn:1   dfail:0   fail:6   skip:710 
time:9181s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8626/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915: Treat i915_reset_engine() as guilty until proven innocent

[Michel Thierry]

On 4/6/2018 2:30 PM, Chris Wilson wrote:

Quoting Michel Thierry (2018-04-06 22:23:21)

And I thought we believed in presumption of innocence...

On 4/6/2018 2:00 PM, Chris Wilson wrote:

If we are resetting just one engine, we know it has stalled. So we can
pass the stalled parameter directly to i915_gem_reset_engine(), which
alleviates the necessity to poke at the generic engine->hangcheck.stalled
magic variable, leaving that under control of hangcheck as its name
implies. Other than simplifying by removing the indirect parameter along
this path, this allows us to introduce new reset mechanisms that run
independently of hangcheck.

Signed-off-by: Chris Wilson 

Cc: Michel Thierry 
Cc: Jeff McGee 
Cc: Mika Kuoppala 
---
   drivers/gpu/drm/i915/i915_drv.c   |  2 +-
   drivers/gpu/drm/i915/i915_drv.h   |  3 +-
   drivers/gpu/drm/i915/i915_gem.c   | 36 +--
   .../gpu/drm/i915/selftests/intel_hangcheck.c  |  9 -
   4 files changed, 20 insertions(+), 30 deletions(-)


...

@@ -774,7 +766,6 @@ static int __igt_reset_engines(struct drm_i915_private 
*i915,
   break;
   }
   
- engine->hangcheck.stalled = false;

   count++;
   
   if (rq) {




Are the ones in igt_handle_error() still needed?
hangcheck.stalled = true;
hangcheck.seqno = intel_engine_get_seqno(engine);

Because igt_handle_error is sending a real request.



(I think the only ones remaining in the selftest should be in
fake_hangcheck).


Right, fake_hangcheck definitely still needs it to behave like
hangcheck.

i915_handle_error() is still "odd". At the moment, yes we still need to
be poking where we shouldn't. If i915_handle_error() uses the
engine_mask to do per-engine resets, no, we don't need the magic
hangcheck.stalled. But, if it falls back to the full device level, we
loose the guilty reset.  So we do get a difference in behaviour, that
really hasn't been noticed before as the only real caller is from
hangcheck. (i915_wedged, I dare anyone to say what they expect ;)



Not the first time I forget about the full reset path.
Thanks for explaining it.


I think the answer will be to pass engine_mask to i915_reset. But I
haven't fleshed that out yet. I think it means we do away with
hangcheck.seqno as well, so bonus?



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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Treat i915_reset_engine() as guilty until proven innocent

[Patchwork]

== Series Details ==

Series: drm/i915: Treat i915_reset_engine() as guilty until proven innocent
URL   : https://patchwork.freedesktop.org/series/41305/
State : success

== Summary ==

Series 41305v1 drm/i915: Treat i915_reset_engine() as guilty until proven 
innocent
https://patchwork.freedesktop.org/api/1.0/series/41305/revisions/1/mbox/

 Known issues:

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (fi-skl-6700k2) fdo#103191
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713
Subgroup suspend-read-crc-pipe-c:
pass   -> FAIL   (fi-skl-guc) fdo#104108

fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:430s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:439s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:386s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:535s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:300s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:513s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:516s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:520s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:516s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:409s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:558s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:514s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:593s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:424s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:313s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:543s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:488s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:402s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:422s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:461s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:435s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:475s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:461s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:509s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:638s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:443s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:558s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:502s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:506s
fi-skl-guc   total:285  pass:256  dwarn:0   dfail:0   fail:1   skip:28  
time:431s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:443s
fi-snb-2520m total:242  pass:208  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:404s

e023242a3ebab3e7a4e5d7647d7b08c0d2be5d4c drm-tip: 2018y-04m-06d-19h-07m-27s UTC 
integration manifest
e970b31ab041 drm/i915: Treat i915_reset_engine() as guilty until proven innocent

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8630/issues.html
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Re: [Intel-gfx] [PATCH] drm/i915: Treat i915_reset_engine() as guilty until proven innocent

[Chris Wilson]

Quoting Michel Thierry (2018-04-06 22:23:21)
> And I thought we believed in presumption of innocence...
> 
> On 4/6/2018 2:00 PM, Chris Wilson wrote:
> > If we are resetting just one engine, we know it has stalled. So we can
> > pass the stalled parameter directly to i915_gem_reset_engine(), which
> > alleviates the necessity to poke at the generic engine->hangcheck.stalled
> > magic variable, leaving that under control of hangcheck as its name
> > implies. Other than simplifying by removing the indirect parameter along
> > this path, this allows us to introduce new reset mechanisms that run
> > independently of hangcheck.
> > > Signed-off-by: Chris Wilson 
> > Cc: Michel Thierry 
> > Cc: Jeff McGee 
> > Cc: Mika Kuoppala 
> > ---
> >   drivers/gpu/drm/i915/i915_drv.c   |  2 +-
> >   drivers/gpu/drm/i915/i915_drv.h   |  3 +-
> >   drivers/gpu/drm/i915/i915_gem.c   | 36 +--
> >   .../gpu/drm/i915/selftests/intel_hangcheck.c  |  9 -
> >   4 files changed, 20 insertions(+), 30 deletions(-)
> > 
> ...
> > @@ -774,7 +766,6 @@ static int __igt_reset_engines(struct drm_i915_private 
> > *i915,
> >   break;
> >   }
> >   
> > - engine->hangcheck.stalled = false;
> >   count++;
> >   
> >   if (rq) {
> > 
> 
> Are the ones in igt_handle_error() still needed?
>hangcheck.stalled = true;
>hangcheck.seqno = intel_engine_get_seqno(engine);
> 
> Because igt_handle_error is sending a real request.

> (I think the only ones remaining in the selftest should be in 
> fake_hangcheck).

Right, fake_hangcheck definitely still needs it to behave like
hangcheck.

i915_handle_error() is still "odd". At the moment, yes we still need to
be poking where we shouldn't. If i915_handle_error() uses the
engine_mask to do per-engine resets, no, we don't need the magic
hangcheck.stalled. But, if it falls back to the full device level, we
loose the guilty reset.  So we do get a difference in behaviour, that
really hasn't been noticed before as the only real caller is from
hangcheck. (i915_wedged, I dare anyone to say what they expect ;)

I think the answer will be to pass engine_mask to i915_reset. But I
haven't fleshed that out yet. I think it means we do away with
hangcheck.seqno as well, so bonus?
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Treat i915_reset_engine() as guilty until proven innocent

[Michel Thierry]

And I thought we believed in presumption of innocence...

On 4/6/2018 2:00 PM, Chris Wilson wrote:

If we are resetting just one engine, we know it has stalled. So we can
pass the stalled parameter directly to i915_gem_reset_engine(), which
alleviates the necessity to poke at the generic engine->hangcheck.stalled
magic variable, leaving that under control of hangcheck as its name
implies. Other than simplifying by removing the indirect parameter along
this path, this allows us to introduce new reset mechanisms that run
independently of hangcheck.
> Signed-off-by: Chris Wilson 
Cc: Michel Thierry 
Cc: Jeff McGee 
Cc: Mika Kuoppala 
---
  drivers/gpu/drm/i915/i915_drv.c   |  2 +-
  drivers/gpu/drm/i915/i915_drv.h   |  3 +-
  drivers/gpu/drm/i915/i915_gem.c   | 36 +--
  .../gpu/drm/i915/selftests/intel_hangcheck.c  |  9 -
  4 files changed, 20 insertions(+), 30 deletions(-)


...

@@ -774,7 +766,6 @@ static int __igt_reset_engines(struct drm_i915_private 
*i915,
break;
}
  
-			engine->hangcheck.stalled = false;

count++;
  
  			if (rq) {




Are the ones in igt_handle_error() still needed?
  hangcheck.stalled = true;
  hangcheck.seqno = intel_engine_get_seqno(engine);

Because igt_handle_error is sending a real request.
(I think the only ones remaining in the selftest should be in 
fake_hangcheck).


Reviewed-by: Michel Thierry 
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[Intel-gfx] ✗ Fi.CI.IGT: failure for Aspect ratio support in DRM layer (rev2)

[Patchwork]

== Series Details ==

Series: Aspect ratio support in DRM layer (rev2)
URL   : https://patchwork.freedesktop.org/series/39960/
State : failure

== Summary ==

 Possible new issues:

Test gem_mmap_gtt:
Subgroup forked-medium-copy-odd:
dmesg-warn -> PASS   (shard-hsw)
Test kms_3d:
pass   -> FAIL   (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-2p-pri-indfb-multidraw:
dmesg-fail -> PASS   (shard-hsw)
Test pm_rc6_residency:
Subgroup rc6-accuracy:
skip   -> PASS   (shard-snb)

 Known issues:

Test kms_cursor_legacy:
Subgroup 2x-long-flip-vs-cursor-legacy:
fail   -> PASS   (shard-hsw) fdo#104873
Test kms_flip:
Subgroup dpms-vs-vblank-race:
pass   -> FAIL   (shard-hsw) fdo#103060
Subgroup plain-flip-fb-recreate:
pass   -> FAIL   (shard-hsw) fdo#100368 +2
Test kms_rotation_crc:
Subgroup primary-rotation-180:
pass   -> FAIL   (shard-snb) fdo#103925
Test testdisplay:
pass   -> DMESG-WARN (shard-apl) fdo#104727

fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
fdo#104727 https://bugs.freedesktop.org/show_bug.cgi?id=104727

shard-apltotal:2680 pass:1834 dwarn:2   dfail:0   fail:7   skip:836 
time:12650s
shard-hswtotal:2680 pass:1781 dwarn:1   dfail:0   fail:6   skip:891 
time:11253s
shard-snbtotal:2680 pass:1377 dwarn:1   dfail:0   fail:4   skip:1298 
time:6834s
Blacklisted hosts:
shard-kbltotal:2680 pass:1961 dwarn:1   dfail:0   fail:8   skip:710 
time:9140s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8625/shards.html
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[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915/fbc/cnl: Add GLK and CNL+ hardware tracking size

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/fbc/cnl: Add GLK and CNL+ hardware 
tracking size
URL   : https://patchwork.freedesktop.org/series/41303/
State : warning

== Summary ==

Series 41303v1 series starting with [1/2] drm/i915/fbc/cnl: Add GLK and CNL+ 
hardware tracking size
https://patchwork.freedesktop.org/api/1.0/series/41303/revisions/1/mbox/

 Possible new issues:

Test gem_exec_gttfill:
Subgroup basic:
pass   -> SKIP   (fi-pnv-d510)

 Known issues:

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (fi-skl-6700k2) fdo#103191

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:430s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:444s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:381s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:549s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:297s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:512s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:512s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:521s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:510s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:412s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:562s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:514s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:588s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:419s
fi-gdg-551   total:285  pass:177  dwarn:0   dfail:0   fail:0   skip:108 
time:317s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:541s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:486s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:405s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:424s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:472s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:434s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:472s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:459s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:509s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:633s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:444s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:533s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:502s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:510s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:430s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:447s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:583s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:399s

e023242a3ebab3e7a4e5d7647d7b08c0d2be5d4c drm-tip: 2018y-04m-06d-19h-07m-27s UTC 
integration manifest
38a8e6805626 drm/i915/fbc: Resize CFB in non-full modeset paths
51c1ab0d8ad0 drm/i915/fbc/cnl: Add GLK and CNL+ hardware tracking size

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8629/issues.html
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/fbc: Resize CFB in non-full modeset paths

[Chris Wilson]

Quoting José Roberto de Souza (2018-04-06 21:53:49)
> A simple page flip can cause the CFB required size to increase and
> if it is bigger than the currently allocated CFB it needs to be
> resized to activate FBC again.

I would have expected the answer to be to plug into atomic. During the
prepare phase, you evaluate the planes for compatibility with FBC, and
record what actions you plan to take in the commit (including allocating
the next slab of stolen if required). Everything now goes through the
same atomic prepare/commit, so it should be possible to eliminate all
guess work.

Hopefully Maarten can either explain it better or why it shouldn't be
done that at all. ;)
-Chris
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[Intel-gfx] [PATCH] drm/i915: Treat i915_reset_engine() as guilty until proven innocent

[Chris Wilson]

If we are resetting just one engine, we know it has stalled. So we can
pass the stalled parameter directly to i915_gem_reset_engine(), which
alleviates the necessity to poke at the generic engine->hangcheck.stalled
magic variable, leaving that under control of hangcheck as its name
implies. Other than simplifying by removing the indirect parameter along
this path, this allows us to introduce new reset mechanisms that run
independently of hangcheck.

Signed-off-by: Chris Wilson 
Cc: Michel Thierry 
Cc: Jeff McGee 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_drv.c   |  2 +-
 drivers/gpu/drm/i915/i915_drv.h   |  3 +-
 drivers/gpu/drm/i915/i915_gem.c   | 36 +--
 .../gpu/drm/i915/selftests/intel_hangcheck.c  |  9 -
 4 files changed, 20 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 684060ed8db6..7ce229c6f424 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2050,7 +2050,7 @@ int i915_reset_engine(struct intel_engine_cs *engine, 
const char *msg)
 * active request and can drop it, adjust head to skip the offending
 * request to resume executing remaining requests in the queue.
 */
-   i915_gem_reset_engine(engine, active_request);
+   i915_gem_reset_engine(engine, active_request, true);
 
/*
 * The engine and its registers (and workarounds in case of render)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5373b171bb96..6b3f2f651def 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3132,7 +3132,8 @@ void i915_gem_reset_finish(struct drm_i915_private 
*dev_priv);
 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
 void i915_gem_reset_engine(struct intel_engine_cs *engine,
-  struct i915_request *request);
+  struct i915_request *request,
+  bool stalled);
 
 void i915_gem_init_mmio(struct drm_i915_private *i915);
 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a69dc19a0bdb..306d7a805eb7 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2990,20 +2990,6 @@ i915_gem_find_active_request(struct intel_engine_cs 
*engine)
return active;
 }
 
-static bool engine_stalled(struct intel_engine_cs *engine)
-{
-   if (!engine->hangcheck.stalled)
-   return false;
-
-   /* Check for possible seqno movement after hang declaration */
-   if (engine->hangcheck.seqno != intel_engine_get_seqno(engine)) {
-   DRM_DEBUG_DRIVER("%s pardoned\n", engine->name);
-   return false;
-   }
-
-   return true;
-}
-
 /*
  * Ensure irq handler finishes, and not run again.
  * Also return the active request so that we only search for it once.
@@ -3142,7 +3128,8 @@ static void engine_skip_context(struct i915_request 
*request)
 /* Returns the request if it was guilty of the hang */
 static struct i915_request *
 i915_gem_reset_request(struct intel_engine_cs *engine,
-  struct i915_request *request)
+  struct i915_request *request,
+  bool stalled)
 {
/* The guilty request will get skipped on a hung engine.
 *
@@ -3165,7 +3152,15 @@ i915_gem_reset_request(struct intel_engine_cs *engine,
 * subsequent hangs.
 */
 
-   if (engine_stalled(engine)) {
+   if (i915_request_completed(request)) {
+   GEM_TRACE("%s pardoned global=%d (fence %llx:%d), current %d\n",
+ engine->name, request->global_seqno,
+ request->fence.context, request->fence.seqno,
+ intel_engine_get_seqno(engine));
+   stalled = false;
+   }
+
+   if (stalled) {
i915_gem_context_mark_guilty(request->ctx);
skip_request(request);
 
@@ -3196,7 +3191,8 @@ i915_gem_reset_request(struct intel_engine_cs *engine,
 }
 
 void i915_gem_reset_engine(struct intel_engine_cs *engine,
-  struct i915_request *request)
+  struct i915_request *request,
+  bool stalled)
 {
/*
 * Make sure this write is visible before we re-enable the interrupt
@@ -3206,7 +3202,7 @@ void i915_gem_reset_engine(struct intel_engine_cs *engine,
smp_store_mb(engine->irq_posted, 0);
 
if (request)
-   request = i915_gem_reset_request(engine, request);
+   request = i915_gem_reset_request(engine, request, stalled);
 
if (request) {
  

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/fbc/cnl: Add GLK and CNL+ hardware tracking size

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/fbc/cnl: Add GLK and CNL+ hardware 
tracking size
URL   : https://patchwork.freedesktop.org/series/41303/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
51c1ab0d8ad0 drm/i915/fbc/cnl: Add GLK and CNL+ hardware tracking size
38a8e6805626 drm/i915/fbc: Resize CFB in non-full modeset paths
-:110: WARNING:LINE_CONTINUATIONS: Avoid line continuations in quoted strings
#110: FILE: drivers/gpu/drm/i915/intel_fbc.c:887:
+   DRM_DEBUG_KMS("CFB requirements have changed, activation  \

total: 0 errors, 1 warnings, 0 checks, 85 lines checked

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[Intel-gfx] [PATCH 2/2] drm/i915/fbc: Resize CFB in non-full modeset paths

[José Roberto de Souza]

A simple page flip can cause the CFB required size to increase and
if it is bigger than the currently allocated CFB it needs to be
resized to activate FBC again.

Until now this case was not being handled but CI is starting to
get some of this errors.

So here it will free the old CFB and a try to allocate the required
CFB in the schedule activation work, it will happen after one vblank
so is guarantee that FBC was completed disabled and is not using CFB.

Also in case that there is no enough stolen memory to allocate the
new CFB it will try 3 times per full modeset as the CFB requirement
could be reduced in the next non-full modeset.

Cc: Paulo Zanoni 
Signed-off-by: José Roberto de Souza 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105683
---
 drivers/gpu/drm/i915/i915_drv.h  |  3 +++
 drivers/gpu/drm/i915/intel_fbc.c | 46 +---
 2 files changed, 33 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5373b171bb96..4ce19b45f67d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -566,6 +566,9 @@ struct intel_fbc {
} work;
 
const char *no_fbc_reason;
+
+   bool cfb_try_resize;
+   u8 cfb_resize_tries_left;
 };
 
 /*
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 573b034a02fd..7d77936db3ec 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -41,6 +41,9 @@
 #include "intel_drv.h"
 #include "i915_drv.h"
 
+static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
+static int intel_fbc_alloc_cfb(struct intel_crtc *crtc);
+
 static inline bool fbc_supported(struct drm_i915_private *dev_priv)
 {
return HAS_FBC(dev_priv);
@@ -446,6 +449,15 @@ static void intel_fbc_work_fn(struct work_struct *__work)
goto retry;
}
 
+   if (fbc->cfb_try_resize && fbc->cfb_resize_tries_left) {
+   __intel_fbc_cleanup_cfb(dev_priv);
+   if (intel_fbc_alloc_cfb(crtc)) {
+   fbc->no_fbc_reason = "not enough stolen memory";
+   fbc->cfb_resize_tries_left--;
+   goto out;
+   }
+   }
+
intel_fbc_hw_activate(dev_priv);
 
work->scheduled = false;
@@ -850,22 +862,6 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
return false;
}
 
-   /* It is possible for the required CFB size change without a
-* crtc->disable + crtc->enable since it is possible to change the
-* stride without triggering a full modeset. Since we try to
-* over-allocate the CFB, there's a chance we may keep FBC enabled even
-* if this happens, but if we exceed the current CFB size we'll have to
-* disable FBC. Notice that it would be possible to disable FBC, wait
-* for a frame, free the stolen node, then try to reenable FBC in case
-* we didn't get any invalidate/deactivate calls, but this would require
-* a lot of tracking just for a specific case. If we conclude it's an
-* important case, we can implement it later. */
-   if (intel_fbc_calculate_cfb_size(dev_priv, >state_cache) >
-   fbc->compressed_fb.size * fbc->threshold) {
-   fbc->no_fbc_reason = "CFB requirements changed";
-   return false;
-   }
-
/*
 * Work around a problem on GEN9+ HW, where enabling FBC on a plane
 * having a Y offset that isn't divisible by 4 causes FIFO underrun
@@ -877,6 +873,23 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
return false;
}
 
+   /* It is possible for the required CFB size change without a
+* crtc->disable + crtc->enable since it is possible to change the
+* stride without triggering a full modeset. Since we try to
+* over-allocate the CFB, there's a chance we may keep FBC enabled even
+* if this happens, but if we exceed the current CFB size we'll have to
+* resize CFB.
+*/
+   if (!drm_mm_node_allocated(>compressed_fb) ||
+   (intel_fbc_calculate_cfb_size(dev_priv, >state_cache) >
+fbc->compressed_fb.size * fbc->threshold)) {
+   fbc->cfb_try_resize = true;
+   DRM_DEBUG_KMS("CFB requirements have changed, activation  \
+ work will try to resize it");
+   } else {
+   fbc->cfb_try_resize = false;
+   }
+
return true;
 }
 
@@ -1208,6 +1221,7 @@ void intel_fbc_enable(struct intel_crtc *crtc,
 
fbc->enabled = true;
fbc->crtc = crtc;
+   fbc->cfb_resize_tries_left = 3;
 out:
mutex_unlock(>lock);
 }
-- 
2.17.0

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[Intel-gfx] [PATCH 1/2] drm/i915/fbc/cnl: Add GLK and CNL+ hardware tracking size

[José Roberto de Souza]

Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/intel_fbc.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 707d49c12638..573b034a02fd 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -714,7 +714,14 @@ static bool intel_fbc_hw_tracking_covers_screen(struct 
intel_crtc *crtc)
struct intel_fbc *fbc = _priv->fbc;
unsigned int effective_w, effective_h, max_w, max_h;
 
-   if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
+   if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+   max_w = 5120;
+   /* BSpec: 21664 WA: 1109 */
+   if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
+   max_h = 4092;
+   else
+   max_h = 4096;
+   } else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
max_w = 4096;
max_h = 4096;
} else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
-- 
2.17.0

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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Split out parking from the idle worker for reuse (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Split out parking from the idle worker for reuse (rev2)
URL   : https://patchwork.freedesktop.org/series/41278/
State : success

== Summary ==

 Possible new issues:

Test gem_mmap_gtt:
Subgroup forked-medium-copy-odd:
dmesg-warn -> PASS   (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup fbc-2p-pri-indfb-multidraw:
dmesg-fail -> PASS   (shard-hsw)
Test pm_rc6_residency:
Subgroup rc6-accuracy:
skip   -> PASS   (shard-snb)

 Known issues:

Test kms_cursor_legacy:
Subgroup 2x-long-flip-vs-cursor-legacy:
fail   -> PASS   (shard-hsw) fdo#104873
Test kms_flip:
Subgroup 2x-dpms-vs-vblank-race-interruptible:
pass   -> FAIL   (shard-hsw) fdo#103060
Subgroup 2x-flip-vs-absolute-wf_vblank:
pass   -> FAIL   (shard-hsw) fdo#100368
Subgroup 2x-flip-vs-expired-vblank:
fail   -> PASS   (shard-hsw) fdo#102887
Test kms_rotation_crc:
Subgroup primary-rotation-180:
pass   -> FAIL   (shard-snb) fdo#103925 +1
Test kms_sysfs_edid_timing:
warn   -> PASS   (shard-apl) fdo#100047
Test prime_vgem:
Subgroup basic-fence-flip:
pass   -> FAIL   (shard-apl) fdo#104008

fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

shard-apltotal:2680 pass:1834 dwarn:1   dfail:0   fail:9   skip:836 
time:12598s
shard-hswtotal:2680 pass:1784 dwarn:1   dfail:0   fail:3   skip:891 
time:11455s
shard-snbtotal:2680 pass:1378 dwarn:1   dfail:0   fail:3   skip:1298 
time:6876s
Blacklisted hosts:
shard-kbltotal:2680 pass:1962 dwarn:1   dfail:0   fail:8   skip:709 
time:9178s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8624/shards.html
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Re: [Intel-gfx] [PATCH 7/7] drm/i915: Engine queues query

[Chris Wilson]

Quoting Lionel Landwerlin (2018-04-05 14:05:52)
> On 05/04/18 13:39, Tvrtko Ursulin wrote:
> > +
> > + /** Number of requests with unresolved fences and dependencies. */
> > + __u32 queued;
> > +
> > + /** Number of ready requests waiting on a slot on GPU. */
> > + __u32 runnable;
> > +
> > + /** Number of requests executing on the GPU. */
> > + __u32 running;
> > +
> > + __u32 rsvd[5];
> 
> Joonas made me add a comment for fields that are supposed to be cleared, 
> probably applies here too.

__u32 mbz[5]; ?
-Chris
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Re: [Intel-gfx] [PATCH 6/7] drm/i915/pmu: Add running counter

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-04-05 13:39:22)
> From: Tvrtko Ursulin 
> 
> We add a PMU counter to expose the number of requests currently executing
> on the GPU.
> 
> This is useful to analyze the overall load of the system.
> 
> v2:
>  * Rebase.
>  * Drop floating point constant. (Chris Wilson)
> 
> v3:
>  * Change scale to 1024 for faster arithmetics. (Chris Wilson)
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: Chris Wilson 

Do we want these separate in the final push? Is there value in reverting
one but not the others? They seem a triumvirate.
-Chris
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Re: [Intel-gfx] [PATCH 5/7] drm/i915/pmu: Add runnable counter

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-04-05 13:39:21)
> From: Tvrtko Ursulin 
> 
> We add a PMU counter to expose the number of requests with resolved
> dependencies waiting for a slot on the GPU to run.
> 
> This is useful to analyze the overall load of the system.
> 
> v2: Don't limit to gen8+.
> 
> v3:
>  * Rebase for dynamic sysfs.
>  * Drop currently executing requests.
> 
> v4:
>  * Sync with internal renaming.
>  * Drop floating point constant. (Chris Wilson)
> 
> v5:
>  * Change scale to 1024 for faster arithmetics. (Chris Wilson)
> 
> Signed-off-by: Tvrtko Ursulin 

Cunningly disguised as the patch I thought I just read,

Reviewed-by: Chris Wilson 
-Chris
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Re: [Intel-gfx] [PATCH 4/7] drm/i915/pmu: Add queued counter

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-04-05 13:39:20)
> From: Tvrtko Ursulin 
> 
> We add a PMU counter to expose the number of requests which have been
> submitted from userspace but are not yet runnable due dependencies and
> unsignaled fences.
> 
> This is useful to analyze the overall load of the system.
> 
> v2:
>  * Rebase for name change and re-order.
>  * Drop floating point constant. (Chris Wilson)
> 
> v3:
>  * Change scale to 1024 for faster arithmetics. (Chris Wilson)
> 
> Signed-off-by: Tvrtko Ursulin 

I have nothing to complain about,
Reviewed-by: Chris Wilson 
-Chris
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Re: [Intel-gfx] [PATCH 3/7] drm/i915: Keep a count of requests submitted from userspace

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-04-05 13:39:19)
> From: Tvrtko Ursulin 
> 
> Keep a count of requests submitted from userspace and not yet runnable due
> unresolved dependencies.
> 
> v2: Rename and move under the container struct. (Chris Wilson)
> v3: Rebase.
> 
> Signed-off-by: Tvrtko Ursulin 
> ---
>  drivers/gpu/drm/i915/i915_request.c | 3 +++
>  drivers/gpu/drm/i915/intel_engine_cs.c  | 3 ++-
>  drivers/gpu/drm/i915/intel_ringbuffer.h | 8 
>  3 files changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_request.c 
> b/drivers/gpu/drm/i915/i915_request.c
> index 5c01291ad1cc..152321655fe6 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -640,6 +640,7 @@ submit_notify(struct i915_sw_fence *fence, enum 
> i915_sw_fence_notify state)
> rcu_read_lock();
> request->engine->submit_request(request);
> rcu_read_unlock();
> +   atomic_dec(>engine->request_stats.queued);

But we use atomic here? Might as well use atomic for
request_stats.runnable here as well?
-Chris
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Re: [Intel-gfx] [PATCH 2/7] drm/i915: Keep a count of requests waiting for a slot on GPU

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-04-05 13:39:18)
> From: Tvrtko Ursulin 
> 
> Keep a per-engine number of runnable (waiting for GPU time) requests.
> 
> v2:
>  * Move queued increment from insert_request to execlist_submit_request to
>avoid bumping when re-ordering for priority.
>  * Support the counter on the ringbuffer submission path as well, albeit
>just notionally. (Chris Wilson)
> 
> v3:
>  * Rebase.
> 
> v4:
>  * Rename and move the stats into a container structure. (Chris Wilson)
> 
> v5:
>  * Re-order fields in struct intel_engine_cs. (Chris Wilson)
> 
> v6-v8:
>  * Rebases.
> 
> v9:
>  * Fix accounting during wedging.
> 
> Signed-off-by: Tvrtko Ursulin 
> ---
>  drivers/gpu/drm/i915/i915_gem.c | 1 +
>  drivers/gpu/drm/i915/i915_request.c | 7 +++
>  drivers/gpu/drm/i915/intel_engine_cs.c  | 5 +++--
>  drivers/gpu/drm/i915/intel_lrc.c| 1 +
>  drivers/gpu/drm/i915/intel_ringbuffer.h | 9 +
>  5 files changed, 21 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 9650a7b10c5f..63f334d5f7fd 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3211,6 +3211,7 @@ static void nop_complete_submit_request(struct 
> i915_request *request)
> dma_fence_set_error(>fence, -EIO);
>  
> spin_lock_irqsave(>engine->timeline->lock, flags);
> +   request->engine->request_stats.runnable++;
> __i915_request_submit(request);
> intel_engine_init_global_seqno(request->engine, 
> request->global_seqno);
> spin_unlock_irqrestore(>engine->timeline->lock, flags);
> diff --git a/drivers/gpu/drm/i915/i915_request.c 
> b/drivers/gpu/drm/i915/i915_request.c
> index 585242831974..5c01291ad1cc 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -540,6 +540,9 @@ void __i915_request_submit(struct i915_request *request)
> /* Transfer from per-context onto the global per-engine timeline */
> move_to_timeline(request, engine->timeline);
>  
> +   GEM_BUG_ON(engine->request_stats.runnable == 0);
> +   engine->request_stats.runnable--;
> +
> trace_i915_request_execute(request);
>  
> wake_up_all(>execute);
> @@ -553,6 +556,8 @@ void i915_request_submit(astruct i915_request *request)
> /* Will be called from irq-context when using foreign fences. */
> spin_lock_irqsave(>timeline->lock, flags);
>  
> +   engine->request_stats.runnable++;

Hmm, I was thinking this should be in submit_notify(), as you want to
count from when all fences are signaled.

But you are using the timeline lock as its guard?

The only downside is having to repeat the inc in each path. And with the
slight disparity for unsubmit. Not a blocker, just had to actually think
about what you were doing, so maybe discuss that upfront in the commit
msg.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: Send DPCD ON for MST before phy_up

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Send DPCD ON for MST before phy_up
URL   : https://patchwork.freedesktop.org/series/41297/
State : success

== Summary ==

Series 41297v1 drm/i915/dp: Send DPCD ON for MST before phy_up
https://patchwork.freedesktop.org/api/1.0/series/41297/revisions/1/mbox/

 Known issues:

Test debugfs_test:
Subgroup read_all_entries:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (fi-skl-6700k2) fdo#103191

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:430s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:447s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:380s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:538s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:300s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:514s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:515s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:520s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:510s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:412s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:559s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:513s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:582s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:423s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:318s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:535s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:488s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:403s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:424s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:476s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:432s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:475s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:465s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:512s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:646s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:442s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:532s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:503s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:506s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:431s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:449s
fi-snb-2520m total:3pass:2dwarn:0   dfail:0   fail:0   skip:0  
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:397s

e023242a3ebab3e7a4e5d7647d7b08c0d2be5d4c drm-tip: 2018y-04m-06d-19h-07m-27s UTC 
integration manifest
34a2da81056d drm/i915/dp: Send DPCD ON for MST before phy_up

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8628/issues.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Split out parking from the idle worker for reuse (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Split out parking from the idle worker for reuse (rev2)
URL   : https://patchwork.freedesktop.org/series/41278/
State : success

== Summary ==

 Possible new issues:

Test gem_mmap_gtt:
Subgroup forked-medium-copy-odd:
dmesg-warn -> PASS   (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup fbc-2p-pri-indfb-multidraw:
dmesg-fail -> PASS   (shard-hsw)

 Known issues:

Test kms_cursor_legacy:
Subgroup 2x-long-flip-vs-cursor-legacy:
fail   -> PASS   (shard-hsw) fdo#104873
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
fail   -> PASS   (shard-hsw) fdo#102887
Test kms_rotation_crc:
Subgroup primary-rotation-180:
pass   -> FAIL   (shard-snb) fdo#103925
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-apl) fdo#99912
Test kms_sysfs_edid_timing:
warn   -> PASS   (shard-apl) fdo#100047

fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047

shard-apltotal:2680 pass:1837 dwarn:1   dfail:0   fail:6   skip:836 
time:12668s
shard-hswtotal:2680 pass:1786 dwarn:1   dfail:0   fail:1   skip:891 
time:11379s
shard-snbtotal:2680 pass:1377 dwarn:1   dfail:0   fail:3   skip:1299 
time:6821s
Blacklisted hosts:
shard-kbltotal:2680 pass:1963 dwarn:1   dfail:0   fail:7   skip:709 
time:9148s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8623/shards.html
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Re: [Intel-gfx] [PATCH v4] drm/i915/dp: Send DPCD ON for MST before phy_up

[Lyude Paul]

On Fri, 2018-04-06 at 12:48 -0700, Laura Abbott wrote:
> On 04/06/2018 11:52 AM, Lyude Paul wrote:
> > When doing a modeset where the sink is transitioning from D3 to D0 , it
> > would sometimes be possible for the initial power_up_phy() to start
> > timing out. This would only be observed in the last action before the
> > sink went into D3 mode was intel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We
> > originally thought this might be an issue with us accidentally shutting
> > off the aux block when putting the sink into D3, but since the DP spec
> > mandates that sinks must wake up within 1ms while we have 100ms to
> > respond to an ESI irq, this didn't really add up. Turns out that the
> > problem is more subtle then that:
> > 
> > It turns out that the timeout is from us not enabling DPMS on the MST
> > hub before actually trying to initiate sideband communications. This
> > would cause the first sideband communication (power_up_phy()), to start
> > timing out because the sink wasn't ready to respond. Afterwards, we
> > would call intel_dp_sink_dpms(DRM_MODE_DPMS_ON) in
> > intel_ddi_pre_enable_dp(), which would actually result in waking up the
> > sink so that sideband requests would work again.
> > 
> > Since DPMS is what lets us actually bring the hub up into a state where
> > sideband communications become functional again, we just need to make
> > sure to enable DPMS on the display before attempting to perform sideband
> > communications.
> > 
> > Changes since v1:
> > - Remove comment above if (!intel_dp->is_mst) - vsryjala
> > - Move intel_dp_sink_dpms() for MST into intel_dp_post_disable_mst() to
> >keep enable/disable paths symmetrical
> > - Improve commit message - dhnkrn
> > Changes since v2:
> > - Only send DPMS off when we're disabling the last sink, and only send
> >DPMS on when we're enabling the first sink - dhnkrn
> > Changes since v3:
> > - Check against is_mst, not intel_dp->is_mst - dhnkrn/vsyrjala
> > 
> 
> For the booting docked with lid down case:
> 
> Tested-by: Laura Abbott 

Awesome, will push once the CI run finishes. Thanks for the help!
> 
> > Signed-off-by: Lyude Paul 
> > Cc: Dhinakaran Pandiyan 
> > Cc: Ville Syrjälä 
> > Cc: Laura Abbott 
> > Cc: sta...@vger.kernel.org
> > Fixes: ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd to enable MST
> > hub.")
> > ---
> >   drivers/gpu/drm/i915/intel_ddi.c| 8 ++--
> >   drivers/gpu/drm/i915/intel_dp_mst.c | 8 +++-
> >   2 files changed, 13 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index a6672a9abd85..92cb26b18a9b 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2324,7 +2324,8 @@ static void intel_ddi_pre_enable_dp(struct
> > intel_encoder *encoder,
> > intel_prepare_dp_ddi_buffers(encoder, crtc_state);
> >   
> > intel_ddi_init_dp_buf_reg(encoder);
> > -   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> > +   if (!is_mst)
> > +   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> > intel_dp_start_link_train(intel_dp);
> > if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
> > intel_dp_stop_link_train(intel_dp);
> > @@ -2422,12 +2423,15 @@ static void intel_ddi_post_disable_dp(struct
> > intel_encoder *encoder,
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > struct intel_digital_port *dig_port = enc_to_dig_port(
> > >base);
> > struct intel_dp *intel_dp = _port->dp;
> > +   bool is_mst = intel_crtc_has_type(old_crtc_state,
> > + INTEL_OUTPUT_DP_MST);
> >   
> > /*
> >  * Power down sink before disabling the port, otherwise we end
> >  * up getting interrupts from the sink on detecting link loss.
> >  */
> > -   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
> > +   if (!is_mst)
> > +   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
> >   
> > intel_disable_ddi_buf(encoder);
> >   
> > diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> > b/drivers/gpu/drm/i915/intel_dp_mst.c
> > index c3de0918ee13..9e6956c08688 100644
> > --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> > @@ -180,9 +180,11 @@ static void intel_mst_post_disable_dp(struct
> > intel_encoder *encoder,
> > intel_dp->active_mst_links--;
> >   
> > intel_mst->connector = NULL;
> > -   if (intel_dp->active_mst_links == 0)
> > +   if (intel_dp->active_mst_links == 0) {
> > +   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
> > intel_dig_port->base.post_disable(_dig_port->base,
> >   old_crtc_state, NULL);
> > +   }
> >   
> > DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
> >   }
> > @@ -223,7 +225,11 @@ static void 

Re: [Intel-gfx] [PATCH v4] drm/i915/dp: Send DPCD ON for MST before phy_up

[Laura Abbott]

On 04/06/2018 11:52 AM, Lyude Paul wrote:

When doing a modeset where the sink is transitioning from D3 to D0 , it
would sometimes be possible for the initial power_up_phy() to start
timing out. This would only be observed in the last action before the
sink went into D3 mode was intel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We
originally thought this might be an issue with us accidentally shutting
off the aux block when putting the sink into D3, but since the DP spec
mandates that sinks must wake up within 1ms while we have 100ms to
respond to an ESI irq, this didn't really add up. Turns out that the
problem is more subtle then that:

It turns out that the timeout is from us not enabling DPMS on the MST
hub before actually trying to initiate sideband communications. This
would cause the first sideband communication (power_up_phy()), to start
timing out because the sink wasn't ready to respond. Afterwards, we
would call intel_dp_sink_dpms(DRM_MODE_DPMS_ON) in
intel_ddi_pre_enable_dp(), which would actually result in waking up the
sink so that sideband requests would work again.

Since DPMS is what lets us actually bring the hub up into a state where
sideband communications become functional again, we just need to make
sure to enable DPMS on the display before attempting to perform sideband
communications.

Changes since v1:
- Remove comment above if (!intel_dp->is_mst) - vsryjala
- Move intel_dp_sink_dpms() for MST into intel_dp_post_disable_mst() to
   keep enable/disable paths symmetrical
- Improve commit message - dhnkrn
Changes since v2:
- Only send DPMS off when we're disabling the last sink, and only send
   DPMS on when we're enabling the first sink - dhnkrn
Changes since v3:
- Check against is_mst, not intel_dp->is_mst - dhnkrn/vsyrjala



For the booting docked with lid down case:

Tested-by: Laura Abbott 


Signed-off-by: Lyude Paul 
Cc: Dhinakaran Pandiyan 
Cc: Ville Syrjälä 
Cc: Laura Abbott 
Cc: sta...@vger.kernel.org
Fixes: ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.")
---
  drivers/gpu/drm/i915/intel_ddi.c| 8 ++--
  drivers/gpu/drm/i915/intel_dp_mst.c | 8 +++-
  2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index a6672a9abd85..92cb26b18a9b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2324,7 +2324,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder 
*encoder,
intel_prepare_dp_ddi_buffers(encoder, crtc_state);
  
  	intel_ddi_init_dp_buf_reg(encoder);

-   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+   if (!is_mst)
+   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
@@ -2422,12 +2423,15 @@ static void intel_ddi_post_disable_dp(struct 
intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port = enc_to_dig_port(>base);
struct intel_dp *intel_dp = _port->dp;
+   bool is_mst = intel_crtc_has_type(old_crtc_state,
+ INTEL_OUTPUT_DP_MST);
  
  	/*

 * Power down sink before disabling the port, otherwise we end
 * up getting interrupts from the sink on detecting link loss.
 */
-   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
+   if (!is_mst)
+   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
  
  	intel_disable_ddi_buf(encoder);
  
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c

index c3de0918ee13..9e6956c08688 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -180,9 +180,11 @@ static void intel_mst_post_disable_dp(struct intel_encoder 
*encoder,
intel_dp->active_mst_links--;
  
  	intel_mst->connector = NULL;

-   if (intel_dp->active_mst_links == 0)
+   if (intel_dp->active_mst_links == 0) {
+   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
intel_dig_port->base.post_disable(_dig_port->base,
  old_crtc_state, NULL);
+   }
  
  	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);

  }
@@ -223,7 +225,11 @@ static void intel_mst_pre_enable_dp(struct intel_encoder 
*encoder,
  
  	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
  
+	if (intel_dp->active_mst_links == 0)

+   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+
drm_dp_send_power_updown_phy(_dp->mst_mgr, connector->port, true);
+
if (intel_dp->active_mst_links == 0)
intel_dig_port->base.pre_enable(_dig_port->base,
 

Re: [Intel-gfx] [PATCH 5/7] drm/vmwgfx: Stop updating plane->fb

[Ville Syrjälä]

On Fri, Apr 06, 2018 at 07:14:51PM +, Deepak Singh Rawat wrote:
> This makes sense once we got rid of plane->fb
> 
> Will this go to drm-next?

The plan is to push to drm-misc-next once we get all
the ducks in a row.

> Could you please CC
> me so that I can do some testing myself. Thanks.

Here's a branch if you want a head start:
git://github.com/vsyrjala/linux.git plane_fb_crtc_nuke_2

I'd definitely appreciate some testing of this stuff. Wouldn't
want to break you stuff accidentally.

> 
> Reviewed-by: Deepak Rawat 
> 
> 
> > 
> > From: Ville Syrjälä 
> > 
> > We want to get rid of plane->fb on atomic drivers. Stop setting it.
> > 
> > Cc: Thomas Hellstrom 
> > Cc: Sinclair Yeh 
> > Cc: VMware Graphics 
> > Cc: Daniel Vetter 
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c | 2 --
> >  drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c | 2 --
> >  2 files changed, 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
> > b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
> > index 648f8127f65a..bbd3f19b1a0b 100644
> > --- a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
> > +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
> > @@ -525,8 +525,6 @@ vmw_sou_primary_plane_atomic_update(struct
> > drm_plane *plane,
> >  */
> > if (ret != 0)
> > DRM_ERROR("Failed to update screen.\n");
> > -
> > -   crtc->primary->fb = plane->state->fb;
> > } else {
> > /*
> >  * When disabling a plane, CRTC and FB should always be
> > NULL
> > diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
> > b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
> > index 67331f01ef32..90445bc590cb 100644
> > --- a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
> > +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
> > @@ -1285,8 +1285,6 @@ vmw_stdu_primary_plane_atomic_update(struct
> > drm_plane *plane,
> >  1, 1, NULL, crtc);
> > if (ret)
> > DRM_ERROR("Failed to update STDU.\n");
> > -
> > -   crtc->primary->fb = plane->state->fb;
> > } else {
> > crtc = old_state->crtc;
> > stdu = vmw_crtc_to_stdu(crtc);
> > --
> > 2.16.1

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: enable psr1 on psr2 panels

[Patchwork]

== Series Details ==

Series: drm/i915/psr: enable psr1 on psr2 panels
URL   : https://patchwork.freedesktop.org/series/41294/
State : success

== Summary ==

Series 41294v1 drm/i915/psr: enable psr1 on psr2 panels
https://patchwork.freedesktop.org/api/1.0/series/41294/revisions/1/mbox/

 Possible new issues:

Test drv_module_reload:
Subgroup basic-no-display:
incomplete -> PASS   (fi-elk-e7500)

 Known issues:

Test prime_vgem:
Subgroup basic-fence-flip:
pass   -> FAIL   (fi-ilk-650) fdo#104008

fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:436s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:444s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:383s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:533s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:297s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:513s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:528s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:511s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:411s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:567s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:514s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:592s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:423s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:317s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:536s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:487s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:405s
fi-ilk-650   total:285  pass:224  dwarn:0   dfail:0   fail:1   skip:60  
time:426s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:473s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:440s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:475s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:465s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:506s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:670s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:449s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:533s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:510s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:502s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:430s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:448s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:572s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:406s

3cbdbfb1ecc8769c8db88e95b1d6ea55c5e87dbf drm-tip: 2018y-04m-06d-15h-15m-21s UTC 
integration manifest
768ed9ff8e29 drm/i915/psr: enable psr1 on psr2 panels

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8627/issues.html
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Re: [Intel-gfx] [PATCH v4] drm/i915/dp: Send DPCD ON for MST before phy_up

[Ville Syrjälä]

On Fri, Apr 06, 2018 at 12:28:30PM -0700, Dhinakaran Pandiyan wrote:
> 
> 
> 
> On Fri, 2018-04-06 at 14:52 -0400, Lyude Paul wrote:
> > When doing a modeset where the sink is transitioning from D3 to D0 , it
> > would sometimes be possible for the initial power_up_phy() to start
> > timing out. This would only be observed in the last action before the
> > sink went into D3 mode was intel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We
> > originally thought this might be an issue with us accidentally shutting
> > off the aux block when putting the sink into D3, but since the DP spec
> > mandates that sinks must wake up within 1ms while we have 100ms to
> > respond to an ESI irq, this didn't really add up. Turns out that the
> > problem is more subtle then that:
> > 
> > It turns out that the timeout is from us not enabling DPMS on the MST
> > hub before actually trying to initiate sideband communications. This
> > would cause the first sideband communication (power_up_phy()), to start
> > timing out because the sink wasn't ready to respond. Afterwards, we
> > would call intel_dp_sink_dpms(DRM_MODE_DPMS_ON) in
> > intel_ddi_pre_enable_dp(), which would actually result in waking up the
> > sink so that sideband requests would work again.
> > 
> > Since DPMS is what lets us actually bring the hub up into a state where
> > sideband communications become functional again, we just need to make
> > sure to enable DPMS on the display before attempting to perform sideband
> > communications.
> > 
> 
> Matches my understanding of the problem
> 
> Reviewed-by: Dhinakaran Pandiyan 
> 
> It's better to get an ack from Ville considering I was okay with the
> D3_AUX_ON solution too.

lgtm
Reviewed-by: Ville Syrjälä 

> 
> 
> > Changes since v1:
> > - Remove comment above if (!intel_dp->is_mst) - vsryjala
> > - Move intel_dp_sink_dpms() for MST into intel_dp_post_disable_mst() to
> >   keep enable/disable paths symmetrical
> > - Improve commit message - dhnkrn
> > Changes since v2:
> > - Only send DPMS off when we're disabling the last sink, and only send
> >   DPMS on when we're enabling the first sink - dhnkrn
> > Changes since v3:
> > - Check against is_mst, not intel_dp->is_mst - dhnkrn/vsyrjala
> > 
> > Signed-off-by: Lyude Paul 
> > Cc: Dhinakaran Pandiyan 
> > Cc: Ville Syrjälä 
> > Cc: Laura Abbott 
> > Cc: sta...@vger.kernel.org
> > Fixes: ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd to enable MST 
> > hub.")
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c| 8 ++--
> >  drivers/gpu/drm/i915/intel_dp_mst.c | 8 +++-
> >  2 files changed, 13 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index a6672a9abd85..92cb26b18a9b 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2324,7 +2324,8 @@ static void intel_ddi_pre_enable_dp(struct 
> > intel_encoder *encoder,
> > intel_prepare_dp_ddi_buffers(encoder, crtc_state);
> >  
> > intel_ddi_init_dp_buf_reg(encoder);
> > -   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> > +   if (!is_mst)
> > +   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> > intel_dp_start_link_train(intel_dp);
> > if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
> > intel_dp_stop_link_train(intel_dp);
> > @@ -2422,12 +2423,15 @@ static void intel_ddi_post_disable_dp(struct 
> > intel_encoder *encoder,
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > struct intel_digital_port *dig_port = enc_to_dig_port(>base);
> > struct intel_dp *intel_dp = _port->dp;
> > +   bool is_mst = intel_crtc_has_type(old_crtc_state,
> > + INTEL_OUTPUT_DP_MST);
> >  
> > /*
> >  * Power down sink before disabling the port, otherwise we end
> >  * up getting interrupts from the sink on detecting link loss.
> >  */
> > -   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
> > +   if (!is_mst)
> > +   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
> >  
> > intel_disable_ddi_buf(encoder);
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
> > b/drivers/gpu/drm/i915/intel_dp_mst.c
> > index c3de0918ee13..9e6956c08688 100644
> > --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> > @@ -180,9 +180,11 @@ static void intel_mst_post_disable_dp(struct 
> > intel_encoder *encoder,
> > intel_dp->active_mst_links--;
> >  
> > intel_mst->connector = NULL;
> > -   if (intel_dp->active_mst_links == 0)
> > +   if (intel_dp->active_mst_links == 0) {
> > +   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
> > intel_dig_port->base.post_disable(_dig_port->base,
> >   old_crtc_state, NULL);

Re: [Intel-gfx] [PATCH 5/7] drm/vmwgfx: Stop updating plane->fb

[Deepak Singh Rawat]

This makes sense once we got rid of plane->fb

Will this go to drm-next? Could you please CC
me so that I can do some testing myself. Thanks.

Reviewed-by: Deepak Rawat 


> 
> From: Ville Syrjälä 
> 
> We want to get rid of plane->fb on atomic drivers. Stop setting it.
> 
> Cc: Thomas Hellstrom 
> Cc: Sinclair Yeh 
> Cc: VMware Graphics 
> Cc: Daniel Vetter 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c | 2 --
>  drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c | 2 --
>  2 files changed, 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
> b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
> index 648f8127f65a..bbd3f19b1a0b 100644
> --- a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
> +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
> @@ -525,8 +525,6 @@ vmw_sou_primary_plane_atomic_update(struct
> drm_plane *plane,
>*/
>   if (ret != 0)
>   DRM_ERROR("Failed to update screen.\n");
> -
> - crtc->primary->fb = plane->state->fb;
>   } else {
>   /*
>* When disabling a plane, CRTC and FB should always be
> NULL
> diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
> b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
> index 67331f01ef32..90445bc590cb 100644
> --- a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
> +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
> @@ -1285,8 +1285,6 @@ vmw_stdu_primary_plane_atomic_update(struct
> drm_plane *plane,
>1, 1, NULL, crtc);
>   if (ret)
>   DRM_ERROR("Failed to update STDU.\n");
> -
> - crtc->primary->fb = plane->state->fb;
>   } else {
>   crtc = old_state->crtc;
>   stdu = vmw_crtc_to_stdu(crtc);
> --
> 2.16.1
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Re: [Intel-gfx] [PATCH v3] drm/i915: Split out parking from the idle worker for reuse

[Chris Wilson]

Quoting Michal Wajdeczko (2018-04-06 17:57:20)
> On Fri, 06 Apr 2018 17:51:44 +0200, Chris Wilson  
>  wrote:
> 
> > We will want to park GEM before disengaging the drive^W^W^W unwedging.
> > Since we already do the work for idling, expose the guts as a new
> > function that we can then reuse.
> >
> > v2: Just skip if already parked; makes it more forgiving to use by
> > future callers.
> > v3: Extract mark_busy, rename it to i915_gem_unpark and place it next to
> > i915_gem_park so that we can evaluate it for symmetry more easily.
> > Calling GEM from inside i915_request looks to be a bit of a layering
> > violation, for the moment I am imaging them as being notify_cb.
> >
> > Signed-off-by: Chris Wilson 
> > Cc: Michal Wajdeczko 
> > Cc: Sagar Arun Kamble 
> > Cc: Tvrtko Ursulin 
> > Cc: Mika Kuoppala 
> > Reviewed-by: Mika Kuoppala  #v1
> > ---
> 
> Reviewed-by: Michal Wajdeczko 

And into the mix it goes. Thanks for the suggestions and reviews,
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/psr: enable psr1 on psr2 panels

[Rodrigo Vivi]

On Fri, Apr 06, 2018 at 12:10:24PM -0700, Dhinakaran Pandiyan wrote:
> 
> 
> 
> On Sat, 2018-04-07 at 00:12 +0530, vathsala nagaraju wrote:
> > From: Vathsala Nagaraju 
> > 
> > Adds force_psr1 mod parameter to enable psr1 on psr2 panels.
> > useful in cases where psr2 fails and user wants to enable
> > psr1 feature for power saving until a fix
> > is provided for psr2.

The parameters shouldn't be used by users to select a configuration.
They are marked as unsafe. We should only enable the feature when
we are comfortable it doesn't cause trouble.

> 
> 
> We should perhaps make enable_psr=1 enable just PSR1. I am not
> comfortable that we enable PSR2 at all, there are no tests in IGT for
> selective update, seems like nobody really knows exactly how well it
> works. 

Agreed. Probably good for now to avoid PSR2 in all situations and only
allow PSR2 when we are properly testing it.

> 
> 
> > 
> > Cc: Rodrigo Vivi 
> > Cc: Dhinakaran Pandiyan 
> > Cc: José Roberto de Souza 
> > Signed-off-by: Vathsala Nagaraju 
> > ---
> >  drivers/gpu/drm/i915/i915_params.c | 5 +
> >  drivers/gpu/drm/i915/i915_params.h | 1 +
> >  drivers/gpu/drm/i915/intel_psr.c   | 2 ++
> >  3 files changed, 8 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_params.c 
> > b/drivers/gpu/drm/i915/i915_params.c
> > index 08108ce..5b6f5af 100644
> > --- a/drivers/gpu/drm/i915/i915_params.c
> > +++ b/drivers/gpu/drm/i915/i915_params.c
> > @@ -95,6 +95,11 @@ struct i915_params i915_modparams __read_mostly = {
> > "(0=disabled, 1=enabled - link mode chosen per-platform, 2=force 
> > link-standby mode, 3=force link-off mode) "
> > "Default: -1 (use per-chip default)");
> >  
> > +i915_param_named_unsafe(force_psr1, int, 0600,
> > +   "Enable PSR1 on PSR2 Panel "
> > +   "(0=disabled, 1=enabled) "
> > +   "Default: -1 (use per-chip default)");
> > +
> >  i915_param_named_unsafe(alpha_support, bool, 0400,
> > "Enable alpha quality driver support for latest hardware. "
> > "See also CONFIG_DRM_I915_ALPHA_SUPPORT.");
> > diff --git a/drivers/gpu/drm/i915/i915_params.h 
> > b/drivers/gpu/drm/i915/i915_params.h
> > index c963603..1f5dd1c 100644
> > --- a/drivers/gpu/drm/i915/i915_params.h
> > +++ b/drivers/gpu/drm/i915/i915_params.h
> > @@ -44,6 +44,7 @@
> > param(int, enable_fbc, -1) \
> > param(int, enable_ppgtt, -1) \
> > param(int, enable_psr, -1) \
> > +   param(int, force_psr1, -1) \
> > param(int, disable_power_well, -1) \
> > param(int, enable_ips, 1) \
> > param(int, invert_brightness, 0) \
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 2d53f73..415e377 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -540,6 +540,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> >  
> > crtc_state->has_psr = true;
> > crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
> > +   if (i915_modparams.force_psr1 == 1 && crtc_state->has_psr2)
> > +   crtc_state->has_psr2 = false;
> > DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2" : "");
> >  }
> >  
> 
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: enable psr1 on psr2 panels

[Patchwork]

== Series Details ==

Series: drm/i915/psr: enable psr1 on psr2 panels
URL   : https://patchwork.freedesktop.org/series/41294/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
768ed9ff8e29 drm/i915/psr: enable psr1 on psr2 panels
-:28: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#28: FILE: drivers/gpu/drm/i915/i915_params.c:99:
+i915_param_named_unsafe(force_psr1, int, 0600,
+   "Enable PSR1 on PSR2 Panel "

total: 0 errors, 0 warnings, 1 checks, 26 lines checked

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Re: [Intel-gfx] [PATCH v4] drm/i915/dp: Send DPCD ON for MST before phy_up

[Dhinakaran Pandiyan]

On Fri, 2018-04-06 at 14:52 -0400, Lyude Paul wrote:
> When doing a modeset where the sink is transitioning from D3 to D0 , it
> would sometimes be possible for the initial power_up_phy() to start
> timing out. This would only be observed in the last action before the
> sink went into D3 mode was intel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We
> originally thought this might be an issue with us accidentally shutting
> off the aux block when putting the sink into D3, but since the DP spec
> mandates that sinks must wake up within 1ms while we have 100ms to
> respond to an ESI irq, this didn't really add up. Turns out that the
> problem is more subtle then that:
> 
> It turns out that the timeout is from us not enabling DPMS on the MST
> hub before actually trying to initiate sideband communications. This
> would cause the first sideband communication (power_up_phy()), to start
> timing out because the sink wasn't ready to respond. Afterwards, we
> would call intel_dp_sink_dpms(DRM_MODE_DPMS_ON) in
> intel_ddi_pre_enable_dp(), which would actually result in waking up the
> sink so that sideband requests would work again.
> 
> Since DPMS is what lets us actually bring the hub up into a state where
> sideband communications become functional again, we just need to make
> sure to enable DPMS on the display before attempting to perform sideband
> communications.
> 

Matches my understanding of the problem

Reviewed-by: Dhinakaran Pandiyan 

It's better to get an ack from Ville considering I was okay with the
D3_AUX_ON solution too.


> Changes since v1:
> - Remove comment above if (!intel_dp->is_mst) - vsryjala
> - Move intel_dp_sink_dpms() for MST into intel_dp_post_disable_mst() to
>   keep enable/disable paths symmetrical
> - Improve commit message - dhnkrn
> Changes since v2:
> - Only send DPMS off when we're disabling the last sink, and only send
>   DPMS on when we're enabling the first sink - dhnkrn
> Changes since v3:
> - Check against is_mst, not intel_dp->is_mst - dhnkrn/vsyrjala
> 
> Signed-off-by: Lyude Paul 
> Cc: Dhinakaran Pandiyan 
> Cc: Ville Syrjälä 
> Cc: Laura Abbott 
> Cc: sta...@vger.kernel.org
> Fixes: ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd to enable MST 
> hub.")
> ---
>  drivers/gpu/drm/i915/intel_ddi.c| 8 ++--
>  drivers/gpu/drm/i915/intel_dp_mst.c | 8 +++-
>  2 files changed, 13 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index a6672a9abd85..92cb26b18a9b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2324,7 +2324,8 @@ static void intel_ddi_pre_enable_dp(struct 
> intel_encoder *encoder,
>   intel_prepare_dp_ddi_buffers(encoder, crtc_state);
>  
>   intel_ddi_init_dp_buf_reg(encoder);
> - intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> + if (!is_mst)
> + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
>   intel_dp_start_link_train(intel_dp);
>   if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
>   intel_dp_stop_link_train(intel_dp);
> @@ -2422,12 +2423,15 @@ static void intel_ddi_post_disable_dp(struct 
> intel_encoder *encoder,
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   struct intel_digital_port *dig_port = enc_to_dig_port(>base);
>   struct intel_dp *intel_dp = _port->dp;
> + bool is_mst = intel_crtc_has_type(old_crtc_state,
> +   INTEL_OUTPUT_DP_MST);
>  
>   /*
>* Power down sink before disabling the port, otherwise we end
>* up getting interrupts from the sink on detecting link loss.
>*/
> - intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
> + if (!is_mst)
> + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
>  
>   intel_disable_ddi_buf(encoder);
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
> b/drivers/gpu/drm/i915/intel_dp_mst.c
> index c3de0918ee13..9e6956c08688 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -180,9 +180,11 @@ static void intel_mst_post_disable_dp(struct 
> intel_encoder *encoder,
>   intel_dp->active_mst_links--;
>  
>   intel_mst->connector = NULL;
> - if (intel_dp->active_mst_links == 0)
> + if (intel_dp->active_mst_links == 0) {
> + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
>   intel_dig_port->base.post_disable(_dig_port->base,
> old_crtc_state, NULL);
> + }
>  
>   DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
>  }
> @@ -223,7 +225,11 @@ static void intel_mst_pre_enable_dp(struct intel_encoder 
> *encoder,
>  
>   DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
>  
> + if 

Re: [Intel-gfx] [PATCH 6/7] drm/vmwgfx: Stop using plane->fb in atomic_enable()

[Deepak Singh Rawat]

> 
> From: Ville Syrjälä 
> 
> Instead of looking at the (soon to be deprecated) plane->fb we'll
> examing plane->state->fb instead. We can do this because
> vmw_du_crtc_atomic_check() prevents us from enabling a crtc
> without the primary plane also being enabled.
> 
> Due to that same reason, I'm actually not sure what the checks here are
> for NULL fb. If we can't enable the crtc without an enabled plane
> we should always have an fb. But I'll leave that for someone else
> to figure out.

Hi Ville,

AFAIK the NULL check is set or clear the implicit framebuffer property
which is specific to vmwgfx and for current hardware version is disabled.
I have this future TODO work item to get rid of implicit placement property
or at least make it read only.

I still don’t have complete understanding of atomic state but this patch looks
good to me.

Reviewed-by: Deepak Rawat 

> 
> Cc: Thomas Hellstrom 
> Cc: Sinclair Yeh 
> Cc: VMware Graphics 
> Cc: Daniel Vetter 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
> b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
> index 90445bc590cb..152e96cb1c01 100644
> --- a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
> +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
> @@ -414,6 +414,7 @@ static void vmw_stdu_crtc_helper_prepare(struct
> drm_crtc *crtc)
>  static void vmw_stdu_crtc_atomic_enable(struct drm_crtc *crtc,
>   struct drm_crtc_state *old_state)
>  {
> + struct drm_plane_state *plane_state = crtc->primary->state;
>   struct vmw_private *dev_priv;
>   struct vmw_screen_target_display_unit *stdu;
>   struct vmw_framebuffer *vfb;
> @@ -422,7 +423,7 @@ static void vmw_stdu_crtc_atomic_enable(struct
> drm_crtc *crtc,
> 
>   stdu = vmw_crtc_to_stdu(crtc);
>   dev_priv = vmw_priv(crtc->dev);
> - fb   = crtc->primary->fb;
> + fb   = plane_state->fb;
> 
>   vfb = (fb) ? vmw_framebuffer_to_vfb(fb) : NULL;
> 
> --
> 2.16.1
> 
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[Intel-gfx] [PATCH v4] drm/i915/dp: Send DPCD ON for MST before phy_up

[Lyude Paul]

When doing a modeset where the sink is transitioning from D3 to D0 , it
would sometimes be possible for the initial power_up_phy() to start
timing out. This would only be observed in the last action before the
sink went into D3 mode was intel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We
originally thought this might be an issue with us accidentally shutting
off the aux block when putting the sink into D3, but since the DP spec
mandates that sinks must wake up within 1ms while we have 100ms to
respond to an ESI irq, this didn't really add up. Turns out that the
problem is more subtle then that:

It turns out that the timeout is from us not enabling DPMS on the MST
hub before actually trying to initiate sideband communications. This
would cause the first sideband communication (power_up_phy()), to start
timing out because the sink wasn't ready to respond. Afterwards, we
would call intel_dp_sink_dpms(DRM_MODE_DPMS_ON) in
intel_ddi_pre_enable_dp(), which would actually result in waking up the
sink so that sideband requests would work again.

Since DPMS is what lets us actually bring the hub up into a state where
sideband communications become functional again, we just need to make
sure to enable DPMS on the display before attempting to perform sideband
communications.

Changes since v1:
- Remove comment above if (!intel_dp->is_mst) - vsryjala
- Move intel_dp_sink_dpms() for MST into intel_dp_post_disable_mst() to
  keep enable/disable paths symmetrical
- Improve commit message - dhnkrn
Changes since v2:
- Only send DPMS off when we're disabling the last sink, and only send
  DPMS on when we're enabling the first sink - dhnkrn
Changes since v3:
- Check against is_mst, not intel_dp->is_mst - dhnkrn/vsyrjala

Signed-off-by: Lyude Paul 
Cc: Dhinakaran Pandiyan 
Cc: Ville Syrjälä 
Cc: Laura Abbott 
Cc: sta...@vger.kernel.org
Fixes: ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.")
---
 drivers/gpu/drm/i915/intel_ddi.c| 8 ++--
 drivers/gpu/drm/i915/intel_dp_mst.c | 8 +++-
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index a6672a9abd85..92cb26b18a9b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2324,7 +2324,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder 
*encoder,
intel_prepare_dp_ddi_buffers(encoder, crtc_state);
 
intel_ddi_init_dp_buf_reg(encoder);
-   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+   if (!is_mst)
+   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
@@ -2422,12 +2423,15 @@ static void intel_ddi_post_disable_dp(struct 
intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port = enc_to_dig_port(>base);
struct intel_dp *intel_dp = _port->dp;
+   bool is_mst = intel_crtc_has_type(old_crtc_state,
+ INTEL_OUTPUT_DP_MST);
 
/*
 * Power down sink before disabling the port, otherwise we end
 * up getting interrupts from the sink on detecting link loss.
 */
-   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
+   if (!is_mst)
+   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
 
intel_disable_ddi_buf(encoder);
 
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
b/drivers/gpu/drm/i915/intel_dp_mst.c
index c3de0918ee13..9e6956c08688 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -180,9 +180,11 @@ static void intel_mst_post_disable_dp(struct intel_encoder 
*encoder,
intel_dp->active_mst_links--;
 
intel_mst->connector = NULL;
-   if (intel_dp->active_mst_links == 0)
+   if (intel_dp->active_mst_links == 0) {
+   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
intel_dig_port->base.post_disable(_dig_port->base,
  old_crtc_state, NULL);
+   }
 
DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
 }
@@ -223,7 +225,11 @@ static void intel_mst_pre_enable_dp(struct intel_encoder 
*encoder,
 
DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
 
+   if (intel_dp->active_mst_links == 0)
+   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+
drm_dp_send_power_updown_phy(_dp->mst_mgr, connector->port, true);
+
if (intel_dp->active_mst_links == 0)
intel_dig_port->base.pre_enable(_dig_port->base,
pipe_config, NULL);
-- 
2.14.3

___
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Re: [Intel-gfx] [PATCH] drm/i915/psr: enable psr1 on psr2 panels

[Dhinakaran Pandiyan]

On Sat, 2018-04-07 at 00:12 +0530, vathsala nagaraju wrote:
> From: Vathsala Nagaraju 
> 
> Adds force_psr1 mod parameter to enable psr1 on psr2 panels.
> useful in cases where psr2 fails and user wants to enable
> psr1 feature for power saving until a fix
> is provided for psr2.


We should perhaps make enable_psr=1 enable just PSR1. I am not
comfortable that we enable PSR2 at all, there are no tests in IGT for
selective update, seems like nobody really knows exactly how well it
works. 


> 
> Cc: Rodrigo Vivi 
> Cc: Dhinakaran Pandiyan 
> Cc: José Roberto de Souza 
> Signed-off-by: Vathsala Nagaraju 
> ---
>  drivers/gpu/drm/i915/i915_params.c | 5 +
>  drivers/gpu/drm/i915/i915_params.h | 1 +
>  drivers/gpu/drm/i915/intel_psr.c   | 2 ++
>  3 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_params.c 
> b/drivers/gpu/drm/i915/i915_params.c
> index 08108ce..5b6f5af 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -95,6 +95,11 @@ struct i915_params i915_modparams __read_mostly = {
>   "(0=disabled, 1=enabled - link mode chosen per-platform, 2=force 
> link-standby mode, 3=force link-off mode) "
>   "Default: -1 (use per-chip default)");
>  
> +i915_param_named_unsafe(force_psr1, int, 0600,
> + "Enable PSR1 on PSR2 Panel "
> + "(0=disabled, 1=enabled) "
> + "Default: -1 (use per-chip default)");
> +
>  i915_param_named_unsafe(alpha_support, bool, 0400,
>   "Enable alpha quality driver support for latest hardware. "
>   "See also CONFIG_DRM_I915_ALPHA_SUPPORT.");
> diff --git a/drivers/gpu/drm/i915/i915_params.h 
> b/drivers/gpu/drm/i915/i915_params.h
> index c963603..1f5dd1c 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -44,6 +44,7 @@
>   param(int, enable_fbc, -1) \
>   param(int, enable_ppgtt, -1) \
>   param(int, enable_psr, -1) \
> + param(int, force_psr1, -1) \
>   param(int, disable_power_well, -1) \
>   param(int, enable_ips, 1) \
>   param(int, invert_brightness, 0) \
> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> b/drivers/gpu/drm/i915/intel_psr.c
> index 2d53f73..415e377 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -540,6 +540,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
>  
>   crtc_state->has_psr = true;
>   crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
> + if (i915_modparams.force_psr1 == 1 && crtc_state->has_psr2)
> + crtc_state->has_psr2 = false;
>   DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2" : "");
>  }
>  

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[Intel-gfx] [PATCH] drm/i915/psr: enable psr1 on psr2 panels

[vathsala nagaraju]

From: Vathsala Nagaraju 

Adds force_psr1 mod parameter to enable psr1 on psr2 panels.
useful in cases where psr2 fails and user wants to enable
psr1 feature for power saving until a fix
is provided for psr2.

Cc: Rodrigo Vivi 
Cc: Dhinakaran Pandiyan 
Cc: José Roberto de Souza 
Signed-off-by: Vathsala Nagaraju 
---
 drivers/gpu/drm/i915/i915_params.c | 5 +
 drivers/gpu/drm/i915/i915_params.h | 1 +
 drivers/gpu/drm/i915/intel_psr.c   | 2 ++
 3 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 08108ce..5b6f5af 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -95,6 +95,11 @@ struct i915_params i915_modparams __read_mostly = {
"(0=disabled, 1=enabled - link mode chosen per-platform, 2=force 
link-standby mode, 3=force link-off mode) "
"Default: -1 (use per-chip default)");
 
+i915_param_named_unsafe(force_psr1, int, 0600,
+   "Enable PSR1 on PSR2 Panel "
+   "(0=disabled, 1=enabled) "
+   "Default: -1 (use per-chip default)");
+
 i915_param_named_unsafe(alpha_support, bool, 0400,
"Enable alpha quality driver support for latest hardware. "
"See also CONFIG_DRM_I915_ALPHA_SUPPORT.");
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index c963603..1f5dd1c 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -44,6 +44,7 @@
param(int, enable_fbc, -1) \
param(int, enable_ppgtt, -1) \
param(int, enable_psr, -1) \
+   param(int, force_psr1, -1) \
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2d53f73..415e377 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -540,6 +540,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 
crtc_state->has_psr = true;
crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
+   if (i915_modparams.force_psr1 == 1 && crtc_state->has_psr2)
+   crtc_state->has_psr2 = false;
DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2" : "");
 }
 
-- 
1.9.1

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Re: [Intel-gfx] [PATCH 4/7] drm/vmwgfx: Stop using plane->fb in vmw_kms_update_implicit_fb()

[Deepak Singh Rawat]

Reviewed-by: Deepak Rawat 

> 
> From: Ville Syrjälä 
> 
> The only caller of vmw_kms_update_implicit_fb() is the page_flip
> hook which itself gets called with the plane mutex already held.
> Hence we can look at plane->state safely. Toss in a lockdep assert
> to make the situation more clear.
> 
> Cc: Thomas Hellstrom 
> Cc: Sinclair Yeh 
> Cc: VMware Graphics 
> Cc: Daniel Vetter 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
> b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
> index 5a824125c231..a93d290b0f35 100644
> --- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
> +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
> @@ -2811,14 +2811,17 @@ void vmw_kms_update_implicit_fb(struct
> vmw_private *dev_priv,
>   struct drm_crtc *crtc)
>  {
>   struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
> + struct drm_plane *plane = crtc->primary;
>   struct vmw_framebuffer *vfb;
> 
> + lockdep_assert_held(>mutex);
> +
>   mutex_lock(_priv->global_kms_state_mutex);
> 
>   if (!du->is_implicit)
>   goto out_unlock;
> 
> - vfb = vmw_framebuffer_to_vfb(crtc->primary->fb);
> + vfb = vmw_framebuffer_to_vfb(plane->state->fb);
>   WARN_ON_ONCE(dev_priv->num_implicit != 1 &&
>dev_priv->implicit_fb != vfb);
> 
> --
> 2.16.1
> 
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Re: [Intel-gfx] [PATCH] drm/i915/psr: Chase psr.enabled only under the psr.lock

[Souza, Jose]

On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote:
> Inside the psr work function, we want to wait for PSR to idle first
> and
> wish to do so without blocking the normal modeset path, so we do so
> without holding the PSR lock. However, we first have to find which
> pipe
> PSR was enabled on, which requires chasing into the PSR struct and
> requires locking to prevent intel_psr_disable() from concurrently
> setting our pointer to NULL.
> 
> Fixes: 995d30477496 ("drm/i915: VLV/CHV PSR Software timer mode")
> Signed-off-by: Chris Wilson 
> Cc: Durgadoss R 
> Cc: Rodrigo Vivi 
> Cc:  # v4.0+

Feel free to add:
Reviewed-by: Jose Roberto de Souza 

> ---
>  drivers/gpu/drm/i915/intel_psr.c | 82 +-
> --
>  1 file changed, 44 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 2d53f7398a6d..69a5b276f4d8 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -775,53 +775,59 @@ void intel_psr_disable(struct intel_dp
> *intel_dp,
>   cancel_delayed_work_sync(_priv->psr.work);
>  }
>  
> -static void intel_psr_work(struct work_struct *work)
> +static bool psr_wait_for_idle(struct drm_i915_private *dev_priv)
>  {
> - struct drm_i915_private *dev_priv =
> - container_of(work, typeof(*dev_priv),
> psr.work.work);
> - struct intel_dp *intel_dp = dev_priv->psr.enabled;
> - struct drm_crtc *crtc = dp_to_dig_port(intel_dp)-
> >base.base.crtc;
> - enum pipe pipe = to_intel_crtc(crtc)->pipe;
> + struct intel_dp *intel_dp;

nitpick: Why not already set it?
struct intel_dp *intel_dp = dev_priv->psr.enabled;


> + i915_reg_t reg;
> + u32 mask;
> + int err;
> +
> + intel_dp = dev_priv->psr.enabled;
> + if (!intel_dp)
> + return false;
>  
> - /* We have to make sure PSR is ready for re-enable
> -  * otherwise it keeps disabled until next full
> enable/disable cycle.
> -  * PSR might take some time to get fully disabled
> -  * and be ready for re-enable.
> -  */
>   if (HAS_DDI(dev_priv)) {


nitpick: While on that you could replace this for:

if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) {

>   if (dev_priv->psr.psr2_enabled) {
> - if (intel_wait_for_register(dev_priv,
> - EDP_PSR2_STATUS,
> - EDP_PSR2_STATUS_
> STATE_MASK,
> - 0,
> - 50)) {
> - DRM_ERROR("Timed out waiting for
> PSR2 Idle for re-enable\n");
> - return;
> - }
> + reg = EDP_PSR2_STATUS;
> + mask = EDP_PSR2_STATUS_STATE_MASK;
>   } else {
> - if (intel_wait_for_register(dev_priv,
> - EDP_PSR_STATUS,
> - EDP_PSR_STATUS_S
> TATE_MASK,
> - 0,
> - 50)) {
> - DRM_ERROR("Timed out waiting for PSR
> Idle for re-enable\n");
> - return;
> - }
> + reg = EDP_PSR_STATUS;
> + mask = EDP_PSR_STATUS_STATE_MASK;
>   }
>   } else {
> - if (intel_wait_for_register(dev_priv,
> - VLV_PSRSTAT(pipe),
> - VLV_EDP_PSR_IN_TRANS,
> - 0,
> - 1)) {
> - DRM_ERROR("Timed out waiting for PSR Idle
> for re-enable\n");
> - return;
> - }
> + struct drm_crtc *crtc =
> + dp_to_dig_port(intel_dp)->base.base.crtc;
> + enum pipe pipe = to_intel_crtc(crtc)->pipe;
> +
> + reg = VLV_PSRSTAT(pipe);
> + mask = VLV_EDP_PSR_IN_TRANS;
>   }
> +
> + mutex_unlock(_priv->psr.lock);
> +
> + err = intel_wait_for_register(dev_priv, reg, mask, 0, 50);
> + if (err)
> + DRM_ERROR("Timed out waiting for PSR Idle for re-
> enable\n");
> +
> + /* After the unlocked wait, verify that PSR is still wanted!
> */
>   mutex_lock(_priv->psr.lock);
> - intel_dp = dev_priv->psr.enabled;
> + return err == 0 && dev_priv->psr.enabled;
> +}
>  
> - if (!intel_dp)
> +static void intel_psr_work(struct work_struct *work)
> +{
> + struct drm_i915_private *dev_priv =
> + container_of(work, typeof(*dev_priv),
> psr.work.work);
> +
> +

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: vbt change for psr

[Patchwork]

== Series Details ==

Series: drm/i915/psr: vbt change for psr
URL   : https://patchwork.freedesktop.org/series/41289/
State : success

== Summary ==

Series 41289v1 drm/i915/psr: vbt change for psr
https://patchwork.freedesktop.org/api/1.0/series/41289/revisions/1/mbox/

 Possible new issues:

Test drv_module_reload:
Subgroup basic-no-display:
incomplete -> PASS   (fi-elk-e7500)

 Known issues:

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-cnl-y3) fdo#104951
Subgroup suspend-read-crc-pipe-c:
incomplete -> PASS   (fi-bxt-dsi) fdo#103927

fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:428s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:442s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:380s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:536s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:299s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:514s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:513s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:522s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:509s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:410s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:561s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:513s
fi-cnl-y3total:285  pass:258  dwarn:1   dfail:0   fail:0   skip:26  
time:594s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:426s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:317s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:544s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:402s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:423s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:468s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:434s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:474s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:463s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:519s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:659s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:445s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:533s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:508s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:504s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:429s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:450s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:569s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:405s

3cbdbfb1ecc8769c8db88e95b1d6ea55c5e87dbf drm-tip: 2018y-04m-06d-15h-15m-21s UTC 
integration manifest
1630bdc52cc9 drm/i915/psr: vbt change for psr

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8626/issues.html
___
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Re: [Intel-gfx] [PATCH v10 10/11] drm: Add aspect ratio parsing in DRM layer

[Ville Syrjälä]

On Fri, Apr 06, 2018 at 10:55:14PM +0530, Nautiyal, Ankit K wrote:
> This patch is causing failure of IGT test kms_3d. The kms_3d test 
> expects the no. of 3d modes to be 13.
> 
> (The test has hard-coded value for expected no. of 3d modes as 13)
> 
> But due to the addition of "matching aspect_ratio" in drm_mode_equal in 
> this patch, the total no. of
> 
> modes in the connector modelist is increased by 2, resulting in failure 
> of assertion 'mode_count==13'.

If kms_3d isn't setting the aspect ratio cap how is it affected by these
changes?

> 
> Perhaps this need to be handled in the test.
> 
> -Regards,
> 
> Ankit
> 
> 
> On 4/6/2018 10:34 PM, Nautiyal, Ankit K wrote:
> > From: "Sharma, Shashank" 
> >
> > Current DRM layer functions don't parse aspect ratio information
> > while converting a user mode->kernel mode or vice versa. This
> > causes modeset to pick mode with wrong aspect ratio, eventually
> > causing failures in HDMI compliance test cases, due to wrong VIC.
> >
> > This patch adds aspect ratio information in DRM's mode conversion
> > and mode comparision functions, to make sure kernel picks mode
> > with right aspect ratio (as per the VIC).
> >
> > Background:
> > This patch was once reviewed and merged, and later reverted due to
> > lack of DRM cap protection. This is a re-spin of this patch, this
> > time with DRM cap protection, to avoid aspect ratio information, when
> > the client doesn't request for it.
> >
> > Review link: https://pw-emeril.freedesktop.org/patch/104068/
> > Background discussion: https://patchwork.kernel.org/patch/9379057/
> >
> > Signed-off-by: Shashank Sharma 
> > Signed-off-by: Lin, Jia 
> > Signed-off-by: Akashdeep Sharma 
> > Reviewed-by: Jim Bride  (V2)
> > Reviewed-by: Jose Abreu  (V4)
> >
> > Cc: Ville Syrjala 
> > Cc: Jim Bride 
> > Cc: Jose Abreu 
> > Cc: Ankit Nautiyal 
> >
> > V3: modified the aspect-ratio check in drm_mode_equal as per new flags
> >  provided by Ville. https://patchwork.freedesktop.org/patch/188043/
> > V4: rebase
> > V5: rebase
> > V6: As recommended by Ville, avoided matching of aspect-ratio in
> >  drm_fb_helper, while trying to find a common mode among connectors
> >  for the target clone mode.
> > V7: rebase
> > V8: rebase
> > V9: rebase
> > V10: rebase
> > ---
> >   drivers/gpu/drm/drm_fb_helper.c | 12 ++--
> >   drivers/gpu/drm/drm_modes.c | 35 ++-
> >   2 files changed, 44 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_fb_helper.c 
> > b/drivers/gpu/drm/drm_fb_helper.c
> > index 0646b10..2ee1eaa 100644
> > --- a/drivers/gpu/drm/drm_fb_helper.c
> > +++ b/drivers/gpu/drm/drm_fb_helper.c
> > @@ -2183,7 +2183,11 @@ static bool drm_target_cloned(struct drm_fb_helper 
> > *fb_helper,
> > for (j = 0; j < i; j++) {
> > if (!enabled[j])
> > continue;
> > -   if (!drm_mode_equal(modes[j], modes[i]))
> > +   if (!drm_mode_match(modes[j], modes[i],
> > +   DRM_MODE_MATCH_TIMINGS |
> > +   DRM_MODE_MATCH_CLOCK |
> > +   DRM_MODE_MATCH_FLAGS |
> > +   DRM_MODE_MATCH_3D_FLAGS))
> > can_clone = false;
> > }
> > }
> > @@ -2203,7 +2207,11 @@ static bool drm_target_cloned(struct drm_fb_helper 
> > *fb_helper,
> >   
> > fb_helper_conn = fb_helper->connector_info[i];
> > list_for_each_entry(mode, _helper_conn->connector->modes, 
> > head) {
> > -   if (drm_mode_equal(mode, dmt_mode))
> > +   if (drm_mode_match(mode, dmt_mode,
> > +  DRM_MODE_MATCH_TIMINGS |
> > +  DRM_MODE_MATCH_CLOCK |
> > +  DRM_MODE_MATCH_FLAGS |
> > +  DRM_MODE_MATCH_3D_FLAGS))
> > modes[i] = mode;
> > }
> > if (!modes[i])
> > diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
> > index d6133e8..454f2ff 100644
> > --- a/drivers/gpu/drm/drm_modes.c
> > +++ b/drivers/gpu/drm/drm_modes.c
> > @@ -1049,7 +1049,8 @@ bool drm_mode_equal(const struct drm_display_mode 
> > *mode1,
> >   DRM_MODE_MATCH_TIMINGS |
> >   DRM_MODE_MATCH_CLOCK |
> >   DRM_MODE_MATCH_FLAGS |
> > - DRM_MODE_MATCH_3D_FLAGS);
> > + DRM_MODE_MATCH_3D_FLAGS|
> > + 

Re: [Intel-gfx] [PATCH] drm/i915/psr: vbt change for psr

[Rodrigo Vivi]

On Fri, Apr 06, 2018 at 10:58:51PM +0530, vathsala nagaraju wrote:
> From: Vathsala Nagaraju 
> 
> For psr block #9, the vbt description has moved to options [0-3] for
> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
> structure. Since spec does not  mention from which VBT version this
> change was added to vbt.bsf file, we cannot depend on bdb->version check
> to change for all the platforms.
> 
> There is RCR inplace for GOP team to  provide the version number
> to make generic change. Since Kabylake with bdb version 209 is having this
> change, limiting this change to kbl and version 209+ to unblock google.
> 
> bspec 20131
> 
> Cc: Rodrigo Vivi 
> CC: Puthikorn Voravootivat 
> 
> Signed-off-by: Maulik V Vaghela 
> Signed-off-by: Vathsala Nagaraju 
> ---
>  drivers/gpu/drm/i915/i915_drv.h   |  1 +
>  drivers/gpu/drm/i915/intel_bios.c |  2 +-
>  drivers/gpu/drm/i915/intel_psr.c  | 84 
> ++-
>  3 files changed, 59 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5373b17..a47be19b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1075,6 +1075,7 @@ struct intel_vbt_data {
>   enum psr_lines_to_wait lines_to_wait;
>   int tp1_wakeup_time;
>   int tp2_tp3_wakeup_time;
> + int bdb_version;

please keep the vbt stuff inside intel_bios.c

so there at intel_bios.c you parse the vbt and based on the vbt version
you export in a standard way to intel_psr.c

>   } psr;
>  
>   struct {
> diff --git a/drivers/gpu/drm/i915/intel_bios.c 
> b/drivers/gpu/drm/i915/intel_bios.c
> index c5c7530..cfefd32 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -658,7 +658,7 @@ static int intel_bios_ssc_frequency(struct 
> drm_i915_private *dev_priv,
>   DRM_DEBUG_KMS("No PSR BDB found.\n");
>   return;
>   }
> -
> + dev_priv->vbt.psr.bdb_version = bdb->version;
>   psr_table = >psr_table[panel_type];
>  
>   dev_priv->vbt.psr.full_link = psr_table->full_link;
> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> b/drivers/gpu/drm/i915/intel_psr.c
> index 2d53f73..e470d5e 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -353,24 +353,45 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>   if (dev_priv->psr.link_standby)
>   val |= EDP_PSR_LINK_STANDBY;
>  
> - if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> - val |= EDP_PSR_TP1_TIME_2500us;
> - else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> - val |= EDP_PSR_TP1_TIME_500us;
> - else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
> - val |= EDP_PSR_TP1_TIME_100us;
> - else
> - val |= EDP_PSR_TP1_TIME_0us;
> -
> - if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> - val |= EDP_PSR_TP2_TP3_TIME_2500us;
> - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> - val |= EDP_PSR_TP2_TP3_TIME_500us;
> - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> - val |= EDP_PSR_TP2_TP3_TIME_100us;
> - else
> - val |= EDP_PSR_TP2_TP3_TIME_0us;
> + if (dev_priv->vbt.psr.bdb_version >= 209 && IS_KABYLAKE(dev_priv)) {
> + if (dev_priv->vbt.psr.tp1_wakeup_time == 0)
> + val |= EDP_PSR_TP1_TIME_500us;
> + else if (dev_priv->vbt.psr.tp1_wakeup_time == 1)
> + val |= EDP_PSR_TP1_TIME_100us;
> + else if (dev_priv->vbt.psr.tp1_wakeup_time == 2)
> + val |= EDP_PSR_TP1_TIME_2500us;
> + else
> + val |= EDP_PSR_TP1_TIME_0us;
> + } else {
> + if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> + val |= EDP_PSR_TP1_TIME_2500us;
> + else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> + val |= EDP_PSR_TP1_TIME_500us;
> + else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
> + val |= EDP_PSR_TP1_TIME_100us;
> + else
> + val |= EDP_PSR_TP1_TIME_0us;
> + }
>  
> + if (dev_priv->vbt.psr.bdb_version >= 209 && IS_KABYLAKE(dev_priv)) {
> + if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
> + val |=  EDP_PSR_TP2_TP3_TIME_500us;
> + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
> + val |= EDP_PSR_TP2_TP3_TIME_100us;
> + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
> + val |= EDP_PSR_TP2_TP3_TIME_2500us;
> + else
> + val |= EDP_PSR_TP2_TP3_TIME_0us;
> + } else {
> + if 

[Intel-gfx] ✓ Fi.CI.BAT: success for Aspect ratio support in DRM layer (rev2)

[Patchwork]

== Series Details ==

Series: Aspect ratio support in DRM layer (rev2)
URL   : https://patchwork.freedesktop.org/series/39960/
State : success

== Summary ==

Series 39960v2 Aspect ratio support in DRM layer
https://patchwork.freedesktop.org/api/1.0/series/39960/revisions/2/mbox/

 Possible new issues:

Test drv_module_reload:
Subgroup basic-no-display:
incomplete -> PASS   (fi-elk-e7500)

 Known issues:

Test kms_chamelium:
Subgroup dp-crc-fast:
pass   -> DMESG-FAIL (fi-kbl-7500u) fdo#105589
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713
Subgroup suspend-read-crc-pipe-c:
incomplete -> PASS   (fi-bxt-dsi) fdo#103927

fdo#105589 https://bugs.freedesktop.org/show_bug.cgi?id=105589
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:429s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:440s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:381s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:542s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:298s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:513s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:518s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:527s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:508s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:412s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:559s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:511s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:583s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:424s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:313s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:545s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:491s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:404s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:422s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:473s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:432s
fi-kbl-7500u total:285  pass:259  dwarn:1   dfail:1   fail:0   skip:24  
time:474s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:463s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:510s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:657s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:441s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:538s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:504s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:501s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:433s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:443s
fi-snb-2520m total:242  pass:208  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:407s

3cbdbfb1ecc8769c8db88e95b1d6ea55c5e87dbf drm-tip: 2018y-04m-06d-15h-15m-21s UTC 
integration manifest
41ab2195ed81 drm: Add and handle new aspect ratios in DRM layer
dc1b0391df73 drm: Add aspect ratio parsing in DRM layer
3fcc37ccf3df drm: Expose modes with aspect ratio, only if requested
03deca3a8769 drm: Handle aspect ratio info in legacy and atomic modeset paths
7044f8820325 drm: Add helper functions to handle aspect-ratio flag bits
73fd1b48e332 drm: Add DRM client cap for aspect-ratio
bb7278472467 video/hdmi: Reject illegal picture aspect ratios
43c4528f5758 drm/edid: Don't send bogus aspect ratios in AVI infoframes
7814e2b10e68 drm/edid: Fix cea mode aspect ratio handling
c8c80aa31122 drm/edid: Use drm_mode_match_no_clocks_no_stereo() for consistentcy
e9fb8279cbaa drm/modes: Introduce drm_mode_match()

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8625/issues.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Split out parking from the idle worker for reuse

[Patchwork]

== Series Details ==

Series: drm/i915: Split out parking from the idle worker for reuse
URL   : https://patchwork.freedesktop.org/series/41278/
State : success

== Summary ==

 Known issues:

Test kms_flip:
Subgroup 2x-dpms-vs-vblank-race-interruptible:
pass   -> FAIL   (shard-hsw) fdo#103060
Subgroup 2x-flip-vs-absolute-wf_vblank-interruptible:
fail   -> PASS   (shard-hsw) fdo#100368 +2

fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368

shard-apltotal:2680 pass:1836 dwarn:1   dfail:0   fail:7   skip:836 
time:12678s
shard-hswtotal:2680 pass:1783 dwarn:1   dfail:0   fail:4   skip:891 
time:11348s
shard-snbtotal:2680 pass:1378 dwarn:1   dfail:0   fail:2   skip:1299 
time:6890s
Blacklisted hosts:
shard-kbltotal:2680 pass:1936 dwarn:27  dfail:0   fail:7   skip:710 
time:8994s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8622/shards.html
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[Intel-gfx] [PATCH] drm/i915/psr: vbt change for psr

[vathsala nagaraju]

From: Vathsala Nagaraju 

For psr block #9, the vbt description has moved to options [0-3] for
TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
structure. Since spec does not  mention from which VBT version this
change was added to vbt.bsf file, we cannot depend on bdb->version check
to change for all the platforms.

There is RCR inplace for GOP team to  provide the version number
to make generic change. Since Kabylake with bdb version 209 is having this
change, limiting this change to kbl and version 209+ to unblock google.

bspec 20131

Cc: Rodrigo Vivi 
CC: Puthikorn Voravootivat 

Signed-off-by: Maulik V Vaghela 
Signed-off-by: Vathsala Nagaraju 
---
 drivers/gpu/drm/i915/i915_drv.h   |  1 +
 drivers/gpu/drm/i915/intel_bios.c |  2 +-
 drivers/gpu/drm/i915/intel_psr.c  | 84 ++-
 3 files changed, 59 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5373b17..a47be19b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1075,6 +1075,7 @@ struct intel_vbt_data {
enum psr_lines_to_wait lines_to_wait;
int tp1_wakeup_time;
int tp2_tp3_wakeup_time;
+   int bdb_version;
} psr;
 
struct {
diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index c5c7530..cfefd32 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -658,7 +658,7 @@ static int intel_bios_ssc_frequency(struct drm_i915_private 
*dev_priv,
DRM_DEBUG_KMS("No PSR BDB found.\n");
return;
}
-
+   dev_priv->vbt.psr.bdb_version = bdb->version;
psr_table = >psr_table[panel_type];
 
dev_priv->vbt.psr.full_link = psr_table->full_link;
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2d53f73..e470d5e 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -353,24 +353,45 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
if (dev_priv->psr.link_standby)
val |= EDP_PSR_LINK_STANDBY;
 
-   if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
-   val |= EDP_PSR_TP1_TIME_2500us;
-   else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
-   val |= EDP_PSR_TP1_TIME_500us;
-   else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
-   val |= EDP_PSR_TP1_TIME_100us;
-   else
-   val |= EDP_PSR_TP1_TIME_0us;
-
-   if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-   val |= EDP_PSR_TP2_TP3_TIME_2500us;
-   else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-   val |= EDP_PSR_TP2_TP3_TIME_500us;
-   else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
-   val |= EDP_PSR_TP2_TP3_TIME_100us;
-   else
-   val |= EDP_PSR_TP2_TP3_TIME_0us;
+   if (dev_priv->vbt.psr.bdb_version >= 209 && IS_KABYLAKE(dev_priv)) {
+   if (dev_priv->vbt.psr.tp1_wakeup_time == 0)
+   val |= EDP_PSR_TP1_TIME_500us;
+   else if (dev_priv->vbt.psr.tp1_wakeup_time == 1)
+   val |= EDP_PSR_TP1_TIME_100us;
+   else if (dev_priv->vbt.psr.tp1_wakeup_time == 2)
+   val |= EDP_PSR_TP1_TIME_2500us;
+   else
+   val |= EDP_PSR_TP1_TIME_0us;
+   } else {
+   if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
+   val |= EDP_PSR_TP1_TIME_2500us;
+   else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
+   val |= EDP_PSR_TP1_TIME_500us;
+   else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
+   val |= EDP_PSR_TP1_TIME_100us;
+   else
+   val |= EDP_PSR_TP1_TIME_0us;
+   }
 
+   if (dev_priv->vbt.psr.bdb_version >= 209 && IS_KABYLAKE(dev_priv)) {
+   if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
+   val |=  EDP_PSR_TP2_TP3_TIME_500us;
+   else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
+   val |= EDP_PSR_TP2_TP3_TIME_100us;
+   else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
+   val |= EDP_PSR_TP2_TP3_TIME_2500us;
+   else
+   val |= EDP_PSR_TP2_TP3_TIME_0us;
+   } else {
+   if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
+   val |= EDP_PSR_TP2_TP3_TIME_2500us;
+   else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
+   val |= EDP_PSR_TP2_TP3_TIME_500us;
+   else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
+   val |= 

Re: [Intel-gfx] [PATCH v10 10/11] drm: Add aspect ratio parsing in DRM layer

[Nautiyal, Ankit K]

This patch is causing failure of IGT test kms_3d. The kms_3d test 
expects the no. of 3d modes to be 13.


(The test has hard-coded value for expected no. of 3d modes as 13)

But due to the addition of "matching aspect_ratio" in drm_mode_equal in 
this patch, the total no. of


modes in the connector modelist is increased by 2, resulting in failure 
of assertion 'mode_count==13'.


Perhaps this need to be handled in the test.

-Regards,

Ankit


On 4/6/2018 10:34 PM, Nautiyal, Ankit K wrote:

From: "Sharma, Shashank" 

Current DRM layer functions don't parse aspect ratio information
while converting a user mode->kernel mode or vice versa. This
causes modeset to pick mode with wrong aspect ratio, eventually
causing failures in HDMI compliance test cases, due to wrong VIC.

This patch adds aspect ratio information in DRM's mode conversion
and mode comparision functions, to make sure kernel picks mode
with right aspect ratio (as per the VIC).

Background:
This patch was once reviewed and merged, and later reverted due to
lack of DRM cap protection. This is a re-spin of this patch, this
time with DRM cap protection, to avoid aspect ratio information, when
the client doesn't request for it.

Review link: https://pw-emeril.freedesktop.org/patch/104068/
Background discussion: https://patchwork.kernel.org/patch/9379057/

Signed-off-by: Shashank Sharma 
Signed-off-by: Lin, Jia 
Signed-off-by: Akashdeep Sharma 
Reviewed-by: Jim Bride  (V2)
Reviewed-by: Jose Abreu  (V4)

Cc: Ville Syrjala 
Cc: Jim Bride 
Cc: Jose Abreu 
Cc: Ankit Nautiyal 

V3: modified the aspect-ratio check in drm_mode_equal as per new flags
 provided by Ville. https://patchwork.freedesktop.org/patch/188043/
V4: rebase
V5: rebase
V6: As recommended by Ville, avoided matching of aspect-ratio in
 drm_fb_helper, while trying to find a common mode among connectors
 for the target clone mode.
V7: rebase
V8: rebase
V9: rebase
V10: rebase
---
  drivers/gpu/drm/drm_fb_helper.c | 12 ++--
  drivers/gpu/drm/drm_modes.c | 35 ++-
  2 files changed, 44 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 0646b10..2ee1eaa 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -2183,7 +2183,11 @@ static bool drm_target_cloned(struct drm_fb_helper 
*fb_helper,
for (j = 0; j < i; j++) {
if (!enabled[j])
continue;
-   if (!drm_mode_equal(modes[j], modes[i]))
+   if (!drm_mode_match(modes[j], modes[i],
+   DRM_MODE_MATCH_TIMINGS |
+   DRM_MODE_MATCH_CLOCK |
+   DRM_MODE_MATCH_FLAGS |
+   DRM_MODE_MATCH_3D_FLAGS))
can_clone = false;
}
}
@@ -2203,7 +2207,11 @@ static bool drm_target_cloned(struct drm_fb_helper 
*fb_helper,
  
  		fb_helper_conn = fb_helper->connector_info[i];

list_for_each_entry(mode, _helper_conn->connector->modes, 
head) {
-   if (drm_mode_equal(mode, dmt_mode))
+   if (drm_mode_match(mode, dmt_mode,
+  DRM_MODE_MATCH_TIMINGS |
+  DRM_MODE_MATCH_CLOCK |
+  DRM_MODE_MATCH_FLAGS |
+  DRM_MODE_MATCH_3D_FLAGS))
modes[i] = mode;
}
if (!modes[i])
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index d6133e8..454f2ff 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -1049,7 +1049,8 @@ bool drm_mode_equal(const struct drm_display_mode *mode1,
  DRM_MODE_MATCH_TIMINGS |
  DRM_MODE_MATCH_CLOCK |
  DRM_MODE_MATCH_FLAGS |
- DRM_MODE_MATCH_3D_FLAGS);
+ DRM_MODE_MATCH_3D_FLAGS|
+ DRM_MODE_MATCH_ASPECT_RATIO);
  }
  EXPORT_SYMBOL(drm_mode_equal);
  
@@ -1647,6 +1648,20 @@ void drm_mode_convert_to_umode(struct drm_mode_modeinfo *out,

out->vrefresh = in->vrefresh;
out->flags = in->flags;
out->type = in->type;
+
+   switch (in->picture_aspect_ratio) {
+   case HDMI_PICTURE_ASPECT_4_3:
+   out->flags |= DRM_MODE_FLAG_PIC_AR_4_3;
+   break;
+   case HDMI_PICTURE_ASPECT_16_9:
+   

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Aspect ratio support in DRM layer (rev2)

[Patchwork]

== Series Details ==

Series: Aspect ratio support in DRM layer (rev2)
URL   : https://patchwork.freedesktop.org/series/39960/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
e9fb8279cbaa drm/modes: Introduce drm_mode_match()
-:39: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#39: FILE: drivers/gpu/drm/drm_modes.c:958:
+static bool drm_mode_match_clock(const struct drm_display_mode *mode1,
+ const struct drm_display_mode *mode2)

total: 0 errors, 0 warnings, 1 checks, 190 lines checked
c8c80aa31122 drm/edid: Use drm_mode_match_no_clocks_no_stereo() for consistentcy
7814e2b10e68 drm/edid: Fix cea mode aspect ratio handling
43c4528f5758 drm/edid: Don't send bogus aspect ratios in AVI infoframes
bb7278472467 video/hdmi: Reject illegal picture aspect ratios
73fd1b48e332 drm: Add DRM client cap for aspect-ratio
7044f8820325 drm: Add helper functions to handle aspect-ratio flag bits
03deca3a8769 drm: Handle aspect ratio info in legacy and atomic modeset paths
-:77: CHECK:SPACING: No space is necessary after a cast
#77: FILE: drivers/gpu/drm/drm_atomic.c:399:
+   u_mode = (struct drm_mode_modeinfo *) blob->data;

total: 0 errors, 0 warnings, 1 checks, 185 lines checked
3fcc37ccf3df drm: Expose modes with aspect ratio, only if requested
dc1b0391df73 drm: Add aspect ratio parsing in DRM layer
-:86: CHECK:SPACING: space preferred before that '|' (ctx:VxE)
#86: FILE: drivers/gpu/drm/drm_modes.c:1052:
+ DRM_MODE_MATCH_3D_FLAGS|
 ^

total: 0 errors, 0 warnings, 1 checks, 77 lines checked
41ab2195ed81 drm: Add and handle new aspect ratios in DRM layer
-:89: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#89: FILE: include/uapi/drm/drm_mode.h:108:
+   (DRM_MODE_PICTURE_ASPECT_64_27<<19)
  ^

-:91: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#91: FILE: include/uapi/drm/drm_mode.h:110:
+   (DRM_MODE_PICTURE_ASPECT_256_135<<19)
^

total: 0 errors, 0 warnings, 2 checks, 42 lines checked

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Split out parking from the idle worker for reuse (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Split out parking from the idle worker for reuse (rev2)
URL   : https://patchwork.freedesktop.org/series/41278/
State : success

== Summary ==

Series 41278v2 drm/i915: Split out parking from the idle worker for reuse
https://patchwork.freedesktop.org/api/1.0/series/41278/revisions/2/mbox/

 Possible new issues:

Test drv_module_reload:
Subgroup basic-no-display:
incomplete -> PASS   (fi-elk-e7500)

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:429s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:444s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:380s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:538s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:297s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:516s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:518s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:506s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:411s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:559s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:512s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:589s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:420s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:316s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:540s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:486s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:405s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:421s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:477s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:435s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:472s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:464s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:511s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:642s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:441s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:538s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:504s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:500s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:430s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:446s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:578s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:403s

3cbdbfb1ecc8769c8db88e95b1d6ea55c5e87dbf drm-tip: 2018y-04m-06d-15h-15m-21s UTC 
integration manifest
1a10dad9eb99 drm/i915: Split out parking from the idle worker for reuse

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8624/issues.html
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[Intel-gfx] [PATCH v10 09/11] drm: Expose modes with aspect ratio, only if requested

[Nautiyal, Ankit K]

From: Ankit Nautiyal 

We parse the EDID and add all the modes in the connector's modelist.
This adds CEA modes with aspect ratio information too, regadless of
whether user space requested this information or not.

This patch prunes the modes with aspect-ratio information, from a
connector's modelist, if the user-space has not set the aspect ratio
DRM client cap.

Cc: Ville Syrjala 
Cc: Shashank Sharma 
Cc: Jose Abreu 

Signed-off-by: Ankit Nautiyal 

V3: As suggested by Ville, modified the mechanism of pruning of modes
with aspect-ratio, if the aspect-ratio is not supported. Instead
of straight away pruning such a mode, the mode is retained with
aspect ratio bits set to zero, provided it is unique.
V4: rebase
V5: Addressed review comments from Ville:
-used a pointer to store last valid mode.
-avoided, modifying of picture_aspect_ratio in kernel mode,
 instead only flags bits of user mode are reset (if aspect-ratio
 is not supported).
V6: As suggested by Ville, corrected the mode pruning logic and
elaborated the mode pruning logic and the assumptions taken.
V7: rebase
V8: rebase
V9: rebase
V10: rebase
---
 drivers/gpu/drm/drm_connector.c | 40 
 1 file changed, 36 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index b3cde89..5420325 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1531,8 +1531,10 @@ static struct drm_encoder 
*drm_connector_get_encoder(struct drm_connector *conne
return connector->encoder;
 }
 
-static bool drm_mode_expose_to_userspace(const struct drm_display_mode *mode,
-const struct drm_file *file_priv)
+static bool
+drm_mode_expose_to_userspace(const struct drm_display_mode *mode,
+const struct drm_display_mode *last_mode,
+const struct drm_file *file_priv)
 {
/*
 * If user-space hasn't configured the driver to expose the stereo 3D
@@ -1540,6 +1542,26 @@ static bool drm_mode_expose_to_userspace(const struct 
drm_display_mode *mode,
 */
if (!file_priv->stereo_allowed && drm_mode_is_stereo(mode))
return false;
+   /*
+* If user-space hasn't configured the driver to expose the modes with
+* aspect-ratio, don't expose them. But in case of a unique mode, let
+* the mode be passed, so that it can be enumerated with aspect-ratio
+* bits erased.
+*
+* It is assumed here, that the list of modes for a given connector, is
+* sorted, such that modes that have different aspect-ratios, but are
+* otherwise identical, are back to back.
+* This way, saving the last valid mode, and matching it with the
+* current mode will help in determining, if the current mode is unique.
+*/
+   if (!file_priv->aspect_ratio_allowed &&
+   mode->picture_aspect_ratio != HDMI_PICTURE_ASPECT_NONE &&
+   last_mode && drm_mode_match(mode, last_mode,
+   DRM_MODE_MATCH_TIMINGS |
+   DRM_MODE_MATCH_CLOCK |
+   DRM_MODE_MATCH_FLAGS |
+   DRM_MODE_MATCH_3D_FLAGS))
+   return false;
 
return true;
 }
@@ -1551,6 +1573,7 @@ int drm_mode_getconnector(struct drm_device *dev, void 
*data,
struct drm_connector *connector;
struct drm_encoder *encoder;
struct drm_display_mode *mode;
+   struct drm_display_mode *last_valid_mode;
int mode_count = 0;
int encoders_count = 0;
int ret = 0;
@@ -1606,9 +1629,13 @@ int drm_mode_getconnector(struct drm_device *dev, void 
*data,
out_resp->connection = connector->status;
 
/* delayed so we get modes regardless of pre-fill_modes state */
+   last_valid_mode = NULL;
list_for_each_entry(mode, >modes, head)
-   if (drm_mode_expose_to_userspace(mode, file_priv))
+   if (drm_mode_expose_to_userspace(mode, last_valid_mode,
+file_priv)) {
mode_count++;
+   last_valid_mode = mode;
+   }
 
/*
 * This ioctl is called twice, once to determine how much space is
@@ -1617,11 +1644,15 @@ int drm_mode_getconnector(struct drm_device *dev, void 
*data,
if ((out_resp->count_modes >= mode_count) && mode_count) {
copied = 0;
mode_ptr = (struct drm_mode_modeinfo __user *)(unsigned 
long)out_resp->modes_ptr;
+   last_valid_mode = NULL;
list_for_each_entry(mode, >modes, head) {
-   if 

[Intel-gfx] [PATCH v10 11/11] drm: Add and handle new aspect ratios in DRM layer

[Nautiyal, Ankit K]

From: "Sharma, Shashank" 

HDMI 2.0/CEA-861-F introduces two new aspect ratios:
- 64:27
- 256:135

This patch:
-  Adds new DRM flags for to represent these new aspect ratios.
-  Adds new cases to handle these aspect ratios while converting
from user->kernel mode or vise versa.

This patch was once reviewed and merged, and later reverted due
to lack of DRM client protection, while adding aspect ratio bits
in user modes. This is a re-spin of the series, with DRM client
cap protection.

The previous series can be found here:
https://pw-emeril.freedesktop.org/series/10850/

Signed-off-by: Shashank Sharma 
Reviewed-by: Sean Paul  (V2)
Reviewed-by: Jose Abreu  (V2)

Cc: Ville Syrjala 
Cc: Sean Paul 
Cc: Jose Abreu 
Cc: Ankit Nautiyal 

V3: rebase
V4: rebase
V5: corrected the macro name for an aspect ratio, in a switch case.
V6: rebase
V7: rebase
V8: rebase
V9: rebase
V10: rebase
---
 drivers/gpu/drm/drm_modes.c | 12 
 include/uapi/drm/drm_mode.h |  6 ++
 2 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 454f2ff..21cc84b 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -1656,6 +1656,12 @@ void drm_mode_convert_to_umode(struct drm_mode_modeinfo 
*out,
case HDMI_PICTURE_ASPECT_16_9:
out->flags |= DRM_MODE_FLAG_PIC_AR_16_9;
break;
+   case HDMI_PICTURE_ASPECT_64_27:
+   out->flags |= DRM_MODE_FLAG_PIC_AR_64_27;
+   break;
+   case HDMI_PICTURE_ASPECT_256_135:
+   out->flags |= DRM_MODE_FLAG_PIC_AR_256_135;
+   break;
case HDMI_PICTURE_ASPECT_RESERVED:
default:
out->flags |= DRM_MODE_FLAG_PIC_AR_NONE;
@@ -1721,6 +1727,12 @@ int drm_mode_convert_umode(struct drm_device *dev,
case DRM_MODE_FLAG_PIC_AR_16_9:
out->picture_aspect_ratio |= HDMI_PICTURE_ASPECT_16_9;
break;
+   case DRM_MODE_FLAG_PIC_AR_64_27:
+   out->picture_aspect_ratio |= HDMI_PICTURE_ASPECT_64_27;
+   break;
+   case DRM_MODE_FLAG_PIC_AR_256_135:
+   out->picture_aspect_ratio |= HDMI_PICTURE_ASPECT_256_135;
+   break;
default:
out->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
break;
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 50bcf42..4b3a1bb 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -93,6 +93,8 @@ extern "C" {
 #define DRM_MODE_PICTURE_ASPECT_NONE   0
 #define DRM_MODE_PICTURE_ASPECT_4_31
 #define DRM_MODE_PICTURE_ASPECT_16_9   2
+#define DRM_MODE_PICTURE_ASPECT_64_27  3
+#define DRM_MODE_PICTURE_ASPECT_256_1354
 
 /* Aspect ratio flag bitmask (4 bits 22:19) */
 #define DRM_MODE_FLAG_PIC_AR_MASK  (0x0F<<19)
@@ -102,6 +104,10 @@ extern "C" {
(DRM_MODE_PICTURE_ASPECT_4_3<<19)
 #define  DRM_MODE_FLAG_PIC_AR_16_9 \
(DRM_MODE_PICTURE_ASPECT_16_9<<19)
+#define  DRM_MODE_FLAG_PIC_AR_64_27 \
+   (DRM_MODE_PICTURE_ASPECT_64_27<<19)
+#define  DRM_MODE_FLAG_PIC_AR_256_135 \
+   (DRM_MODE_PICTURE_ASPECT_256_135<<19)
 
 #define  DRM_MODE_FLAG_ALL (DRM_MODE_FLAG_PHSYNC | \
 DRM_MODE_FLAG_NHSYNC | \
-- 
2.7.4

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[Intel-gfx] [PATCH v10 10/11] drm: Add aspect ratio parsing in DRM layer

[Nautiyal, Ankit K]

From: "Sharma, Shashank" 

Current DRM layer functions don't parse aspect ratio information
while converting a user mode->kernel mode or vice versa. This
causes modeset to pick mode with wrong aspect ratio, eventually
causing failures in HDMI compliance test cases, due to wrong VIC.

This patch adds aspect ratio information in DRM's mode conversion
and mode comparision functions, to make sure kernel picks mode
with right aspect ratio (as per the VIC).

Background:
This patch was once reviewed and merged, and later reverted due to
lack of DRM cap protection. This is a re-spin of this patch, this
time with DRM cap protection, to avoid aspect ratio information, when
the client doesn't request for it.

Review link: https://pw-emeril.freedesktop.org/patch/104068/
Background discussion: https://patchwork.kernel.org/patch/9379057/

Signed-off-by: Shashank Sharma 
Signed-off-by: Lin, Jia 
Signed-off-by: Akashdeep Sharma 
Reviewed-by: Jim Bride  (V2)
Reviewed-by: Jose Abreu  (V4)

Cc: Ville Syrjala 
Cc: Jim Bride 
Cc: Jose Abreu 
Cc: Ankit Nautiyal 

V3: modified the aspect-ratio check in drm_mode_equal as per new flags
provided by Ville. https://patchwork.freedesktop.org/patch/188043/
V4: rebase
V5: rebase
V6: As recommended by Ville, avoided matching of aspect-ratio in
drm_fb_helper, while trying to find a common mode among connectors
for the target clone mode.
V7: rebase
V8: rebase
V9: rebase
V10: rebase
---
 drivers/gpu/drm/drm_fb_helper.c | 12 ++--
 drivers/gpu/drm/drm_modes.c | 35 ++-
 2 files changed, 44 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 0646b10..2ee1eaa 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -2183,7 +2183,11 @@ static bool drm_target_cloned(struct drm_fb_helper 
*fb_helper,
for (j = 0; j < i; j++) {
if (!enabled[j])
continue;
-   if (!drm_mode_equal(modes[j], modes[i]))
+   if (!drm_mode_match(modes[j], modes[i],
+   DRM_MODE_MATCH_TIMINGS |
+   DRM_MODE_MATCH_CLOCK |
+   DRM_MODE_MATCH_FLAGS |
+   DRM_MODE_MATCH_3D_FLAGS))
can_clone = false;
}
}
@@ -2203,7 +2207,11 @@ static bool drm_target_cloned(struct drm_fb_helper 
*fb_helper,
 
fb_helper_conn = fb_helper->connector_info[i];
list_for_each_entry(mode, _helper_conn->connector->modes, 
head) {
-   if (drm_mode_equal(mode, dmt_mode))
+   if (drm_mode_match(mode, dmt_mode,
+  DRM_MODE_MATCH_TIMINGS |
+  DRM_MODE_MATCH_CLOCK |
+  DRM_MODE_MATCH_FLAGS |
+  DRM_MODE_MATCH_3D_FLAGS))
modes[i] = mode;
}
if (!modes[i])
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index d6133e8..454f2ff 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -1049,7 +1049,8 @@ bool drm_mode_equal(const struct drm_display_mode *mode1,
  DRM_MODE_MATCH_TIMINGS |
  DRM_MODE_MATCH_CLOCK |
  DRM_MODE_MATCH_FLAGS |
- DRM_MODE_MATCH_3D_FLAGS);
+ DRM_MODE_MATCH_3D_FLAGS|
+ DRM_MODE_MATCH_ASPECT_RATIO);
 }
 EXPORT_SYMBOL(drm_mode_equal);
 
@@ -1647,6 +1648,20 @@ void drm_mode_convert_to_umode(struct drm_mode_modeinfo 
*out,
out->vrefresh = in->vrefresh;
out->flags = in->flags;
out->type = in->type;
+
+   switch (in->picture_aspect_ratio) {
+   case HDMI_PICTURE_ASPECT_4_3:
+   out->flags |= DRM_MODE_FLAG_PIC_AR_4_3;
+   break;
+   case HDMI_PICTURE_ASPECT_16_9:
+   out->flags |= DRM_MODE_FLAG_PIC_AR_16_9;
+   break;
+   case HDMI_PICTURE_ASPECT_RESERVED:
+   default:
+   out->flags |= DRM_MODE_FLAG_PIC_AR_NONE;
+   break;
+   }
+
strncpy(out->name, in->name, DRM_DISPLAY_MODE_LEN);
out->name[DRM_DISPLAY_MODE_LEN-1] = 0;
 }
@@ -1693,6 +1708,24 @@ int drm_mode_convert_umode(struct drm_device *dev,
strncpy(out->name, in->name, DRM_DISPLAY_MODE_LEN);

[Intel-gfx] [PATCH v10 05/11] video/hdmi: Reject illegal picture aspect ratios

[Nautiyal, Ankit K]

From: Ville Syrjälä 

AVI infoframe can only carry none, 4:3, or 16:9 picture aspect
ratios. Return an error if the user asked for something different.

Cc: Shashank Sharma 
Cc: "Lin, Jia" 
Cc: Akashdeep Sharma 
Cc: Jim Bride 
Cc: Jose Abreu 
Cc: Daniel Vetter 
Cc: Emil Velikov 
Cc: Thierry Reding 
Cc: Hans Verkuil 
Cc: linux-me...@vger.kernel.org
Signed-off-by: Ville Syrjälä 
Reviewed-by: Jose Abreu 
---
 drivers/video/hdmi.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 111a0ab..38716eb5 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -93,6 +93,9 @@ ssize_t hdmi_avi_infoframe_pack(struct hdmi_avi_infoframe 
*frame, void *buffer,
if (size < length)
return -ENOSPC;
 
+   if (frame->picture_aspect > HDMI_PICTURE_ASPECT_16_9)
+   return -EINVAL;
+
memset(buffer, 0, size);
 
ptr[0] = frame->type;
-- 
2.7.4

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[Intel-gfx] [PATCH v10 07/11] drm: Add helper functions to handle aspect-ratio flag bits

[Nautiyal, Ankit K]

From: Ankit Nautiyal 

This patch adds helper functions for determining if aspect-ratio is
expected in user-mode and for allowing/disallowing the aspect-ratio,
if its not expected.

Signed-off-by: Ankit Nautiyal 
---
 drivers/gpu/drm/drm_modes.c | 47 +
 include/drm/drm_modes.h |  4 
 2 files changed, 51 insertions(+)

diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index c395a24..d6133e8 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -1759,3 +1759,50 @@ bool drm_mode_is_420(const struct drm_display_info 
*display,
drm_mode_is_420_also(display, mode);
 }
 EXPORT_SYMBOL(drm_mode_is_420);
+
+/**
+ * drm_mode_aspect_ratio_allowed - checks if the aspect-ratio information
+ * is expected from the user-mode.
+ *
+ * If the user has set aspect-ratio cap, then the flag of the user-mode is
+ * allowed to contain aspect-ratio value.
+ * If the user does not set aspect-ratio cap, then the only value allowed in 
the
+ * flags bits is aspect-ratio NONE.
+ *
+ * @file_priv: file private structure to get the user capabilities
+ * @umode: drm_mode_modeinfo struct, whose flag carry the aspect ratio
+ * information.
+ *
+ * Returns:
+ * true if the aspect-ratio info is allowed in the user-mode flags.
+ * false, otherwise.
+ */
+bool
+drm_mode_aspect_ratio_allowed(const struct drm_file *file_priv,
+ struct drm_mode_modeinfo *umode)
+{
+   return file_priv->aspect_ratio_allowed || (umode->flags &
+   DRM_MODE_FLAG_PIC_AR_MASK) == DRM_MODE_FLAG_PIC_AR_NONE;
+}
+EXPORT_SYMBOL(drm_mode_aspect_ratio_allowed);
+
+/**
+ * drm_mode_filter_aspect_ratio_flags - filters the aspect-ratio bits in the
+ * user-mode flags.
+ *
+ * Checks if the aspect-ratio information is allowed. Resets the aspect-ratio
+ * bits in the user-mode flags, if aspect-ratio info is not allowed.
+ *
+ * @file_priv: file private structure to get the user capabilities.
+ * @umode: drm_mode_modeinfo struct, whose flags' aspect-ratio bits needs to
+ * be filtered.
+ *
+ */
+void
+drm_mode_filter_aspect_ratio_flags(const struct drm_file *file_priv,
+  struct drm_mode_modeinfo *umode)
+{
+   if (!drm_mode_aspect_ratio_allowed(file_priv, umode))
+   umode->flags &= ~DRM_MODE_FLAG_PIC_AR_MASK;
+}
+EXPORT_SYMBOL(drm_mode_filter_aspect_ratio_flags);
diff --git a/include/drm/drm_modes.h b/include/drm/drm_modes.h
index 2f78b7e..e0b060d 100644
--- a/include/drm/drm_modes.h
+++ b/include/drm/drm_modes.h
@@ -461,6 +461,10 @@ bool drm_mode_is_420_also(const struct drm_display_info 
*display,
  const struct drm_display_mode *mode);
 bool drm_mode_is_420(const struct drm_display_info *display,
 const struct drm_display_mode *mode);
+bool drm_mode_aspect_ratio_allowed(const struct drm_file *file_priv,
+  struct drm_mode_modeinfo *umode);
+void drm_mode_filter_aspect_ratio_flags(const struct drm_file *file_priv,
+   struct drm_mode_modeinfo *umode);
 
 struct drm_display_mode *drm_cvt_mode(struct drm_device *dev,
  int hdisplay, int vdisplay, int vrefresh,
-- 
2.7.4

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[Intel-gfx] [PATCH v10 03/11] drm/edid: Fix cea mode aspect ratio handling

[Nautiyal, Ankit K]

From: Ville Syrjälä 

commit 6dffd431e229 ("drm: Add aspect ratio parsing in DRM layer")
cause us to not send out any VICs in the AVI infoframes. That commit
was since reverted, but if and when we add aspect ratio handing back
we need to be more careful.

Let's handle this by considering the aspect ratio as a requirement
for cea mode matching only if the passed in mode actually has a
non-zero aspect ratio field. This will keep userspace that doesn't
provide an aspect ratio working as before by matching it to the
first otherwise equal cea mode. And once userspace starts to
provide the aspect ratio it will be considerd a hard requirement
for the match.

Also change the hdmi mode matching to use drm_mode_match() for
consistency, but we don't match on aspect ratio there since the
spec doesn't list a specific aspect ratio for those modes.

Cc: Shashank Sharma 
Cc: "Lin, Jia" 
Cc: Akashdeep Sharma 
Cc: Jim Bride 
Cc: Jose Abreu 
Cc: Daniel Vetter 
Cc: Emil Velikov 
Signed-off-by: Ville Syrjälä 
Reviewed-by: Shashank Sharma 
---
 drivers/gpu/drm/drm_edid.c | 18 ++
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index c35d3bc..29c88eb 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2930,11 +2930,15 @@ cea_mode_alternate_timings(u8 vic, struct 
drm_display_mode *mode)
 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode 
*to_match,
 unsigned int clock_tolerance)
 {
+   unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | 
DRM_MODE_MATCH_FLAGS;
u8 vic;
 
if (!to_match->clock)
return 0;
 
+   if (to_match->picture_aspect_ratio)
+   match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
+
for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
struct drm_display_mode cea_mode = edid_cea_modes[vic];
unsigned int clock1, clock2;
@@ -2948,7 +2952,7 @@ static u8 drm_match_cea_mode_clock_tolerance(const struct 
drm_display_mode *to_m
continue;
 
do {
-   if (drm_mode_equal_no_clocks_no_stereo(to_match, 
_mode))
+   if (drm_mode_match(to_match, _mode, match_flags))
return vic;
} while (cea_mode_alternate_timings(vic, _mode));
}
@@ -2965,11 +2969,15 @@ static u8 drm_match_cea_mode_clock_tolerance(const 
struct drm_display_mode *to_m
  */
 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
 {
+   unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | 
DRM_MODE_MATCH_FLAGS;
u8 vic;
 
if (!to_match->clock)
return 0;
 
+   if (to_match->picture_aspect_ratio)
+   match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
+
for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
struct drm_display_mode cea_mode = edid_cea_modes[vic];
unsigned int clock1, clock2;
@@ -2983,7 +2991,7 @@ u8 drm_match_cea_mode(const struct drm_display_mode 
*to_match)
continue;
 
do {
-   if (drm_mode_equal_no_clocks_no_stereo(to_match, 
_mode))
+   if (drm_mode_match(to_match, _mode, match_flags))
return vic;
} while (cea_mode_alternate_timings(vic, _mode));
}
@@ -3030,6 +3038,7 @@ hdmi_mode_alternate_clock(const struct drm_display_mode 
*hdmi_mode)
 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode 
*to_match,
  unsigned int clock_tolerance)
 {
+   unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | 
DRM_MODE_MATCH_FLAGS;
u8 vic;
 
if (!to_match->clock)
@@ -3047,7 +3056,7 @@ static u8 drm_match_hdmi_mode_clock_tolerance(const 
struct drm_display_mode *to_
abs(to_match->clock - clock2) > clock_tolerance)
continue;
 
-   if (drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
+   if (drm_mode_match(to_match, hdmi_mode, match_flags))
return vic;
}
 
@@ -3064,6 +3073,7 @@ static u8 drm_match_hdmi_mode_clock_tolerance(const 
struct drm_display_mode *to_
  */
 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
 {
+   unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | 
DRM_MODE_MATCH_FLAGS;
u8 vic;
 
if (!to_match->clock)
@@ -3079,7 +3089,7 @@ static u8 drm_match_hdmi_mode(const struct 
drm_display_mode *to_match)
 
if 

[Intel-gfx] [PATCH v10 06/11] drm: Add DRM client cap for aspect-ratio

[Nautiyal, Ankit K]

From: Ankit Nautiyal 

To enable aspect-ratio support in DRM, blindly exposing the aspect
ratio information along with mode, can break things in existing
user-spaces which have no intention or support to use this aspect
ratio information.

To avoid this, a new drm client cap is required to enable a
user-space to advertise if it supports modes with aspect-ratio. Based
on this cap value, the kernel will take a call on exposing the aspect
ratio info in modes or not.

This patch adds the client cap for aspect-ratio.

Cc: Ville Syrjala 
Cc: Shashank Sharma 
Signed-off-by: Ankit Nautiyal 

V3: rebase
V4: As suggested by Marteen Lankhorst modified the commit message
explaining the need to use the DRM cap for aspect-ratio. Also,
tweaked the comment lines in the code for better understanding and
clarity, as recommended by Shashank Sharma.
V5: rebase
V6: rebase
V7: rebase
V8: rebase
V9: rebase
V10: added comment explaining that no userspace breaks on aspect-ratio
 mode bits.

Reviewed-by: Shashank Sharma 
---
 drivers/gpu/drm/drm_ioctl.c | 9 +
 include/drm/drm_file.h  | 8 
 include/uapi/drm/drm.h  | 7 +++
 3 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index af78291..39c8eab 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -325,6 +325,15 @@ drm_setclientcap(struct drm_device *dev, void *data, 
struct drm_file *file_priv)
file_priv->atomic = req->value;
file_priv->universal_planes = req->value;
break;
+   case DRM_CLIENT_CAP_ASPECT_RATIO:
+   if (req->value > 1)
+   return -EINVAL;
+   /*
+* No Atomic userspace blows up on aspect ratio mode bits. Checked in
+* wayland/weston, xserver, and hardware-composer modeset paths.
+*/
+   file_priv->aspect_ratio_allowed = req->value;
+   break;
default:
return -EINVAL;
}
diff --git a/include/drm/drm_file.h b/include/drm/drm_file.h
index 5176c37..02b7dde 100644
--- a/include/drm/drm_file.h
+++ b/include/drm/drm_file.h
@@ -182,6 +182,14 @@ struct drm_file {
unsigned atomic:1;
 
/**
+* @aspect_ratio_allowed:
+*
+* True, if client can handle picture aspect ratios, and has requested
+* to pass this information along with the mode.
+*/
+   unsigned aspect_ratio_allowed:1;
+
+   /**
 * @is_master:
 *
 * This client is the creator of @master. Protected by struct
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index 6fdff59..9c660e1 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -680,6 +680,13 @@ struct drm_get_cap {
  */
 #define DRM_CLIENT_CAP_ATOMIC  3
 
+/**
+ * DRM_CLIENT_CAP_ASPECT_RATIO
+ *
+ * If set to 1, the DRM core will provide aspect ratio information in modes.
+ */
+#define DRM_CLIENT_CAP_ASPECT_RATIO4
+
 /** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
 struct drm_set_client_cap {
__u64 capability;
-- 
2.7.4

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[Intel-gfx] [PATCH v10 04/11] drm/edid: Don't send bogus aspect ratios in AVI infoframes

[Nautiyal, Ankit K]

From: Ville Syrjälä 

If the user mode would specify an aspect ratio other than 4:3 or 16:9
we now silently ignore it. Maybe a better apporoach is to return an
error? Let's try that.

Also we must be careful that we don't try to send illegal picture
aspect in the infoframe as it's only capable of signalling none,
4:3, and 16:9. Currently we're sending these bogus infoframes
whenever the cea mode specifies some other aspect ratio.

Cc: Shashank Sharma 
Cc: Sean Paul 
Cc: Jose Abreu 
Cc: Daniel Vetter 
Cc: Emil Velikov 
Signed-off-by: Ville Syrjälä 
Reviewed-by: Shashank Sharma 
---
 drivers/gpu/drm/drm_edid.c | 23 +--
 1 file changed, 17 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 29c88eb..d5757aa 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4840,6 +4840,7 @@ drm_hdmi_avi_infoframe_from_display_mode(struct 
hdmi_avi_infoframe *frame,
 const struct drm_display_mode *mode,
 bool is_hdmi2_sink)
 {
+   enum hdmi_picture_aspect picture_aspect;
int err;
 
if (!frame || !mode)
@@ -4882,13 +4883,23 @@ drm_hdmi_avi_infoframe_from_display_mode(struct 
hdmi_avi_infoframe *frame,
 * Populate picture aspect ratio from either
 * user input (if specified) or from the CEA mode list.
 */
-   if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
-   mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
-   frame->picture_aspect = mode->picture_aspect_ratio;
-   else if (frame->video_code > 0)
-   frame->picture_aspect = drm_get_cea_aspect_ratio(
-   frame->video_code);
+   picture_aspect = mode->picture_aspect_ratio;
+   if (picture_aspect == HDMI_PICTURE_ASPECT_NONE)
+   picture_aspect = drm_get_cea_aspect_ratio(frame->video_code);
 
+   /*
+* The infoframe can't convey anything but none, 4:3
+* and 16:9, so if the user has asked for anything else
+* we can only satisfy it by specifying the right VIC.
+*/
+   if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
+   if (picture_aspect !=
+   drm_get_cea_aspect_ratio(frame->video_code))
+   return -EINVAL;
+   picture_aspect = HDMI_PICTURE_ASPECT_NONE;
+   }
+
+   frame->picture_aspect = picture_aspect;
frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
 
-- 
2.7.4

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[Intel-gfx] [PATCH v10 08/11] drm: Handle aspect ratio info in legacy and atomic modeset paths

[Nautiyal, Ankit K]

From: Ankit Nautiyal 

If the user-space does not support aspect-ratio, and requests for a
modeset with mode having aspect ratio bits set, then the given
user-mode must be rejected. Secondly, while preparing a user-mode from
kernel mode, the aspect-ratio info must not be given, if aspect-ratio
is not supported by the user.

Note: In case, a user-space asks for a video-mode blob, from the
getblob ioctl, the aspect-ratio bits in the video-mode blob are passed
to the user as it is, without any filtering. However, no such case is
present in most of the atomic user-spaces. Currently atomic path of
Xserver, Wayland/weston, Hardware-Composer are checked, and none of
them are using getblob ioctl to get the video-mode blob.

This patch:
1. passes the file_priv structure from the drm_mode_atomic_ioctl till
   the drm_mode_crtc_set_mode_prop, to get the user capability.
2. rejects the modes with aspect-ratio info, during modeset, if the
   user does not support aspect ratio.
3. does not load the aspect-ratio info in user-mode structure, if
   aspect ratio is not supported.

Signed-off-by: Ankit Nautiyal 

V3: Addressed review comments from Ville:
Do not corrupt the current crtc state by updating aspect-ratio on
the fly.
V4: rebase
V5: As suggested by Ville, rejected the modeset calls for modes with
aspect ratio, if the user does not set aspect-ratio cap.
V6: Used the helper functions for determining if aspect-ratio is
expected in the user-mode.
V7: rebase
V8: rebase
V9: rebase
v10: Modified the commit-message
---
 drivers/gpu/drm/drm_atomic.c| 34 +-
 drivers/gpu/drm/drm_atomic_helper.c |  6 +++---
 drivers/gpu/drm/drm_crtc.c  |  8 
 drivers/gpu/drm/drm_crtc_internal.h |  3 ++-
 drivers/gpu/drm/drm_mode_object.c   |  9 ++---
 include/drm/drm_atomic.h|  5 +++--
 6 files changed, 47 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 7d25c42..5863072 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -368,6 +368,7 @@ EXPORT_SYMBOL(drm_atomic_set_mode_for_crtc);
  * drm_atomic_set_mode_prop_for_crtc - set mode for CRTC
  * @state: the CRTC whose incoming state to update
  * @blob: pointer to blob property to use for mode
+ * @file_priv: file priv structure, to get the userspace capabilities
  *
  * Set a mode (originating from a blob property) on the desired CRTC state.
  * This function will take a reference on the blob property for the CRTC state,
@@ -378,7 +379,8 @@ EXPORT_SYMBOL(drm_atomic_set_mode_for_crtc);
  * Zero on success, error code on failure. Cannot return -EDEADLK.
  */
 int drm_atomic_set_mode_prop_for_crtc(struct drm_crtc_state *state,
-  struct drm_property_blob *blob)
+ struct drm_property_blob *blob,
+ struct drm_file *file_priv)
 {
if (blob == state->mode_blob)
return 0;
@@ -389,9 +391,21 @@ int drm_atomic_set_mode_prop_for_crtc(struct 
drm_crtc_state *state,
memset(>mode, 0, sizeof(state->mode));
 
if (blob) {
-   if (blob->length != sizeof(struct drm_mode_modeinfo) ||
-   drm_mode_convert_umode(state->crtc->dev, >mode,
-  blob->data))
+   struct drm_mode_modeinfo *u_mode;
+
+   if (blob->length != sizeof(struct drm_mode_modeinfo))
+   return -EINVAL;
+
+   u_mode = (struct drm_mode_modeinfo *) blob->data;
+   if (!drm_mode_aspect_ratio_allowed(file_priv,
+  u_mode)) {
+   DRM_DEBUG_ATOMIC("Unexpected aspect-ratio flag bits\n");
+   return -EINVAL;
+   }
+
+   if (drm_mode_convert_umode(state->crtc->dev, >mode,
+  (const struct drm_mode_modeinfo *)
+  u_mode))
return -EINVAL;
 
state->mode_blob = drm_property_blob_get(blob);
@@ -471,6 +485,7 @@ drm_atomic_replace_property_blob_from_id(struct drm_device 
*dev,
  * @state: the state object to update with the new property value
  * @property: the property to set
  * @val: the new property value
+ * @file_priv: the file private structure, to get the user capabilities
  *
  * This function handles generic/core properties and calls out to driver's
  * _crtc_funcs.atomic_set_property for driver properties. To ensure
@@ -482,7 +497,7 @@ drm_atomic_replace_property_blob_from_id(struct drm_device 
*dev,
  */
 int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
struct drm_crtc_state *state, struct drm_property *property,
-   uint64_t val)
+   uint64_t val, struct drm_file 

[Intel-gfx] [PATCH v10 01/11] drm/modes: Introduce drm_mode_match()

[Nautiyal, Ankit K]

From: Ville Syrjälä 

Make mode matching less confusing by allowing the caller to specify
which parts of the modes should match via some flags.

Signed-off-by: Ville Syrjälä 
Reviewed-by: Shashank Sharma 
---
 drivers/gpu/drm/drm_modes.c | 134 ++--
 include/drm/drm_modes.h |   9 +++
 2 files changed, 112 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index e82b61e..c395a24 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -939,17 +939,68 @@ struct drm_display_mode *drm_mode_duplicate(struct 
drm_device *dev,
 }
 EXPORT_SYMBOL(drm_mode_duplicate);
 
+static bool drm_mode_match_timings(const struct drm_display_mode *mode1,
+  const struct drm_display_mode *mode2)
+{
+   return mode1->hdisplay == mode2->hdisplay &&
+   mode1->hsync_start == mode2->hsync_start &&
+   mode1->hsync_end == mode2->hsync_end &&
+   mode1->htotal == mode2->htotal &&
+   mode1->hskew == mode2->hskew &&
+   mode1->vdisplay == mode2->vdisplay &&
+   mode1->vsync_start == mode2->vsync_start &&
+   mode1->vsync_end == mode2->vsync_end &&
+   mode1->vtotal == mode2->vtotal &&
+   mode1->vscan == mode2->vscan;
+}
+
+static bool drm_mode_match_clock(const struct drm_display_mode *mode1,
+ const struct drm_display_mode *mode2)
+{
+   /*
+* do clock check convert to PICOS
+* so fb modes get matched the same
+*/
+   if (mode1->clock && mode2->clock)
+   return KHZ2PICOS(mode1->clock) == KHZ2PICOS(mode2->clock);
+   else
+   return mode1->clock == mode2->clock;
+}
+
+static bool drm_mode_match_flags(const struct drm_display_mode *mode1,
+const struct drm_display_mode *mode2)
+{
+   return (mode1->flags & ~DRM_MODE_FLAG_3D_MASK) ==
+   (mode2->flags & ~DRM_MODE_FLAG_3D_MASK);
+}
+
+static bool drm_mode_match_3d_flags(const struct drm_display_mode *mode1,
+   const struct drm_display_mode *mode2)
+{
+   return (mode1->flags & DRM_MODE_FLAG_3D_MASK) ==
+   (mode2->flags & DRM_MODE_FLAG_3D_MASK);
+}
+
+static bool drm_mode_match_aspect_ratio(const struct drm_display_mode *mode1,
+   const struct drm_display_mode *mode2)
+{
+   return mode1->picture_aspect_ratio == mode2->picture_aspect_ratio;
+}
+
 /**
- * drm_mode_equal - test modes for equality
+ * drm_mode_match - test modes for (partial) equality
  * @mode1: first mode
  * @mode2: second mode
+ * @match_flags: which parts need to match (DRM_MODE_MATCH_*)
  *
  * Check to see if @mode1 and @mode2 are equivalent.
  *
  * Returns:
- * True if the modes are equal, false otherwise.
+ * True if the modes are (partially) equal, false otherwise.
  */
-bool drm_mode_equal(const struct drm_display_mode *mode1, const struct 
drm_display_mode *mode2)
+bool drm_mode_match(const struct drm_display_mode *mode1,
+   const struct drm_display_mode *mode2,
+   unsigned int match_flags)
 {
if (!mode1 && !mode2)
return true;
@@ -957,15 +1008,48 @@ bool drm_mode_equal(const struct drm_display_mode 
*mode1, const struct drm_displ
if (!mode1 || !mode2)
return false;
 
-   /* do clock check convert to PICOS so fb modes get matched
-* the same */
-   if (mode1->clock && mode2->clock) {
-   if (KHZ2PICOS(mode1->clock) != KHZ2PICOS(mode2->clock))
-   return false;
-   } else if (mode1->clock != mode2->clock)
+   if (match_flags & DRM_MODE_MATCH_TIMINGS &&
+   !drm_mode_match_timings(mode1, mode2))
return false;
 
-   return drm_mode_equal_no_clocks(mode1, mode2);
+   if (match_flags & DRM_MODE_MATCH_CLOCK &&
+   !drm_mode_match_clock(mode1, mode2))
+   return false;
+
+   if (match_flags & DRM_MODE_MATCH_FLAGS &&
+   !drm_mode_match_flags(mode1, mode2))
+   return false;
+
+   if (match_flags & DRM_MODE_MATCH_3D_FLAGS &&
+   !drm_mode_match_3d_flags(mode1, mode2))
+   return false;
+
+   if (match_flags & DRM_MODE_MATCH_ASPECT_RATIO &&
+   !drm_mode_match_aspect_ratio(mode1, mode2))
+   return false;
+
+   return true;
+}
+EXPORT_SYMBOL(drm_mode_match);
+
+/**
+ * drm_mode_equal - test modes for equality
+ * @mode1: first mode
+ * @mode2: second mode
+ *
+ * Check to see if @mode1 and @mode2 are equivalent.
+ *
+ * Returns:
+ * True if the modes are equal, false otherwise.
+ */
+bool drm_mode_equal(const struct drm_display_mode *mode1,
+   const struct drm_display_mode