Re: [Intel-gfx] [PATCH v3 3/4] drm/i915: Add code to accept valid locked WOPCM register values

[Michal Wajdeczko]

On Tue, 10 Apr 2018 02:42:19 +0200, Jackie Li  wrote:

In current code, we only compare the locked WOPCM register values with  
the
calculated values. However, we can continue loading GuC/HuC firmware if  
the
locked (or partially locked) values were valid for current GuC/HuC  
firmware

sizes.

This patch added a new code path to verify whether the locked register
values can be used for GuC/HuC firmware loading, it will recalculate the
verify the new values if these registers were partially locked, so that  
we
won't fail the GuC/HuC firmware loading even if the locked register  
values

are different from the calculated ones.

v2:
 - Update WOPCM register only if it's not locked

Signed-off-by: Jackie Li 
Cc: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Michal Winiarski 
Cc: John Spotswood 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_wopcm.c | 217  
+++--

 1 file changed, 185 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_wopcm.c  
b/drivers/gpu/drm/i915/intel_wopcm.c

index b1c08ca..fa8d2be 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -140,6 +140,53 @@ static inline int check_hw_restriction(struct  
drm_i915_private *i915,

return err;
 }
+static inline u32 calculate_min_guc_wopcm_base(u32 huc_fw_size)
+{
+   return ALIGN(huc_fw_size + WOPCM_RESERVED_SIZE,
+GUC_WOPCM_OFFSET_ALIGNMENT);
+}
+
+static inline u32 calculate_min_guc_wopcm_size(u32 guc_fw_size)
+{
+   return guc_fw_size + GUC_WOPCM_RESERVED + GUC_WOPCM_STACK_RESERVED;
+}
+
+static inline int calculate_max_guc_wopcm_size(struct intel_wopcm  
*wopcm,

+  u32 guc_wopcm_base,
+  u32 *guc_wopcm_size)


Can't we just return this size as positive value?
I guess wopcm size will never be larger than MAX_INT.
We can add GEM_BUG_ON to be sure.


+{
+   struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
+   u32 ctx_rsvd = context_reserved_size(i915);
+
+   if (guc_wopcm_base >= wopcm->size ||
+   (guc_wopcm_base + ctx_rsvd) >= wopcm->size) {
+   DRM_ERROR("GuC WOPCM base (%uKiB) is too big.\n",
+ guc_wopcm_base / 1024);
+   return -E2BIG;


You are mixing calculations with verifications here.
Focus on calculations as you have separate function that verifies values.


+   }
+
+   *guc_wopcm_size =
+   (wopcm->size - guc_wopcm_base - ctx_rsvd) & GUC_WOPCM_SIZE_MASK;
+
+   return 0;
+}
+
+static inline int verify_calculated_values(struct drm_i915_private


hmm, maybe we can unify somehow this verification to be able to work with
both calculated and locked values?


*i915,
+  u32 guc_fw_size, u32 huc_fw_size,
+  u32 guc_wopcm_base,
+  u32 guc_wopcm_size)
+{
+   if (guc_wopcm_size < calculate_min_guc_wopcm_size(guc_fw_size)) {
+   DRM_ERROR("Need %uKiB WOPCM for GuC FW, %uKiB available.\n",
+ calculate_min_guc_wopcm_size(guc_fw_size),


you are calling calculate_min_guc_wopcm_size() twice


+ guc_wopcm_size / 1024);
+   return -E2BIG;
+   }
+
+   return check_hw_restriction(i915, guc_wopcm_base, guc_wopcm_size,
+   huc_fw_size);
+}
+
 /**
  * intel_wopcm_init() - Initialize the WOPCM structure.
  * @wopcm: pointer to intel_wopcm.
@@ -157,10 +204,8 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
u32 guc_fw_size = intel_uc_fw_get_upload_size(>guc.fw);
u32 huc_fw_size = intel_uc_fw_get_upload_size(>huc.fw);
-   u32 ctx_rsvd = context_reserved_size(i915);
u32 guc_wopcm_base;
u32 guc_wopcm_size;
-   u32 guc_wopcm_rsvd;
int err;
GEM_BUG_ON(!wopcm->size);
@@ -177,35 +222,121 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
return -E2BIG;
}
-   guc_wopcm_base = ALIGN(huc_fw_size + WOPCM_RESERVED_SIZE,
-  GUC_WOPCM_OFFSET_ALIGNMENT);
-   if ((guc_wopcm_base + ctx_rsvd) >= wopcm->size) {
-   DRM_ERROR("GuC WOPCM base (%uKiB) is too big.\n",
- guc_wopcm_base / 1024);
+   guc_wopcm_base = calculate_min_guc_wopcm_base(huc_fw_size);
+   err = calculate_max_guc_wopcm_size(wopcm, guc_wopcm_base,
+  _wopcm_size);
+   if (err)
+   return err;
+
+   DRM_DEBUG_DRIVER("Calculated GuC WOPCM Region: [%uKiB, %uKiB)\n",
+guc_wopcm_base 

Re: [Intel-gfx] [PATCH 0/9] GPU-bound energy efficiency improvements for the intel_pstate driver.

[Srinivas Pandruvada]

Hi Francisco,

[...]

> Are you no longer interested in improving those aspects of the non-
> HWP
> governor?  Is it that you're planning to delete it and move back to a
> generic cpufreq governor for non-HWP platforms in the near future?

Yes that is the plan for Atom platforms, which are only non HWP
platforms till now. You have to show good gain for performance and
performance/watt to carry and maintain such big change. So we have to
see your performance and power numbers.

> 
> > This will benefit all architectures including x86 + non i915.
> > 
> 
> The current design encourages re-use of the IO utilization statistic
> (see PATCH 1) by other governors as a mechanism driving the trade-off
> between energy efficiency and responsiveness based on whether the
> system
> is close to CPU-bound, in whatever way is applicable to each governor
> (e.g. it would make sense for it to be hooked up to the EPP
> preference
> knob in the case of the intel_pstate HWP governor, which would allow
> it
> to achieve better energy efficiency in IO-bound situations just like
> this series does for non-HWP parts).  There's nothing really x86- nor
> i915-specific about it.
> 
> > BTW intel-pstate can be driven by sched-util governor (passive
> > mode),
> > so if your prove benefits to Broxton, this can be a default.
> > As before:
> > - No regression to idle power at all. This is more important than
> > benchmarks
> > - Not just score, performance/watt is important
> > 
> 
> Is schedutil actually on par with the intel_pstate non-HWP governor
> as
> of today, according to these metrics and the overall benchmark
> numbers?
Yes, except for few cases. I have not tested recently, so may be
better.

Thanks,
Srinivas


> > Thanks,
> > Srinivas
> > 
> > 
> > > > controller does, even though the frequent IO waits may actually
> > > > be
> > > > an
> > > > indication that the system is IO-bound (which means that the
> > > > large
> > > > energy usage increase may not be translated in any performance
> > > > benefit
> > > > in practice, not to speak of performance being impacted
> > > > negatively
> > > > in
> > > > TDP-bound scenarios like GPU rendering).
> > > > 
> > > > Regarding run-time complexity, I haven't observed this governor
> > > > to
> > > > be
> > > > measurably more computationally intensive than the present
> > > > one.  It's a
> > > > bunch more instructions indeed, but still within the same
> > > > ballpark
> > > > as
> > > > the current governor.  The average increase in CPU utilization
> > > > on
> > > > my BXT
> > > > with this series is less than 0.03% (sampled via ftrace for v1,
> > > > I
> > > > can
> > > > repeat the measurement for the v2 I have in the works, though I
> > > > don't
> > > > expect the result to be substantially different).  If this is a
> > > > problem
> > > > for you there are several optimization opportunities that would
> > > > cut
> > > > down
> > > > the number of CPU cycles get_target_pstate_lp() takes to
> > > > execute by
> > > > a
> > > > large percent (most of the optimization ideas I can think of
> > > > right
> > > > now
> > > > though would come at some
> > > > accuracy/maintainability/debuggability
> > > > cost,
> > > > but may still be worth pursuing), but the computational
> > > > overhead is
> > > > low
> > > > enough at this point that the impact on any benchmark or real
> > > > workload
> > > > would be orders of magnitude lower than its variance, which
> > > > makes
> > > > it
> > > > kind of difficult to keep the discussion data-driven [as
> > > > possibly
> > > > any
> > > > performance optimization discussion should ever be ;)].
> > > > 
> > > > > 
> > > > > Thanks,
> > > > > Srinivas
> > > > > 
> > > > > 
> > > > > 
> > > > > > 
> > > > > > > [Absolute benchmark results are unfortunately omitted
> > > > > > > from
> > > > > > > this
> > > > > > > letter
> > > > > > > due to company policies, but the percent change and
> > > > > > > Student's
> > > > > > > T
> > > > > > > p-value are included above and in the referenced
> > > > > > > benchmark
> > > > > > > results]
> > > > > > > 
> > > > > > > The most obvious impact of this series will likely be the
> > > > > > > overall
> > > > > > > improvement in graphics performance on systems with an
> > > > > > > IGP
> > > > > > > integrated
> > > > > > > into the processor package (though for the moment this is
> > > > > > > only
> > > > > > > enabled
> > > > > > > on BXT+), because the TDP budget shared among CPU and GPU
> > > > > > > can
> > > > > > > frequently become a limiting factor in low-power
> > > > > > > devices.  On
> > > > > > > heavily
> > > > > > > TDP-bound devices this series improves performance of
> > > > > > > virtually any
> > > > > > > non-trivial graphics rendering by a significant amount
> > > > > > > (of
> > > > > > > the
> > > > > > > order
> > > > > > > of the energy efficiency improvement for that workload
> > > > > > > assuming the
> > > > > > > optimization didn't cause it to become non-TDP-bound).
> 

Re: [Intel-gfx] [PATCH v3 2/4] drm/i915: Always set HUC_LOADING_AGENT_GUC bit in WOPCM offset register

[Michal Wajdeczko]

On Tue, 10 Apr 2018 02:42:18 +0200, Jackie Li  wrote:


The enable_guc modparam is used to enable/disable GuC/HuC FW uploading
dynamcially during i915 module loading. If WOPCM offset register was

  
typo


locked
without having HUC_LOADING_AGENT_GUC bit set to 1, the module reloading
with both GuC and HuC FW will fail since we need to set this bit to 1 for
HuC FW uploading.

Since HUC_LOADING_AGENT_GUC bit has no impact on GuC FW uploading, this
patch updates the register updating code to make sure the WOPCM offset
register is always locked with HUC_LOADING_AGENT_GUC bit set to 1 which
will guarantee successful uploading of both GuC and HuC FW. We will  
further

take care of the locked values in the following enhancement patch.

Signed-off-by: Jackie Li 
Cc: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Michal Winiarski 
Cc: John Spotswood 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_wopcm.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_wopcm.c  
b/drivers/gpu/drm/i915/intel_wopcm.c

index 74bf76f..b1c08ca 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -238,8 +238,6 @@ static inline int write_and_verify(struct  
drm_i915_private *dev_priv,

 int intel_wopcm_init_hw(struct intel_wopcm *wopcm)
 {
struct drm_i915_private *dev_priv = wopcm_to_i915(wopcm);
-   u32 huc_agent;
-   u32 mask;
int err;
if (!USES_GUC(dev_priv))
@@ -255,10 +253,10 @@ int intel_wopcm_init_hw(struct intel_wopcm *wopcm)
if (err)
goto err_out;
-   huc_agent = USES_HUC(dev_priv) ? HUC_LOADING_AGENT_GUC : 0;
-   mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
err = write_and_verify(dev_priv, DMA_GUC_WOPCM_OFFSET,
-  wopcm->guc.base | huc_agent, mask,
+  wopcm->guc.base | HUC_LOADING_AGENT_GUC,
+  GUC_WOPCM_OFFSET_MASK | HUC_LOADING_AGENT_GUC |
+  GUC_WOPCM_OFFSET_VALID,


while we can unconditionally set HUC_AGENT bit, there is no need to verify
it unless we are using HuC, so we can consider leaving old mask intact.

/m


   GUC_WOPCM_OFFSET_VALID);
if (err)
goto err_out;

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v3 1/4] drm/i915: Always do WOPCM partitioning based on real firmware sizes

[Michal Wajdeczko]

On Tue, 10 Apr 2018 02:42:17 +0200, Jackie Li  wrote:


After enabled the WOPCM write-once registers locking status checking,
reloading of the i915 module will fail with modparam enable_guc set to 3
(enable GuC and HuC firmware loading) if the module was originally loaded
with enable_guc set to 1 (only enable GuC firmware loading).


Is this frequent and required scenario ? or just for debug/development ?


This is
because WOPCM registers were updated and locked without considering the  
HuC

FW size. Since we need both GuC and HuC FW sizes to determine the final
layout of WOPCM, we should always calculate the WOPCM layout based on the
actual sizes of the GuC and HuC firmware available for a specific  
platform

if we need continue to support enable/disable HuC FW loading dynamically
with enable_guc modparam.

This patch splits uC firmware fetching into two stages. First stage is to
fetch the firmware image and verify the firmware header. uC firmware will
be marked as verified and this will make FW info available for following
WOPCM layout calculation. The second stage is to create a GEM object and
copy the FW data into the created GEM object which will only be available
when GuC/HuC loading is enabled by enable_guc modparam. This will  
guarantee
that the WOPCM layout will be always be calculated correctly without  
making

any assumptions to the GuC and HuC firmware sizes.


You are also assuming that on reload exactly the same GuC/HuC firmwares
will bee used as in initial run. This will make this useless for debug/
development scenarios, where custom fw are likely to be specified.

If we want to support enable_guc=1->3->1 scenarios for debug/dev then
maybe more flexible will be other approach that makes allocations from
the other end as proposed in [1]

[1] https://patchwork.freedesktop.org/patch/212471/



v3:
 - Rebase

Signed-off-by: Jackie Li 
Cc: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Michal Winiarski 
Cc: John Spotswood 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_uc.c| 14 --
 drivers/gpu/drm/i915/intel_uc_fw.c | 31 ---
 drivers/gpu/drm/i915/intel_uc_fw.h |  7 +--
 3 files changed, 29 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uc.c  
b/drivers/gpu/drm/i915/intel_uc.c

index 1cffaf7..73b8f6c 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -172,11 +172,8 @@ void intel_uc_init_early(struct drm_i915_private  
*i915)

sanitize_options_early(i915);
-   if (USES_GUC(i915))
-   intel_uc_fw_fetch(i915, >fw);
-
-   if (USES_HUC(i915))
-   intel_uc_fw_fetch(i915, >fw);
+   intel_uc_fw_fetch(i915, >fw, USES_GUC(i915));
+   intel_uc_fw_fetch(i915, >fw, USES_HUC(i915));


Hmm, side effect of those unconditional fetches might be unwanted warnings
about missing firmwares (on configs with disabled guc) as well as extended
driver load time.

Do we really need to support this corner case enable_guc=1->3 at all costs?

/michal


 }
void intel_uc_cleanup_early(struct drm_i915_private *i915)
@@ -184,11 +181,8 @@ void intel_uc_cleanup_early(struct drm_i915_private  
*i915)

struct intel_guc *guc = >guc;
struct intel_huc *huc = >huc;
-   if (USES_HUC(i915))
-   intel_uc_fw_fini(>fw);
-
-   if (USES_GUC(i915))
-   intel_uc_fw_fini(>fw);
+   intel_uc_fw_fini(>fw);
+   intel_uc_fw_fini(>fw);
guc_free_load_err_log(guc);
 }
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c  
b/drivers/gpu/drm/i915/intel_uc_fw.c

index 6e8e0b5..a9cb900 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/intel_uc_fw.c
@@ -33,11 +33,13 @@
  *
  * @dev_priv: device private
  * @uc_fw: uC firmware
+ * @copy_to_obj: whether fetch uC firmware into GEM object or not


s/copy_to_obj/fetch


  *
- * Fetch uC firmware into GEM obj.
+ * Fetch and verify uC firmware and copy firmware data into GEM object  
if

+ * @copy_to_obj is true.
  */
 void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
-  struct intel_uc_fw *uc_fw)
+  struct intel_uc_fw *uc_fw, bool copy_to_obj)
 {
struct pci_dev *pdev = dev_priv->drm.pdev;
struct drm_i915_gem_object *obj;
@@ -154,17 +156,24 @@ void intel_uc_fw_fetch(struct drm_i915_private  
*dev_priv,

goto fail;
}
-   obj = i915_gem_object_create_from_data(dev_priv, fw->data, fw->size);
-   if (IS_ERR(obj)) {
-   err = PTR_ERR(obj);
-   DRM_DEBUG_DRIVER("%s fw object_create err=%d\n",
-intel_uc_fw_type_repr(uc_fw->type), err);
-   goto fail;
+   uc_fw->size = fw->size;
+   uc_fw->fetch_status = 

Re: [Intel-gfx] [PATCH 0/9] GPU-bound energy efficiency improvements for the intel_pstate driver.

[Francisco Jerez]

Hi Srinivas,

Srinivas Pandruvada  writes:

> On Wed, 2018-04-11 at 09:26 -0700, Francisco Jerez wrote:
>> 
>> "just like" here is possibly somewhat unfair to the schedutil
>> governor,
>> admittedly its progressive IOWAIT boosting behavior seems somewhat
>> less
>> wasteful than the intel_pstate non-HWP governor's IOWAIT boosting
>> behavior, but it's still largely unhelpful on IO-bound conditions.
>> 
>
> OK, if you think so, then improve it for sched-util governor or other
> mechanisms (as Juri suggested) instead of intel-pstate.

You may not have realized but this series provides a full drop-in
replacement for the current non-HWP governor of the intel_pstate driver,
it should be strictly superior to the current cpu-load governor in terms
of energy usage and performance under most scenarios (hold on for v2 for
the idle consumption issue).  Main reason it's implemented as a separate
governor currently is for us to be able to deploy it on BXT+ platforms
only for the moment, in order to decrease our initial validation effort
and get enough test coverage on BXT (which is incidentally the platform
that's going to get the greatest payoff) during a few release cycles.

Are you no longer interested in improving those aspects of the non-HWP
governor?  Is it that you're planning to delete it and move back to a
generic cpufreq governor for non-HWP platforms in the near future?

> This will benefit all architectures including x86 + non i915.
>

The current design encourages re-use of the IO utilization statistic
(see PATCH 1) by other governors as a mechanism driving the trade-off
between energy efficiency and responsiveness based on whether the system
is close to CPU-bound, in whatever way is applicable to each governor
(e.g. it would make sense for it to be hooked up to the EPP preference
knob in the case of the intel_pstate HWP governor, which would allow it
to achieve better energy efficiency in IO-bound situations just like
this series does for non-HWP parts).  There's nothing really x86- nor
i915-specific about it.

> BTW intel-pstate can be driven by sched-util governor (passive mode),
> so if your prove benefits to Broxton, this can be a default.
> As before:
> - No regression to idle power at all. This is more important than
> benchmarks
> - Not just score, performance/watt is important
>

Is schedutil actually on par with the intel_pstate non-HWP governor as
of today, according to these metrics and the overall benchmark numbers?

> Thanks,
> Srinivas
>
>
>> > controller does, even though the frequent IO waits may actually be
>> > an
>> > indication that the system is IO-bound (which means that the large
>> > energy usage increase may not be translated in any performance
>> > benefit
>> > in practice, not to speak of performance being impacted negatively
>> > in
>> > TDP-bound scenarios like GPU rendering).
>> > 
>> > Regarding run-time complexity, I haven't observed this governor to
>> > be
>> > measurably more computationally intensive than the present
>> > one.  It's a
>> > bunch more instructions indeed, but still within the same ballpark
>> > as
>> > the current governor.  The average increase in CPU utilization on
>> > my BXT
>> > with this series is less than 0.03% (sampled via ftrace for v1, I
>> > can
>> > repeat the measurement for the v2 I have in the works, though I
>> > don't
>> > expect the result to be substantially different).  If this is a
>> > problem
>> > for you there are several optimization opportunities that would cut
>> > down
>> > the number of CPU cycles get_target_pstate_lp() takes to execute by
>> > a
>> > large percent (most of the optimization ideas I can think of right
>> > now
>> > though would come at some accuracy/maintainability/debuggability
>> > cost,
>> > but may still be worth pursuing), but the computational overhead is
>> > low
>> > enough at this point that the impact on any benchmark or real
>> > workload
>> > would be orders of magnitude lower than its variance, which makes
>> > it
>> > kind of difficult to keep the discussion data-driven [as possibly
>> > any
>> > performance optimization discussion should ever be ;)].
>> > 
>> > > 
>> > > Thanks,
>> > > Srinivas
>> > > 
>> > > 
>> > > 
>> > > > 
>> > > > > [Absolute benchmark results are unfortunately omitted from
>> > > > > this
>> > > > > letter
>> > > > > due to company policies, but the percent change and Student's
>> > > > > T
>> > > > > p-value are included above and in the referenced benchmark
>> > > > > results]
>> > > > > 
>> > > > > The most obvious impact of this series will likely be the
>> > > > > overall
>> > > > > improvement in graphics performance on systems with an IGP
>> > > > > integrated
>> > > > > into the processor package (though for the moment this is
>> > > > > only
>> > > > > enabled
>> > > > > on BXT+), because the TDP budget shared among CPU and GPU can
>> > > > > frequently become a limiting factor in low-power devices.  On
>> > > > > heavily

Re: [Intel-gfx] [PATCH 0/9] GPU-bound energy efficiency improvements for the intel_pstate driver.

[Francisco Jerez]

Peter Zijlstra  writes:

> On Thu, Apr 12, 2018 at 12:55:39PM -0700, Francisco Jerez wrote:
>> Actually assuming that a single geometric feature of the power curve is
>> known -- it being convex in the frequency range allowed by the policy
>> (which is almost always the case, not only for Intel CPUs), the optimal
>> frequency for an IO-bound workload is fully independent of the exact
>> power curve -- It's just the minimum CPU frequency that's able to keep
>> the bottlenecking IO device at 100% utilization. 
>
> I think that is difficult to determine with the information at hand. We
> have lost all device information by the time we reach the scheduler.

I assume you mean it's difficult to tell whether the workload is
CPU-bound or IO-bound?  Yeah, it's non-trivial to determine whether the
system is bottlenecking on IO, it requires additional infrastructure to
keep track of IO utilization (that's the purpose of PATCH 1), and even
then it involves some heuristic assumptions which are not guaranteed
fail-proof, so the controller needs to be prepared for things to behave
reasonably when the assumptions deviate from reality (see the comments
in PATCH 6 for more details on what happens in such cases) -- How
frequently that happens in practice is what determines how far the
controller's response will be from the optimally energy-efficient
behavior in a real workload.  It seems to work fairly well in practice,
at least in the sample of test-cases I've been able to gather data from
so far.

Anyway that's the difficult part.  Once (if) you know you're IO-bound,
determining the optimal (most energy-efficient) CPU frequency is
relatively straightforward, and doesn't require knowledge of the exact
power curve of the CPU (beyond clamping the controller response to the
convexity region of the power curve).


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Re: [Intel-gfx] [PATCH v3 3/4] drm/i915: Add code to accept valid locked WOPCM register values

[John Spotswood]

On Mon, 2018-04-09 at 17:42 -0700, Jackie Li wrote:
> In current code, we only compare the locked WOPCM register values
> with the
> calculated values. However, we can continue loading GuC/HuC firmware
> if the
> locked (or partially locked) values were valid for current GuC/HuC
> firmware
> sizes.
> 
> This patch added a new code path to verify whether the locked
> register
> values can be used for GuC/HuC firmware loading, it will recalculate
> the
> verify the new values if these registers were partially locked, so
> that we
> won't fail the GuC/HuC firmware loading even if the locked register
> values
> are different from the calculated ones.
> 
> v2:
>  - Update WOPCM register only if it's not locked
> 
> Signed-off-by: Jackie Li 
> Cc: Michal Wajdeczko 
> Cc: Sagar Arun Kamble 
> Cc: Michal Winiarski 
> Cc: John Spotswood 
> Cc: Joonas Lahtinen 

Reviewed-by: John Spotswood 

> ---
>  drivers/gpu/drm/i915/intel_wopcm.c | 217
> +++--
>  1 file changed, 185 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
> b/drivers/gpu/drm/i915/intel_wopcm.c
> index b1c08ca..fa8d2be 100644
> --- a/drivers/gpu/drm/i915/intel_wopcm.c
> +++ b/drivers/gpu/drm/i915/intel_wopcm.c
> @@ -140,6 +140,53 @@ static inline int check_hw_restriction(struct
> drm_i915_private *i915,
>   return err;
>  }
>  
> +static inline u32 calculate_min_guc_wopcm_base(u32 huc_fw_size)
> +{
> + return ALIGN(huc_fw_size + WOPCM_RESERVED_SIZE,
> +  GUC_WOPCM_OFFSET_ALIGNMENT);
> +}
> +
> +static inline u32 calculate_min_guc_wopcm_size(u32 guc_fw_size)
> +{
> + return guc_fw_size + GUC_WOPCM_RESERVED +
> GUC_WOPCM_STACK_RESERVED;
> +}
> +
> +static inline int calculate_max_guc_wopcm_size(struct intel_wopcm
> *wopcm,
> +    u32 guc_wopcm_base,
> +    u32 *guc_wopcm_size)
> +{
> + struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
> + u32 ctx_rsvd = context_reserved_size(i915);
> +
> + if (guc_wopcm_base >= wopcm->size ||
> + (guc_wopcm_base + ctx_rsvd) >= wopcm->size) {
> + DRM_ERROR("GuC WOPCM base (%uKiB) is too big.\n",
> +   guc_wopcm_base / 1024);
> + return -E2BIG;
> + }
> +
> + *guc_wopcm_size =
> + (wopcm->size - guc_wopcm_base - ctx_rsvd) &
> GUC_WOPCM_SIZE_MASK;
> +
> + return 0;
> +}
> +
> +static inline int verify_calculated_values(struct drm_i915_private
> *i915,
> +    u32 guc_fw_size, u32
> huc_fw_size,
> +    u32 guc_wopcm_base,
> +    u32 guc_wopcm_size)
> +{
> + if (guc_wopcm_size <
> calculate_min_guc_wopcm_size(guc_fw_size)) {
> + DRM_ERROR("Need %uKiB WOPCM for GuC FW, %uKiB
> available.\n",
> +   calculate_min_guc_wopcm_size(guc_fw_size),
> +   guc_wopcm_size / 1024);
> + return -E2BIG;
> + }
> +
> + return check_hw_restriction(i915, guc_wopcm_base,
> guc_wopcm_size,
> + huc_fw_size);
> +}
> +
>  /**
>   * intel_wopcm_init() - Initialize the WOPCM structure.
>   * @wopcm: pointer to intel_wopcm.
> @@ -157,10 +204,8 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
>   struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
>   u32 guc_fw_size = intel_uc_fw_get_upload_size(
> >guc.fw);
>   u32 huc_fw_size = intel_uc_fw_get_upload_size(
> >huc.fw);
> - u32 ctx_rsvd = context_reserved_size(i915);
>   u32 guc_wopcm_base;
>   u32 guc_wopcm_size;
> - u32 guc_wopcm_rsvd;
>   int err;
>  
>   GEM_BUG_ON(!wopcm->size);
> @@ -177,35 +222,121 @@ int intel_wopcm_init(struct intel_wopcm
> *wopcm)
>   return -E2BIG;
>   }
>  
> - guc_wopcm_base = ALIGN(huc_fw_size + WOPCM_RESERVED_SIZE,
> -    GUC_WOPCM_OFFSET_ALIGNMENT);
> - if ((guc_wopcm_base + ctx_rsvd) >= wopcm->size) {
> - DRM_ERROR("GuC WOPCM base (%uKiB) is too big.\n",
> -   guc_wopcm_base / 1024);
> + guc_wopcm_base = calculate_min_guc_wopcm_base(huc_fw_size);
> + err = calculate_max_guc_wopcm_size(wopcm, guc_wopcm_base,
> +    _wopcm_size);
> + if (err)
> + return err;
> +
> + DRM_DEBUG_DRIVER("Calculated GuC WOPCM Region: [%uKiB,
> %uKiB)\n",
> +  guc_wopcm_base / 1024,
> +  (guc_wopcm_base + guc_wopcm_size) / 1024);
> +
> + err = verify_calculated_values(i915, guc_fw_size,
> huc_fw_size,
> +    guc_wopcm_base,
> guc_wopcm_size);
> + if (err)
> + 

Re: [Intel-gfx] [PATCH v3 2/4] drm/i915: Always set HUC_LOADING_AGENT_GUC bit in WOPCM offset register

[John Spotswood]

On Mon, 2018-04-09 at 17:42 -0700, Jackie Li wrote:
> The enable_guc modparam is used to enable/disable GuC/HuC FW
> uploading
> dynamcially during i915 module loading. If WOPCM offset register was
> locked
> without having HUC_LOADING_AGENT_GUC bit set to 1, the module
> reloading
> with both GuC and HuC FW will fail since we need to set this bit to 1
> for
> HuC FW uploading.
> 
> Since HUC_LOADING_AGENT_GUC bit has no impact on GuC FW uploading,
> this
> patch updates the register updating code to make sure the WOPCM
> offset
> register is always locked with HUC_LOADING_AGENT_GUC bit set to 1
> which
> will guarantee successful uploading of both GuC and HuC FW. We will
> further
> take care of the locked values in the following enhancement patch.
> 
> Signed-off-by: Jackie Li 
> Cc: Michal Wajdeczko 
> Cc: Sagar Arun Kamble 
> Cc: Michal Winiarski 
> Cc: John Spotswood 
> Cc: Joonas Lahtinen 

Reviewed-by: John Spotswood 

> ---
>  drivers/gpu/drm/i915/intel_wopcm.c | 8 +++-
>  1 file changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
> b/drivers/gpu/drm/i915/intel_wopcm.c
> index 74bf76f..b1c08ca 100644
> --- a/drivers/gpu/drm/i915/intel_wopcm.c
> +++ b/drivers/gpu/drm/i915/intel_wopcm.c
> @@ -238,8 +238,6 @@ static inline int write_and_verify(struct
> drm_i915_private *dev_priv,
>  int intel_wopcm_init_hw(struct intel_wopcm *wopcm)
>  {
>   struct drm_i915_private *dev_priv = wopcm_to_i915(wopcm);
> - u32 huc_agent;
> - u32 mask;
>   int err;
>  
>   if (!USES_GUC(dev_priv))
> @@ -255,10 +253,10 @@ int intel_wopcm_init_hw(struct intel_wopcm
> *wopcm)
>   if (err)
>   goto err_out;
>  
> - huc_agent = USES_HUC(dev_priv) ? HUC_LOADING_AGENT_GUC : 0;
> - mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID |
> huc_agent;
>   err = write_and_verify(dev_priv, DMA_GUC_WOPCM_OFFSET,
> -    wopcm->guc.base | huc_agent, mask,
> +    wopcm->guc.base |
> HUC_LOADING_AGENT_GUC,
> +    GUC_WOPCM_OFFSET_MASK |
> HUC_LOADING_AGENT_GUC |
> +    GUC_WOPCM_OFFSET_VALID,
>      GUC_WOPCM_OFFSET_VALID);
>   if (err)
>   goto err_out;
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Re: [Intel-gfx] [PATCH v3 1/4] drm/i915: Always do WOPCM partitioning based on real firmware sizes

[John Spotswood]

On Mon, 2018-04-09 at 17:42 -0700, Jackie Li wrote:
> After enabled the WOPCM write-once registers locking status checking,
> reloading of the i915 module will fail with modparam enable_guc set
> to 3
> (enable GuC and HuC firmware loading) if the module was originally
> loaded
> with enable_guc set to 1 (only enable GuC firmware loading). This is
> because WOPCM registers were updated and locked without considering
> the HuC
> FW size. Since we need both GuC and HuC FW sizes to determine the
> final
> layout of WOPCM, we should always calculate the WOPCM layout based on
> the
> actual sizes of the GuC and HuC firmware available for a specific
> platform
> if we need continue to support enable/disable HuC FW loading
> dynamically
> with enable_guc modparam.
> 
> This patch splits uC firmware fetching into two stages. First stage
> is to
> fetch the firmware image and verify the firmware header. uC firmware
> will
> be marked as verified and this will make FW info available for
> following
> WOPCM layout calculation. The second stage is to create a GEM object
> and
> copy the FW data into the created GEM object which will only be
> available
> when GuC/HuC loading is enabled by enable_guc modparam. This will
> guarantee
> that the WOPCM layout will be always be calculated correctly without
> making
> any assumptions to the GuC and HuC firmware sizes.
> 
> v3:
>  - Rebase
> 
> Signed-off-by: Jackie Li 
> Cc: Michal Wajdeczko 
> Cc: Sagar Arun Kamble 
> Cc: Michal Winiarski 
> Cc: John Spotswood 
> Cc: Joonas Lahtinen 

Reviewed-by: John Spotswood 

> ---
>  drivers/gpu/drm/i915/intel_uc.c| 14 --
>  drivers/gpu/drm/i915/intel_uc_fw.c | 31 --
> -
>  drivers/gpu/drm/i915/intel_uc_fw.h |  7 +--
>  3 files changed, 29 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uc.c
> b/drivers/gpu/drm/i915/intel_uc.c
> index 1cffaf7..73b8f6c 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -172,11 +172,8 @@ void intel_uc_init_early(struct drm_i915_private
> *i915)
>  
>   sanitize_options_early(i915);
>  
> - if (USES_GUC(i915))
> - intel_uc_fw_fetch(i915, >fw);
> -
> - if (USES_HUC(i915))
> - intel_uc_fw_fetch(i915, >fw);
> + intel_uc_fw_fetch(i915, >fw, USES_GUC(i915));
> + intel_uc_fw_fetch(i915, >fw, USES_HUC(i915));
>  }
>  
>  void intel_uc_cleanup_early(struct drm_i915_private *i915)
> @@ -184,11 +181,8 @@ void intel_uc_cleanup_early(struct
> drm_i915_private *i915)
>   struct intel_guc *guc = >guc;
>   struct intel_huc *huc = >huc;
>  
> - if (USES_HUC(i915))
> - intel_uc_fw_fini(>fw);
> -
> - if (USES_GUC(i915))
> - intel_uc_fw_fini(>fw);
> + intel_uc_fw_fini(>fw);
> + intel_uc_fw_fini(>fw);
>  
>   guc_free_load_err_log(guc);
>  }
> diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c
> b/drivers/gpu/drm/i915/intel_uc_fw.c
> index 6e8e0b5..a9cb900 100644
> --- a/drivers/gpu/drm/i915/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/intel_uc_fw.c
> @@ -33,11 +33,13 @@
>   *
>   * @dev_priv: device private
>   * @uc_fw: uC firmware
> + * @copy_to_obj: whether fetch uC firmware into GEM object or not
>   *
> - * Fetch uC firmware into GEM obj.
> + * Fetch and verify uC firmware and copy firmware data into GEM
> object if
> + * @copy_to_obj is true.
>   */
>  void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
> -    struct intel_uc_fw *uc_fw)
> +    struct intel_uc_fw *uc_fw, bool copy_to_obj)
>  {
>   struct pci_dev *pdev = dev_priv->drm.pdev;
>   struct drm_i915_gem_object *obj;
> @@ -154,17 +156,24 @@ void intel_uc_fw_fetch(struct drm_i915_private
> *dev_priv,
>   goto fail;
>   }
>  
> - obj = i915_gem_object_create_from_data(dev_priv, fw->data,
> fw->size);
> - if (IS_ERR(obj)) {
> - err = PTR_ERR(obj);
> - DRM_DEBUG_DRIVER("%s fw object_create err=%d\n",
> -  intel_uc_fw_type_repr(uc_fw->type), 
> err);
> - goto fail;
> + uc_fw->size = fw->size;
> + uc_fw->fetch_status = INTEL_UC_FIRMWARE_VERIFIED;
> +
> + if (copy_to_obj) {
> + obj = i915_gem_object_create_from_data(dev_priv, fw-
> >data,
> +    fw->size);
> + if (IS_ERR(obj)) {
> + err = PTR_ERR(obj);
> + DRM_DEBUG_DRIVER("%s fw object_create
> err=%d\n",
> +  intel_uc_fw_type_repr(uc_fw
> ->type),
> +  err);
> + goto fail;
> + }
> +
> + uc_fw->obj = obj;
> + uc_fw->fetch_status = 

Re: [Intel-gfx] [PATCH] drm/i915: content-type property for HDMI connector

[Ville Syrjälä]

On Sat, Apr 14, 2018 at 01:00:19AM +0300, StanLis wrote:
> From: Stanislav Lisovskiy 
> 
> Added content_type property to
> drm_connector_state in order to properly handle
> external HDMI TV content-type setting.
> 
> Signed-off-by: Stanislav Lisovskiy 
> ---
>  drivers/gpu/drm/drm_atomic.c|  4 
>  drivers/gpu/drm/drm_connector.c | 34 +
>  drivers/gpu/drm/drm_edid.c  |  1 +
>  drivers/gpu/drm/i915/intel_atomic.c |  1 +
>  drivers/gpu/drm/i915/intel_drv.h|  1 +
>  drivers/gpu/drm/i915/intel_hdmi.c   |  4 
>  drivers/gpu/drm/i915/intel_modes.c  | 10 +
>  include/drm/drm_connector.h |  2 ++
>  include/drm/drm_mode_config.h   |  5 +
>  include/uapi/drm/drm_mode.h |  5 +

Pls split the patch into two parts: one for drm core, the other for
i915. Then post to dri-devel, with intel-gfx cc:d.

>  10 files changed, 67 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index 7d25c42f22db..72fd2a1c801f 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -1266,6 +1266,8 @@ static int drm_atomic_connector_set_property(struct 
> drm_connector *connector,
>   state->link_status = val;
>   } else if (property == config->aspect_ratio_property) {
>   state->picture_aspect_ratio = val;
> + } else if (property == config->content_type_property) {
> + state->content_type = val;
>   } else if (property == connector->scaling_mode_property) {
>   state->scaling_mode = val;
>   } else if (property == connector->content_protection_property) {
> @@ -1351,6 +1353,8 @@ drm_atomic_connector_get_property(struct drm_connector 
> *connector,
>   *val = state->link_status;
>   } else if (property == config->aspect_ratio_property) {
>   *val = state->picture_aspect_ratio;
> + } else if (property == config->content_type_property) {
> + *val = state->content_type;
>   } else if (property == connector->scaling_mode_property) {
>   *val = state->scaling_mode;
>   } else if (property == connector->content_protection_property) {
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index b3cde897cd80..d03586edd483 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -720,6 +720,13 @@ static const struct drm_prop_enum_list 
> drm_aspect_ratio_enum_list[] = {
>   { DRM_MODE_PICTURE_ASPECT_16_9, "16:9" },
>  };
>  
> +static const struct drm_prop_enum_list drm_content_type_enum_list[] = {
> + { DRM_MODE_CONTENT_TYPE_GRAPHICS, "GRAPHICS" },
> + { DRM_MODE_CONTENT_TYPE_PHOTO, "PHOTO" },
> + { DRM_MODE_CONTENT_TYPE_CINEMA, "CINEMA" },
> + { DRM_MODE_CONTENT_TYPE_GAME, "GAME" },
> +};
> +
>  static const struct drm_prop_enum_list drm_panel_orientation_enum_list[] = {
>   { DRM_MODE_PANEL_ORIENTATION_NORMAL,"Normal"},
>   { DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP, "Upside Down"   },
> @@ -1260,6 +1267,33 @@ int drm_mode_create_aspect_ratio_property(struct 
> drm_device *dev)
>  }
>  EXPORT_SYMBOL(drm_mode_create_aspect_ratio_property);
>  
> +/**
> + * drm_mode_create_content_type_property - create content type property
> + * @dev: DRM device
> + *
> + * Called by a driver the first time it's needed, must be attached to desired
> + * connectors.
> + *
> + * Returns:
> + * Zero on success, negative errno on failure.
> + */
> +int drm_mode_create_content_type_property(struct drm_device *dev)
> +{
> + if (dev->mode_config.content_type_property)
> + return 0;
> +
> + dev->mode_config.content_type_property =
> + drm_property_create_enum(dev, 0, "content type",
> + drm_content_type_enum_list,
> + ARRAY_SIZE(drm_content_type_enum_list));
> +
> + if (dev->mode_config.content_type_property == NULL)
> + return -ENOMEM;
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_mode_create_content_type_property);
> +
>  /**
>   * drm_mode_create_suggested_offset_properties - create suggests offset 
> properties
>   * @dev: DRM device
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 134069f36482..946a182e0201 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -4867,6 +4867,7 @@ drm_hdmi_avi_infoframe_from_display_mode(struct 
> hdmi_avi_infoframe *frame,
>   }
>  
>   frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
> + frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
>  
>   /*
>* Populate picture aspect ratio from either
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c 
> b/drivers/gpu/drm/i915/intel_atomic.c
> index 40285d1b91b7..61ddb5871d8a 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: content-type property for HDMI connector

[Patchwork]

== Series Details ==

Series: drm/i915: content-type property for HDMI connector
URL   : https://patchwork.freedesktop.org/series/41677/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4053_full -> Patchwork_8687_full =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/41677/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_8687_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_flip@2x-plain-flip-fb-recreate:
  shard-hsw:  PASS -> FAIL (fdo#100368) +1

igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt:
  shard-kbl:  PASS -> DMESG-WARN (fdo#103558, fdo#105602) +25

igt@kms_plane@plane-position-hole-dpms-pipe-b-planes:
  shard-apl:  PASS -> FAIL (fdo#103166)


 Possible fixes 

igt@kms_sysfs_edid_timing:
  shard-apl:  WARN (fdo#100047) -> PASS


  fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602


== Participating hosts (6 -> 4) ==

  Missing(2): shard-glk shard-glkb 


== Build changes ==

* Linux: CI_DRM_4053 -> Patchwork_8687

  CI_DRM_4053: e2599f775a9c1c27f702e90e6432e555764edcd8 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4429: 80e4910581c7310258375a003a5de9a57ed24546 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8687: 3e378ba61f9d60d5b6d6b9c48cd00b66fad32c21 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4429: 93b35926a150e318439d2505901288594b3548f5 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8687/shards.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds

[Patchwork]

== Series Details ==

Series: series starting with [01/22] drm/i915/icl: Introduce initial Icelake 
Workarounds
URL   : https://patchwork.freedesktop.org/series/41687/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4053_full -> Patchwork_8688_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_8688_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8688_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/41687/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_8688_full:

  === IGT changes ===

 Warnings 

igt@gem_mocs_settings@mocs-rc6-ctx-render:
  shard-kbl:  PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_8688_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_atomic_transition@plane-toggle-modeset-transition:
  shard-hsw:  PASS -> DMESG-WARN (fdo#102614) +1

igt@kms_flip@plain-flip-fb-recreate:
  shard-hsw:  PASS -> FAIL (fdo#100368)


 Possible fixes 

igt@kms_setmode@basic:
  shard-kbl:  FAIL (fdo#99912) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 4) ==

  Missing(2): shard-glk shard-glkb 


== Build changes ==

* Linux: CI_DRM_4053 -> Patchwork_8688

  CI_DRM_4053: e2599f775a9c1c27f702e90e6432e555764edcd8 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4429: 80e4910581c7310258375a003a5de9a57ed24546 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8688: a5d656177b7ead3baa5b6629f814bb4edacd8b61 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4429: 93b35926a150e318439d2505901288594b3548f5 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8688/shards.html
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Re: [Intel-gfx] [PATCH i-g-t] [RFC] CONTRIBUTING: commit rights docs

[Harry Wentland]

On 2018-04-13 06:00 AM, Daniel Vetter wrote:
> This tries to align with the X.org communities's long-standing
> tradition of trying to be an inclusive community and handing out
> commit rights fairly freely.
> 
> We also tend to not revoke commit rights for people no longer
> regularly active in a given project, as long as they're still part of
> the larger community.
> 
> Finally make sure that commit rights, like anything happening on fd.o
> infrastructre, is subject to the fd.o's Code of Conduct.
> 
> v2: Point at MAINTAINERS for contact info (Daniel S.)
> 
> v3:
> - Make it clear that commit rights are voluntary and that committers
>   need to acknowledge positively when they're nominated by someone
>   else (Keith).
> - Encourage committers to drop their commit rights when they're no
>   longer active, and make it clear they'll get readded (Keith).
> - Add a line that maintainers and committers should actively nominate
>   new committers (me).
> 
> v4: Typo (Petri).
> 
> v5: Typo (Sean).
> 
> v6: Wording clarifications and spelling (Jani).
> 
> v7: Require an explicit commitment to the documented merge criteria
> and rules, instead of just the implied one through the Code of Conduct
> threat (Jani).
> 
> Acked-by: Alex Deucher 
> Acked-by: Arkadiusz Hiler 
> Acked-by: Daniel Stone 
> Acked-by: Eric Anholt 
> Acked-by: Gustavo Padovan 
> Acked-by: Petri Latvala 

Acked-by: Harry Wentland 

Harry

> Cc: Alex Deucher 
> Cc: Arkadiusz Hiler 
> Cc: Ben Widawsky 
> Cc: Daniel Stone 
> Cc: Dave Airlie 
> Cc: Eric Anholt 
> Cc: Gustavo Padovan 
> Cc: Jani Nikula 
> Cc: Joonas Lahtinen 
> Cc: Keith Packard 
> Cc: Kenneth Graunke 
> Cc: Kristian H. Kristensen 
> Cc: Maarten Lankhorst 
> Cc: Petri Latvala 
> Cc: Rodrigo Vivi 
> Cc: Sean Paul 
> Reviewed-by: Keith Packard 
> Signed-off-by: Daniel Vetter 
> ---
> If you wonder about the wide distribution list for an igt patch: I'd
> like to start a discussions about x.org community norms around commit
> rights at large, at least for all the shared repos. I plan to propose
> the same text for drm-misc and libdrm too, and hopefully others like
> mesa/xserver/wayland would follow.
> 
> fd.o admins also plan to discuss this (and a pile of other topics and
> hosting and code of conduct) with all projects, ideally this here
> would end up as the starting point for establishing some community
> norms.
> -Daniel
> ---
>  CONTRIBUTING | 48 
>  1 file changed, 48 insertions(+)
> 
> diff --git a/CONTRIBUTING b/CONTRIBUTING
> index 0180641be3aa..8a118134275c 100644
> --- a/CONTRIBUTING
> +++ b/CONTRIBUTING
> @@ -51,4 +51,52 @@ A short list of contribution guidelines:
>  - Changes to the testcases are automatically tested. Take the results into
>account before merging.
>  
> +Commit rights
> +-
> +
> +Commit rights will be granted to anyone who requests them and fulfills the
> +below criteria:
> +
> +- Submitted a few (5-10 as a rule of thumb) non-trivial (not just simple
> +  spelling fixes and whitespace adjustment) patches that have been merged
> +  already.
> +
> +- Are actively participating on discussions about their work (on the mailing
> +  list or IRC). This should not be interpreted as a requirement to review 
> other
> +  peoples patches but just make sure that patch submission isn't one-way
> +  communication. Cross-review is still highly encouraged.
> +
> +- Will be regularly contributing further patches. This includes regular
> +  contributors to other parts of the open source graphics stack who only
> +  do the oddball rare patch within igt itself.
> +
> +- Agrees to use their commit rights in accordance with the documented merge
> +  criteria, tools, and processes.
> +
> +Apply for an account (and any other account change requests) through
> +
> +https://www.freedesktop.org/wiki/AccountRequests/
> +
> +and please ping the maintainers if your request is stuck.
> +
> +Committers are encouraged to request their commit rights get removed when 
> they
> +no longer contribute to the project. Commit rights will be reinstated when 
> they
> +come back to the project.
> +
> +Maintainers and committers should encourage contributors to request commit
> +rights, especially junior contributors tend to underestimate their skills.
> +
> +Code of Conduct
> +---
> +
> +Please be aware the fd.o Code of Conduct also applies to 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: content-type property for HDMI connector

[Patchwork]

== Series Details ==

Series: drm/i915: content-type property for HDMI connector
URL   : https://patchwork.freedesktop.org/series/41677/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4053_full -> Patchwork_8687_full =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/41677/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_8687_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_flip@2x-plain-flip-fb-recreate:
  shard-hsw:  PASS -> FAIL (fdo#100368) +1

igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt:
  shard-kbl:  PASS -> DMESG-WARN (fdo#103558, fdo#105602) +25

igt@kms_plane@plane-position-hole-dpms-pipe-b-planes:
  shard-apl:  PASS -> FAIL (fdo#103166)


 Possible fixes 

igt@kms_sysfs_edid_timing:
  shard-apl:  WARN (fdo#100047) -> PASS


  fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602


== Participating hosts (6 -> 4) ==

  Missing(2): shard-glk shard-glkb 


== Build changes ==

* Linux: CI_DRM_4053 -> Patchwork_8687

  CI_DRM_4053: e2599f775a9c1c27f702e90e6432e555764edcd8 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4429: 80e4910581c7310258375a003a5de9a57ed24546 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8687: 3e378ba61f9d60d5b6d6b9c48cd00b66fad32c21 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4429: 93b35926a150e318439d2505901288594b3548f5 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8687/shards.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for igt/prime_mmap: Test for userptr support first

[Patchwork]

== Series Details ==

Series: igt/prime_mmap: Test for userptr support first
URL   : https://patchwork.freedesktop.org/series/41638/
State : success

== Summary ==

= CI Bug Log - changes from IGT_4426_full -> IGTPW_1251_full =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/41638/revisions/1/mbox/

== Known issues ==

  Here are the changes found in IGTPW_1251_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
  shard-hsw:  PASS -> FAIL (fdo#102887)

igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
  shard-kbl:  PASS -> DMESG-WARN (fdo#103313)

igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
  shard-snb:  PASS -> FAIL (fdo#103166)

igt@kms_universal_plane@cursor-fb-leak-pipe-b:
  shard-kbl:  PASS -> DMESG-WARN (fdo#105602, fdo#103558) +2


 Possible fixes 

igt@kms_flip@flip-vs-expired-vblank-interruptible:
  shard-hsw:  FAIL (fdo#102887) -> PASS

igt@kms_rotation_crc@sprite-rotation-180:
  shard-snb:  FAIL (fdo#103925) -> PASS

igt@kms_sysfs_edid_timing:
  shard-apl:  WARN (fdo#100047) -> PASS

igt@perf@polling:
  shard-hsw:  FAIL (fdo#102252) -> PASS


  fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
  fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602


== Participating hosts (5 -> 4) ==

  Missing(1): shard-glkb 


== Build changes ==

* IGT: IGT_4426 -> IGTPW_1251
* Linux: CI_DRM_4048 -> CI_DRM_4049
* Piglit: piglit_4426 -> piglit_4428

  CI_DRM_4048: 8c59766aea748fef3de2711f69486cb37bef95bd @ 
git://anongit.freedesktop.org/gfx-ci/linux
  CI_DRM_4049: 3dbfa04d62f1f1214a03c3b2d30f987dccf50ab4 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_1251: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1251/
  IGT_4426: d502f055ac4500cada758876a512ac4f14b34851 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4426: 93b35926a150e318439d2505901288594b3548f5 @ 
git://anongit.freedesktop.org/piglit
  piglit_4428: 93b35926a150e318439d2505901288594b3548f5 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1251/shards.html
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Re: [Intel-gfx] [PATCH 0/9] GPU-bound energy efficiency improvements for the intel_pstate driver.

[Peter Zijlstra]

On Thu, Apr 12, 2018 at 12:55:39PM -0700, Francisco Jerez wrote:
> Actually assuming that a single geometric feature of the power curve is
> known -- it being convex in the frequency range allowed by the policy
> (which is almost always the case, not only for Intel CPUs), the optimal
> frequency for an IO-bound workload is fully independent of the exact
> power curve -- It's just the minimum CPU frequency that's able to keep
> the bottlenecking IO device at 100% utilization. 

I think that is difficult to determine with the information at hand. We
have lost all device information by the time we reach the scheduler.
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Re: [Intel-gfx] [PATCH v2] drm/i915: Check whitelist registers across resets

[Chris Wilson]

Quoting Oscar Mateo (2018-04-13 18:04:16)
> 
> 
> On 4/13/2018 9:54 AM, Chris Wilson wrote:
> > Quoting Oscar Mateo (2018-04-13 17:46:42)
> >>
> >> On 4/12/2018 8:21 AM, Chris Wilson wrote:
> >>> Add a selftest to ensure that we restore the whitelisted registers after
> >>> rewrite the registers everytime they might be scrubbed, e.g. module
> >>> load, reset and resume. For the other volatile workaround registers, we
> >>> export their presence via debugfs and check in igt/gem_workarounds.
> >>> However, we don't export the whitelist and rather than do so, let's test
> >>> them directly in the kernel.
> >> I guess my question is... why? what was the problem with exporting the
> >> list of whitelist registers in debugfs?
> > We don't... (There's no RING_NONPRIV checking currently)
> 
> There is no checking, but we were showing the full list in debugfs. Ok, 
> I guess it wasn't that useful without the corresponding igt...

Oh no we weren't. wa_ring_whitelist_reg() isn't storing the reg in the
wa list, just that we have used the RING_NONPRIV slot. At one point, I
think the intention was there but that seems to disappeared and now I
removed the notion entirely ;)

> > I wasn't fond
> > of the igt for it is checking kernel implementation rather than behaviour.
> > The kernel gives it a checklist which it dutifully follows... Now that
> > we have selftests, we don't need to write what I think should be unit
> > tests in igt anymore.
> 
> Ah, so I take the plan is to also check the other WAs in selftests? 
> Somehow I thought you wanted to treat whitelisting differently.

Right, the long term goal will be to move all the workaround testing
here. It just so happens that I wrote a buggy patch that CI was happy
with that alerted me to the lack of testing ;)

The only fly in the ointment is doing S3/S4 testing, as doing
suspend/resume from inside the kernel tricky (trickier than even getting
it right from userspace). So I think we may just have to be a little
more creative, and do something like call i915_drv_suspend() directly.
Hmm, now that's an idea. (i915_drv_suspend(); scribble over state;
i915_drv_resume()).
-Chris
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Re: [Intel-gfx] [PATCH igt] igt/gem_exec_schedule: Exercise preemption timeout

[Chris Wilson]

Quoting Antonio Argenziano (2018-04-13 18:20:02)
> 
> 
> On 13/04/18 08:59, Chris Wilson wrote:
> > die. What we expect to happen is spin[0] is (more or less, there is still
> > dmesg) silently killed by the preempt timeout. If that timeout doesn't
> 
> The silent part is interesting, how do we make sure that during normal 
> preemption operations (e.g. preempt on an ARB_CHECK) we didn't silently 
> discard the preempted batch? Do we care?

Not particularly. From our point of view, the goal is that the high
priority spin[2] runs, no matter what. If the other requests cooperate,
that works out best for them.

The challenge for the test itself is detecting when the timeout was hit.
We aren't particularly good at demonstrating the spinner doesn't block
preemption, it is demonstrated in other tests, but we don't assert that
it is so.
-Chris
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Re: [Intel-gfx] [PATCH 0/9] GPU-bound energy efficiency improvements for the intel_pstate driver.

[Juri Lelli]

Hi,

On 11/04/18 09:26, Francisco Jerez wrote:
> Francisco Jerez  writes:
> 
> > Hi Srinivas,
> >
> > Srinivas Pandruvada  writes:
> >
> >> On Tue, 2018-04-10 at 15:28 -0700, Francisco Jerez wrote:
> >>> Francisco Jerez  writes:
> >>> 
> >> [...]
> >>
> >>
> >>> For the case anyone is wondering what's going on, Srinivas pointed me
> >>> at
> >>> a larger idle power usage increase off-list, ultimately caused by the
> >>> low-latency heuristic as discussed in the paragraph above.  I have a
> >>> v2
> >>> of PATCH 6 that gives the controller a third response curve roughly
> >>> intermediate between the low-latency and low-power states of this
> >>> revision, which avoids the energy usage increase while C0 residency
> >>> is
> >>> low (e.g. during idle) expected for v1.  The low-latency behavior of
> >>> this revision is still going to be available based on a heuristic (in
> >>> particular when a realtime-priority task is scheduled).  We're
> >>> carrying
> >>> out some additional testing, I'll post the code here eventually.
> >>
> >> Please try sched-util governor also. There is a frequency-invariant
> >> patch, which I can send you (This eventually will be pushed by Peter).
> >> We want to avoid complexity to intel-pstate for non HWP power sensitive
> >> platforms as far as possible.
> >>
> >
> > Unfortunately the schedutil governor (whether frequency invariant or
> > not) has the exact same energy efficiency issues as the present
> > intel_pstate non-HWP governor.  Its response is severely underdamped
> > leading to energy-inefficient behavior for any oscillating non-CPU-bound
> > workload.  To exacerbate that problem the frequency is maxed out on
> > frequent IO waiting just like the current intel_pstate cpu-load
> 
> "just like" here is possibly somewhat unfair to the schedutil governor,
> admittedly its progressive IOWAIT boosting behavior seems somewhat less
> wasteful than the intel_pstate non-HWP governor's IOWAIT boosting
> behavior, but it's still largely unhelpful on IO-bound conditions.

Sorry if I jump in out of the blue, but what you are trying to solve
looks very similar to what IPA [1] is targeting as well. I might be
wrong (I'll try to spend more time reviewing your set), but my first
impression is that we should try to solve similar problems with a more
general approach that could benefit different sys/archs.

I'm Cc-ing some Arm folks...

Best,

- Juri

[1] https://developer.arm.com/open-source/intelligent-power-allocation
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Re: [Intel-gfx] [PATCH igt] igt/gem_exec_schedule: Exercise preemption timeout

[Antonio Argenziano]

On 13/04/18 08:59, Chris Wilson wrote:

Quoting Antonio Argenziano (2018-04-13 16:54:27)



On 13/04/18 07:14, Chris Wilson wrote:

Set up a unpreemptible spinner such that the only way we can inject a
high priority request onto the GPU is by resetting the spinner. The test
fails if we trigger hangcheck rather than the fast timeout mechanism.

Signed-off-by: Chris Wilson 
---
   lib/i915/gem_context.c| 72 +++
   lib/i915/gem_context.h|  3 ++
   lib/igt_dummyload.c   | 12 +--
   lib/igt_dummyload.h   |  3 ++
   tests/gem_exec_schedule.c | 34 ++
   5 files changed, 106 insertions(+), 18 deletions(-)



...


@@ -449,8 +457,6 @@ void igt_spin_batch_end(igt_spin_t *spin)
   if (!spin)
   return;
   
- igt_assert(*spin->batch == MI_ARB_CHK ||

-*spin->batch == MI_BATCH_BUFFER_END);


I am not sure why we needed this, but it seems safe to remove.


   *spin->batch = MI_BATCH_BUFFER_END;
   __sync_synchronize();
   }



diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
index 6ff15b6ef..93254945b 100644
--- a/tests/gem_exec_schedule.c
+++ b/tests/gem_exec_schedule.c
@@ -656,6 +656,37 @@ static void preemptive_hang(int fd, unsigned ring)
   gem_context_destroy(fd, ctx[HI]);
   }
   
+static void preempt_timeout(int fd, unsigned ring)

+{
+ igt_spin_t *spin[3];
+ uint32_t ctx;
+
+ igt_require(__gem_context_set_preempt_timeout(fd, 0, 0));
+
+ ctx = gem_context_create(fd);
+ gem_context_set_priority(fd, ctx, MIN_PRIO);
+ spin[0] = __igt_spin_batch_new_hang(fd, ctx, ring);
+ spin[1] = __igt_spin_batch_new_hang(fd, ctx, ring);

Should we send MAX_ELSP_QLEN batches to match other preemption tests?


+ gem_context_destroy(fd, ctx);
+
+ ctx = gem_context_create(fd);
+ gem_context_set_priority(fd, ctx, MAX_PRIO);
+ gem_context_set_preempt_timeout(fd, ctx, 1000 * 1000);
+ spin[2] = __igt_spin_batch_new(fd, ctx, ring, 0);
+ gem_context_destroy(fd, ctx);
+
+ igt_spin_batch_end(spin[2]);
+ gem_sync(fd, spin[2]->handle);


Does this guarantee that spin[1] did not overtake spin[2]?


It does as well. Neither spin[0] or spin[1] can complete without being
reset at this point. If they are reset (by hangcheck) we detect that and


Cool.


die. What we expect to happen is spin[0] is (more or less, there is still
dmesg) silently killed by the preempt timeout. If that timeout doesn't


The silent part is interesting, how do we make sure that during normal 
preemption operations (e.g. preempt on an ARB_CHECK) we didn't silently 
discard the preempted batch? Do we care?


Test looks good,
Reviewed-by: Antonio Argenziano 

Thanks,
Antonio


happen, more hangcheck. What we don't check here is how quick. Now we
could reasonably assert that the spin[2] -> gem_sync takes less than 2ms.
-Chris


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Re: [Intel-gfx] [RFC v4 03/25] drm/fb-helper: No need to cache rotation and sw_rotations

[Hans de Goede]

Hi Noralf,

1 comment inline.

On 13-04-18 18:53, Noralf Trønnes wrote:

Getting rotation info is cheap so we can do it on demand.

This is done in preparation for the removal of struct drm_fb_helper_crtc.

Cc: Hans de Goede 
Signed-off-by: Noralf Trønnes 
---
  drivers/gpu/drm/drm_fb_helper.c | 131 
  include/drm/drm_fb_helper.h |   8 ---
  2 files changed, 65 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 0646b108030b..e48ace2d55f5 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -361,6 +361,48 @@ int drm_fb_helper_debug_leave(struct fb_info *info)
  }
  EXPORT_SYMBOL(drm_fb_helper_debug_leave);
  
+/* Check if the plane can hw rotate to match panel orientation */

+static bool drm_fb_helper_panel_rotation(struct drm_connector *connector,
+struct drm_plane *plane,
+unsigned int *rotation)
+{
+   uint64_t valid_mask = 0;
+   unsigned int i;
+
+   if (!connector)
+   return false;
+
+   switch (connector->display_info.panel_orientation) {
+   case DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP:
+   *rotation = DRM_MODE_ROTATE_180;
+   break;
+   case DRM_MODE_PANEL_ORIENTATION_LEFT_UP:
+   *rotation = DRM_MODE_ROTATE_90;
+   break;
+   case DRM_MODE_PANEL_ORIENTATION_RIGHT_UP:
+   *rotation = DRM_MODE_ROTATE_270;
+   break;
+   default:
+   *rotation = DRM_MODE_ROTATE_0;
+   }
+
+   /*
+* TODO: support 90 / 270 degree hardware rotation,
+* depending on the hardware this may require the framebuffer
+* to be in a specific tiling format.
+*/
+   if (*rotation != DRM_MODE_ROTATE_180 || !plane->rotation_property)
+   return false;
+
+   for (i = 0; i < plane->rotation_property->num_values; i++)
+   valid_mask |= (1ULL << plane->rotation_property->values[i]);
+
+   if (!(*rotation & valid_mask))
+   return false;
+
+   return true;
+}
+
  static int restore_fbdev_mode_atomic(struct drm_fb_helper *fb_helper, bool 
active)
  {
struct drm_device *dev = fb_helper->dev;
@@ -406,10 +448,13 @@ static int restore_fbdev_mode_atomic(struct drm_fb_helper 
*fb_helper, bool activ
for (i = 0; i < fb_helper->crtc_count; i++) {
struct drm_mode_set *mode_set = 
_helper->crtc_info[i].mode_set;
struct drm_plane *primary = mode_set->crtc->primary;
+   unsigned int rotation;
  
-		/* Cannot fail as we've already gotten the plane state above */

-   plane_state = drm_atomic_get_new_plane_state(state, primary);
-   plane_state->rotation = fb_helper->crtc_info[i].rotation;
+   if (drm_fb_helper_panel_rotation(mode_set->connectors[0], primary, 
)) {
+   /* Cannot fail as we've already gotten the plane state 
above */
+   plane_state = drm_atomic_get_new_plane_state(state, 
primary);
+   plane_state->rotation = rotation;
+   }


We want plane_state->rotation to be set to DRM_MODE_ROTATE_0 in the else
case, AFAIK new_plane_state starts with the current state and rotation
may have a different value there.

Otherwise this looks good to me.

Regards,

Hans




ret = __drm_atomic_helper_set_config(mode_set, state);
if (ret != 0)
@@ -841,7 +886,6 @@ int drm_fb_helper_init(struct drm_device *dev,
if (!fb_helper->crtc_info[i].mode_set.connectors)
goto out_free;
fb_helper->crtc_info[i].mode_set.num_connectors = 0;
-   fb_helper->crtc_info[i].rotation = DRM_MODE_ROTATE_0;
}
  
  	i = 0;

@@ -2414,62 +2458,6 @@ static int drm_pick_crtcs(struct drm_fb_helper 
*fb_helper,
return best_score;
  }
  
-/*

- * This function checks if rotation is necessary because of panel orientation
- * and if it is, if it is supported.
- * If rotation is necessary and supported, its gets set in fb_crtc.rotation.
- * If rotation is necessary but not supported, a DRM_MODE_ROTATE_* flag gets
- * or-ed into fb_helper->sw_rotations. In drm_setup_crtcs_fb() we check if only
- * one bit is set and then we set fb_info.fbcon_rotate_hint to make fbcon do
- * the unsupported rotation.
- */
-static void drm_setup_crtc_rotation(struct drm_fb_helper *fb_helper,
-   struct drm_fb_helper_crtc *fb_crtc,
-   struct drm_connector *connector)
-{
-   struct drm_plane *plane = fb_crtc->mode_set.crtc->primary;
-   uint64_t valid_mask = 0;
-   int i, rotation;
-
-   fb_crtc->rotation = DRM_MODE_ROTATE_0;
-
-   switch 

Re: [Intel-gfx] [RFC v4 00/25] drm: Add generic fbdev emulation

[Noralf Trønnes]

Argh, it didn't go through this time either.
I'll just have to strip off recipients and just send to the lists when 
the cool off period is over.


Sorry about the noise, I'll have to investigate this further.

Noralf.


Den 13.04.2018 18.53, skrev Noralf Trønnes:

This patchset explores the possibility of having generic fbdev emulation
in DRM for drivers that supports dumb buffers which they can export. An
API is added to support in-kernel clients in general.

In this version I was able to reuse the modesetting code from
drm_fb_helper in the client API. This avoids code duplication, carries
over lessons learned and the modesetting code is bisectable. The
downside is that it takes +10 patches to rip drm_fb_helper in two, so
maybe it's not worth it wrt possible breakage and a challenging review.

Does the Intel CI test the fbdev emulation?

Daniel had this concern with the previous version:

 The register/unregister model needs more thought. Allowing both clients
 to register whenever they want to, and drm_device instances to come and
 go is what fbcon has done, and the resulting locking is a horror show.

 I think if we require that all in-kernel drm_clients are registers when
 loading drm.ko (and enabled/disabled only per module options and
 Kconfig), then we can throw out all the locking. That avoids a lot of
 the headaches.

I have solved this by adding a notifier that fires when a new DRM device
is registered (I've removed the new() callback). Currently only
bootsplash uses this. The fbdev client needs to be setup from the driver
since it can't know on device registration if the driver will setup it's
own fbdev emulation later and the vtcon client hooks up to a user
provided device id.

Since fbcon can't handle fb_open failing, the buffer has to be
pre-allocated. Exporting a GEM buffer pins the driver module making it
impossible to unload it.
I have included 2 solutions to the problem:
- sysfs file to remove/close clients: remove_internal_clients
- Change drm_gem_prime_export() so it doesn't pin on client buffers

If a dumb buffer is exported from a kernel thread (worker) context, the
file descriptor isn't closed and I leak a reference so the buffer isn't
freed. Please look at drm_client_buffer_create() in patch
'drm/client: Finish the in-kernel client API'.
This is a blocker that needs a solution.


Noralf.

Changes since version 3:
Client API changes:
- Drop drm_client_register_funcs() which attached clients indirectly.
   Let clients attach directly using drm_client_new{_from_id}(). Clients
   that wants to attach to all devices must be linked into drm.ko and use
   the DRM device notifier. This is done to avoid the lock/race
   register/unregister hell we have with fbcon. (Daniel Vetter)
- drm_client_display_restore() checks if there is a master and if so
   returns -EBUSY. (Daniel Vetter)
- Allocate drm_file up front instead of on-demand. Since fbdev can't do
   on demand buffer allocation because of fbcon, there's no need for this.
- Add sysfs file to remove clients
- Don't pin driver module when exporting gem client buffers
- Dropped page flip support since drm_fb_helper is now used for fbdev
   emulation.

- The bootsplash client now switches over to fbdev on keypress.

Changes since version 2:
- Don't set drm master for in-kernel clients. (Daniel Vetter)
- Add in-kernel client API

Changes since version 1:
- Don't add drm_fb_helper_fb_open() and drm_fb_helper_fb_release() to
   DRM_FB_HELPER_DEFAULT_OPS(). (Fi.CI.STATIC)
   The following uses that macro and sets fb_open/close: udlfb_ops,
   amdgpufb_ops, drm_fb_helper_generic_fbdev_ops, nouveau_fbcon_ops,
   nouveau_fbcon_sw_ops, radeonfb_ops.
   This results in: warning: Initializer entry defined twice
- Support CONFIG_DRM_KMS_HELPER=m (kbuild test robot)
   ERROR:  [drivers/gpu/drm/drm_kms_helper.ko] undefined!
- Drop buggy patch: (Chris Wilson)
   drm/prime: Clear drm_gem_object->dma_buf on release
- Defer buffer creation until fb_open.


David Herrmann (1):
   drm: provide management functions for drm_file

Noralf Trønnes (24):
   drm/file: Don't set master on in-kernel clients
   drm/fb-helper: No need to cache rotation and sw_rotations
   drm/fb-helper: Remove drm_fb_helper_debug_enter/leave()
   drm/fb-helper: dpms_legacy(): Only set on connectors in use
   drm/atomic: Move __drm_atomic_helper_disable_plane/set_config()
   drm: Begin an API for in-kernel clients
   drm/fb-helper: Use struct drm_client_display
   drm/fb-helper: Move modeset commit code to drm_client
   drm/connector: Add
 drm_connector_has_preferred_mode/pick_cmdline_mode()
   drm/connector: Add connector array functions
   drm/i915: Add drm_driver->initial_client_display callback
   drm/fb-helper: Remove struct drm_fb_helper_crtc
   drm/fb-helper: Remove struct drm_fb_helper_connector
   drm/fb-helper: Move modeset config code to drm_client
   drm: Make ioctls available for in-kernel clients
   drm/client: Bail out if there's a DRM 

Re: [Intel-gfx] [PATCH v2] drm/i915: Check whitelist registers across resets

[Oscar Mateo]

On 4/13/2018 9:54 AM, Chris Wilson wrote:

Quoting Oscar Mateo (2018-04-13 17:46:42)


On 4/12/2018 8:21 AM, Chris Wilson wrote:

Add a selftest to ensure that we restore the whitelisted registers after
rewrite the registers everytime they might be scrubbed, e.g. module
load, reset and resume. For the other volatile workaround registers, we
export their presence via debugfs and check in igt/gem_workarounds.
However, we don't export the whitelist and rather than do so, let's test
them directly in the kernel.

I guess my question is... why? what was the problem with exporting the
list of whitelist registers in debugfs?

We don't... (There's no RING_NONPRIV checking currently)


There is no checking, but we were showing the full list in debugfs. Ok, 
I guess it wasn't that useful without the corresponding igt...



I wasn't fond
of the igt for it is checking kernel implementation rather than behaviour.
The kernel gives it a checklist which it dutifully follows... Now that
we have selftests, we don't need to write what I think should be unit
tests in igt anymore.


Ah, so I take the plan is to also check the other WAs in selftests? 
Somehow I thought you wanted to treat whitelisting differently.



The test we use is to read the registers back from the CS (this helps us
be sure that the registers will be valid for MI_LRI etc). In order to
generate the expected list, we split intel_whitelist_workarounds_emit
into two phases, the first to build the list and the second to apply.
Inside the test, we only build the list and then check that list against
the hw.

v2: Filter out pre-gen8 as they do not have RING_NONPRIV.

Signed-off-by: Chris Wilson 
Cc: Oscar Mateo 
Cc: Mika Kuoppala 
Cc: Joonas Lahtinen 
---
+static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
+  struct whitelist *w)
+{
+ struct drm_i915_private *i915 = engine->i915;
+
+ GEM_BUG_ON(engine->id != RCS);
+
+ w->count = 0;
+ w->nopid = i915_mmio_reg_offset(RING_NOPID(engine->mmio_base));

:)


+
+ if (INTEL_GEN(i915) < 8)
+ return NULL;
+ else if (IS_BROADWELL(i915))
+ bdw_whitelist_build(engine, w);

Is it worth passing the engine around? Even of we end up with
whitelisted register in engines != RCS, we will need more changes than this.

No idea, it was easy enough to pass around, so I did just in case it was
useful in future (pulling out i915 or whatever).
-Chris


I'd say let's cross that bridge when we get to it, but with or without it:

Reviewed-by: Oscar Mateo 

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[Intel-gfx] [RFC v4 20/25] drm/prime: Don't pin module on export for in-kernel clients

[Noralf Trønnes]

Avoid pinning the module when exporting a GEM object as a dmabuf. This
makes it possible to unload drivers that has in-kernel clients using it.
The client is removed on drm_dev_unregister() so no need to pin the driver.

Signed-off-by: Noralf Trønnes 
---
 drivers/gpu/drm/drm_prime.c | 24 
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
index e6052ab2bec4..f9dbe3b9db20 100644
--- a/drivers/gpu/drm/drm_prime.c
+++ b/drivers/gpu/drm/drm_prime.c
@@ -567,6 +567,30 @@ struct dma_buf *drm_gem_prime_export(struct drm_device 
*dev,
.flags = flags,
.priv = obj,
};
+   bool is_internal = false;
+   struct drm_file *file;
+
+   mutex_lock(>filelist_mutex);
+   list_for_each_entry(file, >filelist_internal, lhead) {
+   struct drm_gem_object *iter;
+   int id;
+
+   spin_lock(>table_lock);
+   idr_for_each_entry(>object_idr, iter, id) {
+   if (iter == obj) {
+   is_internal = true;
+   break;
+   }
+   }
+   spin_unlock(>table_lock);
+
+   if (is_internal)
+   break;
+   }
+   mutex_unlock(>filelist_mutex);
+
+   if (is_internal)
+   exp_info.owner = NULL;
 
if (dev->driver->gem_prime_res_obj)
exp_info.resv = dev->driver->gem_prime_res_obj(obj);
-- 
2.15.1

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[Intel-gfx] [RFC v4 18/25] drm/client: Make the display modes available to clients

[Noralf Trønnes]

Give clients easy access to the display modes.

Signed-off-by: Noralf Trønnes 
---
 drivers/gpu/drm/drm_client.c | 159 +--
 include/drm/drm_client.h |  25 +++
 2 files changed, 148 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/drm_client.c b/drivers/gpu/drm/drm_client.c
index 764c556630b8..bce1630a0db2 100644
--- a/drivers/gpu/drm/drm_client.c
+++ b/drivers/gpu/drm/drm_client.c
@@ -8,6 +8,7 @@
  * Copyright (c) 2007 Dave Airlie 
  */
 
+#include 
 #include 
 
 #include 
@@ -54,6 +55,7 @@ struct drm_client_display *drm_client_display_create(struct 
drm_device *dev)
}
 
display->dev = dev;
+   INIT_LIST_HEAD(>modes);
display->modeset_count = num_crtc;
 
drm_for_each_crtc(crtc, dev)
@@ -84,12 +86,16 @@ EXPORT_SYMBOL(drm_client_display_create);
  */
 void drm_client_display_free(struct drm_client_display *display)
 {
+   struct drm_display_mode *mode, *tmp;
struct drm_mode_set *modeset;
unsigned int i;
 
if (!display)
return;
 
+   list_for_each_entry_safe(mode, tmp, >modes, head)
+   drm_mode_destroy(display->dev, mode);
+
drm_client_display_for_each_modeset(modeset, display) {
if (modeset->mode)
drm_mode_destroy(display->dev, modeset->mode);
@@ -670,22 +676,70 @@ static int drm_pick_crtcs(struct drm_client_display 
*display,
return best_score;
 }
 
-/**
- * drm_client_find_display() - Find display
- * @dev: DRM device
- * @width: Maximum display mode width (optional)
- * @height: Maximum display mode height (optional)
- *
- * This function returns a display the client can use if available.
- *
- * Free resources by calling drm_client_display_free().
- *
- * Returns:
- * A _client_display on success, NULL if no connectors are found
- * or error pointer on failure.
- */
-struct drm_client_display *
-drm_client_find_display(struct drm_device *dev, unsigned int width, unsigned 
int height)
+/* Give the client a static list of display modes */
+static int drm_client_display_copy_modes(struct drm_client_display *display)
+{
+   int hdisplay = 0, vdisplay = 0, vrefresh;
+   struct drm_device *dev = display->dev;
+   struct drm_display_mode *mode, *copy;
+   struct drm_connector *connector;
+   struct drm_mode_set *modeset;
+   unsigned int count = 0;
+
+   drm_client_display_for_each_modeset(modeset, display) {
+   if (!modeset->num_connectors || !modeset->mode)
+   continue;
+
+   connector = modeset->connectors[0];
+   mode = modeset->mode;
+   count++;
+
+   if (modeset->num_connectors == 2) {
+   /* Cloned output */
+   copy = drm_mode_duplicate(dev, modeset->mode);
+   if (!copy)
+   return -ENOMEM;
+   list_add_tail(>head, >modes);
+   display->mode = copy;
+
+   return 0;
+   }
+
+   if (!modeset->y)
+   hdisplay += modeset->mode->hdisplay;
+   if (!modeset->x)
+   vdisplay += modeset->mode->vdisplay;
+   vrefresh = modeset->mode->vrefresh;
+   }
+
+   if (!count)
+   return 0;
+
+   if (count == 1) {
+   struct drm_display_mode *iter;
+
+   list_for_each_entry(iter, >modes, head) {
+   copy = drm_mode_duplicate(dev, iter);
+   if (!copy)
+   return -ENOMEM;
+   list_add_tail(>head, >modes);
+   if (!display->mode && drm_mode_equal(iter, mode))
+   display->mode = copy;
+   }
+   } else {
+   /* Combined tile mode. Only the default one for now */
+   copy = drm_cvt_mode(dev, hdisplay, vdisplay, vrefresh, false, 
false, false);
+   if (!copy)
+   return -ENOMEM;
+   list_add_tail(>head, >modes);
+   display->mode = copy;
+   }
+
+   return 0;
+}
+
+static struct drm_client_display *
+drm_client_find_display_default(struct drm_device *dev, unsigned int width, 
unsigned int height)
 {
struct drm_client_display_offset *offsets;
struct drm_client_display *display;
@@ -695,25 +749,6 @@ drm_client_find_display(struct drm_device *dev, unsigned 
int width, unsigned int
int i, connector_count;
bool *enabled;
 
-   DRM_DEBUG_KMS("\n");
-
-   if (!width)
-   width = dev->mode_config.max_width;
-   if (!height)
-   height = dev->mode_config.max_height;
-
-   mutex_lock(>mode_config.mutex);
-   if (!drm_client_probe_connector_modes(dev, width, height))
-   

[Intel-gfx] [RFC v4 17/25] drm/client: Bail out if there's a DRM master

[Noralf Trønnes]

If there's a DRM master, return -EBUSY.
Block userspace from becoming master by taking the master lock while
the client is setting the mode.

Suggested-by: Daniel Vetter 
Signed-off-by: Noralf Trønnes 
---
 drivers/gpu/drm/drm_auth.c  | 33 +
 drivers/gpu/drm/drm_client.c| 34 +-
 drivers/gpu/drm/drm_fb_helper.c |  8 
 drivers/gpu/drm/drm_internal.h  |  2 ++
 include/drm/drm_client.h|  4 ++--
 5 files changed, 70 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/drm_auth.c b/drivers/gpu/drm/drm_auth.c
index d9c0f7573905..d656d0d93da3 100644
--- a/drivers/gpu/drm/drm_auth.c
+++ b/drivers/gpu/drm/drm_auth.c
@@ -366,3 +366,36 @@ void drm_master_put(struct drm_master **master)
*master = NULL;
 }
 EXPORT_SYMBOL(drm_master_put);
+
+/**
+ * drm_master_block - Block DRM master operations
+ * @dev: DRM device
+ *
+ * This function checks if there is a master on @dev. If there is no master it
+ * blocks anyone from becoming master. In-kernel clients can use this to know
+ * when they can act as master. Use drm_master_unblock() to unblock.
+ *
+ * Returns:
+ * True if there is no master, false otherwise.
+ */
+bool drm_master_block(struct drm_device *dev)
+{
+   mutex_lock(>master_mutex);
+   if (dev->master) {
+   mutex_unlock(>master_mutex);
+   return false;
+   }
+
+   return true;
+}
+
+/**
+ * drm_master_unblock - Unblock DRM master operations
+ * @dev: DRM device
+ *
+ * Unblock and allow userspace to become master.
+ */
+void drm_master_unblock(struct drm_device *dev)
+{
+   mutex_unlock(>master_mutex);
+}
diff --git a/drivers/gpu/drm/drm_client.c b/drivers/gpu/drm/drm_client.c
index 27818a467b09..764c556630b8 100644
--- a/drivers/gpu/drm/drm_client.c
+++ b/drivers/gpu/drm/drm_client.c
@@ -18,6 +18,8 @@
 #include 
 #include 
 
+#include "drm_internal.h"
+
 struct drm_client_display_offset {
int x, y;
 };
@@ -313,18 +315,30 @@ static int drm_client_display_restore_legacy(struct 
drm_client_display *display)
 /**
  * drm_client_display_restore() - Restore client display
  * @display: Client display
+ * @force: If true, restore even if there's a DRM master
  *
  * Restore client display using the current modeset configuration.
  *
  * Return:
  * Zero on succes or negative error code on failure.
  */
-int drm_client_display_restore(struct drm_client_display *display)
+int drm_client_display_restore(struct drm_client_display *display, bool force)
 {
-   if (drm_drv_uses_atomic_modeset(display->dev))
-   return drm_client_display_restore_atomic(display, true);
+   struct drm_device *dev = display->dev;
+   int ret;
+
+   if (!force && !drm_master_block(dev))
+   return -EBUSY;
+
+   if (drm_drv_uses_atomic_modeset(dev))
+   ret = drm_client_display_restore_atomic(display, true);
else
-   return drm_client_display_restore_legacy(display);
+   ret = drm_client_display_restore_legacy(display);
+
+   if (!force)
+   drm_master_unblock(dev);
+
+   return ret;
 }
 EXPORT_SYMBOL(drm_client_display_restore);
 
@@ -354,13 +368,23 @@ static void drm_client_display_dpms_legacy(struct 
drm_client_display *display, i
  * drm_client_display_dpms() - Set display DPMS mode
  * @display: Client display
  * @mode: DPMS mode
+ *
+ * Returns:
+ * Zero on success, -EBUSY if there's a DRM master.
  */
-void drm_client_display_dpms(struct drm_client_display *display, int mode)
+int drm_client_display_dpms(struct drm_client_display *display, int mode)
 {
+   if (!drm_master_block(display->dev))
+   return -EBUSY;
+
if (drm_drv_uses_atomic_modeset(display->dev))
drm_client_display_restore_atomic(display, mode == 
DRM_MODE_DPMS_ON);
else
drm_client_display_dpms_legacy(display, mode);
+
+   drm_master_unblock(display->dev);
+
+   return 0;
 }
 EXPORT_SYMBOL(drm_client_display_dpms);
 
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 01d8840930a3..98e5bc92c9f2 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -181,7 +181,7 @@ int drm_fb_helper_restore_fbdev_mode_unlocked(struct 
drm_fb_helper *fb_helper)
return 0;
 
mutex_lock(_helper->lock);
-   ret = drm_client_display_restore(fb_helper->display);
+   ret = drm_client_display_restore(fb_helper->display, false);
 
do_delayed = fb_helper->delayed_hotplug;
if (do_delayed)
@@ -243,7 +243,7 @@ static bool drm_fb_helper_force_kernel_mode(void)
continue;
 
mutex_lock(>lock);
-   ret = drm_client_display_restore(helper->display);
+   ret = drm_client_display_restore(helper->display, true);
if (ret)

[Intel-gfx] [RFC v4 16/25] drm: Make ioctls available for in-kernel clients

[Noralf Trønnes]

Make ioctl wrappers for functions that will be used by the in-kernel API.
The following functions are touched:
- drm_mode_create_dumb_ioctl()
- drm_mode_destroy_dumb_ioctl()
- drm_mode_addfb2()
- drm_mode_rmfb()
- drm_prime_handle_to_fd_ioctl()

drm_mode_addfb2() also gets the ability to override the debug name.

Signed-off-by: Noralf Trønnes 
---
 drivers/gpu/drm/drm_crtc_internal.h | 18 ++---
 drivers/gpu/drm/drm_dumb_buffers.c  | 33 
 drivers/gpu/drm/drm_framebuffer.c   | 50 -
 drivers/gpu/drm/drm_internal.h  |  3 +++
 drivers/gpu/drm/drm_ioc32.c |  2 +-
 drivers/gpu/drm/drm_ioctl.c |  4 +--
 drivers/gpu/drm/drm_prime.c | 13 +++---
 7 files changed, 84 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/drm_crtc_internal.h 
b/drivers/gpu/drm/drm_crtc_internal.h
index 3c2b82865ad2..8f8886ac0e4d 100644
--- a/drivers/gpu/drm/drm_crtc_internal.h
+++ b/drivers/gpu/drm/drm_crtc_internal.h
@@ -62,6 +62,12 @@ int drm_mode_getresources(struct drm_device *dev,
 
 
 /* drm_dumb_buffers.c */
+int drm_mode_create_dumb(struct drm_device *dev,
+struct drm_mode_create_dumb *args,
+struct drm_file *file_priv);
+int drm_mode_destroy_dumb(struct drm_device *dev, u32 handle,
+ struct drm_file *file_priv);
+
 /* IOCTLs */
 int drm_mode_create_dumb_ioctl(struct drm_device *dev,
   void *data, struct drm_file *file_priv);
@@ -163,14 +169,18 @@ int drm_framebuffer_check_src_coords(uint32_t src_x, 
uint32_t src_y,
 const struct drm_framebuffer *fb);
 void drm_fb_release(struct drm_file *file_priv);
 
+int drm_mode_addfb2(struct drm_device *dev, struct drm_mode_fb_cmd2 *r,
+   struct drm_file *file_priv, const char *comm);
+int drm_mode_rmfb(struct drm_device *dev, u32 fb_id,
+ struct drm_file *file_priv);
 
 /* IOCTL */
 int drm_mode_addfb(struct drm_device *dev,
   void *data, struct drm_file *file_priv);
-int drm_mode_addfb2(struct drm_device *dev,
-   void *data, struct drm_file *file_priv);
-int drm_mode_rmfb(struct drm_device *dev,
- void *data, struct drm_file *file_priv);
+int drm_mode_addfb2_ioctl(struct drm_device *dev,
+ void *data, struct drm_file *file_priv);
+int drm_mode_rmfb_ioctl(struct drm_device *dev,
+   void *data, struct drm_file *file_priv);
 int drm_mode_getfb(struct drm_device *dev,
   void *data, struct drm_file *file_priv);
 int drm_mode_dirtyfb_ioctl(struct drm_device *dev,
diff --git a/drivers/gpu/drm/drm_dumb_buffers.c 
b/drivers/gpu/drm/drm_dumb_buffers.c
index 39ac15ce4702..eed9687b8698 100644
--- a/drivers/gpu/drm/drm_dumb_buffers.c
+++ b/drivers/gpu/drm/drm_dumb_buffers.c
@@ -53,10 +53,10 @@
  * a hardware-specific ioctl to allocate suitable buffer objects.
  */
 
-int drm_mode_create_dumb_ioctl(struct drm_device *dev,
-  void *data, struct drm_file *file_priv)
+int drm_mode_create_dumb(struct drm_device *dev,
+struct drm_mode_create_dumb *args,
+struct drm_file *file_priv)
 {
-   struct drm_mode_create_dumb *args = data;
u32 cpp, stride, size;
 
if (!dev->driver->dumb_create)
@@ -91,6 +91,12 @@ int drm_mode_create_dumb_ioctl(struct drm_device *dev,
return dev->driver->dumb_create(file_priv, dev, args);
 }
 
+int drm_mode_create_dumb_ioctl(struct drm_device *dev,
+  void *data, struct drm_file *file_priv)
+{
+   return drm_mode_create_dumb(dev, data, file_priv);
+}
+
 /**
  * drm_mode_mmap_dumb_ioctl - create an mmap offset for a dumb backing storage 
buffer
  * @dev: DRM device
@@ -122,17 +128,22 @@ int drm_mode_mmap_dumb_ioctl(struct drm_device *dev,
   >offset);
 }
 
+int drm_mode_destroy_dumb(struct drm_device *dev, u32 handle,
+ struct drm_file *file_priv)
+{
+   if (!dev->driver->dumb_create)
+   return -ENOSYS;
+
+   if (dev->driver->dumb_destroy)
+   return dev->driver->dumb_destroy(file_priv, dev, handle);
+   else
+   return drm_gem_dumb_destroy(file_priv, dev, handle);
+}
+
 int drm_mode_destroy_dumb_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv)
 {
struct drm_mode_destroy_dumb *args = data;
 
-   if (!dev->driver->dumb_create)
-   return -ENOSYS;
-
-   if (dev->driver->dumb_destroy)
-   return dev->driver->dumb_destroy(file_priv, dev, args->handle);
-   else
-   return drm_gem_dumb_destroy(file_priv, dev, args->handle);
+   return drm_mode_destroy_dumb(dev, args->handle, file_priv);
 }
-
diff --git 

[Intel-gfx] [RFC v4 21/25] drm/fb-helper: Add drm_fb_helper_fb_open/release()

[Noralf Trønnes]

These helpers keep track of fbdev users and drm_driver.last_close will
only restore fbdev when actually in use. Additionally the display is
turned off when the last user is closing. fbcon is a user in this context.

If struct fb_ops is defined in a library, fb_open() takes a ref on the
library (fb_ops.owner) instead of the driver module. Fix that by ensuring
that the driver module is pinned.

The functions are not added to the DRM_FB_HELPER_DEFAULT_OPS() macro,
because some of its users do set fb_open/release themselves.

Signed-off-by: Noralf Trønnes 
---
 drivers/gpu/drm/drm_fb_helper.c | 54 -
 include/drm/drm_fb_helper.h | 29 ++
 2 files changed, 82 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 98e5bc92c9f2..b1124c08b1ed 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -177,7 +177,7 @@ int drm_fb_helper_restore_fbdev_mode_unlocked(struct 
drm_fb_helper *fb_helper)
if (!drm_fbdev_emulation || !fb_helper)
return -ENODEV;
 
-   if (READ_ONCE(fb_helper->deferred_setup))
+   if (READ_ONCE(fb_helper->deferred_setup) || 
!READ_ONCE(fb_helper->open_count))
return 0;
 
mutex_lock(_helper->lock);
@@ -368,6 +368,7 @@ void drm_fb_helper_prepare(struct drm_device *dev, struct 
drm_fb_helper *helper,
INIT_WORK(>dirty_work, drm_fb_helper_dirty_work);
helper->dirty_clip.x1 = helper->dirty_clip.y1 = ~0;
mutex_init(>lock);
+   helper->open_count = 1;
helper->funcs = funcs;
helper->dev = dev;
 }
@@ -620,6 +621,53 @@ int drm_fb_helper_defio_init(struct drm_fb_helper 
*fb_helper)
 }
 EXPORT_SYMBOL(drm_fb_helper_defio_init);
 
+/**
+ * drm_fb_helper_fb_open - implementation for _ops.fb_open
+ * @info: fbdev registered by the helper
+ * @user: 1=userspace, 0=fbcon
+ *
+ * Increase fbdev use count.
+ * If _ops is wrapped in a library, pin the driver module.
+ */
+int drm_fb_helper_fb_open(struct fb_info *info, int user)
+{
+   struct drm_fb_helper *fb_helper = info->par;
+   struct drm_device *dev = fb_helper->dev;
+
+   if (info->fbops->owner != dev->driver->fops->owner) {
+   if (!try_module_get(dev->driver->fops->owner))
+   return -ENODEV;
+   }
+
+   fb_helper->open_count++;
+
+   return 0;
+}
+EXPORT_SYMBOL(drm_fb_helper_fb_open);
+
+/**
+ * drm_fb_helper_fb_release - implementation for _ops.fb_release
+ * @info: fbdev registered by the helper
+ * @user: 1=userspace, 0=fbcon
+ *
+ * Decrease fbdev use count and turn off if there are no users left.
+ * If _ops is wrapped in a library, unpin the driver module.
+ */
+int drm_fb_helper_fb_release(struct fb_info *info, int user)
+{
+   struct drm_fb_helper *fb_helper = info->par;
+   struct drm_device *dev = fb_helper->dev;
+
+   if (!(--fb_helper->open_count))
+   drm_fb_helper_dpms(info, DRM_MODE_DPMS_OFF);
+
+   if (info->fbops->owner != dev->driver->fops->owner)
+   module_put(dev->driver->fops->owner);
+
+   return 0;
+}
+EXPORT_SYMBOL(drm_fb_helper_fb_release);
+
 /**
  * drm_fb_helper_sys_read - wrapper around fb_sys_read
  * @info: fb_info struct pointer
@@ -1436,6 +1484,10 @@ static int drm_fb_helper_single_fb_probe(struct 
drm_fb_helper *fb_helper,
if (ret < 0)
return ret;
 
+   /* Block restore without users if we do track it */
+   if (fb_helper->fbdev->fbops->fb_open == drm_fb_helper_fb_open)
+   fb_helper->open_count = 0;
+
strcpy(fb_helper->fb->comm, "[fbcon]");
return 0;
 }
diff --git a/include/drm/drm_fb_helper.h b/include/drm/drm_fb_helper.h
index 5f66f253a97b..330983975d5e 100644
--- a/include/drm/drm_fb_helper.h
+++ b/include/drm/drm_fb_helper.h
@@ -184,6 +184,22 @@ struct drm_fb_helper {
 * See also: @deferred_setup
 */
int preferred_bpp;
+
+   /**
+* @open_count:
+*
+* Keeps track of fbdev use to know when to not restore fbdev and to
+* disable the pipeline when the last user is gone.
+*
+* Drivers that use drm_fb_helper_fb_open() as their \.fb_open
+* callback will get an initial value of 0 and get restore based on
+* actual use. Others will get an initial value of 1 which means that
+* fbdev will always be restored. Drivers that call
+* drm_fb_helper_fb_open() in their \.fb_open, thus needs to set the
+* initial value to 0 themselves in their _fb_helper_funcs->fb_probe
+* callback.
+*/
+   unsigned int open_count;
 };
 
 /**
@@ -230,6 +246,9 @@ void drm_fb_helper_deferred_io(struct fb_info *info,
   struct list_head *pagelist);
 int drm_fb_helper_defio_init(struct drm_fb_helper *fb_helper);
 
+int drm_fb_helper_fb_open(struct fb_info *info, int 

[Intel-gfx] [RFC v4 15/25] drm/fb-helper: Move modeset config code to drm_client

[Noralf Trønnes]

Call the function drm_client_find_display().
No functional change apart from making width/height arguments optional.
Some function name/signature changes and whitespace adjustments.

Signed-off-by: Noralf Trønnes 
---
 drivers/gpu/drm/drm_client.c| 399 
 drivers/gpu/drm/drm_fb_helper.c | 371 +
 include/drm/drm_client.h|   2 +
 include/drm/drm_fb_helper.h |   4 -
 4 files changed, 403 insertions(+), 373 deletions(-)

diff --git a/drivers/gpu/drm/drm_client.c b/drivers/gpu/drm/drm_client.c
index c85c13568cf9..27818a467b09 100644
--- a/drivers/gpu/drm/drm_client.c
+++ b/drivers/gpu/drm/drm_client.c
@@ -18,6 +18,10 @@
 #include 
 #include 
 
+struct drm_client_display_offset {
+   int x, y;
+};
+
 /**
  * drm_client_display_create() - Create display structure
  * @dev: DRM device
@@ -359,3 +363,398 @@ void drm_client_display_dpms(struct drm_client_display 
*display, int mode)
drm_client_display_dpms_legacy(display, mode);
 }
 EXPORT_SYMBOL(drm_client_display_dpms);
+
+static int drm_client_probe_connector_modes(struct drm_device *dev,
+   u32 max_width, u32 max_height)
+{
+   struct drm_connector_list_iter conn_iter;
+   struct drm_connector *connector;
+   int count = 0;
+
+   drm_connector_list_iter_begin(dev, _iter);
+   drm_for_each_connector_iter(connector, _iter) {
+   count += connector->funcs->fill_modes(connector, max_width, 
max_height);
+   }
+   drm_connector_list_iter_end(_iter);
+
+   return count;
+}
+
+static bool drm_target_cloned(struct drm_device *dev,
+ struct drm_connector **connectors,
+ unsigned int connector_count,
+ struct drm_display_mode **modes,
+ struct drm_client_display_offset *offsets,
+ bool *enabled, int width, int height)
+{
+   int count, i, j;
+   bool can_clone = false;
+   struct drm_display_mode *dmt_mode, *mode;
+
+   /* only contemplate cloning in the single crtc case */
+   if (dev->mode_config.num_crtc > 1)
+   return false;
+
+   count = 0;
+   for (i = 0; i < connector_count; i++) {
+   if (enabled[i])
+   count++;
+   }
+
+   /* only contemplate cloning if more than one connector is enabled */
+   if (count <= 1)
+   return false;
+
+   /* check the command line or if nothing common pick 1024x768 */
+   can_clone = true;
+   for (i = 0; i < connector_count; i++) {
+   if (!enabled[i])
+   continue;
+   modes[i] = drm_connector_pick_cmdline_mode(connectors[i]);
+   if (!modes[i]) {
+   can_clone = false;
+   break;
+   }
+   for (j = 0; j < i; j++) {
+   if (!enabled[j])
+   continue;
+   if (!drm_mode_equal(modes[j], modes[i]))
+   can_clone = false;
+   }
+   }
+
+   if (can_clone) {
+   DRM_DEBUG_KMS("can clone using command line\n");
+   return true;
+   }
+
+   /* try and find a 1024x768 mode on each connector */
+   can_clone = true;
+   dmt_mode = drm_mode_find_dmt(dev, 1024, 768, 60, false);
+
+   for (i = 0; i < connector_count; i++) {
+   if (!enabled[i])
+   continue;
+
+   list_for_each_entry(mode, [i]->modes, head) {
+   if (drm_mode_equal(mode, dmt_mode))
+   modes[i] = mode;
+   }
+   if (!modes[i])
+   can_clone = false;
+   }
+
+   if (can_clone) {
+   DRM_DEBUG_KMS("can clone using 1024x768\n");
+   return true;
+   }
+   DRM_INFO("kms: can't enable cloning when we probably wanted to.\n");
+
+   return false;
+}
+
+static void drm_get_tile_offsets(struct drm_connector **connectors,
+unsigned int connector_count,
+struct drm_display_mode **modes,
+struct drm_client_display_offset *offsets,
+int idx,
+int h_idx, int v_idx)
+{
+   int i;
+   int hoffset = 0, voffset = 0;
+
+   for (i = 0; i < connector_count; i++) {
+   struct drm_connector *connector = connectors[i];
+
+   if (!connector->has_tile)
+   continue;
+
+   if (!modes[i] && (h_idx || v_idx)) {
+   DRM_DEBUG_KMS("no modes for connector tiled %d %d\n", i,
+ connector->base.id);
+   

[Intel-gfx] [RFC v4 14/25] drm/fb-helper: Remove struct drm_fb_helper_connector

[Noralf Trønnes]

No need to maintain a list of registered connectors. Just use the
connector iterator.

TODO: Remove:
- drm_fb_helper_add_one_connector()
- drm_fb_helper_single_add_all_connectors()
- drm_fb_helper_remove_one_connector()

Signed-off-by: Noralf Trønnes 
---
 drivers/gpu/drm/drm_fb_helper.c | 359 ++--
 include/drm/drm_fb_helper.h |  13 --
 2 files changed, 86 insertions(+), 286 deletions(-)

diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index ce38eadcb346..6ee61f195321 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -112,59 +112,10 @@ static DEFINE_MUTEX(kernel_fb_helper_lock);
  * deferred I/O (coupled with drm_fb_helper_fbdev_teardown()).
  */
 
-#define drm_fb_helper_for_each_connector(fbh, i__) \
-   for (({ lockdep_assert_held(&(fbh)->lock); }), \
-i__ = 0; i__ < (fbh)->connector_count; i__++)
-
-static int __drm_fb_helper_add_one_connector(struct drm_fb_helper *fb_helper,
-struct drm_connector *connector)
-{
-   struct drm_fb_helper_connector *fb_conn;
-   struct drm_fb_helper_connector **temp;
-   unsigned int count;
-
-   if (!drm_fbdev_emulation)
-   return 0;
-
-   lockdep_assert_held(_helper->lock);
-
-   count = fb_helper->connector_count + 1;
-
-   if (count > fb_helper->connector_info_alloc_count) {
-   size_t size = count * sizeof(fb_conn);
-
-   temp = krealloc(fb_helper->connector_info, size, GFP_KERNEL);
-   if (!temp)
-   return -ENOMEM;
-
-   fb_helper->connector_info_alloc_count = count;
-   fb_helper->connector_info = temp;
-   }
-
-   fb_conn = kzalloc(sizeof(*fb_conn), GFP_KERNEL);
-   if (!fb_conn)
-   return -ENOMEM;
-
-   drm_connector_get(connector);
-   fb_conn->connector = connector;
-   fb_helper->connector_info[fb_helper->connector_count++] = fb_conn;
-
-   return 0;
-}
-
 int drm_fb_helper_add_one_connector(struct drm_fb_helper *fb_helper,
struct drm_connector *connector)
 {
-   int err;
-
-   if (!fb_helper)
-   return 0;
-
-   mutex_lock(_helper->lock);
-   err = __drm_fb_helper_add_one_connector(fb_helper, connector);
-   mutex_unlock(_helper->lock);
-
-   return err;
+   return 0;
 }
 EXPORT_SYMBOL(drm_fb_helper_add_one_connector);
 
@@ -184,87 +135,14 @@ EXPORT_SYMBOL(drm_fb_helper_add_one_connector);
  */
 int drm_fb_helper_single_add_all_connectors(struct drm_fb_helper *fb_helper)
 {
-   struct drm_device *dev;
-   struct drm_connector *connector;
-   struct drm_connector_list_iter conn_iter;
-   int i, ret = 0;
-
-   if (!drm_fbdev_emulation || !fb_helper)
-   return 0;
-
-   dev = fb_helper->dev;
-
-   mutex_lock(_helper->lock);
-   drm_connector_list_iter_begin(dev, _iter);
-   drm_for_each_connector_iter(connector, _iter) {
-   ret = __drm_fb_helper_add_one_connector(fb_helper, connector);
-   if (ret)
-   goto fail;
-   }
-   goto out;
-
-fail:
-   drm_fb_helper_for_each_connector(fb_helper, i) {
-   struct drm_fb_helper_connector *fb_helper_connector =
-   fb_helper->connector_info[i];
-
-   drm_connector_put(fb_helper_connector->connector);
-
-   kfree(fb_helper_connector);
-   fb_helper->connector_info[i] = NULL;
-   }
-   fb_helper->connector_count = 0;
-out:
-   drm_connector_list_iter_end(_iter);
-   mutex_unlock(_helper->lock);
-
-   return ret;
-}
-EXPORT_SYMBOL(drm_fb_helper_single_add_all_connectors);
-
-static int __drm_fb_helper_remove_one_connector(struct drm_fb_helper 
*fb_helper,
-   struct drm_connector *connector)
-{
-   struct drm_fb_helper_connector *fb_helper_connector;
-   int i, j;
-
-   if (!drm_fbdev_emulation)
-   return 0;
-
-   lockdep_assert_held(_helper->lock);
-
-   drm_fb_helper_for_each_connector(fb_helper, i) {
-   if (fb_helper->connector_info[i]->connector == connector)
-   break;
-   }
-
-   if (i == fb_helper->connector_count)
-   return -EINVAL;
-   fb_helper_connector = fb_helper->connector_info[i];
-   drm_connector_put(fb_helper_connector->connector);
-
-   for (j = i + 1; j < fb_helper->connector_count; j++)
-   fb_helper->connector_info[j - 1] = fb_helper->connector_info[j];
-
-   fb_helper->connector_count--;
-   kfree(fb_helper_connector);
-
return 0;
 }
+EXPORT_SYMBOL(drm_fb_helper_single_add_all_connectors);
 
 int drm_fb_helper_remove_one_connector(struct drm_fb_helper *fb_helper,
   struct drm_connector 

[Intel-gfx] [RFC v4 13/25] drm/fb-helper: Remove struct drm_fb_helper_crtc

[Noralf Trønnes]

The stage is now set for a clean removal of drm_fb_helper_crtc.
struct drm_client_display is doing its job now.

Also remove the drm_fb_helper_funcs->initial_config which has been
superseded by drm_driver->initial_client_display.

Signed-off-by: Noralf Trønnes 
---
 drivers/gpu/drm/drm_fb_helper.c | 124 +---
 include/drm/drm_fb_helper.h |  31 --
 2 files changed, 26 insertions(+), 129 deletions(-)

diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 5407bf6dc8c0..ce38eadcb346 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -443,24 +443,6 @@ int drm_fb_helper_blank(int blank, struct fb_info *info)
 }
 EXPORT_SYMBOL(drm_fb_helper_blank);
 
-static void drm_fb_helper_modeset_release(struct drm_fb_helper *helper,
- struct drm_mode_set *modeset)
-{
-   int i;
-
-   for (i = 0; i < modeset->num_connectors; i++) {
-   drm_connector_put(modeset->connectors[i]);
-   modeset->connectors[i] = NULL;
-   }
-   modeset->num_connectors = 0;
-
-   drm_mode_destroy(helper->dev, modeset->mode);
-   modeset->mode = NULL;
-
-   /* FIXME should hold a ref? */
-   modeset->fb = NULL;
-}
-
 static void drm_fb_helper_crtc_free(struct drm_fb_helper *helper)
 {
int i;
@@ -470,14 +452,6 @@ static void drm_fb_helper_crtc_free(struct drm_fb_helper 
*helper)
kfree(helper->connector_info[i]);
}
kfree(helper->connector_info);
-
-   for (i = 0; i < helper->crtc_count; i++) {
-   struct drm_mode_set *modeset = >crtc_info[i].mode_set;
-
-   drm_fb_helper_modeset_release(helper, modeset);
-   kfree(modeset->connectors);
-   }
-   kfree(helper->crtc_info);
 }
 
 static void drm_fb_helper_resume_worker(struct work_struct *work)
@@ -552,48 +526,18 @@ int drm_fb_helper_init(struct drm_device *dev,
   struct drm_fb_helper *fb_helper,
   int max_conn_count)
 {
-   struct drm_crtc *crtc;
-   struct drm_mode_config *config = >mode_config;
-   int i;
-
if (!drm_fbdev_emulation) {
dev->fb_helper = fb_helper;
return 0;
}
 
-   if (!max_conn_count)
-   return -EINVAL;
-
-   fb_helper->crtc_info = kcalloc(config->num_crtc, sizeof(struct 
drm_fb_helper_crtc), GFP_KERNEL);
-   if (!fb_helper->crtc_info)
-   return -ENOMEM;
-
-   fb_helper->crtc_count = config->num_crtc;
fb_helper->connector_info = kcalloc(dev->mode_config.num_connector, 
sizeof(struct drm_fb_helper_connector *), GFP_KERNEL);
-   if (!fb_helper->connector_info) {
-   kfree(fb_helper->crtc_info);
+   if (!fb_helper->connector_info)
return -ENOMEM;
-   }
+
fb_helper->connector_info_alloc_count = dev->mode_config.num_connector;
fb_helper->connector_count = 0;
 
-   for (i = 0; i < fb_helper->crtc_count; i++) {
-   fb_helper->crtc_info[i].mode_set.connectors =
-   kcalloc(max_conn_count,
-   sizeof(struct drm_connector *),
-   GFP_KERNEL);
-
-   if (!fb_helper->crtc_info[i].mode_set.connectors)
-   goto out_free;
-   fb_helper->crtc_info[i].mode_set.num_connectors = 0;
-   }
-
-   i = 0;
-   drm_for_each_crtc(crtc, dev) {
-   fb_helper->crtc_info[i].mode_set.crtc = crtc;
-   i++;
-   }
-
fb_helper->display = drm_client_display_create(dev);
if (IS_ERR(fb_helper->display))
goto out_free;
@@ -1830,7 +1774,7 @@ static bool drm_target_cloned(struct drm_fb_helper 
*fb_helper,
struct drm_display_mode *dmt_mode, *mode;
 
/* only contemplate cloning in the single crtc case */
-   if (fb_helper->crtc_count > 1)
+   if (fb_helper->dev->mode_config.num_crtc > 1)
return false;
 
count = 0;
@@ -1997,16 +1941,18 @@ static bool drm_target_preferred(struct drm_fb_helper 
*fb_helper,
 }
 
 static int drm_pick_crtcs(struct drm_fb_helper *fb_helper,
- struct drm_fb_helper_crtc **best_crtcs,
+ struct drm_crtc **best_crtcs,
  struct drm_display_mode **modes,
  int n, int width, int height)
 {
-   int c, o;
+   struct drm_client_display *display = fb_helper->display;
+   struct drm_device *dev = display->dev;
+   int o, my_score, best_score, score;
struct drm_connector *connector;
const struct drm_connector_helper_funcs *connector_funcs;
+   struct drm_mode_set *modeset;
struct drm_encoder *encoder;
-   int my_score, best_score, score;
-   struct drm_fb_helper_crtc **crtcs, *crtc;
+   struct 

[Intel-gfx] [RFC v4 19/25] drm/client: Finish the in-kernel client API

[Noralf Trønnes]

The modesetting code is already present, this adds the rest of the API.

Signed-off-by: Noralf Trønnes 
---
 drivers/gpu/drm/drm_client.c   | 573 +
 drivers/gpu/drm/drm_debugfs.c  |   7 +
 drivers/gpu/drm/drm_drv.c  |  11 +
 drivers/gpu/drm/drm_file.c |   3 +
 drivers/gpu/drm/drm_probe_helper.c |   3 +
 drivers/gpu/drm/drm_sysfs.c|  20 ++
 include/drm/drm_client.h   | 103 +++
 include/drm/drm_device.h   |   4 +
 8 files changed, 724 insertions(+)

diff --git a/drivers/gpu/drm/drm_client.c b/drivers/gpu/drm/drm_client.c
index bce1630a0db2..760f1795f812 100644
--- a/drivers/gpu/drm/drm_client.c
+++ b/drivers/gpu/drm/drm_client.c
@@ -8,7 +8,9 @@
  * Copyright (c) 2007 Dave Airlie 
  */
 
+#include 
 #include 
+#include 
 #include 
 
 #include 
@@ -17,14 +19,280 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
+#include "drm_crtc_internal.h"
 #include "drm_internal.h"
 
 struct drm_client_display_offset {
int x, y;
 };
 
+static int drm_client_alloc_file(struct drm_client_dev *client)
+{
+   struct drm_device *dev = client->dev;
+   struct drm_file *file;
+
+   file = drm_file_alloc(dev->primary);
+   if (IS_ERR(file))
+   return PTR_ERR(file);
+
+   drm_dev_get(dev);
+
+   mutex_lock(>filelist_mutex);
+   list_add(>lhead, >filelist_internal);
+   mutex_unlock(>filelist_mutex);
+
+   client->file = file;
+
+   return 0;
+}
+
+static void drm_client_free_file(struct drm_client_dev *client)
+{
+   struct drm_device *dev = client->dev;
+
+   mutex_lock(>filelist_mutex);
+   list_del(>file->lhead);
+   mutex_unlock(>filelist_mutex);
+
+   drm_file_free(client->file);
+   drm_dev_put(dev);
+}
+
+struct drm_client_dev *
+drm_client_new(struct drm_device *dev, const struct drm_client_funcs *funcs)
+{
+   struct drm_client_dev *client;
+   int ret;
+
+   if (WARN_ON(!funcs->name))
+   return ERR_PTR(-EINVAL);
+
+   client = kzalloc(sizeof(*client), GFP_KERNEL);
+   if (!client)
+   return ERR_PTR(-ENOMEM);
+
+   client->dev = dev;
+   client->funcs = funcs;
+
+   ret = drm_client_alloc_file(client);
+   if (ret) {
+   kfree(client);
+   return ERR_PTR(ret);
+   }
+
+   mutex_lock(>clientlist_mutex);
+   list_add(>list, >clientlist);
+   mutex_unlock(>clientlist_mutex);
+
+   return client;
+}
+EXPORT_SYMBOL(drm_client_new);
+
+struct drm_client_dev *
+drm_client_new_from_id(unsigned int dev_id, const struct drm_client_funcs 
*funcs)
+{
+   struct drm_client_dev *client;
+   struct drm_minor *minor;
+
+   minor = drm_minor_acquire(dev_id);
+   if (IS_ERR(minor))
+   return ERR_CAST(minor);
+
+   client = drm_client_new(minor->dev, funcs);
+
+   drm_minor_release(minor);
+
+   return client;
+}
+EXPORT_SYMBOL(drm_client_new_from_id);
+
+/**
+ * drm_client_free - Free DRM client resources
+ * @client: DRM client
+ *
+ * This is called automatically on client removal unless the client returns
+ * non-zero in the _client_funcs->remove callback. The fbdev client does
+ * this when it can't close _file because userspace has an open fd.
+ *
+ * Note:
+ * If the client can't release it's resources on remove, it needs to hold a
+ * reference on the driver module to prevent the code from going away.
+ */
+void drm_client_free(struct drm_client_dev *client)
+{
+   DRM_DEV_DEBUG_KMS(client->dev->dev, "%s\n", client->funcs->name);
+   drm_client_free_file(client);
+   kfree(client);
+}
+EXPORT_SYMBOL(drm_client_free);
+
+static void drm_client_remove_locked(struct drm_client_dev *client)
+{
+   list_del(>list);
+
+   if (!client->funcs->remove || !client->funcs->remove(client))
+   drm_client_free(client);
+}
+
+static void drm_client_remove_safe(struct drm_device *dev,
+  struct drm_client_dev *client)
+{
+   struct drm_client_dev *iter;
+
+   mutex_lock(>clientlist_mutex);
+   list_for_each_entry(iter, >clientlist, list) {
+   if (iter == client) {
+   drm_client_remove_locked(client);
+   break;
+   }
+   }
+   mutex_unlock(>clientlist_mutex);
+}
+
+/**
+ * drm_client_remove - Remove client
+ * @client: Client
+ *
+ * Remove a client.
+ */
+void drm_client_remove(struct drm_client_dev *client)
+{
+   struct drm_device *dev;
+
+   if (!client)
+   return;
+
+   dev = client->dev;
+   drm_dev_get(dev);
+   drm_client_remove_safe(dev, client);
+   drm_dev_put(dev);
+}
+EXPORT_SYMBOL(drm_client_remove);
+
+struct drm_client_remove_defer {
+   struct list_head list;
+   struct drm_device *dev;
+   struct drm_client_dev *client;
+};
+
+static LIST_HEAD(drm_client_remove_defer_list);

[Intel-gfx] [RFC v4 12/25] drm/i915: Add drm_driver->initial_client_display callback

[Noralf Trønnes]

As part of moving the modesetting code out of drm_fb_helper and into
drm_client, the drm_fb_helper_funcs->initial_config callback needs to go.
Replace it with a drm_driver->initial_client_display callback that can
work for all in-kernel clients.

TODO:
- Add a patch that moves the function out of intel_fbdev.c since it's not
  fbdev specific anymore.

Signed-off-by: Noralf Trønnes 
---
 drivers/gpu/drm/drm_fb_helper.c|  19 +--
 drivers/gpu/drm/i915/i915_drv.c|   1 +
 drivers/gpu/drm/i915/intel_drv.h   |  11 
 drivers/gpu/drm/i915/intel_fbdev.c | 113 ++---
 include/drm/drm_drv.h  |  21 +++
 5 files changed, 104 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index b992f59dad30..5407bf6dc8c0 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -2103,6 +2103,20 @@ static void drm_setup_crtcs(struct drm_fb_helper 
*fb_helper,
/* prevent concurrent modification of connector_count by hotplug */
lockdep_assert_held(_helper->lock);
 
+   mutex_lock(>mode_config.mutex);
+   if (drm_fb_helper_probe_connector_modes(fb_helper, width, height) == 0)
+   DRM_DEBUG_KMS("No connectors reported connected with modes\n");
+
+   if (dev->driver->initial_client_display) {
+   display = dev->driver->initial_client_display(dev, width, 
height);
+   if (display) {
+   drm_client_display_free(fb_helper->display);
+   fb_helper->display = display;
+   mutex_unlock(>mode_config.mutex);
+   return;
+   }
+   }
+
crtcs = kcalloc(fb_helper->connector_count,
sizeof(struct drm_fb_helper_crtc *), GFP_KERNEL);
modes = kcalloc(fb_helper->connector_count,
@@ -2120,9 +2134,6 @@ static void drm_setup_crtcs(struct drm_fb_helper 
*fb_helper,
if (IS_ERR(display))
goto out;
 
-   mutex_lock(_helper->dev->mode_config.mutex);
-   if (drm_fb_helper_probe_connector_modes(fb_helper, width, height) == 0)
-   DRM_DEBUG_KMS("No connectors reported connected with modes\n");
drm_enable_connectors(fb_helper, enabled);
 
if (!(fb_helper->funcs->initial_config &&
@@ -2144,7 +2155,6 @@ static void drm_setup_crtcs(struct drm_fb_helper 
*fb_helper,
 
drm_pick_crtcs(fb_helper, crtcs, modes, 0, width, height);
}
-   mutex_unlock(_helper->dev->mode_config.mutex);
 
/* need to set the modesets up here for use later */
/* fill out the connector<->crtc mappings into the modesets */
@@ -2182,6 +2192,7 @@ static void drm_setup_crtcs(struct drm_fb_helper 
*fb_helper,
drm_client_display_free(fb_helper->display);
fb_helper->display = display;
 out:
+   mutex_unlock(>mode_config.mutex);
kfree(crtcs);
kfree(modes);
kfree(offsets);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 07c07d55398b..b746c0cbaa4b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2857,6 +2857,7 @@ static struct drm_driver driver = {
 
.dumb_create = i915_gem_dumb_create,
.dumb_map_offset = i915_gem_mmap_gtt,
+   .initial_client_display = i915_initial_client_display,
.ioctls = i915_ioctls,
.num_ioctls = ARRAY_SIZE(i915_ioctls),
.fops = _driver_fops,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d4368589b355..f77f510617c5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1720,6 +1720,9 @@ extern void intel_fbdev_fini(struct drm_i915_private 
*dev_priv);
 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool 
synchronous);
 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
 extern void intel_fbdev_restore_mode(struct drm_device *dev);
+struct drm_client_display *
+i915_initial_client_display(struct drm_device *dev, unsigned int width,
+   unsigned int height);
 #else
 static inline int intel_fbdev_init(struct drm_device *dev)
 {
@@ -1749,6 +1752,14 @@ static inline void 
intel_fbdev_output_poll_changed(struct drm_device *dev)
 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
 {
 }
+
+static inline struct drm_client_display *
+i915_initial_client_display(struct drm_device *dev, unsigned int width,
+   unsigned int height)
+{
+   return NULL;
+}
+
 #endif
 
 /* intel_fbc.c */
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c 
b/drivers/gpu/drm/i915/intel_fbdev.c
index a4ab8575a72e..b7f44c9475a8 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -38,6 +38,7 @@
 #include 
 
 #include 
+#include 
 #include 
 #include 
 #include "intel_drv.h"
@@ 

[Intel-gfx] [RFC v4 08/25] drm/fb-helper: Use struct drm_client_display

[Noralf Trønnes]

Prepare to move the modeset committing code to drm_client.

Signed-off-by: Noralf Trønnes 
---
 drivers/gpu/drm/drm_fb_helper.c | 161 
 include/drm/drm_fb_helper.h |   8 ++
 2 files changed, 89 insertions(+), 80 deletions(-)

diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 2eef24db21f8..bdb4b57d2c12 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -35,6 +35,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -321,13 +322,14 @@ static bool drm_fb_helper_panel_rotation(struct 
drm_connector *connector,
return true;
 }
 
-static int restore_fbdev_mode_atomic(struct drm_fb_helper *fb_helper, bool 
active)
+static int drm_client_display_restore_atomic(struct drm_client_display 
*display, bool active)
 {
-   struct drm_device *dev = fb_helper->dev;
+   struct drm_device *dev = display->dev;
struct drm_plane_state *plane_state;
+   struct drm_mode_set *mode_set;
struct drm_plane *plane;
struct drm_atomic_state *state;
-   int i, ret;
+   int ret;
unsigned int plane_mask;
struct drm_modeset_acquire_ctx ctx;
 
@@ -363,8 +365,7 @@ static int restore_fbdev_mode_atomic(struct drm_fb_helper 
*fb_helper, bool activ
goto out_state;
}
 
-   for (i = 0; i < fb_helper->crtc_count; i++) {
-   struct drm_mode_set *mode_set = 
_helper->crtc_info[i].mode_set;
+   drm_client_display_for_each_modeset(mode_set, display) {
struct drm_plane *primary = mode_set->crtc->primary;
unsigned int rotation;
 
@@ -412,13 +413,14 @@ static int restore_fbdev_mode_atomic(struct drm_fb_helper 
*fb_helper, bool activ
goto retry;
 }
 
-static int restore_fbdev_mode_legacy(struct drm_fb_helper *fb_helper)
+static int drm_client_display_restore_legacy(struct drm_client_display 
*display)
 {
-   struct drm_device *dev = fb_helper->dev;
+   struct drm_device *dev = display->dev;
+   struct drm_mode_set *mode_set;
struct drm_plane *plane;
-   int i, ret = 0;
+   int ret = 0;
 
-   drm_modeset_lock_all(fb_helper->dev);
+   drm_modeset_lock_all(dev);
drm_for_each_plane(plane, dev) {
if (plane->type != DRM_PLANE_TYPE_PRIMARY)
drm_plane_force_disable(plane);
@@ -429,8 +431,7 @@ static int restore_fbdev_mode_legacy(struct drm_fb_helper 
*fb_helper)
DRM_MODE_ROTATE_0);
}
 
-   for (i = 0; i < fb_helper->crtc_count; i++) {
-   struct drm_mode_set *mode_set = 
_helper->crtc_info[i].mode_set;
+   drm_client_display_for_each_modeset(mode_set, display) {
struct drm_crtc *crtc = mode_set->crtc;
 
if (crtc->funcs->cursor_set2) {
@@ -448,19 +449,17 @@ static int restore_fbdev_mode_legacy(struct drm_fb_helper 
*fb_helper)
goto out;
}
 out:
-   drm_modeset_unlock_all(fb_helper->dev);
+   drm_modeset_unlock_all(dev);
 
return ret;
 }
 
-static int restore_fbdev_mode(struct drm_fb_helper *fb_helper)
+static int drm_client_display_restore(struct drm_client_display *display)
 {
-   struct drm_device *dev = fb_helper->dev;
-
-   if (drm_drv_uses_atomic_modeset(dev))
-   return restore_fbdev_mode_atomic(fb_helper, true);
+   if (drm_drv_uses_atomic_modeset(display->dev))
+   return drm_client_display_restore_atomic(display, true);
else
-   return restore_fbdev_mode_legacy(fb_helper);
+   return drm_client_display_restore_legacy(display);
 }
 
 /**
@@ -486,7 +485,7 @@ int drm_fb_helper_restore_fbdev_mode_unlocked(struct 
drm_fb_helper *fb_helper)
return 0;
 
mutex_lock(_helper->lock);
-   ret = restore_fbdev_mode(fb_helper);
+   ret = drm_client_display_restore(fb_helper->display);
 
do_delayed = fb_helper->delayed_hotplug;
if (do_delayed)
@@ -548,7 +547,7 @@ static bool drm_fb_helper_force_kernel_mode(void)
continue;
 
mutex_lock(>lock);
-   ret = restore_fbdev_mode(helper);
+   ret = drm_client_display_restore(helper->display);
if (ret)
error = true;
mutex_unlock(>lock);
@@ -580,22 +579,20 @@ static struct sysrq_key_op sysrq_drm_fb_helper_restore_op 
= {
 static struct sysrq_key_op sysrq_drm_fb_helper_restore_op = { };
 #endif
 
-static void dpms_legacy(struct drm_fb_helper *fb_helper, int dpms_mode)
+static void drm_client_display_dpms_legacy(struct drm_client_display *display, 
int dpms_mode)
 {
-   struct drm_device *dev = fb_helper->dev;
+   struct drm_device *dev = display->dev;
struct drm_connector *connector;
struct drm_mode_set *modeset;
-   

[Intel-gfx] [RFC v4 10/25] drm/connector: Add drm_connector_has_preferred_mode/pick_cmdline_mode()

[Noralf Trønnes]

Move them over from drm_fb_helper since they are connector functions.

Signed-off-by: Noralf Trønnes 
---
 drivers/gpu/drm/drm_connector.c| 94 ++
 drivers/gpu/drm/drm_fb_helper.c| 75 ++
 drivers/gpu/drm/i915/intel_fbdev.c |  7 +--
 include/drm/drm_connector.h|  6 +++
 include/drm/drm_fb_helper.h| 19 
 5 files changed, 108 insertions(+), 93 deletions(-)

diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index b3cde897cd80..b9eb143d70fc 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1760,3 +1760,97 @@ struct drm_tile_group *drm_mode_create_tile_group(struct 
drm_device *dev,
return tg;
 }
 EXPORT_SYMBOL(drm_mode_create_tile_group);
+
+/**
+ * drm_connector_has_preferred_mode() - Lookup preferred display mode
+ * @connector: DRM connector
+ * @width: Max width
+ * @height: Max height
+ *
+ * Look for a preferred display mode within the bounds of @width and @height
+ * (inclusive).
+ *
+ * Returns:
+ * A _display_mode or NULL.
+ */
+struct drm_display_mode *
+drm_connector_has_preferred_mode(struct drm_connector *connector,
+int width, int height)
+{
+   struct drm_display_mode *mode;
+
+   list_for_each_entry(mode, >modes, head) {
+   if (mode->hdisplay > width || mode->vdisplay > height)
+   continue;
+   if (mode->type & DRM_MODE_TYPE_PREFERRED)
+   return mode;
+   }
+
+   return NULL;
+}
+EXPORT_SYMBOL(drm_connector_has_preferred_mode);
+
+/**
+ * drm_connector_pick_cmdline_mode() - Get commandline display mode
+ * @connector: DRM connector
+ *
+ * Return the display mode specified on the kernel commandline or NULL if not
+ * specified.
+ *
+ * Returns:
+ * A _display_mode or NULL.
+ */
+struct drm_display_mode *
+drm_connector_pick_cmdline_mode(struct drm_connector *connector)
+{
+   struct drm_cmdline_mode *cmdline_mode;
+   struct drm_display_mode *mode;
+   bool prefer_non_interlace;
+
+   cmdline_mode = >cmdline_mode;
+   if (!cmdline_mode->specified)
+   return NULL;
+
+   /* attempt to find a matching mode in the list of modes
+*  we have gotten so far, if not add a CVT mode that conforms
+*/
+   if (cmdline_mode->rb || cmdline_mode->margins)
+   goto create_mode;
+
+   prefer_non_interlace = !cmdline_mode->interlace;
+again:
+   list_for_each_entry(mode, >modes, head) {
+   /* check width/height */
+   if (mode->hdisplay != cmdline_mode->xres ||
+   mode->vdisplay != cmdline_mode->yres)
+   continue;
+
+   if (cmdline_mode->refresh_specified) {
+   if (mode->vrefresh != cmdline_mode->refresh)
+   continue;
+   }
+
+   if (cmdline_mode->interlace) {
+   if (!(mode->flags & DRM_MODE_FLAG_INTERLACE))
+   continue;
+   } else if (prefer_non_interlace) {
+   if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+   continue;
+   }
+
+   return mode;
+   }
+
+   if (prefer_non_interlace) {
+   prefer_non_interlace = false;
+   goto again;
+   }
+
+create_mode:
+   mode = drm_mode_create_from_cmdline_mode(connector->dev,
+cmdline_mode);
+   list_add(>head, >modes);
+
+   return mode;
+}
+EXPORT_SYMBOL(drm_connector_pick_cmdline_mode);
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 785a2f5d2647..b992f59dad30 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -1774,78 +1774,11 @@ static int drm_fb_helper_probe_connector_modes(struct 
drm_fb_helper *fb_helper,
return count;
 }
 
-struct drm_display_mode *drm_has_preferred_mode(struct drm_fb_helper_connector 
*fb_connector, int width, int height)
-{
-   struct drm_display_mode *mode;
-
-   list_for_each_entry(mode, _connector->connector->modes, head) {
-   if (mode->hdisplay > width ||
-   mode->vdisplay > height)
-   continue;
-   if (mode->type & DRM_MODE_TYPE_PREFERRED)
-   return mode;
-   }
-   return NULL;
-}
-EXPORT_SYMBOL(drm_has_preferred_mode);
-
 static bool drm_has_cmdline_mode(struct drm_fb_helper_connector *fb_connector)
 {
return fb_connector->connector->cmdline_mode.specified;
 }
 
-struct drm_display_mode *drm_pick_cmdline_mode(struct drm_fb_helper_connector 
*fb_helper_conn)
-{
-   struct drm_cmdline_mode *cmdline_mode;
-   struct drm_display_mode *mode;
-   bool prefer_non_interlace;
-
-   cmdline_mode = 

[Intel-gfx] [RFC v4 11/25] drm/connector: Add connector array functions

[Noralf Trønnes]

Add functions to deal with the registred connectors as an array:
- drm_connector_get_all()
- drm_connector_put_all()

And to get the enabled status of those connectors:
drm_connector_get_enabled_status()

This is prep work to remove struct drm_fb_helper_connector.

Signed-off-by: Noralf Trønnes 
---
 drivers/gpu/drm/drm_connector.c | 105 
 include/drm/drm_connector.h |   5 ++
 2 files changed, 110 insertions(+)

diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index b9eb143d70fc..25c333c05a4e 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1854,3 +1854,108 @@ drm_connector_pick_cmdline_mode(struct drm_connector 
*connector)
return mode;
 }
 EXPORT_SYMBOL(drm_connector_pick_cmdline_mode);
+
+/**
+ * drm_connector_get_all - Get all connectors into an array
+ * @dev: DRM device
+ * @connectors: Returned connector array
+ *
+ * This function iterates through all registered connectors and adds them to an
+ * array allocated by this function. A ref is taken on the connectors.
+ *
+ * Use drm_connector_put_all() to drop refs and free the array.
+ *
+ * Returns:
+ * Number of connectors or -ENOMEM on failure.
+ */
+int drm_connector_get_all(struct drm_device *dev, struct drm_connector 
***connectors)
+{
+   struct drm_connector *connector, **temp, **conns = NULL;
+   struct drm_connector_list_iter conn_iter;
+   int connector_count = 0;
+
+   drm_connector_list_iter_begin(dev, _iter);
+   drm_for_each_connector_iter(connector, _iter) {
+   temp = krealloc(conns, (connector_count + 1) * sizeof(*conns), 
GFP_KERNEL);
+   if (!temp)
+   goto err_put_free;
+
+   conns = temp;
+   conns[connector_count++] = connector;
+   drm_connector_get(connector);
+   }
+   drm_connector_list_iter_end(_iter);
+
+   *connectors = conns;
+
+   return connector_count;
+
+err_put_free:
+   drm_connector_list_iter_end(_iter);
+   drm_connector_put_all(conns, connector_count);
+
+   return -ENOMEM;
+}
+EXPORT_SYMBOL(drm_connector_get_all);
+
+/**
+ * drm_connector_put_all - Put and free connector array
+ * @connectors: Array of connectors
+ * @connector_count: Number of connectors in the array (can be negative or 
zero)
+ *
+ * This function drops the ref on the connectors an frees the array.
+ */
+void drm_connector_put_all(struct drm_connector **connectors, int 
connector_count)
+{
+   int i;
+
+   if (connector_count < 1)
+   return;
+
+   for (i = 0; i < connector_count; i++)
+   drm_connector_put(connectors[i]);
+   kfree(connectors);
+}
+EXPORT_SYMBOL(drm_connector_put_all);
+
+/**
+ * drm_connector_get_enabled_status - Get enabled status on connectors
+ * @connectors: Array of connectors
+ * @connector_count: Number of connectors in the array
+ *
+ * This loops over the connector array and sets enabled if connector status is
+ * _connected_. If no connectors are connected, a new pass is done and
+ * connectors that are not _disconnected_ are set enabled.
+ *
+ * The caller is responsible for freeing the array using kfree().
+ *
+ * Returns:
+ * A boolean array of connector enabled statuses or NULL on allocation failure.
+ */
+bool *drm_connector_get_enabled_status(struct drm_connector **connectors,
+  unsigned int connector_count)
+{
+   bool *enabled, any_enabled = false;
+   unsigned int i;
+
+   enabled = kcalloc(connector_count, sizeof(*enabled), GFP_KERNEL);
+   if (!enabled)
+   return NULL;
+
+   for (i = 0; i < connector_count; i++) {
+   if (connectors[i]->status == connector_status_connected) {
+   enabled[i] = true;
+   any_enabled = true;
+   }
+   }
+
+   if (any_enabled)
+   return enabled;
+
+   for (i = 0; i < connector_count; i++)
+   if (connectors[i]->status != connector_status_disconnected)
+   enabled[i] = true;
+
+   return enabled;
+}
+EXPORT_SYMBOL(drm_connector_get_enabled_status);
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 9cb4ca42373c..c3556a5f40c9 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -1169,4 +1169,9 @@ drm_connector_has_preferred_mode(struct drm_connector 
*connector,
 struct drm_display_mode *
 drm_connector_pick_cmdline_mode(struct drm_connector *connector);
 
+int drm_connector_get_all(struct drm_device *dev, struct drm_connector 
***connectors);
+void drm_connector_put_all(struct drm_connector **connectors, int 
connector_count);
+bool *drm_connector_get_enabled_status(struct drm_connector **connectors,
+  unsigned int connector_count);
+
 #endif
-- 
2.15.1

[Intel-gfx] [RFC v4 07/25] drm: Begin an API for in-kernel clients

[Noralf Trønnes]

This the beginning of an API for in-kernel clients.
First out is a display representation that will be used by drm_fb_helper
in order to move out its mode setting code.

Signed-off-by: Noralf Trønnes 
---
 drivers/gpu/drm/Makefile |   2 +-
 drivers/gpu/drm/drm_client.c | 119 +++
 include/drm/drm_client.h |  44 
 3 files changed, 164 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/drm_client.c
 create mode 100644 include/drm/drm_client.h

diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 9d66657ea117..d25afa136d8f 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -18,7 +18,7 @@ drm-y   :=drm_auth.o drm_bufs.o drm_cache.o \
drm_encoder.o drm_mode_object.o drm_property.o \
drm_plane.o drm_color_mgmt.o drm_print.o \
drm_dumb_buffers.o drm_mode_config.o drm_vblank.o \
-   drm_syncobj.o drm_lease.o
+   drm_syncobj.o drm_lease.o drm_client.o
 
 drm-$(CONFIG_DRM_LIB_RANDOM) += lib/drm_random.o
 drm-$(CONFIG_DRM_VM) += drm_vm.o
diff --git a/drivers/gpu/drm/drm_client.c b/drivers/gpu/drm/drm_client.c
new file mode 100644
index ..7c31a6efb2f4
--- /dev/null
+++ b/drivers/gpu/drm/drm_client.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018 Noralf Trønnes
+ *
+ * For parts copied from drm_fb_helper:
+ * Copyright (c) 2006-2009 Red Hat Inc.
+ * Copyright (c) 2006-2008 Intel Corporation
+ * Copyright (c) 2007 Dave Airlie 
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * drm_client_display_create() - Create display structure
+ * @dev: DRM device
+ *
+ * This function creates a display structure for clients backed by an array of
+ * _mode_set, one per CRTC.
+ *
+ * Returns:
+ * A _client_display or an error pointer on allocation failure.
+ */
+struct drm_client_display *drm_client_display_create(struct drm_device *dev)
+{
+   unsigned int num_crtc = dev->mode_config.num_crtc;
+   struct drm_client_display *display;
+   struct drm_mode_set *modeset;
+   struct drm_crtc *crtc;
+   unsigned int i = 0;
+
+   display = kzalloc(sizeof(*display), GFP_KERNEL);
+   if (!display)
+   return ERR_PTR(-ENOMEM);
+
+   /* Add NULL terminating entry to enable index less iteration */
+   display->modesets = kcalloc(num_crtc + 1, sizeof(*display->modesets), 
GFP_KERNEL);
+   if (!display->modesets) {
+   kfree(display);
+   return ERR_PTR(-ENOMEM);
+   }
+
+   display->dev = dev;
+   display->modeset_count = num_crtc;
+
+   drm_for_each_crtc(crtc, dev)
+   display->modesets[i++].crtc = crtc;
+
+   drm_client_display_for_each_modeset(modeset, display) {
+   /* One connector per crtc except for the cloned case */
+   modeset->connectors = kcalloc(2, sizeof(*modeset->connectors), 
GFP_KERNEL);
+   if (!modeset->connectors)
+   goto err_free;
+   }
+
+   return display;
+
+err_free:
+   drm_client_display_free(display);
+
+   return ERR_PTR(-ENOMEM);
+}
+EXPORT_SYMBOL(drm_client_display_create);
+
+/**
+ * drm_client_display_free() - Free display structure
+ * @display: Client display
+ *
+ * This function frees the structure allocated by drm_client_display_create().
+ * It also destroys display modes and puts connectors.
+ */
+void drm_client_display_free(struct drm_client_display *display)
+{
+   struct drm_mode_set *modeset;
+   unsigned int i;
+
+   if (!display)
+   return;
+
+   drm_client_display_for_each_modeset(modeset, display) {
+   if (modeset->mode)
+   drm_mode_destroy(display->dev, modeset->mode);
+
+   for (i = 0; i < modeset->num_connectors; i++)
+   drm_connector_put(modeset->connectors[i]);
+   kfree(modeset->connectors);
+   }
+   kfree(display->modesets);
+   kfree(display);
+}
+EXPORT_SYMBOL(drm_client_display_free);
+
+/**
+ * drm_client_display_find_modeset() - Find modeset matching a CRTC
+ * @display: Client display
+ * @crtc: CRTC
+ *
+ * This function looks up the @display modeset connected to @crtc.
+ *
+ * Returns:
+ * A _mode_set or NULL.
+ */
+struct drm_mode_set *
+drm_client_display_find_modeset(struct drm_client_display *display, struct 
drm_crtc *crtc)
+{
+   struct drm_mode_set *modeset;
+
+   drm_client_display_for_each_modeset(modeset, display)
+   if (modeset->crtc == crtc)
+   return modeset;
+
+   return NULL;
+}
+EXPORT_SYMBOL(drm_client_display_find_modeset);
diff --git a/include/drm/drm_client.h b/include/drm/drm_client.h
new file mode 100644
index ..b6a057802769
--- /dev/null
+++ b/include/drm/drm_client.h
@@ -0,0 +1,44 @@
+/* 

[Intel-gfx] [RFC v4 05/25] drm/fb-helper: dpms_legacy(): Only set on connectors in use

[Noralf Trønnes]

For each enabled crtc the functions sets dpms on all registered connectors.
Limit this to only doing it once and on the connectors actually in use.

Signed-off-by: Noralf Trønnes 
---
 drivers/gpu/drm/drm_fb_helper.c | 11 +--
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 06e94de6452a..d0936671a9a6 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -583,20 +583,19 @@ static struct sysrq_key_op sysrq_drm_fb_helper_restore_op 
= { };
 static void dpms_legacy(struct drm_fb_helper *fb_helper, int dpms_mode)
 {
struct drm_device *dev = fb_helper->dev;
-   struct drm_crtc *crtc;
struct drm_connector *connector;
+   struct drm_mode_set *modeset;
int i, j;
 
drm_modeset_lock_all(dev);
for (i = 0; i < fb_helper->crtc_count; i++) {
-   crtc = fb_helper->crtc_info[i].mode_set.crtc;
+   modeset = _helper->crtc_info[i].mode_set;
 
-   if (!crtc->enabled)
+   if (!modeset->crtc->enabled)
continue;
 
-   /* Walk the connectors & encoders on this fb turning them 
on/off */
-   drm_fb_helper_for_each_connector(fb_helper, j) {
-   connector = fb_helper->connector_info[j]->connector;
+   for (j = 0; j < modeset->num_connectors; j++) {
+   connector = modeset->connectors[j];
connector->funcs->dpms(connector, dpms_mode);
drm_object_property_set_value(>base,
dev->mode_config.dpms_property, dpms_mode);
-- 
2.15.1

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[Intel-gfx] [RFC v4 00/25] drm: Add generic fbdev emulation

[Noralf Trønnes]

This patchset explores the possibility of having generic fbdev emulation
in DRM for drivers that supports dumb buffers which they can export. An
API is added to support in-kernel clients in general.

In this version I was able to reuse the modesetting code from
drm_fb_helper in the client API. This avoids code duplication, carries
over lessons learned and the modesetting code is bisectable. The
downside is that it takes +10 patches to rip drm_fb_helper in two, so
maybe it's not worth it wrt possible breakage and a challenging review.

Does the Intel CI test the fbdev emulation?

Daniel had this concern with the previous version:

The register/unregister model needs more thought. Allowing both clients
to register whenever they want to, and drm_device instances to come and
go is what fbcon has done, and the resulting locking is a horror show.

I think if we require that all in-kernel drm_clients are registers when
loading drm.ko (and enabled/disabled only per module options and
Kconfig), then we can throw out all the locking. That avoids a lot of
the headaches.

I have solved this by adding a notifier that fires when a new DRM device
is registered (I've removed the new() callback). Currently only
bootsplash uses this. The fbdev client needs to be setup from the driver
since it can't know on device registration if the driver will setup it's
own fbdev emulation later and the vtcon client hooks up to a user
provided device id.

Since fbcon can't handle fb_open failing, the buffer has to be
pre-allocated. Exporting a GEM buffer pins the driver module making it
impossible to unload it.
I have included 2 solutions to the problem:
- sysfs file to remove/close clients: remove_internal_clients
- Change drm_gem_prime_export() so it doesn't pin on client buffers

If a dumb buffer is exported from a kernel thread (worker) context, the
file descriptor isn't closed and I leak a reference so the buffer isn't
freed. Please look at drm_client_buffer_create() in patch
'drm/client: Finish the in-kernel client API'.
This is a blocker that needs a solution.


Noralf.

Changes since version 3:
Client API changes:
- Drop drm_client_register_funcs() which attached clients indirectly.
  Let clients attach directly using drm_client_new{_from_id}(). Clients
  that wants to attach to all devices must be linked into drm.ko and use
  the DRM device notifier. This is done to avoid the lock/race
  register/unregister hell we have with fbcon. (Daniel Vetter)
- drm_client_display_restore() checks if there is a master and if so
  returns -EBUSY. (Daniel Vetter)
- Allocate drm_file up front instead of on-demand. Since fbdev can't do
  on demand buffer allocation because of fbcon, there's no need for this.
- Add sysfs file to remove clients
- Don't pin driver module when exporting gem client buffers
- Dropped page flip support since drm_fb_helper is now used for fbdev
  emulation.

- The bootsplash client now switches over to fbdev on keypress.

Changes since version 2:
- Don't set drm master for in-kernel clients. (Daniel Vetter)
- Add in-kernel client API

Changes since version 1:
- Don't add drm_fb_helper_fb_open() and drm_fb_helper_fb_release() to
  DRM_FB_HELPER_DEFAULT_OPS(). (Fi.CI.STATIC)
  The following uses that macro and sets fb_open/close: udlfb_ops,
  amdgpufb_ops, drm_fb_helper_generic_fbdev_ops, nouveau_fbcon_ops,
  nouveau_fbcon_sw_ops, radeonfb_ops.
  This results in: warning: Initializer entry defined twice
- Support CONFIG_DRM_KMS_HELPER=m (kbuild test robot)
  ERROR:  [drivers/gpu/drm/drm_kms_helper.ko] undefined!
- Drop buggy patch: (Chris Wilson)
  drm/prime: Clear drm_gem_object->dma_buf on release
- Defer buffer creation until fb_open.


David Herrmann (1):
  drm: provide management functions for drm_file

Noralf Trønnes (24):
  drm/file: Don't set master on in-kernel clients
  drm/fb-helper: No need to cache rotation and sw_rotations
  drm/fb-helper: Remove drm_fb_helper_debug_enter/leave()
  drm/fb-helper: dpms_legacy(): Only set on connectors in use
  drm/atomic: Move __drm_atomic_helper_disable_plane/set_config()
  drm: Begin an API for in-kernel clients
  drm/fb-helper: Use struct drm_client_display
  drm/fb-helper: Move modeset commit code to drm_client
  drm/connector: Add
drm_connector_has_preferred_mode/pick_cmdline_mode()
  drm/connector: Add connector array functions
  drm/i915: Add drm_driver->initial_client_display callback
  drm/fb-helper: Remove struct drm_fb_helper_crtc
  drm/fb-helper: Remove struct drm_fb_helper_connector
  drm/fb-helper: Move modeset config code to drm_client
  drm: Make ioctls available for in-kernel clients
  drm/client: Bail out if there's a DRM master
  drm/client: Make the display modes available to clients
  drm/client: Finish the in-kernel client API
  drm/prime: Don't pin module on export for in-kernel clients
  drm/fb-helper: Add drm_fb_helper_fb_open/release()
  drm/fb-helper: Add generic fbdev emulation
  drm: Add DRM device registered 

[Intel-gfx] [RFC v4 03/25] drm/fb-helper: No need to cache rotation and sw_rotations

[Noralf Trønnes]

Getting rotation info is cheap so we can do it on demand.

This is done in preparation for the removal of struct drm_fb_helper_crtc.

Cc: Hans de Goede 
Signed-off-by: Noralf Trønnes 
---
 drivers/gpu/drm/drm_fb_helper.c | 131 
 include/drm/drm_fb_helper.h |   8 ---
 2 files changed, 65 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 0646b108030b..e48ace2d55f5 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -361,6 +361,48 @@ int drm_fb_helper_debug_leave(struct fb_info *info)
 }
 EXPORT_SYMBOL(drm_fb_helper_debug_leave);
 
+/* Check if the plane can hw rotate to match panel orientation */
+static bool drm_fb_helper_panel_rotation(struct drm_connector *connector,
+struct drm_plane *plane,
+unsigned int *rotation)
+{
+   uint64_t valid_mask = 0;
+   unsigned int i;
+
+   if (!connector)
+   return false;
+
+   switch (connector->display_info.panel_orientation) {
+   case DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP:
+   *rotation = DRM_MODE_ROTATE_180;
+   break;
+   case DRM_MODE_PANEL_ORIENTATION_LEFT_UP:
+   *rotation = DRM_MODE_ROTATE_90;
+   break;
+   case DRM_MODE_PANEL_ORIENTATION_RIGHT_UP:
+   *rotation = DRM_MODE_ROTATE_270;
+   break;
+   default:
+   *rotation = DRM_MODE_ROTATE_0;
+   }
+
+   /*
+* TODO: support 90 / 270 degree hardware rotation,
+* depending on the hardware this may require the framebuffer
+* to be in a specific tiling format.
+*/
+   if (*rotation != DRM_MODE_ROTATE_180 || !plane->rotation_property)
+   return false;
+
+   for (i = 0; i < plane->rotation_property->num_values; i++)
+   valid_mask |= (1ULL << plane->rotation_property->values[i]);
+
+   if (!(*rotation & valid_mask))
+   return false;
+
+   return true;
+}
+
 static int restore_fbdev_mode_atomic(struct drm_fb_helper *fb_helper, bool 
active)
 {
struct drm_device *dev = fb_helper->dev;
@@ -406,10 +448,13 @@ static int restore_fbdev_mode_atomic(struct drm_fb_helper 
*fb_helper, bool activ
for (i = 0; i < fb_helper->crtc_count; i++) {
struct drm_mode_set *mode_set = 
_helper->crtc_info[i].mode_set;
struct drm_plane *primary = mode_set->crtc->primary;
+   unsigned int rotation;
 
-   /* Cannot fail as we've already gotten the plane state above */
-   plane_state = drm_atomic_get_new_plane_state(state, primary);
-   plane_state->rotation = fb_helper->crtc_info[i].rotation;
+   if (drm_fb_helper_panel_rotation(mode_set->connectors[0], 
primary, )) {
+   /* Cannot fail as we've already gotten the plane state 
above */
+   plane_state = drm_atomic_get_new_plane_state(state, 
primary);
+   plane_state->rotation = rotation;
+   }
 
ret = __drm_atomic_helper_set_config(mode_set, state);
if (ret != 0)
@@ -841,7 +886,6 @@ int drm_fb_helper_init(struct drm_device *dev,
if (!fb_helper->crtc_info[i].mode_set.connectors)
goto out_free;
fb_helper->crtc_info[i].mode_set.num_connectors = 0;
-   fb_helper->crtc_info[i].rotation = DRM_MODE_ROTATE_0;
}
 
i = 0;
@@ -2414,62 +2458,6 @@ static int drm_pick_crtcs(struct drm_fb_helper 
*fb_helper,
return best_score;
 }
 
-/*
- * This function checks if rotation is necessary because of panel orientation
- * and if it is, if it is supported.
- * If rotation is necessary and supported, its gets set in fb_crtc.rotation.
- * If rotation is necessary but not supported, a DRM_MODE_ROTATE_* flag gets
- * or-ed into fb_helper->sw_rotations. In drm_setup_crtcs_fb() we check if only
- * one bit is set and then we set fb_info.fbcon_rotate_hint to make fbcon do
- * the unsupported rotation.
- */
-static void drm_setup_crtc_rotation(struct drm_fb_helper *fb_helper,
-   struct drm_fb_helper_crtc *fb_crtc,
-   struct drm_connector *connector)
-{
-   struct drm_plane *plane = fb_crtc->mode_set.crtc->primary;
-   uint64_t valid_mask = 0;
-   int i, rotation;
-
-   fb_crtc->rotation = DRM_MODE_ROTATE_0;
-
-   switch (connector->display_info.panel_orientation) {
-   case DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP:
-   rotation = DRM_MODE_ROTATE_180;
-   break;
-   case DRM_MODE_PANEL_ORIENTATION_LEFT_UP:
-   rotation = DRM_MODE_ROTATE_90;
-   break;
-   case DRM_MODE_PANEL_ORIENTATION_RIGHT_UP:
-   

[Intel-gfx] [RFC v4 04/25] drm/fb-helper: Remove drm_fb_helper_debug_enter/leave()

[Noralf Trønnes]

Atomic drivers can't use them so finish what was started in
commit 9c79e0b1d096 ("drm/fb-helper: Give up on kgdb for atomic drivers").

This prepares the ground for creating modesets on demand.

TODO:
- Actually remove the functions, not just the contents.
- Nuke drm_crtc_helper_funcs->mode_set_base_atomic
- Documentation/dev-tools/kgdb.rst

Signed-off-by: Noralf Trønnes 
---
 drivers/gpu/drm/drm_fb_helper.c | 82 -
 1 file changed, 82 deletions(-)

diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index e48ace2d55f5..06e94de6452a 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -267,96 +267,14 @@ int drm_fb_helper_remove_one_connector(struct 
drm_fb_helper *fb_helper,
 }
 EXPORT_SYMBOL(drm_fb_helper_remove_one_connector);
 
-static void drm_fb_helper_restore_lut_atomic(struct drm_crtc *crtc)
-{
-   uint16_t *r_base, *g_base, *b_base;
-
-   if (crtc->funcs->gamma_set == NULL)
-   return;
-
-   r_base = crtc->gamma_store;
-   g_base = r_base + crtc->gamma_size;
-   b_base = g_base + crtc->gamma_size;
-
-   crtc->funcs->gamma_set(crtc, r_base, g_base, b_base,
-  crtc->gamma_size, NULL);
-}
-
-/**
- * drm_fb_helper_debug_enter - implementation for _ops.fb_debug_enter
- * @info: fbdev registered by the helper
- */
 int drm_fb_helper_debug_enter(struct fb_info *info)
 {
-   struct drm_fb_helper *helper = info->par;
-   const struct drm_crtc_helper_funcs *funcs;
-   int i;
-
-   list_for_each_entry(helper, _fb_helper_list, kernel_fb_list) {
-   for (i = 0; i < helper->crtc_count; i++) {
-   struct drm_mode_set *mode_set =
-   >crtc_info[i].mode_set;
-
-   if (!mode_set->crtc->enabled)
-   continue;
-
-   funcs = mode_set->crtc->helper_private;
-   if (funcs->mode_set_base_atomic == NULL)
-   continue;
-
-   if (drm_drv_uses_atomic_modeset(mode_set->crtc->dev))
-   continue;
-
-   funcs->mode_set_base_atomic(mode_set->crtc,
-   mode_set->fb,
-   mode_set->x,
-   mode_set->y,
-   ENTER_ATOMIC_MODE_SET);
-   }
-   }
-
return 0;
 }
 EXPORT_SYMBOL(drm_fb_helper_debug_enter);
 
-/**
- * drm_fb_helper_debug_leave - implementation for _ops.fb_debug_leave
- * @info: fbdev registered by the helper
- */
 int drm_fb_helper_debug_leave(struct fb_info *info)
 {
-   struct drm_fb_helper *helper = info->par;
-   struct drm_crtc *crtc;
-   const struct drm_crtc_helper_funcs *funcs;
-   struct drm_framebuffer *fb;
-   int i;
-
-   for (i = 0; i < helper->crtc_count; i++) {
-   struct drm_mode_set *mode_set = >crtc_info[i].mode_set;
-
-   crtc = mode_set->crtc;
-   if (drm_drv_uses_atomic_modeset(crtc->dev))
-   continue;
-
-   funcs = crtc->helper_private;
-   fb = crtc->primary->fb;
-
-   if (!crtc->enabled)
-   continue;
-
-   if (!fb) {
-   DRM_ERROR("no fb to restore??\n");
-   continue;
-   }
-
-   if (funcs->mode_set_base_atomic == NULL)
-   continue;
-
-   drm_fb_helper_restore_lut_atomic(mode_set->crtc);
-   funcs->mode_set_base_atomic(mode_set->crtc, fb, crtc->x,
-   crtc->y, LEAVE_ATOMIC_MODE_SET);
-   }
-
return 0;
 }
 EXPORT_SYMBOL(drm_fb_helper_debug_leave);
-- 
2.15.1

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[Intel-gfx] [RFC v4 09/25] drm/fb-helper: Move modeset commit code to drm_client

[Noralf Trønnes]

This moves the committing part of the modesetting code to drm_client.

Signed-off-by: Noralf Trønnes 
---
 drivers/gpu/drm/drm_client.c| 242 
 drivers/gpu/drm/drm_fb_helper.c | 216 +--
 include/drm/drm_client.h|   8 ++
 3 files changed, 252 insertions(+), 214 deletions(-)

diff --git a/drivers/gpu/drm/drm_client.c b/drivers/gpu/drm/drm_client.c
index 7c31a6efb2f4..c85c13568cf9 100644
--- a/drivers/gpu/drm/drm_client.c
+++ b/drivers/gpu/drm/drm_client.c
@@ -10,6 +10,8 @@
 
 #include 
 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -117,3 +119,243 @@ drm_client_display_find_modeset(struct drm_client_display 
*display, struct drm_c
return NULL;
 }
 EXPORT_SYMBOL(drm_client_display_find_modeset);
+
+/**
+ * drm_client_display_panel_rotation() - Check panel orientation
+ * @connector: DRM connector
+ * @plane: DRM plane
+ * @rotation: Returned rotation value
+ *
+ * This function checks if @plane can hw rotate to match the panel orientation
+ * on @connector.
+ *
+ * Return:
+ * True if the plane can do the rotation, false otherwise.
+ */
+bool drm_client_display_panel_rotation(struct drm_connector *connector,
+  struct drm_plane *plane,
+  unsigned int *rotation)
+{
+   uint64_t valid_mask = 0;
+   unsigned int i;
+
+   if (!connector)
+   return false;
+
+   switch (connector->display_info.panel_orientation) {
+   case DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP:
+   *rotation = DRM_MODE_ROTATE_180;
+   break;
+   case DRM_MODE_PANEL_ORIENTATION_LEFT_UP:
+   *rotation = DRM_MODE_ROTATE_90;
+   break;
+   case DRM_MODE_PANEL_ORIENTATION_RIGHT_UP:
+   *rotation = DRM_MODE_ROTATE_270;
+   break;
+   default:
+   *rotation = DRM_MODE_ROTATE_0;
+   }
+
+   /*
+* TODO: support 90 / 270 degree hardware rotation,
+* depending on the hardware this may require the framebuffer
+* to be in a specific tiling format.
+*/
+   if (*rotation != DRM_MODE_ROTATE_180 || !plane->rotation_property)
+   return false;
+
+   for (i = 0; i < plane->rotation_property->num_values; i++)
+   valid_mask |= (1ULL << plane->rotation_property->values[i]);
+
+   if (!(*rotation & valid_mask))
+   return false;
+
+   return true;
+}
+EXPORT_SYMBOL(drm_client_display_panel_rotation);
+
+static int drm_client_display_restore_atomic(struct drm_client_display 
*display, bool active)
+{
+   struct drm_device *dev = display->dev;
+   struct drm_plane_state *plane_state;
+   struct drm_mode_set *mode_set;
+   struct drm_plane *plane;
+   struct drm_atomic_state *state;
+   int ret;
+   unsigned int plane_mask;
+   struct drm_modeset_acquire_ctx ctx;
+
+   drm_modeset_acquire_init(, 0);
+
+   state = drm_atomic_state_alloc(dev);
+   if (!state) {
+   ret = -ENOMEM;
+   goto out_ctx;
+   }
+
+   state->acquire_ctx = 
+retry:
+   plane_mask = 0;
+   drm_for_each_plane(plane, dev) {
+   plane_state = drm_atomic_get_plane_state(state, plane);
+   if (IS_ERR(plane_state)) {
+   ret = PTR_ERR(plane_state);
+   goto out_state;
+   }
+
+   plane_state->rotation = DRM_MODE_ROTATE_0;
+
+   plane->old_fb = plane->fb;
+   plane_mask |= 1 << drm_plane_index(plane);
+
+   /* disable non-primary: */
+   if (plane->type == DRM_PLANE_TYPE_PRIMARY)
+   continue;
+
+   ret = drm_atomic_disable_plane(plane, plane_state);
+   if (ret != 0)
+   goto out_state;
+   }
+
+   drm_client_display_for_each_modeset(mode_set, display) {
+   struct drm_plane *primary = mode_set->crtc->primary;
+   unsigned int rotation;
+
+   if (drm_client_display_panel_rotation(mode_set->connectors[0], 
primary, )) {
+   /* Cannot fail as we've already gotten the plane state 
above */
+   plane_state = drm_atomic_get_new_plane_state(state, 
primary);
+   plane_state->rotation = rotation;
+   }
+
+   ret = drm_atomic_set_config(mode_set, state);
+   if (ret != 0)
+   goto out_state;
+
+   /*
+* drm_atomic_set_config() sets active when a
+* mode is set, unconditionally clear it if we force DPMS off
+*/
+   if (!active) {
+   struct drm_crtc *crtc = mode_set->crtc;
+   struct drm_crtc_state *crtc_state = 
drm_atomic_get_new_crtc_state(state, crtc);
+
+   

[Intel-gfx] [RFC v4 06/25] drm/atomic: Move __drm_atomic_helper_disable_plane/set_config()

[Noralf Trønnes]

Prepare for moving drm_fb_helper modesetting code to drm_client.
drm_client will be linked to drm.ko, so move
__drm_atomic_helper_disable_plane() and __drm_atomic_helper_set_config()
out of drm_kms_helper.ko.

Signed-off-by: Noralf Trønnes 
---
 drivers/gpu/drm/drm_atomic.c| 168 
 drivers/gpu/drm/drm_atomic_helper.c | 168 +---
 drivers/gpu/drm/drm_fb_helper.c |   8 +-
 include/drm/drm_atomic.h|   5 ++
 include/drm/drm_atomic_helper.h |   4 -
 5 files changed, 179 insertions(+), 174 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 7d25c42f22db..1fb602b6c8b1 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -2060,6 +2060,174 @@ void drm_atomic_clean_old_fb(struct drm_device *dev,
 }
 EXPORT_SYMBOL(drm_atomic_clean_old_fb);
 
+/* just used from drm_client and atomic-helper: */
+int drm_atomic_disable_plane(struct drm_plane *plane,
+struct drm_plane_state *plane_state)
+{
+   int ret;
+
+   ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
+   if (ret != 0)
+   return ret;
+
+   drm_atomic_set_fb_for_plane(plane_state, NULL);
+   plane_state->crtc_x = 0;
+   plane_state->crtc_y = 0;
+   plane_state->crtc_w = 0;
+   plane_state->crtc_h = 0;
+   plane_state->src_x = 0;
+   plane_state->src_y = 0;
+   plane_state->src_w = 0;
+   plane_state->src_h = 0;
+
+   return 0;
+}
+EXPORT_SYMBOL(drm_atomic_disable_plane);
+
+static int update_output_state(struct drm_atomic_state *state,
+  struct drm_mode_set *set)
+{
+   struct drm_device *dev = set->crtc->dev;
+   struct drm_crtc *crtc;
+   struct drm_crtc_state *new_crtc_state;
+   struct drm_connector *connector;
+   struct drm_connector_state *new_conn_state;
+   int ret, i;
+
+   ret = drm_modeset_lock(>mode_config.connection_mutex,
+  state->acquire_ctx);
+   if (ret)
+   return ret;
+
+   /* First disable all connectors on the target crtc. */
+   ret = drm_atomic_add_affected_connectors(state, set->crtc);
+   if (ret)
+   return ret;
+
+   for_each_new_connector_in_state(state, connector, new_conn_state, i) {
+   if (new_conn_state->crtc == set->crtc) {
+   ret = drm_atomic_set_crtc_for_connector(new_conn_state,
+   NULL);
+   if (ret)
+   return ret;
+
+   /* Make sure legacy setCrtc always re-trains */
+   new_conn_state->link_status = DRM_LINK_STATUS_GOOD;
+   }
+   }
+
+   /* Then set all connectors from set->connectors on the target crtc */
+   for (i = 0; i < set->num_connectors; i++) {
+   new_conn_state = drm_atomic_get_connector_state(state,
+   set->connectors[i]);
+   if (IS_ERR(new_conn_state))
+   return PTR_ERR(new_conn_state);
+
+   ret = drm_atomic_set_crtc_for_connector(new_conn_state,
+   set->crtc);
+   if (ret)
+   return ret;
+   }
+
+   for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
+   /*
+* Don't update ->enable for the CRTC in the set_config request,
+* since a mismatch would indicate a bug in the upper layers.
+* The actual modeset code later on will catch any
+* inconsistencies here.
+*/
+   if (crtc == set->crtc)
+   continue;
+
+   if (!new_crtc_state->connector_mask) {
+   ret = drm_atomic_set_mode_prop_for_crtc(new_crtc_state,
+   NULL);
+   if (ret < 0)
+   return ret;
+
+   new_crtc_state->active = false;
+   }
+   }
+
+   return 0;
+}
+
+/* just used from drm_client and atomic-helper: */
+int drm_atomic_set_config(struct drm_mode_set *set,
+ struct drm_atomic_state *state)
+{
+   struct drm_crtc_state *crtc_state;
+   struct drm_plane_state *primary_state;
+   struct drm_crtc *crtc = set->crtc;
+   int hdisplay, vdisplay;
+   int ret;
+
+   crtc_state = drm_atomic_get_crtc_state(state, crtc);
+   if (IS_ERR(crtc_state))
+   return PTR_ERR(crtc_state);
+
+   primary_state = drm_atomic_get_plane_state(state, crtc->primary);
+   if (IS_ERR(primary_state))
+   return PTR_ERR(primary_state);
+
+   if (!set->mode) {
+  

[Intel-gfx] [RFC v4 01/25] drm: provide management functions for drm_file

[Noralf Trønnes]

From: David Herrmann 

Rather than doing drm_file allocation/destruction right in the fops, lets
provide separate helpers. This decouples drm_file management from the
still-mandatory drm-fops. It prepares for use of drm_file without the
fops, both by possible separate fops implementations and APIs (not that I
am aware of any such plans), and more importantly from in-kernel use where
no real file is available.

Signed-off-by: David Herrmann 
Signed-off-by: Noralf Trønnes 
Reviewed-by: Daniel Vetter 
---
 drivers/gpu/drm/drm_file.c | 305 +++--
 drivers/gpu/drm/drm_internal.h |   2 +
 2 files changed, 175 insertions(+), 132 deletions(-)

diff --git a/drivers/gpu/drm/drm_file.c b/drivers/gpu/drm/drm_file.c
index e394799979a6..d4588d33f91c 100644
--- a/drivers/gpu/drm/drm_file.c
+++ b/drivers/gpu/drm/drm_file.c
@@ -101,6 +101,175 @@ DEFINE_MUTEX(drm_global_mutex);
 
 static int drm_open_helper(struct file *filp, struct drm_minor *minor);
 
+/**
+ * drm_file_alloc - allocate file context
+ * @minor: minor to allocate on
+ *
+ * This allocates a new DRM file context. It is not linked into any context and
+ * can be used by the caller freely. Note that the context keeps a pointer to
+ * @minor, so it must be freed before @minor is.
+ *
+ * RETURNS:
+ * Pointer to newly allocated context, ERR_PTR on failure.
+ */
+struct drm_file *drm_file_alloc(struct drm_minor *minor)
+{
+   struct drm_device *dev = minor->dev;
+   struct drm_file *file;
+   int ret;
+
+   file = kzalloc(sizeof(*file), GFP_KERNEL);
+   if (!file)
+   return ERR_PTR(-ENOMEM);
+
+   file->pid = get_pid(task_pid(current));
+   file->minor = minor;
+
+   /* for compatibility root is always authenticated */
+   file->authenticated = capable(CAP_SYS_ADMIN);
+   file->lock_count = 0;
+
+   INIT_LIST_HEAD(>lhead);
+   INIT_LIST_HEAD(>fbs);
+   mutex_init(>fbs_lock);
+   INIT_LIST_HEAD(>blobs);
+   INIT_LIST_HEAD(>pending_event_list);
+   INIT_LIST_HEAD(>event_list);
+   init_waitqueue_head(>event_wait);
+   file->event_space = 4096; /* set aside 4k for event buffer */
+
+   mutex_init(>event_read_lock);
+
+   if (drm_core_check_feature(dev, DRIVER_GEM))
+   drm_gem_open(dev, file);
+
+   if (drm_core_check_feature(dev, DRIVER_SYNCOBJ))
+   drm_syncobj_open(file);
+
+   if (drm_core_check_feature(dev, DRIVER_PRIME))
+   drm_prime_init_file_private(>prime);
+
+   if (dev->driver->open) {
+   ret = dev->driver->open(dev, file);
+   if (ret < 0)
+   goto out_prime_destroy;
+   }
+
+   if (drm_is_primary_client(file)) {
+   ret = drm_master_open(file);
+   if (ret)
+   goto out_close;
+   }
+
+   return file;
+
+out_close:
+   if (dev->driver->postclose)
+   dev->driver->postclose(dev, file);
+out_prime_destroy:
+   if (drm_core_check_feature(dev, DRIVER_PRIME))
+   drm_prime_destroy_file_private(>prime);
+   if (drm_core_check_feature(dev, DRIVER_SYNCOBJ))
+   drm_syncobj_release(file);
+   if (drm_core_check_feature(dev, DRIVER_GEM))
+   drm_gem_release(dev, file);
+   put_pid(file->pid);
+   kfree(file);
+
+   return ERR_PTR(ret);
+}
+
+static void drm_events_release(struct drm_file *file_priv)
+{
+   struct drm_device *dev = file_priv->minor->dev;
+   struct drm_pending_event *e, *et;
+   unsigned long flags;
+
+   spin_lock_irqsave(>event_lock, flags);
+
+   /* Unlink pending events */
+   list_for_each_entry_safe(e, et, _priv->pending_event_list,
+pending_link) {
+   list_del(>pending_link);
+   e->file_priv = NULL;
+   }
+
+   /* Remove unconsumed events */
+   list_for_each_entry_safe(e, et, _priv->event_list, link) {
+   list_del(>link);
+   kfree(e);
+   }
+
+   spin_unlock_irqrestore(>event_lock, flags);
+}
+
+/**
+ * drm_file_free - free file context
+ * @file: context to free, or NULL
+ *
+ * This destroys and deallocates a DRM file context previously allocated via
+ * drm_file_alloc(). The caller must make sure to unlink it from any contexts
+ * before calling this.
+ *
+ * If NULL is passed, this is a no-op.
+ *
+ * RETURNS:
+ * 0 on success, or error code on failure.
+ */
+void drm_file_free(struct drm_file *file)
+{
+   struct drm_device *dev;
+
+   if (!file)
+   return;
+
+   dev = file->minor->dev;
+
+   DRM_DEBUG("pid = %d, device = 0x%lx, open_count = %d\n",
+ task_pid_nr(current),
+ (long)old_encode_dev(file->minor->kdev->devt),
+ dev->open_count);
+
+   if (drm_core_check_feature(dev, 

[Intel-gfx] [RFC v4 02/25] drm/file: Don't set master on in-kernel clients

[Noralf Trønnes]

It only makes sense for userspace clients.

Signed-off-by: Noralf Trønnes 
Reviewed-by: Daniel Vetter 
---
 drivers/gpu/drm/drm_file.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/drm_file.c b/drivers/gpu/drm/drm_file.c
index d4588d33f91c..55505378df47 100644
--- a/drivers/gpu/drm/drm_file.c
+++ b/drivers/gpu/drm/drm_file.c
@@ -155,17 +155,8 @@ struct drm_file *drm_file_alloc(struct drm_minor *minor)
goto out_prime_destroy;
}
 
-   if (drm_is_primary_client(file)) {
-   ret = drm_master_open(file);
-   if (ret)
-   goto out_close;
-   }
-
return file;
 
-out_close:
-   if (dev->driver->postclose)
-   dev->driver->postclose(dev, file);
 out_prime_destroy:
if (drm_core_check_feature(dev, DRIVER_PRIME))
drm_prime_destroy_file_private(>prime);
@@ -365,6 +356,7 @@ static int drm_open_helper(struct file *filp, struct 
drm_minor *minor)
 {
struct drm_device *dev = minor->dev;
struct drm_file *priv;
+   int ret;
 
if (filp->f_flags & O_EXCL)
return -EBUSY;  /* No exclusive opens */
@@ -379,6 +371,14 @@ static int drm_open_helper(struct file *filp, struct 
drm_minor *minor)
if (IS_ERR(priv))
return PTR_ERR(priv);
 
+   if (drm_is_primary_client(priv)) {
+   ret = drm_master_open(priv);
+   if (ret) {
+   drm_file_free(priv);
+   return ret;
+   }
+   }
+
filp->private_data = priv;
priv->filp = filp;
 
-- 
2.15.1

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Re: [Intel-gfx] [PATCH v2] drm/i915: Check whitelist registers across resets

[Chris Wilson]

Quoting Oscar Mateo (2018-04-13 17:46:42)
> 
> 
> On 4/12/2018 8:21 AM, Chris Wilson wrote:
> > Add a selftest to ensure that we restore the whitelisted registers after
> > rewrite the registers everytime they might be scrubbed, e.g. module
> > load, reset and resume. For the other volatile workaround registers, we
> > export their presence via debugfs and check in igt/gem_workarounds.
> > However, we don't export the whitelist and rather than do so, let's test
> > them directly in the kernel.
> 
> I guess my question is... why? what was the problem with exporting the 
> list of whitelist registers in debugfs?

We don't... (There's no RING_NONPRIV checking currently) I wasn't fond
of the igt for it is checking kernel implementation rather than behaviour.
The kernel gives it a checklist which it dutifully follows... Now that
we have selftests, we don't need to write what I think should be unit
tests in igt anymore.

> > The test we use is to read the registers back from the CS (this helps us
> > be sure that the registers will be valid for MI_LRI etc). In order to
> > generate the expected list, we split intel_whitelist_workarounds_emit
> > into two phases, the first to build the list and the second to apply.
> > Inside the test, we only build the list and then check that list against
> > the hw.
> >
> > v2: Filter out pre-gen8 as they do not have RING_NONPRIV.
> >
> > Signed-off-by: Chris Wilson 
> > Cc: Oscar Mateo 
> > Cc: Mika Kuoppala 
> > Cc: Joonas Lahtinen 
> > ---
> > +static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
> > +  struct whitelist *w)
> > +{
> > + struct drm_i915_private *i915 = engine->i915;
> > +
> > + GEM_BUG_ON(engine->id != RCS);
> > +
> > + w->count = 0;
> > + w->nopid = i915_mmio_reg_offset(RING_NOPID(engine->mmio_base));
> 
> :)
> 
> > +
> > + if (INTEL_GEN(i915) < 8)
> > + return NULL;
> > + else if (IS_BROADWELL(i915))
> > + bdw_whitelist_build(engine, w);
> 
> Is it worth passing the engine around? Even of we end up with 
> whitelisted register in engines != RCS, we will need more changes than this.

No idea, it was easy enough to pass around, so I did just in case it was
useful in future (pulling out i915 or whatever).
-Chris
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Re: [Intel-gfx] [PATCH v2] drm/i915: Check whitelist registers across resets

[Oscar Mateo]

On 4/12/2018 8:21 AM, Chris Wilson wrote:

Add a selftest to ensure that we restore the whitelisted registers after
rewrite the registers everytime they might be scrubbed, e.g. module
load, reset and resume. For the other volatile workaround registers, we
export their presence via debugfs and check in igt/gem_workarounds.
However, we don't export the whitelist and rather than do so, let's test
them directly in the kernel.


I guess my question is... why? what was the problem with exporting the 
list of whitelist registers in debugfs?



The test we use is to read the registers back from the CS (this helps us
be sure that the registers will be valid for MI_LRI etc). In order to
generate the expected list, we split intel_whitelist_workarounds_emit
into two phases, the first to build the list and the second to apply.
Inside the test, we only build the list and then check that list against
the hw.

v2: Filter out pre-gen8 as they do not have RING_NONPRIV.

Signed-off-by: Chris Wilson 
Cc: Oscar Mateo 
Cc: Mika Kuoppala 
Cc: Joonas Lahtinen 
---
  drivers/gpu/drm/i915/i915_debugfs.c   |  14 +-
  drivers/gpu/drm/i915/i915_drv.h   |   1 -
  drivers/gpu/drm/i915/intel_lrc.c  |   8 +-
  drivers/gpu/drm/i915/intel_ringbuffer.c   |   4 +-
  drivers/gpu/drm/i915/intel_workarounds.c  | 215 ++---
  drivers/gpu/drm/i915/intel_workarounds.h  |   2 +-
  .../drm/i915/selftests/i915_live_selftests.h  |   1 +
  .../drm/i915/selftests/intel_workarounds.c| 284 ++
  8 files changed, 389 insertions(+), 140 deletions(-)
  create mode 100644 drivers/gpu/drm/i915/selftests/intel_workarounds.c

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 2e6652a9bb9e..e0274f41bc76 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3304,24 +3304,13 @@ static int i915_shared_dplls_info(struct seq_file *m, 
void *unused)
  
  static int i915_wa_registers(struct seq_file *m, void *unused)

  {
-   int i;
-   int ret;
-   struct intel_engine_cs *engine;
struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct drm_device *dev = _priv->drm;
struct i915_workarounds *workarounds = _priv->workarounds;
-   enum intel_engine_id id;
-
-   ret = mutex_lock_interruptible(>struct_mutex);
-   if (ret)
-   return ret;
+   int i;
  
  	intel_runtime_pm_get(dev_priv);
  
  	seq_printf(m, "Workarounds applied: %d\n", workarounds->count);

-   for_each_engine(engine, dev_priv, id)
-   seq_printf(m, "HW whitelist count for %s: %d\n",
-  engine->name, workarounds->hw_whitelist_count[id]);
for (i = 0; i < workarounds->count; ++i) {
i915_reg_t addr;
u32 mask, value, read;
@@ -3337,7 +3326,6 @@ static int i915_wa_registers(struct seq_file *m, void 
*unused)
}
  
  	intel_runtime_pm_put(dev_priv);

-   mutex_unlock(>struct_mutex);
  
  	return 0;

  }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 649c0f2f3bae..15e1260be58e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1297,7 +1297,6 @@ struct i915_wa_reg {
  struct i915_workarounds {
struct i915_wa_reg reg[I915_MAX_WA_REGS];
u32 count;
-   u32 hw_whitelist_count[I915_NUM_ENGINES];
  };
  
  struct i915_virtual_gpu {

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c7c85134a84a..4f728587a756 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1744,9 +1744,7 @@ static int gen8_init_render_ring(struct intel_engine_cs 
*engine)
if (ret)
return ret;
  
-	ret = intel_whitelist_workarounds_apply(engine);

-   if (ret)
-   return ret;
+   intel_whitelist_workarounds_apply(engine);
  
  	/* We need to disable the AsyncFlip performance optimisations in order

 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
@@ -1769,9 +1767,7 @@ static int gen9_init_render_ring(struct intel_engine_cs 
*engine)
if (ret)
return ret;
  
-	ret = intel_whitelist_workarounds_apply(engine);

-   if (ret)
-   return ret;
+   intel_whitelist_workarounds_apply(engine);
  
  	return 0;

  }
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 757bb0990c07..c68ac605b8a9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -618,9 +618,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
if (ret)
return ret;
  
-	ret = intel_whitelist_workarounds_apply(engine);

-   if (ret)
-   return ret;
+  

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds

[Patchwork]

== Series Details ==

Series: series starting with [01/22] drm/i915/icl: Introduce initial Icelake 
Workarounds
URL   : https://patchwork.freedesktop.org/series/41687/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4053 -> Patchwork_8688 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/41687/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_8688 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_mmap_gtt@basic-small-bo-tiledx:
  fi-gdg-551: PASS -> FAIL (fdo#102575)


 Possible fixes 

igt@debugfs_test@read_all_entries:
  fi-snb-2520m:   INCOMPLETE (fdo#103713) -> PASS


  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713


== Participating hosts (35 -> 33) ==

  Missing(2): fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4053 -> Patchwork_8688

  CI_DRM_4053: e2599f775a9c1c27f702e90e6432e555764edcd8 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4429: 80e4910581c7310258375a003a5de9a57ed24546 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8688: a5d656177b7ead3baa5b6629f814bb4edacd8b61 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4429: 93b35926a150e318439d2505901288594b3548f5 @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

a5d656177b7e drm/i915/icl: WaAllowUMDToModifySamplerMode
797cfbca5d58 drm/i915/icl: WaAllowUmdWriteTRTTRootTable
317ef6d4aedf drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
4dfa2b45285d drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
40b8ef4094c1 drm/i915/icl: WaSendPushConstantsFromMMIO
a753045fa070 drm/i915/icl: WaEnableFloatBlendOptimization
4c42d02cef0a drm/i915/icl: Wa_2006665173
a9f9101ed56b drm/i915/icl: WaEnableStateCacheRedirectToCS
82515343b1a6 drm/i915/icl: WaDisableImprovedTdlClkGating
ed3af10bec1d drm/i915/icl: WaForwardProgressSoftReset
e30c867f83d8 drm/i915/icl: Wa_1406838659
bb7e420ff378 drm/i915/icl: Wa_1604302699
005066f5b27e drm/i915/icl: Wa_1406680159 and Wa_2201832410
9f3dfb692dec drm/i915/icl: Wa_1405779004
75938bbf671a drm/i915/icl: WaDisCtxReload
8a6f39285391 drm/i915/icl: WaCL2SFHalfMaxAlloc
e0c061b03dd4 drm/i915/icl: WaDisableCleanEvicts
a78f4ed1040f drm/i915/icl: WaModifyGamTlbPartitioning
011f158b8a19 drm/i915/icl: WaL3BankAddressHashing
b36a6c421a87 drm/i915/icl: WaGAPZPriorityScheme
5ae138861bbe drm/i915/icl: Enable Sampler DFR
bc09764ddda4 drm/i915/icl: Introduce initial Icelake Workarounds

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8688/issues.html
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/22] drm/i915/icl: Introduce initial Icelake Workarounds

[Patchwork]

== Series Details ==

Series: series starting with [01/22] drm/i915/icl: Introduce initial Icelake 
Workarounds
URL   : https://patchwork.freedesktop.org/series/41687/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
bc09764ddda4 drm/i915/icl: Introduce initial Icelake Workarounds
-:46: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#46: FILE: drivers/gpu/drm/i915/i915_drv.h:2471:
+#define IS_ICL_REVID(p, since, until) \
+   (IS_ICELAKE(p) && IS_REVID(p, since, until))

total: 0 errors, 0 warnings, 1 checks, 135 lines checked
5ae138861bbe drm/i915/icl: Enable Sampler DFR
b36a6c421a87 drm/i915/icl: WaGAPZPriorityScheme
011f158b8a19 drm/i915/icl: WaL3BankAddressHashing
a78f4ed1040f drm/i915/icl: WaModifyGamTlbPartitioning
e0c061b03dd4 drm/i915/icl: WaDisableCleanEvicts
8a6f39285391 drm/i915/icl: WaCL2SFHalfMaxAlloc
75938bbf671a drm/i915/icl: WaDisCtxReload
9f3dfb692dec drm/i915/icl: Wa_1405779004
005066f5b27e drm/i915/icl: Wa_1406680159 and Wa_2201832410
bb7e420ff378 drm/i915/icl: Wa_1604302699
e30c867f83d8 drm/i915/icl: Wa_1406838659
ed3af10bec1d drm/i915/icl: WaForwardProgressSoftReset
82515343b1a6 drm/i915/icl: WaDisableImprovedTdlClkGating
a9f9101ed56b drm/i915/icl: WaEnableStateCacheRedirectToCS
4c42d02cef0a drm/i915/icl: Wa_2006665173
a753045fa070 drm/i915/icl: WaEnableFloatBlendOptimization
40b8ef4094c1 drm/i915/icl: WaSendPushConstantsFromMMIO
4dfa2b45285d drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
317ef6d4aedf drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
797cfbca5d58 drm/i915/icl: WaAllowUmdWriteTRTTRootTable
a5d656177b7e drm/i915/icl: WaAllowUMDToModifySamplerMode

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Re: [Intel-gfx] [PATCH v2 2/6] drm/i915: Add NV12 as supported format for primary plane

[Kristian Høgsberg]

On Fri, Apr 13, 2018 at 5:17 AM Vidya Srinivas 
wrote:

> From: Chandra Konduru 

> This patch adds NV12 to list of supported formats for
> primary plane

Reviewed-by: Kristian H. Kristensen 

> v2: Rebased (Chandra Konduru)

> v3: Rebased (me)

> v4: Review comments by Ville addressed
> Removed the skl_primary_formats_with_nv12 and
> added NV12 case in existing skl_primary_formats

> v5: Rebased (me)

> v6: Missed the Tested-by/Reviewed-by in the previous series
> Adding the same to commit message in this version.

> v7: Review comments by Ville addressed
>  Restricting the NV12 for BXT and on PIPE A and B
> Rebased (me)

> v8: Rebased (me)
> Modified restricting the NV12 support for both BXT and KBL.

> v9: Rebased (me)

> v10: Addressed review comments from Maarten.
>  Adding NV12 inside skl_primary_formats itself.

> v11: Adding Reviewed By tag from Shashank Sharma

> v12: Addressed review comments from Juha-Pekka Heikkila
> "NV12 not to be supported by SKL"

> v13: Addressed review comments from Ville
> Added skl_pri_planar_formats to include NV12
> and skl_plane_has_planar function to check for
> NV12 support on plane. Added NV12 format to
> skl_mod_supported. These were review comments
> from Kristian Høgsberg 

> v14: Added reviewed by from Juha-Pekka Heikkila

> v15: Rebased the series

> v16: Added all tiling support under mod supported
> for NV12. Credits to Megha Aggarwal

> Credits-to: Megha Aggarwal megha.aggar...@intel.com
> Tested-by: Clinton Taylor 
> Reviewed-by: Juha-Pekka Heikkila 
> Reviewed-by: Clinton Taylor 
> Reviewed-by: Shashank Sharma 
> Signed-off-by: Chandra Konduru 
> Signed-off-by: Nabendu Maiti 
> Signed-off-by: Vidya Srinivas 
> ---
>   drivers/gpu/drm/i915/intel_display.c | 55
++--
>   drivers/gpu/drm/i915/intel_drv.h |  2 ++
>   2 files changed, 55 insertions(+), 2 deletions(-)

> diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
> index 22c8a7d..1a0fae9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -88,6 +88,22 @@ static const uint32_t skl_primary_formats[] = {
>  DRM_FORMAT_VYUY,
>   };

> +static const uint32_t skl_pri_planar_formats[] = {
> +   DRM_FORMAT_C8,
> +   DRM_FORMAT_RGB565,
> +   DRM_FORMAT_XRGB,
> +   DRM_FORMAT_XBGR,
> +   DRM_FORMAT_ARGB,
> +   DRM_FORMAT_ABGR,
> +   DRM_FORMAT_XRGB2101010,
> +   DRM_FORMAT_XBGR2101010,
> +   DRM_FORMAT_YUYV,
> +   DRM_FORMAT_YVYU,
> +   DRM_FORMAT_UYVY,
> +   DRM_FORMAT_VYUY,
> +   DRM_FORMAT_NV12,
> +};
> +
>   static const uint64_t skl_format_modifiers_noccs[] = {
>  I915_FORMAT_MOD_Yf_TILED,
>  I915_FORMAT_MOD_Y_TILED,
> @@ -13124,6 +13140,12 @@ static bool skl_mod_supported(uint32_t format,
uint64_t modifier)
>  if (modifier == I915_FORMAT_MOD_Yf_TILED)
>  return true;
>  /* fall through */
> +   case DRM_FORMAT_NV12:
> +   if (modifier == DRM_FORMAT_MOD_LINEAR ||
> +   modifier == I915_FORMAT_MOD_X_TILED ||
> +   modifier == I915_FORMAT_MOD_Y_TILED ||
> +   modifier == I915_FORMAT_MOD_Yf_TILED)
> +   return true;
>  case DRM_FORMAT_C8:
>  if (modifier == DRM_FORMAT_MOD_LINEAR ||
>  modifier == I915_FORMAT_MOD_X_TILED ||
> @@ -13328,6 +13350,30 @@ static bool skl_plane_has_fbc(struct
drm_i915_private *dev_priv,
>  return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
>   }

> +bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
> + enum pipe pipe, enum plane_id plane_id)
> +{
> +   if (plane_id == PLANE_PRIMARY) {
> +   if (IS_SKYLAKE(dev_priv))
> +   return false;
> +   else if ((INTEL_GEN(dev_priv) == 9 && pipe == PIPE_C) &&
> +!IS_GEMINILAKE(dev_priv))
> +   return false;
> +   } else if (plane_id >= PLANE_SPRITE0) {
> +   if (plane_id == PLANE_CURSOR)
> +   return false;
> +   if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) == 10)
{
> +   if (plane_id != PLANE_SPRITE0)
> +   return false;
> +   } else {
> +   if (plane_id != PLANE_SPRITE0 || pipe == PIPE_C ||
> +   IS_SKYLAKE(dev_priv))
> +   return false;
> +   }
> +   }
> +   return true;
> +}
> +
>   static struct intel_plane *

Re: [Intel-gfx] [PATCH v2 3/6] drm/i915: Add NV12 as supported format for sprite plane

[Kristian Høgsberg]

On Fri, Apr 13, 2018 at 5:18 AM Vidya Srinivas 
wrote:

> From: Chandra Konduru 

> This patch adds NV12 to list of supported formats for sprite plane.

> v2: Rebased (me)

> v3: Review comments by Ville addressed
> - Removed skl_plane_formats_with_nv12 and added
> NV12 case in existing skl_plane_formats
> - Added the 10bpc RGB formats

> v4: Addressed review comments from Clinton A Taylor
> "Why are we adding 10 bit RGB formats with the NV12 series patches?
> Trying to set XR30 or AB30 results in error returned even though
> the modes are advertised for the planes"
> - Removed 10bit RGB formats added previously with NV12 series

> v5: Missed the Tested-by/Reviewed-by in the previous series
> Adding the same to commit message in this version.
> Addressed review comments from Clinton A Taylor
> "Why are we adding 10 bit RGB formats with the NV12 series patches?
> Trying to set XR30 or AB30 results in error returned even though
> the modes are advertised for the planes"
> - Previous version has 10bit RGB format removed from VLV formats
> by mistake. Fixing that in this version.
> Removed 10bit RGB formats added previously with NV12 series
> for SKL.

> v6: Addressed review comments by Ville
> Restricting the NV12 to BXT and PIPE A and B

> v7: Rebased (me)

> v8: Rebased (me)
> Restricting NV12 changes to BXT and KBL
> Restricting NV12 changes for plane 0 (overlay)

> v9: Rebased (me)

> v10: Addressed review comments from Maarten.
> Adding NV12 to skl_plane_formats itself.

> v11: Addressed review comments from Shashank Sharma

> v12: Addressed review comments from Shashank Sharma
> Made the condition in intel_sprite_plane_create
> simple and easy to read as suggested.

> v13: Adding reviewed by tag from Shashank Sharma
> Addressed review comments from Juha-Pekka Heikkila
> "NV12 not to be supported by SKL"

> v14: Addressed review comments from Ville
> Added skl_planar_formats to include NV12
> and a check skl_plane_has_planar in sprite create
> Added NV12 format to skl_mod_supported. These were
> review comments from Kristian Høgsberg 

> v15: Added reviewed by from Juha-Pekka Heikkila

> v16: Rebased the series

> v17: Added all tiling under mod supported for NV12
> Credits to Megha Aggarwal

> Credits-to: Megha Aggarwal 
> Credits-to: Kristian Høgsberg 
> Tested-by: Clinton Taylor 
> Reviewed-by: Juha-Pekka Heikkila 
> Reviewed-by: Shashank Sharma 
> Reviewed-by: Clinton Taylor 
> Signed-off-by: Chandra Konduru 
> Signed-off-by: Nabendu Maiti 
> Signed-off-by: Vidya Srinivas 
> ---
>   drivers/gpu/drm/i915/intel_sprite.c | 29 +++--
>   1 file changed, 27 insertions(+), 2 deletions(-)

> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
> index aa1dfaa..8b7947d 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1253,6 +1253,19 @@ static uint32_t skl_plane_formats[] = {
>  DRM_FORMAT_VYUY,
>   };

> +static uint32_t skl_planar_formats[] = {
> +   DRM_FORMAT_RGB565,
> +   DRM_FORMAT_ABGR,
> +   DRM_FORMAT_ARGB,
> +   DRM_FORMAT_XBGR,
> +   DRM_FORMAT_XRGB,
> +   DRM_FORMAT_YUYV,
> +   DRM_FORMAT_YVYU,
> +   DRM_FORMAT_UYVY,
> +   DRM_FORMAT_VYUY,
> +   DRM_FORMAT_NV12,
> +};
> +
>   static const uint64_t skl_plane_format_modifiers_noccs[] = {
>  I915_FORMAT_MOD_Yf_TILED,
>  I915_FORMAT_MOD_Y_TILED,
> @@ -1350,6 +1363,12 @@ static bool skl_mod_supported(uint32_t format,
uint64_t modifier)
>  if (modifier == I915_FORMAT_MOD_Yf_TILED)
>  return true;
>  /* fall through */
> +   case DRM_FORMAT_NV12:
> +   if (modifier == DRM_FORMAT_MOD_LINEAR ||
> +   modifier == I915_FORMAT_MOD_X_TILED ||
> +   modifier == I915_FORMAT_MOD_Y_TILED ||
> +   modifier == I915_FORMAT_MOD_Yf_TILED)
> +   return true;

Thanks for adding the modifier support.

Reviewed-by: Kristian H. Kristensen 

>  case DRM_FORMAT_C8:
>  if (modifier == DRM_FORMAT_MOD_LINEAR ||
>  modifier == I915_FORMAT_MOD_X_TILED ||
> @@ -1446,8 +1465,14 @@ intel_sprite_plane_create(struct drm_i915_private
*dev_priv,
>  intel_plane->disable_plane = skl_disable_plane;
>  intel_plane->get_hw_state = skl_plane_get_hw_state;

> -   plane_formats = skl_plane_formats;
> -   num_plane_formats = ARRAY_SIZE(skl_plane_formats);
> +   if (skl_plane_has_planar(dev_priv, pipe,
> + 

[Intel-gfx] [PATCH 09/22] drm/i915/icl: Wa_1405779004

[Oscar Mateo]

Disable MSC clock gating to prevent data corruption.

BSpec: 19257

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 1 +
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 161d04e..9ab5731 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3840,6 +3840,7 @@ enum {
 #define SLICE_UNIT_LEVEL_CLKGATE   _MMIO(0x94d4)
 #define  SARBUNIT_CLKGATE_DIS  (1 << 5)
 #define  RCCUNIT_CLKGATE_DIS   (1 << 7)
+#define  MSCUNIT_CLKGATE_DIS   (1 << 10)
 
 #define SUBSLICE_UNIT_LEVEL_CLKGATE_MMIO(0x9524)
 #define  GWUNIT_CLKGATE_DIS(1 << 16)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 75fad6f..76059ed 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -745,6 +745,12 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
 */
I915_WRITE(GAMW_ECO_DEV_RW_IA_REG, (I915_READ(GAMW_ECO_DEV_RW_IA_REG) |
GAMW_ECO_DEV_CTX_RELOAD_DISABLE));
+
+   /* Wa_1405779004:icl (pre-prod) */
+   if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+   I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
+  (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
+   MSCUNIT_CLKGATE_DIS));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset

[Oscar Mateo]

Avoids a hang during soft reset.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 5 +
 drivers/gpu/drm/i915/intel_workarounds.c | 8 
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fc09b83..cfb9b0d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9711,6 +9711,11 @@ enum skl_power_gate {
 #define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers 
*/
 #define GEN9_BLT_MOCS(i)   _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS 
registers */
 
+#define GEN10_SCRATCH_LNCF2_MMIO(0xb0a0)
+#define   PMFLUSHDONE_LNICRSDROP   (1 << 20)
+#define   PMFLUSH_GAPL3UNBLOCK (1 << 21)
+#define   PMFLUSHDONE_LNEBLK   (1 << 22)
+
 /* gamt regs */
 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for 
LRA1/2 */
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 72497e1..413a43d 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -768,6 +768,14 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
   (I915_READ(INF_UNIT_LEVEL_CLKGATE) |
CGPSF_CLKGATE_DIS));
+
+   /* WaForwardProgressSoftReset:icl (pre-prod) */
+   if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+   I915_WRITE(GEN10_SCRATCH_LNCF2,
+  (I915_READ(GEN10_SCRATCH_LNCF2) |
+   PMFLUSHDONE_LNICRSDROP |
+   PMFLUSH_GAPL3UNBLOCK |
+   PMFLUSHDONE_LNEBLK));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 19/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2

[Oscar Mateo]

Required to dinamically set 'Small PL Lossless Fix Enable'

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_workarounds.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 970a763..43dbeed 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -963,6 +963,11 @@ static int icl_whitelist_workarounds_apply(struct 
intel_engine_cs *engine)
if (ret)
return ret;
 
+   /* WaAllowUMDToModifyHalfSliceChicken2:icl */
+   ret = wa_ring_whitelist_reg(engine, HALF_SLICE_CHICKEN2);
+   if (ret)
+   return ret;
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 05/22] drm/i915/icl: WaModifyGamTlbPartitioning

[Oscar Mateo]

Adjust default GAM TLB partitioning for performance reasons.

v2: Only touch the bits that we really need
v3: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 5 +
 drivers/gpu/drm/i915/intel_workarounds.c | 5 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5637cd7..fe35785 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8228,6 +8228,11 @@ enum {
 #define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
 #define   DFR_DISABLE  (1 << 9)
 
+#define GEN11_GACB_PERF_CTRL   _MMIO(0x4B80)
+#define   GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
+#define   GEN11_HASH_CTRL_BIT0 (1 << 0)
+#define   GEN11_HASH_CTRL_BIT4 (1 << 12)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index a94cd93..d7b2b07 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -721,6 +721,11 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN11_GLBLINVL,
   ((I915_READ(GEN11_GLBLINVL) & 
~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
GEN11_BANK_HASH_ADDR_EXCL_BIT0));
+
+   /* WaModifyGamTlbPartitioning:icl */
+   I915_WRITE(GEN11_GACB_PERF_CTRL,
+  ((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
+   GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 12/22] drm/i915/icl: Wa_1406838659

[Oscar Mateo]

Disable CGPSF unit clock gating to prevent an issue.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 13 -
 drivers/gpu/drm/i915/intel_workarounds.c |  6 ++
 2 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b462938..fc09b83 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3838,15 +3838,18 @@ enum {
  * GEN10 clock gating regs
  */
 #define SLICE_UNIT_LEVEL_CLKGATE   _MMIO(0x94d4)
-#define  SARBUNIT_CLKGATE_DIS  (1 << 5)
-#define  RCCUNIT_CLKGATE_DIS   (1 << 7)
-#define  MSCUNIT_CLKGATE_DIS   (1 << 10)
+#define   SARBUNIT_CLKGATE_DIS (1 << 5)
+#define   RCCUNIT_CLKGATE_DIS  (1 << 7)
+#define   MSCUNIT_CLKGATE_DIS  (1 << 10)
 
 #define SUBSLICE_UNIT_LEVEL_CLKGATE_MMIO(0x9524)
-#define  GWUNIT_CLKGATE_DIS(1 << 16)
+#define   GWUNIT_CLKGATE_DIS   (1 << 16)
 
 #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
-#define  VFUNIT_CLKGATE_DIS(1 << 20)
+#define   VFUNIT_CLKGATE_DIS   (1 << 20)
+
+#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
+#define   CGPSF_CLKGATE_DIS(1 << 3)
 
 /*
  * Display engine regs
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 0cebafa..72497e1 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -762,6 +762,12 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER,
   (I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) |
GEN11_I2M_WRITE_DISABLE));
+
+   /* Wa_1406838659:icl (pre-prod) */
+   if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_C0))
+   I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
+  (I915_READ(INF_UNIT_LEVEL_CLKGATE) |
+   CGPSF_CLKGATE_DIS));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 11/22] drm/i915/icl: Wa_1604302699

[Oscar Mateo]

Disable I2M Write for performance reasons.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 4 +++-
 drivers/gpu/drm/i915/intel_workarounds.c | 5 +
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9ab5731..b462938 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7192,7 +7192,9 @@ enum {
 #define GEN7_L3CNTLREG3_MMIO(0xB024)
 
 #define GEN7_L3_CHICKEN_MODE_REGISTER  _MMIO(0xB030)
-#define  GEN7_WA_L3_CHICKEN_MODE   0x2000
+#define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xB114)
+#define  GEN7_WA_L3_CHICKEN_MODE   0x2000
+#define  GEN11_I2M_WRITE_DISABLE   (1 << 28)
 
 #define GEN7_L3SQCREG4 _MMIO(0xb034)
 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE   (1<<27)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 57a69aa..0cebafa 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -757,6 +757,11 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
   (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
GWUNIT_CLKGATE_DIS));
+
+   /* Wa_1604302699:icl */
+   I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER,
+  (I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) |
+   GEN11_I2M_WRITE_DISABLE));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 18/22] drm/i915/icl: WaSendPushConstantsFromMMIO

[Oscar Mateo]

Allows UMDs to set 'Disable Gather at Set Shader Common Slice'.

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it...

v2: Rebased
v3: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_workarounds.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 9e50fba..970a763 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -956,6 +956,13 @@ static int cnl_whitelist_workarounds_apply(struct 
intel_engine_cs *engine)
 
 static int icl_whitelist_workarounds_apply(struct intel_engine_cs *engine)
 {
+   int ret;
+
+   /* WaSendPushConstantsFromMMIO:icl */
+   ret = wa_ring_whitelist_reg(engine, COMMON_SLICE_CHICKEN2);
+   if (ret)
+   return ret;
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 20/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7

[Oscar Mateo]

Required to dinamically set 'Trilinear Filter Quality Mode'

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_workarounds.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 43dbeed..8a76bc4 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -968,6 +968,11 @@ static int icl_whitelist_workarounds_apply(struct 
intel_engine_cs *engine)
if (ret)
return ret;
 
+   /* WaAllowUMDToModifyHalfSliceChicken7:icl */
+   ret = wa_ring_whitelist_reg(engine, GEN9_HALF_SLICE_CHICKEN7);
+   if (ret)
+   return ret;
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

[Oscar Mateo]

Inherit workarounds from previous platforms that are still valid for
Icelake.

v2: GEN7_ROW_CHICKEN2 is masked
v3:
  - Since it has been fixed already in upstream, removed the TODO
comment about WA_SET_BIT for WaInPlaceDecompressionHang.
  - Squashed with this patch:
  drm/i915/icl: add icelake_init_clock_gating()
from Paulo Zanoni 
  - Squashed with this patch:
  drm/i915/icl: WaForceEnableNonCoherent
from Oscar Mateo 
  - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
applies to B0 as well.
  - WaPipeControlBefore3DStateSamplePattern WABB was being applied
to ICL incorrectly.
v4:
  - Wrap the commit message
  - s/dev_priv/p to please checkpatch
v5: Rebased on top of the WA refactoring

Cc: Tomasz Lis 
Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_drv.h  |  9 ++
 drivers/gpu/drm/i915/i915_gem_gtt.c  |  4 +--
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 drivers/gpu/drm/i915/intel_lrc.c |  2 ++
 drivers/gpu/drm/i915/intel_pm.c  |  2 ++
 drivers/gpu/drm/i915/intel_workarounds.c | 47 
 6 files changed, 63 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e50d958..b08a22a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2462,6 +2462,15 @@ static inline unsigned int i915_sg_segment_size(void)
 #define IS_CNL_REVID(p, since, until) \
(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
 
+#define ICL_REVID_A0   0x0
+#define ICL_REVID_A2   0x1
+#define ICL_REVID_B0   0x3
+#define ICL_REVID_B2   0x4
+#define ICL_REVID_C0   0x5
+
+#define IS_ICL_REVID(p, since, until) \
+   (IS_ICELAKE(p) && IS_REVID(p, since, until))
+
 /*
  * The genX designation typically refers to the render engine, so render
  * capability related checks should use IS_GEN, while display and other checks
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 21d72f6..221b873 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct 
drm_i915_private *dev_priv)
 * called on driver load and after a GPU reset, so you can place
 * workarounds here even if they get overwritten by GPU reset.
 */
-   /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
+   /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
if (IS_BROADWELL(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
else if (IS_CHERRYVIEW(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
-   else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
+   else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || 
IS_GEN11(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
else if (IS_GEN9_LP(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb10602..f2ee225 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7203,6 +7203,7 @@ enum {
 /* GEN8 chicken */
 #define HDC_CHICKEN0   _MMIO(0x7300)
 #define CNL_HDC_CHICKEN0   _MMIO(0xE5F0)
+#define ICL_HDC_CHICKEN0   _MMIO(0xE5F4)
 #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE(1<<15)
 #define  HDC_FENCE_DEST_SLM_DISABLE(1<<14)
 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED   (1<<11)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c7c8513..675c19d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1633,6 +1633,8 @@ static int intel_init_workaround_bb(struct 
intel_engine_cs *engine)
return -EINVAL;
 
switch (INTEL_GEN(engine->i915)) {
+   case 11:
+   return 0;
case 10:
wa_bb_fn[0] = gen10_init_indirectctx_bb;
wa_bb_fn[1] = NULL;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4baab85..cfa03ba 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9123,6 +9123,8 @@ static void nop_init_clock_gating(struct drm_i915_private 
*dev_priv)
  */
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
+   if (IS_ICELAKE(dev_priv))
+   dev_priv->display.init_clock_gating = nop_init_clock_gating;
if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating 

[Intel-gfx] [PATCH 17/22] drm/i915/icl: WaEnableFloatBlendOptimization

[Oscar Mateo]

Enables blend optimization for floating point RTs

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 71696dc..127d2a3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2663,6 +2663,9 @@ enum i915_power_well_id {
 #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE(1<<6)
 #define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE   (1<<1)
 
+#define GEN10_CACHE_MODE_SS_MMIO(0xe420)
+#define   FLOAT_BLEND_OPTIMIZATION_ENABLE  (1 << 4)
+
 #define GEN6_BLITTER_ECOSKPD   _MMIO(0x221d0)
 #define   GEN6_BLITTER_LOCK_SHIFT  16
 #define   GEN6_BLITTER_FBC_NOTIFY  (1<<3)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 90906ab..9e50fba 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -475,6 +475,9 @@ static int icl_ctx_workarounds_init(struct drm_i915_private 
*dev_priv)
WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
  GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
 
+   /* WaEnableFloatBlendOptimization:icl */
+   WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS, FLOAT_BLEND_OPTIMIZATION_ENABLE);
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 21/22] drm/i915/icl: WaAllowUmdWriteTRTTRootTable

[Oscar Mateo]

Required for TR-TT (Tiled Resource Translation Table) support.

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 8 
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 127d2a3..d008a70 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8255,6 +8255,9 @@ enum {
 #define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
 #define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE  (1 << 7)
 
+#define TR_VA_TTL3_PTR_DW0 _MMIO(0x4DE0)
+#define TR_VA_TTL3_PTR_DW1 _MMIO(0x4DE4)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 8a76bc4..b52ac41 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -973,6 +973,14 @@ static int icl_whitelist_workarounds_apply(struct 
intel_engine_cs *engine)
if (ret)
return ret;
 
+   /* WaAllowUmdWriteTRTTRootTable:icl */
+   ret = wa_ring_whitelist_reg(engine, TR_VA_TTL3_PTR_DW0);
+   if (ret)
+   return ret;
+   ret = wa_ring_whitelist_reg(engine, TR_VA_TTL3_PTR_DW1);
+   if (ret)
+   return ret;
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 06/22] drm/i915/icl: WaDisableCleanEvicts

[Oscar Mateo]

Avoids an undefined LLC behavior.

BSpec: 9613

v2: Renamed to Wa_1405733216
v3: Spaces around '<<' and fix surrounding code
v4: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 5 +++--
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fe35785..fea85ac 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7197,8 +7197,9 @@ enum {
 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE   (1<<27)
 
 #define GEN8_L3SQCREG4 _MMIO(0xb118)
-#define  GEN8_LQSC_RO_PERF_DIS (1<<27)
-#define  GEN8_LQSC_FLUSH_COHERENT_LINES(1<<21)
+#define  GEN11_LQSC_CLEAN_EVICT_DISABLE(1 << 6)
+#define  GEN8_LQSC_RO_PERF_DIS (1 << 27)
+#define  GEN8_LQSC_FLUSH_COHERENT_LINES(1 << 21)
 
 /* GEN8 chicken */
 #define HDC_CHICKEN0   _MMIO(0x7300)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index d7b2b07..f9c6174 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -726,6 +726,12 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN11_GACB_PERF_CTRL,
   ((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4));
+
+   /* Wa_1405733216:icl
+* Formerly known as WaDisableCleanEvicts
+*/
+   I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
+   GEN11_LQSC_CLEAN_EVICT_DISABLE));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 10/22] drm/i915/icl: Wa_1406680159 and Wa_2201832410

[Oscar Mateo]

Disable GWL clock gating to prevent two different issues that
might cause hangs.

Please notice that one of the issues is pre-production only.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 76059ed..57a69aa 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -751,6 +751,12 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
   (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
MSCUNIT_CLKGATE_DIS));
+
+   /* Wa_1406680159:icl */
+   /* Wa_2201832410:icl (pre-prod, only until C0) */
+   I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
+  (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
+   GWUNIT_CLKGATE_DIS));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 02/22] drm/i915/icl: Enable Sampler DFR

[Oscar Mateo]

Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
power by dynamically changing its clock frequency in low-throughput
conditions. This patches enables it by default on Gen11.

v2: Wrong operation to clear the bit (Praveen)
v3: Rebased on top of the WA refactoring

Cc: Sagar Arun Kamble 
Cc: Praveen Paneri 
Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 4 
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f2ee225..4b7e6bc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8218,6 +8218,9 @@ enum {
 #define GEN8_GARBCNTL   _MMIO(0xB004)
 #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
 
+#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
+#define   DFR_DISABLE  (1 << 9)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 8c2d17c..34a0b56 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -692,6 +692,10 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(_3D_CHICKEN3,
   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
 
+   /* This is not an Wa. Enable to reduce Sampler power */
+   I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
+  (I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE));
+
/* WaInPlaceDecompressionHang:icl */
I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) 
|
 
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
-- 
1.9.1

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[Intel-gfx] [PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing

[Oscar Mateo]

Revert to an L3 non-hash model, for performance reasons.

v2:
  - Place the WA name above the actual change
  - Improve the register naming
v3:
  - Rebased
  - Renamed to Wa_1604223664
v4: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  |  6 ++
 drivers/gpu/drm/i915/intel_workarounds.c | 20 
 2 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a6b1f85..5637cd7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8218,6 +8218,12 @@ enum {
 #define GEN8_GARBCNTL  _MMIO(0xB004)
 #define   GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
 #define   GEN11_ARBITRATION_PRIO_ORDER_MASK(0x3f << 22)
+#define   GEN11_HASH_CTRL_EXCL_MASK(0x7f << 0)
+#define   GEN11_HASH_CTRL_EXCL_BIT0(1 << 0)
+
+#define GEN11_GLBLINVL _MMIO(0xB404)
+#define   GEN11_BANK_HASH_ADDR_EXCL_BIT0   (1 << 0)
+#define   GEN11_BANK_HASH_ADDR_EXCL_MASK   (0x3f << 5)
 
 #define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
 #define   DFR_DISABLE  (1 << 9)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 3a44f6f..a94cd93 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -704,11 +704,23 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES));
 
-   /* Wa_1405543622:icl
-* Formerly known as WaGAPZPriorityScheme
+   I915_WRITE(GEN8_GARBCNTL,
+  /* Wa_1604223664:icl
+   * Formerly known as WaL3BankAddressHashing
+   */
+  ((I915_READ(GEN8_GARBCNTL) & ~GEN11_HASH_CTRL_EXCL_MASK) |
+   GEN11_HASH_CTRL_EXCL_BIT0 |
+   /* Wa_1405543622:icl
+* Formerly known as WaGAPZPriorityScheme
+*/
+   GEN11_ARBITRATION_PRIO_ORDER_MASK));
+
+   /* Wa_1604223664:icl
+* Formerly known as WaL3BankAddressHashing
 */
-   I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
-  GEN11_ARBITRATION_PRIO_ORDER_MASK));
+   I915_WRITE(GEN11_GLBLINVL,
+  ((I915_READ(GEN11_GLBLINVL) & 
~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
+   GEN11_BANK_HASH_ADDR_EXCL_BIT0));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc

[Oscar Mateo]

This workarounds an issue with insufficient storage for the
CL2 and SF units.

v2: Renamed to Wa_1405766107
v3: Wrapped the commit message
v4: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 4 
 drivers/gpu/drm/i915/intel_workarounds.c | 7 +++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fea85ac..43fdd2e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8234,6 +8234,10 @@ enum {
 #define   GEN11_HASH_CTRL_BIT0 (1 << 0)
 #define   GEN11_HASH_CTRL_BIT4 (1 << 12)
 
+#define GEN11_LSN_UNSLCVC  _MMIO(0xB43C)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC (1 << 9)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC  (1 << 7)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index f9c6174..642325a 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -732,6 +732,13 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
 */
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN11_LQSC_CLEAN_EVICT_DISABLE));
+
+   /* Wa_1405766107:icl
+* Formerly known as WaCL2SFHalfMaxAlloc
+*/
+   I915_WRITE(GEN11_LSN_UNSLCVC, (I915_READ(GEN11_LSN_UNSLCVC) |
+  GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
+  
GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 03/22] drm/i915/icl: WaGAPZPriorityScheme

[Oscar Mateo]

The default GAPZ arbitrer priority value at power-on has been found
to be incorrect.

v2: Now renamed to Wa_1405543622

v3: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 5 +++--
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4b7e6bc..a6b1f85 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8215,8 +8215,9 @@ enum {
 #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE   (1<<4)
 #define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6)
 
-#define GEN8_GARBCNTL   _MMIO(0xB004)
-#define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
+#define GEN8_GARBCNTL  _MMIO(0xB004)
+#define   GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
+#define   GEN11_ARBITRATION_PRIO_ORDER_MASK(0x3f << 22)
 
 #define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
 #define   DFR_DISABLE  (1 << 9)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 34a0b56..3a44f6f 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -703,6 +703,12 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
/* WaPipelineFlushCoherentLines:icl */
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES));
+
+   /* Wa_1405543622:icl
+* Formerly known as WaGAPZPriorityScheme
+*/
+   I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
+  GEN11_ARBITRATION_PRIO_ORDER_MASK));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 22/22] drm/i915/icl: WaAllowUMDToModifySamplerMode

[Oscar Mateo]

Required for Bindless samplers.

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 2 ++
 drivers/gpu/drm/i915/intel_workarounds.c | 5 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d008a70..3394cc0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8258,6 +8258,8 @@ enum {
 #define TR_VA_TTL3_PTR_DW0 _MMIO(0x4DE0)
 #define TR_VA_TTL3_PTR_DW1 _MMIO(0x4DE4)
 
+#define GEN10_SAMPLER_MODE _MMIO(0xE18C)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index b52ac41..d8f0cf9 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -981,6 +981,11 @@ static int icl_whitelist_workarounds_apply(struct 
intel_engine_cs *engine)
if (ret)
return ret;
 
+   /* WaAllowUMDToModifySamplerMode:icl */
+   ret = wa_ring_whitelist_reg(engine, GEN10_SAMPLER_MODE);
+   if (ret)
+   return ret;
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 16/22] drm/i915/icl: Wa_2006665173

[Oscar Mateo]

Disable blend embellishment in RCC.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 18 +++---
 drivers/gpu/drm/i915/intel_workarounds.c |  5 +
 2 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 452e24d..71696dc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7157,13 +7157,17 @@ enum {
 
 /* GEN7 chicken */
 #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
-# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
-# define GEN9_RHWO_OPTIMIZATION_DISABLE(1<<14)
-#define COMMON_SLICE_CHICKEN2  _MMIO(0x7014)
-# define GEN9_PBE_COMPRESSED_HASH_SELECTION(1<<13)
-# define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12)
-# define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
-# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE  (1<<0)
+  #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC((1 << 10) | (1 << 26))
+  #define GEN9_RHWO_OPTIMIZATION_DISABLE   (1 << 14)
+
+#define COMMON_SLICE_CHICKEN2  _MMIO(0x7014)
+  #define GEN9_PBE_COMPRESSED_HASH_SELECTION   (1 << 13)
+  #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE   (1 << 12)
+  #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8)
+  #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0)
+
+#define GEN11_COMMON_SLICE_CHICKEN3_MMIO(0x7304)
+  #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC   (1 << 11)
 
 #define HIZ_CHICKEN_MMIO(0x7018)
 # define CHV_HZ_8X8_MODE_IN_1X (1<<15)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 5884a7d5..90906ab 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -470,6 +470,11 @@ static int icl_ctx_workarounds_init(struct 
drm_i915_private *dev_priv)
WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
  GEN11_STATE_CACHE_REDIRECT_TO_CS);
 
+   /* Wa_2006665173:icl (pre-prod) */
+   if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+   WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
+ GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 08/22] drm/i915/icl: WaDisCtxReload

[Oscar Mateo]

Revert to the legacy implementation to avoid a system hang.

v2: Correct the address for GAMW_ECO_DEV_RW_IA_REG
v3: Renamed to Wa_220166154
v4: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 43fdd2e..161d04e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8238,6 +8238,9 @@ enum {
 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC (1 << 9)
 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC  (1 << 7)
 
+#define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
+#define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE  (1 << 7)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD 
Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 642325a..75fad6f 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -739,6 +739,12 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN11_LSN_UNSLCVC, (I915_READ(GEN11_LSN_UNSLCVC) |
   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
   
GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC));
+
+   /* Wa_220166154:icl
+* Formerly known as WaDisCtxReload
+*/
+   I915_WRITE(GAMW_ECO_DEV_RW_IA_REG, (I915_READ(GAMW_ECO_DEV_RW_IA_REG) |
+   GAMW_ECO_DEV_CTX_RELOAD_DISABLE));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH 14/22] drm/i915/icl: WaDisableImprovedTdlClkGating

[Oscar Mateo]

Revert to the legacy implementation.

v2: GEN7_ROW_CHICKEN2 is masked
v3:
  - Rebased
  - Renamed to Wa_2006611047
  - A0 and B0 only
v4:
  - Add spaces around '<<' (and fix the surrounding code as well)
  - Mark the WA as pre-prod
v5: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 5 +++--
 drivers/gpu/drm/i915/intel_workarounds.c | 7 +++
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cfb9b0d..fca143b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8284,8 +8284,9 @@ enum {
 
 #define GEN7_ROW_CHICKEN2  _MMIO(0xe4f4)
 #define GEN7_ROW_CHICKEN2_GT2  _MMIO(0xf4f4)
-#define   DOP_CLOCK_GATING_DISABLE (1<<0)
-#define   PUSH_CONSTANT_DEREF_DISABLE  (1<<8)
+#define   DOP_CLOCK_GATING_DISABLE (1 << 0)
+#define   PUSH_CONSTANT_DEREF_DISABLE  (1 << 8)
+#define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE   (1 << 1)
 
 #define HSW_ROW_CHICKEN3   _MMIO(0xe49c)
 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE(1 << 6)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 413a43d..6c03af0 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -459,6 +459,13 @@ static int icl_ctx_workarounds_init(struct 
drm_i915_private *dev_priv)
 */
WA_SET_BIT_MASKED(ICL_HDC_CHICKEN0, HDC_FORCE_NON_COHERENT);
 
+   /* Wa_2006611047:icl (pre-prod)
+* Formerly known as WaDisableImprovedTdlClkGating
+*/
+   if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+   WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
+
return 0;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 15/22] drm/i915/icl: WaEnableStateCacheRedirectToCS

[Oscar Mateo]

Redirects the state cache to the CS Command buffer section for
performance reasons.

v2: Rebased
v3: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_reg.h  | 1 +
 drivers/gpu/drm/i915/intel_workarounds.c | 4 
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fca143b..452e24d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7173,6 +7173,7 @@ enum {
 #define  DISABLE_PIXEL_MASK_CAMMING(1<<14)
 
 #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
+#define   GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
 
 #define GEN7_L3SQCREG1 _MMIO(0xB010)
 #define  VLV_B0_WA_L3SQCREG1_VALUE 0x00D3
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 6c03af0..5884a7d5 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -466,6 +466,10 @@ static int icl_ctx_workarounds_init(struct 
drm_i915_private *dev_priv)
WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
  GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
 
+   /* WaEnableStateCacheRedirectToCS:icl */
+   WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
+ GEN11_STATE_CACHE_REDIRECT_TO_CS);
+
return 0;
 }
 
-- 
1.9.1

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Re: [Intel-gfx] [PATCH igt] igt/gem_exec_schedule: Exercise preemption timeout

[Chris Wilson]

Quoting Antonio Argenziano (2018-04-13 16:54:27)
> 
> 
> On 13/04/18 07:14, Chris Wilson wrote:
> > Set up a unpreemptible spinner such that the only way we can inject a
> > high priority request onto the GPU is by resetting the spinner. The test
> > fails if we trigger hangcheck rather than the fast timeout mechanism.
> > 
> > Signed-off-by: Chris Wilson 
> > ---
> >   lib/i915/gem_context.c| 72 +++
> >   lib/i915/gem_context.h|  3 ++
> >   lib/igt_dummyload.c   | 12 +--
> >   lib/igt_dummyload.h   |  3 ++
> >   tests/gem_exec_schedule.c | 34 ++
> >   5 files changed, 106 insertions(+), 18 deletions(-)
> > 
> 
> ...
> 
> > @@ -449,8 +457,6 @@ void igt_spin_batch_end(igt_spin_t *spin)
> >   if (!spin)
> >   return;
> >   
> > - igt_assert(*spin->batch == MI_ARB_CHK ||
> > -*spin->batch == MI_BATCH_BUFFER_END);
> 
> I am not sure why we needed this, but it seems safe to remove.
> 
> >   *spin->batch = MI_BATCH_BUFFER_END;
> >   __sync_synchronize();
> >   }
> 
> > diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
> > index 6ff15b6ef..93254945b 100644
> > --- a/tests/gem_exec_schedule.c
> > +++ b/tests/gem_exec_schedule.c
> > @@ -656,6 +656,37 @@ static void preemptive_hang(int fd, unsigned ring)
> >   gem_context_destroy(fd, ctx[HI]);
> >   }
> >   
> > +static void preempt_timeout(int fd, unsigned ring)
> > +{
> > + igt_spin_t *spin[3];
> > + uint32_t ctx;
> > +
> > + igt_require(__gem_context_set_preempt_timeout(fd, 0, 0));
> > +
> > + ctx = gem_context_create(fd);
> > + gem_context_set_priority(fd, ctx, MIN_PRIO);
> > + spin[0] = __igt_spin_batch_new_hang(fd, ctx, ring);
> > + spin[1] = __igt_spin_batch_new_hang(fd, ctx, ring);
> > + gem_context_destroy(fd, ctx);
> > +
> > + ctx = gem_context_create(fd);
> > + gem_context_set_priority(fd, ctx, MAX_PRIO);
> > + gem_context_set_preempt_timeout(fd, ctx, 1000 * 1000);
> > + spin[2] = __igt_spin_batch_new(fd, ctx, ring, 0);
> > + gem_context_destroy(fd, ctx);
> > +
> > + igt_spin_batch_end(spin[2]);
> > + gem_sync(fd, spin[2]->handle);
> 
> Does this guarantee that spin[1] did not overtake spin[2]?

It does as well. Neither spin[0] or spin[1] can complete without being
reset at this point. If they are reset (by hangcheck) we detect that and
die. What we expect to happen is spin[0] is (more or less, there is still
dmesg) silently killed by the preempt timeout. If that timeout doesn't
happen, more hangcheck. What we don't check here is how quick. Now we
could reasonably assert that the spin[2] -> gem_sync takes less than 2ms.
-Chris
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Re: [Intel-gfx] [PATCH igt] igt/gem_exec_schedule: Exercise preemption timeout

[Antonio Argenziano]

On 13/04/18 07:14, Chris Wilson wrote:

Set up a unpreemptible spinner such that the only way we can inject a
high priority request onto the GPU is by resetting the spinner. The test
fails if we trigger hangcheck rather than the fast timeout mechanism.

Signed-off-by: Chris Wilson 
---
  lib/i915/gem_context.c| 72 +++
  lib/i915/gem_context.h|  3 ++
  lib/igt_dummyload.c   | 12 +--
  lib/igt_dummyload.h   |  3 ++
  tests/gem_exec_schedule.c | 34 ++
  5 files changed, 106 insertions(+), 18 deletions(-)



...


@@ -449,8 +457,6 @@ void igt_spin_batch_end(igt_spin_t *spin)
if (!spin)
return;
  
-	igt_assert(*spin->batch == MI_ARB_CHK ||

-  *spin->batch == MI_BATCH_BUFFER_END);


I am not sure why we needed this, but it seems safe to remove.


*spin->batch = MI_BATCH_BUFFER_END;
__sync_synchronize();
  }



diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
index 6ff15b6ef..93254945b 100644
--- a/tests/gem_exec_schedule.c
+++ b/tests/gem_exec_schedule.c
@@ -656,6 +656,37 @@ static void preemptive_hang(int fd, unsigned ring)
gem_context_destroy(fd, ctx[HI]);
  }
  
+static void preempt_timeout(int fd, unsigned ring)

+{
+   igt_spin_t *spin[3];
+   uint32_t ctx;
+
+   igt_require(__gem_context_set_preempt_timeout(fd, 0, 0));
+
+   ctx = gem_context_create(fd);
+   gem_context_set_priority(fd, ctx, MIN_PRIO);
+   spin[0] = __igt_spin_batch_new_hang(fd, ctx, ring);
+   spin[1] = __igt_spin_batch_new_hang(fd, ctx, ring);
+   gem_context_destroy(fd, ctx);
+
+   ctx = gem_context_create(fd);
+   gem_context_set_priority(fd, ctx, MAX_PRIO);
+   gem_context_set_preempt_timeout(fd, ctx, 1000 * 1000);
+   spin[2] = __igt_spin_batch_new(fd, ctx, ring, 0);
+   gem_context_destroy(fd, ctx);
+
+   igt_spin_batch_end(spin[2]);
+   gem_sync(fd, spin[2]->handle);


Does this guarantee that spin[1] did not overtake spin[2]?

Thanks,
Antonio


+
+   /* spin[0] is kicked, leaving spin[1] running */
+
+   igt_assert(gem_bo_busy(fd, spin[1]->handle));
+
+   igt_spin_batch_free(fd, spin[2]);
+   igt_spin_batch_free(fd, spin[1]);
+   igt_spin_batch_free(fd, spin[0]);
+}
+
  static void deep(int fd, unsigned ring)
  {
  #define XS 8
@@ -1120,6 +1151,9 @@ igt_main
igt_subtest_f("preempt-self-%s", 
e->name)
preempt_self(fd, e->exec_id | 
e->flags);
  
+	igt_subtest_f("preempt-timeout-%s", e->name)

+   preempt_timeout(fd, e->exec_id | 
e->flags);
+
igt_subtest_f("preempt-other-%s", 
e->name)
preempt_other(fd, e->exec_id | 
e->flags, 0);
  


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Re: [Intel-gfx] [PATCH v2 3/4] drm/i915: Check hdcp key loadability

[Daniel Vetter]

On Wed, Apr 11, 2018 at 01:57:15PM +0530, Ramalingam C wrote:
> 
> 
> On Monday 09 April 2018 01:58 PM, Daniel Vetter wrote:
> > On Fri, Apr 06, 2018 at 07:02:02PM +0300, Ville Syrjälä wrote:
> > > On Mon, Apr 02, 2018 at 02:35:42PM +0530, Ramalingam C wrote:
> > > > 
> > > > On Thursday 29 March 2018 07:54 PM, Ville Syrjälä wrote:
> > > > > On Thu, Mar 29, 2018 at 07:39:07PM +0530, Ramalingam C wrote:
> > > > > > HDCP1.4 key can be loaded, only when Power well #1 is enabled and 
> > > > > > cdclk
> > > > > > is enabled. Using the I915 power well infrastruture, above 
> > > > > > requirement
> > > > > > is verified.
> > > > > > 
> > > > > > This patch enables the hdcp initialization for HSW, BDW, and BXT.
> > > > > > 
> > > > > > v2:
> > > > > > Choose the PW# based on the platform.
> > > > > > 
> > > > > > Signed-off-by: Ramalingam C 
> > > > > > Reviewed-by: Sean Paul 
> > > > > > ---
> > > > > >drivers/gpu/drm/i915/intel_hdcp.c | 41 
> > > > > > +--
> > > > > >1 file changed, 39 insertions(+), 2 deletions(-)
> > > > > > 
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_hdcp.c 
> > > > > > b/drivers/gpu/drm/i915/intel_hdcp.c
> > > > > > index f77d956b2b18..d8af09b46a44 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_hdcp.c
> > > > > > +++ b/drivers/gpu/drm/i915/intel_hdcp.c
> > > > > > @@ -37,6 +37,43 @@ static int intel_hdcp_poll_ksv_fifo(struct 
> > > > > > intel_digital_port *intel_dig_port,
> > > > > > return 0;
> > > > > >}
> > > > > > +static bool hdcp_key_loadable(struct drm_i915_private *dev_priv)
> > > > > > +{
> > > > > > +   struct i915_power_domains *power_domains = 
> > > > > > _priv->power_domains;
> > > > > > +   struct i915_power_well *power_well;
> > > > > > +   enum i915_power_well_id id;
> > > > > > +   bool enabled = false;
> > > > > > +
> > > > > > +   /*
> > > > > > +* On HSW and BDW, Display HW loads the Key as soon as Display 
> > > > > > resumes.
> > > > > > +* On all BXT+, SW can load the keys only when the PW#1 is 
> > > > > > turned on.
> > > > > > +*/
> > > > > > +   if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> > > > > > +   id = HSW_DISP_PW_GLOBAL;
> > > > > > +   else
> > > > > > +   id = SKL_DISP_PW_1;
> > > > > > +
> > > > > > +   mutex_lock(_domains->lock);
> > > > > > +
> > > > > > +   /* PG1 (power well #1) needs to be enabled */
> > > > > > +   for_each_power_well(dev_priv, power_well) {
> > > > > > +   if (power_well->id == id) {
> > > > > > +   enabled = power_well->ops->is_enabled(dev_priv,
> > > > > > + 
> > > > > > power_well);
> > > > > > +   break;
> > > > > > +   }
> > > > > > +   }
> > > > > > +   mutex_unlock(_domains->lock);
> > > > > > +
> > > > > > +   /*
> > > > > > +* Another req for hdcp key loadability is enabled state of pll 
> > > > > > for
> > > > > > +* cdclk. Without active crtc we wont land here. So we are 
> > > > > > assuming that
> > > > > > +* cdclk is already on.
> > > > > > +*/
> > > > > > +
> > > > > > +   return enabled;
> > > > > > +}
> > > > > > +
> > > > > >static void intel_hdcp_clear_keys(struct drm_i915_private 
> > > > > > *dev_priv)
> > > > > >{
> > > > > > I915_WRITE(HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER);
> > > > > > @@ -615,8 +652,8 @@ static int _intel_hdcp_enable(struct 
> > > > > > intel_connector *connector)
> > > > > > DRM_DEBUG_KMS("[%s:%d] HDCP is being enabled...\n",
> > > > > >   connector->base.name, connector->base.base.id);
> > > > > > -   if (!(I915_READ(SKL_FUSE_STATUS) & SKL_FUSE_PG_DIST_STATUS(1))) 
> > > > > > {
> > > > > > -   DRM_ERROR("PG1 is disabled, cannot load keys\n");
> > > > > > +   if (!hdcp_key_loadable(dev_priv)) {
> > > > > > +   DRM_ERROR("HDCP key Load is not possible\n");
> > > > > > return -ENXIO;
> > > > > > }
> > > > > If you need the power well then why aren't you grabbing the correct
> > > > > power domain reference somewhere?
> > > > Ville,
> > > > 
> > > > As HDCP is supposed to be enabled after the basic display is up, power 
> > > > well #1 is supposed to be enabled.
> > > > If not that is mostly an error w.r.t HDCP.
> > > > 
> > > > So at this point we just want to verify whether required PW is up and 
> > > > HDCP key can be loaded from the HW. Else fail the HDCP request.
> > > So this is in practice dead code to deal with a hypothetical bug
> > > elsewhere in the driver?
> > Yeah looks like it should be wrapped in a WARN_ON, or maybe outright
> > thrown out. The unclaimed mmio debug stuff will catch when this happens
> > (or well, should).
> > -Daniel
> Ok. Intention of this patch was generalizing the existing SKL specific PW
> check for all hdcp capable intel platforms.
> Please suggest if this needs to be wrapped into WARN_ON or really want to
> discard 

[Intel-gfx] ✗ Fi.CI.BAT: failure for igt/gem_exec_schedule: Exercise preemption timeout

[Patchwork]

== Series Details ==

Series: igt/gem_exec_schedule: Exercise preemption timeout
URL   : https://patchwork.freedesktop.org/series/41679/
State : failure

== Summary ==

Applying: igt/gem_exec_schedule: Exercise preemption timeout
Using index info to reconstruct a base tree...
M   tests/gem_exec_schedule.c
Falling back to patching base and 3-way merge...
Auto-merging tests/gem_exec_schedule.c
CONFLICT (content): Merge conflict in tests/gem_exec_schedule.c
Patch failed at 0001 igt/gem_exec_schedule: Exercise preemption timeout
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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[Intel-gfx] [PATCH igt] igt/gem_exec_schedule: Exercise preemption timeout

[Chris Wilson]

Set up a unpreemptible spinner such that the only way we can inject a
high priority request onto the GPU is by resetting the spinner. The test
fails if we trigger hangcheck rather than the fast timeout mechanism.

Signed-off-by: Chris Wilson 
---
 lib/i915/gem_context.c| 72 +++
 lib/i915/gem_context.h|  3 ++
 lib/igt_dummyload.c   | 12 +--
 lib/igt_dummyload.h   |  3 ++
 tests/gem_exec_schedule.c | 34 ++
 5 files changed, 106 insertions(+), 18 deletions(-)

diff --git a/lib/i915/gem_context.c b/lib/i915/gem_context.c
index 669bd318c..c76f78d97 100644
--- a/lib/i915/gem_context.c
+++ b/lib/i915/gem_context.c
@@ -112,15 +112,17 @@ uint32_t gem_context_create(int fd)
 int __gem_context_destroy(int fd, uint32_t ctx_id)
 {
struct drm_i915_gem_context_destroy destroy;
-   int ret;
+   int err;
 
memset(, 0, sizeof(destroy));
destroy.ctx_id = ctx_id;
 
-   ret = igt_ioctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY, );
-   if (ret)
-   return -errno;
-   return 0;
+   err = 0;
+   if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY, ))
+   err = -errno;
+
+   errno = 0;
+   return err;
 }
 
 /**
@@ -142,11 +144,14 @@ void gem_context_destroy(int fd, uint32_t ctx_id)
 
 int __gem_context_get_param(int fd, struct drm_i915_gem_context_param *p)
 {
+   int err;
+
+   err = 0;
if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, p))
-   return -errno;
+   err = -errno;
 
errno = 0;
-   return 0;
+   return err;
 }
 
 /**
@@ -159,17 +164,20 @@ int __gem_context_get_param(int fd, struct 
drm_i915_gem_context_param *p)
  */
 void gem_context_get_param(int fd, struct drm_i915_gem_context_param *p)
 {
-   igt_assert(__gem_context_get_param(fd, p) == 0);
+   igt_assert_eq(__gem_context_get_param(fd, p), 0);
 }
 
 
 int __gem_context_set_param(int fd, struct drm_i915_gem_context_param *p)
 {
+   int err;
+
+   err = 0;
if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, p))
-   return -errno;
+   err = -errno;
 
errno = 0;
-   return 0;
+   return err;
 }
 /**
  * gem_context_set_param:
@@ -181,7 +189,7 @@ int __gem_context_set_param(int fd, struct 
drm_i915_gem_context_param *p)
  */
 void gem_context_set_param(int fd, struct drm_i915_gem_context_param *p)
 {
-   igt_assert(__gem_context_set_param(fd, p) == 0);
+   igt_assert_eq(__gem_context_set_param(fd, p), 0);
 }
 
 /**
@@ -234,8 +242,6 @@ void gem_context_require_bannable(int fd)
igt_require(has_ban_period || has_bannable);
 }
 
-#define DRM_I915_CONTEXT_PARAM_PRIORITY 0x6
-
 /**
  * __gem_context_set_priority:
  * @fd: open i915 drm file descriptor
@@ -255,7 +261,7 @@ int __gem_context_set_priority(int fd, uint32_t ctx_id, int 
prio)
memset(, 0, sizeof(p));
p.ctx_id = ctx_id;
p.size = 0;
-   p.param = DRM_I915_CONTEXT_PARAM_PRIORITY;
+   p.param = I915_CONTEXT_PARAM_PRIORITY;
p.value = prio;
 
return __gem_context_set_param(fd, );
@@ -271,5 +277,41 @@ int __gem_context_set_priority(int fd, uint32_t ctx_id, 
int prio)
  */
 void gem_context_set_priority(int fd, uint32_t ctx_id, int prio)
 {
-   igt_assert(__gem_context_set_priority(fd, ctx_id, prio) == 0);
+   igt_assert_eq(__gem_context_set_priority(fd, ctx_id, prio), 0);
+}
+
+/**
+ * __gem_context_set_preempt_timeout:
+ * @fd: open i915 drm file descriptor
+ * @ctx_id: i915 context id
+ * @timeout_ns: desired preempt_timeout
+ *
+ * Returns: An integer equal to zero for success and negative for failure
+ */
+int __gem_context_set_preempt_timeout(int fd, uint32_t ctx, uint64_t 
timeout_ns)
+{
+#define LOCAL_CONTEXT_PARAM_PREEMPT_TIMEOUT 7
+   struct drm_i915_gem_context_param p;
+
+   memset(, 0, sizeof(p));
+   p.ctx_id = ctx;
+   p.size = 0;
+   p.param = LOCAL_CONTEXT_PARAM_PREEMPT_TIMEOUT;
+   p.value = timeout_ns;
+
+   return __gem_context_set_param(fd, );
+}
+
+/**
+ * gem_context_set_preempt_timeout:
+ * @fd: open i915 drm file descriptor
+ * @ctx: i915 context id
+ * @timeout_ns: desired preempt timeout
+ *
+ * Like __gem_context_set_priority(), except we assert on failure.
+ */
+void gem_context_set_preempt_timeout(int fd, uint32_t ctx, uint64_t timeout_ns)
+{
+   igt_assert_eq(__gem_context_set_preempt_timeout(fd, ctx, timeout_ns),
+ 0);
 }
diff --git a/lib/i915/gem_context.h b/lib/i915/gem_context.h
index aef68dda6..634bf584e 100644
--- a/lib/i915/gem_context.h
+++ b/lib/i915/gem_context.h
@@ -45,4 +45,7 @@ int __gem_context_get_param(int fd, struct 
drm_i915_gem_context_param *p);
 int __gem_context_set_priority(int fd, uint32_t ctx, int prio);
 void gem_context_set_priority(int fd, uint32_t ctx, int prio);
 
+int __gem_context_set_preempt_timeout(int fd, uint32_t ctx, uint64_t 

[Intel-gfx] ✗ Fi.CI.BAT: failure for igt: Add gem_ctx_freq to exercise requesting freq on a ctx (rev3)

[Patchwork]

== Series Details ==

Series: igt: Add gem_ctx_freq to exercise requesting freq on a ctx (rev3)
URL   : https://patchwork.freedesktop.org/series/39571/
State : failure

== Summary ==

IGT patchset build failed on latest successful build
80e4910581c7310258375a003a5de9a57ed24546 lib: Adjust refactored gpu_fill 
library to our coding style

Source dir: /home/cidrm/intel-gpu-tools
Build dir: /home/cidrm/intel-gpu-tools/build
Build type: native build
Project name: intel-gpu-tools
Native c compiler: ccache cc (gcc 6.3.0)
Appending CPPFLAGS from environment: '-I/home/cidrm/kernel_headers/include'
Build machine cpu family: x86_64
Build machine cpu: x86_64
Compiler for c supports argument -Wno-unused-parameter: YES
Compiler for c supports argument -Wno-sign-compare: YES
Compiler for c supports argument -Wno-missing-field-initializers: YES
Compiler for c supports argument -Wno-clobbered: YES
Compiler for c supports argument -Wno-type-limits: YES
Compiler for c supports argument -Wimplicit-fallthrough=0: NO
Found pkg-config: /usr/bin/pkg-config (0.29.1)
Native dependency libdrm found: YES 2.4.91
Native dependency libdrm_intel found: YES 2.4.91
Native dependency libdrm_nouveau found: NO found '2.4.76' but need: '>=2.4.82'
Dependency libdrm_nouveau found: NO
Native dependency libdrm_amdgpu found: NO found '2.4.76' but need: '>=2.4.82'
Dependency libdrm_amdgpu found: NO
Native dependency pciaccess found: YES 0.13.4
Native dependency libkmod found: YES 22
Native dependency libprocps found: YES 3.3.12
Native dependency libunwind found: YES 1.1
Native dependency cairo found: YES 1.14.8
Native dependency libudev found: YES 232
Native dependency glib-2.0 found: YES 2.52.0
Native dependency gsl found: YES 2.3
Dependency alsa found: NO
Native dependency pixman-1 found: YES 0.34.0
Dependency xmlrpc found: NO
Dependency xmlrpc_util found: NO
Dependency xmlrpc_client found: NO
Program xmlrpc-c-config found: YES (/usr/bin/xmlrpc-c-config)
Dependency threads found: YES
Library m found: YES
Library rt found: YES
Library dl found: YES
Library z found: YES
Has header "linux/kd.h": YES
Has header "sys/kd.h": YES
Has header "libgen.h": YES
Has header "sys/io.h": YES
Has header "cpuid.h": YES
Checking whether type "struct sysinfo" has member "totalram": YES
Configuring config.h using configuration

Meson encountered an error in file tests/meson.build, line 306, column 1:
Tried to create target "gem_ctx_freq", but a target of that name already exists.

___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: content-type property for HDMI connector

[Patchwork]

== Series Details ==

Series: drm/i915: content-type property for HDMI connector
URL   : https://patchwork.freedesktop.org/series/41677/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4053 -> Patchwork_8687 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/41677/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_8687 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_mmap_gtt@basic-small-bo-tiledx:
  fi-gdg-551: PASS -> FAIL (fdo#102575)

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
  fi-bxt-dsi: PASS -> INCOMPLETE (fdo#103927)


 Possible fixes 

igt@debugfs_test@read_all_entries:
  fi-snb-2520m:   INCOMPLETE (fdo#103713) -> PASS


  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927


== Participating hosts (35 -> 33) ==

  Missing(2): fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4053 -> Patchwork_8687

  CI_DRM_4053: e2599f775a9c1c27f702e90e6432e555764edcd8 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4429: 80e4910581c7310258375a003a5de9a57ed24546 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8687: 3e378ba61f9d60d5b6d6b9c48cd00b66fad32c21 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4429: 93b35926a150e318439d2505901288594b3548f5 @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

3e378ba61f9d drm/i915: content-type property for HDMI connector

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8687/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for Enable NV12 support

[Patchwork]

== Series Details ==

Series: Enable NV12 support
URL   : https://patchwork.freedesktop.org/series/41674/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4052_full -> Patchwork_8686_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_8686_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8686_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/41674/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_8686_full:

  === IGT changes ===

 Warnings 

igt@gem_mocs_settings@mocs-rc6-ctx-render:
  shard-kbl:  PASS -> SKIP

igt@gem_mocs_settings@mocs-rc6-render:
  shard-kbl:  SKIP -> PASS

igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu:
  shard-snb:  SKIP -> PASS +2


== Known issues ==

  Here are the changes found in Patchwork_8686_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_flip@2x-dpms-vs-vblank-race:
  shard-hsw:  PASS -> FAIL (fdo#103060)

igt@perf_pmu@rc6-runtime-pm-long:
  shard-kbl:  PASS -> FAIL (fdo#105010)


 Possible fixes 

igt@kms_flip@2x-plain-flip-fb-recreate:
  shard-hsw:  FAIL (fdo#100368) -> PASS +1

igt@kms_flip@flip-vs-expired-vblank-interruptible:
  shard-hsw:  FAIL (fdo#105189) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#105010 https://bugs.freedesktop.org/show_bug.cgi?id=105010
  fdo#105189 https://bugs.freedesktop.org/show_bug.cgi?id=105189


== Participating hosts (6 -> 4) ==

  Missing(2): shard-glk shard-glkb 


== Build changes ==

* Linux: CI_DRM_4052 -> Patchwork_8686

  CI_DRM_4052: ff6d5cf7b19871af5657774f4e8f5f91f6285e12 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4429: 80e4910581c7310258375a003a5de9a57ed24546 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8686: ff50c03cffbe8d8fbedbd51d5cab2b4ea6e0e2bb @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4429: 93b35926a150e318439d2505901288594b3548f5 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8686/shards.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm/i915: content-type property for HDMI connector

[StanLis]

From: Stanislav Lisovskiy 

Added content_type property to
drm_connector_state in order to properly handle
external HDMI TV content-type setting.

Signed-off-by: Stanislav Lisovskiy 
---
 drivers/gpu/drm/drm_atomic.c|  4 
 drivers/gpu/drm/drm_connector.c | 34 +
 drivers/gpu/drm/drm_edid.c  |  1 +
 drivers/gpu/drm/i915/intel_atomic.c |  1 +
 drivers/gpu/drm/i915/intel_drv.h|  1 +
 drivers/gpu/drm/i915/intel_hdmi.c   |  4 
 drivers/gpu/drm/i915/intel_modes.c  | 10 +
 include/drm/drm_connector.h |  2 ++
 include/drm/drm_mode_config.h   |  5 +
 include/uapi/drm/drm_mode.h |  5 +
 10 files changed, 67 insertions(+)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 7d25c42f22db..72fd2a1c801f 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -1266,6 +1266,8 @@ static int drm_atomic_connector_set_property(struct 
drm_connector *connector,
state->link_status = val;
} else if (property == config->aspect_ratio_property) {
state->picture_aspect_ratio = val;
+   } else if (property == config->content_type_property) {
+   state->content_type = val;
} else if (property == connector->scaling_mode_property) {
state->scaling_mode = val;
} else if (property == connector->content_protection_property) {
@@ -1351,6 +1353,8 @@ drm_atomic_connector_get_property(struct drm_connector 
*connector,
*val = state->link_status;
} else if (property == config->aspect_ratio_property) {
*val = state->picture_aspect_ratio;
+   } else if (property == config->content_type_property) {
+   *val = state->content_type;
} else if (property == connector->scaling_mode_property) {
*val = state->scaling_mode;
} else if (property == connector->content_protection_property) {
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index b3cde897cd80..d03586edd483 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -720,6 +720,13 @@ static const struct drm_prop_enum_list 
drm_aspect_ratio_enum_list[] = {
{ DRM_MODE_PICTURE_ASPECT_16_9, "16:9" },
 };
 
+static const struct drm_prop_enum_list drm_content_type_enum_list[] = {
+   { DRM_MODE_CONTENT_TYPE_GRAPHICS, "GRAPHICS" },
+   { DRM_MODE_CONTENT_TYPE_PHOTO, "PHOTO" },
+   { DRM_MODE_CONTENT_TYPE_CINEMA, "CINEMA" },
+   { DRM_MODE_CONTENT_TYPE_GAME, "GAME" },
+};
+
 static const struct drm_prop_enum_list drm_panel_orientation_enum_list[] = {
{ DRM_MODE_PANEL_ORIENTATION_NORMAL,"Normal"},
{ DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP, "Upside Down"   },
@@ -1260,6 +1267,33 @@ int drm_mode_create_aspect_ratio_property(struct 
drm_device *dev)
 }
 EXPORT_SYMBOL(drm_mode_create_aspect_ratio_property);
 
+/**
+ * drm_mode_create_content_type_property - create content type property
+ * @dev: DRM device
+ *
+ * Called by a driver the first time it's needed, must be attached to desired
+ * connectors.
+ *
+ * Returns:
+ * Zero on success, negative errno on failure.
+ */
+int drm_mode_create_content_type_property(struct drm_device *dev)
+{
+   if (dev->mode_config.content_type_property)
+   return 0;
+
+   dev->mode_config.content_type_property =
+   drm_property_create_enum(dev, 0, "content type",
+   drm_content_type_enum_list,
+   ARRAY_SIZE(drm_content_type_enum_list));
+
+   if (dev->mode_config.content_type_property == NULL)
+   return -ENOMEM;
+
+   return 0;
+}
+EXPORT_SYMBOL(drm_mode_create_content_type_property);
+
 /**
  * drm_mode_create_suggested_offset_properties - create suggests offset 
properties
  * @dev: DRM device
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 134069f36482..946a182e0201 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4867,6 +4867,7 @@ drm_hdmi_avi_infoframe_from_display_mode(struct 
hdmi_avi_infoframe *frame,
}
 
frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
+   frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
 
/*
 * Populate picture aspect ratio from either
diff --git a/drivers/gpu/drm/i915/intel_atomic.c 
b/drivers/gpu/drm/i915/intel_atomic.c
index 40285d1b91b7..61ddb5871d8a 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -124,6 +124,7 @@ int intel_digital_connector_atomic_check(struct 
drm_connector *conn,
if (new_conn_state->force_audio != old_conn_state->force_audio ||
new_conn_state->broadcast_rgb != old_conn_state->broadcast_rgb ||
new_conn_state->base.picture_aspect_ratio != 

Re: [Intel-gfx] [RFC v2 2/2] drm/i915/gmbus: Enable burst read

[Jani Nikula]

On Thu, 12 Apr 2018, Ramalingam C  wrote:
> Support for Burst read in HW is added for HDCP2.2 compliance
> requirement.
>
> This patch enables the burst read for all the gmbus read of more than
> 511Bytes, on capable platforms.
>
> v2:
>   Extra line is removed.
>
> Signed-off-by: Ramalingam C 
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  1 +
>  drivers/gpu/drm/i915/intel_i2c.c | 38 ++
>  2 files changed, 35 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4f583da0cee9..0ef162ee9ce0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2984,6 +2984,7 @@ enum i915_power_well_id {
>  #define   GMBUS_RATE_400KHZ  (2<<8) /* reserved on Pineview */
>  #define   GMBUS_RATE_1MHZ(3<<8) /* reserved on Pineview */
>  #define   GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
> +#define   GMBUS_BYTE_CNT_OVERRIDE (1<<6)
>  #define   GMBUS_PIN_DISABLED 0
>  #define   GMBUS_PIN_SSC  1
>  #define   GMBUS_PIN_VGADDC   2
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c 
> b/drivers/gpu/drm/i915/intel_i2c.c
> index 7e92c7934657..2ee9cf2effcd 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -364,12 +364,24 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
>  static int
>  gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
> unsigned short addr, u8 *buf, unsigned int len,
> -   u32 gmbus1_index)
> +   u32 gmbus1_index, bool burst_read)

I think you could throw out the burst_read parameter. See below.

>  {
> + unsigned int bytes_af_override, size;
> +
> + if (burst_read) {
> + bytes_af_override = len - (((len / 256) - 1) * 256);
> + size = bytes_af_override;
> +
> + I915_WRITE_FW(GMBUS0, (I915_READ_FW(GMBUS0) |
> +   GMBUS_BYTE_CNT_OVERRIDE));
> + } else {
> + size = len;
> + }
> +
>   I915_WRITE_FW(GMBUS1,
> gmbus1_index |
> GMBUS_CYCLE_WAIT |
> -   (len << GMBUS_BYTE_COUNT_SHIFT) |
> +   (size << GMBUS_BYTE_COUNT_SHIFT) |
> (addr << GMBUS_SLAVE_ADDR_SHIFT) |
> GMBUS_SLAVE_READ | GMBUS_SW_RDY);
>   while (len) {
> @@ -385,11 +397,23 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
>   *buf++ = val & 0xff;
>   val >>= 8;
>   } while (--len && ++loop < 4);
> +
> + if (burst_read && len == (bytes_af_override - 4))
> + I915_WRITE_FW(GMBUS0, (I915_READ_FW(GMBUS0) &
> +   ~GMBUS_BYTE_CNT_OVERRIDE));
>   }
>  
>   return 0;
>  }
>  
> +static bool gmbus_burst_read_supported(struct drm_i915_private *dev_priv)
> +{
> + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) ||
> + IS_KABYLAKE(dev_priv))
> + return true;
> + return false;
> +}

Name this HAS_GMBUS_BURST_READ() and put below HAS_GMBUS_IRQ() in
i915_drv.h.

> +
>  static int
>  gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
>   u32 gmbus1_index)
> @@ -398,15 +422,21 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, 
> struct i2c_msg *msg,
>   unsigned int rx_size = msg->len;
>   unsigned int len;
>   int ret;
> + bool burst_read = false;
> +
> + if (rx_size > BXT_GMBUS_BYTE_COUNT_MAX)
> + burst_read = gmbus_burst_read_supported(dev_priv);
>  
>   do {
> - if (INTEL_GEN(dev_priv) >= 9)
> + if (burst_read)
> + len = rx_size;
> + else if (INTEL_GEN(dev_priv) >= 9)
>   len = min(rx_size, BXT_GMBUS_BYTE_COUNT_MAX);
>   else
>   len = min(rx_size, GMBUS_BYTE_COUNT_MAX);

If you abstracted the max transfer length in the previous patch, I think
you could condence this into something like:

if (HAS_GMBUS_BURST_READ(dev_priv))
len = rx_size;
else
len = min(rx_size, gmbus_max_xfer_size(dev_priv))

You could throw away the burst_read variable and parameter altogether,
and have gmbus_xfer_read_chunk() decide internally if burst read is to
be used by:

burst_read = len > gmbus_max_xfer_size(dev_priv);

(Potentially with a WARN_ON(burst_read && !HAS_GMBUS_BURST_READ()) if
you want to be paranoid.)

BR,
Jani.

>  
>   ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
> - buf, len, gmbus1_index);
> + buf, len, gmbus1_index, burst_read);
>   if (ret)
>   return ret;

-- 
Jani Nikula, Intel Open Source 

[Intel-gfx] ✓ Fi.CI.BAT: success for Enable NV12 support

[Patchwork]

== Series Details ==

Series: Enable NV12 support
URL   : https://patchwork.freedesktop.org/series/41674/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4052 -> Patchwork_8686 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/41674/revisions/1/mbox/


== Changes ==

  No changes found


== Participating hosts (35 -> 32) ==

  Additional (1): fi-cnl-y3 
  Missing(4): fi-ctg-p8600 fi-ilk-m540 fi-skl-6700hq fi-snb-2520m 


== Build changes ==

* Linux: CI_DRM_4052 -> Patchwork_8686

  CI_DRM_4052: ff6d5cf7b19871af5657774f4e8f5f91f6285e12 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4429: 80e4910581c7310258375a003a5de9a57ed24546 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8686: ff50c03cffbe8d8fbedbd51d5cab2b4ea6e0e2bb @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4429: 93b35926a150e318439d2505901288594b3548f5 @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

ff50c03cffbe drm/i915: Do not do fb src adjustments for NV12
124a184d1872 drm/i915: Enable Display WA 0528
e82aedce2347 drm/i915: Add NV12 support to intel_framebuffer_init
8a5b4eaabb39 drm/i915: Add NV12 as supported format for sprite plane
40fa95f31fce drm/i915: Add NV12 as supported format for primary plane
d24b3eca473a drm/i915: Enable display workaround 827 for all planes, v2.

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8686/issues.html
___
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Re: [Intel-gfx] [RFC 1/2] drm/i915/gmbus: Increase the Bytes per Rd/Wr Op

[Jani Nikula]

On Thu, 12 Apr 2018, Ramalingam C  wrote:
> From BXT onwards Bspec says HW supports Max Bytes per single RD/WR op is
> 511Bytes instead of previous 256Bytes used in SW.

"BXT onwards" and "SKL onwards" are always slightly confusing, because
it's not always clear if one includes the other. Since the code is
written gen 9+, perhaps use that here and in the macro definition too?

>
> This change allows the max bytes per op upto 511Bytes from BXT onwards.
>
> Cc: Jani Nikula 
> Cc: Chris Wilson 
> Signed-off-by: Ramalingam C 
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  1 +
>  drivers/gpu/drm/i915/intel_i2c.c | 10 --
>  2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 475cac07d3e6..4f583da0cee9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3013,6 +3013,7 @@ enum i915_power_well_id {
>  #define   GMBUS_CYCLE_STOP   (4<<25)
>  #define   GMBUS_BYTE_COUNT_SHIFT 16
>  #define   GMBUS_BYTE_COUNT_MAX   256U
> +#define   BXT_GMBUS_BYTE_COUNT_MAX 511U
>  #define   GMBUS_SLAVE_INDEX_SHIFT 8
>  #define   GMBUS_SLAVE_ADDR_SHIFT 1
>  #define   GMBUS_SLAVE_READ   (1<<0)
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c 
> b/drivers/gpu/drm/i915/intel_i2c.c
> index e6875509bcd9..7e92c7934657 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -400,7 +400,10 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, 
> struct i2c_msg *msg,
>   int ret;
>  
>   do {
> - len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
> + if (INTEL_GEN(dev_priv) >= 9)
> + len = min(rx_size, BXT_GMBUS_BYTE_COUNT_MAX);
> + else
> + len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
>  
>   ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
>   buf, len, gmbus1_index);
> @@ -462,7 +465,10 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, 
> struct i2c_msg *msg,
>   int ret;
>  
>   do {
> - len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
> + if (INTEL_GEN(dev_priv) >= 9)
> + len = min(tx_size, BXT_GMBUS_BYTE_COUNT_MAX);
> + else
> + len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
>  
>   ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
>gmbus1_index);

-- 
Jani Nikula, Intel Open Source Technology Center
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable NV12 support

[Patchwork]

== Series Details ==

Series: Enable NV12 support
URL   : https://patchwork.freedesktop.org/series/41674/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
d24b3eca473a drm/i915: Enable display workaround 827 for all planes, v2.
-:58: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#58: FILE: drivers/gpu/drm/i915/intel_display.c:5148:
+   if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
+  IS_CANNONLAKE(dev_priv))

total: 0 errors, 0 warnings, 1 checks, 95 lines checked
40fa95f31fce drm/i915: Add NV12 as supported format for primary plane
8a5b4eaabb39 drm/i915: Add NV12 as supported format for sprite plane
e82aedce2347 drm/i915: Add NV12 support to intel_framebuffer_init
124a184d1872 drm/i915: Enable Display WA 0528
ff50c03cffbe drm/i915: Do not do fb src adjustments for NV12
-:35: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#35: FILE: drivers/gpu/drm/i915/intel_display.c:13009:
+   src->x1 = (((src->x1 >> 16)/4)*4) << 16;
   ^

-:35: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#35: FILE: drivers/gpu/drm/i915/intel_display.c:13009:
+   src->x1 = (((src->x1 >> 16)/4)*4) << 16;
  ^

-:36: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#36: FILE: drivers/gpu/drm/i915/intel_display.c:13010:
+   src->x2 = (((src->x2 >> 16)/4)*4) << 16;
   ^

-:36: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#36: FILE: drivers/gpu/drm/i915/intel_display.c:13010:
+   src->x2 = (((src->x2 >> 16)/4)*4) << 16;
  ^

-:37: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#37: FILE: drivers/gpu/drm/i915/intel_display.c:13011:
+   src->y1 = (((src->y1 >> 16)/4)*4) << 16;
   ^

-:37: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#37: FILE: drivers/gpu/drm/i915/intel_display.c:13011:
+   src->y1 = (((src->y1 >> 16)/4)*4) << 16;
  ^

-:38: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#38: FILE: drivers/gpu/drm/i915/intel_display.c:13012:
+   src->y2 = (((src->y2 >> 16)/4)*4) << 16;
   ^

-:38: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#38: FILE: drivers/gpu/drm/i915/intel_display.c:13012:
+   src->y2 = (((src->y2 >> 16)/4)*4) << 16;
  ^

-:74: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#74: FILE: drivers/gpu/drm/i915/intel_sprite.c:1118:
+   src->x1 = (((src->x1 >> 16)/4)*4) << 16;
   ^

-:74: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#74: FILE: drivers/gpu/drm/i915/intel_sprite.c:1118:
+   src->x1 = (((src->x1 >> 16)/4)*4) << 16;
  ^

-:75: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#75: FILE: drivers/gpu/drm/i915/intel_sprite.c:1119:
+   src->x2 = (((src->x2 >> 16)/4)*4) << 16;
   ^

-:75: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#75: FILE: drivers/gpu/drm/i915/intel_sprite.c:1119:
+   src->x2 = (((src->x2 >> 16)/4)*4) << 16;
  ^

-:76: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#76: FILE: drivers/gpu/drm/i915/intel_sprite.c:1120:
+   src->y1 = (((src->y1 >> 16)/4)*4) << 16;
   ^

-:76: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#76: FILE: drivers/gpu/drm/i915/intel_sprite.c:1120:
+   src->y1 = (((src->y1 >> 16)/4)*4) << 16;
  ^

-:77: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#77: FILE: drivers/gpu/drm/i915/intel_sprite.c:1121:
+   src->y2 = (((src->y2 >> 16)/4)*4) << 16;
   ^

-:77: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#77: FILE: drivers/gpu/drm/i915/intel_sprite.c:1121:
+   src->y2 = (((src->y2 >> 16)/4)*4) << 16;
  ^

total: 0 errors, 0 warnings, 16 checks, 55 lines checked

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[Intel-gfx] Updated drm-intel-testing

[Jani Nikula]

Hi all,

The following changes tagged drm-intel-testing-2018-04-13:

drm-intel-next-2018-04-13:
First drm/i915 feature batch heading for v4.18:

- drm-next backmerge to fix build (Rodrigo)
- GPU documentation improvements (Kevin)
- GuC and HuC refactoring, host/GuC communication, logging, fixes, and more
  (mostly Michal and Michał, also Jackie, Michel and Piotr)
- PSR and PSR2 enabling and fixes (DK, José, Rodrigo and Chris)
- Selftest updates (Chris, Daniele)
- DPLL management refactoring (Lucas)
- DP MST fixes (Lyude and DK)
- Watermark refactoring and changes to support NV12 (Mahesh)
- NV12 prep work (Chandra)
- Icelake Combo PHY enablers (Manasi)
- Perf OA refactoring and ICL enabling (Lionel)
- ICL enabling (Oscar, Paulo, Nabendu, Mika, Kelvin, Michel)
- Workarounds refactoring (Oscar)
- HDCP fixes and improvements (Ramalingam, Radhakrishna)
- Power management fixes (Imre)
- Various display fixes (Maarten, Ville, Vidya, Jani, Gaurav)
- debugfs for FIFO underrun clearing (Maarten)
- Execlist improvements (Chris)
- Reset improvements (Chris)
- Plenty of things here and there I overlooked and/or didn't understand... 
(Everyone)

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] [PATCH igt v9] igt: Add gem_ctx_freq to exercise requesting freq on a ctx

[Chris Wilson]

Exercise some new API that allows applications to request that
individual contexts are executed within a desired frequency range.

v2: Split single/continuous set_freq subtests
v3: Do an up/down ramp for individual freq request, check nothing
changes after each invalid request
v4: Check the frequencies reported by the kernel across the entire
range.
v5: Rewrite sandwich to create a sandwich between multiple concurrent
engines.
v6: Exercise sysfs overrides.
v7: Reset min/max of default context after independent(); don't ask
about failure
v8: Check transition beyond randomly chosen frequencies as well as
up/down ramps.
v9: Check inheritance and sprinkle comments around the place.

With meson.build provided by Arkadiusz Hiler.

Signed-off-by: Chris Wilson 
Cc: Praveen Paneri 
Cc: Sagar A Kamble 
Cc: Antonio Argenziano 
Reviewed-by: Antonio Argenziano  #v5
---
 lib/i915/gem_scheduler.c |  15 +
 lib/i915/gem_scheduler.h |   2 +
 tests/Makefile.am|   1 +
 tests/Makefile.sources   |   1 +
 tests/gem_ctx_freq.c | 953 +++
 tests/meson.build|  21 +-
 6 files changed, 987 insertions(+), 6 deletions(-)
 create mode 100644 tests/gem_ctx_freq.c

diff --git a/lib/i915/gem_scheduler.c b/lib/i915/gem_scheduler.c
index ad156306f..fd0f2e84f 100644
--- a/lib/i915/gem_scheduler.c
+++ b/lib/i915/gem_scheduler.c
@@ -104,6 +104,19 @@ bool gem_scheduler_has_preemption(int fd)
   LOCAL_I915_SCHEDULER_CAP_PREEMPTION;
 }
 
+/**
+ * gem_scheduler_has_frequency_control:
+ * @fd: open i915 drm file descriptor
+ *
+ * Feature test macro to query whether the driver supports controlling the
+ * GPU frequency for individual contexts and requests.
+ */
+bool gem_scheduler_has_frequency_control(int fd)
+{
+   return gem_scheduler_capability(fd) &
+  LOCAL_I915_SCHEDULER_CAP_FREQUENCY;
+}
+
 /**
  * gem_scheduler_print_capability:
  * @fd: open i915 drm file descriptor
@@ -122,4 +135,6 @@ void gem_scheduler_print_capability(int fd)
igt_info(" - With priority sorting\n");
if (caps & LOCAL_I915_SCHEDULER_CAP_PREEMPTION)
igt_info(" - With preemption enabled\n");
+   if (caps & LOCAL_I915_SCHEDULER_CAP_FREQUENCY)
+   igt_info(" - With frequency control\n");
 }
diff --git a/lib/i915/gem_scheduler.h b/lib/i915/gem_scheduler.h
index 9fcb02665..6cc8444f6 100644
--- a/lib/i915/gem_scheduler.h
+++ b/lib/i915/gem_scheduler.h
@@ -27,11 +27,13 @@
 #define LOCAL_I915_SCHEDULER_CAP_ENABLED   (1 << 0)
 #define LOCAL_I915_SCHEDULER_CAP_PRIORITY  (1 << 1)
 #define LOCAL_I915_SCHEDULER_CAP_PREEMPTION(1 << 2)
+#define LOCAL_I915_SCHEDULER_CAP_FREQUENCY (1 << 3)
 
 unsigned gem_scheduler_capability(int fd);
 bool gem_scheduler_enabled(int fd);
 bool gem_scheduler_has_ctx_priority(int fd);
 bool gem_scheduler_has_preemption(int fd);
+bool gem_scheduler_has_frequency_control(int fd);
 void gem_scheduler_print_capability(int fd);
 
 #endif /* GEM_SCHEDULER_H */
diff --git a/tests/Makefile.am b/tests/Makefile.am
index f41ad5096..408c8b423 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -104,6 +104,7 @@ drm_import_export_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
 drm_import_export_LDADD = $(LDADD) -lpthread
 gem_close_race_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
 gem_close_race_LDADD = $(LDADD) -lpthread
+gem_ctx_freq_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la
 gem_ctx_thrash_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
 gem_ctx_thrash_LDADD = $(LDADD) -lpthread
 gem_exec_parallel_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 791e4f83d..5ce345963 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -58,6 +58,7 @@ TESTS_progs = \
gem_ctx_bad_exec \
gem_ctx_create \
gem_ctx_exec \
+   gem_ctx_freq \
gem_ctx_isolation \
gem_ctx_param \
gem_ctx_switch \
diff --git a/tests/gem_ctx_freq.c b/tests/gem_ctx_freq.c
new file mode 100644
index 0..236c2a667
--- /dev/null
+++ b/tests/gem_ctx_freq.c
@@ -0,0 +1,953 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 

Re: [Intel-gfx] [PATCH v4] drm/i915/guc: Remove GUC_CTL_DEVICE_INFO parameter

[Chris Wilson]

Quoting Piotr Piórkowski (2018-04-13 09:52:45)
> It looks that GuC does not actively use GUC_CTL_DEVICE_INFO parameter
> where we are passing GT type and Core family values.
> Let's stop/remove setup of this parameter and remove related
> definitions.
> 
> v2: (this time without squashed HAX)
>   - New title and description
>   - Remove also GUC_CORE_FAMILY_* definitions (Michel)
> v3:
>   - The removed define GUC_CTL_DEVICE_INFO has been restored (Michel)
>   - Updated description (Sagar)
> v4: rebase
> 
> Signed-off-by: Piotr Piórkowski 
> Cc: Sagar Arun Kamble 
> Cc: Michał Winiarski 
> Cc: John A Spotswood 
> Cc: Michal Wajdeczko 
> Cc: Chris Wilson 
> Cc: Michel Thierry 
> Acked-by: Michel Thierry 
> Reviewed-by: Sagar Arun Kamble 

And pushed, thanks for the patch and review.
-Chris
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[Intel-gfx] [PATCH v2 3/6] drm/i915: Add NV12 as supported format for sprite plane

[Vidya Srinivas]

From: Chandra Konduru 

This patch adds NV12 to list of supported formats for sprite plane.

v2: Rebased (me)

v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_formats
- Added the 10bpc RGB formats

v4: Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Removed 10bit RGB formats added previously with NV12 series

v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Previous version has 10bit RGB format removed from VLV formats
by mistake. Fixing that in this version.
Removed 10bit RGB formats added previously with NV12 series
for SKL.

v6: Addressed review comments by Ville
Restricting the NV12 to BXT and PIPE A and B

v7: Rebased (me)

v8: Rebased (me)
Restricting NV12 changes to BXT and KBL
Restricting NV12 changes for plane 0 (overlay)

v9: Rebased (me)

v10: Addressed review comments from Maarten.
Adding NV12 to skl_plane_formats itself.

v11: Addressed review comments from Shashank Sharma

v12: Addressed review comments from Shashank Sharma
Made the condition in intel_sprite_plane_create
simple and easy to read as suggested.

v13: Adding reviewed by tag from Shashank Sharma
Addressed review comments from Juha-Pekka Heikkila
"NV12 not to be supported by SKL"

v14: Addressed review comments from Ville
Added skl_planar_formats to include NV12
and a check skl_plane_has_planar in sprite create
Added NV12 format to skl_mod_supported. These were
review comments from Kristian Høgsberg 

v15: Added reviewed by from Juha-Pekka Heikkila

v16: Rebased the series

v17: Added all tiling under mod supported for NV12
Credits to Megha Aggarwal

Credits-to: Megha Aggarwal 
Credits-to: Kristian Høgsberg 
Tested-by: Clinton Taylor 
Reviewed-by: Juha-Pekka Heikkila 
Reviewed-by: Shashank Sharma 
Reviewed-by: Clinton Taylor 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_sprite.c | 29 +++--
 1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index aa1dfaa..8b7947d 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1253,6 +1253,19 @@ static uint32_t skl_plane_formats[] = {
DRM_FORMAT_VYUY,
 };
 
+static uint32_t skl_planar_formats[] = {
+   DRM_FORMAT_RGB565,
+   DRM_FORMAT_ABGR,
+   DRM_FORMAT_ARGB,
+   DRM_FORMAT_XBGR,
+   DRM_FORMAT_XRGB,
+   DRM_FORMAT_YUYV,
+   DRM_FORMAT_YVYU,
+   DRM_FORMAT_UYVY,
+   DRM_FORMAT_VYUY,
+   DRM_FORMAT_NV12,
+};
+
 static const uint64_t skl_plane_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
@@ -1350,6 +1363,12 @@ static bool skl_mod_supported(uint32_t format, uint64_t 
modifier)
if (modifier == I915_FORMAT_MOD_Yf_TILED)
return true;
/* fall through */
+   case DRM_FORMAT_NV12:
+   if (modifier == DRM_FORMAT_MOD_LINEAR ||
+   modifier == I915_FORMAT_MOD_X_TILED ||
+   modifier == I915_FORMAT_MOD_Y_TILED ||
+   modifier == I915_FORMAT_MOD_Yf_TILED)
+   return true;
case DRM_FORMAT_C8:
if (modifier == DRM_FORMAT_MOD_LINEAR ||
modifier == I915_FORMAT_MOD_X_TILED ||
@@ -1446,8 +1465,14 @@ intel_sprite_plane_create(struct drm_i915_private 
*dev_priv,
intel_plane->disable_plane = skl_disable_plane;
intel_plane->get_hw_state = skl_plane_get_hw_state;
 
-   plane_formats = skl_plane_formats;
-   num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+   if (skl_plane_has_planar(dev_priv, pipe,
+PLANE_SPRITE0 + plane)) {
+   plane_formats = skl_planar_formats;
+   num_plane_formats = ARRAY_SIZE(skl_planar_formats);
+   } else {
+   plane_formats = skl_plane_formats;
+   num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+   }
 
if 

[Intel-gfx] [PATCH v2 5/6] drm/i915: Enable Display WA 0528

[Vidya Srinivas]

Possible hang with NV12 plane surface formats.
WA: When the plane source pixel format is NV12,
the CHICKEN_PIPESL_* register bit 22 must be set to 1
and the render decompression must not be enabled
on any of the planes in that pipe.

v2: removed unnecessary POSTING_READ

Credits-to: Maarten Lankhorst 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_display.c | 20 ++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index f64bef9..bc83f10 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -505,6 +505,18 @@ static const struct intel_limit intel_limits_bxt = {
 };
 
 static void
+skl_wa_528(struct drm_i915_private *dev_priv, int pipe, bool enable)
+{
+   if (IS_SKYLAKE(dev_priv))
+   return;
+
+   if (enable)
+   I915_WRITE(CHICKEN_PIPESL_1(pipe), HSW_FBCQ_DIS);
+   else
+   I915_WRITE(CHICKEN_PIPESL_1(pipe), 0);
+}
+
+static void
 skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
 {
if (IS_SKYLAKE(dev_priv))
@@ -5202,8 +5214,10 @@ static void intel_post_plane_update(struct 
intel_crtc_state *old_crtc_state)
 
/* Display WA 827 */
if (needs_nv12_wa(dev_priv, old_crtc_state) &&
-   !needs_nv12_wa(dev_priv, pipe_config))
+   !needs_nv12_wa(dev_priv, pipe_config)) {
skl_wa_clkgate(dev_priv, crtc->pipe, false);
+   skl_wa_528(dev_priv, crtc->pipe, false);
+   }
 }
 
 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
@@ -5240,8 +5254,10 @@ static void intel_pre_plane_update(struct 
intel_crtc_state *old_crtc_state,
 
/* Display WA 827 */
if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
-   needs_nv12_wa(dev_priv, pipe_config))
+   needs_nv12_wa(dev_priv, pipe_config)) {
skl_wa_clkgate(dev_priv, crtc->pipe, true);
+   skl_wa_528(dev_priv, crtc->pipe, true);
+   }
 
/*
 * Vblank time updates from the shadow to live plane control register
-- 
2.7.4

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[Intel-gfx] [PATCH v2 0/6] Enable NV12 support

[Vidya Srinivas]

Enabling NV12 support:
- Framebuffer creation
- Primary and Sprite plane support
Patch series depend on Enable display workaround 827 patch
mentioned below submitted by Maarten

Chandra Konduru (3):
  drm/i915: Add NV12 as supported format for primary plane
  drm/i915: Add NV12 as supported format for sprite plane
  drm/i915: Add NV12 support to intel_framebuffer_init

Maarten Lankhorst (1):
  drm/i915: Enable display workaround 827 for all planes, v2.

Vidya Srinivas (2):
  drm/i915: Enable Display WA 0528
  drm/i915: Do not do fb src adjustments for NV12

 drivers/gpu/drm/i915/intel_atomic_plane.c |   7 +-
 drivers/gpu/drm/i915/intel_display.c  | 136 ++
 drivers/gpu/drm/i915/intel_drv.h  |   3 +
 drivers/gpu/drm/i915/intel_sprite.c   |  44 +-
 4 files changed, 169 insertions(+), 21 deletions(-)

-- 
2.7.4

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[Intel-gfx] [PATCH v2 6/6] drm/i915: Do not do fb src adjustments for NV12

[Vidya Srinivas]

We skip src trunction/adjustments for
NV12 case and handle the sizes directly.
Without this, pipe fifo underruns are seen on APL/KBL.

v2: For NV12, making the src coordinates multiplier of 4

Credits-to: Maarten Lankhorst 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_display.c | 11 +++
 drivers/gpu/drm/i915/intel_sprite.c  | 15 +++
 2 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index bc83f10..f64708f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12978,6 +12978,10 @@ intel_check_primary_plane(struct intel_plane *plane,
bool can_position = false;
int ret;
uint32_t pixel_format = 0;
+   struct drm_plane_state *plane_state = >base;
+   struct drm_rect *src = _state->src;
+
+   *src = drm_plane_state_src(plane_state);
 
if (INTEL_GEN(dev_priv) >= 9) {
/* use scaler when colorkey is not required */
@@ -13001,6 +13005,13 @@ intel_check_primary_plane(struct intel_plane *plane,
if (!state->base.fb)
return 0;
 
+   if (pixel_format == DRM_FORMAT_NV12) {
+   src->x1 = (((src->x1 >> 16)/4)*4) << 16;
+   src->x2 = (((src->x2 >> 16)/4)*4) << 16;
+   src->y1 = (((src->y1 >> 16)/4)*4) << 16;
+   src->y2 = (((src->y2 >> 16)/4)*4) << 16;
+   }
+
if (INTEL_GEN(dev_priv) >= 9) {
ret = skl_check_plane_surface(crtc_state, state);
if (ret)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 8b7947d..c1dd85e 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1035,11 +1035,20 @@ intel_check_sprite_plane(struct intel_plane *plane,
return vscale;
}
 
+   if (fb->format->format == DRM_FORMAT_NV12) {
+   if (src->x2 >> 16 == 16)
+   src->x2 = 16 << 16;
+   if (src->y2 >> 16 == 16)
+   src->y2 = 16 << 16;
+   goto nv12_min_no_clip;
+   }
+
/* Make the source viewport size an exact multiple of the 
scaling factors. */
drm_rect_adjust_size(src,
 drm_rect_width(dst) * hscale - 
drm_rect_width(src),
 drm_rect_height(dst) * vscale - 
drm_rect_height(src));
 
+nv12_min_no_clip:
drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
state->base.rotation);
 
@@ -1105,6 +1114,12 @@ intel_check_sprite_plane(struct intel_plane *plane,
src->x2 = (src_x + src_w) << 16;
src->y1 = src_y << 16;
src->y2 = (src_y + src_h) << 16;
+   if (fb->format->format == DRM_FORMAT_NV12) {
+   src->x1 = (((src->x1 >> 16)/4)*4) << 16;
+   src->x2 = (((src->x2 >> 16)/4)*4) << 16;
+   src->y1 = (((src->y1 >> 16)/4)*4) << 16;
+   src->y2 = (((src->y2 >> 16)/4)*4) << 16;
+   }
}
 
dst->x1 = crtc_x;
-- 
2.7.4

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[Intel-gfx] [PATCH v2 4/6] drm/i915: Add NV12 support to intel_framebuffer_init

[Vidya Srinivas]

From: Chandra Konduru 

This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.

v2:
-Fix an issue in checks added (Chandra Konduru)

v3: rebased (me)

v4: Review comments by Ville addressed
Added platform check for NV12 in intel_framebuffer_init
Removed offset checks for NV12 case

v5: Addressed review comments by Clinton A Taylor
This NV12 support only correctly works on SKL.
Plane color space conversion is different on GLK and later platforms
causing the colors to display incorrectly.
Ville's plane color space property patch series
in review will fix this issue.
- Restricted the NV12 case in intel_framebuffer_init to
SKL and BXT only.

v6: Rebased (me)

v7: Addressed review comments by Ville
Restricting the NV12 to BXT for now.

v8: Rebased (me)
Restricting the NV12 changes to BXT and KBL for now.

v9: Rebased (me)

v10: NV12 supported by all GEN >= 9.
Making this change in intel_framebuffer_init. This is
part of addressing Maarten's review comments.
Comment under v8 no longer applicable

v11: Addressed review comments from Shashank Sharma

v12: Adding Reviewed By from Shashank Sharma

v13: Addressed review comments from Juha-Pekka Heikkila
"NV12 not to be supported by SKL"

v14: Addressed review comments from Maarten.
Add checks for fb width height for NV12 and fail the fb
creation if check fails. Added reviewed by from
Juha-Pekka Heikkila

v15: Rebased the series

v16: Setting the minimum value during fb creating to 16
as per Bspec for NV12. Earlier minimum was expected
to be > 16. Now changed it to >=16.

v17: Adding restriction to framebuffer_init - the fb
width and height should be a multiplier of 4

Credits-to: Maarten Lankhorst 
Tested-by: Clinton Taylor 
Reviewed-by: Shashank Sharma 
Reviewed-by: Clinton Taylor 
Reviewed-by: Juha-Pekka Heikkila 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_display.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 1a0fae9..f64bef9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14261,6 +14261,14 @@ static int intel_framebuffer_init(struct 
intel_framebuffer *intel_fb,
goto err;
}
break;
+   case DRM_FORMAT_NV12:
+   if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv)) {
+   DRM_DEBUG_KMS("unsupported pixel format: %s\n",
+ 
drm_get_format_name(mode_cmd->pixel_format,
+ _name));
+   goto err;
+   }
+   break;
default:
DRM_DEBUG_KMS("unsupported pixel format: %s\n",
  drm_get_format_name(mode_cmd->pixel_format, 
_name));
@@ -14273,6 +14281,14 @@ static int intel_framebuffer_init(struct 
intel_framebuffer *intel_fb,
 
drm_helper_mode_fill_fb_struct(_priv->drm, fb, mode_cmd);
 
+   if (fb->format->format == DRM_FORMAT_NV12 &&
+   (fb->width < SKL_MIN_YUV_420_SRC_W ||
+fb->height < SKL_MIN_YUV_420_SRC_H ||
+(fb->width % 4) != 0 || (fb->height % 4) != 0)) {
+   DRM_DEBUG_KMS("src dimensions not correct for NV12\n");
+   return -EINVAL;
+   }
+
for (i = 0; i < fb->format->num_planes; i++) {
u32 stride_alignment;
 
-- 
2.7.4

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[Intel-gfx] [PATCH v2 2/6] drm/i915: Add NV12 as supported format for primary plane

[Vidya Srinivas]

From: Chandra Konduru 

This patch adds NV12 to list of supported formats for
primary plane

v2: Rebased (Chandra Konduru)

v3: Rebased (me)

v4: Review comments by Ville addressed
Removed the skl_primary_formats_with_nv12 and
added NV12 case in existing skl_primary_formats

v5: Rebased (me)

v6: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v7: Review comments by Ville addressed
Restricting the NV12 for BXT and on PIPE A and B
Rebased (me)

v8: Rebased (me)
Modified restricting the NV12 support for both BXT and KBL.

v9: Rebased (me)

v10: Addressed review comments from Maarten.
Adding NV12 inside skl_primary_formats itself.

v11: Adding Reviewed By tag from Shashank Sharma

v12: Addressed review comments from Juha-Pekka Heikkila
"NV12 not to be supported by SKL"

v13: Addressed review comments from Ville
Added skl_pri_planar_formats to include NV12
and skl_plane_has_planar function to check for
NV12 support on plane. Added NV12 format to
skl_mod_supported. These were review comments
from Kristian Høgsberg 

v14: Added reviewed by from Juha-Pekka Heikkila

v15: Rebased the series

v16: Added all tiling support under mod supported
for NV12. Credits to Megha Aggarwal

Credits-to: Megha Aggarwal megha.aggar...@intel.com
Tested-by: Clinton Taylor 
Reviewed-by: Juha-Pekka Heikkila 
Reviewed-by: Clinton Taylor 
Reviewed-by: Shashank Sharma 
Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/intel_display.c | 55 ++--
 drivers/gpu/drm/i915/intel_drv.h |  2 ++
 2 files changed, 55 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 22c8a7d..1a0fae9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -88,6 +88,22 @@ static const uint32_t skl_primary_formats[] = {
DRM_FORMAT_VYUY,
 };
 
+static const uint32_t skl_pri_planar_formats[] = {
+   DRM_FORMAT_C8,
+   DRM_FORMAT_RGB565,
+   DRM_FORMAT_XRGB,
+   DRM_FORMAT_XBGR,
+   DRM_FORMAT_ARGB,
+   DRM_FORMAT_ABGR,
+   DRM_FORMAT_XRGB2101010,
+   DRM_FORMAT_XBGR2101010,
+   DRM_FORMAT_YUYV,
+   DRM_FORMAT_YVYU,
+   DRM_FORMAT_UYVY,
+   DRM_FORMAT_VYUY,
+   DRM_FORMAT_NV12,
+};
+
 static const uint64_t skl_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
@@ -13124,6 +13140,12 @@ static bool skl_mod_supported(uint32_t format, 
uint64_t modifier)
if (modifier == I915_FORMAT_MOD_Yf_TILED)
return true;
/* fall through */
+   case DRM_FORMAT_NV12:
+   if (modifier == DRM_FORMAT_MOD_LINEAR ||
+   modifier == I915_FORMAT_MOD_X_TILED ||
+   modifier == I915_FORMAT_MOD_Y_TILED ||
+   modifier == I915_FORMAT_MOD_Yf_TILED)
+   return true;
case DRM_FORMAT_C8:
if (modifier == DRM_FORMAT_MOD_LINEAR ||
modifier == I915_FORMAT_MOD_X_TILED ||
@@ -13328,6 +13350,30 @@ static bool skl_plane_has_fbc(struct drm_i915_private 
*dev_priv,
return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
 }
 
+bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
+ enum pipe pipe, enum plane_id plane_id)
+{
+   if (plane_id == PLANE_PRIMARY) {
+   if (IS_SKYLAKE(dev_priv))
+   return false;
+   else if ((INTEL_GEN(dev_priv) == 9 && pipe == PIPE_C) &&
+!IS_GEMINILAKE(dev_priv))
+   return false;
+   } else if (plane_id >= PLANE_SPRITE0) {
+   if (plane_id == PLANE_CURSOR)
+   return false;
+   if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) == 10) {
+   if (plane_id != PLANE_SPRITE0)
+   return false;
+   } else {
+   if (plane_id != PLANE_SPRITE0 || pipe == PIPE_C ||
+   IS_SKYLAKE(dev_priv))
+   return false;
+   }
+   }
+   return true;
+}
+
 static struct intel_plane *
 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 {
@@ -13388,8 +13434,13 @@ intel_primary_plane_create(struct drm_i915_private 
*dev_priv, enum pipe pipe)
primary->check_plane = intel_check_primary_plane;
 
if (INTEL_GEN(dev_priv) >= 9) {
-   intel_primary_formats = skl_primary_formats;
-   num_formats = 

[Intel-gfx] [PATCH v2 1/6] drm/i915: Enable display workaround 827 for all planes, v2.

[Vidya Srinivas]

From: Maarten Lankhorst 

The workaround was applied only to the primary plane, but is required
on all planes. Iterate over all planes in the crtc atomic check to see
if the workaround is enabled, and only perform the actual toggling in
the pre/post plane update functions.

Changes since v1:
- Track active NV12 planes in a nv12_planes bitmask. (Ville)

Signed-off-by: Maarten Lankhorst 
Cc: Ville Syrjälä 
Reviewed-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_atomic_plane.c |  7 +-
 drivers/gpu/drm/i915/intel_display.c  | 40 ++-
 drivers/gpu/drm/i915/intel_drv.h  |  1 +
 3 files changed, 30 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c 
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 7481ce8..6d06878 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -183,11 +183,16 @@ int intel_plane_atomic_check_with_state(const struct 
intel_crtc_state *old_crtc_
}
 
/* FIXME pre-g4x don't work like this */
-   if (intel_state->base.visible)
+   if (state->visible)
crtc_state->active_planes |= BIT(intel_plane->id);
else
crtc_state->active_planes &= ~BIT(intel_plane->id);
 
+   if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
+   crtc_state->nv12_planes |= BIT(intel_plane->id);
+   else
+   crtc_state->nv12_planes &= ~BIT(intel_plane->id);
+
return intel_plane_atomic_calc_changes(old_crtc_state,
   _state->base,
   old_plane_state,
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 020900e..22c8a7d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5138,6 +5138,19 @@ static bool hsw_post_update_enable_ips(const struct 
intel_crtc_state *old_crtc_s
return !old_crtc_state->ips_enabled;
 }
 
+static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
+ const struct intel_crtc_state *crtc_state)
+{
+   if (!crtc_state->nv12_planes)
+   return false;
+
+   if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
+  IS_CANNONLAKE(dev_priv))
+   return true;
+
+   return false;
+}
+
 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
 {
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
@@ -5162,7 +5175,6 @@ static void intel_post_plane_update(struct 
intel_crtc_state *old_crtc_state)
if (old_primary_state) {
struct drm_plane_state *new_primary_state =
drm_atomic_get_new_plane_state(old_state, primary);
-   struct drm_framebuffer *fb = new_primary_state->fb;
 
intel_fbc_post_update(crtc);
 
@@ -5170,15 +5182,12 @@ static void intel_post_plane_update(struct 
intel_crtc_state *old_crtc_state)
(needs_modeset(_config->base) ||
 !old_primary_state->visible))
intel_post_enable_primary(>base, pipe_config);
-
-   /* Display WA 827 */
-   if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
-   IS_CANNONLAKE(dev_priv)) {
-   if (fb && fb->format->format == DRM_FORMAT_NV12)
-   skl_wa_clkgate(dev_priv, crtc->pipe, false);
-   }
-
}
+
+   /* Display WA 827 */
+   if (needs_nv12_wa(dev_priv, old_crtc_state) &&
+   !needs_nv12_wa(dev_priv, pipe_config))
+   skl_wa_clkgate(dev_priv, crtc->pipe, false);
 }
 
 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
@@ -5202,14 +5211,6 @@ static void intel_pre_plane_update(struct 
intel_crtc_state *old_crtc_state,
struct intel_plane_state *new_primary_state =
intel_atomic_get_new_plane_state(old_intel_state,
 
to_intel_plane(primary));
-   struct drm_framebuffer *fb = new_primary_state->base.fb;
-
-   /* Display WA 827 */
-   if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
-   IS_CANNONLAKE(dev_priv)) {
-   if (fb && fb->format->format == DRM_FORMAT_NV12)
-   skl_wa_clkgate(dev_priv, crtc->pipe, true);
-   }
 
intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
/*
@@ -5221,6 +5222,11 @@ static void intel_pre_plane_update(struct 
intel_crtc_state *old_crtc_state,
intel_set_cpu_fifo_underrun_reporting(dev_priv, 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Removed unused GuC parameters. (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Removed unused GuC parameters. (rev4)
URL   : https://patchwork.freedesktop.org/series/39154/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4052_full -> Patchwork_8685_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_8685_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8685_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/39154/revisions/4/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_8685_full:

  === IGT changes ===

 Warnings 

igt@gem_mocs_settings@mocs-rc6-render:
  shard-kbl:  SKIP -> PASS

igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu:
  shard-snb:  SKIP -> PASS +2


== Known issues ==

  Here are the changes found in Patchwork_8685_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_rotation_crc@sprite-rotation-180:
  shard-hsw:  PASS -> FAIL (fdo#103925)


 Possible fixes 

igt@kms_flip@2x-plain-flip-fb-recreate:
  shard-hsw:  FAIL (fdo#100368) -> PASS +1

igt@kms_flip@flip-vs-expired-vblank-interruptible:
  shard-hsw:  FAIL (fdo#105189) -> PASS


  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
  fdo#105189 https://bugs.freedesktop.org/show_bug.cgi?id=105189


== Participating hosts (6 -> 4) ==

  Missing(2): shard-glk shard-glkb 


== Build changes ==

* Linux: CI_DRM_4052 -> Patchwork_8685

  CI_DRM_4052: ff6d5cf7b19871af5657774f4e8f5f91f6285e12 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4429: 80e4910581c7310258375a003a5de9a57ed24546 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8685: 3084d8f9b609dc6fa9808a730db5d3d639274378 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4429: 93b35926a150e318439d2505901288594b3548f5 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8685/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Removed unused GuC parameters. (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Removed unused GuC parameters. (rev4)
URL   : https://patchwork.freedesktop.org/series/39154/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4052 -> Patchwork_8685 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/39154/revisions/4/mbox/


== Changes ==

  No changes found


== Participating hosts (35 -> 32) ==

  Missing(3): fi-ctg-p8600 fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4052 -> Patchwork_8685

  CI_DRM_4052: ff6d5cf7b19871af5657774f4e8f5f91f6285e12 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4429: 80e4910581c7310258375a003a5de9a57ed24546 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8685: 3084d8f9b609dc6fa9808a730db5d3d639274378 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4429: 93b35926a150e318439d2505901288594b3548f5 @ 
git://anongit.freedesktop.org/piglit


== Linux commits ==

3084d8f9b609 drm/i915/guc: Remove GUC_CTL_DEVICE_INFO parameter

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8685/issues.html
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Re: [Intel-gfx] [RFC v2 2/2] drm/i915/gmbus: Enable burst read

[Ramalingam C]

On Thursday 12 April 2018 09:31 PM, Ramalingam C wrote:

Support for Burst read in HW is added for HDCP2.2 compliance
requirement.

This patch enables the burst read for all the gmbus read of more than
511Bytes, on capable platforms.

v2:
   Extra line is removed.

Signed-off-by: Ramalingam C 
---
  drivers/gpu/drm/i915/i915_reg.h  |  1 +
  drivers/gpu/drm/i915/intel_i2c.c | 38 ++
  2 files changed, 35 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4f583da0cee9..0ef162ee9ce0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2984,6 +2984,7 @@ enum i915_power_well_id {
  #define   GMBUS_RATE_400KHZ   (2<<8) /* reserved on Pineview */
  #define   GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
  #define   GMBUS_HOLD_EXT  (1<<7) /* 300ns hold time, rsvd on Pineview */
+#define   GMBUS_BYTE_CNT_OVERRIDE (1<<6)
  #define   GMBUS_PIN_DISABLED  0
  #define   GMBUS_PIN_SSC   1
  #define   GMBUS_PIN_VGADDC2
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 7e92c7934657..2ee9cf2effcd 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -364,12 +364,24 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
  static int
  gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
  unsigned short addr, u8 *buf, unsigned int len,
- u32 gmbus1_index)
+ u32 gmbus1_index, bool burst_read)
  {
+   unsigned int bytes_af_override, size;
+
+   if (burst_read) {
+   bytes_af_override = len - (((len / 256) - 1) * 256);
Just realized that this could be simplified as (len % 256) + 256; Will 
update the next version.


--Ram

+   size = bytes_af_override;
+
+   I915_WRITE_FW(GMBUS0, (I915_READ_FW(GMBUS0) |
+ GMBUS_BYTE_CNT_OVERRIDE));
+   } else {
+   size = len;
+   }
+
I915_WRITE_FW(GMBUS1,
  gmbus1_index |
  GMBUS_CYCLE_WAIT |
- (len << GMBUS_BYTE_COUNT_SHIFT) |
+ (size << GMBUS_BYTE_COUNT_SHIFT) |
  (addr << GMBUS_SLAVE_ADDR_SHIFT) |
  GMBUS_SLAVE_READ | GMBUS_SW_RDY);
while (len) {
@@ -385,11 +397,23 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
*buf++ = val & 0xff;
val >>= 8;
} while (--len && ++loop < 4);
+
+   if (burst_read && len == (bytes_af_override - 4))
+   I915_WRITE_FW(GMBUS0, (I915_READ_FW(GMBUS0) &
+ ~GMBUS_BYTE_CNT_OVERRIDE));
}
  
  	return 0;

  }
  
+static bool gmbus_burst_read_supported(struct drm_i915_private *dev_priv)

+{
+   if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) ||
+   IS_KABYLAKE(dev_priv))
+   return true;
+   return false;
+}
+
  static int
  gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
u32 gmbus1_index)
@@ -398,15 +422,21 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct 
i2c_msg *msg,
unsigned int rx_size = msg->len;
unsigned int len;
int ret;
+   bool burst_read = false;
+
+   if (rx_size > BXT_GMBUS_BYTE_COUNT_MAX)
+   burst_read = gmbus_burst_read_supported(dev_priv);
  
  	do {

-   if (INTEL_GEN(dev_priv) >= 9)
+   if (burst_read)
+   len = rx_size;
+   else if (INTEL_GEN(dev_priv) >= 9)
len = min(rx_size, BXT_GMBUS_BYTE_COUNT_MAX);
else
len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
  
  		ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,

-   buf, len, gmbus1_index);
+   buf, len, gmbus1_index, burst_read);
if (ret)
return ret;
  


___
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[Intel-gfx] [PATCH i-g-t] [RFC] CONTRIBUTING: commit rights docs

[Daniel Vetter]

This tries to align with the X.org communities's long-standing
tradition of trying to be an inclusive community and handing out
commit rights fairly freely.

We also tend to not revoke commit rights for people no longer
regularly active in a given project, as long as they're still part of
the larger community.

Finally make sure that commit rights, like anything happening on fd.o
infrastructre, is subject to the fd.o's Code of Conduct.

v2: Point at MAINTAINERS for contact info (Daniel S.)

v3:
- Make it clear that commit rights are voluntary and that committers
  need to acknowledge positively when they're nominated by someone
  else (Keith).
- Encourage committers to drop their commit rights when they're no
  longer active, and make it clear they'll get readded (Keith).
- Add a line that maintainers and committers should actively nominate
  new committers (me).

v4: Typo (Petri).

v5: Typo (Sean).

v6: Wording clarifications and spelling (Jani).

v7: Require an explicit commitment to the documented merge criteria
and rules, instead of just the implied one through the Code of Conduct
threat (Jani).

Acked-by: Alex Deucher 
Acked-by: Arkadiusz Hiler 
Acked-by: Daniel Stone 
Acked-by: Eric Anholt 
Acked-by: Gustavo Padovan 
Acked-by: Petri Latvala 
Cc: Alex Deucher 
Cc: Arkadiusz Hiler 
Cc: Ben Widawsky 
Cc: Daniel Stone 
Cc: Dave Airlie 
Cc: Eric Anholt 
Cc: Gustavo Padovan 
Cc: Jani Nikula 
Cc: Joonas Lahtinen 
Cc: Keith Packard 
Cc: Kenneth Graunke 
Cc: Kristian H. Kristensen 
Cc: Maarten Lankhorst 
Cc: Petri Latvala 
Cc: Rodrigo Vivi 
Cc: Sean Paul 
Reviewed-by: Keith Packard 
Signed-off-by: Daniel Vetter 
---
If you wonder about the wide distribution list for an igt patch: I'd
like to start a discussions about x.org community norms around commit
rights at large, at least for all the shared repos. I plan to propose
the same text for drm-misc and libdrm too, and hopefully others like
mesa/xserver/wayland would follow.

fd.o admins also plan to discuss this (and a pile of other topics and
hosting and code of conduct) with all projects, ideally this here
would end up as the starting point for establishing some community
norms.
-Daniel
---
 CONTRIBUTING | 48 
 1 file changed, 48 insertions(+)

diff --git a/CONTRIBUTING b/CONTRIBUTING
index 0180641be3aa..8a118134275c 100644
--- a/CONTRIBUTING
+++ b/CONTRIBUTING
@@ -51,4 +51,52 @@ A short list of contribution guidelines:
 - Changes to the testcases are automatically tested. Take the results into
   account before merging.
 
+Commit rights
+-
+
+Commit rights will be granted to anyone who requests them and fulfills the
+below criteria:
+
+- Submitted a few (5-10 as a rule of thumb) non-trivial (not just simple
+  spelling fixes and whitespace adjustment) patches that have been merged
+  already.
+
+- Are actively participating on discussions about their work (on the mailing
+  list or IRC). This should not be interpreted as a requirement to review other
+  peoples patches but just make sure that patch submission isn't one-way
+  communication. Cross-review is still highly encouraged.
+
+- Will be regularly contributing further patches. This includes regular
+  contributors to other parts of the open source graphics stack who only
+  do the oddball rare patch within igt itself.
+
+- Agrees to use their commit rights in accordance with the documented merge
+  criteria, tools, and processes.
+
+Apply for an account (and any other account change requests) through
+
+https://www.freedesktop.org/wiki/AccountRequests/
+
+and please ping the maintainers if your request is stuck.
+
+Committers are encouraged to request their commit rights get removed when they
+no longer contribute to the project. Commit rights will be reinstated when they
+come back to the project.
+
+Maintainers and committers should encourage contributors to request commit
+rights, especially junior contributors tend to underestimate their skills.
+
+Code of Conduct
+---
+
+Please be aware the fd.o Code of Conduct also applies to igt:
+
+https://www.freedesktop.org/wiki/CodeOfConduct/
+
+See the MAINTAINERS file for contact details of the igt maintainers.
+
+Abuse of commit rights, like engaging in commit fights or willfully pushing
+patches that violate the documented merge criteria, will also be handled 
through
+the Code of Conduct enforcement process.
+
 Happy hacking!
--