[Intel-gfx] [PATCH igt] igt/gem_ppgtt: Flush the driver to idle before counting leaks

I have a cunning plan to make the vma open/close lazy to cache frequent reallocations (as buffers are passed between applications, e.g. DRI). However, this will mean that we will not be immediately closing vma and so need to tell the kernel to process the idle handlers before checking for leaks.

Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/gmbus: Increase the Bytes per Rd/Wr Op

On Wednesday 18 April 2018 08:47 PM, Ville Syrjälä wrote: On Wed, Apr 18, 2018 at 09:20:23AM +0300, Jani Nikula wrote: On Wed, 18 Apr 2018, Ramalingam C wrote: On Tuesday 17 April 2018 11:39 PM, Ville Syrjälä wrote: On Tue, Apr 17, 2018 at 02:25:32PM +0530,

Re: [Intel-gfx] [PATCH v4 6/6] drm/i915: Add skl_check_nv12_surface for NV12

> -Original Message- > From: Kahola, Mika > Sent: Wednesday, April 18, 2018 5:39 PM > To: Srinivas, Vidya ; intel- > g...@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH v4 6/6] drm/i915: Add > skl_check_nv12_surface for NV12 > > On Wed, 2018-04-18 at

Re: [Intel-gfx] [PATCH v4 6/6] drm/i915: Add skl_check_nv12_surface for NV12

> -Original Message- > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > Sent: Thursday, April 19, 2018 12:06 AM > To: Maarten Lankhorst > Cc: Srinivas, Vidya ; intel- > g...@lists.freedesktop.org > Subject:

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/fbdev: Enable late fbdev initial configuration (rev4)

== Series Details == Series: drm/i915/fbdev: Enable late fbdev initial configuration (rev4) URL : https://patchwork.freedesktop.org/series/41851/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4067_full -> Patchwork_8744_full = == Summary - WARNING == Minor unknown

Re: [Intel-gfx] [PATCH] drm/i915: Refine the has_audio assignment

>-Original Message- >From: Jani Nikula [mailto:jani.nik...@linux.intel.com] >Sent: Wednesday, April 18, 2018 8:44 PM >To: Chris Wilson ; Shi, Yang A >; >intel-gfx@lists.freedesktop.org >Cc: Shi, Yang A >Subject: Re:

Re: [Intel-gfx] [PATCH v3] drm/i915: set minimum CD clock to twice the BCLK.

On 4/18/2018 8:41 AM, Ville Syrjälä wrote: On Wed, Apr 18, 2018 at 01:49:23PM +0300, Jani Nikula wrote: On Tue, 17 Apr 2018, "Kumar, Abhay" wrote: On 4/17/2018 12:06 PM, Abhay Kumar wrote: In glk when device boots with only 1366x768 panel, HDA codec doesn't comeup.

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/9] drm/i915/psr: Move specific HSW+ WARN_ON to HSW+ function

== Series Details == Series: series starting with [v2,1/9] drm/i915/psr: Move specific HSW+ WARN_ON to HSW+ function URL : https://patchwork.freedesktop.org/series/41923/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4066_full -> Patchwork_8743_full = == Summary - FAILURE

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/fbdev: Enable late fbdev initial configuration (rev4)

== Series Details == Series: drm/i915/fbdev: Enable late fbdev initial configuration (rev4) URL : https://patchwork.freedesktop.org/series/41851/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4067 -> Patchwork_8744 = == Summary - SUCCESS == No regressions found.

[Intel-gfx] [PATCH v2] drm/i915/fbdev: Enable late fbdev initial configuration

If the initial fbdev configuration(intel_fbdev_initial_config()) runs and there still no sink connected it will cause drm_fb_helper_initial_config() to return 0 as no error happened(but internally the return is -EAGAIN). Because no framebuffer was allocated, when a sink is connected

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/3] drm/i915: Move the priotree struct to its own headers

== Series Details == Series: series starting with [CI,1/3] drm/i915: Move the priotree struct to its own headers URL : https://patchwork.freedesktop.org/series/41911/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4066_full -> Patchwork_8740_full = == Summary - FAILURE ==

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/9] drm/i915/psr: Move specific HSW+ WARN_ON to HSW+ function

== Series Details == Series: series starting with [v2,1/9] drm/i915/psr: Move specific HSW+ WARN_ON to HSW+ function URL : https://patchwork.freedesktop.org/series/41923/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4066 -> Patchwork_8743 = == Summary - SUCCESS == No

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/9] drm/i915/psr: Move specific HSW+ WARN_ON to HSW+ function

== Series Details == Series: series starting with [v2,1/9] drm/i915/psr: Move specific HSW+ WARN_ON to HSW+ function URL : https://patchwork.freedesktop.org/series/41923/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/psr: Move specific HSW+ WARN_ON to HSW+

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/9] drm/i915/psr: Move specific HSW+ WARN_ON to HSW+ function

== Series Details == Series: series starting with [v2,1/9] drm/i915/psr: Move specific HSW+ WARN_ON to HSW+ function URL : https://patchwork.freedesktop.org/series/41923/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9dc8e92b44ac drm/i915/psr: Move specific HSW+ WARN_ON to

[Intel-gfx] [PATCH v2 2/9] drm/i915/psr: Move PSR exit specific code to hardware specific function

To proper execute PSR exit it was using 'if (HAS_DDI(dev_priv))' to differentiate between VLV/CHV and HSW+ hardware, so here moving each hardware handling to his own function. Signed-off-by: José Roberto de Souza Cc: Dhinakaran Pandiyan

[Intel-gfx] [PATCH v2 7/9] drm/i915/dp: Move code to check if aux ch is busy to a function

This reduces the spaghetti that intel_dp_aux_xfer(). Moved doing less changes possible here, improvements to the new function in further patch. Signed-off-by: José Roberto de Souza Cc: Dhinakaran Pandiyan --- New patch in this series.

[Intel-gfx] [PATCH v2 5/9] drm/i915/psr: Handle PSR RFB storage error

Sink will interrupt source when it have any problem saving or reading the remote frame buffer. Signed-off-by: José Roberto de Souza Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi --- Changes from v1: - printing a debug

[Intel-gfx] [PATCH v2 3/9] drm/i915/psr: Remove intel_crtc_state parameter from disable()

It is only used by VLV/CHV and we can get this information from intel_dp for those platforms. Signed-off-by: José Roberto de Souza Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Cc: Lucas De Marchi

[Intel-gfx] [PATCH v2 8/9] drm/i915/dp: Improve intel_dp_aux_is_busy()

- Doing earlier return when not busy - using u32 instead of uint32_t - counting from 3 to 0 as it is is the most common in the driver - using DRM_WARN() instead of WARN() - adding aux port name to the debug message - nuking last_status, it is one static variable to all DP ports also 2 different

[Intel-gfx] [PATCH v2 9/9] drm/i915/dp: Avoid concurrent access when HW is using aux ch

This will avoid some cases of concurrent access to aux ch registers when hardware is using it(HW uses it when PSR, GTC and aux frame is enabled). It is just first step to see if this scenario happens, if so it will be properly handled as described in bspec. Signed-off-by: José Roberto de Souza

[Intel-gfx] [PATCH v2 4/9] drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink

eDP spec states that sink device will do a short pulse in HPD line when there is a PSR/PSR2 error that needs to be handled by source, this is handling the first and most simples error: DP_PSR_SINK_INTERNAL_ERROR. Signed-off-by: José Roberto de Souza Cc: Dhinakaran Pandiyan

[Intel-gfx] [PATCH v2 6/9] drm/i915/psr/bdw+: Enable CRC check in the static frame on the sink side

Sink can be configured to calculate the CRC over the static frame and compare with the CRC calculated and transmited in the VSC SDP by source, if there is a mismatch sink will do a short pulse in HPD and set DP_PSR_LINK_CRC_ERROR on DP_PSR_ERROR_STATUS. Also spec recommends to disable MAX_SLEEP

[Intel-gfx] [PATCH v2 1/9] drm/i915/psr: Move specific HSW+ WARN_ON to HSW+ function

It was reading some random register in VLV and CHV. Signed-off-by: José Roberto de Souza Cc: Dhinakaran Pandiyan Reviewed-by: Rodrigo Vivi --- No changes from v1. drivers/gpu/drm/i915/intel_psr.c | 9 + 1

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v11,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev16)

== Series Details == Series: series starting with [v11,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev16) URL : https://patchwork.freedesktop.org/series/40503/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4066 -> Patchwork_8742 = == Summary -

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v4,1/4] drm/i915: Always do WOPCM partitioning based on real firmware sizes

== Series Details == Series: series starting with [v4,1/4] drm/i915: Always do WOPCM partitioning based on real firmware sizes URL : https://patchwork.freedesktop.org/series/41909/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4066_full -> Patchwork_8739_full = == Summary

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v11,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev16)

== Series Details == Series: series starting with [v11,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev16) URL : https://patchwork.freedesktop.org/series/40503/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0f9b8e8c4c75 drm/i915: Implement

Re: [Intel-gfx] [PATCH v11 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

On 4/18/2018 3:01 PM, Yunwei Zhang wrote: WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO read into Slice/Subslice specific registers, MCR packet control register(0xFDC) needs to be programmed to point to any enabled slice/subslice pair. Otherwise, incorrect value

[Intel-gfx] [PATCH v11 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO read into Slice/Subslice specific registers, MCR packet control register(0xFDC) needs to be programmed to point to any enabled slice/subslice pair. Otherwise, incorrect value will be returned. However, that means each

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/crc: Only report a single overflow when a CRC fd is opened

== Series Details == Series: drm/crc: Only report a single overflow when a CRC fd is opened URL : https://patchwork.freedesktop.org/series/41897/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4066_full -> Patchwork_8737_full = == Summary - WARNING == Minor unknown

[Intel-gfx] ✓ Fi.CI.IGT: success for gpu: drm: i915: Change return type to vm_fault_t (rev2)

== Series Details == Series: gpu: drm: i915: Change return type to vm_fault_t (rev2) URL : https://patchwork.freedesktop.org/series/41893/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4066_full -> Patchwork_8736_full = == Summary - WARNING == Minor unknown changes

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v10,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev15)

== Series Details == Series: series starting with [v10,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev15) URL : https://patchwork.freedesktop.org/series/40503/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4066 -> Patchwork_8741 = == Summary -

Re: [Intel-gfx] [PATCH v10 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

On 4/18/2018 1:23 PM, Yunwei Zhang wrote: L3Bank could be fused off in hardware for debug purpose, and it is possible that subslice is enabled while its corresponding L3Bank pairs are disabled. In such case, if MCR packet control register(0xFDC) is programed to point to a disabled bank pair, a

Re: [Intel-gfx] [PATCH v10 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

On 4/18/2018 1:23 PM, Yunwei Zhang wrote: WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO read into Slice/Subslice specific registers, MCR packet control register(0xFDC) needs to be programmed to point to any enabled slice/subslice pair. Otherwise, incorrect value

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v10,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev15)

== Series Details == Series: series starting with [v10,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev15) URL : https://patchwork.freedesktop.org/series/40503/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4d91b554a00a drm/i915: Implement

[Intel-gfx] [PATCH v10 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

L3Bank could be fused off in hardware for debug purpose, and it is possible that subslice is enabled while its corresponding L3Bank pairs are disabled. In such case, if MCR packet control register(0xFDC) is programed to point to a disabled bank pair, a MMIO read into L3Bank range will return 0

[Intel-gfx] [PATCH v10 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO read into Slice/Subslice specific registers, MCR packet control register(0xFDC) needs to be programmed to point to any enabled slice/subslice pair. Otherwise, incorrect value will be returned. However, that means each

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/audio: set minimum CD clock to twice the BCLK

== Series Details == Series: drm/i915/audio: set minimum CD clock to twice the BCLK URL : https://patchwork.freedesktop.org/series/41888/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4066_full -> Patchwork_8735_full = == Summary - WARNING == Minor unknown changes

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/3] drm/i915: Move the priotree struct to its own headers (rev2)

== Series Details == Series: series starting with [v2,1/3] drm/i915: Move the priotree struct to its own headers (rev2) URL : https://patchwork.freedesktop.org/series/41827/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4066_full -> Patchwork_8734_full = == Summary -

[Intel-gfx] [PULL] drm-misc-fixes

Hi Dave, Here's the first misc-fixes pull. It unfortunately contains a backmerge due to Eric committing Daniel's patch before I had a chance to fast forward. Anyways, it's not too convoluted, so I'll try to win the race this week :-). In general, this is going to become more common as the number

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915: Move the priotree struct to its own headers

== Series Details == Series: series starting with [CI,1/3] drm/i915: Move the priotree struct to its own headers URL : https://patchwork.freedesktop.org/series/41911/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4066 -> Patchwork_8740 = == Summary - SUCCESS == No

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/3] drm/i915: Move the priotree struct to its own headers

== Series Details == Series: series starting with [CI,1/3] drm/i915: Move the priotree struct to its own headers URL : https://patchwork.freedesktop.org/series/41911/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Move the priotree struct to its own headers Okay!

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/3] drm/i915: Move the priotree struct to its own headers

== Series Details == Series: series starting with [CI,1/3] drm/i915: Move the priotree struct to its own headers URL : https://patchwork.freedesktop.org/series/41911/ State : warning == Summary == $ dim checkpatch origin/drm-tip f9eaeb0abf9f drm/i915: Move the priotree struct to its own

[Intel-gfx] [CI 2/3] drm/i915: Rename priotree to sched

Having moved the priotree struct into i915_scheduler.h, identify it as the scheduling element and rebrand into i915_sched. This becomes more useful as we start attaching more information we require to propagate through the scheduler. v2: Use i915_sched_node for future distinctiveness

[Intel-gfx] [CI 3/3] drm/i915: Pack params to engine->schedule() into a struct

Today we only want to pass along the priority to engine->schedule(), but in the future we want to have much more control over the various aspects of the GPU during a context's execution, for example controlling the frequency allowed. As we need an ever growing number of parameters for scheduling,

[Intel-gfx] [CI 1/3] drm/i915: Move the priotree struct to its own headers

Over time the priotree has grown from a sorted list to a more complicated structure for propagating constraints along the dependency chain to try and resolve priority inversion. Start to segregate this information from the rest of the request/fence tracking. Signed-off-by: Chris Wilson

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: Adjust BSD2 semantics to mean any second VCS instance

== Series Details == Series: drm/i915/icl: Adjust BSD2 semantics to mean any second VCS instance URL : https://patchwork.freedesktop.org/series/41883/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4066_full -> Patchwork_8733_full = == Summary - WARNING == Minor unknown

Re: [Intel-gfx] [PATCH v4 6/6] drm/i915: Add skl_check_nv12_surface for NV12

On Wed, Apr 18, 2018 at 08:06:57PM +0200, Maarten Lankhorst wrote: > Op 18-04-18 om 17:32 schreef Ville Syrjälä: > > On Wed, Apr 18, 2018 at 09:38:13AM +0530, Vidya Srinivas wrote: > >> From: Maarten Lankhorst > >> > >> We skip src trunction/adjustments for > >>

Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for gpu: drm: i915: Change return type to vm_fault_t (rev2)

On Wed, Apr 18, 2018 at 9:24 PM, Patchwork wrote: > == Series Details == > > Series: gpu: drm: i915: Change return type to vm_fault_t (rev2) > URL : https://patchwork.freedesktop.org/series/41893/ > State : warning > > == Summary == > > $ dim checkpatch

Re: [Intel-gfx] [PATCH v4 6/6] drm/i915: Add skl_check_nv12_surface for NV12

Op 18-04-18 om 17:32 schreef Ville Syrjälä: > On Wed, Apr 18, 2018 at 09:38:13AM +0530, Vidya Srinivas wrote: >> From: Maarten Lankhorst >> >> We skip src trunction/adjustments for >> NV12 case and handle the sizes directly. >> Without this, pipe fifo underruns

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Wait for vblank after register read

== Series Details == Series: drm/i915: Wait for vblank after register read URL : https://patchwork.freedesktop.org/series/41877/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4066_full -> Patchwork_8731_full = == Summary - FAILURE == Serious unknown changes coming with

Re: [Intel-gfx] [PATCH] drm/i915/fbdev: Enable late fbdev initial configuration

On Wed, 2018-04-18 at 17:55 +0100, Chris Wilson wrote: > Quoting Souza, Jose (2018-04-18 17:42:47) > > On Wed, 2018-04-18 at 09:26 +0100, Chris Wilson wrote: > > > Quoting Souza, Jose (2018-04-18 01:07:16) > > > > On Wed, 2018-04-18 at 00:44 +0100, Chris Wilson wrote: > > > > > Quoting José

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/4] drm/i915: Always do WOPCM partitioning based on real firmware sizes

== Series Details == Series: series starting with [v4,1/4] drm/i915: Always do WOPCM partitioning based on real firmware sizes URL : https://patchwork.freedesktop.org/series/41909/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4066 -> Patchwork_8739 = == Summary - SUCCESS

[Intel-gfx] [PATCH v4 4/4] HAX enable guc for CI

Signed-off-by: Jackie Li --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index c963603..53037b5 100644 ---

[Intel-gfx] [PATCH v4 2/4] drm/i915: Always set HUC_LOADING_AGENT_GUC bit in WOPCM offset register

The enable_guc modparam is used to enable/disable GuC/HuC FW uploading dynamically during i915 module loading. If WOPCM offset register was locked without having HUC_LOADING_AGENT_GUC bit set to 1, the module reloading with both GuC and HuC FW will fail since we need to set this bit to 1 for HuC

[Intel-gfx] [PATCH v4 1/4] drm/i915: Always do WOPCM partitioning based on real firmware sizes

After enabled the WOPCM write-once registers locking status checking, reloading of the i915 module will fail with modparam enable_guc set to 3 (enable GuC and HuC firmware loading) if the module was originally loaded with enable_guc set to 1 (only enable GuC firmware loading). This is because

[Intel-gfx] [PATCH v4 3/4] drm/i915: Add code to accept valid locked WOPCM register values

In current code, we only compare the locked WOPCM register values with the calculated values. However, we can continue loading GuC/HuC firmware if the locked (or partially locked) values were valid for current GuC/HuC firmware sizes. This patch added a new code path to verify whether the locked

Re: [Intel-gfx] [PATCH i-g-t 09/11] trace.pl: Add support for colouring context execution

One suggestion below, otherwise : Reviewed-by: Lionel Landwerlin On 06/03/18 04:43, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Add the command line switch which uses different colours for different context execution boxes.

Re: [Intel-gfx] [PATCH v9 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

On 4/18/2018 9:40 AM, Oscar Mateo wrote: On 4/17/2018 3:59 PM, Yunwei Zhang wrote: L3Bank could be fused off in hardware for debug purpose, and it is possible that subslice is enabled while its corresponding L3Bank pairs are disabled. In such case, if MCR packet control register(0xFDC) is

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 07/11] trace.pl: Move min/max timestamp lookup to last loop

Reviewed-by: Lionel Landwerlin On 06/03/18 04:43, Tvrtko Ursulin wrote: From: Tvrtko Ursulin It makes sense to fetch the min and max timestamp only after the last sort of the array. Signed-off-by: Tvrtko Ursulin

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 06/11] trace.pl: Move sortQueue near its user

Reviewed-by: Lionel Landwerlin On 06/03/18 04:43, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Just to clear up some space for incoming code refactoring. Signed-off-by: Tvrtko Ursulin Cc: John Harrison

Re: [Intel-gfx] [PATCH] drm/i915/fbdev: Enable late fbdev initial configuration

Quoting Souza, Jose (2018-04-18 17:42:47) > On Wed, 2018-04-18 at 09:26 +0100, Chris Wilson wrote: > > Quoting Souza, Jose (2018-04-18 01:07:16) > > > On Wed, 2018-04-18 at 00:44 +0100, Chris Wilson wrote: > > > > Quoting José Roberto de Souza (2018-04-17 23:34:18) > > > > > If the initial fbdev >

Re: [Intel-gfx] [PATCH v9 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

On 4/18/2018 9:45 AM, Oscar Mateo wrote: On 4/18/2018 9:38 AM, Chris Wilson wrote: Quoting Oscar Mateo (2018-04-18 17:30:41) On 4/17/2018 3:58 PM, Yunwei Zhang wrote: + /* +  * HW expects MCR to be programed to a enabled slice/subslice pair +  * before any MMIO read into

Re: [Intel-gfx] [PATCH v9 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

On 4/18/2018 9:38 AM, Chris Wilson wrote: Quoting Oscar Mateo (2018-04-18 17:30:41) On 4/17/2018 3:58 PM, Yunwei Zhang wrote: + /* + * HW expects MCR to be programed to a enabled slice/subslice pair + * before any MMIO read into slice/subslice register + */ The comment

[Intel-gfx] ✓ Fi.CI.IGT: success for Enabling content-type setting for HDMI displays.

== Series Details == Series: Enabling content-type setting for HDMI displays. URL : https://patchwork.freedesktop.org/series/41876/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4065_full -> Patchwork_8730_full = == Summary - WARNING == Minor unknown changes coming with

Re: [Intel-gfx] [PATCH] drm/i915/fbdev: Enable late fbdev initial configuration

On Wed, 2018-04-18 at 09:26 +0100, Chris Wilson wrote: > Quoting Souza, Jose (2018-04-18 01:07:16) > > On Wed, 2018-04-18 at 00:44 +0100, Chris Wilson wrote: > > > Quoting José Roberto de Souza (2018-04-17 23:34:18) > > > > If the initial fbdev > > > > configuration(intel_fbdev_initial_config()) >

Re: [Intel-gfx] [PATCH v9 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

On 4/17/2018 3:59 PM, Yunwei Zhang wrote: L3Bank could be fused off in hardware for debug purpose, and it is possible that subslice is enabled while its corresponding L3Bank pairs are disabled. In such case, if MCR packet control register(0xFDC) is programed to point to a disabled bank pair, a

Re: [Intel-gfx] [PATCH v9 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

Quoting Oscar Mateo (2018-04-18 17:30:41) > > > On 4/17/2018 3:58 PM, Yunwei Zhang wrote: > > + /* > > + * HW expects MCR to be programed to a enabled slice/subslice pair > > + * before any MMIO read into slice/subslice register > > + */ > > The comment above makes more sense

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Don't use -ETIMEDOUT from inside a test

== Series Details == Series: drm/i915/selftests: Don't use -ETIMEDOUT from inside a test URL : https://patchwork.freedesktop.org/series/41828/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4065_full -> Patchwork_8728_full = == Summary - WARNING == Minor unknown changes

Re: [Intel-gfx] [PATCH v9 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

On 4/17/2018 3:58 PM, Yunwei Zhang wrote: WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO read into Slice/Subslice specific registers, MCR packet control register(0xFDC) needs to be programmed to point to any enabled slice/subslice pair. Otherwise, incorrect value

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Move request->ctx aside

== Series Details == Series: series starting with [1/3] drm/i915: Move request->ctx aside URL : https://patchwork.freedesktop.org/series/41903/ State : failure == Summary == Applying: drm/i915: Move request->ctx aside error: sha1 information is lacking or useless

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/crc: Only report a single overflow when a CRC fd is opened

== Series Details == Series: drm/crc: Only report a single overflow when a CRC fd is opened URL : https://patchwork.freedesktop.org/series/41897/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4066 -> Patchwork_8737 = == Summary - SUCCESS == No regressions found.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/crc: Only report a single overflow when a CRC fd is opened

== Series Details == Series: drm/crc: Only report a single overflow when a CRC fd is opened URL : https://patchwork.freedesktop.org/series/41897/ State : warning == Summary == $ dim checkpatch origin/drm-tip e17f1c739f3f drm/crc: Only report a single overflow when a CRC fd is opened -:52:

[Intel-gfx] ✓ Fi.CI.BAT: success for gpu: drm: i915: Change return type to vm_fault_t (rev2)

== Series Details == Series: gpu: drm: i915: Change return type to vm_fault_t (rev2) URL : https://patchwork.freedesktop.org/series/41893/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4066 -> Patchwork_8736 = == Summary - SUCCESS == No regressions found. External

Re: [Intel-gfx] [PATCH v10 10/11] drm: Add aspect ratio parsing in DRM layer

On 4/17/2018 11:17 PM, Ville Syrjälä wrote: On Tue, Apr 17, 2018 at 10:45:07AM +0530, Nautiyal, Ankit K wrote: On 4/6/2018 11:14 PM, Ville Syrjälä wrote: On Fri, Apr 06, 2018 at 10:55:14PM +0530, Nautiyal, Ankit K wrote: This patch is causing failure of IGT test kms_3d. The kms_3d test

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for gpu: drm: i915: Change return type to vm_fault_t (rev2)

== Series Details == Series: gpu: drm: i915: Change return type to vm_fault_t (rev2) URL : https://patchwork.freedesktop.org/series/41893/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: gpu: drm: i915: Change return type to vm_fault_t

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for gpu: drm: i915: Change return type to vm_fault_t (rev2)

== Series Details == Series: gpu: drm: i915: Change return type to vm_fault_t (rev2) URL : https://patchwork.freedesktop.org/series/41893/ State : warning == Summary == $ dim checkpatch origin/drm-tip 045e647f1204 gpu: drm: i915: Change return type to vm_fault_t -:11: ERROR:GIT_COMMIT_ID:

Re: [Intel-gfx] [PATCH] drm: Print unadorned pointers

On 2018-04-18 05:24 AM, Alexey Brodkin wrote: > After commit ad67b74 ("printk: hash addresses printed with %p") > pointers are being hashed when printed. However, this makes > debug output completely useless. Switch to %px in order to see the > unadorned kernel pointers. My understanding of the

Re: [Intel-gfx] [PATCH] drm: Print unadorned pointers

On Wed, Apr 18, 2018 at 12:24:50PM +0300, Alexey Brodkin wrote: > After commit ad67b74 ("printk: hash addresses printed with %p") > pointers are being hashed when printed. However, this makes > debug output completely useless. Switch to %px in order to see the > unadorned kernel pointers. > >

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/audio: set minimum CD clock to twice the BCLK

== Series Details == Series: drm/i915/audio: set minimum CD clock to twice the BCLK URL : https://patchwork.freedesktop.org/series/41888/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4066 -> Patchwork_8735 = == Summary - SUCCESS == No regressions found. External

Re: [Intel-gfx] [PATCH v3] drm/i915: set minimum CD clock to twice the BCLK.

On Wed, Apr 18, 2018 at 01:49:23PM +0300, Jani Nikula wrote: > On Tue, 17 Apr 2018, "Kumar, Abhay" wrote: > > On 4/17/2018 12:06 PM, Abhay Kumar wrote: > >> In glk when device boots with only 1366x768 panel, HDA codec doesn't > >> comeup. > >> This result in no audio

Re: [Intel-gfx] [PATCH] drm/crc: Only report a single overflow when a CRC fd is opened

On Wed, Apr 18, 2018 at 02:51:21PM +0200, Maarten Lankhorst wrote: > This reduces the amount of spam when you debug a CRC reading > program. > > Signed-off-by: Maarten Lankhorst > --- > drivers/gpu/drm/drm_debugfs_crc.c | 9 - >

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/audio: set minimum CD clock to twice the BCLK

== Series Details == Series: drm/i915/audio: set minimum CD clock to twice the BCLK URL : https://patchwork.freedesktop.org/series/41888/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/audio: set minimum CD clock to twice the BCLK

Re: [Intel-gfx] [PATCH v4 6/6] drm/i915: Add skl_check_nv12_surface for NV12

On Wed, Apr 18, 2018 at 09:38:13AM +0530, Vidya Srinivas wrote: > From: Maarten Lankhorst > > We skip src trunction/adjustments for > NV12 case and handle the sizes directly. > Without this, pipe fifo underruns are seen on APL/KBL. > > v2: For NV12, making the

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/3] drm/i915: Move the priotree struct to its own headers (rev2)

== Series Details == Series: series starting with [v2,1/3] drm/i915: Move the priotree struct to its own headers (rev2) URL : https://patchwork.freedesktop.org/series/41827/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4066 -> Patchwork_8734 = == Summary - SUCCESS ==

Re: [Intel-gfx] [PATCH 3/3] just some guess work to findout the culprit. If this breaks then we know what do.

On Wed, 14 Feb 2018, "Kumar, Abhijeet" wrote: > On 2/14/2018 4:48 PM, Takashi Iwai wrote: >> On Wed, 14 Feb 2018 10:06:19 +0100, >> Kumar, Abhijeet wrote: >>> >>> >>> On 2/14/2018 2:17 PM, Chris Wilson wrote: Quoting Kumar, Abhijeet (2018-02-14 04:53:57) > On

Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/gmbus: Increase the Bytes per Rd/Wr Op

On Wed, Apr 18, 2018 at 09:20:23AM +0300, Jani Nikula wrote: > On Wed, 18 Apr 2018, Ramalingam C wrote: > > On Tuesday 17 April 2018 11:39 PM, Ville Syrjälä wrote: > >> On Tue, Apr 17, 2018 at 02:25:32PM +0530, Ramalingam C wrote: > >>> >From Gen9 onwards Bspec says HW

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/3] drm/i915: Move the priotree struct to its own headers (rev2)

== Series Details == Series: series starting with [v2,1/3] drm/i915: Move the priotree struct to its own headers (rev2) URL : https://patchwork.freedesktop.org/series/41827/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Move the priotree struct to its own

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/3] drm/i915: Move the priotree struct to its own headers (rev2)

== Series Details == Series: series starting with [v2,1/3] drm/i915: Move the priotree struct to its own headers (rev2) URL : https://patchwork.freedesktop.org/series/41827/ State : warning == Summary == $ dim checkpatch origin/drm-tip 690cae7b1c87 drm/i915: Move the priotree struct to its

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Adjust BSD2 semantics to mean any second VCS instance

== Series Details == Series: drm/i915/icl: Adjust BSD2 semantics to mean any second VCS instance URL : https://patchwork.freedesktop.org/series/41883/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4066 -> Patchwork_8733 = == Summary - SUCCESS == No regressions found.

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t v2 00/11] trace.pl fixes

On 06/03/2018 12:43, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Collection of fixes on top of John's recent work. Problems were mostly in the request split logic which had several issues both in my original version, and also after John's improvements. Handling of

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: Adjust BSD2 semantics to mean any second VCS instance

== Series Details == Series: drm/i915/icl: Adjust BSD2 semantics to mean any second VCS instance URL : https://patchwork.freedesktop.org/series/41883/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7f451ce363f7 drm/i915/icl: Adjust BSD2 semantics to mean any second VCS instance

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/fbdev: Enable late fbdev initial configuration (rev3)

== Series Details == Series: drm/i915/fbdev: Enable late fbdev initial configuration (rev3) URL : https://patchwork.freedesktop.org/series/41851/ State : failure == Summary == Applying: drm/i915/fbdev: Enable late fbdev initial configuration error: patch failed:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Wait for vblank after register read

== Series Details == Series: drm/i915: Wait for vblank after register read URL : https://patchwork.freedesktop.org/series/41877/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4066 -> Patchwork_8731 = == Summary - SUCCESS == No regressions found. External URL:

[Intel-gfx] [PATCH 3/3] drm/i915: Store a pointer to intel_context in i915_request

To ease the frequent and ugly pointer dance of >gem_context->engine[request->engine->id] during request submission, store that pointer as request->hw_context. One major advantage that we will exploit later is that this decouples the logical context state from the engine itself. Signed-off-by:

[Intel-gfx] [PATCH 1/3] drm/i915: Move request->ctx aside

In the next patch, we want to store the intel_context pointer inside i915_request, as it is frequently access via a convoluted dance when submitting the request to hw. Having two context pointers inside i915_request leads to confusion so first rename the existing i915_gem_context pointer to

[Intel-gfx] [PATCH 2/3] drm/i915: Move fiddling with engine->last_retired_context

Move the knowledge about resetting the current context tracking on the engine from inside i915_gem_context.c into intel_engine_cs.c Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_context.c | 12 ++-- drivers/gpu/drm/i915/intel_engine_cs.c | 24

[Intel-gfx] ✓ Fi.CI.BAT: success for Enabling content-type setting for HDMI displays.

== Series Details == Series: Enabling content-type setting for HDMI displays. URL : https://patchwork.freedesktop.org/series/41876/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4065 -> Patchwork_8730 = == Summary - SUCCESS == No regressions found. External URL:

Re: [Intel-gfx] [PATCH] drm/i915: Fix LSPCON TMDS output buffer enabling from low-power state

On Mon, 16 Apr 2018, Clint Taylor wrote: > On 04/16/2018 08:53 AM, Imre Deak wrote: >> LSPCON adapters in low-power state may ignore the first I2C write during >> TMDS output buffer enabling, resulting in a blank screen even with an >> otherwise enabled pipe. Fix this

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Fix error checking for wait_var_timeout

== Series Details == Series: drm/i915/selftests: Fix error checking for wait_var_timeout URL : https://patchwork.freedesktop.org/series/41835/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4063_full -> Patchwork_8727_full = == Summary - WARNING == Minor unknown changes

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enabling content-type setting for HDMI displays.

== Series Details == Series: Enabling content-type setting for HDMI displays. URL : https://patchwork.freedesktop.org/series/41876/ State : warning == Summary == $ dim checkpatch origin/drm-tip ffb3db0b7c7e drm: content-type property for HDMI connector -:78: CHECK:PARENTHESIS_ALIGNMENT:

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