Re: [Intel-gfx] [PATCH] drm/syncobj: Use dma_fence_wait for the simple wait case

On Sat, May 05, 2018 at 11:55:49AM +0100, Chris Wilson wrote: > When waiting for a single fence beneath a syncobj, forgo our open coding > for waiting over multiple fences and call the driver specific > dma_fence_wait_timeout(). This gives the opportunity for the driver to > handle it more

[Intel-gfx] ✓ Fi.CI.IGT: success for Enable NV12 support (rev6)

== Series Details == Series: Enable NV12 support (rev6) URL : https://patchwork.freedesktop.org/series/41674/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4152_full -> Patchwork_8932_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_8932_full

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Expose RPCS (SSEU) configuration to userspace

>> I'm pretty sure Dmitry wants dynamic configurations. Yes, I afraid we really need dynamic slice configurations for media. From: Landwerlin, Lionel G Sent: Friday, May 4, 2018 9:25 AM To: Tvrtko Ursulin ; intel-gfx@lists.freedesktop.org; Rogozhkin, Dmitry V

[Intel-gfx] ✓ Fi.CI.BAT: success for Enable NV12 support (rev6)

== Series Details == Series: Enable NV12 support (rev6) URL : https://patchwork.freedesktop.org/series/41674/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4152 -> Patchwork_8932 = == Summary - SUCCESS == No regressions found. External URL:

[Intel-gfx] [PATCH v8 6/6] drm/i915: Add NV12 as supported format for sprite plane

From: Chandra Konduru This patch adds NV12 to list of supported formats for sprite plane. v2: Rebased (me) v3: Review comments by Ville addressed - Removed skl_plane_formats_with_nv12 and added NV12 case in existing skl_plane_formats - Added the 10bpc RGB formats

[Intel-gfx] [PATCH v8 5/6] drm/i915: Add NV12 as supported format for primary plane

From: Chandra Konduru This patch adds NV12 to list of supported formats for primary plane v2: Rebased (Chandra Konduru) v3: Rebased (me) v4: Review comments by Ville addressed Removed the skl_primary_formats_with_nv12 and added NV12 case in existing

[Intel-gfx] [PATCH v8 0/6] Enable NV12 support

Enabling NV12 support: - Framebuffer creation - Primary and Sprite plane support Patch series depend on Enable display workaround 827 patch mentioned below submitted by Maarten Removed BXT support for NV12 due to WA826 Changes from prev version: Made change to skl_check_nv12_surface as required

Re: [Intel-gfx] [PATCH v7 3/6] drm/i915: Add skl_check_nv12_surface for NV12

> -Original Message- > From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com] > Sent: Monday, May 7, 2018 2:56 PM > To: Srinivas, Vidya ; intel- > g...@lists.freedesktop.org > Subject: Re: [PATCH v7 3/6] drm/i915: Add skl_check_nv12_surface for NV12

[Intel-gfx] [PATCH v8 2/6] drm/i915: Enable Display WA 0528

From: "Srinivas, Vidya" Possible hang with NV12 plane surface formats. WA: When the plane source pixel format is NV12, the CHICKEN_PIPESL_* register bit 22 must be set to 1 and the render decompression must not be enabled on any of the planes in that pipe. v2: removed

[Intel-gfx] [PATCH v8 3/6] drm/i915: Add skl_check_nv12_surface for NV12

From: Maarten Lankhorst We skip src trunction/adjustments for NV12 case and handle the sizes directly. Without this, pipe fifo underruns are seen on APL/KBL. v2: For NV12, making the src coordinates multiplier of 4 v3: Moving all the src coords handling code

[Intel-gfx] [PATCH v8 1/6] drm/i915: Enable display workaround 827 for all planes, v2.

From: Maarten Lankhorst The workaround was applied only to the primary plane, but is required on all planes. Iterate over all planes in the crtc atomic check to see if the workaround is enabled, and only perform the actual toggling in the pre/post plane update

[Intel-gfx] [PATCH v8 4/6] drm/i915: Add NV12 support to intel_framebuffer_init

From: Chandra Konduru This patch adds NV12 as supported format to intel_framebuffer_init and performs various checks. v2: -Fix an issue in checks added (Chandra Konduru) v3: rebased (me) v4: Review comments by Ville addressed Added platform check for NV12 in

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/execlists: Drop unused parameter to lookup_priolist()

== Series Details == Series: series starting with [1/2] drm/i915/execlists: Drop unused parameter to lookup_priolist() URL : https://patchwork.freedesktop.org/series/42836/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4152_full -> Patchwork_8930_full = == Summary -

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for linux-next: build failure after merge of the drm-intel tree

Hi all, On Tue, 08 May 2018 01:36:25 - Patchwork wrote: > > == Series Details == > > Series: linux-next: build failure after merge of the drm-intel tree > URL : https://patchwork.freedesktop.org/series/42839/ > State : failure Blah, blah :-) Can

[Intel-gfx] ✗ Fi.CI.BAT: failure for linux-next: build failure after merge of the drm-intel tree

== Series Details == Series: linux-next: build failure after merge of the drm-intel tree URL : https://patchwork.freedesktop.org/series/42839/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4152 -> Patchwork_8931 = == Summary - FAILURE == Serious unknown changes coming

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for linux-next: build failure after merge of the drm-intel tree

== Series Details == Series: linux-next: build failure after merge of the drm-intel tree URL : https://patchwork.freedesktop.org/series/42839/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3c1454cc91d5 linux-next: build failure after merge of the drm-intel tree -:25:

[Intel-gfx] linux-next: build failure after merge of the drm-intel tree

Hi all, After merging the drm-intel tree, today's linux-next build (x86_64 allmodconfig) failed like this: drivers/gpu/drm/xen/xen_drm_front.c: In function 'xen_drv_probe': drivers/gpu/drm/xen/xen_drm_front.c:740:10: error: 'struct bus_type' has no member named 'force_dma' dev->bus->force_dma

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: configure the transcoder clocks before touching pipeconf on HSW+ (rev2)

== Series Details == Series: drm/i915: configure the transcoder clocks before touching pipeconf on HSW+ (rev2) URL : https://patchwork.freedesktop.org/series/42436/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4151_full -> Patchwork_8929_full = == Summary - FAILURE ==

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/execlists: Drop unused parameter to lookup_priolist()

== Series Details == Series: series starting with [1/2] drm/i915/execlists: Drop unused parameter to lookup_priolist() URL : https://patchwork.freedesktop.org/series/42836/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4152 -> Patchwork_8930 = == Summary - SUCCESS ==

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/execlists: Drop unused parameter to lookup_priolist()

== Series Details == Series: series starting with [1/2] drm/i915/execlists: Drop unused parameter to lookup_priolist() URL : https://patchwork.freedesktop.org/series/42836/ State : warning == Summary == $ dim checkpatch origin/drm-tip fbc6c33847ee drm/i915/execlists: Drop unused parameter to

[Intel-gfx] [PATCH 2/2] drm/i915/execlists: Cache the priolist when rescheduling

When rescheduling a change of dependencies, they all need to be added to the same priolist (at least the ones on the same engine!). Since we likely want to move a batch of requests, keep the priolist around. Signed-off-by: Chris Wilson ---

[Intel-gfx] [PATCH 1/2] drm/i915/execlists: Drop unused parameter to lookup_priolist()

lookup_priolist() no longer attaches the request into the priolist, it just returns the priolist for the given priority instead. Drop the unused parameter. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_lrc.c | 8 +++- 1 file changed, 3 insertions(+), 5

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: configure the transcoder clocks before touching pipeconf on HSW+ (rev2)

== Series Details == Series: drm/i915: configure the transcoder clocks before touching pipeconf on HSW+ (rev2) URL : https://patchwork.freedesktop.org/series/42436/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4151 -> Patchwork_8929 = == Summary - SUCCESS == No

Re: [Intel-gfx] [PATCH i-g-t 3/4] trace.pl: Fix incomplete request handling

On 4/23/2018 2:52 AM, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Incomplete requests (no notify, no context complete) have to be corrected by looking at the engine timeline, and not the sorted-by-start-time view as was previously used. Per-engine timelines are

Re: [Intel-gfx] [PATCH 1/5] drm/i915/gtt: Move wmb inside ggtt_invalidate

Quoting Mika Kuoppala (2018-05-07 17:52:18) > We use a pattern of wmb() along with ggtt_invalidate. > Move the wmb out from call sites into the ggtt_invalidate > as it is part of invalidation. > > Cc: Chris Wilson > Cc: Matthew Auld >

Re: [Intel-gfx] [PATCH] drm/i915: Don't request a bug report for unsafe module parameters

On Sun, May 06, 2018 at 07:31:47PM +0100, Chris Wilson wrote: > Unsafe module parameters are just that, unsafe. If the user is foolish > enough to try them and the kernel breaks, they get to keep both pieces. > Don't ask them to file a bug report if they broke it themselves. > > References:

Re: [Intel-gfx] [PATCH 4/5] drm/i915/gtt: Flush write combining buffer on insert entries

Quoting Mika Kuoppala (2018-05-07 17:52:21) > We could be using write combining map through which we insert > our ptes. Make sure to flush the write combining buffer > after the writes. "Could?" We do flush the ppgtt before execution, and the ppgtt is only used by execution. -Chris

Re: [Intel-gfx] [PATCH 3/5] drm/i915/gtt: Don't track dirty in gen6_alloc_va_range

Quoting Mika Kuoppala (2018-05-07 17:52:20) > gen6_alloc_va_range is only used to init the aliasing ppgtt, so > we can be certain that it will be dirty every time. No need > to track it. Nah, we want it for full-ppgtt... -Chris ___ Intel-gfx mailing

Re: [Intel-gfx] [PATCH 2/5] drm/i915/gtt: Combine marking engines dirty with wmb

Quoting Mika Kuoppala (2018-05-07 17:52:19) > It is a common pattern to mark the tlbs dirty along with flushing > the writes. Introduce gen6_ppgtt_invalidate for this. It wasn't that common at all. We were careful not to do more wmb() than required before; not so now. -Chris

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915/gtt: Move wmb inside ggtt_invalidate

== Series Details == Series: series starting with [1/5] drm/i915/gtt: Move wmb inside ggtt_invalidate URL : https://patchwork.freedesktop.org/series/42821/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4151_full -> Patchwork_8928_full = == Summary - WARNING == Minor

Re: [Intel-gfx] [PATCH 3/8] drm/i915/icl: add basic support for the ICL clocks

On Fri, Apr 27, 2018 at 04:14:36PM -0700, Paulo Zanoni wrote: > This commit introduces the definitions for the ICL clocks and adds the > basic functions to the shared DPLL framework. It adds code for the > Enable and Disable sequences for some PLLs, but it does not have the > code to compute the

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/7] drm/i915: Flush submission tasklet after bumping priority

== Series Details == Series: series starting with [v2,1/7] drm/i915: Flush submission tasklet after bumping priority URL : https://patchwork.freedesktop.org/series/42815/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4151_full -> Patchwork_8927_full = == Summary - SUCCESS

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/gtt: Move wmb inside ggtt_invalidate

== Series Details == Series: series starting with [1/5] drm/i915/gtt: Move wmb inside ggtt_invalidate URL : https://patchwork.freedesktop.org/series/42821/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4151 -> Patchwork_8928 = == Summary - SUCCESS == No regressions

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915/gtt: Move wmb inside ggtt_invalidate

== Series Details == Series: series starting with [1/5] drm/i915/gtt: Move wmb inside ggtt_invalidate URL : https://patchwork.freedesktop.org/series/42821/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/gtt: Move wmb inside ggtt_invalidate Okay! Commit:

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915/gtt: Move wmb inside ggtt_invalidate

== Series Details == Series: series starting with [1/5] drm/i915/gtt: Move wmb inside ggtt_invalidate URL : https://patchwork.freedesktop.org/series/42821/ State : warning == Summary == $ dim checkpatch origin/drm-tip 09ef7cafacef drm/i915/gtt: Move wmb inside ggtt_invalidate 778f0e880a15

[Intel-gfx] [PATCH 2/5] drm/i915/gtt: Combine marking engines dirty with wmb

It is a common pattern to mark the tlbs dirty along with flushing the writes. Introduce gen6_ppgtt_invalidate for this. Cc: Chris Wilson Cc: Matthew Auld Signed-off-by: Mika Kuoppala ---

[Intel-gfx] [PATCH 1/5] drm/i915/gtt: Move wmb inside ggtt_invalidate

We use a pattern of wmb() along with ggtt_invalidate. Move the wmb out from call sites into the ggtt_invalidate as it is part of invalidation. Cc: Chris Wilson Cc: Matthew Auld Signed-off-by: Mika Kuoppala ---

[Intel-gfx] [PATCH 3/5] drm/i915/gtt: Don't track dirty in gen6_alloc_va_range

gen6_alloc_va_range is only used to init the aliasing ppgtt, so we can be certain that it will be dirty every time. No need to track it. Cc: Chris Wilson Cc: Matthew Auld Signed-off-by: Mika Kuoppala ---

[Intel-gfx] [PATCH 4/5] drm/i915/gtt: Flush write combining buffer on insert entries

We could be using write combining map through which we insert our ptes. Make sure to flush the write combining buffer after the writes. Cc: Chris Wilson Cc: Matthew Auld Signed-off-by: Mika Kuoppala ---

[Intel-gfx] [PATCH 5/5] drm/i915/gtt: Trust the uncached store to flush wcb

Not all architectures guarantee that uncached read will flush the write combining buffer. So marking it explicitly is recommended [1]. However we know the architecture we are operating on and can avoid wmb as the UC store will flush the wcb [2]. Omit the wmb() on gen6_ppgtt_invalidate as

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/7] drm/i915: Flush submission tasklet after bumping priority

== Series Details == Series: series starting with [v2,1/7] drm/i915: Flush submission tasklet after bumping priority URL : https://patchwork.freedesktop.org/series/42815/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4151 -> Patchwork_8927 = == Summary - SUCCESS == No

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/7] drm/i915: Flush submission tasklet after bumping priority

== Series Details == Series: series starting with [v2,1/7] drm/i915: Flush submission tasklet after bumping priority URL : https://patchwork.freedesktop.org/series/42815/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Flush submission tasklet after bumping

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/7] drm/i915: Flush submission tasklet after bumping priority

== Series Details == Series: series starting with [v2,1/7] drm/i915: Flush submission tasklet after bumping priority URL : https://patchwork.freedesktop.org/series/42815/ State : warning == Summary == $ dim checkpatch origin/drm-tip 8cef3a53edbb drm/i915: Flush submission tasklet after

Re: [Intel-gfx] [PATCH] drm/dp: add module parameter for the dpcd access max retries

On Mon, May 07, 2018 at 05:09:21PM +0200, Daniel Vetter wrote: > On Mon, May 07, 2018 at 02:33:25PM +0100, Chris Wilson wrote: > > Quoting Feng Tang (2018-05-07 22:26:34) > > > Hi Chris, > > > > > > Thanks for the prompt review! > > > > > > On Mon, May 07, 2018 at 11:40:45AM +0100, Chris Wilson

[Intel-gfx] ✓ Fi.CI.IGT: success for Enabling content-type setting for HDMI displays. (rev8)

== Series Details == Series: Enabling content-type setting for HDMI displays. (rev8) URL : https://patchwork.freedesktop.org/series/41876/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4150_full -> Patchwork_8926_full = == Summary - WARNING == Minor unknown changes

Re: [Intel-gfx] [PATCH] drm/dp: add module parameter for the dpcd access max retries

On Mon, May 07, 2018 at 02:33:25PM +0100, Chris Wilson wrote: > Quoting Feng Tang (2018-05-07 22:26:34) > > Hi Chris, > > > > Thanks for the prompt review! > > > > On Mon, May 07, 2018 at 11:40:45AM +0100, Chris Wilson wrote: > > > Quoting Feng Tang (2018-05-07 11:36:09) > > > > To fulfil the

Re: [Intel-gfx] [PATCH] drm/i915: Add documentation to gen9_set_dc_state()

On Tue, Apr 17, 2018 at 02:31:47PM +0300, Imre Deak wrote: > Add documentation to gen9_set_dc_state() on what enabling a given DC > state means and at what point HW/DMC actually enters/exits these states. > > Cc: Jani Nikula > Cc: Daniel Vetter >

Re: [Intel-gfx] [PATCH v3] drm/i915: Speed up idle detection by kicking the tasklets

/0day-ci/linux/commits/Chris-Wilson/drm-i915-Speed-up-idle-detection-by-kicking-the-tasklets/20180507-184057 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: i386-randconfig-x0-05071422 (attached as .config) compiler: gcc-5 (Debian 5.5.0-3) 5.4.1 20171010 reproduce: # save

Re: [Intel-gfx] [PATCH v9 1/2] drm: content-type property for HDMI connector

On Mon, May 07, 2018 at 04:16:40PM +0300, StanLis wrote: > From: Stanislav Lisovskiy > > Added content_type property to drm_connector_state > in order to properly handle external HDMI TV content-type setting. > > v2: > * Moved helper function which attaches

[Intel-gfx] [PATCH v2 4/7] drm/i915/guc: Make submission tasklet hardirq safe

Prepare to allow the GuC submission to be run from underneath a hardirq timer context (and not just the current softirq context) as is required for fast preemption resets and context switches. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_guc_submission.c

[Intel-gfx] [PATCH v2 7/7] drm/i915: Speed up idle detection by kicking the tasklets

We rely on ksoftirqd to run in a timely fashion in order to drain the execlists queue. Quite frequently, it does not. In some cases we may see latencies of over 200ms triggering our idle timeouts and forcing us to declare the driver wedged! Thus we can speed up idle detection by bypassing

[Intel-gfx] [PATCH v2 5/7] drm/i915/execlists: Direct submit onto idle engines

Bypass using the tasklet to submit the first request to HW, as the tasklet may be deferred unto ksoftirqd and at a minimum will add in excess of 10us (and maybe tens of milliseconds) to our execution latency. This latency reduction is most notable when execution flows between engines. v2: Beware

[Intel-gfx] [PATCH v2 2/7] drm/i915: Disable tasklet scheduling across initial scheduling

During request submission, we call the engine->schedule() function so that we may reorder the active requests as required for inheriting the new request's priority. This may schedule several tasklets to run on the local CPU, but we will need to schedule the tasklets again for the new request.

[Intel-gfx] [PATCH v2 3/7] drm/i915/execlists: Make submission tasklet hardirq safe

Prepare to allow the execlists submission to be run from underneath a hardirq timer context (and not just the current softirq context) as is required for fast preemption resets and context switches. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_lrc.c | 42

[Intel-gfx] [PATCH v2 6/7] drm/i915/execlists: Direct submission from irq handler

Continuing the themem of bypassing ksoftirqd latency, also first try to directly submit from the CS interrupt handler to clear the ELSP and queue the next. In the past, we have been hesitant to do this as the context switch processing has been quite heavy, requiring forcewaked mmio. However, as

[Intel-gfx] [PATCH v2 1/7] drm/i915: Flush submission tasklet after bumping priority

When called from process context tasklet_schedule() defers itself to ksoftirqd. From experience this may cause unacceptable latencies of over 200ms in executing the submission tasklet, our goal is to reprioritise the HW execution queue and trigger HW preemption immediately, so disable bh over the

[Intel-gfx] ✓ Fi.CI.BAT: success for Enabling content-type setting for HDMI displays. (rev8)

== Series Details == Series: Enabling content-type setting for HDMI displays. (rev8) URL : https://patchwork.freedesktop.org/series/41876/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4150 -> Patchwork_8926 = == Summary - SUCCESS == No regressions found. External

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enabling content-type setting for HDMI displays. (rev8)

== Series Details == Series: Enabling content-type setting for HDMI displays. (rev8) URL : https://patchwork.freedesktop.org/series/41876/ State : warning == Summary == $ dim checkpatch origin/drm-tip fbbcc8d1f453 drm: content-type property for HDMI connector -:129: CHECK:LINE_SPACING: Please

Re: [Intel-gfx] [PATCH v13 08/10] drm: Expose modes with aspect ratio, only if requested

On Fri, May 04, 2018 at 11:19:45PM +0300, Ville Syrjälä wrote: > On Thu, May 03, 2018 at 08:26:26AM +0200, Daniel Vetter wrote: > > On Wed, May 02, 2018 at 12:20:20PM +0530, Nautiyal, Ankit K wrote: > > > From: Ankit Nautiyal > > > > > > We parse the EDID and add all

Re: [Intel-gfx] [PATCH] drm/dp: add module parameter for the dpcd access max retries

Quoting Feng Tang (2018-05-07 22:26:34) > Hi Chris, > > Thanks for the prompt review! > > On Mon, May 07, 2018 at 11:40:45AM +0100, Chris Wilson wrote: > > Quoting Feng Tang (2018-05-07 11:36:09) > > > To fulfil the Dell 4K monitor, the dpcd max retries has been bumped > > > from 7 to 32, which

Re: [Intel-gfx] [PATCH] drm/dp: add module parameter for the dpcd access max retries

Hi Chris, Thanks for the prompt review! On Mon, May 07, 2018 at 11:40:45AM +0100, Chris Wilson wrote: > Quoting Feng Tang (2018-05-07 11:36:09) > > To fulfil the Dell 4K monitor, the dpcd max retries has been bumped > > from 7 to 32, which may hurt the boot/init time for some platforms, > > as

[Intel-gfx] [PATCH v9 2/2] i915: content-type property for HDMI connector

From: Stanislav Lisovskiy Added encoding of drm content_type property from drm_connector_state within AVI infoframe in order to properly handle external HDMI TV content-type setting. This requires also manipulationg ITC bit, as stated in HDMI spec. v2: * Moved

[Intel-gfx] [PATCH v9 1/2] drm: content-type property for HDMI connector

From: Stanislav Lisovskiy Added content_type property to drm_connector_state in order to properly handle external HDMI TV content-type setting. v2: * Moved helper function which attaches content type property to the drm core, as was suggested. Removed

[Intel-gfx] [PATCH v9 0/2] Enabling content-type setting for HDMI displays.

From: Stanislav Lisovskiy Added content type setting property to drm_connector(part 1) and enabled transmitting it with HDMI AVI infoframes for i915(part 2). Stanislav Lisovskiy (2): drm: content-type property for HDMI connector i915: content-type property for

Re: [Intel-gfx] [PATCH v13 08/10] drm: Expose modes with aspect ratio, only if requested

On 5/7/2018 5:58 PM, Ville Syrjälä wrote: On Mon, May 07, 2018 at 10:34:53AM +0530, Nautiyal, Ankit K wrote: On 5/5/2018 1:49 AM, Ville Syrjälä wrote: On Thu, May 03, 2018 at 08:26:26AM +0200, Daniel Vetter wrote: On Wed, May 02, 2018 at 12:20:20PM +0530, Nautiyal, Ankit K wrote: From:

Re: [Intel-gfx] [PATCH v13 08/10] drm: Expose modes with aspect ratio, only if requested

On Mon, May 07, 2018 at 10:34:53AM +0530, Nautiyal, Ankit K wrote: > > > On 5/5/2018 1:49 AM, Ville Syrjälä wrote: > > On Thu, May 03, 2018 at 08:26:26AM +0200, Daniel Vetter wrote: > >> On Wed, May 02, 2018 at 12:20:20PM +0530, Nautiyal, Ankit K wrote: > >>> From: Ankit Nautiyal

Re: [Intel-gfx] [PATCH 2/7] drm/i915: Combine set-wedged protection and tasklet kicking

Quoting Mika Kuoppala (2018-05-07 13:09:20) > Chris Wilson writes: > > > Around request submission, we protect the call to schedule with a > > premption disable loop to prevent set-wedge chaning function pointers > > s/premption/preemption > s/chaning/changing > >

Re: [Intel-gfx] [PATCH 2/7] drm/i915: Combine set-wedged protection and tasklet kicking

Chris Wilson writes: > Around request submission, we protect the call to schedule with a > premption disable loop to prevent set-wedge chaning function pointers s/premption/preemption s/chaning/changing Also RCU read critical sections can be preempted if

Re: [Intel-gfx] [PATCH 1/7] drm/i915: Flush submission tasklet after bumping priority

Quoting Mika Kuoppala (2018-05-07 12:15:58) > Chris Wilson writes: > > > When called from process context tasklet_schedule() defers itself to > > ksoftirqd. From experience this may cause unacceptable latencies of over > > 200ms in executing the submission tasklet, our

Re: [Intel-gfx] [PATCH 1/7] drm/i915: Flush submission tasklet after bumping priority

Chris Wilson writes: > When called from process context tasklet_schedule() defers itself to > ksoftirqd. From experience this may cause unacceptable latencies of over > 200ms in executing the submission tasklet, our goal is to reprioritise > the HW execution queue and

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/dp: add module parameter for the dpcd access max retries

== Series Details == Series: drm/dp: add module parameter for the dpcd access max retries URL : https://patchwork.freedesktop.org/series/42803/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4150 -> Patchwork_8925 = == Summary - FAILURE == Serious unknown changes coming

Re: [Intel-gfx] [PATCH] drm/dp: add module parameter for the dpcd access max retries

Quoting Feng Tang (2018-05-07 11:36:09) > To fulfil the Dell 4K monitor, the dpcd max retries has been bumped > from 7 to 32, which may hurt the boot/init time for some platforms, > as the 32 retries may take hundreds of ms. If we need that many retries, so be it. No modparam, the driver just has

[Intel-gfx] [PATCH] drm/dp: add module parameter for the dpcd access max retries

To fulfil the Dell 4K monitor, the dpcd max retries has been bumped from 7 to 32, which may hurt the boot/init time for some platforms, as the 32 retries may take hundreds of ms. This patch makes no functional change, but make the max retries adjustable, so that concerned users/platforms can have

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/7] drm/i915: Flush submission tasklet after bumping priority (rev2)

== Series Details == Series: series starting with [1/7] drm/i915: Flush submission tasklet after bumping priority (rev2) URL : https://patchwork.freedesktop.org/series/42800/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4150 -> Patchwork_8924 = == Summary - FAILURE ==

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/7] drm/i915: Flush submission tasklet after bumping priority (rev2)

== Series Details == Series: series starting with [1/7] drm/i915: Flush submission tasklet after bumping priority (rev2) URL : https://patchwork.freedesktop.org/series/42800/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Flush submission tasklet after bumping

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] drm/i915: Flush submission tasklet after bumping priority (rev2)

== Series Details == Series: series starting with [1/7] drm/i915: Flush submission tasklet after bumping priority (rev2) URL : https://patchwork.freedesktop.org/series/42800/ State : warning == Summary == $ dim checkpatch origin/drm-tip a337a1138169 drm/i915: Flush submission tasklet after

[Intel-gfx] ✓ Fi.CI.IGT: success for Enable NV12 support (rev5)

== Series Details == Series: Enable NV12 support (rev5) URL : https://patchwork.freedesktop.org/series/41674/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4150_full -> Patchwork_8922_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_8922_full

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/7] drm/i915: Flush submission tasklet after bumping priority

== Series Details == Series: series starting with [1/7] drm/i915: Flush submission tasklet after bumping priority URL : https://patchwork.freedesktop.org/series/42800/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4150 -> Patchwork_8923 = == Summary - FAILURE ==

Re: [Intel-gfx] [PATCH] dma-fence: Make ->enable_signaling optional

Op 04-05-18 om 16:10 schreef Daniel Vetter: > Many drivers have a trivial implementation for ->enable_signaling. > Let's make it optional by assuming that signalling is already > available when the callback isn't present. > > v2: Don't do the trick to set the ENABLE_SIGNAL_BIT > unconditionally,

[Intel-gfx] [PATCH v3] drm/i915: Speed up idle detection by kicking the tasklets

We rely on ksoftirqd to run in a timely fashion in order to drain the execlists queue. Quite frequently, it does not. In some cases we may see latencies of over 200ms triggering our idle timeouts and forcing us to declare the driver wedged! Thus we can speed up idle detection by bypassing

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/7] drm/i915: Flush submission tasklet after bumping priority

== Series Details == Series: series starting with [1/7] drm/i915: Flush submission tasklet after bumping priority URL : https://patchwork.freedesktop.org/series/42800/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Flush submission tasklet after bumping priority

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] drm/i915: Flush submission tasklet after bumping priority

== Series Details == Series: series starting with [1/7] drm/i915: Flush submission tasklet after bumping priority URL : https://patchwork.freedesktop.org/series/42800/ State : warning == Summary == $ dim checkpatch origin/drm-tip 003f117f2171 drm/i915: Flush submission tasklet after bumping

Re: [Intel-gfx] [PATCH v7 3/6] drm/i915: Add skl_check_nv12_surface for NV12

Op 10-05-18 om 10:31 schreef Vidya Srinivas: > From: Maarten Lankhorst > > We skip src trunction/adjustments for > NV12 case and handle the sizes directly. > Without this, pipe fifo underruns are seen on APL/KBL. > > v2: For NV12, making the src coordinates

[Intel-gfx] [PATCH 2/7] drm/i915: Combine set-wedged protection and tasklet kicking

Around request submission, we protect the call to schedule with a premption disable loop to prevent set-wedge chaning function pointers underneath us. This also prevents the tasklet running on the local CPU, a trick we use immediately afterwards to forcibly execute the tasklet after submission. We

[Intel-gfx] [PATCH 3/7] drm/i915/execlists: Make submission tasklet hardirq safe

Prepare to allow the execlists submission to be run from underneath a hardirq timer context (and not just the current softirq context) as is required for fast preemption resets and context switches. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_lrc.c | 25

[Intel-gfx] [PATCH 6/7] drm/i915/execlists: Direct submission from irq handler

Continuing the themem of bypassing ksoftirqd latency, also first try to directly submit from the CS interrupt handler to clear the ELSP and queue the next. In the past, we have been hesitant to do this as the context switch processing has been quite heavy, requiring forcewaked mmio. However, as

[Intel-gfx] [PATCH 7/7] drm/i915: Speed up idle detection by kicking the tasklets

We rely on ksoftirqd to run in a timely fashion in order to drain the execlists queue. Quite frequently, it does not. In some cases we may see latencies of over 200ms triggering our idle timeouts and forcing us to declare the driver wedged! Thus we can speed up idle detection by bypassing

[Intel-gfx] [PATCH 5/7] drm/i915/execlists: Direct submit onto idle engines

Bypass using the tasklet to submit the first request to HW, as the tasklet may be deferred unto ksoftirqd and at a minimum will add in excess of 10us (and maybe tens of milliseconds) to our execution latency. This latency reduction is most notable when execution flows between engines.

[Intel-gfx] [PATCH 1/7] drm/i915: Flush submission tasklet after bumping priority

When called from process context tasklet_schedule() defers itself to ksoftirqd. From experience this may cause unacceptable latencies of over 200ms in executing the submission tasklet, our goal is to reprioritise the HW execution queue and trigger preemption immediately, so convert the rcu

[Intel-gfx] [PATCH 4/7] drm/i915/guc: Make submission tasklet hardirq safe

Prepare to allow the GuC submission to be run from underneath a hardirq timer context (and not just the current softirq context) as is required for fast preemption resets and context switches. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_guc_submission.c

[Intel-gfx] ✓ Fi.CI.BAT: success for Enable NV12 support (rev5)

== Series Details == Series: Enable NV12 support (rev5) URL : https://patchwork.freedesktop.org/series/41674/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4150 -> Patchwork_8922 = == Summary - SUCCESS == No regressions found. External URL:

Re: [Intel-gfx] [PATCH v2] drm/i915: Speed up idle detection by kicking the tasklets

Quoting Mika Kuoppala (2018-05-07 09:54:27) > Chris Wilson writes: > > > Quoting Mika Kuoppala (2018-05-07 09:34:24) > >> Chris Wilson writes: > >> > >> > We rely on ksoftirqd to run in a timely fashion in order to drain the > >> > execlists

Re: [Intel-gfx] [PATCH v2] drm/i915: Speed up idle detection by kicking the tasklets

Chris Wilson writes: > Quoting Mika Kuoppala (2018-05-07 09:34:24) >> Chris Wilson writes: >> >> > We rely on ksoftirqd to run in a timely fashion in order to drain the >> > execlists queue. Quite frequently, it does not. In some cases we may

Re: [Intel-gfx] [PATCH 1/2] x86/gpu: reserve ICL's graphics stolen memory

Ingo, do you prefer to merge through our tree with your ack? Quoting Paulo Zanoni (2018-05-04 23:32:51) > ICL changes the registers and addresses to 64 bits. > > I also briefly looked at implementing an u64 version of the PCI config > read functions, but I concluded this wouldn't be trivial, so

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority (rev2)

== Series Details == Series: series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority (rev2) URL : https://patchwork.freedesktop.org/series/42783/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4150_full -> Patchwork_8920_full = == Summary -

Re: [Intel-gfx] [PATCH v6 6/6] drm/i915: Add NV12 as supported format for sprite plane

> -Original Message- > From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com] > Sent: Monday, May 7, 2018 2:08 PM > To: Srinivas, Vidya ; intel- > g...@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH v6 6/6] drm/i915: Add NV12 as supported >

Re: [Intel-gfx] [PATCH v6 6/6] drm/i915: Add NV12 as supported format for sprite plane

Op 07-05-18 om 10:34 schreef Srinivas, Vidya: > >> -Original Message- >> From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com] >> Sent: Monday, May 7, 2018 1:59 PM >> To: Srinivas, Vidya ; intel- >> g...@lists.freedesktop.org >> Subject: Re:

Re: [Intel-gfx] [PATCH v2] drm/i915: Speed up idle detection by kicking the tasklets

Quoting Mika Kuoppala (2018-05-07 09:34:24) > Chris Wilson writes: > > > We rely on ksoftirqd to run in a timely fashion in order to drain the > > execlists queue. Quite frequently, it does not. In some cases we may see > > latencies of over 200ms triggering our idle

Re: [Intel-gfx] [PATCH v6 6/6] drm/i915: Add NV12 as supported format for sprite plane

> -Original Message- > From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com] > Sent: Monday, May 7, 2018 1:59 PM > To: Srinivas, Vidya ; intel- > g...@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH v6 6/6] drm/i915: Add NV12 as supported >

Re: [Intel-gfx] [PATCH v2] drm/i915: Speed up idle detection by kicking the tasklets

Chris Wilson writes: > We rely on ksoftirqd to run in a timely fashion in order to drain the > execlists queue. Quite frequently, it does not. In some cases we may see > latencies of over 200ms triggering our idle timeouts and forcing us to > declare the driver wedged!

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