Re: [Intel-gfx] [PATCH] drm/i915: Release power well if load DMC failed
On Tue, 20 Nov 2018, "Lee, Shawn C" wrote:
> Driver obtain power well at intel_csr_ucode_init().
> And release it after load DMC firmware successful.
Correct.
> An issue happened when DMC was not found or failed
> to load. Power well would not be released and just
> output some error messages. Driver have to release
> power well properly to keep put/get balance.
No. We intentionally do not release it until dmc firmware load succeeds.
See the comment in intel_csr_ucode_init(), as well as this in the branch
where dmc load fails:
dev_notice(dev_priv->drm.dev,
"Failed to load DMC firmware %s."
" Disabling runtime power management.\n",
csr->fw_path);
We don't support runtime pm without dmc on platforms with dmc.
BR,
Jani.
>
> Cc: Jani Nikula
> Cc: Rodrigo Vivi
> Cc: Jose Roberto de Souza
> Cc: Cooper Chiou
>
> Signed-off-by: Lee, Shawn C
> ---
> drivers/gpu/drm/i915/intel_csr.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_csr.c
> b/drivers/gpu/drm/i915/intel_csr.c
> index a516697bf57d..8d04d7b6f00a 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -425,8 +425,6 @@ static void csr_load_work_fn(struct work_struct *work)
> if (dev_priv->csr.dmc_payload) {
> intel_csr_load_program(dev_priv);
>
> - intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
> -
> DRM_INFO("Finished loading DMC firmware %s (v%u.%u)\n",
>dev_priv->csr.fw_path,
>CSR_VERSION_MAJOR(csr->version),
> @@ -440,6 +438,7 @@ static void csr_load_work_fn(struct work_struct *work)
> INTEL_UC_FIRMWARE_URL);
> }
>
> + intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
> release_firmware(fw);
> }
--
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/gvt: Avoid use-after-free iterating the gtt list
== Series Details == Series: series starting with [1/2] drm/i915/gvt: Avoid use-after-free iterating the gtt list URL : https://patchwork.freedesktop.org/series/52786/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5174_full -> Patchwork_10870_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10870_full that come from known issues: === IGT changes === Issues hit igt@gem_ctx_isolation@vcs1-s3: shard-apl: SKIP -> INCOMPLETE (fdo#103927) igt@kms_ccs@pipe-a-crc-sprite-planes-basic: shard-glk: PASS -> FAIL (fdo#108145) igt@kms_cursor_crc@cursor-128x128-suspend: shard-skl: PASS -> INCOMPLETE (fdo#104108) igt@kms_cursor_crc@cursor-256x256-suspend: shard-skl: PASS -> FAIL (fdo#103232, fdo#103191) igt@kms_cursor_crc@cursor-256x85-onscreen: shard-apl: PASS -> FAIL (fdo#103232) +1 igt@kms_fbcon_fbt@psr: shard-skl: NOTRUN -> FAIL (fdo#107882) igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#105363) igt@kms_flip@flip-vs-expired-vblank: shard-skl: NOTRUN -> FAIL (fdo#105363) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen: shard-skl: NOTRUN -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite: shard-glk: PASS -> FAIL (fdo#103167) +2 igt@kms_plane@pixel-format-pipe-c-planes: shard-apl: PASS -> FAIL (fdo#103166) +1 igt@kms_plane@plane-position-covered-pipe-a-planes: shard-skl: NOTRUN -> FAIL (fdo#103166) igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#108145) +2 igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: shard-skl: PASS -> FAIL (fdo#107815) Possible fixes igt@gem_pwrite@big-gtt-backwards: shard-apl: INCOMPLETE (fdo#103927) -> PASS igt@kms_cursor_crc@cursor-128x128-onscreen: shard-apl: FAIL (fdo#103232) -> PASS igt@kms_cursor_legacy@cursora-vs-flipa-toggle: shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite: shard-glk: FAIL (fdo#103167) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render: shard-apl: FAIL (fdo#103167) -> PASS +1 igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: shard-skl: FAIL (fdo#107815) -> PASS igt@kms_plane_multiple@atomic-pipe-b-tiling-y: shard-glk: FAIL (fdo#103166) -> PASS igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: shard-apl: FAIL (fdo#103166) -> PASS fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763 fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538 fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815 fdo#107882 https://bugs.freedesktop.org/show_bug.cgi?id=107882 fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145 == Participating hosts (7 -> 6) == Missing(1): shard-iclb == Build changes == * Linux: CI_DRM_5174 -> Patchwork_10870 CI_DRM_5174: 0bfa7192170c039a271ebc27222b4b91516e73f6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4722: fdcdfa1e220c5070072d5dac9523cd105e7406c2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10870: 295606f32d7a980ca03d0ad39aba1b2f13899bc0 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10870/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Release power well if load DMC failed
Driver obtain power well at intel_csr_ucode_init().
And release it after load DMC firmware successful.
An issue happened when DMC was not found or failed
to load. Power well would not be released and just
output some error messages. Driver have to release
power well properly to keep put/get balance.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Jose Roberto de Souza
Cc: Cooper Chiou
Signed-off-by: Lee, Shawn C
---
drivers/gpu/drm/i915/intel_csr.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index a516697bf57d..8d04d7b6f00a 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -425,8 +425,6 @@ static void csr_load_work_fn(struct work_struct *work)
if (dev_priv->csr.dmc_payload) {
intel_csr_load_program(dev_priv);
- intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
-
DRM_INFO("Finished loading DMC firmware %s (v%u.%u)\n",
dev_priv->csr.fw_path,
CSR_VERSION_MAJOR(csr->version),
@@ -440,6 +438,7 @@ static void csr_load_work_fn(struct work_struct *work)
INTEL_UC_FIRMWARE_URL);
}
+ intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
release_firmware(fw);
}
--
2.7.4
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[Intel-gfx] ✓ Fi.CI.IGT: success for Respin of remaining DSC + FEC patches
== Series Details == Series: Respin of remaining DSC + FEC patches URL : https://patchwork.freedesktop.org/series/52781/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5174_full -> Patchwork_10869_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10869_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10869_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10869_full: === IGT changes === Warnings igt@pm_rc6_residency@rc6-accuracy: shard-snb: SKIP -> PASS igt@tools_test@tools_test: shard-apl: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_10869_full that come from known issues: === IGT changes === Issues hit igt@kms_cursor_crc@cursor-256x85-random: shard-apl: NOTRUN -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-size-change: shard-apl: PASS -> FAIL (fdo#103232) igt@kms_fbcon_fbt@psr: shard-skl: NOTRUN -> FAIL (fdo#107882) igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#105363) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen: shard-skl: NOTRUN -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen: shard-glk: PASS -> FAIL (fdo#103167) +1 igt@kms_plane@plane-position-covered-pipe-a-planes: shard-skl: NOTRUN -> FAIL (fdo#103166) igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: shard-skl: NOTRUN -> FAIL (fdo#108145, fdo#107815) +2 igt@kms_plane_multiple@atomic-pipe-b-tiling-y: shard-apl: PASS -> FAIL (fdo#103166) +3 igt@kms_universal_plane@cursor-fb-leak-pipe-b: shard-kbl: PASS -> DMESG-WARN (fdo#105602, fdo#103558) +7 igt@kms_universal_plane@universal-plane-pipe-c-functional: shard-glk: PASS -> FAIL (fdo#103166) igt@pm_rpm@modeset-lpsp-stress: shard-skl: PASS -> INCOMPLETE (fdo#107807) igt@pm_rpm@universal-planes: shard-skl: NOTRUN -> INCOMPLETE (fdo#107807) Possible fixes igt@gem_ppgtt@blt-vs-render-ctxn: shard-skl: TIMEOUT (fdo#108039) -> PASS igt@gem_pwrite@big-gtt-backwards: shard-apl: INCOMPLETE (fdo#103927) -> PASS igt@kms_color@pipe-a-ctm-max: shard-apl: FAIL (fdo#108147) -> PASS igt@kms_color@pipe-c-legacy-gamma: shard-apl: FAIL (fdo#104782) -> PASS igt@kms_cursor_crc@cursor-256x85-sliding: shard-apl: FAIL (fdo#103232) -> PASS +2 igt@kms_cursor_legacy@cursora-vs-flipa-toggle: shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite: shard-glk: FAIL (fdo#103167) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render: shard-apl: FAIL (fdo#103167) -> PASS +1 igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: shard-skl: FAIL (fdo#107815) -> PASS igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: shard-apl: FAIL (fdo#103166) -> PASS +2 Warnings igt@i915_suspend@shrink: shard-skl: DMESG-WARN (fdo#108784) -> INCOMPLETE (fdo#106886) igt@kms_plane_alpha_blend@pipe-c-alpha-7efc: shard-kbl: FAIL (fdo#108145, fdo#108590) -> DMESG-FAIL (fdo#108145, fdo#105602, fdo#103558) fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763 fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807 fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815 fdo#107882 https://bugs.freedesktop.org/show_bug.cgi?id=107882 fdo#108039 https://bugs.freedesktop.org/show_bug.cgi?id=108039 fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145 fdo#108147 https://bugs.freedesktop.org/show_bug.cgi?id=108147 fdo#108590
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)
== Series Details == Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev8) URL : https://patchwork.freedesktop.org/series/51878/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5174_full -> Patchwork_10868_full = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10868_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10868_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10868_full: === IGT changes === Possible regressions igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic: shard-skl: PASS -> FAIL igt@kms_cursor_legacy@nonblocking-modeset-vs-cursor-atomic: shard-apl: PASS -> FAIL Warnings igt@pm_rc6_residency@rc6-accuracy: shard-snb: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_10868_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_schedule@preempt-hang-render: shard-apl: PASS -> INCOMPLETE (fdo#103927) igt@gem_render_copy_redux@normal: shard-kbl: PASS -> INCOMPLETE (fdo#103665, fdo#106650) igt@kms_ccs@pipe-a-crc-sprite-planes-basic: shard-glk: PASS -> FAIL (fdo#108145) igt@kms_chv_cursor_fail@pipe-a-128x128-top-edge: shard-skl: NOTRUN -> FAIL (fdo#104671) +1 igt@kms_cursor_crc@cursor-256x256-suspend: shard-skl: PASS -> FAIL (fdo#103191, fdo#103232) igt@kms_cursor_crc@cursor-256x85-onscreen: shard-apl: PASS -> FAIL (fdo#103232) igt@kms_flip@2x-flip-vs-expired-vblank: shard-glk: PASS -> FAIL (fdo#105363) igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-skl: PASS -> FAIL (fdo#105363) igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc: shard-skl: NOTRUN -> FAIL (fdo#105682) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen: shard-skl: NOTRUN -> FAIL (fdo#103167) +3 igt@kms_frontbuffer_tracking@fbc-modesetfrombusy: shard-glk: PASS -> FAIL (fdo#103167) +2 igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: shard-skl: PASS -> INCOMPLETE (fdo#107773, fdo#104108) +1 igt@kms_plane@plane-position-covered-pipe-a-planes: shard-skl: NOTRUN -> FAIL (fdo#103166) igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#108145) igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: shard-skl: PASS -> FAIL (fdo#107815) igt@kms_plane_multiple@atomic-pipe-c-tiling-y: shard-apl: PASS -> FAIL (fdo#103166) igt@kms_universal_plane@universal-plane-pipe-c-functional: shard-glk: PASS -> FAIL (fdo#103166) +1 igt@perf@oa-exponents: shard-glk: PASS -> FAIL (fdo#105483) Possible fixes igt@gem_ppgtt@blt-vs-render-ctxn: shard-skl: TIMEOUT (fdo#108039) -> PASS igt@gem_pwrite@big-gtt-backwards: shard-apl: INCOMPLETE (fdo#103927) -> PASS igt@kms_cursor_crc@cursor-256x85-sliding: shard-apl: FAIL (fdo#103232) -> PASS igt@kms_cursor_legacy@cursora-vs-flipa-toggle: shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: shard-apl: FAIL (fdo#103167) -> PASS +2 shard-glk: FAIL (fdo#103167) -> PASS +1 igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: shard-skl: FAIL (fdo#107815) -> PASS igt@kms_plane_multiple@atomic-pipe-b-tiling-y: shard-glk: FAIL (fdo#103166) -> PASS +2 igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: shard-apl: FAIL (fdo#103166) -> PASS +1 igt@kms_setmode@basic: shard-hsw: FAIL (fdo#99912) -> PASS fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#104671 https://bugs.freedesktop.org/show_bug.cgi?id=104671 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105483 https://bugs.freedesktop.org/show_bug.cgi?id=105483 fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/atomic: Fix the early return in drm_atomic_set_mode_for_crtc()
== Series Details == Series: drm/atomic: Fix the early return in drm_atomic_set_mode_for_crtc() URL : https://patchwork.freedesktop.org/series/52777/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5174_full -> Patchwork_10867_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10867_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10867_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10867_full: === IGT changes === Warnings igt@pm_rc6_residency@rc6-accuracy: shard-snb: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_10867_full that come from known issues: === IGT changes === Issues hit igt@gem_softpin@noreloc-s3: shard-skl: PASS -> INCOMPLETE (fdo#104108, fdo#107773) igt@kms_cursor_crc@cursor-128x42-onscreen: shard-glk: PASS -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-256x256-suspend: shard-skl: PASS -> FAIL (fdo#103232, fdo#103191) igt@kms_cursor_crc@cursor-size-change: shard-apl: PASS -> FAIL (fdo#103232) igt@kms_fbcon_fbt@psr: shard-skl: NOTRUN -> FAIL (fdo#107882) igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#105363) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt: shard-glk: PASS -> FAIL (fdo#103167) +5 igt@kms_frontbuffer_tracking@fbcpsr-suspend: shard-skl: PASS -> INCOMPLETE (fdo#104108, fdo#106978) igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: shard-skl: PASS -> FAIL (fdo#107815) igt@kms_plane_alpha_blend@pipe-c-alpha-7efc: shard-skl: NOTRUN -> FAIL (fdo#108145, fdo#107815) +1 igt@kms_universal_plane@universal-plane-pipe-a-functional: shard-apl: PASS -> FAIL (fdo#103166) +1 igt@kms_universal_plane@universal-plane-pipe-c-functional: shard-glk: PASS -> FAIL (fdo#103166) +2 igt@perf@blocking: shard-hsw: PASS -> FAIL (fdo#102252) igt@pm_rpm@gem-mmap-cpu: shard-skl: PASS -> INCOMPLETE (fdo#107807) Possible fixes igt@drm_import_export@import-close-race-flink: shard-skl: TIMEOUT (fdo#108667) -> PASS igt@gem_pwrite@big-gtt-backwards: shard-apl: INCOMPLETE (fdo#103927) -> PASS igt@kms_cursor_crc@cursor-256x85-sliding: shard-apl: FAIL (fdo#103232) -> PASS +1 igt@kms_cursor_legacy@cursora-vs-flipa-toggle: shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: shard-glk: FAIL (fdo#103167) -> PASS igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: shard-skl: FAIL (fdo#107815) -> PASS igt@kms_plane_multiple@atomic-pipe-b-tiling-y: shard-glk: FAIL (fdo#103166) -> PASS +1 igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: shard-apl: FAIL (fdo#103166) -> PASS fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763 fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538 fdo#106978 https://bugs.freedesktop.org/show_bug.cgi?id=106978 fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773 fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807 fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815 fdo#107882 https://bugs.freedesktop.org/show_bug.cgi?id=107882 fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145 fdo#108667 https://bugs.freedesktop.org/show_bug.cgi?id=108667 == Participating hosts (7 -> 6) == Missing(1): shard-iclb == Build changes == * Linux: CI_DRM_5174 -> Patchwork_10867 CI_DRM_5174: 0bfa7192170c039a271ebc27222b4b91516e73f6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4722: fdcdfa1e220c5070072d5dac9523cd105e7406c2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10867: 3ee4095248db4aa5a00447be02bba09be878caf8 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Log test and subtest names for easier debugging
== Series Details == Series: drm/i915/selftests: Log test and subtest names for easier debugging URL : https://patchwork.freedesktop.org/series/52774/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5174_full -> Patchwork_10866_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10866_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10866_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10866_full: === IGT changes === Warnings igt@pm_rc6_residency@rc6-accuracy: shard-snb: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_10866_full that come from known issues: === IGT changes === Issues hit igt@kms_chv_cursor_fail@pipe-a-128x128-top-edge: shard-skl: NOTRUN -> FAIL (fdo#104671) +1 igt@kms_cursor_crc@cursor-256x85-onscreen: shard-apl: PASS -> FAIL (fdo#103232) +1 igt@kms_fbcon_fbt@psr: shard-skl: NOTRUN -> FAIL (fdo#107882) igt@kms_flip@plain-flip-ts-check: shard-skl: PASS -> FAIL (fdo#100368) igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc: shard-skl: NOTRUN -> FAIL (fdo#103167) +2 igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen: shard-glk: PASS -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-blt: shard-skl: NOTRUN -> FAIL (fdo#105682) igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render: shard-skl: NOTRUN -> FAIL (fdo#103167, fdo#105682) igt@kms_plane@pixel-format-pipe-c-planes: shard-glk: PASS -> FAIL (fdo#103166) igt@kms_plane@plane-position-covered-pipe-a-planes: shard-skl: NOTRUN -> FAIL (fdo#103166) igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: shard-skl: NOTRUN -> FAIL (fdo#108145, fdo#107815) +2 igt@kms_universal_plane@universal-plane-pipe-a-functional: shard-apl: PASS -> FAIL (fdo#103166) Possible fixes igt@kms_cursor_crc@cursor-256x85-sliding: shard-apl: FAIL (fdo#103232) -> PASS +1 igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic: shard-glk: FAIL (fdo#105454, fdo#106509) -> PASS igt@kms_cursor_legacy@cursora-vs-flipa-toggle: shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS igt@kms_plane_multiple@atomic-pipe-b-tiling-y: shard-glk: FAIL (fdo#103166) -> PASS igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: shard-apl: FAIL (fdo#103166) -> PASS igt@kms_setmode@basic: shard-kbl: FAIL (fdo#99912) -> PASS Warnings igt@kms_content_protection@legacy: shard-apl: FAIL (fdo#108597) -> INCOMPLETE (fdo#103927) fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104671 https://bugs.freedesktop.org/show_bug.cgi?id=104671 fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454 fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682 fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763 fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509 fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538 fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815 fdo#107882 https://bugs.freedesktop.org/show_bug.cgi?id=107882 fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145 fdo#108597 https://bugs.freedesktop.org/show_bug.cgi?id=108597 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (7 -> 6) == Missing(1): shard-iclb == Build changes == * Linux: CI_DRM_5174 -> Patchwork_10866 CI_DRM_5174: 0bfa7192170c039a271ebc27222b4b91516e73f6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4722: fdcdfa1e220c5070072d5dac9523cd105e7406c2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10866: 892a393cb77f0051624d17df57e5d53c3ca43ead @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10866/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/edid: Add CTA-861-G modes with VIC < 128
== Series Details ==
Series: series starting with [1/4] drm/edid: Add CTA-861-G modes with VIC < 128
URL : https://patchwork.freedesktop.org/series/52770/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5174_full -> Patchwork_10865_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10865_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10865_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in
Patchwork_10865_full:
=== IGT changes ===
Warnings
igt@tools_test@tools_test:
shard-hsw: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_10865_full that come from known
issues:
=== IGT changes ===
Issues hit
igt@gem_exec_reuse@baggage:
shard-apl: PASS -> INCOMPLETE (fdo#103927)
igt@i915_suspend@fence-restore-untiled:
shard-snb: PASS -> DMESG-WARN (fdo#102365)
igt@i915_suspend@shrink:
{shard-iclb}: NOTRUN -> DMESG-WARN (fdo#108784)
igt@kms_busy@extended-modeset-hang-newfb-render-b:
{shard-iclb}: NOTRUN -> DMESG-WARN (fdo#107956)
igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
{shard-iclb}: PASS -> DMESG-WARN (fdo#107956) +1
igt@kms_chv_cursor_fail@pipe-a-128x128-top-edge:
shard-skl: NOTRUN -> FAIL (fdo#104671) +1
igt@kms_cursor_crc@cursor-256x256-suspend:
shard-skl: PASS -> FAIL (fdo#103191, fdo#103232)
igt@kms_cursor_crc@cursor-64x64-suspend:
{shard-iclb}: NOTRUN -> FAIL (fdo#103232) +1
igt@kms_fbcon_fbt@psr:
shard-skl: NOTRUN -> FAIL (fdo#107882)
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-skl: PASS -> FAIL (fdo#105363)
igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc:
shard-skl: NOTRUN -> FAIL (fdo#105682) +2
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
{shard-iclb}: PASS -> FAIL (fdo#103167) +3
shard-apl: PASS -> FAIL (fdo#103167)
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
shard-glk: PASS -> FAIL (fdo#103167)
igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
shard-skl: NOTRUN -> FAIL (fdo#103167) +1
igt@kms_plane@pixel-format-pipe-b-planes:
{shard-iclb}: NOTRUN -> FAIL (fdo#103166)
igt@kms_plane@plane-position-covered-pipe-a-planes:
shard-skl: NOTRUN -> FAIL (fdo#103166)
igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
shard-skl: NOTRUN -> FAIL (fdo#108145, fdo#107815) +2
igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
shard-skl: PASS -> FAIL (fdo#107815)
igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
shard-glk: PASS -> FAIL (fdo#103166)
igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format:
{shard-iclb}: NOTRUN -> DMESG-WARN (fdo#107724)
igt@kms_psr@no_drrs:
{shard-iclb}: PASS -> FAIL (fdo#108341)
igt@kms_universal_plane@universal-plane-pipe-a-functional:
shard-apl: PASS -> FAIL (fdo#103166)
igt@pm_rpm@modeset-non-lpsp:
shard-skl: SKIP -> INCOMPLETE (fdo#107807)
igt@pm_rps@min-max-config-loaded:
{shard-iclb}: NOTRUN -> FAIL (fdo#102250)
Possible fixes
igt@drm_import_export@import-close-race-flink:
shard-skl: TIMEOUT (fdo#108667) -> PASS
igt@gem_pwrite@big-gtt-backwards:
shard-apl: INCOMPLETE (fdo#103927) -> PASS
igt@kms_cursor_crc@cursor-128x128-suspend:
shard-glk: FAIL (fdo#103232) -> PASS
igt@kms_cursor_crc@cursor-256x85-sliding:
shard-apl: FAIL (fdo#103232) -> PASS +1
igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
shard-glk: FAIL (fdo#103167) -> PASS +1
igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt:
{shard-iclb}: FAIL (fdo#103167) -> PASS +1
igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
shard-glk: FAIL (fdo#108145) -> PASS
igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
shard-skl: FAIL (fdo#107815) -> PASS
igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
shard-glk: FAIL (fdo#103166) -> PASS +1
igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
{shard-iclb}: FAIL (fdo#103166) -> PASS
igt@pm_rpm@fences:
{shard-iclb}: DMESG-WARN (fdo#108654) -> PASS
Re: [Intel-gfx] [PATCH 1/2] drm/i915/gvt: Avoid use-after-free iterating the gtt list
Sorry I missed it. Thanks for the correction!
Regards,
Henry
> -Original Message-
> From: Zhenyu Wang [mailto:zhen...@linux.intel.com]
> Sent: Wednesday, November 21, 2018 10:29 AM
> To: Chris Wilson
> Cc: intel-gfx@lists.freedesktop.org; Zhenyu Wang
> ; Yuan, Hang
> Subject: Re: [PATCH 1/2] drm/i915/gvt: Avoid use-after-free iterating the gtt
> list
>
> On 2018.11.20 20:24:38 +, Chris Wilson wrote:
> > Found by smatch:
> >
> > drivers/gpu/drm/i915/gvt/gtt.c:2452 intel_vgpu_destroy_ggtt_mm() error:
> dereferencing freed memory 'pos'
> >
> > Signed-off-by: Chris Wilson
> > Cc: Zhenyu Wang
> > ---
> > drivers/gpu/drm/i915/gvt/gtt.c | 7 ---
> > 1 file changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gvt/gtt.c
> > b/drivers/gpu/drm/i915/gvt/gtt.c index 58e166effa45..c7103dd2d8d5
> > 100644
> > --- a/drivers/gpu/drm/i915/gvt/gtt.c
> > +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> > @@ -2447,10 +2447,11 @@ static void
> > intel_vgpu_destroy_all_ppgtt_mm(struct intel_vgpu *vgpu)
> >
> > static void intel_vgpu_destroy_ggtt_mm(struct intel_vgpu *vgpu) {
> > - struct intel_gvt_partial_pte *pos;
> > + struct intel_gvt_partial_pte *pos, *next;
> >
> > - list_for_each_entry(pos,
> > - >gtt.ggtt_mm->ggtt_mm.partial_pte_list, list) {
> > + list_for_each_entry_safe(pos, next,
> > +>gtt.ggtt_mm-
> >ggtt_mm.partial_pte_list,
> > +list) {
> > gvt_dbg_mm("partial PTE update on hold 0x%lx : 0x%llx\n",
> > pos->offset, pos->data);
> > kfree(pos);
>
> Reviewed-by: Zhenyu Wang
>
> Thanks! I should really run check against each one when apply..
>
> --
> Open Source Technology Center, Intel ltd.
>
> $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/gvt: Avoid use-after-free iterating the gtt list
On 2018.11.20 20:24:38 +, Chris Wilson wrote:
> Found by smatch:
>
> drivers/gpu/drm/i915/gvt/gtt.c:2452 intel_vgpu_destroy_ggtt_mm() error:
> dereferencing freed memory 'pos'
>
> Signed-off-by: Chris Wilson
> Cc: Zhenyu Wang
> ---
> drivers/gpu/drm/i915/gvt/gtt.c | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> index 58e166effa45..c7103dd2d8d5 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.c
> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> @@ -2447,10 +2447,11 @@ static void intel_vgpu_destroy_all_ppgtt_mm(struct
> intel_vgpu *vgpu)
>
> static void intel_vgpu_destroy_ggtt_mm(struct intel_vgpu *vgpu)
> {
> - struct intel_gvt_partial_pte *pos;
> + struct intel_gvt_partial_pte *pos, *next;
>
> - list_for_each_entry(pos,
> - >gtt.ggtt_mm->ggtt_mm.partial_pte_list, list) {
> + list_for_each_entry_safe(pos, next,
> + >gtt.ggtt_mm->ggtt_mm.partial_pte_list,
> + list) {
> gvt_dbg_mm("partial PTE update on hold 0x%lx : 0x%llx\n",
> pos->offset, pos->data);
> kfree(pos);
Reviewed-by: Zhenyu Wang
Thanks! I should really run check against each one when apply..
--
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: fix spelling mistake "reserverd" -> "reserved"
== Series Details == Series: drm/i915: fix spelling mistake "reserverd" -> "reserved" URL : https://patchwork.freedesktop.org/series/52800/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5175 -> Patchwork_10873 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/52800/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10873 that come from known issues: === IGT changes === Issues hit igt@i915_selftest@live_execlists: fi-apl-guc: PASS -> INCOMPLETE (fdo#108622, fdo#103927) igt@kms_pipe_crc_basic@read-crc-pipe-b: fi-byt-clapper: PASS -> FAIL (fdo#107362) Possible fixes igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: FAIL (fdo#103167) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#108622 https://bugs.freedesktop.org/show_bug.cgi?id=108622 == Participating hosts (52 -> 46) == Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_5175 -> Patchwork_10873 CI_DRM_5175: eccbba7017aafd70e09bb105c8a6b85572a93eb8 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4723: 53bb24ad410b53cdd96f15ced8fd5921c8ab0eac @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10873: a454eb85ca0121acd2cbcd279e4fdc42047705a8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a454eb85ca01 drm/i915: fix spelling mistake "reserverd" -> "reserved" == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10873/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for DRM cgroup controller
== Series Details == Series: DRM cgroup controller URL : https://patchwork.freedesktop.org/series/52799/ State : failure == Summary == CALLscripts/checksyscalls.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_device.o In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:36:0: ./include/drm/drm_cgroup.h:28:43: warning: ‘struct drmcgrp_vendor’ declared inside parameter list will not be visible outside of this definition or declaration static int drmcgrp_register_vendor(struct drmcgrp_vendor *vendor, enum drmcgrp_vendor_id id) ^~ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c: In function ‘amdgpu_device_init’: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:2653:6: error: ‘drmcgrp_vendors’ undeclared (first use in this function); did you mean ‘drmcgrp_vendor_id’? if (drmcgrp_vendors[amd_drmcgrp_vendor_id] == NULL) ^~~ drmcgrp_vendor_id drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:2653:6: note: each undeclared identifier is reported only once for each function it appears in drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:2653:22: error: ‘amd_drmcgrp_vendor_id’ undeclared (first use in this function); did you mean ‘drmcgrp_vendor_id’? if (drmcgrp_vendors[amd_drmcgrp_vendor_id] == NULL) ^ drmcgrp_vendor_id drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:2654:28: error: ‘amd_drmcgrp_vendor’ undeclared (first use in this function); did you mean ‘amd_drmcgrp_vendor_id’? drmcgrp_register_vendor(_drmcgrp_vendor, amd_drmcgrp_vendor_id); ^~ amd_drmcgrp_vendor_id scripts/Makefile.build:293: recipe for target 'drivers/gpu/drm/amd/amdgpu/amdgpu_device.o' failed make[4]: *** [drivers/gpu/drm/amd/amdgpu/amdgpu_device.o] Error 1 scripts/Makefile.build:518: recipe for target 'drivers/gpu/drm/amd/amdgpu' failed make[3]: *** [drivers/gpu/drm/amd/amdgpu] Error 2 scripts/Makefile.build:518: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:518: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1060: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH RFC 1/5] cgroup: Introduce cgroup for drm subsystem
Change-Id: I6830d3990f63f0c13abeba29b1d330cf28882831
Signed-off-by: Kenny Ho
---
include/linux/cgroup_drm.h| 32
include/linux/cgroup_subsys.h | 4 +++
init/Kconfig | 5
kernel/cgroup/Makefile| 1 +
kernel/cgroup/drm.c | 46 +++
5 files changed, 88 insertions(+)
create mode 100644 include/linux/cgroup_drm.h
create mode 100644 kernel/cgroup/drm.c
diff --git a/include/linux/cgroup_drm.h b/include/linux/cgroup_drm.h
new file mode 100644
index ..79ab38b0f46d
--- /dev/null
+++ b/include/linux/cgroup_drm.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ */
+#ifndef _CGROUP_DRM_H
+#define _CGROUP_DRM_H
+
+#ifdef CONFIG_CGROUP_DRM
+
+#include
+
+struct drmcgrp {
+ struct cgroup_subsys_state css;
+};
+
+static inline struct drmcgrp *css_drmcgrp(struct cgroup_subsys_state *css)
+{
+ return css ? container_of(css, struct drmcgrp, css) : NULL;
+}
+
+static inline struct drmcgrp *get_drmcgrp(struct task_struct *task)
+{
+ return css_drmcgrp(task_get_css(task, drm_cgrp_id));
+}
+
+
+static inline struct drmcgrp *parent_drmcgrp(struct drmcgrp *cg)
+{
+ return css_drmcgrp(cg->css.parent);
+}
+
+#endif /* CONFIG_CGROUP_DRM */
+#endif /* _CGROUP_DRM_H */
diff --git a/include/linux/cgroup_subsys.h b/include/linux/cgroup_subsys.h
index acb77dcff3b4..ddedad809e8b 100644
--- a/include/linux/cgroup_subsys.h
+++ b/include/linux/cgroup_subsys.h
@@ -61,6 +61,10 @@ SUBSYS(pids)
SUBSYS(rdma)
#endif
+#if IS_ENABLED(CONFIG_CGROUP_DRM)
+SUBSYS(drm)
+#endif
+
/*
* The following subsystems are not supported on the default hierarchy.
*/
diff --git a/init/Kconfig b/init/Kconfig
index a4112e95724a..bee1e164443a 100644
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -836,6 +836,11 @@ config CGROUP_RDMA
Attaching processes with active RDMA resources to the cgroup
hierarchy is allowed even if can cross the hierarchy's limit.
+config CGROUP_DRM
+ bool "DRM controller (EXPERIMENTAL)"
+ help
+ Provides accounting and enforcement of resources in the DRM subsystem.
+
config CGROUP_FREEZER
bool "Freezer controller"
help
diff --git a/kernel/cgroup/Makefile b/kernel/cgroup/Makefile
index bfcdae896122..6af14bd93050 100644
--- a/kernel/cgroup/Makefile
+++ b/kernel/cgroup/Makefile
@@ -4,5 +4,6 @@ obj-y := cgroup.o rstat.o namespace.o cgroup-v1.o
obj-$(CONFIG_CGROUP_FREEZER) += freezer.o
obj-$(CONFIG_CGROUP_PIDS) += pids.o
obj-$(CONFIG_CGROUP_RDMA) += rdma.o
+obj-$(CONFIG_CGROUP_DRM) += drm.o
obj-$(CONFIG_CPUSETS) += cpuset.o
obj-$(CONFIG_CGROUP_DEBUG) += debug.o
diff --git a/kernel/cgroup/drm.c b/kernel/cgroup/drm.c
new file mode 100644
index ..d9e194b9aead
--- /dev/null
+++ b/kernel/cgroup/drm.c
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: MIT
+// Copyright 2018 Advanced Micro Devices, Inc.
+#include
+#include
+#include
+
+static u64 drmcgrp_test_read(struct cgroup_subsys_state *css,
+ struct cftype *cft)
+{
+ return 88;
+}
+
+static void drmcgrp_css_free(struct cgroup_subsys_state *css)
+{
+ struct drmcgrp *drmcgrp = css_drmcgrp(css);
+
+ kfree(css_drmcgrp(css));
+}
+
+static struct cgroup_subsys_state *
+drmcgrp_css_alloc(struct cgroup_subsys_state *parent_css)
+{
+ struct drmcgrp *drmcgrp;
+
+ drmcgrp = kzalloc(sizeof(struct drmcgrp), GFP_KERNEL);
+ if (!drmcgrp)
+ return ERR_PTR(-ENOMEM);
+
+ return >css;
+}
+
+struct cftype files[] = {
+ {
+ .name = "drm_test",
+ .read_u64 = drmcgrp_test_read,
+ },
+ { } /* terminate */
+};
+
+struct cgroup_subsys drm_cgrp_subsys = {
+ .css_alloc = drmcgrp_css_alloc,
+ .css_free = drmcgrp_css_free,
+ .early_init = false,
+ .legacy_cftypes = files,
+ .dfl_cftypes= files,
+};
--
2.19.1
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[Intel-gfx] [PATCH RFC 4/5] drm/amdgpu: Add accounting of command submission via DRM cgroup
Account for the number of command submitted to amdgpu by type on a per
cgroup basis, for the purpose of profiling/monitoring applications.
x prefix in the control file name x.cmd_submitted.amd.stat signify
experimental.
Change-Id: Ibc22e5bda600f54fe820fe0af5400ca348691550
Signed-off-by: Kenny Ho
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c | 54 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h | 5 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c| 15 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h| 5 +-
5 files changed, 83 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 663043c8f0f5..b448160aed89 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -33,6 +33,7 @@
#include "amdgpu_trace.h"
#include "amdgpu_gmc.h"
#include "amdgpu_gem.h"
+#include "amdgpu_drmcgrp.h"
static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
struct drm_amdgpu_cs_chunk_fence *data,
@@ -1275,6 +1276,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
union drm_amdgpu_cs *cs = data;
struct amdgpu_cs_parser parser = {};
bool reserved_buffers = false;
+ struct amdgpu_ring *ring;
int i, r;
if (!adev->accel_working)
@@ -1317,6 +1319,9 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
if (r)
goto out;
+ ring = to_amdgpu_ring(parser.entity->rq->sched);
+ amdgpu_drmcgrp_count_cs(current, dev, ring->funcs->type);
+
r = amdgpu_cs_submit(, cs);
out:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c
index ed8aac17769c..853b77532428 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c
@@ -1,11 +1,65 @@
// SPDX-License-Identifier: MIT
// Copyright 2018 Advanced Micro Devices, Inc.
#include
+#include
#include
#include
+#include "amdgpu_ring.h"
#include "amdgpu_drmcgrp.h"
+void amdgpu_drmcgrp_count_cs(struct task_struct *task, struct drm_device *dev,
+ enum amdgpu_ring_type r_type)
+{
+ struct drmcgrp *drmcgrp = get_drmcgrp(task);
+ struct drmcgrp_device_resource *ddr;
+ struct drmcgrp *p;
+ struct amd_drmcgrp_dev_resource *a_ddr;
+
+ if (drmcgrp == NULL)
+ return;
+
+ ddr = drmcgrp->dev_resources[dev->primary->index];
+
+ mutex_lock(>ddev->mutex);
+ for (p = drmcgrp; p != NULL; p = parent_drmcgrp(drmcgrp)) {
+ a_ddr = ddr_amdddr(p->dev_resources[dev->primary->index]);
+
+ a_ddr->cs_count[r_type]++;
+ }
+ mutex_unlock(>ddev->mutex);
+}
+
+int amd_drmcgrp_cmd_submit_accounting_read(struct seq_file *sf, void *v)
+{
+ struct drmcgrp *drmcgrp = css_drmcgrp(seq_css(sf));
+ struct drmcgrp_device_resource *ddr = NULL;
+ struct amd_drmcgrp_dev_resource *a_ddr = NULL;
+ int i, j;
+
+ seq_puts(sf, "---\n");
+ for (i = 0; i < MAX_DRM_DEV; i++) {
+ ddr = drmcgrp->dev_resources[i];
+
+ if (ddr == NULL || ddr->ddev->vid != amd_drmcgrp_vendor_id)
+ continue;
+
+ a_ddr = ddr_amdddr(ddr);
+
+ seq_printf(sf, "card%d:\n", i);
+ for (j = 0; j < __MAX_AMDGPU_RING_TYPE; j++)
+ seq_printf(sf, " %s: %llu\n", amdgpu_ring_names[j],
a_ddr->cs_count[j]);
+ }
+
+ return 0;
+}
+
+
struct cftype files[] = {
+ {
+ .name = "x.cmd_submitted.amd.stat",
+ .seq_show = amd_drmcgrp_cmd_submit_accounting_read,
+ .flags = CFTYPE_NOT_ON_ROOT,
+ },
{ } /* terminate */
};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h
index e2934b7a49f5..f894a9a1059f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h
@@ -5,12 +5,17 @@
#define _AMDGPU_DRMCGRP_H
#include
+#include "amdgpu_ring.h"
/* for AMD specific DRM resources */
struct amd_drmcgrp_dev_resource {
struct drmcgrp_device_resource ddr;
+ u64 cs_count[__MAX_AMDGPU_RING_TYPE];
};
+void amdgpu_drmcgrp_count_cs(struct task_struct *task, struct drm_device *dev,
+ enum amdgpu_ring_type r_type);
+
static inline struct amd_drmcgrp_dev_resource *ddr_amdddr(struct
drmcgrp_device_resource *ddr)
{
return ddr ? container_of(ddr, struct amd_drmcgrp_dev_resource, ddr) :
NULL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index b70e85ec147d..1606f84d2334 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -34,6
[Intel-gfx] [PATCH RFC 3/5] drm/amdgpu: Add DRM cgroup support for AMD devices
Change-Id: Ib66c44ac1b1c367659e362a2fc05b6fbb3805876
Signed-off-by: Kenny Ho
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7
drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c | 37 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h | 19 +++
include/drm/drmcgrp_vendors.h | 1 +
5 files changed, 67 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 138cb787d27e..5cf8048f2d75 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -186,4 +186,7 @@ amdgpu-y += $(AMD_DISPLAY_FILES)
endif
+#DRM cgroup controller
+amdgpu-y += amdgpu_drmcgrp.o
+
obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 30bc345d6fdf..ad0373f83ed3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -33,6 +33,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -2645,6 +2646,12 @@ int amdgpu_device_init(struct amdgpu_device *adev,
goto failed;
}
+ /* TODO:docs */
+ if (drmcgrp_vendors[amd_drmcgrp_vendor_id] == NULL)
+ drmcgrp_register_vendor(_drmcgrp_vendor,
amd_drmcgrp_vendor_id);
+
+ drmcgrp_register_device(adev->ddev, amd_drmcgrp_vendor_id);
+
return 0;
failed:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c
new file mode 100644
index ..ed8aac17769c
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: MIT
+// Copyright 2018 Advanced Micro Devices, Inc.
+#include
+#include
+#include
+#include "amdgpu_drmcgrp.h"
+
+struct cftype files[] = {
+ { } /* terminate */
+};
+
+struct cftype *drmcgrp_amd_get_cftypes(void)
+{
+ return files;
+}
+
+struct drmcgrp_device_resource *amd_drmcgrp_alloc_dev_resource(void)
+{
+ struct amd_drmcgrp_dev_resource *a_ddr;
+
+ a_ddr = kzalloc(sizeof(struct amd_drmcgrp_dev_resource), GFP_KERNEL);
+ if (!a_ddr)
+ return ERR_PTR(-ENOMEM);
+
+ return _ddr->ddr;
+}
+
+void amd_drmcgrp_free_dev_resource(struct drmcgrp_device_resource *ddr)
+{
+ kfree(ddr_amdddr(ddr));
+}
+
+struct drmcgrp_vendor amd_drmcgrp_vendor = {
+ .get_cftypes = drmcgrp_amd_get_cftypes,
+ .alloc_dev_resource = amd_drmcgrp_alloc_dev_resource,
+ .free_dev_resource = amd_drmcgrp_free_dev_resource,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h
new file mode 100644
index ..e2934b7a49f5
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ */
+#ifndef _AMDGPU_DRMCGRP_H
+#define _AMDGPU_DRMCGRP_H
+
+#include
+
+/* for AMD specific DRM resources */
+struct amd_drmcgrp_dev_resource {
+ struct drmcgrp_device_resource ddr;
+};
+
+static inline struct amd_drmcgrp_dev_resource *ddr_amdddr(struct
drmcgrp_device_resource *ddr)
+{
+ return ddr ? container_of(ddr, struct amd_drmcgrp_dev_resource, ddr) :
NULL;
+}
+
+#endif /* _AMDGPU_DRMCGRP_H */
diff --git a/include/drm/drmcgrp_vendors.h b/include/drm/drmcgrp_vendors.h
index b04d8649851b..6cfbf1825344 100644
--- a/include/drm/drmcgrp_vendors.h
+++ b/include/drm/drmcgrp_vendors.h
@@ -3,5 +3,6 @@
*/
#if IS_ENABLED(CONFIG_CGROUP_DRM)
+DRMCGRP_VENDOR(amd)
#endif
--
2.19.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH RFC 2/5] cgroup: Add mechanism to register vendor specific DRM devices
Hi Tejun, Thanks for the reply. A few clarifying questions: On Tue, Nov 20, 2018 at 3:21 PM Tejun Heo wrote: > So, I'm still pretty negative about adding drm controller at this > point. There isn't enough of common resource model defined yet and > until that gets sorted out I think it's in the best interest of > everyone involved to keep it inside drm or specific driver proper. By this reply, are you suggesting that vendor specific resources will never be acceptable to be managed under cgroup? Let say a user want to have similar functionality as what cgroup is offering but to manage vendor specific resources, what would you suggest as a solution? When you say keeping vendor specific resource regulation inside drm or specific drivers, do you mean we should replicate the cgroup infrastructure there or do you mean either drm or specific driver should query existing hierarchy (such as device or perhaps cpu) for the process organization information? To put the questions in more concrete terms, let say a user wants to expose certain part of a gpu to a particular cgroup similar to the way selective cpu cores are exposed to a cgroup via cpuset, how should we go about enabling such functionality? Regards, Kenny ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH RFC 2/5] cgroup: Add mechanism to register vendor specific DRM devices
Since many parts of the DRM subsystem has vendor-specific
implementations, we introduce mechanisms for vendor to register their
specific resources and control files to the DRM cgroup subsystem. A
vendor will register itself with the DRM cgroup subsystem first before
registering individual DRM devices to the cgroup subsystem.
In addition to the cgroup_subsys_state that is common to all DRM
devices, a device-specific state is introduced and it is allocated
according to the vendor of the device.
Change-Id: I908ee6975ea0585e4c30eafde4599f87094d8c65
Signed-off-by: Kenny Ho
---
include/drm/drm_cgroup.h | 39
include/drm/drmcgrp_vendors.h | 7 +++
include/linux/cgroup_drm.h| 26 +++
kernel/cgroup/drm.c | 84 +++
4 files changed, 156 insertions(+)
create mode 100644 include/drm/drm_cgroup.h
create mode 100644 include/drm/drmcgrp_vendors.h
diff --git a/include/drm/drm_cgroup.h b/include/drm/drm_cgroup.h
new file mode 100644
index ..26cbea7059a6
--- /dev/null
+++ b/include/drm/drm_cgroup.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ */
+#ifndef __DRM_CGROUP_H__
+#define __DRM_CGROUP_H__
+
+#define DRMCGRP_VENDOR(_x) _x ## _drmcgrp_vendor_id,
+enum drmcgrp_vendor_id {
+#include
+ DRMCGRP_VENDOR_COUNT,
+};
+#undef DRMCGRP_VENDOR
+
+#define DRMCGRP_VENDOR(_x) extern struct drmcgrp_vendor _x ## _drmcgrp_vendor;
+#include
+#undef DRMCGRP_VENDOR
+
+
+
+#ifdef CONFIG_CGROUP_DRM
+
+extern struct drmcgrp_vendor *drmcgrp_vendors[];
+
+int drmcgrp_register_vendor(struct drmcgrp_vendor *vendor, enum
drmcgrp_vendor_id id);
+int drmcgrp_register_device(struct drm_device *device, enum drmcgrp_vendor_id
id);
+
+#else
+static int drmcgrp_register_vendor(struct drmcgrp_vendor *vendor, enum
drmcgrp_vendor_id id)
+{
+ return 0;
+}
+
+static int drmcgrp_register_device(struct drm_device *device, enum
drmcgrp_vendor_id id)
+{
+ return 0;
+}
+
+#endif /* CONFIG_CGROUP_DRM */
+#endif /* __DRM_CGROUP_H__ */
diff --git a/include/drm/drmcgrp_vendors.h b/include/drm/drmcgrp_vendors.h
new file mode 100644
index ..b04d8649851b
--- /dev/null
+++ b/include/drm/drmcgrp_vendors.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ */
+#if IS_ENABLED(CONFIG_CGROUP_DRM)
+
+
+#endif
diff --git a/include/linux/cgroup_drm.h b/include/linux/cgroup_drm.h
index 79ab38b0f46d..a776662d9593 100644
--- a/include/linux/cgroup_drm.h
+++ b/include/linux/cgroup_drm.h
@@ -6,10 +6,36 @@
#ifdef CONFIG_CGROUP_DRM
+#include
#include
+#include
+#include
+
+/* limit defined per the way drm_minor_alloc operates */
+#define MAX_DRM_DEV (64 * DRM_MINOR_RENDER)
+
+struct drmcgrp_device {
+ enum drmcgrp_vendor_id vid;
+ struct drm_device *dev;
+ struct mutexmutex;
+};
+
+/* vendor-common resource counting goes here */
+/* this struct should be included in the vendor specific resource */
+struct drmcgrp_device_resource {
+ struct drmcgrp_device *ddev;
+};
+
+struct drmcgrp_vendor {
+ struct cftype *(*get_cftypes)(void);
+ struct drmcgrp_device_resource *(*alloc_dev_resource)(void);
+ void (*free_dev_resource)(struct drmcgrp_device_resource *dev_resource);
+};
+
struct drmcgrp {
struct cgroup_subsys_state css;
+ struct drmcgrp_device_resource *dev_resources[MAX_DRM_DEV];
};
static inline struct drmcgrp *css_drmcgrp(struct cgroup_subsys_state *css)
diff --git a/kernel/cgroup/drm.c b/kernel/cgroup/drm.c
index d9e194b9aead..f9630cc389bc 100644
--- a/kernel/cgroup/drm.c
+++ b/kernel/cgroup/drm.c
@@ -1,8 +1,30 @@
// SPDX-License-Identifier: MIT
// Copyright 2018 Advanced Micro Devices, Inc.
+#include
#include
#include
+#include
+#include
+#include
#include
+#include
+#include
+
+/* generate an array of drm cgroup vendor pointers */
+#define DRMCGRP_VENDOR(_x)[_x ## _drmcgrp_vendor_id] = NULL,
+struct drmcgrp_vendor *drmcgrp_vendors[] = {
+#include
+};
+#undef DRMCGRP_VENDOR
+EXPORT_SYMBOL(drmcgrp_vendors);
+
+static DEFINE_MUTEX(drmcgrp_mutex);
+
+/* indexed by drm_minor for access speed */
+static struct drmcgrp_device *known_drmcgrp_devs[MAX_DRM_DEV];
+
+static int max_minor;
+
static u64 drmcgrp_test_read(struct cgroup_subsys_state *css,
struct cftype *cft)
@@ -13,6 +35,12 @@ static u64 drmcgrp_test_read(struct cgroup_subsys_state *css,
static void drmcgrp_css_free(struct cgroup_subsys_state *css)
{
struct drmcgrp *drmcgrp = css_drmcgrp(css);
+ int i;
+
+ for (i = 0; i <= max_minor; i++) {
+ if (drmcgrp->dev_resources[i] != NULL)
+
drmcgrp_vendors[known_drmcgrp_devs[i]->vid]->free_dev_resource(drmcgrp->dev_resources[i]);
+ }
kfree(css_drmcgrp(css));
}
@@ -21,11 +49,27 @@ static struct cgroup_subsys_state *
[Intel-gfx] [PATCH RFC 0/5] DRM cgroup controller
The purpose of this patch series is to start a discussion for a generic cgroup controller for the drm subsystem. The design proposed here is a very early one. We are hoping to engage the community as we develop the idea. Backgrounds == Control Groups/cgroup provide a mechanism for aggregating/partitioning sets of tasks, and all their future children, into hierarchical groups with specialized behaviour, such as accounting/limiting the resources which processes in a cgroup can access[1]. Weights, limits, protections, allocations are the main resource distribution models. Existing cgroup controllers includes cpu, memory, io, rdma, and more. cgroup is one of the foundational technologies that enables the popular container application deployment and management method. Direct Rendering Manager/drm contains code intended to support the needs of complex graphics devices. Graphics drivers in the kernel may make use of DRM functions to make tasks like memory management, interrupt handling and DMA easier, and provide a uniform interface to applications. The DRM has also developed beyond traditional graphics applications to support compute/GPGPU applications. Motivations = As GPU grow beyond the realm of desktop/workstation graphics into areas like data center clusters and IoT, there are increasing needs to monitor and regulate GPU as a resource like cpu, memory and io. Matt Roper from Intel began working on similar idea in early 2018 [2] for the purpose of managing GPU priority using the cgroup hierarchy. While that particular use case may not warrant a standalone drm cgroup controller, there are other use cases where having one can be useful [3]. Monitoring GPU resources such as VRAM and buffers, CU (compute unit [AMD's nomenclature])/EU (execution unit [Intel's nomenclature]), GPU job scheduling [4] can help sysadmins get a better understanding of the applications usage profile. Further usage regulations of the aforementioned resources can also help sysadmins optimize workload deployment on limited GPU resources. With the increased importance of machine learning, data science and other cloud-based applications, GPUs are already in production use in data centers today [5,6,7]. Existing GPU resource management is very course grain, however, as sysadmins are only able to distribute workload on a per-GPU basis [8]. An alternative is to use GPU virtualization (with or without SRIOV) but it generally acts on the entire GPU instead of the specific resources in a GPU. With a drm cgroup controller, we can enable alternate, fine-grain, sub-GPU resource management (in addition to what may be available via GPU virtualization.) In addition to production use, the DRM cgroup can also help with testing graphics application robustness by providing a mean to artificially limit DRM resources availble to the applications. Challenges While there are common infrastructure in DRM that is shared across many vendors (the scheduler [4] for example), there are also aspects of DRM that are vendor specific. To accommodate this, we borrowed the mechanism used by the cgroup to handle different kinds of cgroup controller. Resources for DRM are also often device (GPU) specific instead of system specific and a system may contain more than one GPU. For this, we borrowed some of the ideas from RDMA cgroup controller. Approach === To experiment with the idea of a DRM cgroup, we would like to start with basic accounting and statistics, then continue to iterate and add regulating mechanisms into the driver. [1] https://www.kernel.org/doc/Documentation/cgroup-v1/cgroups.txt [2] https://lists.freedesktop.org/archives/intel-gfx/2018-January/153156.html [3] https://www.spinics.net/lists/cgroups/msg20720.html [4] https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/scheduler [5] https://kubernetes.io/docs/tasks/manage-gpus/scheduling-gpus/ [6] https://blog.openshift.com/gpu-accelerated-sql-queries-with-postgresql-pg-strom-in-openshift-3-10/ [7] https://github.com/RadeonOpenCompute/k8s-device-plugin [8] https://github.com/kubernetes/kubernetes/issues/52757 Kenny Ho (5): cgroup: Introduce cgroup for drm subsystem cgroup: Add mechanism to register vendor specific DRM devices drm/amdgpu: Add DRM cgroup support for AMD devices drm/amdgpu: Add accounting of command submission via DRM cgroup drm/amdgpu: Add accounting of buffer object creation request via DRM cgroup drivers/gpu/drm/amd/amdgpu/Makefile | 3 + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 + drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c | 147 drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h | 27 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 13 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c| 15 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h| 5 +- include/drm/drm_cgroup.h| 39 ++
[Intel-gfx] [PATCH] drm/i915: fix spelling mistake "reserverd" -> "reserved"
Fix a spelling mistake in a comment.
Signed-off-by: Alexandre Belloni
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index f9ce35da4123..742f8ff101e4 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4280,7 +4280,7 @@ static void gen10_sseu_device_status(struct
drm_i915_private *dev_priv,
for (s = 0; s < info->sseu.max_slices; s++) {
/*
* FIXME: Valid SS Mask respects the spec and read
-* only valid bits for those registers, excluding reserverd
+* only valid bits for those registers, excluding reserved
* although this seems wrong because it would leave many
* subslices without ACK.
*/
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH RFC 5/5] drm/amdgpu: Add accounting of buffer object creation request via DRM cgroup
Account for the total size of buffer object requested to amdgpu by
buffer type on a per cgroup basis.
x prefix in the control file name x.bo_requested.amd.stat signify
experimental.
Change-Id: Ifb680c4bcf3652879a7a659510e25680c2465cf6
Signed-off-by: Kenny Ho
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c | 56 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h | 3 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 13 +
include/uapi/drm/amdgpu_drm.h | 24 ++---
4 files changed, 90 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c
index 853b77532428..e3d98ed01b79 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c
@@ -7,6 +7,57 @@
#include "amdgpu_ring.h"
#include "amdgpu_drmcgrp.h"
+void amdgpu_drmcgrp_count_bo_req(struct task_struct *task, struct drm_device
*dev,
+ u32 domain, unsigned long size)
+{
+ struct drmcgrp *drmcgrp = get_drmcgrp(task);
+ struct drmcgrp_device_resource *ddr;
+ struct drmcgrp *p;
+ struct amd_drmcgrp_dev_resource *a_ddr;
+int i;
+
+ if (drmcgrp == NULL)
+ return;
+
+ ddr = drmcgrp->dev_resources[dev->primary->index];
+
+ mutex_lock(>ddev->mutex);
+ for (p = drmcgrp; p != NULL; p = parent_drmcgrp(drmcgrp)) {
+ a_ddr = ddr_amdddr(p->dev_resources[dev->primary->index]);
+
+ for (i = 0; i < __MAX_AMDGPU_MEM_DOMAIN; i++)
+ if ( (1 << i) & domain)
+ a_ddr->bo_req_count[i] += size;
+ }
+ mutex_unlock(>ddev->mutex);
+}
+
+int amd_drmcgrp_bo_req_stat_read(struct seq_file *sf, void *v)
+{
+ struct drmcgrp *drmcgrp = css_drmcgrp(seq_css(sf));
+ struct drmcgrp_device_resource *ddr = NULL;
+ struct amd_drmcgrp_dev_resource *a_ddr = NULL;
+ int i, j;
+
+ seq_puts(sf, "---\n");
+ for (i = 0; i < MAX_DRM_DEV; i++) {
+ ddr = drmcgrp->dev_resources[i];
+
+ if (ddr == NULL || ddr->ddev->vid != amd_drmcgrp_vendor_id)
+ continue;
+
+ a_ddr = ddr_amdddr(ddr);
+
+ seq_printf(sf, "card%d:\n", i);
+ for (j = 0; j < __MAX_AMDGPU_MEM_DOMAIN; j++)
+ seq_printf(sf, " %s: %llu\n",
amdgpu_mem_domain_names[j], a_ddr->bo_req_count[j]);
+ }
+
+ return 0;
+}
+
+
+
void amdgpu_drmcgrp_count_cs(struct task_struct *task, struct drm_device *dev,
enum amdgpu_ring_type r_type)
{
@@ -55,6 +106,11 @@ int amd_drmcgrp_cmd_submit_accounting_read(struct seq_file
*sf, void *v)
struct cftype files[] = {
+ {
+ .name = "x.bo_requested.amd.stat",
+ .seq_show = amd_drmcgrp_bo_req_stat_read,
+ .flags = CFTYPE_NOT_ON_ROOT,
+ },
{
.name = "x.cmd_submitted.amd.stat",
.seq_show = amd_drmcgrp_cmd_submit_accounting_read,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h
index f894a9a1059f..8b9d61e47dde 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.h
@@ -11,10 +11,13 @@
struct amd_drmcgrp_dev_resource {
struct drmcgrp_device_resource ddr;
u64 cs_count[__MAX_AMDGPU_RING_TYPE];
+ u64 bo_req_count[__MAX_AMDGPU_MEM_DOMAIN];
};
void amdgpu_drmcgrp_count_cs(struct task_struct *task, struct drm_device *dev,
enum amdgpu_ring_type r_type);
+void amdgpu_drmcgrp_count_bo_req(struct task_struct *task, struct drm_device
*dev,
+ u32 domain, unsigned long size);
static inline struct amd_drmcgrp_dev_resource *ddr_amdddr(struct
drmcgrp_device_resource *ddr)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 7b3d1ebda9df..339e1d3edad8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -31,6 +31,17 @@
#include
#include "amdgpu.h"
#include "amdgpu_display.h"
+#include "amdgpu_drmcgrp.h"
+
+char const *amdgpu_mem_domain_names[] = {
+ [AMDGPU_MEM_DOMAIN_CPU] = "cpu",
+ [AMDGPU_MEM_DOMAIN_GTT] = "gtt",
+ [AMDGPU_MEM_DOMAIN_VRAM]= "vram",
+ [AMDGPU_MEM_DOMAIN_GDS] = "gds",
+ [AMDGPU_MEM_DOMAIN_GWS] = "gws",
+ [AMDGPU_MEM_DOMAIN_OA] = "oa",
+ [__MAX_AMDGPU_MEM_DOMAIN] = "_max"
+};
void amdgpu_gem_object_free(struct drm_gem_object *gobj)
{
@@ -52,6 +63,8 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev,
unsigned long size,
struct amdgpu_bo_param bp;
int r;
+ amdgpu_drmcgrp_count_bo_req(current, adev->ddev, initial_domain, size);
+
memset(, 0, sizeof(bp));
*obj = NULL;
/* At least align on page
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Synchronize hpd work in i915_hpd_storm_ctl_show()
== Series Details == Series: drm/i915: Synchronize hpd work in i915_hpd_storm_ctl_show() URL : https://patchwork.freedesktop.org/series/52796/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5175 -> Patchwork_10872 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/52796/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10872 that come from known issues: === IGT changes === Issues hit igt@gem_ctx_create@basic-files: fi-icl-u2: PASS -> DMESG-WARN (fdo#107724) igt@i915_selftest@live_contexts: fi-bsw-n3050: PASS -> DMESG-FAIL (fdo#108656, fdo#108626) igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) Possible fixes igt@gem_exec_suspend@basic-s3: fi-icl-u2: DMESG-WARN (fdo#107724) -> PASS igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: FAIL (fdo#103167) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724 fdo#108626 https://bugs.freedesktop.org/show_bug.cgi?id=108626 fdo#108656 https://bugs.freedesktop.org/show_bug.cgi?id=108656 == Participating hosts (52 -> 46) == Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_5175 -> Patchwork_10872 CI_DRM_5175: eccbba7017aafd70e09bb105c8a6b85572a93eb8 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4723: 53bb24ad410b53cdd96f15ced8fd5921c8ab0eac @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10872: 00564e2ed50a0457edc524714a6879c2c5d3a976 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 00564e2ed50a drm/i915: Synchronize hpd work in i915_hpd_storm_ctl_show() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10872/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: Enable fastset for non-boot modesets.
== Series Details ==
Series: series starting with [1/2] drm/i915: Enable fastset for non-boot
modesets.
URL : https://patchwork.freedesktop.org/series/52758/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5174_full -> Patchwork_10863_full =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10863_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10863_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in
Patchwork_10863_full:
=== IGT changes ===
Possible regressions
igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
{shard-iclb}: PASS -> DMESG-WARN +1
igt@kms_rotation_crc@sprite-rotation-90:
shard-skl: PASS -> DMESG-WARN +2
shard-kbl: PASS -> DMESG-WARN
{igt@runner@aborted}:
shard-kbl: NOTRUN -> FAIL
shard-skl: NOTRUN -> ( 3 FAIL )
Warnings
igt@pm_rc6_residency@rc6-accuracy:
shard-snb: SKIP -> PASS
{igt@runner@aborted}:
{shard-iclb}: FAIL -> ( 2 FAIL )
== Known issues ==
Here are the changes found in Patchwork_10863_full that come from known
issues:
=== IGT changes ===
Issues hit
igt@i915_suspend@shrink:
{shard-iclb}: NOTRUN -> DMESG-WARN (fdo#108784)
igt@kms_busy@extended-modeset-hang-newfb-render-b:
{shard-iclb}: NOTRUN -> DMESG-WARN (fdo#107956)
igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
{shard-iclb}: PASS -> DMESG-WARN (fdo#107956) +1
igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
shard-glk: PASS -> FAIL (fdo#108145)
igt@kms_chv_cursor_fail@pipe-a-128x128-top-edge:
shard-skl: NOTRUN -> FAIL (fdo#104671) +1
igt@kms_cursor_crc@cursor-128x128-random:
shard-glk: PASS -> FAIL (fdo#103232)
igt@kms_cursor_crc@cursor-64x64-suspend:
{shard-iclb}: NOTRUN -> FAIL (fdo#103232) +1
igt@kms_fbcon_fbt@psr:
shard-skl: NOTRUN -> FAIL (fdo#107882)
igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc:
shard-skl: NOTRUN -> FAIL (fdo#105682)
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
{shard-iclb}: PASS -> FAIL (fdo#103167) +3
shard-apl: PASS -> FAIL (fdo#103167)
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
shard-skl: NOTRUN -> FAIL (fdo#103167) +3
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite:
shard-glk: PASS -> FAIL (fdo#103167) +2
igt@kms_plane@pixel-format-pipe-b-planes:
{shard-iclb}: NOTRUN -> FAIL (fdo#103166)
igt@kms_plane@pixel-format-pipe-c-planes:
shard-glk: PASS -> FAIL (fdo#103166)
igt@kms_plane@plane-position-covered-pipe-a-planes:
shard-skl: NOTRUN -> FAIL (fdo#103166)
igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#108145) +2
igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
{shard-iclb}: PASS -> FAIL (fdo#103166)
igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
shard-apl: PASS -> FAIL (fdo#103166) +1
igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format:
{shard-iclb}: NOTRUN -> DMESG-WARN (fdo#107724)
igt@pm_rpm@reg-read-ioctl:
shard-skl: PASS -> INCOMPLETE (fdo#107807)
igt@pm_rps@min-max-config-loaded:
{shard-iclb}: NOTRUN -> FAIL (fdo#102250)
Possible fixes
igt@gem_pwrite@big-gtt-backwards:
shard-apl: INCOMPLETE (fdo#103927) -> PASS
igt@kms_busy@extended-pageflip-hang-newfb-render-b:
shard-apl: DMESG-WARN (fdo#107956) -> PASS
igt@kms_color@pipe-a-ctm-max:
shard-apl: FAIL (fdo#108147) -> PASS
igt@kms_color@pipe-c-legacy-gamma:
shard-apl: FAIL (fdo#104782) -> PASS
igt@kms_cursor_crc@cursor-128x128-onscreen:
shard-apl: FAIL (fdo#103232) -> PASS +1
igt@kms_cursor_crc@cursor-128x128-suspend:
shard-glk: FAIL (fdo#103232) -> PASS
igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
shard-glk: FAIL (fdo#103167) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
shard-apl: FAIL (fdo#103167) -> PASS +1
igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc:
{shard-iclb}: FAIL (fdo#103167) -> PASS
Re: [Intel-gfx] [PATCH v2 10/13] drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+
On Wed, Nov 14, 2018 at 11:07:26PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On SKL+ the plane WM/BUF_CFG registers are a proper part of each
> plane's register set. That means accessing them will cancel any
> pending plane update, and we would need a PLANE_SURF register write
> to arm the wm/ddb change as well.
>
> To avoid all the problems with that let's just move the wm/ddb
> programming into the plane update/disable hooks. Now all plane
> registers get written in one (hopefully atomic) operation.
>
> To make that feasible we'll move the plane ddb tracking into
> the crtc state. Watermarks were already tracked there.
>
> v2: Rebase due to input CSC
> v3: Split out a bunch of junk (Matt)
>
> Cc: Matt Roper
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 21 +-
> drivers/gpu/drm/i915/i915_drv.h | 3 -
> drivers/gpu/drm/i915/intel_display.c | 16 +-
> drivers/gpu/drm/i915/intel_display.h | 11 +-
> drivers/gpu/drm/i915/intel_drv.h | 9 +
> drivers/gpu/drm/i915/intel_pm.c | 317 ---
> drivers/gpu/drm/i915/intel_sprite.c | 4 +
> 7 files changed, 181 insertions(+), 200 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 670db5073d70..f8b2200947cf 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3437,31 +3437,32 @@ static int i915_ddb_info(struct seq_file *m, void
> *unused)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> struct drm_device *dev = _priv->drm;
> - struct skl_ddb_allocation *ddb;
> struct skl_ddb_entry *entry;
> - enum pipe pipe;
> - int plane;
> + struct intel_crtc *crtc;
>
> if (INTEL_GEN(dev_priv) < 9)
> return -ENODEV;
>
> drm_modeset_lock_all(dev);
>
> - ddb = _priv->wm.skl_hw.ddb;
> -
> seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
>
> - for_each_pipe(dev_priv, pipe) {
> + for_each_intel_crtc(_priv->drm, crtc) {
> + struct intel_crtc_state *crtc_state =
> + to_intel_crtc_state(crtc->base.state);
> + enum pipe pipe = crtc->pipe;
> + enum plane_id plane_id;
> +
> seq_printf(m, "Pipe %c\n", pipe_name(pipe));
>
> - for_each_universal_plane(dev_priv, pipe, plane) {
> - entry = >plane[pipe][plane];
> - seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
> + for_each_plane_id_on_crtc(crtc, plane_id) {
> + entry = _state->wm.skl.plane_ddb_y[plane_id];
> + seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane_id + 1,
> entry->start, entry->end,
> skl_ddb_entry_size(entry));
> }
>
> - entry = >plane[pipe][PLANE_CURSOR];
> + entry = _state->wm.skl.plane_ddb_y[PLANE_CURSOR];
> seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
> entry->end, skl_ddb_entry_size(entry));
> }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5d686b585a95..89af64fe90a5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1241,9 +1241,6 @@ static inline bool skl_ddb_entry_equal(const struct
> skl_ddb_entry *e1,
> }
>
> struct skl_ddb_allocation {
> - /* packed/y */
> - struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
> - struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
> u8 enabled_slices; /* GEN11 has configurable 2 slices */
> };
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 0caba7258fee..2981cea3704a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10083,6 +10083,10 @@ static void i9xx_update_cursor(struct intel_plane
> *plane,
>* except when the plane is getting enabled at which time
>* the CURCNTR write arms the update.
>*/
> +
> + if (INTEL_GEN(dev_priv) >= 9)
> + skl_write_cursor_wm(plane, crtc_state);
> +
> if (plane->cursor.base != base ||
> plane->cursor.size != fbc_ctl ||
> plane->cursor.cntl != cntl) {
> @@ -11872,6 +11876,8 @@ static void verify_wm_state(struct drm_crtc *crtc,
> struct skl_pipe_wm hw_wm, *sw_wm;
> struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
> struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
> + struct skl_ddb_entry hw_ddb_y[I915_MAX_PLANES];
> + struct skl_ddb_entry hw_ddb_uv[I915_MAX_PLANES];
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> const enum pipe pipe = intel_crtc->pipe;
> int plane, level, max_level = ilk_wm_max_level(dev_priv);
> @@ -11882,6 +11888,8 @@ static
[Intel-gfx] [PATCH] drm/i915: Synchronize hpd work in i915_hpd_storm_ctl_show()
While trying to add a chamelium test for short HPD IRQs, I ran into issues where a hotplug storm would be triggered, but the point at which it would be reported by the kernel would be after igt actually finished checking i915_hpd_storm_ctl's status. So, fix this by simply synchronizing our IRQ work, dig_port_work, and hotplug_work before printing out the HPD storm status in i915_hpd_storm_ctl_show(). Signed-off-by: Lyude Paul Cc: Ville Syrjälä --- drivers/gpu/drm/i915/i915_debugfs.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 69447c68b9af..af4268a6d2d9 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4592,6 +4592,13 @@ static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data) struct drm_i915_private *dev_priv = m->private; struct i915_hotplug *hotplug = _priv->hotplug; + /* Synchronize with everything first in case there's been an HPD +* storm, but we haven't finished handling it in the kernel yet +*/ + synchronize_irq(dev_priv->drm.irq); + flush_work(_priv->hotplug.dig_port_work); + flush_work(_priv->hotplug.hotplug_work); + seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold); seq_printf(m, "Detected: %s\n", yesno(delayed_work_pending(>reenable_work))); -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for Add Colorspace connector property interface (rev3)
== Series Details ==
Series: Add Colorspace connector property interface (rev3)
URL : https://patchwork.freedesktop.org/series/47132/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5174_full -> Patchwork_10862_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10862_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10862_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in
Patchwork_10862_full:
=== IGT changes ===
Warnings
igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic:
shard-snb: PASS -> SKIP +3
igt@pm_rc6_residency@rc6-accuracy:
shard-snb: SKIP -> PASS
== Known issues ==
Here are the changes found in Patchwork_10862_full that come from known
issues:
=== IGT changes ===
Issues hit
igt@i915_suspend@shrink:
{shard-iclb}: NOTRUN -> DMESG-WARN (fdo#108784)
igt@kms_busy@extended-modeset-hang-newfb-render-b:
{shard-iclb}: NOTRUN -> DMESG-WARN (fdo#107956)
igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
{shard-iclb}: PASS -> DMESG-WARN (fdo#107956) +1
igt@kms_chv_cursor_fail@pipe-a-128x128-top-edge:
shard-skl: NOTRUN -> FAIL (fdo#104671) +1
igt@kms_cursor_crc@cursor-64x64-suspend:
{shard-iclb}: NOTRUN -> FAIL (fdo#103232) +1
igt@kms_fbcon_fbt@psr:
shard-skl: NOTRUN -> FAIL (fdo#107882)
igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc:
shard-skl: NOTRUN -> FAIL (fdo#103167) +2
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
shard-apl: PASS -> FAIL (fdo#103167)
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
shard-skl: NOTRUN -> FAIL (fdo#105682)
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu:
shard-glk: PASS -> FAIL (fdo#103167) +1
igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc:
{shard-iclb}: PASS -> FAIL (fdo#103167) +8
igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
shard-skl: NOTRUN -> FAIL (fdo#105682, fdo#103167)
igt@kms_plane@pixel-format-pipe-b-planes:
{shard-iclb}: NOTRUN -> FAIL (fdo#103166)
igt@kms_plane@pixel-format-pipe-c-planes:
shard-glk: PASS -> FAIL (fdo#103166) +1
igt@kms_plane@plane-position-covered-pipe-a-planes:
shard-skl: NOTRUN -> FAIL (fdo#103166)
igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#108145) +2
igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
{shard-iclb}: PASS -> FAIL (fdo#103166) +2
igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
shard-apl: PASS -> FAIL (fdo#103166)
igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format:
{shard-iclb}: NOTRUN -> DMESG-WARN (fdo#107724)
igt@pm_rpm@debugfs-read:
{shard-iclb}: PASS -> DMESG-WARN (fdo#107724)
igt@pm_rpm@system-suspend-devices:
shard-skl: PASS -> INCOMPLETE (fdo#107807)
igt@pm_rps@min-max-config-loaded:
{shard-iclb}: NOTRUN -> FAIL (fdo#102250)
Possible fixes
igt@gem_pwrite@big-gtt-backwards:
shard-apl: INCOMPLETE (fdo#103927) -> PASS
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
shard-kbl: DMESG-WARN (fdo#107956) -> PASS
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
shard-apl: DMESG-WARN (fdo#107956) -> PASS
igt@kms_color@pipe-a-ctm-max:
shard-apl: FAIL (fdo#108147) -> PASS
igt@kms_color@pipe-c-legacy-gamma:
shard-apl: FAIL (fdo#104782) -> PASS
igt@kms_cursor_crc@cursor-256x85-sliding:
shard-apl: FAIL (fdo#103232) -> PASS +2
igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
shard-glk: DMESG-WARN (fdo#105763, fdo#106538) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
shard-glk: FAIL (fdo#103167) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
shard-apl: FAIL (fdo#103167) -> PASS +1
igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
{shard-iclb}: FAIL (fdo#103167) -> PASS +1
igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
shard-skl: FAIL (fdo#107815) -> PASS
igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
shard-glk: FAIL (fdo#103166) -> PASS +1
igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
{shard-iclb}:
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Add HAS_DISPLAY() and use it
== Series Details == Series: series starting with [1/3] drm/i915: Add HAS_DISPLAY() and use it URL : https://patchwork.freedesktop.org/series/52790/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5175 -> Patchwork_10871 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/52790/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10871 that come from known issues: === IGT changes === Issues hit igt@gem_ctx_create@basic-files: fi-bsw-kefka: PASS -> FAIL (fdo#108656) igt@gem_ctx_switch@basic-default: fi-icl-u2: PASS -> DMESG-WARN (fdo#107724) igt@gem_exec_suspend@basic-s4-devices: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191) igt@prime_vgem@basic-fence-flip: fi-ilk-650: PASS -> FAIL (fdo#104008) Possible fixes igt@gem_exec_suspend@basic-s3: fi-icl-u2: DMESG-WARN (fdo#107724) -> PASS igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: FAIL (fdo#103167) -> PASS igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724 fdo#108656 https://bugs.freedesktop.org/show_bug.cgi?id=108656 == Participating hosts (52 -> 46) == Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_5175 -> Patchwork_10871 CI_DRM_5175: eccbba7017aafd70e09bb105c8a6b85572a93eb8 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4723: 53bb24ad410b53cdd96f15ced8fd5921c8ab0eac @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10871: dbb983309d1585015e0ad441cadec6e902122e60 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == dbb983309d15 drm/i915: Move display device info capabilities to its own struct 3259afbd74f1 drm/i915: Do not touch PCH handshake registers if PCH is not present 7a61c38bd7ad drm/i915: Add HAS_DISPLAY() and use it == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10871/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/7] drm/i915: Disable PSR when a PSR aux error happen
On Tue, 2018-11-20 at 14:47 -0800, Rodrigo Vivi wrote:
> On Fri, Nov 09, 2018 at 12:20:13PM -0800, José Roberto de Souza
> wrote:
> > While PSR is active hardware will do aux transactions by it self to
> > wakeup sink to receive a new frame when necessary. If that
> > transaction is not acked by sink, hardware will trigger this
> > interruption.
> >
> > So let's disable PSR as it is a hint that there is problem with
> > this
> > sink.
> >
> > The removed FIXME was asking to manually train the link but we
> > don't
> > need to do that as by spec sink should do a short pulse when it is
> > out of sync with source, we just need to make sure it is awaken and
> > the SDP header with PSR disable will trigger this condition.
> >
> > v3: added workarround to fix scheduled work starvation cause by
> > to frequent PSR error interruption
> > v4: only setting irq_aux_error as we don't care in clear it and
> > not using dev_priv->irq_lock as consequence.
> >
> > Cc: Dhinakaran Pandiyan
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/intel_psr.c | 41
> >
> > 2 files changed, 38 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index e13222518c1b..4022a317cf05 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -642,6 +642,7 @@ struct i915_psr {
> > ktime_t last_entry_attempt;
> > ktime_t last_exit;
> > bool sink_not_reliable;
> > + bool irq_aux_error;
> > };
> >
> > enum intel_pch {
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index cc738497d551..93d8538a2383 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -152,6 +152,7 @@ void intel_psr_irq_handler(struct
> > drm_i915_private *dev_priv, u32 psr_iir)
> > u32 transcoders = BIT(TRANSCODER_EDP);
> > enum transcoder cpu_transcoder;
> > ktime_t time_ns = ktime_get();
> > + u32 mask = 0;
> >
> > if (INTEL_GEN(dev_priv) >= 8)
> > transcoders |= BIT(TRANSCODER_A) |
> > @@ -159,10 +160,22 @@ void intel_psr_irq_handler(struct
> > drm_i915_private *dev_priv, u32 psr_iir)
> >BIT(TRANSCODER_C);
> >
> > for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder,
> > transcoders) {
> > - /* FIXME: Exit PSR and link train manually when this
> > happens. */
> > - if (psr_iir & EDP_PSR_ERROR(cpu_transcoder))
> > - DRM_DEBUG_KMS("[transcoder %s] PSR aux
> > error\n",
> > - transcoder_name(cpu_transcoder));
> > + if (psr_iir & EDP_PSR_ERROR(cpu_transcoder)) {
> > + DRM_WARN("[transcoder %s] PSR aux error\n",
> > +transcoder_name(cpu_transcoder));
> > +
> > + dev_priv->psr.irq_aux_error = true;
> > +
> > + /*
> > +* If this interruption is not masked it will
> > keep
> > +* interrupting so fast that it prevents the
> > scheduled
> > +* work to run.
> > +* Also after a PSR error, we don't want to arm
> > PSR
> > +* again so we don't care about unmask the
> > interruption
> > +* or unset irq_aux_error.
> > +*/
> > + mask |= EDP_PSR_ERROR(cpu_transcoder);
> > + }
> >
> > if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
> > dev_priv->psr.last_entry_attempt = time_ns;
> > @@ -184,6 +197,13 @@ void intel_psr_irq_handler(struct
> > drm_i915_private *dev_priv, u32 psr_iir)
> > }
> > }
> > }
> > +
> > + if (mask) {
> > + mask |= I915_READ(EDP_PSR_IMR);
> > + I915_WRITE(EDP_PSR_IMR, mask);
> > +
> > + schedule_work(_priv->psr.work);
> > + }
> > }
> >
> > static bool intel_dp_get_colorimetry_status(struct intel_dp
> > *intel_dp)
> > @@ -898,6 +918,16 @@ int intel_psr_set_debugfs_mode(struct
> > drm_i915_private *dev_priv,
> > return ret;
> > }
> >
> > +static void intel_psr_handle_irq(struct drm_i915_private
> > *dev_priv)
> > +{
> > + struct i915_psr *psr = _priv->psr;
> > +
> > + intel_psr_disable_locked(psr->dp);
> > + psr->sink_not_reliable = true;
> > + /* let's make sure that sink is awaken */
> > + drm_dp_dpcd_writeb(>dp->aux, DP_SET_POWER,
> > DP_SET_POWER_D0);
>
> H... my gut feeling and my bad memory about PSR tells this can
> flicker
> in some panels. But at least you are disabling PSR for good after
> that what
> is a good thing.
>
> I wonder what other alternatives we would have here?
> maybe the one suggested on FIXME? disable PSR and train link
> manually?
I think that sinks will trigger a short pulse with a bad link
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915: Add HAS_DISPLAY() and use it
== Series Details == Series: series starting with [1/3] drm/i915: Add HAS_DISPLAY() and use it URL : https://patchwork.freedesktop.org/series/52790/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Add HAS_DISPLAY() and use it -drivers/gpu/drm/i915/selftests/../i915_drv.h:3567:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3569:16: warning: expression using sizeof(void) Commit: drm/i915: Do not touch PCH handshake registers if PCH is not present Okay! Commit: drm/i915: Move display device info capabilities to its own struct Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Add HAS_DISPLAY() and use it
== Series Details == Series: series starting with [1/3] drm/i915: Add HAS_DISPLAY() and use it URL : https://patchwork.freedesktop.org/series/52790/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7a61c38bd7ad drm/i915: Add HAS_DISPLAY() and use it 3259afbd74f1 drm/i915: Do not touch PCH handshake registers if PCH is not present dbb983309d15 drm/i915: Move display device info capabilities to its own struct -:395: WARNING:TRAILING_SEMICOLON: macros should not use a trailing semicolon #395: FILE: drivers/gpu/drm/i915/intel_device_info.c:81: +#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name)); -:435: ERROR:MULTISTATEMENT_MACRO_USE_DO_WHILE: Macros with multiple statements should be enclosed in a do - while loop #435: FILE: drivers/gpu/drm/i915/intel_device_info.h:110: +#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ + /* Keep in alphabetical order */ \ func(cursor_needs_physical); \ + func(has_csr); \ + func(has_ddi); \ + func(has_dp_mst); \ + func(has_fbc); \ + func(has_gmch_display); \ + func(has_hotplug); \ + func(has_ipc); \ + func(has_overlay); \ + func(has_psr); \ func(overlay_needs_physical); \ + func(supports_tv); -:435: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'func' - possible side-effects? #435: FILE: drivers/gpu/drm/i915/intel_device_info.h:110: +#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ + /* Keep in alphabetical order */ \ func(cursor_needs_physical); \ + func(has_csr); \ + func(has_ddi); \ + func(has_dp_mst); \ + func(has_fbc); \ + func(has_gmch_display); \ + func(has_hotplug); \ + func(has_ipc); \ + func(has_overlay); \ + func(has_psr); \ func(overlay_needs_physical); \ + func(supports_tv); -:435: WARNING:TRAILING_SEMICOLON: macros should not use a trailing semicolon #435: FILE: drivers/gpu/drm/i915/intel_device_info.h:110: +#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ + /* Keep in alphabetical order */ \ func(cursor_needs_physical); \ + func(has_csr); \ + func(has_ddi); \ + func(has_dp_mst); \ + func(has_fbc); \ + func(has_gmch_display); \ + func(has_hotplug); \ + func(has_ipc); \ + func(has_overlay); \ + func(has_psr); \ func(overlay_needs_physical); \ + func(supports_tv); total: 1 errors, 2 warnings, 1 checks, 432 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 6/7] drm/i915/hsw: Drop the stereo 3D enabled check in psr_compute_config()
On Fri, Nov 09, 2018 at 12:20:15PM -0800, José Roberto de Souza wrote:
> We should not access hardware while computing config also we don't
> support stereo 3D so this tests was never true.
yeap... it was there becase at some point we were planing to enabled that S3D
and if that happen we would easily forgot about the PSR case and have
bad bugs. But I don't see that happening any time soon, so, let's clean it up.
Reviewed-by: Rodrigo Vivi
>
> Suggested-by: Ville Syrjälä
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_psr.c | 7 ---
> 1 file changed, 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index e505b0b9ae47..853e3f1370a0 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -533,13 +533,6 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> return;
> }
>
> - if (IS_HASWELL(dev_priv) &&
> - I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) &
> - S3D_ENABLE) {
> - DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
> - return;
> - }
> -
> if (IS_HASWELL(dev_priv) &&
> adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
> --
> 2.19.1
>
> ___
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Re: [Intel-gfx] [PATCH 5/7] drm/i915: Keep PSR disabled after a driver reload after a PSR error
On Fri, Nov 09, 2018 at 12:20:14PM -0800, José Roberto de Souza wrote:
> If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
> will still keep the error set even after the reset done in the
> irq_preinstall and irq_uninstall hooks.
> And enabling in this situation cause the screen to freeze in the
> first time that PSR HW tries to activate so lets keep PSR disabled
> to avoid any rendering problems.
>
> v4: Moved handling from intel_psr_compute_config() to
> intel_psr_init() to avoid hardware access during compute(Ville)
>
> Cc: Ville Syrjälä
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_psr.c | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 93d8538a2383..e505b0b9ae47 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -1084,6 +1084,20 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
> if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable)
> i915_modparams.enable_psr = 0;
>
> + /*
> + * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
> + * will still keep the error set even after the reset done in the
> + * irq_preinstall and irq_uninstall hooks.
> + * And enabling in this situation cause the screen to freeze in the
> + * first time that PSR HW tries to activate so lets keep PSR disabled
> + * to avoid any rendering problems.
> + */
> + if (I915_READ(EDP_PSR_IIR) & EDP_PSR_ERROR(TRANSCODER_EDP)) {
> + DRM_DEBUG_KMS("PSR interruption error set\n");
> + dev_priv->psr.sink_not_reliable = true;
> + return;
> + }
> +
> /* Set link_standby x link_off defaults */
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> /* HSW and BDW require workarounds that we don't implement. */
> --
> 2.19.1
>
> ___
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Re: [Intel-gfx] [PATCH 4/7] drm/i915: Disable PSR when a PSR aux error happen
On Fri, Nov 09, 2018 at 12:20:13PM -0800, José Roberto de Souza wrote:
> While PSR is active hardware will do aux transactions by it self to
> wakeup sink to receive a new frame when necessary. If that
> transaction is not acked by sink, hardware will trigger this
> interruption.
>
> So let's disable PSR as it is a hint that there is problem with this
> sink.
>
> The removed FIXME was asking to manually train the link but we don't
> need to do that as by spec sink should do a short pulse when it is
> out of sync with source, we just need to make sure it is awaken and
> the SDP header with PSR disable will trigger this condition.
>
> v3: added workarround to fix scheduled work starvation cause by
> to frequent PSR error interruption
> v4: only setting irq_aux_error as we don't care in clear it and
> not using dev_priv->irq_lock as consequence.
>
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_psr.c | 41
> 2 files changed, 38 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e13222518c1b..4022a317cf05 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -642,6 +642,7 @@ struct i915_psr {
> ktime_t last_entry_attempt;
> ktime_t last_exit;
> bool sink_not_reliable;
> + bool irq_aux_error;
> };
>
> enum intel_pch {
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index cc738497d551..93d8538a2383 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -152,6 +152,7 @@ void intel_psr_irq_handler(struct drm_i915_private
> *dev_priv, u32 psr_iir)
> u32 transcoders = BIT(TRANSCODER_EDP);
> enum transcoder cpu_transcoder;
> ktime_t time_ns = ktime_get();
> + u32 mask = 0;
>
> if (INTEL_GEN(dev_priv) >= 8)
> transcoders |= BIT(TRANSCODER_A) |
> @@ -159,10 +160,22 @@ void intel_psr_irq_handler(struct drm_i915_private
> *dev_priv, u32 psr_iir)
> BIT(TRANSCODER_C);
>
> for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
> - /* FIXME: Exit PSR and link train manually when this happens. */
> - if (psr_iir & EDP_PSR_ERROR(cpu_transcoder))
> - DRM_DEBUG_KMS("[transcoder %s] PSR aux error\n",
> - transcoder_name(cpu_transcoder));
> + if (psr_iir & EDP_PSR_ERROR(cpu_transcoder)) {
> + DRM_WARN("[transcoder %s] PSR aux error\n",
> + transcoder_name(cpu_transcoder));
> +
> + dev_priv->psr.irq_aux_error = true;
> +
> + /*
> + * If this interruption is not masked it will keep
> + * interrupting so fast that it prevents the scheduled
> + * work to run.
> + * Also after a PSR error, we don't want to arm PSR
> + * again so we don't care about unmask the interruption
> + * or unset irq_aux_error.
> + */
> + mask |= EDP_PSR_ERROR(cpu_transcoder);
> + }
>
> if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
> dev_priv->psr.last_entry_attempt = time_ns;
> @@ -184,6 +197,13 @@ void intel_psr_irq_handler(struct drm_i915_private
> *dev_priv, u32 psr_iir)
> }
> }
> }
> +
> + if (mask) {
> + mask |= I915_READ(EDP_PSR_IMR);
> + I915_WRITE(EDP_PSR_IMR, mask);
> +
> + schedule_work(_priv->psr.work);
> + }
> }
>
> static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
> @@ -898,6 +918,16 @@ int intel_psr_set_debugfs_mode(struct drm_i915_private
> *dev_priv,
> return ret;
> }
>
> +static void intel_psr_handle_irq(struct drm_i915_private *dev_priv)
> +{
> + struct i915_psr *psr = _priv->psr;
> +
> + intel_psr_disable_locked(psr->dp);
> + psr->sink_not_reliable = true;
> + /* let's make sure that sink is awaken */
> + drm_dp_dpcd_writeb(>dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
H... my gut feeling and my bad memory about PSR tells this can flicker
in some panels. But at least you are disabling PSR for good after that what
is a good thing.
I wonder what other alternatives we would have here?
maybe the one suggested on FIXME? disable PSR and train link manually?
> +}
> +
> static void intel_psr_work(struct work_struct *work)
> {
> struct drm_i915_private *dev_priv =
> @@ -908,6 +938,9 @@ static void intel_psr_work(struct work_struct *work)
> if (!dev_priv->psr.enabled)
> goto unlock;
>
> + if (READ_ONCE(dev_priv->psr.irq_aux_error))
> +
Re: [Intel-gfx] [PATCH v2 09/13] drm/i915: Don't pass dev_priv around so much
On Wed, Nov 14, 2018 at 11:07:25PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Simplify the calling convention of the skl+ watermark functions
> by not passing around dev_priv needlessly. The callees have
> what they need to dig it out anyway.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/intel_pm.c | 27 +--
> 1 file changed, 13 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a743e089ab7d..a21654c974ba 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4578,12 +4578,12 @@ skl_adjusted_plane_pixel_rate(const struct
> intel_crtc_state *cstate,
> }
>
> static int
> -skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
> - const struct intel_crtc_state *cstate,
> +skl_compute_plane_wm_params(const struct intel_crtc_state *cstate,
> const struct intel_plane_state *intel_pstate,
> struct skl_wm_params *wp, int plane_id)
> {
> struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> const struct drm_plane_state *pstate = _pstate->base;
> const struct drm_framebuffer *fb = pstate->fb;
> uint32_t interm_pbpl;
> @@ -4682,8 +4682,7 @@ skl_compute_plane_wm_params(const struct
> drm_i915_private *dev_priv,
> return 0;
> }
>
> -static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> - const struct intel_crtc_state *cstate,
> +static int skl_compute_plane_wm(const struct intel_crtc_state *cstate,
> const struct intel_plane_state *intel_pstate,
> uint16_t ddb_allocation,
> int level,
> @@ -4691,6 +4690,8 @@ static int skl_compute_plane_wm(const struct
> drm_i915_private *dev_priv,
> const struct skl_wm_level *result_prev,
> struct skl_wm_level *result /* out */)
> {
> + struct drm_i915_private *dev_priv =
> + to_i915(intel_pstate->base.plane->dev);
> const struct drm_plane_state *pstate = _pstate->base;
> uint32_t latency = dev_priv->wm.skl_latency[level];
> uint_fixed_16_16_t method1, method2;
> @@ -4825,13 +4826,14 @@ static int skl_compute_plane_wm(const struct
> drm_i915_private *dev_priv,
> }
>
> static int
> -skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
> - const struct intel_crtc_state *cstate,
> +skl_compute_wm_levels(const struct intel_crtc_state *cstate,
> const struct intel_plane_state *intel_pstate,
> uint16_t ddb_blocks,
> const struct skl_wm_params *wm_params,
> struct skl_wm_level *levels)
> {
> + struct drm_i915_private *dev_priv =
> + to_i915(intel_pstate->base.plane->dev);
> int level, max_level = ilk_wm_max_level(dev_priv);
> struct skl_wm_level *result_prev = [0];
> int ret;
> @@ -4839,8 +4841,7 @@ skl_compute_wm_levels(const struct drm_i915_private
> *dev_priv,
> for (level = 0; level <= max_level; level++) {
> struct skl_wm_level *result = [level];
>
> - ret = skl_compute_plane_wm(dev_priv,
> -cstate,
> + ret = skl_compute_plane_wm(cstate,
> intel_pstate,
> ddb_blocks,
> level,
> @@ -4944,19 +4945,18 @@ static int skl_build_plane_wm_single(struct
> skl_ddb_allocation *ddb,
>enum plane_id plane_id, int color_plane)
> {
> struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> - struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> struct skl_plane_wm *wm = _state->wm.skl.optimal.planes[plane_id];
> struct skl_wm_params wm_params;
> enum pipe pipe = plane->pipe;
> uint16_t ddb_blocks = skl_ddb_entry_size(>plane[pipe][plane_id]);
> int ret;
>
> - ret = skl_compute_plane_wm_params(dev_priv, crtc_state, plane_state,
> + ret = skl_compute_plane_wm_params(crtc_state, plane_state,
> _params, color_plane);
> if (ret)
> return ret;
>
> - ret = skl_compute_wm_levels(dev_priv, crtc_state, plane_state,
> + ret = skl_compute_wm_levels(crtc_state, plane_state,
> ddb_blocks, _params, wm->wm);
> if (ret)
> return ret;
> @@ -4972,7 +4972,6 @@ static int skl_build_plane_wm_uv(struct
> skl_ddb_allocation *ddb,
>enum plane_id plane_id)
> {
> struct
Re: [Intel-gfx] [PATCH v2 08/13] drm/i915: Clean up skl+ vs. icl+ watermark computation
On Wed, Nov 14, 2018 at 11:07:24PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Make a cleaner split between the skl+ and icl+ ways of computing
> watermarks. This way skl_build_pipe_wm() doesn't have to know any
> of the gritty details of icl+ master/slave planes.
>
> We can also simplify a bunch of the lower level code by pulling
> the plane visibility checks a bit higher up.
>
> Cc: Matt Roper
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pm.c | 192 +---
> 1 file changed, 103 insertions(+), 89 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 59c91ec11c60..a743e089ab7d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4591,9 +4591,6 @@ skl_compute_plane_wm_params(const struct
> drm_i915_private *dev_priv,
> to_intel_atomic_state(cstate->base.state);
> bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
>
> - if (!intel_wm_plane_visible(cstate, intel_pstate))
> - return 0;
> -
> /* only NV12 format has two planes */
> if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
> DRM_DEBUG_KMS("Non NV12 format have single plane\n");
> @@ -4707,9 +4704,6 @@ static int skl_compute_plane_wm(const struct
> drm_i915_private *dev_priv,
> if (latency == 0)
> return level == 0 ? -EINVAL : 0;
>
> - if (!intel_wm_plane_visible(cstate, intel_pstate))
> - return 0;
> -
> /* Display WA #1141: kbl,cfl */
> if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
> IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) &&
> @@ -4832,21 +4826,16 @@ static int skl_compute_plane_wm(const struct
> drm_i915_private *dev_priv,
>
> static int
> skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
> - struct skl_ddb_allocation *ddb,
> const struct intel_crtc_state *cstate,
> const struct intel_plane_state *intel_pstate,
> uint16_t ddb_blocks,
> const struct skl_wm_params *wm_params,
> - struct skl_plane_wm *wm,
> struct skl_wm_level *levels)
> {
> int level, max_level = ilk_wm_max_level(dev_priv);
> struct skl_wm_level *result_prev = [0];
> int ret;
>
> - if (WARN_ON(!intel_pstate->base.fb))
> - return -EINVAL;
> -
> for (level = 0; level <= max_level; level++) {
> struct skl_wm_level *result = [level];
>
> @@ -4864,9 +4853,6 @@ skl_compute_wm_levels(const struct drm_i915_private
> *dev_priv,
> result_prev = result;
> }
>
> - if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
> - wm->is_planar = true;
> -
> return 0;
> }
>
> @@ -4904,9 +4890,6 @@ static void skl_compute_transition_wm(const struct
> intel_crtc_state *cstate,
> const uint16_t trans_amount = 10; /* This is configurable amount */
> uint16_t wm0_sel_res_b, trans_offset_b, res_blocks;
>
> - if (!cstate->base.active)
> - return;
> -
> /* Transition WM are not recommended by HW team for GEN9 */
> if (INTEL_GEN(dev_priv) <= 9)
> return;
> @@ -4955,97 +4938,134 @@ static void skl_compute_transition_wm(const struct
> intel_crtc_state *cstate,
> }
> }
>
> -static int __skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
> -struct skl_pipe_wm *pipe_wm,
> -enum plane_id plane_id,
> -const struct intel_crtc_state *cstate,
> -const struct intel_plane_state *pstate,
> -int color_plane)
> -{
> - struct drm_i915_private *dev_priv = to_i915(pstate->base.plane->dev);
> - struct skl_plane_wm *wm = _wm->planes[plane_id];
> - enum pipe pipe = to_intel_plane(pstate->base.plane)->pipe;
> - struct skl_wm_params wm_params;
> - uint16_t ddb_blocks = skl_ddb_entry_size(>plane[pipe][plane_id]);
> - int ret;
> -
> - ret = skl_compute_plane_wm_params(dev_priv, cstate, pstate,
> - _params, color_plane);
> - if (ret)
> - return ret;
> -
> - ret = skl_compute_wm_levels(dev_priv, ddb, cstate, pstate,
> - ddb_blocks, _params, wm, wm->wm);
> -
> - if (ret)
> - return ret;
> -
> - skl_compute_transition_wm(cstate, _params, wm, ddb_blocks);
> -
> - return 0;
> -}
> -
> static int skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
> - struct skl_pipe_wm *pipe_wm,
> - const struct intel_crtc_state *cstate,
> - const struct intel_plane_state *pstate)
> +
Re: [Intel-gfx] [PATCH 3/7] drm/i915: Do not enable PSR in the next modeset after a error
On Fri, Nov 09, 2018 at 12:20:12PM -0800, José Roberto de Souza wrote:
> When we detect a error and disable PSR, it is kept disable until the
> next modeset but as the sink already show signs that it do not
> properly work with PSR lets disabled it for good to avoid any
> additional flickering.
>
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
Maybe you can now just ignore my comment on the previous patch! :)
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_psr.c | 10 +-
> 2 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 08d25aa480f7..e13222518c1b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -641,6 +641,7 @@ struct i915_psr {
> u8 sink_sync_latency;
> ktime_t last_entry_attempt;
> ktime_t last_exit;
> + bool sink_not_reliable;
> };
>
> enum intel_pch {
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index f940305b72e4..cc738497d551 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -508,6 +508,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> return;
> }
>
> + if (dev_priv->psr.sink_not_reliable) {
> + DRM_DEBUG_KMS("Sink not reliable set\n");
> + return;
> + }
> +
> if (IS_HASWELL(dev_priv) &&
> I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) &
> S3D_ENABLE) {
> @@ -1083,6 +1088,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
> if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR) {
> DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n");
> intel_psr_disable_locked(intel_dp);
> + psr->sink_not_reliable = true;
> }
>
> if (drm_dp_dpcd_readb(_dp->aux, DP_PSR_ERROR_STATUS, ) != 1) {
> @@ -1100,8 +1106,10 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
> if (val & ~errors)
> DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n",
> val & ~errors);
> - if (val & errors)
> + if (val & errors) {
> intel_psr_disable_locked(intel_dp);
> + psr->sink_not_reliable = true;
> + }
> /* clear status register */
> drm_dp_dpcd_writeb(_dp->aux, DP_PSR_ERROR_STATUS, val);
> exit:
> --
> 2.19.1
>
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Re: [Intel-gfx] [PATCH 2/7] drm/i915: Check PSR errors instead of retrain while PSR is enabled
On Fri, Nov 09, 2018 at 12:20:11PM -0800, José Roberto de Souza wrote:
> When a PSR error happens sink sets the PSR errors register and also
> set the link to a error status.
> So in the short pulse handling it was returning earlier and doing a
> full detection and attempting to retrain but it fails as PSR HW is
> in change of the main-link.
>
> Just call intel_psr_short_pulse() before
> intel_dp_needs_link_retrain() is not the right fix as
> intel_dp_needs_link_retrain() would return true and trigger a full
> detection while PSR HW is still in change of main-link.
>
> Check for PSR active is also not safe as it could be inactive due a
> frontbuffer invalidate and still doing the PSR exit sequence.
>
> v3: added comment in intel_dp_needs_link_retrain()
>
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
I wonder if we shouldn't disable psr and then move with
link training on situations like this instead of dropping some
link trainings... Not sure if I trust PSR more to take care of
this case. But well, maybe this case is only happening on
recoverable PSR errors where hpd pulses end up happening so
this should be ok.
Let's try this approach, but please consider the option
to disable psr instead if we face some issues around here...
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_dp.c | 11 +++
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_psr.c | 15 +++
> 3 files changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 577c166f6483..158c6f25d2e2 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4383,6 +4383,17 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
> if (!intel_dp->link_trained)
> return false;
>
> + /*
> + * While PSR source HW is enabled, it will control main-link sending
> + * frames, enabling and disabling it so trying to do a retrain will fail
> + * as the link would or not be on or it could mix training patterns
> + * and frame data at the same time causing retrain to fail.
> + * Also when exiting PSR, HW will retrain the link anyways fixing
> + * any link status error.
> + */
> + if (intel_psr_enabled(intel_dp))
> + return false;
> +
> if (!intel_dp_get_link_status(intel_dp, link_status))
> return false;
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index cc7fab2b61f4..12f96297299e 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -2046,6 +2046,7 @@ void intel_psr_irq_handler(struct drm_i915_private
> *dev_priv, u32 psr_iir);
> void intel_psr_short_pulse(struct intel_dp *intel_dp);
> int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
> u32 *out_value);
> +bool intel_psr_enabled(struct intel_dp *intel_dp);
>
> /* intel_quirks.c */
> void intel_init_quirks(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 48df16a02fac..f940305b72e4 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -1107,3 +1107,18 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
> exit:
> mutex_unlock(>lock);
> }
> +
> +bool intel_psr_enabled(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + bool ret;
> +
> + if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))
> + return false;
> +
> + mutex_lock(_priv->psr.lock);
> + ret = (dev_priv->psr.dp == intel_dp && dev_priv->psr.enabled);
> + mutex_unlock(_priv->psr.lock);
> +
> + return ret;
> +}
> --
> 2.19.1
>
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[Intel-gfx] [PATCH 1/3] drm/i915: Add HAS_DISPLAY() and use it
Right now it is decided if GEN has display by checking the num_pipes,
so lets make it explicit and use a macro.
Cc: Lucas De Marchi
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 10 +-
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_bios.c| 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 4 ++--
drivers/gpu/drm/i915/intel_display.c | 4 ++--
drivers/gpu/drm/i915/intel_fbdev.c | 2 +-
drivers/gpu/drm/i915/intel_i2c.c | 2 +-
7 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b1d23c73c147..5e2d91f4dd2d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -287,7 +287,7 @@ static void intel_detect_pch(struct drm_i915_private
*dev_priv)
* Use PCH_NOP (PCH but no South Display) for PCH platforms without
* display.
*/
- if (pch && INTEL_INFO(dev_priv)->num_pipes == 0) {
+ if (pch && !HAS_DISPLAY(dev_priv)) {
DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
dev_priv->pch_type = PCH_NOP;
dev_priv->pch_id = 0;
@@ -645,7 +645,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (i915_inject_load_failure())
return -ENODEV;
- if (INTEL_INFO(dev_priv)->num_pipes) {
+ if (HAS_DISPLAY(dev_priv)) {
ret = drm_vblank_init(_priv->drm,
INTEL_INFO(dev_priv)->num_pipes);
if (ret)
@@ -696,7 +696,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
intel_overlay_setup(dev_priv);
- if (INTEL_INFO(dev_priv)->num_pipes == 0)
+ if (!HAS_DISPLAY(dev_priv))
return 0;
ret = intel_fbdev_init(dev);
@@ -1551,7 +1551,7 @@ static void i915_driver_register(struct drm_i915_private
*dev_priv)
} else
DRM_ERROR("Failed to register driver for userspace access!\n");
- if (INTEL_INFO(dev_priv)->num_pipes) {
+ if (HAS_DISPLAY(dev_priv)) {
/* Must be done after probing outputs */
intel_opregion_register(dev_priv);
acpi_video_register();
@@ -1575,7 +1575,7 @@ static void i915_driver_register(struct drm_i915_private
*dev_priv)
* We need to coordinate the hotplugs with the asynchronous fbdev
* configuration, for which we use the fbdev->async_cookie.
*/
- if (INTEL_INFO(dev_priv)->num_pipes)
+ if (HAS_DISPLAY(dev_priv))
drm_kms_helper_poll_init(dev);
intel_power_domains_enable(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 21e4405e2168..3cdbb3d074db 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2568,6 +2568,8 @@ intel_info(const struct drm_i915_private *dev_priv)
#define GT_FREQUENCY_MULTIPLIER 50
#define GEN9_FREQ_SCALER 3
+#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->num_pipes > 0)
+
#include "i915_trace.h"
static inline bool intel_vtd_active(void)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 0694aa8bb9bc..6d3e0260d49c 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1752,7 +1752,7 @@ void intel_bios_init(struct drm_i915_private *dev_priv)
const struct bdb_header *bdb;
u8 __iomem *bios = NULL;
- if (INTEL_INFO(dev_priv)->num_pipes == 0) {
+ if (!HAS_DISPLAY(dev_priv)) {
DRM_DEBUG_KMS("Skipping VBT init due to disabled display.\n");
return;
}
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index ceecb5bd5226..677002a9e893 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -782,7 +782,7 @@ void intel_device_info_runtime_init(struct
intel_device_info *info)
if (i915_modparams.disable_display) {
DRM_INFO("Display disabled (module parameter)\n");
info->num_pipes = 0;
- } else if (info->num_pipes > 0 &&
+ } else if (HAS_DISPLAY(dev_priv) &&
(IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
HAS_PCH_SPLIT(dev_priv)) {
u32 fuse_strap = I915_READ(FUSE_STRAP);
@@ -807,7 +807,7 @@ void intel_device_info_runtime_init(struct
intel_device_info *info)
DRM_INFO("PipeC fused off\n");
info->num_pipes -= 1;
}
- } else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) {
+ } else if (HAS_DISPLAY(dev_priv) && IS_GEN9(dev_priv)) {
u32 dfsm = I915_READ(SKL_DFSM);
u8 disabled_mask = 0;
bool invalid;
diff --git
[Intel-gfx] [PATCH 2/3] drm/i915: Do not touch PCH handshake registers if PCH is not present
If no PCH was detected in intel_detect_pch() don't touch the
handshake registers.
Cc: Lucas De Marchi
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 1c2de9b69a19..f33f335d6106 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3325,6 +3325,9 @@ static void intel_pch_reset_handshake(struct
drm_i915_private *dev_priv,
i915_reg_t reg;
u32 reset_bits, val;
+ if (!HAS_PCH_SPLIT(dev_priv))
+ return;
+
if (IS_IVYBRIDGE(dev_priv)) {
reg = GEN7_MSG_CTL;
reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK;
--
2.19.1
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[Intel-gfx] [PATCH 3/3] drm/i915: Move display device info capabilities to its own struct
This helps separate what capabilities are display capabilities.
Cc: Jani Nikula
Cc: Lucas De Marchi
Suggested-by: Jani Nikula
Suggested-by: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 22 ++---
drivers/gpu/drm/i915/i915_pci.c | 117 +--
drivers/gpu/drm/i915/intel_device_info.c | 4 +
drivers/gpu/drm/i915/intel_device_info.h | 31 +++---
drivers/gpu/drm/i915/intel_display.c | 4 +-
drivers/gpu/drm/i915/intel_fbc.c | 2 +-
6 files changed, 102 insertions(+), 78 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3cdbb3d074db..834ea2cc6662 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2448,9 +2448,9 @@ intel_info(const struct drm_i915_private *dev_priv)
((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
})
-#define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
+#define HAS_OVERLAY(dev_priv) ((dev_priv)->info.display.has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
- ((dev_priv)->info.overlay_needs_physical)
+ ((dev_priv)->info.display.overlay_needs_physical)
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
#define HAS_BROKEN_CS_TLB(dev_priv)(IS_I830(dev_priv) ||
IS_I845G(dev_priv))
@@ -2471,31 +2471,31 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
!(IS_I915G(dev_priv) || \
IS_I915GM(dev_priv)))
-#define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
-#define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
+#define SUPPORTS_TV(dev_priv) ((dev_priv)->info.display.supports_tv)
+#define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.display.has_hotplug)
#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
-#define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
+#define HAS_FBC(dev_priv) ((dev_priv)->info.display.has_fbc)
#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) &&
INTEL_GEN(dev_priv) >= 7)
#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
-#define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
+#define HAS_DP_MST(dev_priv) ((dev_priv)->info.display.has_dp_mst)
-#define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
+#define HAS_DDI(dev_priv) ((dev_priv)->info.display.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
-#define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
+#define HAS_PSR(dev_priv) ((dev_priv)->info.display.has_psr)
#define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
#define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
#define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
-#define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
+#define HAS_CSR(dev_priv) ((dev_priv)->info.display.has_csr)
#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
-#define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc)
+#define HAS_IPC(dev_priv) ((dev_priv)->info.display.has_ipc)
/*
* For now, anything with a GuC requires uCode loading, and then supports
@@ -2556,7 +2556,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
-#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
+#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.display.has_gmch_display)
#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 983ae7fd8217..8e37a835314f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -65,8 +65,9 @@
#define GEN2_FEATURES \
GEN(2), \
.num_pipes = 1, \
- .has_overlay = 1, .overlay_needs_physical = 1, \
- .has_gmch_display = 1, \
+ .display.has_overlay = 1, \
+ .display.overlay_needs_physical = 1, \
+ .display.has_gmch_display = 1, \
.hws_needs_physical = 1, \
.unfenced_needs_alignment = 1, \
.ring_mask = RENDER_RING, \
@@ -79,7 +80,8 @@
static const struct intel_device_info intel_i830_info = {
GEN2_FEATURES,
PLATFORM(INTEL_I830),
- .is_mobile = 1, .cursor_needs_physical = 1,
+ .is_mobile = 1,
+ .display.cursor_needs_physical = 1,
.num_pipes = 2, /* legal, last one wins */
};
@@ -93,8 +95,8 @@ static const struct intel_device_info intel_i85x_info = {
PLATFORM(INTEL_I85X),
Re: [Intel-gfx] [PATCH RFC 2/5] cgroup: Add mechanism to register vendor specific DRM devices
Hello, On Tue, Nov 20, 2018 at 10:21:14PM +, Ho, Kenny wrote: > By this reply, are you suggesting that vendor specific resources > will never be acceptable to be managed under cgroup? Let say a user I wouldn't say never but whatever which gets included as a cgroup controller should have clearly defined resource abstractions and the control schemes around them including support for delegation. AFAICS, gpu side still seems to have a long way to go (and it's not clear whether that's somewhere it will or needs to end up). > want to have similar functionality as what cgroup is offering but to > manage vendor specific resources, what would you suggest as a > solution? When you say keeping vendor specific resource regulation > inside drm or specific drivers, do you mean we should replicate the > cgroup infrastructure there or do you mean either drm or specific > driver should query existing hierarchy (such as device or perhaps > cpu) for the process organization information? > > To put the questions in more concrete terms, let say a user wants to > expose certain part of a gpu to a particular cgroup similar to the > way selective cpu cores are exposed to a cgroup via cpuset, how > should we go about enabling such functionality? Do what the intel driver or bpf is doing? It's not difficult to hook into cgroup for identification purposes. Thanks. -- tejun ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Re-enable fastset by default
On Tue, Nov 20, 2018 at 02:40:49PM +0100, Maarten Lankhorst wrote: > Now that we've solved the backlight issue, I think it's time to enable > this again by default. We've enabled it in the past, but backlight > issues prevented us from enabling it by default. > > Our hardware readout is pretty complete, and with all of the connector > state moved to atomic I'm hoping we finally have enough capability to > re-enable fastset by default. > > Signed-off-by: Maarten Lankhorst > --- > drivers/gpu/drm/i915/i915_params.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_params.h > b/drivers/gpu/drm/i915/i915_params.h > index 7e56c516c815..149ab592a695 100644 > --- a/drivers/gpu/drm/i915/i915_params.h > +++ b/drivers/gpu/drm/i915/i915_params.h > @@ -57,7 +57,7 @@ struct drm_printer; > /* leave bools at the end to not create holes */ \ > param(bool, alpha_support, IS_ENABLED(CONFIG_DRM_I915_ALPHA_SUPPORT)) \ > param(bool, enable_hangcheck, true) \ > - param(bool, fastboot, false) \ > + param(bool, fastboot, true) \ Do we know the impact of this on PSR, FBC and DRRS? Last time that I checked a while ago this would break this features since they just get enabled right after pipe getting enabled. > param(bool, prefault_disable, false) \ > param(bool, load_detect_test, false) \ > param(bool, force_reset_modeset_test, false) \ > -- > 2.19.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Force a LUT update in intel_initial_commit()
On Tue, Nov 20, 2018 at 03:54:49PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> If we force a plane update to fix up our half populated plane state
> we'll also force on the pipe gamma for the plane (since we always
> enable pipe gamma currently). If the BIOS hasn't programmed a sensible
> LUT into the hardware this will cause the image to become corrupted.
> Typical symptoms are a purple/yellow/etc. flash when the driver loads.
>
> To avoid this let's program something sensible into the LUT when
> we do the plane update. In the future I plan to add proper plane
> gamma enable readout so this is just a temporary measure.
Since this is temporary and marked with FIXME and Hans confirmed
it solves the best behaviour let's move with this.
But I'm wondering if there is no way to minimize this instead of
forcing this to every commit for each crtc...
Anyway,
Reviewed-by: Rodrigo Vivi
>
> Cc: Hans de Goede
> Fixes: 516a49cc1946 ("drm/i915: Fix assert_plane() warning on bootup with
> external display")
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 132e978227fb..60c1e54285c1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15011,6 +15011,14 @@ static int intel_initial_commit(struct drm_device
> *dev)
> ret = drm_atomic_add_affected_planes(state, crtc);
> if (ret)
> goto out;
> +
> + /*
> + * FIXME hack to force a LUT update to avoid the
> + * plane update forcing the pipe gamma on without
> + * having a proper LUT loaded. Remove once we
> + * have readout for pipe gamma enable.
> + */
> + crtc_state->color_mgmt_changed = true;
> }
> }
>
> --
> 2.18.1
>
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add rotation readout for plane initial config
On Tue, Nov 20, 2018 at 03:54:50PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> If we need to force a full plane update before userspace/fbdev
> have given us a proper plane state we should try to maintain the
> current plane state as much as possible (apart from the parts
> of the state we're trying to fix up with the plane update).
> To that end add basic readout for the plane rotation and
> maintain it during the initial fb takeover.
>
> Cc: Hans de Goede
> Fixes: 516a49cc1946 ("drm/i915: Fix assert_plane() warning on bootup with
> external display")
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 27 +++
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 2 files changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 60c1e54285c1..4d339f54559c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2831,6 +2831,7 @@ intel_find_initial_plane_obj(struct intel_crtc
> *intel_crtc,
> return;
>
> valid_fb:
> + intel_state->base.rotation = plane_config->rotation;
> intel_fill_fb_ggtt_view(_state->view, fb,
> intel_state->base.rotation);
> intel_state->color_plane[0].stride =
> @@ -7787,8 +7788,15 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
> plane_config->tiling = I915_TILING_X;
> fb->modifier = I915_FORMAT_MOD_X_TILED;
> }
> +
> + if (val & DISPPLANE_ROTATE_180)
> + plane_config->rotation = DRM_MODE_ROTATE_180;
> }
>
> + if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
> + val & DISPPLANE_MIRROR)
> + plane_config->rotation |= DRM_MODE_REFLECT_X;
> +
> pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
> fourcc = i9xx_format_to_fourcc(pixel_format);
> fb->format = drm_format_info(fourcc);
> @@ -8898,6 +8906,25 @@ skylake_get_initial_plane_config(struct intel_crtc
> *crtc,
> goto error;
> }
>
> + switch (val & PLANE_CTL_ROTATE_MASK) {
> + case PLANE_CTL_ROTATE_0:
> + plane_config->rotation = DRM_MODE_ROTATE_0;
> + break;
> + case PLANE_CTL_ROTATE_90:
> + plane_config->rotation = DRM_MODE_ROTATE_270;
we should add that comment that DRM_MODE_ROTATE_ is counter clockwise
to avoid later confusion.
Also I wonder if we shouldn't move all the cases to a unique
map function.
Anyways,
Reviewed-by: Rodrigo Vivi
> + break;
> + case PLANE_CTL_ROTATE_180:
> + plane_config->rotation = DRM_MODE_ROTATE_180;
> + break;
> + case PLANE_CTL_ROTATE_270:
> + plane_config->rotation = DRM_MODE_ROTATE_90;
> + break;
> + }
> +
> + if (INTEL_GEN(dev_priv) >= 10 &&
> + val & PLANE_CTL_FLIP_HORIZONTAL)
> + plane_config->rotation |= DRM_MODE_REFLECT_X;
> +
> base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xf000;
> plane_config->base = base;
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index f575ba2a59da..a7d9ac912125 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -572,6 +572,7 @@ struct intel_initial_plane_config {
> unsigned int tiling;
> int size;
> u32 base;
> + u8 rotation;
> };
>
> #define SKL_MIN_SRC_W 8
> --
> 2.18.1
>
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Re: [Intel-gfx] [PATCH] drm/i915/ilk: Fix warning when reading emon_status with no output
On Mon, 2018-11-19 at 17:05 -0800, Rodrigo Vivi wrote: > On Mon, Nov 19, 2018 at 03:01:01PM -0800, José Roberto de Souza > wrote: > > When there is no output no one will hold a runtime_pm reference > > causing a warning when trying to read emom_status in debugfs. > > > > [22.756480] [ cut here ] > > [22.756489] RPM wakelock ref not held during HW access > > [22.756578] WARNING: CPU: 0 PID: 1058 at > > drivers/gpu/drm/i915/intel_drv.h:2104 gen5_read32+0x16b/0x1a0 > > [i915] > > [22.756580] Modules linked in: snd_hda_codec_hdmi > > snd_hda_codec_realtek snd_hda_codec_generic i915 coretemp > > crct10dif_pclmul crc32_pclmul ghash_clmulni_intel snd_hda_intel > > snd_hda_codec snd_hwdep snd_hda_core e1000e snd_pcm mei_me > > prime_numbers mei lpc_ich > > [22.756595] CPU: 0 PID: 1058 Comm: debugfs_test Not tainted 4.20.0- > > rc1-CI-Trybot_3219+ #1 > > [22.756597] Hardware name: Hewlett-Packard HP Compaq 8100 Elite SFF > > PC/304Ah, BIOS 786H1 v01.13 07/14/2011 > > [22.756634] RIP: 0010:gen5_read32+0x16b/0x1a0 [i915] > > [22.756637] Code: a4 ea e0 0f 0b e9 d2 fe ff ff 80 3d a5 71 19 00 > > 00 0f 85 d3 fe ff ff 48 c7 c7 48 d0 2d a0 c6 05 91 71 19 00 01 e8 > > 35 a4 ea e0 <0f> 0b e9 b9 fe ff ff e8 69 c6 f2 e0 85 c0 75 92 48 c7 > > c2 78 d0 2d > > [22.756639] RSP: 0018:c9f1fd38 EFLAGS: 00010282 > > [22.756642] RAX: RBX: 8801f7ab RCX: > > 0006 > > [22.756643] RDX: 0006 RSI: 8212886a RDI: > > 820d6d57 > > [22.756645] RBP: 00011020 R08: 43e3d1a8 R09: > > > > [22.756647] R10: c9f1fd80 R11: R12: > > 0001 > > [22.756649] R13: 8801f7ab0068 R14: 0001 R15: > > 88020d53d188 > > [22.756651] FS: 7f2878849980() GS:880213a0() > > knlGS: > > [22.756653] CS: 0010 DS: ES: CR0: 80050033 > > [22.756655] CR2: 5638deedf028 CR3: 000203292001 CR4: > > 000206f0 > > [22.756657] Call Trace: > > [22.756689] i915_mch_val+0x1b/0x60 [i915] > > [22.756721] i915_emon_status+0x45/0xd0 [i915] > > [22.756730] seq_read+0xdb/0x3c0 > > [22.756736] ? lockdep_hardirqs_off+0x94/0xd0 > > [22.756740] ? __slab_free+0x24e/0x510 > > [22.756746] full_proxy_read+0x52/0x90 > > [22.756752] __vfs_read+0x31/0x170 > > [22.756759] ? do_sys_open+0x13b/0x240 > > [22.756763] ? rcu_read_lock_sched_held+0x6f/0x80 > > [22.756766] vfs_read+0x9e/0x140 > > [22.756770] ksys_read+0x50/0xc0 > > [22.756775] do_syscall_64+0x55/0x190 > > [22.756781] entry_SYSCALL_64_after_hwframe+0x49/0xbe > > [22.756783] RIP: 0033:0x7f28781dc34e > > [22.756786] Code: 00 00 00 00 48 8b 15 71 8c 20 00 f7 d8 64 89 02 > > 48 c7 c0 ff ff ff ff c3 0f 1f 40 00 8b 05 ba d0 20 00 85 c0 75 16 > > 31 c0 0f 05 <48> 3d 00 f0 ff ff 77 5a f3 c3 0f 1f 84 00 00 00 00 00 > > 41 54 55 49 > > [22.756787] RSP: 002b:7ffd33fa0d08 EFLAGS: 0246 ORIG_RAX: > > > > [22.756790] RAX: ffda RBX: RCX: > > 7f28781dc34e > > [22.756792] RDX: 0200 RSI: 7ffd33fa0d50 RDI: > > 0008 > > [22.756794] RBP: 7ffd33fa0f60 R08: R09: > > 0020 > > [22.756796] R10: R11: 0246 R12: > > 5638de45c2c0 > > [22.756797] R13: 7ffd33fa14b0 R14: R15: > > > > [22.756806] irq event stamp: 47950 > > [22.756811] hardirqs last enabled at (47949): [] > > vprintk_emit+0x124/0x320 > > [22.756813] hardirqs last disabled at (47950): [] > > trace_hardirqs_off_thunk+0x1a/0x1c > > [22.756816] softirqs last enabled at (47518): [] > > __do_softirq+0x33a/0x4b9 > > [22.756820] softirqs last disabled at (47479): [] > > irq_exit+0xa9/0xc0 > > [22.756858] WARNING: CPU: 0 PID: 1058 at > > drivers/gpu/drm/i915/intel_drv.h:2104 gen5_read32+0x16b/0x1a0 > > [i915] > > [22.756860] ---[ end trace bf56fa7d6a3cbf7a ] > > > > Signed-off-by: José Roberto de Souza > > Reviewed-by: Rodrigo Vivi Thanks for the review, pushed to drm-intel-next-queued. > > > --- > > drivers/gpu/drm/i915/i915_debugfs.c | 4 > > 1 file changed, 4 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c > > b/drivers/gpu/drm/i915/i915_debugfs.c > > index 670db5073d70..69447c68b9af 100644 > > --- a/drivers/gpu/drm/i915/i915_debugfs.c > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > > @@ -1788,6 +1788,8 @@ static int i915_emon_status(struct seq_file > > *m, void *unused) > > if (!IS_GEN5(dev_priv)) > > return -ENODEV; > > > > + intel_runtime_pm_get(dev_priv); > > + > > ret = mutex_lock_interruptible(>struct_mutex); > > if (ret) > > return ret; > > @@ -1802,6 +1804,8 @@ static int i915_emon_status(struct seq_file > > *m, void *unused) > > seq_printf(m, "GFX power: %ld\n", gfx); > > seq_printf(m, "Total power: %ld\n", chipset + gfx); > > > > + intel_runtime_pm_put(dev_priv); > > + >
Re: [Intel-gfx] [PATCH RFC 4/5] drm/amdgpu: Add accounting of command submission via DRM cgroup
Kenny Ho writes: > Account for the number of command submitted to amdgpu by type on a per > cgroup basis, for the purpose of profiling/monitoring applications. For profiling other drivers, I've used perf tracepoints, which let you get useful timelines of multiple events in the driver. Have you made use of this stat for productive profiling? signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH RFC 5/5] drm/amdgpu: Add accounting of buffer object creation request via DRM cgroup
Kenny Ho writes: > Account for the total size of buffer object requested to amdgpu by > buffer type on a per cgroup basis. > > x prefix in the control file name x.bo_requested.amd.stat signify > experimental. Why is a counting of the size of buffer objects ever allocated useful, as opposed to the current size of buffer objects allocated? And, really, why is this stat in cgroups, instead of a debugfs entry? signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Force a LUT update in intel_initial_commit()
== Series Details ==
Series: series starting with [1/2] drm/i915: Force a LUT update in
intel_initial_commit()
URL : https://patchwork.freedesktop.org/series/52754/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5172_full -> Patchwork_10861_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10861_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10861_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in
Patchwork_10861_full:
=== IGT changes ===
Possible regressions
{igt@runner@aborted}:
{shard-iclb}: NOTRUN -> FAIL
Warnings
igt@perf_pmu@rc6:
shard-kbl: SKIP -> PASS
igt@pm_rc6_residency@rc6-accuracy:
shard-snb: SKIP -> PASS
igt@tools_test@tools_test:
shard-snb: PASS -> SKIP
shard-kbl: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_10861_full that come from known
issues:
=== IGT changes ===
Issues hit
igt@gem_workarounds@suspend-resume-context:
shard-skl: NOTRUN -> INCOMPLETE (fdo#104108, fdo#107773)
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
shard-glk: PASS -> DMESG-WARN (fdo#107956)
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
{shard-iclb}: PASS -> DMESG-WARN (fdo#107956)
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
{shard-iclb}: NOTRUN -> DMESG-WARN (fdo#107956)
igt@kms_cursor_crc@cursor-64x64-dpms:
shard-glk: PASS -> FAIL (fdo#103232)
igt@kms_cursor_crc@cursor-size-change:
shard-apl: PASS -> FAIL (fdo#103232) +1
igt@kms_draw_crc@draw-method-xrgb2101010-render-xtiled:
shard-skl: PASS -> FAIL (fdo#103184) +1
igt@kms_flip@dpms-vs-vblank-race-interruptible:
shard-glk: PASS -> FAIL (fdo#103060)
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-skl: PASS -> FAIL (fdo#105363)
igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
shard-glk: PASS -> FAIL (fdo#103167)
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
shard-apl: PASS -> FAIL (fdo#103167) +1
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
shard-skl: NOTRUN -> FAIL (fdo#103167)
igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-render:
shard-skl: PASS -> FAIL (fdo#103167) +5
igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
shard-skl: PASS -> FAIL (fdo#105682)
igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
{shard-iclb}: PASS -> FAIL (fdo#103167) +2
igt@kms_plane@plane-position-covered-pipe-b-planes:
shard-apl: PASS -> FAIL (fdo#103166)
igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
shard-apl: NOTRUN -> FAIL (fdo#108145)
igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
shard-skl: PASS -> FAIL (fdo#107815, fdo#108145)
igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#108145)
igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
shard-glk: PASS -> FAIL (fdo#103166)
{shard-iclb}: PASS -> FAIL (fdo#103166) +1
igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format:
{shard-iclb}: NOTRUN -> DMESG-WARN (fdo#107724) +1
igt@pm_backlight@basic-brightness:
{shard-iclb}: PASS -> DMESG-WARN (fdo#107724) +2
igt@pm_rpm@modeset-pc8-residency-stress:
shard-skl: SKIP -> INCOMPLETE (fdo#107807)
igt@pm_rpm@pm-tiling:
shard-skl: PASS -> INCOMPLETE (fdo#107807)
Possible fixes
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-apl: INCOMPLETE (fdo#103927) -> PASS
igt@gem_userptr_blits@readonly-unsync:
shard-glk: INCOMPLETE (k.org#198133, fdo#103359) -> PASS
igt@kms_atomic_transition@plane-all-transition-nonblocking-fencing:
shard-apl: DMESG-WARN (fdo#105602, fdo#103558) -> PASS +5
igt@kms_chv_cursor_fail@pipe-c-64x64-bottom-edge:
shard-skl: FAIL (fdo#104671) -> PASS
igt@kms_color@pipe-c-ctm-green-to-red:
shard-skl: FAIL (fdo#107201) -> PASS
igt@kms_color@pipe-c-degamma:
shard-skl: FAIL (fdo#104782) -> PASS
igt@kms_cursor_crc@cursor-256x256-suspend:
shard-skl: INCOMPLETE (fdo#104108, fdo#107773) -> PASS +1
igt@kms_cursor_crc@cursor-256x85-random:
shard-glk: FAIL (fdo#103232) ->
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gvt: Avoid use-after-free iterating the gtt list
== Series Details == Series: series starting with [1/2] drm/i915/gvt: Avoid use-after-free iterating the gtt list URL : https://patchwork.freedesktop.org/series/52786/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5174 -> Patchwork_10870 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/52786/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10870 that come from known issues: === IGT changes === Issues hit igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b: fi-byt-clapper: PASS -> FAIL (fdo#107362) Possible fixes igt@i915_selftest@live_execlists: fi-apl-guc: DMESG-WARN (fdo#108622) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#108622 https://bugs.freedesktop.org/show_bug.cgi?id=108622 == Participating hosts (52 -> 46) == Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-u3 == Build changes == * Linux: CI_DRM_5174 -> Patchwork_10870 CI_DRM_5174: 0bfa7192170c039a271ebc27222b4b91516e73f6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4722: fdcdfa1e220c5070072d5dac9523cd105e7406c2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10870: 295606f32d7a980ca03d0ad39aba1b2f13899bc0 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 295606f32d7a drm/i915/dp: Fix inconsistent indenting 23dd8701d720 drm/i915/gvt: Avoid use-after-free iterating the gtt list == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10870/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/dp: Fix inconsistent indenting
Always show the FEC capability as it is initialised to 0 before error.
Fixing,
drivers/gpu/drm/i915/intel_dp.c:3846 intel_dp_get_dsc_sink_cap() warn:
inconsistent indenting
Fixes: 08cadae8e157 ("i915/dp/fec: Cache the FEC_CAPABLE DPCD register")
Signed-off-by: Chris Wilson
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Cc: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_dp.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7699f9b7b2d2..de6c982b1d1e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3837,15 +3837,14 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp
*intel_dp)
DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
(int)sizeof(intel_dp->dsc_dpcd),
intel_dp->dsc_dpcd);
+
/* FEC is supported only on DP 1.4 */
- if (!intel_dp_is_edp(intel_dp)) {
- if (drm_dp_dpcd_readb(_dp->aux, DP_FEC_CAPABILITY,
- _dp->fec_capable) < 0)
- DRM_ERROR("Failed to read FEC DPCD register\n");
+ if (!intel_dp_is_edp(intel_dp) &&
+ drm_dp_dpcd_readb(_dp->aux, DP_FEC_CAPABILITY,
+ _dp->fec_capable) < 0)
+ DRM_ERROR("Failed to read FEC DPCD register\n");
- DRM_DEBUG_KMS("FEC CAPABILITY: %x\n",
- intel_dp->fec_capable);
- }
+ DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable);
}
}
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/gvt: Avoid use-after-free iterating the gtt list
Found by smatch:
drivers/gpu/drm/i915/gvt/gtt.c:2452 intel_vgpu_destroy_ggtt_mm() error:
dereferencing freed memory 'pos'
Signed-off-by: Chris Wilson
Cc: Zhenyu Wang
---
drivers/gpu/drm/i915/gvt/gtt.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 58e166effa45..c7103dd2d8d5 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -2447,10 +2447,11 @@ static void intel_vgpu_destroy_all_ppgtt_mm(struct
intel_vgpu *vgpu)
static void intel_vgpu_destroy_ggtt_mm(struct intel_vgpu *vgpu)
{
- struct intel_gvt_partial_pte *pos;
+ struct intel_gvt_partial_pte *pos, *next;
- list_for_each_entry(pos,
- >gtt.ggtt_mm->ggtt_mm.partial_pte_list, list) {
+ list_for_each_entry_safe(pos, next,
+>gtt.ggtt_mm->ggtt_mm.partial_pte_list,
+list) {
gvt_dbg_mm("partial PTE update on hold 0x%lx : 0x%llx\n",
pos->offset, pos->data);
kfree(pos);
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH RFC 2/5] cgroup: Add mechanism to register vendor specific DRM devices
Hello, On Tue, Nov 20, 2018 at 01:58:11PM -0500, Kenny Ho wrote: > Since many parts of the DRM subsystem has vendor-specific > implementations, we introduce mechanisms for vendor to register their > specific resources and control files to the DRM cgroup subsystem. A > vendor will register itself with the DRM cgroup subsystem first before > registering individual DRM devices to the cgroup subsystem. > > In addition to the cgroup_subsys_state that is common to all DRM > devices, a device-specific state is introduced and it is allocated > according to the vendor of the device. So, I'm still pretty negative about adding drm controller at this point. There isn't enough of common resource model defined yet and until that gets sorted out I think it's in the best interest of everyone involved to keep it inside drm or specific driver proper. Thanks. -- tejun ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Respin of remaining DSC + FEC patches
== Series Details == Series: Respin of remaining DSC + FEC patches URL : https://patchwork.freedesktop.org/series/52781/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5174 -> Patchwork_10869 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/52781/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10869 that come from known issues: === IGT changes === Issues hit igt@gem_ctx_create@basic-files: fi-icl-u2: PASS -> DMESG-WARN (fdo#107724) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191) igt@kms_pipe_crc_basic@read-crc-pipe-b: fi-byt-clapper: PASS -> FAIL (fdo#107362) Possible fixes igt@gem_exec_suspend@basic-s3: fi-icl-u2: DMESG-WARN (fdo#107724) -> PASS igt@i915_selftest@live_execlists: fi-apl-guc: DMESG-WARN (fdo#108622) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724 fdo#108622 https://bugs.freedesktop.org/show_bug.cgi?id=108622 == Participating hosts (52 -> 45) == Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-icl-u3 == Build changes == * Linux: CI_DRM_5174 -> Patchwork_10869 CI_DRM_5174: 0bfa7192170c039a271ebc27222b4b91516e73f6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4722: fdcdfa1e220c5070072d5dac9523cd105e7406c2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10869: e95ff6bc66aad8bae971e61143107d032c25b9bb @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e95ff6bc66aa drm/i915/fec: Disable FEC state. ad56252fd46e i915/dp/fec: Configure the Forward Error Correction bits. d38e09c8d991 drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION fef051c49e3c i915/dp/fec: Add fec_enable to the crtc state. 82aebc9e1c88 drm/i915/dsc: Enable and disable appropriate power wells for VDSC 417ab30c448b drm/i915/dp: Disable DSC in source by disabling DSS CTL bits fb7745f881e6 drm/i915/dp: Configure Display stream splitter registers during DSC enable c34e300a58e5 drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes 4548baa9da14 drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs f87a34c1eb7e drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling 45a2fece864d drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI 0b22b472ebcb drm/i915/dp: Enable/Disable DSC in DP Sink db901e30a037 drm/i915/dsc: Compute Rate Control parameters for DSC 9fbdaa92dab4 drm/i915/dsc: Define & Compute VESA DSC params be95861715ab drm/i915/dp: Do not enable PSR2 if DSC is enabled db356f2721ef drm/i915/dp: Compute DSC pipe config in atomic check c24373fbec9f drm/i915/dp: Add DSC params and DSC config to intel_crtc_state de9e97e60143 drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants d1679441f001 drm/dsc: Add helpers for DSC picture parameter set infoframes fb2dad924fca drm/dsc: Define Rate Control values that do not change over configurations 5c29875bf189 drm/dsc: Define VESA Display Stream Compression Capabilities a82354d4ddcd drm/dsc: Define Display Stream Compression PPS infoframe 72d53683f5ab drm/dsc: Modify DRM helper to return complete DSC color depth capabilities == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10869/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Respin of remaining DSC + FEC patches
== Series Details == Series: Respin of remaining DSC + FEC patches URL : https://patchwork.freedesktop.org/series/52781/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/dsc: Modify DRM helper to return complete DSC color depth capabilities Okay! Commit: drm/dsc: Define Display Stream Compression PPS infoframe Okay! Commit: drm/dsc: Define VESA Display Stream Compression Capabilities Okay! Commit: drm/dsc: Define Rate Control values that do not change over configurations Okay! Commit: drm/dsc: Add helpers for DSC picture parameter set infoframes - +drivers/gpu/drm/drm_dsc.c:200:61:expected restricted __be16 +drivers/gpu/drm/drm_dsc.c:200:61:got int +drivers/gpu/drm/drm_dsc.c:200:61: warning: incorrect type in assignment (different base types) +drivers/gpu/drm/drm_dsc.c:207:25:expected unsigned short [unsigned] [usertype] val +drivers/gpu/drm/drm_dsc.c:207:25:got restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: incorrect type in argument 1 (different base types) Commit: drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Okay! Commit: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state -drivers/gpu/drm/i915/selftests/../i915_drv.h:3567:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3568:16: warning: expression using sizeof(void) Commit: drm/i915/dp: Compute DSC pipe config in atomic check +drivers/gpu/drm/i915/intel_dp.c:1898:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:1918:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:1918:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:1937:58: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:1937:58: warning: expression using sizeof(void) Commit: drm/i915/dp: Do not enable PSR2 if DSC is enabled Okay! Commit: drm/i915/dsc: Define & Compute VESA DSC params +drivers/gpu/drm/i915/intel_vdsc.c:351:17: warning: expression using sizeof(void) +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) Commit: drm/i915/dsc: Compute Rate Control parameters for DSC Okay! Commit: drm/i915/dp: Enable/Disable DSC in DP Sink Okay! Commit: drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Okay! Commit: drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling -drivers/gpu/drm/i915/selftests/../i915_drv.h:3568:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3570:16: warning: expression using sizeof(void) Commit: drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Okay! Commit: drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Okay! Commit: drm/i915/dp: Configure Display stream splitter registers during DSC enable Okay! Commit: drm/i915/dp: Disable DSC in source by disabling DSS CTL bits -drivers/gpu/drm/i915/selftests/../i915_drv.h:3570:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3571:16: warning: expression using sizeof(void) Commit: drm/i915/dsc: Enable and disable appropriate power wells for VDSC Okay! Commit: i915/dp/fec: Add fec_enable to the crtc state. Okay! Commit: drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION Okay! Commit: i915/dp/fec: Configure the Forward Error Correction bits. Okay! Commit: drm/i915/fec: Disable FEC state. Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Respin of remaining DSC + FEC patches
== Series Details ==
Series: Respin of remaining DSC + FEC patches
URL : https://patchwork.freedesktop.org/series/52781/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
72d53683f5ab drm/dsc: Modify DRM helper to return complete DSC color depth
capabilities
a82354d4ddcd drm/dsc: Define Display Stream Compression PPS infoframe
-:31: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#31:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 342 lines checked
5c29875bf189 drm/dsc: Define VESA Display Stream Compression Capabilities
-:34: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#34:
Co-developed-by: Gaurav K Singh
-:73: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#73: FILE: include/drm/drm_dsc.h:40:
+ bool convert_rgb;
-:83: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#83: FILE: include/drm/drm_dsc.h:50:
+ bool enable422;
-:108: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#108: FILE: include/drm/drm_dsc.h:75:
+ bool block_pred_enable;
-:136: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#136: FILE: include/drm/drm_dsc.h:103:
+ bool vbr_enable;
-:151: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#151: FILE: include/drm/drm_dsc.h:118:
+ bool native_422;
-:153: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#153: FILE: include/drm/drm_dsc.h:120:
+ bool native_420;
total: 0 errors, 1 warnings, 6 checks, 121 lines checked
fb2dad924fca drm/dsc: Define Rate Control values that do not change over
configurations
-:42: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch
author 'Srivatsa, Anusha '
total: 0 errors, 1 warnings, 0 checks, 12 lines checked
d1679441f001 drm/dsc: Add helpers for DSC picture parameter set infoframes
-:79: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#79:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 285 lines checked
de9e97e60143 drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
c24373fbec9f drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
-:49: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#49: FILE: drivers/gpu/drm/i915/intel_drv.h:942:
+ bool compression_enable;
-:50: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#50: FILE: drivers/gpu/drm/i915/intel_drv.h:943:
+ bool dsc_split;
total: 0 errors, 0 warnings, 2 checks, 22 lines checked
db356f2721ef drm/i915/dp: Compute DSC pipe config in atomic check
-:262: WARNING:TABSTOP: Statements should start on a tabstop
#262: FILE: drivers/gpu/drm/i915/intel_dp.c:2025:
+else
total: 0 errors, 1 warnings, 0 checks, 262 lines checked
be95861715ab drm/i915/dp: Do not enable PSR2 if DSC is enabled
9fbdaa92dab4 drm/i915/dsc: Define & Compute VESA DSC params
-:68: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#68:
Co-developed-by: Manasi Navare
-:95: WARNING:MISSING_SPACE: break quoted strings at a space character
#95: FILE: drivers/gpu/drm/i915/intel_dp.c:1957:
+ DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input
Bpp = %d"
+ "Compressed BPP = %d\n",
-:119: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#119:
new file mode 100644
-:405: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#405: FILE: drivers/gpu/drm/i915/intel_vdsc.c:282:
+}
+};
total: 0 errors, 3 warnings, 1 checks, 496 lines checked
db901e30a037 drm/i915/dsc: Compute Rate Control parameters for DSC
-:141: CHECK:SPACING: space preferred before that '*' (ctx:VxE)
#141: FILE: drivers/gpu/drm/i915/intel_vdsc.c:411:
+ vdsc_cfg->slice_bpg_offset)*
^
-:173: CHECK:LINE_SPACING: Please don't use multiple blank lines
#173: FILE: drivers/gpu/drm/i915/intel_vdsc.c:443:
+
+
total: 0 errors, 0 warnings, 2 checks, 136 lines checked
0b22b472ebcb drm/i915/dp: Enable/Disable DSC in DP Sink
45a2fece864d drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
f87a34c1eb7e drm/i915/dp: Configure i915 Picture parameter Set registers during
DSC enabling
-:48:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)
== Series Details == Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev8) URL : https://patchwork.freedesktop.org/series/51878/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5174 -> Patchwork_10868 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51878/revisions/8/mbox/ == Known issues == Here are the changes found in Patchwork_10868 that come from known issues: === IGT changes === Issues hit igt@i915_selftest@live_coherency: fi-gdg-551: PASS -> DMESG-FAIL (fdo#107164) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@read-crc-pipe-a: fi-byt-clapper: PASS -> FAIL (fdo#107362) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) +2 Possible fixes igt@i915_selftest@live_execlists: fi-apl-guc: DMESG-WARN (fdo#108622) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#108622 https://bugs.freedesktop.org/show_bug.cgi?id=108622 == Participating hosts (52 -> 46) == Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-u3 == Build changes == * Linux: CI_DRM_5174 -> Patchwork_10868 CI_DRM_5174: 0bfa7192170c039a271ebc27222b4b91516e73f6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4722: fdcdfa1e220c5070072d5dac9523cd105e7406c2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10868: 145a11acda90d218c1127096da2f508cc178651f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 145a11acda90 drm/i915: Pass the plane to icl_program_input_csc_coeff() df683fdcc903 drm/i915: Rename the confusing 'plane_id' to 'color_plane' 5fba35efbdf4 drm/i915: Commit skl+ planes in an order that avoids ddb overlaps 3af1ac36dccf drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+ 9c3dd2383e13 drm/i915: Don't pass dev_priv around so much 0abaf8ab6989 drm/i915: Clean up skl+ vs. icl+ watermark computation 2fbbf2ed154f drm/i915: Pass the entire skl_plane_wm to skl_compute_transition_wm() c65dade8d072 drm/i915: Remove some useless zeroing on skl+ wm calculations bc734f57b05a drm/i915: Fix latency==0 handling for level 0 watermark on skl+ 2d80c5958d01 drm/i915: Pass the new crtc_state to ->disable_plane() a89fe2cf093a drm/i915: Introduce crtc_state->update_planes bitmask bd824902b5d5 drm/i915: Move single buffered plane register writes to the end 09c8e5196e04 drm/i915: Reorganize plane register writes to make them more atomic == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10868/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/backlight: Fix backlight takeover on LPT
On Tue, Nov 20, 2018 at 11:39:26AM +0100, Maarten Lankhorst wrote:
> On lynxpoint the bios sometimes sets up the backlight using the CPU
> display, but the driver expects using the PWM PCH override register.
>
> Read the value from the CPU register, then convert it to the other
> units by converting from the old duty cycle, to freq, to the new units.
>
> This value is then programmed in the override register, after which
> we set the override and disable the CPU display control. This allows
> us to switch the source without flickering, and make the backlight
> controls work in the driver.
>
> Signed-off-by: Maarten Lankhorst
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108225
> Cc: Basil Eric Rabi
> Cc: Hans de Goede
> Cc: Tolga Cakir
> Tested-by: Tolga Cakir
> ---
> drivers/gpu/drm/i915/intel_panel.c | 34 +++---
> 1 file changed, 31 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_panel.c
> b/drivers/gpu/drm/i915/intel_panel.c
> index e6cd7b55c018..3357232f1b0e 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -1485,7 +1485,7 @@ static int lpt_setup_backlight(struct intel_connector
> *connector, enum pipe unus
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct intel_panel *panel = >panel;
> u32 pch_ctl1, pch_ctl2, val;
> - bool alt;
> + bool alt, cpu_mode = false;
>
> if (HAS_PCH_LPT(dev_priv))
> alt = I915_READ(SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY;
> @@ -1507,12 +1507,40 @@ static int lpt_setup_backlight(struct intel_connector
> *connector, enum pipe unus
>
> panel->backlight.min = get_backlight_min_vbt(connector);
>
> - val = lpt_get_backlight(connector);
> + panel->backlight.enabled = pch_ctl1 & BLM_PCH_PWM_ENABLE;
> + if (panel->backlight.enabled && HAS_PCH_LPT(dev_priv) &&
> + (I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE) &&
> + !WARN_ON(pch_ctl1 & BLM_PCH_OVERRIDE_ENABLE)) {
> + u32 freq;
> +
> + cpu_mode = true;
> + /*
> + * We're in cpu mode, convert to PCH units.
> + *
> + * Convert CPU pwm tick back to hz, back to new PCH units again.
> + * this is the same formula as pch_hz_to_pwm, but the other way
> + * around..
> + */
> + val = pch_get_backlight(connector);
> + freq = DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq), val * 128);
The docs are telling me that HSW/BDW use cdclk for the CPU backlight,
and the increment is configurable as well.
Also what about S4 resume? Don't we need this trick there as well?
> +
> + val = lpt_hz_to_pwm(connector, freq);
> + } else
> + val = lpt_get_backlight(connector);
> val = intel_panel_compute_brightness(connector, val);
> panel->backlight.level = clamp(val, panel->backlight.min,
> panel->backlight.max);
>
> - panel->backlight.enabled = pch_ctl1 & BLM_PCH_PWM_ENABLE;
> + if (cpu_mode) {
> + u32 tmp;
> +
> + /* Use PWM mode, instead of cpu clock */
> + lpt_set_backlight(connector->base.state,
> panel->backlight.level);
> + I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 |
> BLM_PCH_OVERRIDE_ENABLE);
> +
> + tmp = I915_READ(BLC_PWM_CPU_CTL2);
> + I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE);
> + }
>
> return 0;
> }
> --
> 2.19.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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[Intel-gfx] [PATCH v10 21/23] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
From: Anusha Srivatsa
If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.
This has to happen before link training.
v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
- change commit message. (Gaurav)
v3: rebased. (r-b Manasi)
v4: Use fec crtc state, before setting FEC_READY
bit. (Anusha)
v5: Move to intel_ddi.c
- Make the function static (Anusha)
v6: Dont pass state as a separate argument (Ville)
v7: (From Manasi)
* Correct the debug print (Ville)
Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_ddi.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index aeb454c3573c..b778e6fed5f8 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3102,6 +3102,16 @@ static void icl_program_mg_dp_mode(struct
intel_digital_port *intel_dig_port)
I915_WRITE(MG_DP_MODE(port, 1), ln1);
}
+static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state)
+{
+ if (!crtc_state->fec_enable)
+ return;
+
+ if (drm_dp_dpcd_writeb(_dp->aux, DP_FEC_CONFIGURATION,
DP_FEC_READY) <= 0)
+ DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
+}
+
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state
*conn_state)
@@ -3142,6 +3152,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
true);
+ intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
--
2.19.1
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[Intel-gfx] [PATCH v10 14/23] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the pipe and after
compression is enabled on the sink.
v7:
* Remove unnecessary comments, leftovers (Ville)
* No need for explicit val &= ~ (Ville)
v6:
intel_dsc_enable to be part of pre_enable hook (Ville)
v5:
* make crtc_state const (Ville)
v4:
* Use cpu_transcoder instead of encoder->type for using EDP transcoder
DSC registers(Ville)
* Keep all PSS regs together (Anusha)
v3:
* Configure Pic_width/2 for each VDSC engine when two VDSC engines per pipe
are used (Manasi)
* Add DSC slice_row_per_frame in PPS16 (Manasi)
v2:
* Enable PG2 power well for VDSC on eDP
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_ddi.c | 2 +
drivers/gpu/drm/i915/intel_vdsc.c | 410 ++
3 files changed, 414 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8fbf45cd3eb8..dbabe54b0ae2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3490,6 +3490,8 @@ extern void intel_rps_mark_interactive(struct
drm_i915_private *i915,
bool interactive);
extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
bool enable);
+extern void intel_dsc_enable(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state);
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index c7d417e6262f..044203504a3d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3144,6 +3144,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
if (!is_mst)
intel_ddi_enable_pipe_clock(crtc_state);
+
+ intel_dsc_enable(encoder, crtc_state);
}
static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index b644f69f1c93..0e72520abdfc 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -577,3 +577,413 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
return intel_compute_rc_parameters(vdsc_cfg);
}
+
+static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ const struct drm_dsc_config *vdsc_cfg = _state->dp_dsc_cfg;
+ enum pipe pipe = crtc->pipe;
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 pps_val = 0;
+ u32 rc_buf_thresh_dword[4];
+ u32 rc_range_params_dword[8];
+ u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1;
+ int i = 0;
+
+ /* Populate PICTURE_PARAMETER_SET_0 registers */
+ pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
+ DSC_VER_MIN_SHIFT |
+ vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
+ vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
+ if (vdsc_cfg->block_pred_enable)
+ pps_val |= DSC_BLOCK_PREDICTION;
+ if (vdsc_cfg->convert_rgb)
+ pps_val |= DSC_COLOR_SPACE_CONVERSION;
+ if (vdsc_cfg->enable422)
+ pps_val |= DSC_422_ENABLE;
+ if (vdsc_cfg->vbr_enable)
+ pps_val |= DSC_VBR_ENABLE;
+ DRM_INFO("PPS0 = 0x%08x\n", pps_val);
+ if (cpu_transcoder == TRANSCODER_EDP) {
+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val);
+ /*
+* If 2 VDSC instances are needed, configure PPS for second
+* VDSC
+*/
+ if (crtc_state->dsc_params.dsc_split)
+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val);
+ } else {
+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val);
+ if (crtc_state->dsc_params.dsc_split)
+ I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
+ pps_val);
+ }
+
+ /* Populate PICTURE_PARAMETER_SET_1 registers */
+ pps_val = 0;
+ pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
+ DRM_INFO("PPS1 = 0x%08x\n", pps_val);
+ if (cpu_transcoder == TRANSCODER_EDP) {
+
[Intel-gfx] [PATCH v10 08/23] drm/i915/dp: Compute DSC pipe config in atomic check
DSC params like the enable, compressed bpp, slice count and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the remaining DSC
and RC parameters before enbaling DSC in atomic commit.
v14:
Remove leftovers, use dsc_bpc, refine dsc_compute_config (Ville)
v13:
* Compute DSC bpc only when DSC is req to be enabled (Ville)
v12:
* Override bpp with dsc dpcd color depth (Manasi)
v11:
* Const crtc_state, reject DSC on DP without FEC (Ville)
* Dont set dsc_split to false (Ville)
v10:
* Add a helper for dp_dsc support (Ville)
* Set pipe_config to max bpp, link params for DSC for now (Ville)
* Compute bpp - use dp dsc support helper (Ville)
v9:
* Rebase on top of drm-tip that now uses fast_narrow config
for edp (Manasi)
v8:
* Check for DSC bpc not 0 (manasi)
v7:
* Fix indentation in compute_m_n (Manasi)
v6 (From Gaurav):
* Remove function call of intel_dp_compute_dsc_params() and
invoke intel_dp_compute_dsc_params() in the patch where
it is defined to fix compilation warning (Gaurav)
v5:
Add drm_dsc_cfg in intel_crtc_state (Manasi)
v4:
* Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
* Add a comment why we need to check PSR while enabling DSC (Gaurav)
v3:
* Check PPR > max_cdclock to use 2 VDSC instances (Ville)
v2:
* Add if-else for eDP/DP (Gaurav)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
Acked-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_display.h | 2 +-
drivers/gpu/drm/i915/intel_dp.c | 191 ---
3 files changed, 171 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 132e978227fb..f2e6425d09ef 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6723,7 +6723,7 @@ static void compute_m_n(unsigned int m, unsigned int n,
}
void
-intel_link_compute_m_n(int bits_per_pixel, int nlanes,
+intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool constant_n)
diff --git a/drivers/gpu/drm/i915/intel_display.h
b/drivers/gpu/drm/i915/intel_display.h
index 5d50decbcbb5..afb6435887df 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -407,7 +407,7 @@ struct intel_link_m_n {
(__i)++) \
for_each_if(plane)
-void intel_link_compute_m_n(int bpp, int nlanes,
+void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool constant_n);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2b090609bee2..78ec775aa90a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -47,6 +47,8 @@
/* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
+#define DP_DSC_MIN_SUPPORTED_BPC 8
+#define DP_DSC_MAX_SUPPORTED_BPC 10
/* DP DSC throughput values used for slice count calculations KPixels/s */
#define DP_DSC_PEAK_PIXEL_RATE 272
@@ -1708,6 +1710,26 @@ struct link_config_limits {
int min_bpp, max_bpp;
};
+static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
+const struct intel_crtc_state
*pipe_config)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ /* FIXME: FEC needed for external DP until then reject DSC on DP */
+ if (!intel_dp_is_edp(intel_dp))
+ return false;
+
+ return INTEL_GEN(dev_priv) >= 10 &&
+ pipe_config->cpu_transcoder != TRANSCODER_A;
+}
+
+static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *pipe_config)
+{
+ return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
+ drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
+}
+
static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config)
{
@@ -1842,14 +1864,114 @@ intel_dp_compute_link_config_fast(struct intel_dp
*intel_dp,
return false;
}
+static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
+{
+ int i, num_bpc;
+ u8 dsc_bpc[3] = {0};
+
+ num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
+ dsc_bpc);
+ for (i = 0; i < num_bpc; i++) {
+ if
[Intel-gfx] [PATCH v10 00/23] Respin of remaining DSC + FEC patches
This patch series addresses review comments from previous series posted: https://patchwork.freedesktop.org/series/52461/ Anusha Srivatsa (4): i915/dp/fec: Add fec_enable to the crtc state. drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION i915/dp/fec: Configure the Forward Error Correction bits. drm/i915/fec: Disable FEC state. Gaurav K Singh (3): drm/i915/dsc: Define & Compute VESA DSC params drm/i915/dsc: Compute Rate Control parameters for DSC drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare (15): drm/dsc: Modify DRM helper to return complete DSC color depth capabilities drm/dsc: Define Display Stream Compression PPS infoframe drm/dsc: Define VESA Display Stream Compression Capabilities drm/dsc: Add helpers for DSC picture parameter set infoframes drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants drm/i915/dp: Add DSC params and DSC config to intel_crtc_state drm/i915/dp: Compute DSC pipe config in atomic check drm/i915/dp: Do not enable PSR2 if DSC is enabled drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes drm/i915/dp: Configure Display stream splitter registers during DSC enable drm/i915/dp: Disable DSC in source by disabling DSS CTL bits drm/i915/dsc: Enable and disable appropriate power wells for VDSC Srivatsa, Anusha (1): drm/dsc: Define Rate Control values that do not change over configurations Documentation/gpu/drm-kms-helpers.rst | 12 + drivers/gpu/drm/Makefile|2 +- drivers/gpu/drm/drm_dp_helper.c | 14 +- drivers/gpu/drm/drm_dsc.c | 228 + drivers/gpu/drm/i915/Makefile |3 +- drivers/gpu/drm/i915/i915_drv.h |4 + drivers/gpu/drm/i915/i915_reg.h |3 + drivers/gpu/drm/i915/intel_ddi.c| 75 +- drivers/gpu/drm/i915/intel_display.c|4 +- drivers/gpu/drm/i915/intel_display.h|3 +- drivers/gpu/drm/i915/intel_dp.c | 233 - drivers/gpu/drm/i915/intel_drv.h| 21 + drivers/gpu/drm/i915/intel_hdmi.c | 21 +- drivers/gpu/drm/i915/intel_psr.c| 14 + drivers/gpu/drm/i915/intel_runtime_pm.c |4 +- drivers/gpu/drm/i915/intel_vdsc.c | 1088 +++ include/drm/drm_dp_helper.h |6 +- include/drm/drm_dsc.h | 485 ++ 18 files changed, 2179 insertions(+), 41 deletions(-) create mode 100644 drivers/gpu/drm/drm_dsc.c create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c create mode 100644 include/drm/drm_dsc.h -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v10 13/23] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.
v3:
* Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville)
* Move it around TRANSCODER power domain defs (Ville)
v2:
* Fix the power well mismatch CI error (Ville)
* Rename as VDSC_PIPE_A (Imre)
* Fix a whitespace (Anusha)
* Fix Comments (Imre)
Cc: Ville Syrjala
Cc: Rodrigo Vivi
Cc: Imre Deak
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjala
---
drivers/gpu/drm/i915/intel_display.h| 1 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.h
b/drivers/gpu/drm/i915/intel_display.h
index afb6435887df..98a9c22c58fd 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -226,6 +226,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_TRANSCODER_C,
POWER_DOMAIN_TRANSCODER_EDP,
+ POWER_DOMAIN_TRANSCODER_EDP_VDSC,
POWER_DOMAIN_TRANSCODER_DSI_A,
POWER_DOMAIN_TRANSCODER_DSI_C,
POWER_DOMAIN_PORT_DDI_A_LANES,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index f945db6ea420..0d8b57382961 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -76,6 +76,8 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
return "TRANSCODER_C";
case POWER_DOMAIN_TRANSCODER_EDP:
return "TRANSCODER_EDP";
+ case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
+ return "TRANSCODER_EDP_VDSC";
case POWER_DOMAIN_TRANSCODER_DSI_A:
return "TRANSCODER_DSI_A";
case POWER_DOMAIN_TRANSCODER_DSI_C:
@@ -2014,9 +2016,9 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
*/
#define ICL_PW_2_POWER_DOMAINS ( \
ICL_PW_3_POWER_DOMAINS |\
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
BIT_ULL(POWER_DOMAIN_INIT))
/*
-* - eDP/DSI VDSC
* - KVMR (HW control)
*/
#define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
--
2.19.1
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[Intel-gfx] [PATCH v10 11/23] drm/i915/dsc: Compute Rate Control parameters for DSC
From: Gaurav K Singh
This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.
v7 (From Manasi):
* Use DRM_DEBUG instead of DRM_ERROR (Ville)
* Use Error numberinstead of -1 (Ville)
v6 (From Manasi):
* Use 9 instead of 0x9 for consistency (Anusha)
v5 (From Manasi):
* Fix dim checkpatch warnings/checks
v4(From Gaurav):
* No change.Rebase on drm-tip
v3 (From Gaurav):
* Rebase on top of Manasi's latest series
* Return -ve value in case of failure scenarios (Manasi)
Fix review comments from Ville:
* Remove unnecessary comments
* Remove unnecessary paranthesis
* Add comments for few RC params calculations
v2 (From Manasi):
* Rebase Gaurav's patch from intel-gfx to gfx-internal
* Use struct drm_dsc_cfg instead of struct intel_dp
as a parameter
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 126 +-
1 file changed, 125 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 0a1918f2f643..b644f69f1c93 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -317,6 +317,130 @@ static int get_column_index_for_rc_params(u8
bits_per_component)
}
}
+static int intel_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
+{
+ unsigned long groups_per_line = 0;
+ unsigned long groups_total = 0;
+ unsigned long num_extra_mux_bits = 0;
+ unsigned long slice_bits = 0;
+ unsigned long hrd_delay = 0;
+ unsigned long final_scale = 0;
+ unsigned long rbs_min = 0;
+
+ /* Number of groups used to code each line of a slice */
+ groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
+ DSC_RC_PIXELS_PER_GROUP);
+
+ /* chunksize in Bytes */
+ vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
+ vdsc_cfg->bits_per_pixel,
+ (8 * 16));
+
+ if (vdsc_cfg->convert_rgb)
+ num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
+ (4 * vdsc_cfg->bits_per_component + 4)
+ - 2);
+ else
+ num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
+ (4 * vdsc_cfg->bits_per_component + 4) +
+ 2 * (4 * vdsc_cfg->bits_per_component) - 2;
+ /* Number of bits in one Slice */
+ slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
+
+ while ((num_extra_mux_bits > 0) &&
+ ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
+ num_extra_mux_bits--;
+
+ if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
+ vdsc_cfg->initial_scale_value = groups_per_line + 8;
+
+ /* scale_decrement_interval calculation according to DSC spec 1.11 */
+ if (vdsc_cfg->initial_scale_value > 8)
+ vdsc_cfg->scale_decrement_interval = groups_per_line /
+ (vdsc_cfg->initial_scale_value - 8);
+ else
+ vdsc_cfg->scale_decrement_interval =
DSC_SCALE_DECREMENT_INTERVAL_MAX;
+
+ vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
+ (vdsc_cfg->initial_xmit_delay *
+vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
+
+ if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
+ DRM_DEBUG_KMS("FinalOfs < RcModelSze for this
InitialXmitDelay\n");
+ return -ERANGE;
+ }
+
+ final_scale = (vdsc_cfg->rc_model_size * 8) /
+ (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
+ if (vdsc_cfg->slice_height > 1)
+ /*
+* NflBpgOffset is 16 bit value with 11 fractional bits
+* hence we multiply by 2^11 for preserving the
+* fractional part
+*/
+ vdsc_cfg->nfl_bpg_offset =
DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
+ (vdsc_cfg->slice_height
- 1));
+ else
+ vdsc_cfg->nfl_bpg_offset = 0;
+
+ /* 2^16 - 1 */
+ if (vdsc_cfg->nfl_bpg_offset > 65535) {
+ DRM_DEBUG_KMS("NflBpgOffset is too large for this slice
height\n");
+ return -ERANGE;
+ }
+
+ /* Number of groups used to code the entire slice */
+ groups_total = groups_per_line * vdsc_cfg->slice_height;
+
+ /* slice_bpg_offset is 16 bit value with 11 fractional bits */
+ vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
+
[Intel-gfx] [PATCH v10 15/23] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
v3:
* Unused variables cleanup (Ville)
v2:
* Rebase on drm-tip (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 21 +++--
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fe4b913e46ac..21e82c03cf80 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4567,6 +4567,7 @@ enum {
* of the infoframe structure specified by CEA-861. */
#define VIDEO_DIP_DATA_SIZE 32
#define VIDEO_DIP_VSC_DATA_SIZE 36
+#define VIDEO_DIP_PPS_DATA_SIZE 132
#define VIDEO_DIP_CTL _MMIO(0x61170)
/* Pre HSW: */
#define VIDEO_DIP_ENABLE (1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index bc5b945f9a71..ae751679047c 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -115,6 +115,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
switch (type) {
case DP_SDP_VSC:
return VIDEO_DIP_ENABLE_VSC_HSW;
+ case DP_SDP_PPS:
+ return VDIP_ENABLE_PPS;
case HDMI_INFOFRAME_TYPE_AVI:
return VIDEO_DIP_ENABLE_AVI_HSW;
case HDMI_INFOFRAME_TYPE_SPD:
@@ -136,6 +138,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
switch (type) {
case DP_SDP_VSC:
return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
+ case DP_SDP_PPS:
+ return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_AVI:
return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_SPD:
@@ -148,6 +152,18 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
}
}
+static int hsw_dip_data_size(unsigned int type)
+{
+ switch (type) {
+ case DP_SDP_VSC:
+ return VIDEO_DIP_VSC_DATA_SIZE;
+ case DP_SDP_PPS:
+ return VIDEO_DIP_PPS_DATA_SIZE;
+ default:
+ return VIDEO_DIP_DATA_SIZE;
+ }
+}
+
static void g4x_write_infoframe(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
unsigned int type,
@@ -382,11 +398,12 @@ static void hsw_write_infoframe(struct intel_encoder
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
- int data_size = type == DP_SDP_VSC ?
- VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE;
+ int data_size;
int i;
u32 val = I915_READ(ctl_reg);
+ data_size = hsw_dip_data_size(type);
+
val &= ~hsw_infoframe_enable(type);
I915_WRITE(ctl_reg, val);
--
2.19.1
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[Intel-gfx] [PATCH v10 01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities
DSC DPCD color depth register advertises its color depth capabilities
by setting each of the bits that corresponding to a specific color
depth. This patch defines those specific color depths and adds
a helper to return an array of color depth capabilities.
v2:
* Simplify the logic (Ville)
Signed-off-by: Manasi Navare
Cc: Ville Syrjala
---
drivers/gpu/drm/drm_dp_helper.c | 14 --
include/drm/drm_dp_helper.h | 3 ++-
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 6d483487f2b4..2d6c491a0542 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1428,17 +1428,19 @@ u8 drm_dp_dsc_sink_line_buf_depth(const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
}
EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
-u8 drm_dp_dsc_sink_max_color_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+int drm_dp_dsc_sink_supported_input_bpcs(const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
+u8 dsc_bpc[3])
{
+ int num_bpc = 0;
u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
if (color_depth & DP_DSC_12_BPC)
- return 12;
+ dsc_bpc[num_bpc++] = 12;
if (color_depth & DP_DSC_10_BPC)
- return 10;
+ dsc_bpc[num_bpc++] = 10;
if (color_depth & DP_DSC_8_BPC)
- return 8;
+ dsc_bpc[num_bpc++] = 8;
- return 0;
+ return num_bpc;
}
-EXPORT_SYMBOL(drm_dp_dsc_sink_max_color_depth);
+EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 3314e91f6eb3..5736c942c85b 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1123,7 +1123,8 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
bool is_edp);
u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
-u8 drm_dp_dsc_sink_max_color_depth(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE]);
+int drm_dp_dsc_sink_supported_input_bpcs(const u8
dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
+u8 dsc_bpc[3]);
static inline bool
drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
--
2.19.1
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[Intel-gfx] [PATCH v10 20/23] i915/dp/fec: Add fec_enable to the crtc state.
From: Anusha Srivatsa
For DP 1.4 and above, Display Stream compression can be
enabled only if Forward Error Correctin can be performed.
Add a crtc state for FEC. Currently, the state
is determined by platform, DP and DSC being
enabled. Moving forward we can use the state
to have error correction on other scenarios too
if needed.
v2:
- Control compression_enable with the fec_enable
parameter in crtc state and with intel_dp_supports_fec()
(Ville)
- intel_dp_can_fec()/intel_dp_supports_fec()(manasi)
v3: Check for FEC support along with setting crtc state.
v4: add checks to intel_dp_source_supports_dsc.(manasi)
- Move intel_dp_supports_fec() closer to
intel_dp_supports_dsc() (Anusha)
v5: Move fec check to intel_dp_supports_dsc(Ville)
v6: Remove warning. rebase.
v7: change crtc state to include DP sink and fec capability
of source.(Manasi)
v8: Set fec_enable in crtc in intel_dp_compute_config().
v9 (From Manasi):
* Combine the !edp and !fec_support check
* Derive dev_priv from intel_dp directly
v10 (From Manasi):
* Rebase
Suggested-by: Ville Syrjala
Cc: dri-de...@lists.freedesktop.org
Cc: Ville Syrjala
Cc: Jani Nikula
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_dp.c | 27 ++-
drivers/gpu/drm/i915/intel_drv.h | 3 +++
2 files changed, 25 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8b1694c631c7..94adbd988b91 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -545,7 +545,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
dsc_slice_count =
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
true);
- } else {
+ } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
dsc_max_output_bpp =
intel_dp_dsc_get_output_bpp(max_link_clock,
max_lanes,
@@ -1710,14 +1710,25 @@ struct link_config_limits {
int min_bpp, max_bpp;
};
-static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
+static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
const struct intel_crtc_state
*pipe_config)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- /* FIXME: FEC needed for external DP until then reject DSC on DP */
- if (!intel_dp_is_edp(intel_dp))
- return false;
+ return INTEL_GEN(dev_priv) >= 11 && pipe_config->cpu_transcoder !=
TRANSCODER_A;
+}
+
+static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *pipe_config)
+{
+ return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
+ drm_dp_sink_supports_fec(intel_dp->fec_capable);
+}
+
+static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
+const struct intel_crtc_state
*pipe_config)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
return INTEL_GEN(dev_priv) >= 10 &&
pipe_config->cpu_transcoder != TRANSCODER_A;
@@ -1726,6 +1737,9 @@ static bool intel_dp_source_supports_dsc(struct intel_dp
*intel_dp,
static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
const struct intel_crtc_state *pipe_config)
{
+ if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
+ return false;
+
return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
}
@@ -2128,6 +2142,9 @@ intel_dp_compute_config(struct intel_encoder *encoder,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
return false;
+ pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
+ intel_dp_supports_fec(intel_dp, pipe_config);
+
if (!intel_dp_compute_link_config(encoder, pipe_config, conn_state))
return false;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 92e987fc3d9f..0dfddb907f10 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -945,6 +945,9 @@ struct intel_crtc_state {
u8 slice_count;
} dsc_params;
struct drm_dsc_config dp_dsc_cfg;
+
+ /* Forward Error correction State */
+ bool fec_enable;
};
struct intel_crtc {
--
2.19.1
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[Intel-gfx] [PATCH v10 17/23] drm/i915/dp: Configure Display stream splitter registers during DSC enable
Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.
v4:
* Remove redundant comment (Ville)
v3:
* Use cpu_transcoder instead of encoder->type (Ville)
v2:
* Rebase (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 2cc933b57d94..c2534142167f 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -998,6 +998,12 @@ static void intel_dp_write_dsc_pps_sdp(struct
intel_encoder *encoder,
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum pipe pipe = crtc->pipe;
+ i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+ u32 dss_ctl1_val = 0;
+ u32 dss_ctl2_val = 0;
if (!crtc_state->dsc_params.compression_enable)
return;
@@ -1006,5 +1012,20 @@ void intel_dsc_enable(struct intel_encoder *encoder,
intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
+ if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {
+ dss_ctl1_reg = DSS_CTL1;
+ dss_ctl2_reg = DSS_CTL2;
+ } else {
+ dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
+ dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+ }
+ dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
+ if (crtc_state->dsc_params.dsc_split) {
+ dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
+ dss_ctl1_val |= JOINER_ENABLE;
+ }
+ I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
+ I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+
return;
}
--
2.19.1
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[Intel-gfx] [PATCH v10 18/23] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v4:
* Remove encoder, make crtc_state const (Ville)
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc params
* Add a condition to disable only if
dsc state compression is enabled
* Use correct DSS CTL regs
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Signed-off-by: Gaurav K Singh
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 2 ++
drivers/gpu/drm/i915/intel_vdsc.c| 32
3 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dbabe54b0ae2..a2f1b27abbd6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3492,6 +3492,7 @@ extern bool intel_set_memory_cxsr(struct drm_i915_private
*dev_priv,
bool enable);
extern void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
+extern void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index f2e6425d09ef..ad19ca286535 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5888,6 +5888,8 @@ static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state,
if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_disable_transcoder_func(old_crtc_state);
+ intel_dsc_disable(old_crtc_state);
+
if (INTEL_GEN(dev_priv) >= 9)
skylake_scaler_disable(intel_crtc);
else
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index c2534142167f..a13b776dc8fa 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -1029,3 +1029,35 @@ void intel_dsc_enable(struct intel_encoder *encoder,
return;
}
+
+void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+ u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
+
+ if (!old_crtc_state->dsc_params.compression_enable)
+ return;
+
+ if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) {
+ dss_ctl1_reg = DSS_CTL1;
+ dss_ctl2_reg = DSS_CTL2;
+ } else {
+ dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
+ dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+ }
+ dss_ctl1_val = I915_READ(dss_ctl1_reg);
+ if (dss_ctl1_val & JOINER_ENABLE)
+ dss_ctl1_val &= ~JOINER_ENABLE;
+ I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
+
+ dss_ctl2_val = I915_READ(dss_ctl2_reg);
+ if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
+ dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
+ dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
+ RIGHT_BRANCH_VDSC_ENABLE);
+ I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+
+}
--
2.19.1
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[Intel-gfx] [PATCH v10 22/23] i915/dp/fec: Configure the Forward Error Correction bits.
From: Anusha Srivatsa
If FEC is supported, the corresponding
DP_TP_CTL register bits have to be configured.
The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register
and wait till FEC_STATUS in DP_TP_CTL[28] is 1.
Also add the warn message to make sure that the control
register is already active while enabling FEC.
v2:
- Change commit message. Configure fec state after
link training (Manasi, Gaurav)
- Remove redundent checks (Manasi)
- Remove the registers that get added automagically (Anusha)
v3: s/intel_dp_set_fec_state()/intel_dp_enable_fec_state() (Gaurav)
v4: rebased.
v5:
- Move the code to the proper spot, according to spec.(Ville)
- Use fec state as a check too.
v6: Pass intel_encoder, instead of intel_dp. (Ville)
v7: Remove unwanted comments (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_ddi.c | 23 +++
2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 21e82c03cf80..5713754ace99 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9198,6 +9198,7 @@ enum skl_power_gate {
#define _DP_TP_CTL_B 0x64140
#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
#define DP_TP_CTL_ENABLE (1 << 31)
+#define DP_TP_CTL_FEC_ENABLE (1 << 30)
#define DP_TP_CTL_MODE_SST(0 << 27)
#define DP_TP_CTL_MODE_MST(1 << 27)
#define DP_TP_CTL_FORCE_ACT (1 << 25)
@@ -9216,6 +9217,7 @@ enum skl_power_gate {
#define _DP_TP_STATUS_A0x64044
#define _DP_TP_STATUS_B0x64144
#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
+#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
#define DP_TP_STATUS_IDLE_DONE(1 << 25)
#define DP_TP_STATUS_ACT_SENT (1 << 24)
#define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index b778e6fed5f8..78d8dcaa1618 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3112,6 +3112,27 @@ static void intel_dp_sink_set_fec_ready(struct intel_dp
*intel_dp,
DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
}
+static void intel_ddi_enable_fec(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+ u32 val;
+
+ if (!crtc_state->fec_enable)
+ return;
+
+ val = I915_READ(DP_TP_CTL(port));
+ val |= DP_TP_CTL_FEC_ENABLE;
+ I915_WRITE(DP_TP_CTL(port), val);
+
+ if (intel_wait_for_register(dev_priv, DP_TP_STATUS(port),
+ DP_TP_STATUS_FEC_ENABLE_LIVE,
+ DP_TP_STATUS_FEC_ENABLE_LIVE,
+ 1))
+ DRM_ERROR("Timed out waiting for FEC Enable Status\n");
+}
+
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state
*conn_state)
@@ -3157,6 +3178,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
+ intel_ddi_enable_fec(encoder, crtc_state);
+
icl_enable_phy_clock_gating(dig_port);
if (!is_mst)
--
2.19.1
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[Intel-gfx] [PATCH v10 09/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled
If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.
v4:
Fix the unrealted stuff removed during rebase (Ville)
v3:
* Rebase
v2:
* Add warning for DSC and PSR2 enabled together (DK)
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_psr.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 48df16a02fac..c42670b20326 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -75,6 +75,10 @@ static bool intel_psr2_enabled(struct drm_i915_private
*dev_priv,
if (i915_modparams.enable_psr == -1)
return false;
+ /* Cannot enable DSC and PSR2 simultaneously */
+ WARN_ON(crtc_state->dsc_params.compression_enable &&
+ crtc_state->has_psr2);
+
switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
case I915_PSR_DEBUG_FORCE_PSR1:
return false;
@@ -463,6 +467,16 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
if (!dev_priv->psr.sink_psr2_support)
return false;
+ /*
+* DSC and PSR2 cannot be enabled simultaneously. If a requested
+* resolution requires DSC to be enabled, priority is given to DSC
+* over PSR2.
+*/
+ if (crtc_state->dsc_params.compression_enable) {
+ DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n");
+ return false;
+ }
+
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
psr_max_h = 4096;
psr_max_v = 2304;
--
2.19.1
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[Intel-gfx] [PATCH v10 23/23] drm/i915/fec: Disable FEC state.
From: Anusha Srivatsa
Set the suitable bits in DP_TP_CTL to stop
bit correction when DSC is disabled.
v2:
- rebased.
- Add additional check for compression state. (Gaurav)
v3: rebased.
v4:
- Move the code to the proper spot according to spec (Ville)
- Use proper checks (manasi)
v5: Remove unnecessary checks (Ville)
v6: Resolve warnings. Add crtc_state as an argument to
intel_disable_ddi_buf(). (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_ddi.c | 28
1 file changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 78d8dcaa1618..468200648b66 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3133,6 +3133,22 @@ static void intel_ddi_enable_fec(struct intel_encoder
*encoder,
DRM_ERROR("Timed out waiting for FEC Enable Status\n");
}
+static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+ u32 val;
+
+ if (!crtc_state->fec_enable)
+ return;
+
+ val = I915_READ(DP_TP_CTL(port));
+ val &= ~DP_TP_CTL_FEC_ENABLE;
+ I915_WRITE(DP_TP_CTL(port), val);
+ POSTING_READ(DP_TP_CTL(port));
+}
+
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state
*conn_state)
@@ -3272,7 +3288,8 @@ static void intel_ddi_pre_enable(struct intel_encoder
*encoder,
}
}
-static void intel_disable_ddi_buf(struct intel_encoder *encoder)
+static void intel_disable_ddi_buf(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
@@ -3291,6 +3308,9 @@ static void intel_disable_ddi_buf(struct intel_encoder
*encoder)
val |= DP_TP_CTL_LINK_TRAIN_PAT1;
I915_WRITE(DP_TP_CTL(port), val);
+ /* Disable FEC in DP Sink */
+ intel_ddi_disable_fec_state(encoder, crtc_state);
+
if (wait)
intel_wait_ddi_buf_idle(dev_priv, port);
}
@@ -3314,7 +3334,7 @@ static void intel_ddi_post_disable_dp(struct
intel_encoder *encoder,
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
}
- intel_disable_ddi_buf(encoder);
+ intel_disable_ddi_buf(encoder, old_crtc_state);
intel_edp_panel_vdd_on(intel_dp);
intel_edp_panel_off(intel_dp);
@@ -3337,7 +3357,7 @@ static void intel_ddi_post_disable_hdmi(struct
intel_encoder *encoder,
intel_ddi_disable_pipe_clock(old_crtc_state);
- intel_disable_ddi_buf(encoder);
+ intel_disable_ddi_buf(encoder, old_crtc_state);
intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
@@ -3388,7 +3408,7 @@ void intel_ddi_fdi_post_disable(struct intel_encoder
*encoder,
val &= ~FDI_RX_ENABLE;
I915_WRITE(FDI_RX_CTL(PIPE_A), val);
- intel_disable_ddi_buf(encoder);
+ intel_disable_ddi_buf(encoder, old_crtc_state);
intel_ddi_clk_disable(encoder);
val = I915_READ(FDI_RX_MISC(PIPE_A));
--
2.19.1
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[Intel-gfx] [PATCH v10 19/23] drm/i915/dsc: Enable and disable appropriate power wells for VDSC
A separate power well 2 (PG2) is required for VDSC on eDP transcoder
whereas all other transcoders use the power wells associated with the
transcoders for VDSC.
This patch adds a helper to obtain correct power domain depending on
transcoder being used and enables/disables the power wells during
VDSC enabling/disabling.
v4:
* Get VDSC power domain only if compression en is set
in crtc_state (Ville, Imre)
v3:
* Call it intel_dsc_power_domain, add to
intel_ddi_get_power_domains (Ville)
v2:
* Fix tabs, const crtc_state, fix comments (Ville)
Suggested-by: Ville Syrjala
Cc: Ville Syrjala
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c | 6 ++
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_vdsc.c | 25 +
3 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 044203504a3d..aeb454c3573c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2154,6 +2154,12 @@ static u64 intel_ddi_get_power_domains(struct
intel_encoder *encoder,
intel_port_is_tc(dev_priv, encoder->port))
domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
+ /*
+* VDSC power is needed when DSC is enabled
+*/
+ if (crtc_state->dsc_params.compression_enable)
+ domains |= BIT_ULL(intel_dsc_power_domain(crtc_state));
+
return domains;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5b53fc262b91..92e987fc3d9f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1857,6 +1857,8 @@ uint8_t intel_dp_dsc_get_slice_count(struct intel_dp
*intel_dp, int mode_clock,
/* intel_vdsc.c */
int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config);
+enum intel_display_power_domain
+intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
{
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index a13b776dc8fa..17ef78652f71 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -578,6 +578,24 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
return intel_compute_rc_parameters(vdsc_cfg);
}
+enum intel_display_power_domain
+intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
+{
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+ /*
+* On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
+* This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
+* For any other transcoder, VDSC/joining uses the power well associated
+* with the pipe/transcoder in use. Hence another reference on the
+* transcoder power domain will suffice.
+*/
+ if (cpu_transcoder == TRANSCODER_EDP)
+ return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
+ else
+ return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
+}
+
static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
const struct intel_crtc_state
*crtc_state)
{
@@ -1008,6 +1026,10 @@ void intel_dsc_enable(struct intel_encoder *encoder,
if (!crtc_state->dsc_params.compression_enable)
return;
+ /* Enable Power wells for VDSC/joining */
+ intel_display_power_get(dev_priv,
+ intel_dsc_power_domain(crtc_state));
+
intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
@@ -1060,4 +1082,7 @@ void intel_dsc_disable(const struct intel_crtc_state
*old_crtc_state)
RIGHT_BRANCH_VDSC_ENABLE);
I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+ /* Disable Power wells for VDSC/joining */
+ intel_display_power_put(dev_priv,
+ intel_dsc_power_domain(old_crtc_state));
}
--
2.19.1
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[Intel-gfx] [PATCH v10 16/23] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.
v3:
* Rename to intel_dp_write_pps_sdp (Ville)
* Use const intel_crtc_state (Ville)
v2:
* Rebase ond drm-tip
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 0e72520abdfc..2cc933b57d94 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -976,6 +976,25 @@ static void intel_configure_pps_for_dsc_encoder(struct
intel_encoder *encoder,
}
}
+static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*crtc_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(>base);
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ const struct drm_dsc_config *vdsc_cfg = _state->dp_dsc_cfg;
+ struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
+
+ /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
+ drm_dsc_dp_pps_header_init(_dsc_pps_sdp);
+
+ /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
+ drm_dsc_pps_infoframe_pack(_dsc_pps_sdp, vdsc_cfg);
+
+ intel_dig_port->write_infoframe(encoder, crtc_state,
+ DP_SDP_PPS, _dsc_pps_sdp,
+ sizeof(dp_dsc_pps_sdp));
+}
+
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -985,5 +1004,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
+ intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
+
return;
}
--
2.19.1
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[Intel-gfx] [PATCH v10 02/23] drm/dsc: Define Display Stream Compression PPS infoframe
This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.
v4:
* Remove redundant blankline in doc (Ville)
* use drm_dsc namespace for all structs (Ville)
* Use packed struct (Ville)
v3:
* Add the SPDX shorthand (Chris Wilson)
v2:
* Do not use bitfields in the struct (Jani Nikula)
Cc: Gaurav K Singh
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Reviewed-by: Harry Wentland
---
include/drm/drm_dsc.h | 342 ++
1 file changed, 342 insertions(+)
create mode 100644 include/drm/drm_dsc.h
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
new file mode 100644
index ..78db4f61d01c
--- /dev/null
+++ b/include/drm/drm_dsc.h
@@ -0,0 +1,342 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright (C) 2018 Intel Corp.
+ *
+ * Authors:
+ * Manasi Navare
+ */
+
+#ifndef DRM_DSC_H_
+#define DRM_DSC_H_
+
+#include
+
+/* VESA Display Stream Compression DSC 1.2 constants */
+#define DSC_NUM_BUF_RANGES 15
+
+/**
+ * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
+ *
+ * The VESA DSC standard defines picture parameter set (PPS) which display
+ * stream compression encoders must communicate to decoders.
+ * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in
+ * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2.
+ * The PPS fields that span over more than a byte should be stored in Big
Endian
+ * format.
+ */
+struct drm_dsc_picture_parameter_set {
+ /**
+* @dsc_version:
+* PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC
+* PPS0[7:4] - dsc_version_major: Contains major version of DSC
+*/
+ u8 dsc_version;
+ /**
+* @pps_identifier:
+* PPS1[7:0] - Application specific identifier that can be
+* used to differentiate between different PPS tables.
+*/
+ u8 pps_identifier;
+ /**
+* @pps_reserved:
+* PPS2[7:0]- RESERVED Byte
+*/
+ u8 pps_reserved;
+ /**
+* @pps_3:
+* PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to
+* generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits,
+* 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
+* 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
+* PPS3[7:4] - bits_per_component: Bits per component for the original
+* pixels of the encoded picture.
+* 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2)
+* 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also
+* allowed only when dsc_minor_version = 0x2)
+*/
+ u8 pps_3;
+ /**
+* @pps_4:
+* PPS4[1:0] -These are the most significant 2 bits of
+* compressed BPP bits_per_pixel[9:0] syntax element.
+* PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled
+* PPS4[3] - simple_422: Indicates if decoder drops samples to
+* reconstruct the 4:2:2 picture.
+* PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is
+* active.
+* PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any
+* groups in picture
+* PPS4[7:6] - Reseved bits
+*/
+ u8 pps_4;
+ /**
+* @bits_per_pixel_low:
+* PPS5[7:0] - This indicates the lower significant 8 bits of
+* the compressed BPP bits_per_pixel[9:0] element.
+*/
+ u8 bits_per_pixel_low;
+ /**
+* @pic_height:
+* PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows
+* within the raster.
+*/
+ __be16 pic_height;
+ /**
+* @pic_width:
+* PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within
+* the raster.
+*/
+ __be16 pic_width;
+ /**
+* @slice_height:
+* PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
+*/
+ __be16 slice_height;
+ /**
+* @slice_width:
+* PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
+*/
+ __be16 slice_width;
+ /**
+* @chunk_size:
+* PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
+* that are used for slice multiplexing.
+*/
+ __be16 chunk_size;
+ /**
+* @initial_xmit_delay_high:
+* PPS16[1:0] - Most Significant two bits of initial transmission delay.
+* It specifies the number of pixel times that the encoder waits before
+* transmitting data from its rate buffer.
+* PPS16[7:2] - Reserved
+*/
+
[Intel-gfx] [PATCH v10 06/23] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec
v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
include/drm/drm_dsc.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 52e57ceaff80..d03f1b83421a 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -40,6 +40,9 @@
#define DSC_PPS_RC_RANGE_MINQP_SHIFT 11
#define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6
#define DSC_PPS_NATIVE_420_SHIFT 1
+#define DSC_1_2_MAX_LINEBUF_DEPTH_BITS 16
+#define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0
+#define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13
/* Configuration for a single Rate Control model range */
struct drm_dsc_rc_range_parameters {
--
2.19.1
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[Intel-gfx] [PATCH v10 12/23] drm/i915/dp: Enable/Disable DSC in DP Sink
From: Gaurav K Singh
This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.
v3 (From manasi):
* Pass bool state to enable/disable (Ville)
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of intel_dp as an argument (Manasi)
* Use the compression_enable flag as part of crtc_state (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_ddi.c | 5 +
drivers/gpu/drm/i915/intel_dp.c | 16
drivers/gpu/drm/i915/intel_drv.h | 3 +++
3 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 4913bbdac843..c7d417e6262f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3134,6 +3134,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
intel_ddi_init_dp_buf_reg(encoder);
if (!is_mst)
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+ intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
+ true);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
@@ -3478,6 +3480,9 @@ static void intel_disable_ddi_dp(struct intel_encoder
*encoder,
intel_edp_drrs_disable(intel_dp, old_crtc_state);
intel_psr_disable(intel_dp, old_crtc_state);
intel_edp_backlight_off(old_conn_state);
+ /* Disable the decompression in DP Sink */
+ intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
+ false);
}
static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f1bc62df1f76..8b1694c631c7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2856,6 +2856,22 @@ static bool downstream_hpd_needs_d0(struct intel_dp
*intel_dp)
intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
}
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state,
+ bool enable)
+{
+ int ret;
+
+ if (!crtc_state->dsc_params.compression_enable)
+ return;
+
+ ret = drm_dp_dpcd_writeb(_dp->aux, DP_DSC_ENABLE,
+enable ? DP_DECOMPRESSION_EN : 0);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
+ enable ? "enable" : "disable");
+}
+
/* If the sink supports it, try to set the power state appropriately */
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
{
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d6466c401358..5b53fc262b91 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1796,6 +1796,9 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp);
int intel_dp_retrain_link(struct intel_encoder *encoder,
struct drm_modeset_acquire_ctx *ctx);
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state,
+ bool enable);
void intel_dp_encoder_reset(struct drm_encoder *encoder);
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
--
2.19.1
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[Intel-gfx] [PATCH v10 10/23] drm/i915/dsc: Define & Compute VESA DSC params
From: Gaurav K Singh
This patches does the following:
1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state of intel_crtc_state.
3. Compute all parameters that are VESA DSC specific
This computation happens in the atomic check phase during
compute_config() to validate if display stream compression
can be enabled for the requested mode.
v8 (From Manasi):
* DEBUG_KMS instead of DRM_ERROR for user triggerable
errors (Ville)
v7: (From Manasi)
* Dont use signed int for rc_range_params (Manasi)
* Mask the range_bpg_offset to use only 6 bits
* Add SPDX identifier (Chris Wilson)
v6 (From Manasi):
* Add a check for line_buf_depth return value (Anusha)
* Remove DRM DSC constants to different patch (Manasi)
v5 (From Manasi):
* Add logic to limit the max line buf depth for DSC 1.1 to 13
as per DSC 1.1 spec
* Fix dim checkpatch warnings/checks
v4 (From Gaurav):
* Rebase on latest drm tip
* rename variable name(Manasi)
* Populate linebuf_depth variable(Manasi)
v3 (From Gaurav):
* Rebase my previous patches on top of Manasi's latest patch
series
* Using >>n rather than /2^n (Manasi)
* Change the commit message to explain what the patch is doing(Gaurav)
Fixed review comments from Ville:
* Don't use macro TWOS_COMPLEMENT
* Mention in comment about the source of RC params
* Return directly from case statements
* Using single asssignment for assigning rc_range_params
* Using <
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Co-developed-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/intel_dp.c | 7 +
drivers/gpu/drm/i915/intel_drv.h | 4 +
drivers/gpu/drm/i915/intel_vdsc.c | 455 ++
include/drm/drm_dp_helper.h | 3 +
5 files changed, 471 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0ff878c994e2..8370b9de6e4f 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -157,7 +157,8 @@ i915-y += dvo_ch7017.o \
intel_sdvo.o \
intel_tv.o \
vlv_dsi.o \
- vlv_dsi_pll.o
+ vlv_dsi_pll.o \
+ intel_vdsc.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 78ec775aa90a..f1bc62df1f76 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1952,6 +1952,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
return false;
}
}
+ if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) {
+ DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input
Bpp = %d"
+ "Compressed BPP = %d\n",
+ pipe_config->pipe_bpp,
+ pipe_config->dsc_params.compressed_bpp);
+ return false;
+ }
pipe_config->dsc_params.compression_enable = true;
DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
"Compressed Bpp = %d Slice Count = %d\n",
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 10476fec9485..d6466c401358 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1851,6 +1851,10 @@ uint16_t intel_dp_dsc_get_output_bpp(int link_clock,
uint8_t lane_count,
uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
int mode_hdisplay);
+/* intel_vdsc.c */
+int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config);
+
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
{
return ~((1 << lane_count) - 1) & 0xf;
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
new file mode 100644
index ..0a1918f2f643
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -0,0 +1,455 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Author: Gaurav K Singh
+ * Manasi Navare
+ */
+
+#include
+#include
+#include "i915_drv.h"
+#include "intel_drv.h"
+
+enum ROW_INDEX_BPP {
+ ROW_INDEX_6BPP = 0,
+ ROW_INDEX_8BPP,
+ ROW_INDEX_10BPP,
+ ROW_INDEX_12BPP,
+ ROW_INDEX_15BPP,
+ MAX_ROW_INDEX
+};
+
+enum COLUMN_INDEX_BPC {
+ COLUMN_INDEX_8BPC = 0,
+ COLUMN_INDEX_10BPC,
+ COLUMN_INDEX_12BPC,
+ COLUMN_INDEX_14BPC,
+ COLUMN_INDEX_16BPC,
+
[Intel-gfx] [PATCH v10 07/23] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason we need to add these params and config structure
to the intel_crtc_state so that if valid this state information
can directly be used while enabling DSC in atomic commit.
v2:
* Rebase on drm-tip (Manasi)
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 9 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5d686b585a95..8fbf45cd3eb8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -53,6 +53,7 @@
#include
#include
#include
+#include
#include "i915_params.h"
#include "i915_reg.h"
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 18b419f7f7fe..10476fec9485 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -936,6 +936,15 @@ struct intel_crtc_state {
/* Output down scaling is done in LSPCON device */
bool lspcon_downsampling;
+
+ /* Display Stream compression state */
+ struct {
+ bool compression_enable;
+ bool dsc_split;
+ u16 compressed_bpp;
+ u8 slice_count;
+ } dsc_params;
+ struct drm_dsc_config dp_dsc_cfg;
};
struct intel_crtc {
--
2.19.1
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[Intel-gfx] [PATCH v10 04/23] drm/dsc: Define Rate Control values that do not change over configurations
From: "Srivatsa, Anusha"
DSC has some Rate Control values that remain constant
across all configurations. These are as per the DSC
standard.
v3:
* Define them in drm_dsc.h as they are
DSC constants (Manasi)
v2:
* Add DP_DSC_ prefix (Jani Nikula)
Cc: dri-de...@lists.freedesktop.org
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Gaurav K Singh
Cc: Harry Wentland
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
include/drm/drm_dsc.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 3292dfed9d0a..b88e31bd9da7 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -18,6 +18,12 @@
#define DSC_SCALE_DECREMENT_INTERVAL_MAX 4095
#define DSC_RANGE_BPG_OFFSET_MASK 0x3f
+/* DSC Rate Control Constants */
+#define DSC_RC_MODEL_SIZE_CONST8192
+#define DSC_RC_EDGE_FACTOR_CONST 6
+#define DSC_RC_TGT_OFFSET_HI_CONST 3
+#define DSC_RC_TGT_OFFSET_LO_CONST 3
+
/* Configuration for a single Rate Control model range */
struct drm_dsc_rc_range_parameters {
/* Min Quantization Parameters allowed for this range */
--
2.19.1
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[Intel-gfx] [PATCH v10 03/23] drm/dsc: Define VESA Display Stream Compression Capabilities
This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder
v6: (From Manasi)
* Add a bit mask for RANGE_BPG_OFFSET for 6 bits(Manasi)
v5 (From Manasi)
* Add the RC constants as per the spec
v4 (From Manasi)
* Add the DSC_MUX_WORD_SIZE constants (Manasi)
v3 (From Manasi)
* Remove the duplicate define (Suggested By:Harry Wentland)
v2: Define this struct in DRM (From Manasi)
* Changed the data types to u8/u16 instead of unsigned longs (Manasi)
* Remove driver specific fields (Manasi)
* Move this struct definition to DRM (Manasi)
* Define DSC 1.2 parameters (Manasi)
* Use DSC_NUM_BUF_RANGES (Manasi)
* Call it drm_dsc_config (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Signed-off-by: Gaurav K Singh
Co-developed-by: Gaurav K Singh
Acked-by: Harry Wentland
Reviewed-by: Anusha Srivatsa
---
include/drm/drm_dsc.h | 115 +-
1 file changed, 114 insertions(+), 1 deletion(-)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 78db4f61d01c..3292dfed9d0a 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -11,7 +11,120 @@
#include
/* VESA Display Stream Compression DSC 1.2 constants */
-#define DSC_NUM_BUF_RANGES 15
+#define DSC_NUM_BUF_RANGES 15
+#define DSC_MUX_WORD_SIZE_8_10_BPC 48
+#define DSC_MUX_WORD_SIZE_12_BPC 64
+#define DSC_RC_PIXELS_PER_GROUP3
+#define DSC_SCALE_DECREMENT_INTERVAL_MAX 4095
+#define DSC_RANGE_BPG_OFFSET_MASK 0x3f
+
+/* Configuration for a single Rate Control model range */
+struct drm_dsc_rc_range_parameters {
+ /* Min Quantization Parameters allowed for this range */
+ u8 range_min_qp;
+ /* Max Quantization Parameters allowed for this range */
+ u8 range_max_qp;
+ /* Bits/group offset to apply to target for this group */
+ u8 range_bpg_offset;
+};
+
+struct drm_dsc_config {
+ /* Bits / component for previous reconstructed line buffer */
+ u8 line_buf_depth;
+ /* Bits per component to code (must be 8, 10, or 12) */
+ u8 bits_per_component;
+ /*
+* Flag indicating to do RGB - YCoCg conversion
+* and back (should be 1 for RGB input)
+*/
+ bool convert_rgb;
+ u8 slice_count;
+ /* Slice Width */
+ u16 slice_width;
+ /* Slice Height */
+ u16 slice_height;
+ /*
+* 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
+* outside of DSC encode/decode algorithm)
+*/
+ bool enable422;
+ /* Picture Width */
+ u16 pic_width;
+ /* Picture Height */
+ u16 pic_height;
+ /* Offset to bits/group used by RC to determine QP adjustment */
+ u8 rc_tgt_offset_high;
+ /* Offset to bits/group used by RC to determine QP adjustment */
+ u8 rc_tgt_offset_low;
+ /* Bits/pixel target << 4 (ie., 4 fractional bits) */
+ u16 bits_per_pixel;
+ /*
+* Factor to determine if an edge is present based
+* on the bits produced
+*/
+ u8 rc_edge_factor;
+ /* Slow down incrementing once the range reaches this value */
+ u8 rc_quant_incr_limit1;
+ /* Slow down incrementing once the range reaches this value */
+ u8 rc_quant_incr_limit0;
+ /* Number of pixels to delay the initial transmission */
+ u16 initial_xmit_delay;
+ /* Number of pixels to delay the VLD on the decoder,not including SSM */
+ u16 initial_dec_delay;
+ /* Block prediction enable */
+ bool block_pred_enable;
+ /* Bits/group offset to use for first line of the slice */
+ u8 first_line_bpg_offset;
+ /* Value to use for RC model offset at slice start */
+ u16 initial_offset;
+ /* Thresholds defining each of the buffer ranges */
+ u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
+ /* Parameters for each of the RC ranges */
+ struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+ /* Total size of RC model */
+ u16 rc_model_size;
+ /* Minimum QP where flatness information is sent */
+ u8 flatness_min_qp;
+ /* Maximum QP where flatness information is sent */
+ u8 flatness_max_qp;
+ /* Initial value for scale factor */
+ u8 initial_scale_value;
+ /* Decrement scale factor every scale_decrement_interval groups */
+ u16 scale_decrement_interval;
+ /* Increment scale factor every scale_increment_interval groups */
+ u16 scale_increment_interval;
+ /* Non-first line BPG offset to use */
+ u16 nfl_bpg_offset;
+ /* BPG offset used to enforce slice bit */
+ u16 slice_bpg_offset;
+ /* Final RC linear transformation offset value */
+ u16 final_offset;
+ /* Enable on-off VBR (ie.,
[Intel-gfx] [PATCH v10 05/23] drm/dsc: Add helpers for DSC picture parameter set infoframes
According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP payload according to the DSC 1.2 specification.
v7:
* Use BUILD_BUG_ON() to protect changing struct size (Ville)
* Remove typecaseting (Ville)
* Include byteorder.h in drm_dsc.c (Ville)
* Correct kernel doc spacing (Anusha)
v6:
* Use proper sequence points for breaking down the
assignments (Chris Wilson)
* Use SPDX identifier
v5:
Do not use bitfields for DRM structs (Jani N)
v4:
* Use DSC constants for params that dont change across
configurations
v3:
* Add reference to added kernel-docs in
Documentation/gpu/drm-kms-helpers.rst (Daniel Vetter)
v2:
* Add EXPORT_SYMBOL for the drm functions (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Acked-by: Harry Wentland
---
Documentation/gpu/drm-kms-helpers.rst | 12 ++
drivers/gpu/drm/Makefile | 2 +-
drivers/gpu/drm/drm_dsc.c | 228 ++
include/drm/drm_dsc.h | 21 +++
4 files changed, 262 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/drm_dsc.c
diff --git a/Documentation/gpu/drm-kms-helpers.rst
b/Documentation/gpu/drm-kms-helpers.rst
index 4b4dc236ef6f..b422eb8edf16 100644
--- a/Documentation/gpu/drm-kms-helpers.rst
+++ b/Documentation/gpu/drm-kms-helpers.rst
@@ -232,6 +232,18 @@ MIPI DSI Helper Functions Reference
.. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c
:export:
+Display Stream Compression Helper Functions Reference
+=
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+ :doc: dsc helpers
+
+.. kernel-doc:: include/drm/drm_dsc.h
+ :internal:
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+ :export:
+
Output Probing Helper Functions Reference
=
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 576ba985e138..3a3e6fb6d476 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -32,7 +32,7 @@ drm-$(CONFIG_AGP) += drm_agpsupport.o
drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
-drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
+drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_dsc.o
drm_probe_helper.o \
drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \
drm_kms_helper_common.o drm_dp_dual_mode_helper.o \
drm_simple_kms_helper.o drm_modeset_helper.o \
diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
new file mode 100644
index ..bc2b23adb072
--- /dev/null
+++ b/drivers/gpu/drm/drm_dsc.c
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2018 Intel Corp
+ *
+ * Author:
+ * Manasi Navare
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * DOC: dsc helpers
+ *
+ * These functions contain some common logic and helpers to deal with VESA
+ * Display Stream Compression standard required for DSC on Display Port/eDP or
+ * MIPI display interfaces.
+ */
+
+/**
+ * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
+ * for DisplayPort as per the DP 1.4 spec.
+ * @pps_sdp: Secondary data packet for DSC Picture Parameter Set
+ */
+void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
+{
+ memset(_sdp->pps_header, 0, sizeof(pps_sdp->pps_header));
+
+ pps_sdp->pps_header.HB1 = DP_SDP_PPS;
+ pps_sdp->pps_header.HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
+}
+EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
+
+/**
+ * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
+ * using the DSC configuration parameters in the order expected
+ * by the DSC Display Sink device. For the DSC, the sink device
+ * expects the PPS payload in the big endian format for the fields
+ * that span more than 1 byte.
+ *
+ * @pps_sdp:
+ * Secondary data packet for DSC Picture Parameter Set
+ * @dsc_cfg:
+ * DSC Configuration data filled by driver
+ */
+void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
+ const struct drm_dsc_config *dsc_cfg)
+{
+ int i;
+
+ /* Protect against someone accidently changing struct size */
+ BUILD_BUG_ON(sizeof(pps_sdp->pps_payload) !=
+DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1);
+
+ memset(_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload));
+
+ /* PPS 0 */
+ pps_sdp->pps_payload.dsc_version =
+ dsc_cfg->dsc_version_minor |
+ dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
+
+ /* PPS 1, 2 is 0 */
+
+
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Force a LUT update in intel_initial_commit()
Hi Ville,
On 20-11-18 14:54, Ville Syrjala wrote:
From: Ville Syrjälä
If we force a plane update to fix up our half populated plane state
we'll also force on the pipe gamma for the plane (since we always
enable pipe gamma currently). If the BIOS hasn't programmed a sensible
LUT into the hardware this will cause the image to become corrupted.
Typical symptoms are a purple/yellow/etc. flash when the driver loads.
To avoid this let's program something sensible into the LUT when
we do the plane update. In the future I plan to add proper plane
gamma enable readout so this is just a temporary measure.
Cc: Hans de Goede
Fixes: 516a49cc1946 ("drm/i915: Fix assert_plane() warning on bootup with external
display")
Signed-off-by: Ville Syrjälä
I can confirm that this series fixes the purple flash I was seeing on
DSI panels.
And the reporter in bug https://bugs.freedesktop.org/show_bug.cgi?id=108225
has also just reported back that the blanking he was seeing which was
also caused by the "drm/i915: Fix assert_plane() warning on bootup with external
display"
commit is also fixed, so it looks like this series is good to go:
Tested-by: Hans de Goede
Regards,
Hans
---
drivers/gpu/drm/i915/intel_display.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 132e978227fb..60c1e54285c1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15011,6 +15011,14 @@ static int intel_initial_commit(struct drm_device *dev)
ret = drm_atomic_add_affected_planes(state, crtc);
if (ret)
goto out;
+
+ /*
+* FIXME hack to force a LUT update to avoid the
+* plane update forcing the pipe gamma on without
+* having a proper LUT loaded. Remove once we
+* have readout for pipe gamma enable.
+*/
+ crtc_state->color_mgmt_changed = true;
}
}
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Re: [Intel-gfx] [PATCH i-g-t] tests/drv_selftest: Allow passing in module options from the command line
On 20/11/2018 18:16, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-20 18:07:57)
From: Tvrtko Ursulin
A new option '--kmod-options' is added which takes a string which will be
passed to modprobe when loading the module.
This for instance allows easy override of things like the random seed when
trying to reproduce failures.
Anyway we can simply extend the option parsing locally? (Just find it
unsightly to have test specific options in libigt.)
Well.. it is not test specific but kmod specific but point still stands.
Stashing argc/argv in igt_subtest_init_parse_opts() and then being able
to run getopts inside igt_main {}?
Yep, I didn't know we have this already.
I also had in mind an env for module options, which may be also useful
for the module reloading and autoloading.
In that case, since modprobe(8) supports MODPROBE_OPTIONS, we could
perhaps emulate that in igt_kmod? Or add support directly to libkmod?
With either we wouldn't even need the command line pass through. Adding
Lucas for an opinion since kmod seems to be his baby.
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH] drm/i915/selftests: Log test and subtest names for easier debugging
Quoting Tvrtko Ursulin (2018-11-20 18:18:00) > > On 20/11/2018 18:10, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2018-11-20 17:58:33) > >> > >> On 20/11/2018 17:33, Chris Wilson wrote: > >>> Quoting Tvrtko Ursulin (2018-11-20 17:28:39) > From: Tvrtko Ursulin > > Since pr_debug is not printed by default, change both test and subtest > log messages to pr_info so they are always logged. > >>> > >>> I just use the trace... As when the test fails we say which subtest > >>> failed, and hopefully include more details in the error message, and > >>> recent history is in the trace dumped when considered relevant. > >> > >> Fair. My thinking was simply to leave more breadcrumbs if the machine > >> died in the middle of a subtest. > > > > Thinking more about it, the easiest option would be to actually enable > > pr_debug, iirc a config option. > > AFAICT we would need to pass -DDEBUG to interesting compilation units. > > > However, the only time we don't get breadcrumbs is if the machine > > spontaneously combusts, which we are told is a mere figment of our > > imagination. Most often I wonder if we simply do not get the death > > throes - adding logging won't help if we don't capture it. For the true > > spontaneous combustion, it's pretty random and all I can think of > > suggesting are more sanity checks to try and catch inconsistencies early. > > Well I was looking at one such log today so hence the patch.. :) But given the number of unexplained skl lockups, looking at a sporadic (if not one off) example as opposed to say gem_cpu_reloc which kills shard-skl every time seems like hunting in the dark. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/atomic: Fix the early return in drm_atomic_set_mode_for_crtc()
== Series Details == Series: drm/atomic: Fix the early return in drm_atomic_set_mode_for_crtc() URL : https://patchwork.freedesktop.org/series/52777/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5174 -> Patchwork_10867 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/52777/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10867 that come from known issues: === IGT changes === Issues hit igt@gem_ctx_create@basic-files: fi-icl-u2: PASS -> DMESG-WARN (fdo#107724) fi-bsw-kefka: PASS -> FAIL (fdo#108656) igt@kms_flip@basic-flip-vs-wf_vblank: fi-bsw-n3050: PASS -> FAIL (fdo#100368) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191) Possible fixes igt@gem_exec_suspend@basic-s3: fi-icl-u2: DMESG-WARN (fdo#107724) -> PASS igt@i915_selftest@live_execlists: fi-apl-guc: DMESG-WARN (fdo#108622) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724 fdo#108622 https://bugs.freedesktop.org/show_bug.cgi?id=108622 fdo#108656 https://bugs.freedesktop.org/show_bug.cgi?id=108656 == Participating hosts (52 -> 45) == Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-u3 fi-icl-y == Build changes == * Linux: CI_DRM_5174 -> Patchwork_10867 CI_DRM_5174: 0bfa7192170c039a271ebc27222b4b91516e73f6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4722: fdcdfa1e220c5070072d5dac9523cd105e7406c2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10867: 3ee4095248db4aa5a00447be02bba09be878caf8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 3ee4095248db drm/atomic: Fix the early return in drm_atomic_set_mode_for_crtc() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10867/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] tests/drv_selftest: Allow passing in module options from the command line
Quoting Chris Wilson (2018-11-20 18:16:53)
> Quoting Tvrtko Ursulin (2018-11-20 18:07:57)
> > From: Tvrtko Ursulin
> >
> > A new option '--kmod-options' is added which takes a string which will be
> > passed to modprobe when loading the module.
> >
> > This for instance allows easy override of things like the random seed when
> > trying to reproduce failures.
>
> Anyway we can simply extend the option parsing locally? (Just find it
> unsightly to have test specific options in libigt.)
>
> Stashing argc/argv in igt_subtest_init_parse_opts() and then being able
> to run getopts inside igt_main {}?
Or perhaps,
#define igt_main_argv \
static void igt_tokencat(__real_main, __LINE__)(int argc, char **argv);
\
int main(int argc, char **argv) { \
igt_subtest_init_parse_opts(, argv, NULL, NULL, NULL, \
NULL, NULL); \
igt_tokencat(__real_main, __LINE__)(argc, char **argv); \
igt_exit(); \
} \
static void igt_tokencat(__real_main, __LINE__)(int argc, char **argv) \
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Re: [Intel-gfx] [PATCH] drm/i915/selftests: Log test and subtest names for easier debugging
On 20/11/2018 18:10, Chris Wilson wrote: > Quoting Tvrtko Ursulin (2018-11-20 17:58:33) >> >> On 20/11/2018 17:33, Chris Wilson wrote: >>> Quoting Tvrtko Ursulin (2018-11-20 17:28:39) From: Tvrtko Ursulin Since pr_debug is not printed by default, change both test and subtest log messages to pr_info so they are always logged. >>> >>> I just use the trace... As when the test fails we say which subtest >>> failed, and hopefully include more details in the error message, and >>> recent history is in the trace dumped when considered relevant. >> >> Fair. My thinking was simply to leave more breadcrumbs if the machine >> died in the middle of a subtest. > > Thinking more about it, the easiest option would be to actually enable > pr_debug, iirc a config option. AFAICT we would need to pass -DDEBUG to interesting compilation units. > However, the only time we don't get breadcrumbs is if the machine > spontaneously combusts, which we are told is a mere figment of our > imagination. Most often I wonder if we simply do not get the death > throes - adding logging won't help if we don't capture it. For the true > spontaneous combustion, it's pretty random and all I can think of > suggesting are more sanity checks to try and catch inconsistencies early. Well I was looking at one such log today so hence the patch.. :) <6>[ 491.437102] i915: Performing live selftests with st_random_seed=0x3bd88daf st_timeout=1000 <7>[ 491.438062] [drm:intel_power_well_enable [i915]] enabling always-on <7>[ 491.438121] [drm:intel_power_well_enable [i915]] enabling DC off <7>[ 491.438509] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 <7>[ 491.541663] [drm:intel_power_well_disable [i915]] disabling DC off <7>[ 491.541722] [drm:skl_enable_dc6 [i915]] Enabling DC6 <7>[ 491.541751] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 <7>[ 491.542180] [drm:intel_power_well_disable [i915]] disabling always-on <7>[ 495.443505] [drm:intel_power_well_enable [i915]] enabling always-on <7>[ 495.443533] [drm:intel_power_well_enable [i915]] enabling DC off <7>[ 495.443817] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 <7>[ 499.549369] [drm:intel_power_well_disable [i915]] disabling DC off <7>[ 499.549403] [drm:skl_enable_dc6 [i915]] Enabling DC6 <7>[ 499.549431] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02 <7>[ 499.549863] [drm:intel_power_well_disable [i915]] disabling always-on <6>[ 500.448268] i915_reset_engine(rcs0:idle): 265564 resets <6>[ 501.449250] i915_reset_engine(bcs0:idle): 249487 resets EOF I can certainly send a patch for -DDEBUG, seems like that would be the correct thing to do for all selftests. Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] tests/drv_selftest: Allow passing in module options from the command line
Quoting Tvrtko Ursulin (2018-11-20 18:07:57)
> From: Tvrtko Ursulin
>
> A new option '--kmod-options' is added which takes a string which will be
> passed to modprobe when loading the module.
>
> This for instance allows easy override of things like the random seed when
> trying to reproduce failures.
Anyway we can simply extend the option parsing locally? (Just find it
unsightly to have test specific options in libigt.)
Stashing argc/argv in igt_subtest_init_parse_opts() and then being able
to run getopts inside igt_main {}?
I also had in mind an env for module options, which may be also useful
for the module reloading and autoloading.
-Chris
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Hold task reference to reset worker
== Series Details ==
Series: drm/i915/selftests: Hold task reference to reset worker
URL : https://patchwork.freedesktop.org/series/52750/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5171_full -> Patchwork_10860_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10860_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10860_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in
Patchwork_10860_full:
=== IGT changes ===
Warnings
igt@kms_content_protection@legacy:
shard-apl: FAIL (fdo#108597) -> DMESG-FAIL
igt@kms_vblank@pipe-a-wait-busy:
shard-snb: SKIP -> PASS +3
igt@perf_pmu@rc6:
shard-kbl: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_10860_full that come from known
issues:
=== IGT changes ===
Issues hit
igt@gem_exec_schedule@pi-ringfull-bsd:
shard-skl: NOTRUN -> FAIL (fdo#103158)
igt@gem_ppgtt@blt-vs-render-ctx0:
shard-skl: PASS -> TIMEOUT (fdo#108039)
igt@i915_suspend@debugfs-reader:
{shard-iclb}: PASS -> INCOMPLETE (fdo#107713) +1
igt@kms_busy@extended-modeset-hang-newfb-render-b:
shard-snb: PASS -> DMESG-WARN (fdo#107956)
igt@kms_color@pipe-b-legacy-gamma:
shard-apl: PASS -> FAIL (fdo#104782)
igt@kms_cursor_crc@cursor-64x21-onscreen:
shard-apl: PASS -> FAIL (fdo#103232) +1
igt@kms_cursor_crc@cursor-64x64-random:
{shard-iclb}: NOTRUN -> FAIL (fdo#103232)
igt@kms_cursor_crc@cursor-size-change:
shard-glk: PASS -> FAIL (fdo#103232)
igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
{shard-iclb}: PASS -> DMESG-WARN (fdo#107724) +8
igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
shard-glk: PASS -> DMESG-WARN (fdo#106538, fdo#105763) +2
igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled:
{shard-iclb}: PASS -> WARN (fdo#108336)
igt@kms_fbcon_fbt@psr:
{shard-iclb}: NOTRUN -> FAIL (fdo#107882)
igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
shard-glk: PASS -> FAIL (fdo#103060)
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
shard-apl: PASS -> FAIL (fdo#103167)
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
shard-glk: PASS -> FAIL (fdo#103167) +1
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
{shard-iclb}: PASS -> FAIL (fdo#103167) +3
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu:
shard-glk: PASS -> DMESG-FAIL (fdo#106538, fdo#105763)
igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-render:
shard-skl: PASS -> FAIL (fdo#103167) +4
igt@kms_frontbuffer_tracking@psr-slowdraw:
{shard-iclb}: PASS -> DMESG-WARN (fdo#107724, fdo#108336) +6
igt@kms_frontbuffer_tracking@psr-suspend:
shard-skl: PASS -> INCOMPLETE (fdo#107773, fdo#106978,
fdo#104108)
igt@kms_hdmi_inject@inject-audio:
{shard-iclb}: NOTRUN -> FAIL (fdo#102370)
igt@kms_plane@pixel-format-pipe-a-planes:
{shard-iclb}: NOTRUN -> FAIL (fdo#103166)
igt@kms_plane@plane-panning-top-left-pipe-a-planes:
shard-apl: PASS -> DMESG-WARN (fdo#103558, fdo#105602) +7
igt@kms_plane@plane-position-covered-pipe-a-planes:
shard-glk: PASS -> FAIL (fdo#103166)
igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
shard-skl: PASS -> FAIL (fdo#108145, fdo#107815)
igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb:
shard-skl: NOTRUN -> FAIL (fdo#108145) +1
igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
shard-apl: PASS -> FAIL (fdo#103166)
igt@kms_vblank@pipe-b-wait-forked-busy-hang:
shard-apl: PASS -> DMESG-FAIL (fdo#103558, fdo#105602)
igt@pm_rpm@sysfs-read:
{shard-iclb}: NOTRUN -> DMESG-WARN (fdo#107724) +1
Possible fixes
igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
shard-hsw: DMESG-WARN (fdo#107956) -> PASS
shard-kbl: DMESG-WARN (fdo#107956) -> PASS
igt@kms_cursor_crc@cursor-128x128-random:
shard-apl: FAIL (fdo#103232) -> PASS +1
igt@kms_cursor_crc@cursor-256x85-onscreen:
shard-glk: FAIL (fdo#103232) -> PASS +3
igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled:
shard-skl: FAIL (fdo#103184) -> PASS
igt@kms_flip@flip-vs-expired-vblank:
shard-skl: FAIL
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Log test and subtest names for easier debugging
Quoting Tvrtko Ursulin (2018-11-20 17:58:33) > > On 20/11/2018 17:33, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2018-11-20 17:28:39) > >> From: Tvrtko Ursulin > >> > >> Since pr_debug is not printed by default, change both test and subtest > >> log messages to pr_info so they are always logged. > > > > I just use the trace... As when the test fails we say which subtest > > failed, and hopefully include more details in the error message, and > > recent history is in the trace dumped when considered relevant. > > Fair. My thinking was simply to leave more breadcrumbs if the machine > died in the middle of a subtest. Thinking more about it, the easiest option would be to actually enable pr_debug, iirc a config option. However, the only time we don't get breadcrumbs is if the machine spontaneously combusts, which we are told is a mere figment of our imagination. Most often I wonder if we simply do not get the death throes - adding logging won't help if we don't capture it. For the true spontaneous combustion, it's pretty random and all I can think of suggesting are more sanity checks to try and catch inconsistencies early. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] tests/drv_selftest: Allow passing in module options from the command line
From: Tvrtko Ursulin
A new option '--kmod-options' is added which takes a string which will be
passed to modprobe when loading the module.
This for instance allows easy override of things like the random seed when
trying to reproduce failures.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_core.c | 9 +
lib/igt_kmod.h | 2 ++
tests/drv_selftest.c | 24 ++--
3 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/lib/igt_core.c b/lib/igt_core.c
index e0989f538aa9..8076d636afa3 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -282,6 +282,7 @@ bool test_child;
enum {
OPT_LIST_SUBTESTS,
OPT_RUN_SUBTEST,
+ OPT_KMOD_OPTIONS,
OPT_DESCRIPTION,
OPT_DEBUG,
OPT_INTERACTIVE_DEBUG,
@@ -302,6 +303,8 @@ GKeyFile *igt_key_file;
char *igt_frame_dump_path;
+char *igt_kmod_options;
+
static bool stderr_needs_sentinel = false;
const char *igt_test_name(void)
@@ -552,6 +555,7 @@ static void print_usage(const char *help_str, bool
output_on_stderr)
" --run-subtest \n"
" --debug[=log-domain]\n"
" --interactive-debug[=domain]\n"
+ " --kmod-options=\n"
" --help-description\n"
" --help\n");
if (help_str)
@@ -660,6 +664,7 @@ static int common_init(int *argc, char **argv,
static struct option long_options[] = {
{"list-subtests", 0, 0, OPT_LIST_SUBTESTS},
{"run-subtest", 1, 0, OPT_RUN_SUBTEST},
+ {"kmod-options", 1, 0, OPT_KMOD_OPTIONS},
{"help-description", 0, 0, OPT_DESCRIPTION},
{"debug", optional_argument, 0, OPT_DEBUG},
{"interactive-debug", optional_argument, 0,
OPT_INTERACTIVE_DEBUG},
@@ -757,6 +762,10 @@ static int common_init(int *argc, char **argv,
if (!list_subtests)
run_single_subtest = strdup(optarg);
break;
+ case OPT_KMOD_OPTIONS:
+ if (!list_subtests)
+ igt_kmod_options = strdup(optarg);
+ break;
case OPT_DESCRIPTION:
print_test_description();
ret = -1;
diff --git a/lib/igt_kmod.h b/lib/igt_kmod.h
index 87d36d400184..e1d286a2e2c1 100644
--- a/lib/igt_kmod.h
+++ b/lib/igt_kmod.h
@@ -28,6 +28,8 @@
#include "igt_list.h"
+extern char *igt_kmod_options;
+
bool igt_kmod_is_loaded(const char *mod_name);
void igt_kmod_list_loaded(void);
diff --git a/tests/drv_selftest.c b/tests/drv_selftest.c
index 80e515c6123b..c67535bf573f 100644
--- a/tests/drv_selftest.c
+++ b/tests/drv_selftest.c
@@ -28,10 +28,22 @@ IGT_TEST_DESCRIPTION("Basic unit tests for i915.ko");
igt_main
{
- igt_kselftests("i915",
- "mock_selftests=-1 disable_display=1",
- NULL, "mock");
- igt_kselftests("i915",
- "live_selftests=-1 disable_display=1",
- "live_selftests", "live");
+ const char *live_opts = "live_selftests=-1 disable_display=1";
+ const char *mock_opts = "mock_selftests=-1 disable_display=1";
+ char *opts;
+ int ret;
+
+ /* Mock selftests */
+
+ ret = asprintf(, "%s %s", mock_opts, igt_kmod_options ?: "");
+ igt_assert(ret > 0);
+ igt_kselftests("i915", opts, NULL, "mock");
+ free(opts);
+
+ /* Live selftests */
+
+ ret = asprintf(, "%s %s", live_opts, igt_kmod_options ?: "");
+ igt_assert(ret > 0);
+ igt_kselftests("i915", opts, "live_selftests", "live");
+ free(opts);
}
--
2.19.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Log test and subtest names for easier debugging
== Series Details == Series: drm/i915/selftests: Log test and subtest names for easier debugging URL : https://patchwork.freedesktop.org/series/52774/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5174 -> Patchwork_10866 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/52774/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10866 that come from known issues: === IGT changes === Issues hit igt@gem_ctx_switch@basic-default: fi-icl-u2: PASS -> DMESG-WARN (fdo#107724) igt@i915_selftest@live_coherency: fi-gdg-551: PASS -> DMESG-FAIL (fdo#107164) igt@i915_selftest@live_hangcheck: fi-bwr-2160:PASS -> DMESG-FAIL (fdo#108735) Possible fixes igt@gem_exec_suspend@basic-s3: fi-icl-u2: DMESG-WARN (fdo#107724) -> PASS igt@i915_selftest@live_execlists: fi-apl-guc: DMESG-WARN (fdo#108622) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164 fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724 fdo#108622 https://bugs.freedesktop.org/show_bug.cgi?id=108622 fdo#108735 https://bugs.freedesktop.org/show_bug.cgi?id=108735 == Participating hosts (52 -> 46) == Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-u3 == Build changes == * Linux: CI_DRM_5174 -> Patchwork_10866 CI_DRM_5174: 0bfa7192170c039a271ebc27222b4b91516e73f6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4722: fdcdfa1e220c5070072d5dac9523cd105e7406c2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10866: 892a393cb77f0051624d17df57e5d53c3ca43ead @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 892a393cb77f drm/i915/selftests: Log test and subtest names for easier debugging == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10866/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Log test and subtest names for easier debugging
On 20/11/2018 17:33, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-11-20 17:28:39) From: Tvrtko Ursulin Since pr_debug is not printed by default, change both test and subtest log messages to pr_info so they are always logged. I just use the trace... As when the test fails we say which subtest failed, and hopefully include more details in the error message, and recent history is in the trace dumped when considered relevant. Fair. My thinking was simply to leave more breadcrumbs if the machine died in the middle of a subtest. Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/atomic: Fix the early return in drm_atomic_set_mode_for_crtc()
From: Ville Syrjälä
The early return in drm_atomic_set_mode_for_crtc() isn't quite
right. It would mistakenly return and fail to update
crtc_state->enable if someone actually tried to set a zeroed
mode on a currently disabled crtc. I suppose that should never
happen but better safe than sorry.
Additionally the early return will not be taken if we're trying to
disable an already disable crtc. While that is not actually harmful
it is inconsistent, so let's handle that case as well.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_atomic_uapi.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 86ac33922b09..ed0ea82e8a1d 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -68,8 +68,13 @@ int drm_atomic_set_mode_for_crtc(struct drm_crtc_state
*state,
struct drm_mode_modeinfo umode;
/* Early return for no change. */
- if (mode && memcmp(>mode, mode, sizeof(*mode)) == 0)
- return 0;
+ if (state->enable) {
+ if (mode && memcmp(>mode, mode, sizeof(*mode)) == 0)
+ return 0;
+ } else {
+ if (!mode)
+ return 0;
+ }
drm_property_blob_put(state->mode_blob);
state->mode_blob = NULL;
--
2.18.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/edid: Add CTA-861-G modes with VIC < 128
== Series Details == Series: series starting with [1/4] drm/edid: Add CTA-861-G modes with VIC < 128 URL : https://patchwork.freedesktop.org/series/52770/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5174 -> Patchwork_10865 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/52770/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10865 that come from known issues: === IGT changes === Issues hit igt@gem_ctx_create@basic-files: fi-icl-u2: PASS -> DMESG-WARN (fdo#107724) igt@i915_module_load@reload: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@i915_selftest@live_coherency: fi-gdg-551: PASS -> DMESG-FAIL (fdo#107164) igt@i915_selftest@live_contexts: fi-bsw-n3050: PASS -> DMESG-FAIL (fdo#108626, fdo#108656) igt@i915_selftest@live_gtt: fi-kbl-7560u: PASS -> INCOMPLETE (fdo#108790) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) Possible fixes igt@gem_exec_suspend@basic-s3: fi-icl-u2: DMESG-WARN (fdo#107724) -> PASS igt@i915_selftest@live_execlists: fi-apl-guc: DMESG-WARN (fdo#108622) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724 fdo#108622 https://bugs.freedesktop.org/show_bug.cgi?id=108622 fdo#108626 https://bugs.freedesktop.org/show_bug.cgi?id=108626 fdo#108656 https://bugs.freedesktop.org/show_bug.cgi?id=108656 fdo#108790 https://bugs.freedesktop.org/show_bug.cgi?id=108790 == Participating hosts (52 -> 46) == Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-u3 == Build changes == * Linux: CI_DRM_5174 -> Patchwork_10865 CI_DRM_5174: 0bfa7192170c039a271ebc27222b4b91516e73f6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4722: fdcdfa1e220c5070072d5dac9523cd105e7406c2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10865: 36ada60c39cee864aa747377eb5dacc014673c73 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 36ada60c39ce drm/edid: Throw away the dummy VIC 0 cea mode 2c9a6aa49973 drm/edid: Add CTA-861-G modes with VIC >= 193 4214536fc50e drm/edid: Abstract away cea_edid_modes[] 4fec2531580e drm/edid: Add CTA-861-G modes with VIC < 128 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10865/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Log test and subtest names for easier debugging
Quoting Tvrtko Ursulin (2018-11-20 17:28:39) > From: Tvrtko Ursulin > > Since pr_debug is not printed by default, change both test and subtest > log messages to pr_info so they are always logged. I just use the trace... As when the test fails we say which subtest failed, and hopefully include more details in the error message, and recent history is in the trace dumped when considered relevant. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/selftests: Log test and subtest names for easier debugging
From: Tvrtko Ursulin
Since pr_debug is not printed by default, change both test and subtest
log messages to pr_info so they are always logged.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/selftests/i915_selftest.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_selftest.c
b/drivers/gpu/drm/i915/selftests/i915_selftest.c
index 86c54ea37f48..0fa4501c4599 100644
--- a/drivers/gpu/drm/i915/selftests/i915_selftest.c
+++ b/drivers/gpu/drm/i915/selftests/i915_selftest.c
@@ -133,7 +133,7 @@ static int __run_selftests(const char *name,
if (signal_pending(current))
return -EINTR;
- pr_debug(DRIVER_NAME ": Running %s\n", st->name);
+ pr_info(DRIVER_NAME ": Running %s\n", st->name);
if (data)
err = st->live(data);
else
@@ -209,7 +209,7 @@ int __i915_subtests(const char *caller,
if (signal_pending(current))
return -EINTR;
- pr_debug(DRIVER_NAME ": Running %s/%s\n", caller, st->name);
+ pr_info(DRIVER_NAME ": Running %s/%s\n", caller, st->name);
GEM_TRACE("Running %s/%s\n", caller, st->name);
err = st->func(data);
--
2.19.1
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Re: [Intel-gfx] [PATCH v9 22/24] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
On Mon, Nov 19, 2018 at 10:19:42PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 13, 2018 at 05:52:30PM -0800, Manasi Navare wrote:
> > From: Anusha Srivatsa
> >
> > If the panel supports FEC, the driver has to
> > set the FEC_READY bit in the dpcd register:
> > FEC_CONFIGURATION.
> >
> > This has to happen before link training.
> >
> > v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
> >- change commit message. (Gaurav)
> >
> > v3: rebased. (r-b Manasi)
> >
> > v4: Use fec crtc state, before setting FEC_READY
> > bit. (Anusha)
> >
> > v5: Move to intel_ddi.c
> > - Make the function static (Anusha)
> >
> > v6: Dont pass state as a separate argument (Ville)
> >
> > Cc: dri-de...@lists.freedesktop.org
> > Cc: Gaurav K Singh
> > Cc: Jani Nikula
> > Cc: Ville Syrjala
> > Cc: Manasi Navare
> > Signed-off-by: Anusha Srivatsa
> > Reviewed-by: Manasi Navare
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 11 +++
> > 1 file changed, 11 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index 0638fd2febfb..2d15520f13c5 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -3102,6 +3102,16 @@ static void icl_program_mg_dp_mode(struct
> > intel_digital_port *intel_dig_port)
> > I915_WRITE(MG_DP_MODE(port, 1), ln1);
> > }
> >
> > +static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
> > + const struct intel_crtc_state
> > *crtc_state)
> > +{
> > + if (!crtc_state->fec_enable)
> > + return;
> > +
> > + if (drm_dp_dpcd_writeb(_dp->aux, DP_FEC_CONFIGURATION,
> > DP_FEC_READY) <= 0)
> > + DRM_DEBUG_KMS("Failed to get FEC enabled in sink\n");
>
> The debug message is still bonkers.
Should I get rid of the debug message here?
Manasi
>
> > +}
> > +
> > static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state,
> > const struct drm_connector_state
> > *conn_state)
> > @@ -3142,6 +3152,7 @@ static void intel_ddi_pre_enable_dp(struct
> > intel_encoder *encoder,
> > intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> > intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
> > true);
> > + intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
> > intel_dp_start_link_train(intel_dp);
> > if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
> > intel_dp_stop_link_train(intel_dp);
> > --
> > 2.19.1
>
> --
> Ville Syrjälä
> Intel
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/edid: Add CTA-861-G modes with VIC < 128
== Series Details == Series: series starting with [1/4] drm/edid: Add CTA-861-G modes with VIC < 128 URL : https://patchwork.freedesktop.org/series/52770/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4fec2531580e drm/edid: Add CTA-861-G modes with VIC < 128 4214536fc50e drm/edid: Abstract away cea_edid_modes[] -:131: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "cea_mode_for_vic" #131: FILE: drivers/gpu/drm/drm_edid.c:3146: + return cea_mode_for_vic(vic) != NULL; total: 0 errors, 0 warnings, 1 checks, 152 lines checked 2c9a6aa49973 drm/edid: Add CTA-861-G modes with VIC >= 193 36ada60c39ce drm/edid: Throw away the dummy VIC 0 cea mode ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/edid: Pass connector to AVI inforframe functions
== Series Details == Series: series starting with [1/4] drm/edid: Pass connector to AVI inforframe functions URL : https://patchwork.freedesktop.org/series/52767/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5174 -> Patchwork_10864 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/52767/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10864 that come from known issues: === IGT changes === Issues hit igt@gem_ctx_switch@basic-default: fi-icl-u2: PASS -> DMESG-WARN (fdo#107724) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) Possible fixes igt@gem_exec_suspend@basic-s3: fi-icl-u2: DMESG-WARN (fdo#107724) -> PASS igt@i915_selftest@live_execlists: fi-apl-guc: DMESG-WARN (fdo#108622) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724 fdo#108622 https://bugs.freedesktop.org/show_bug.cgi?id=108622 == Participating hosts (52 -> 45) == Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-u3 fi-icl-y == Build changes == * Linux: CI_DRM_5174 -> Patchwork_10864 CI_DRM_5174: 0bfa7192170c039a271ebc27222b4b91516e73f6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4722: fdcdfa1e220c5070072d5dac9523cd105e7406c2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10864: ceb81320d146bab4e835083c29ad14f3444cd080 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ceb81320d146 drm/edid: Add display_info.rgb_quant_range_selectable 9be3dca0d438 drm/radeon: Use drm_hdmi_avi_infoframe_quant_range() 25296a851990 drm/i915: Use drm_hdmi_avi_infoframe_quant_range() for SDVO HDMI as well 3b5027b538c5 drm/edid: Pass connector to AVI inforframe functions == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10864/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/4] drm/edid: Throw away the dummy VIC 0 cea mode
From: Ville Syrjälä
Now that the cea mode handling is not 100% tied to the single
array the dummy VIC 0 mode is pretty much pointles. Throw it
out.
Cc: Hans Verkuil
Cc: Shashank Sharma
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 1def8dd8fdf3..1879ea68ee53 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -691,11 +691,9 @@ static const struct minimode extra_modes[] = {
/*
* From CEA/CTA-861 spec.
*
- * Index with VIC.
+ * Index with VIC-1.
*/
-static const struct drm_display_mode edid_cea_modes_0[] = {
- /* 0 - dummy, VICs start at 1 */
- { },
+static const struct drm_display_mode edid_cea_modes_1[] = {
/* 1 - 640x480@60Hz 4:3 */
{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
752, 800, 0, 480, 490, 492, 525, 0,
@@ -3122,10 +3120,8 @@ static u8 *drm_find_displayid_extension(const struct
edid *edid)
static const struct drm_display_mode *cea_mode_for_vic(u8 vic)
{
- if (!vic)
- return NULL;
- if (vic < ARRAY_SIZE(edid_cea_modes_0))
- return _cea_modes_0[vic];
+ if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
+ return _cea_modes_1[vic - 1];
if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
return _cea_modes_193[vic - 193];
return NULL;
@@ -3138,7 +3134,7 @@ static u8 cea_num_vics(void)
static u8 cea_next_vic(u8 vic)
{
- if (++vic == ARRAY_SIZE(edid_cea_modes_0))
+ if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
vic = 193;
return vic;
}
--
2.18.1
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