[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v3,1/4] drm/i915/psr: Allow PSR2 to be enabled when debugfs asks
== Series Details ==
Series: series starting with [v3,1/4] drm/i915/psr: Allow PSR2 to be enabled
when debugfs asks
URL : https://patchwork.freedesktop.org/series/55097/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5405_full -> Patchwork_11286_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_11286_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_fbcon_fbt@psr-suspend:
- shard-iclb: FAIL [fdo#107882] -> {SKIP} +1
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite:
- shard-iclb: PASS -> {SKIP} +144
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc:
- shard-iclb: NOTRUN -> {SKIP} +4
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move:
- shard-iclb: FAIL [fdo#103167] -> {SKIP} +3
* igt@kms_psr@suspend:
- shard-iclb: INCOMPLETE [fdo#107713] -> {SKIP}
Known issues
Here are the changes found in Patchwork_11286_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@pi-ringfull-bsd:
- shard-skl: NOTRUN -> FAIL [fdo#103158]
* igt@gem_exec_schedule@pi-ringfull-vebox:
- shard-kbl: NOTRUN -> FAIL [fdo#103158] +4
* igt@gem_exec_suspend@basic-s3-devices:
- shard-kbl: NOTRUN -> DMESG-WARN [fdo#103558] / [fdo#105079] /
[fdo#105602]
* igt@i915_suspend@forcewake:
- shard-snb: PASS -> INCOMPLETE [fdo#105411]
* igt@i915_suspend@shrink:
- shard-kbl: NOTRUN -> DMESG-WARN [fdo#109244]
* igt@kms_atomic_transition@plane-all-transition:
- shard-kbl: NOTRUN -> DMESG-WARN [fdo#103558] / [fdo#105602] /
[fdo#109225]
* igt@kms_available_modes_crc@available_mode_test_crc:
- shard-kbl: NOTRUN -> FAIL [fdo#106641]
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-iclb: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +2
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-kbl: NOTRUN -> DMESG-WARN [fdo#107956] +8
* igt@kms_chv_cursor_fail@pipe-c-128x128-top-edge:
- shard-skl: PASS -> FAIL [fdo#104671]
* igt@kms_color@pipe-c-ctm-blue-to-red:
- shard-skl: PASS -> FAIL [fdo#107201]
* igt@kms_content_protection@atomic:
- shard-kbl: NOTRUN -> FAIL [fdo#108597] +1
* igt@kms_cursor_crc@cursor-128x128-onscreen:
- shard-kbl: NOTRUN -> FAIL [fdo#103232] +1
* igt@kms_cursor_crc@cursor-128x128-random:
- shard-skl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-256x256-random:
- shard-iclb: NOTRUN -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x21-onscreen:
- shard-kbl: NOTRUN -> DMESG-WARN [fdo#103558] / [fdo#105602] +16
* igt@kms_cursor_crc@cursor-64x64-onscreen:
- shard-glk: PASS -> FAIL [fdo#103232] +1
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-kbl: NOTRUN -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_draw_crc@draw-method-xrgb-mmap-gtt-xtiled:
- shard-glk: PASS -> FAIL [fdo#107791]
* igt@kms_flip@dpms-vs-vblank-race-interruptible:
- shard-apl: PASS -> FAIL [fdo#103060]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- shard-iclb: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
- shard-apl: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-kbl: NOTRUN -> FAIL [fdo#103167]
* igt@kms_plane@pixel-format-pipe-b-planes:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] +2
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb:
- shard-kbl: NOTRUN -> FAIL [fdo#108145] +8
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815]
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> FAIL [fdo#108145] / [fdo#108590] +4
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-kbl: NOTRUN -> DMESG-FAIL [fdo#103558] / [fdo#105602] /
[fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +3
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: PASS -> FAIL
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: GTT remapping for display
== Series Details == Series: drm/i915: GTT remapping for display URL : https://patchwork.freedesktop.org/series/55095/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5405_full -> Patchwork_11285_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_11285_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_11285_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_11285_full: ### IGT changes ### Possible regressions * igt@i915_selftest@mock_vma: - shard-iclb: PASS -> INCOMPLETE Known issues Here are the changes found in Patchwork_11285_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@pi-ringfull-bsd: - shard-skl: NOTRUN -> FAIL [fdo#103158] +1 * igt@gem_exec_schedule@pi-ringfull-vebox: - shard-kbl: NOTRUN -> FAIL [fdo#103158] +4 * igt@i915_selftest@mock_vma: - shard-hsw: PASS -> INCOMPLETE [fdo#103540] - shard-apl: PASS -> INCOMPLETE [fdo#103927] - shard-glk: PASS -> INCOMPLETE [fdo#103359] / [k.org#198133] - shard-snb: PASS -> INCOMPLETE [fdo#105411] * igt@i915_suspend@shrink: - shard-kbl: NOTRUN -> DMESG-WARN [fdo#109244] * igt@kms_available_modes_crc@available_mode_test_crc: - shard-kbl: NOTRUN -> FAIL [fdo#106641] * igt@kms_busy@extended-modeset-hang-newfb-render-a: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +2 * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c: - shard-kbl: NOTRUN -> DMESG-WARN [fdo#107956] +8 * igt@kms_chv_cursor_fail@pipe-a-256x256-bottom-edge: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +1 * igt@kms_chv_cursor_fail@pipe-c-128x128-top-edge: - shard-skl: PASS -> FAIL [fdo#104671] * igt@kms_color@pipe-c-ctm-blue-to-red: - shard-skl: PASS -> FAIL [fdo#107201] * igt@kms_content_protection@atomic: - shard-kbl: NOTRUN -> FAIL [fdo#108597] +1 * igt@kms_cursor_crc@cursor-128x128-onscreen: - shard-kbl: NOTRUN -> FAIL [fdo#103232] +1 * igt@kms_cursor_crc@cursor-256x256-random: - shard-iclb: NOTRUN -> FAIL [fdo#103232] * igt@kms_cursor_crc@cursor-256x85-random: - shard-apl: PASS -> FAIL [fdo#103232] +5 - shard-glk: PASS -> FAIL [fdo#103232] * igt@kms_cursor_crc@cursor-64x64-suspend: - shard-kbl: NOTRUN -> FAIL [fdo#103191] / [fdo#103232] * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: NOTRUN -> FAIL [fdo#105363] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-iclb: PASS -> FAIL [fdo#103167] +6 - shard-apl: PASS -> FAIL [fdo#103167] +3 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move: - shard-kbl: NOTRUN -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu: - shard-glk: PASS -> FAIL [fdo#103167] +2 * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu: - shard-iclb: PASS -> DMESG-FAIL [fdo#107724] +2 * igt@kms_plane@pixel-format-pipe-b-planes: - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] +2 * igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb: - shard-kbl: NOTRUN -> FAIL [fdo#108145] +8 * igt@kms_plane_alpha_blend@pipe-c-alpha-7efc: - shard-kbl: NOTRUN -> FAIL [fdo#108145] / [fdo#108590] +5 * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb: - shard-skl: NOTRUN -> FAIL [fdo#108145] +2 * igt@kms_plane_multiple@atomic-pipe-a-tiling-yf: - shard-glk: PASS -> FAIL [fdo#103166] * igt@kms_plane_multiple@atomic-pipe-b-tiling-none: - shard-apl: PASS -> FAIL [fdo#103166] +1 * igt@kms_plane_multiple@atomic-pipe-b-tiling-y: - shard-iclb: PASS -> FAIL [fdo#103166] +4 * igt@kms_plane_multiple@atomic-pipe-c-tiling-x: - shard-kbl: NOTRUN -> FAIL [fdo#103166] +1 * igt@kms_rmfb@close-fd: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] +13 * igt@kms_setmode@basic: - shard-skl: NOTRUN -> FAIL [fdo#99912] * igt@kms_sysfs_edid_timing: - shard-kbl: NOTRUN -> FAIL [fdo#100047] - shard-skl: NOTRUN -> FAIL [fdo#100047] * igt@kms_vblank@pipe-b-ts-continuation-suspend: - shard-hsw: PASS
Re: [Intel-gfx] [PATCH 05/13] drm/i915: Pull GAMMA_MODE write out from haswell_load_luts()
On Fri, Jan 11, 2019 at 07:08:15PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> For bdw+ let's move the GAMMA_MODE write for the legacy LUT
> mode into the .load_luts() funciton directly, rather than
> relying on haswell_load_luts(). We'll be getting rid of
> haswell_load_luts() entirely soon, and it's anyway cleaner
> to have the GAMMA_MODE write in a single place.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/intel_color.c | 36 +-
> 1 file changed, 20 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index 0dfd104b89d7..df3567686c45 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -473,21 +473,20 @@ static void broadwell_load_luts(const struct
> intel_crtc_state *crtc_state)
> enum pipe pipe = crtc->pipe;
>
> if (crtc_state_is_legacy_gamma(crtc_state)) {
> - haswell_load_luts(crtc_state);
> - return;
> - }
> + i9xx_load_luts(crtc_state);
> + } else {
> + bdw_load_degamma_lut(crtc_state);
> + bdw_load_gamma_lut(crtc_state,
> +
> INTEL_INFO(dev_priv)->color.degamma_lut_size);
>
> - bdw_load_degamma_lut(crtc_state);
> - bdw_load_gamma_lut(crtc_state,
> -INTEL_INFO(dev_priv)->color.degamma_lut_size);
> + /*
> + * Reset the index, otherwise it prevents the legacy palette to
> be
> + * written properly.
> + */
> + I915_WRITE(PREC_PAL_INDEX(pipe), 0);
> + }
>
> I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
> -
> - /*
> - * Reset the index, otherwise it prevents the legacy palette to be
> - * written properly.
> - */
> - I915_WRITE(PREC_PAL_INDEX(pipe), 0);
> }
>
> static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
> @@ -530,11 +529,16 @@ static void glk_load_luts(const struct intel_crtc_state
> *crtc_state)
> glk_load_degamma_lut(crtc_state);
>
> if (crtc_state_is_legacy_gamma(crtc_state)) {
> - haswell_load_luts(crtc_state);
> - return;
> - }
> + i9xx_load_luts(crtc_state);
> + } else {
> + bdw_load_gamma_lut(crtc_state, 0);
>
> - bdw_load_gamma_lut(crtc_state, 0);
> + /*
> + * Reset the index, otherwise it prevents the legacy palette to
> be
> + * written properly.
> + */
> + I915_WRITE(PREC_PAL_INDEX(pipe), 0);
> + }
>
> I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
> }
> --
> 2.19.2
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
___
Intel-gfx mailing list
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Re: [Intel-gfx] [PATCH 02/13] drm/i915: Split the gamma/csc enable bits from the plane_ctl() function
On Fri, Jan 11, 2019 at 07:08:12PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On g4x+ the pipe gamma enable bit for the primary plane affects
> the pipe bottom color as well. The same for the pipe csc enable
> bit on ilk+. Thus we must configure those bits correctly even
> when the primary plane is disabled.
This is only true for https://patchwork.freedesktop.org/patch/271109/
> To make the feasible let's split those settings from the
> plane_ctl() function into a seprate funciton that we can
> call from the ->disable_plane() hook as well.
Is calling it from ->disable_plane() enough? If we just disable the
primary plane, then those bits will remain set while the crtc remains
active. But if you then disable the whole crtc and re-enable it again
later, won't we have lost the bits at that point?
Matt
>
> For consistency we'll do that on all the plane types. While
> that has no real benefits at this time, it'll become useful
> when we start to control the pipe gamma/csc enable bits
> dynamically when we overhaul the color management code.
>
> On pre-g4x there doesn't appear to be any way to gamma
> correct the pipe bottom color, but sticking to the same
> pattern doesn't hurt. And it'll still help us to do
> crtc state readout correctly for the pipe gamma enable
> bit for the color management overhaul.
>
> An alternative apporach would be to still precompute these
> bits into plane_state->ctl, but that would require that we
> run through the plane check even when the plane isn't logically
> enabled on any crtc. Currently that condition causes us to
> short circuit the entire thing and not call ->check_plane().
> There would also be some chicken and egg problems with
> ->check_plane() vs. crtc color state check that would
> requite splitting certain things into multiple steps.
> So all in all this seems like the easier route.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 128 ---
> drivers/gpu/drm/i915/intel_drv.h | 3 +-
> drivers/gpu/drm/i915/intel_sprite.c | 54 ---
> 3 files changed, 139 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 5dc0de89c49e..a3871db4703b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3180,28 +3180,38 @@ i9xx_plane_max_stride(struct intel_plane *plane,
> }
> }
>
> +static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + u32 dspcntr = 0;
> +
> + dspcntr |= DISPPLANE_GAMMA_ENABLE;
> +
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> + dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
> +
> + if (INTEL_GEN(dev_priv) < 5)
> + dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
> +
> + return dspcntr;
> +}
> +
> static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv =
> to_i915(plane_state->base.plane->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> const struct drm_framebuffer *fb = plane_state->base.fb;
> unsigned int rotation = plane_state->base.rotation;
> u32 dspcntr;
>
> - dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
> + dspcntr = DISPLAY_PLANE_ENABLE;
>
> if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
> IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
> dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
>
> - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> - dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
> -
> - if (INTEL_GEN(dev_priv) < 5)
> - dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
> -
> switch (fb->format->format) {
> case DRM_FORMAT_C8:
> dspcntr |= DISPPLANE_8BPP;
> @@ -3329,11 +3339,13 @@ static void i9xx_update_plane(struct intel_plane
> *plane,
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> u32 linear_offset;
> - u32 dspcntr = plane_state->ctl;
> int x = plane_state->color_plane[0].x;
> int y = plane_state->color_plane[0].y;
> unsigned long irqflags;
> u32 dspaddr_offset;
> + u32 dspcntr;
> +
> + dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
>
> linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
>
> @@ -3393,10 +3405,23 @@ static void i9xx_disable_plane(struct intel_plane
> *plane,
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> unsigned long irqflags;
> + u32 dspcntr;
> +
> +
Re: [Intel-gfx] [PATCH 01/13] drm/i915: Clean up intel_plane_atomic_check_with_state()
On Fri, Jan 11, 2019 at 07:08:11PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Rename some of the state variables in
> intel_plane_atomic_check_with_state() to make it less confusing.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/intel_atomic_plane.c | 36 +++
> 1 file changed, 17 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index 683a75dad4fb..50be2c5dd76e 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -110,41 +110,39 @@ intel_plane_destroy_state(struct drm_plane *plane,
> }
>
> int intel_plane_atomic_check_with_state(const struct intel_crtc_state
> *old_crtc_state,
> - struct intel_crtc_state *crtc_state,
> + struct intel_crtc_state *new_crtc_state,
> const struct intel_plane_state
> *old_plane_state,
> - struct intel_plane_state *intel_state)
> + struct intel_plane_state
> *new_plane_state)
> {
> - struct drm_plane *plane = intel_state->base.plane;
> - struct drm_plane_state *state = _state->base;
> - struct intel_plane *intel_plane = to_intel_plane(plane);
> + struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
> int ret;
>
> - crtc_state->active_planes &= ~BIT(intel_plane->id);
> - crtc_state->nv12_planes &= ~BIT(intel_plane->id);
> - intel_state->base.visible = false;
> + new_crtc_state->active_planes &= ~BIT(plane->id);
> + new_crtc_state->nv12_planes &= ~BIT(plane->id);
> + new_plane_state->base.visible = false;
>
> - /* If this is a cursor plane, no further checks are needed. */
> - if (!intel_state->base.crtc && !old_plane_state->base.crtc)
> + if (!new_plane_state->base.crtc && !old_plane_state->base.crtc)
> return 0;
>
> - ret = intel_plane->check_plane(crtc_state, intel_state);
> + ret = plane->check_plane(new_crtc_state, new_plane_state);
> if (ret)
> return ret;
>
> /* FIXME pre-g4x don't work like this */
> - if (state->visible)
> - crtc_state->active_planes |= BIT(intel_plane->id);
> + if (new_plane_state->base.visible)
> + new_crtc_state->active_planes |= BIT(plane->id);
>
> - if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
> - crtc_state->nv12_planes |= BIT(intel_plane->id);
> + if (new_plane_state->base.visible &&
> + new_plane_state->base.fb->format->format == DRM_FORMAT_NV12)
> + new_crtc_state->nv12_planes |= BIT(plane->id);
>
> - if (state->visible || old_plane_state->base.visible)
> - crtc_state->update_planes |= BIT(intel_plane->id);
> + if (new_plane_state->base.visible || old_plane_state->base.visible)
> + new_crtc_state->update_planes |= BIT(plane->id);
>
> return intel_plane_atomic_calc_changes(old_crtc_state,
> -_state->base,
> +_crtc_state->base,
> old_plane_state,
> -state);
> +_plane_state->base);
> }
>
> static int intel_plane_atomic_check(struct drm_plane *plane,
> --
> 2.19.2
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH 04/13] drm/i915: Constify the state arguments to the color management stuff
On Fri, Jan 11, 2019 at 07:08:14PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Pass the crtc state etc. as const to the color management commit
> functions. And while at it polish some of the local variables.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_drv.h| 4 +-
> drivers/gpu/drm/i915/intel_color.c | 128 -
> drivers/gpu/drm/i915/intel_drv.h | 4 +-
> 3 files changed, 73 insertions(+), 63 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5df26ccda8a4..7182a580002c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -320,8 +320,8 @@ struct drm_i915_display_funcs {
> /* display clock increase/decrease */
> /* pll clock increase/decrease */
>
> - void (*load_csc_matrix)(struct intel_crtc_state *crtc_state);
> - void (*load_luts)(struct intel_crtc_state *crtc_state);
> + void (*load_csc_matrix)(const struct intel_crtc_state *crtc_state);
> + void (*load_luts)(const struct intel_crtc_state *crtc_state);
> };
>
> #define CSR_VERSION(major, minor)((major) << 16 | (minor))
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index b10e66ce3970..0dfd104b89d7 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -74,12 +74,12 @@
> #define ILK_CSC_COEFF_1_0\
> ((7 << 12) | ILK_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
>
> -static bool lut_is_legacy(struct drm_property_blob *lut)
> +static bool lut_is_legacy(const struct drm_property_blob *lut)
> {
> return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH;
> }
>
> -static bool crtc_state_is_legacy_gamma(struct intel_crtc_state *crtc_state)
> +static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state
> *crtc_state)
> {
> return !crtc_state->base.degamma_lut &&
> !crtc_state->base.ctm &&
> @@ -115,8 +115,8 @@ static u64 *ctm_mult_by_limited(u64 *result, const u64
> *input)
>
> static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
> {
> - int pipe = crtc->pipe;
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
>
> I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
> I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
> @@ -137,13 +137,14 @@ static void ilk_load_ycbcr_conversion_matrix(struct
> intel_crtc *crtc)
> I915_WRITE(PIPE_CSC_MODE(pipe), 0);
> }
>
> -static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state)
> +static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - int i, pipe = crtc->pipe;
> - uint16_t coeffs[9] = { 0, };
> bool limited_color_range = false;
> + enum pipe pipe = crtc->pipe;
> + u16 coeffs[9] = {};
> + int i;
>
> /*
>* FIXME if there's a gamma LUT after the CSC, we should
> @@ -256,15 +257,15 @@ static void ilk_load_csc_matrix(struct intel_crtc_state
> *crtc_state)
> /*
> * Set up the pipe CSC unit on CherryView.
> */
> -static void cherryview_load_csc_matrix(struct intel_crtc_state *crtc_state)
> +static void cherryview_load_csc_matrix(const struct intel_crtc_state
> *crtc_state)
> {
> - struct drm_device *dev = crtc_state->base.crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - int pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> uint32_t mode;
>
> if (crtc_state->base.ctm) {
> - struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
> + const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
> uint16_t coeffs[9] = { 0, };
> int i;
>
> @@ -303,18 +304,17 @@ static void cherryview_load_csc_matrix(struct
> intel_crtc_state *crtc_state)
> I915_WRITE(CGM_PIPE_MODE(pipe), mode);
> }
>
> -void intel_color_set_csc(struct intel_crtc_state *crtc_state)
> +void intel_color_set_csc(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_device *dev = crtc_state->base.crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>
> if (dev_priv->display.load_csc_matrix)
> dev_priv->display.load_csc_matrix(crtc_state);
> }
>
> /* Loads the legacy palette/gamma unit for the CRTC. */
> -static void i9xx_load_luts_internal(struct intel_crtc_state *crtc_state,
> - struct drm_property_blob *blob)
> +static void i9xx_load_luts_internal(const
Re: [Intel-gfx] [PATCH 03/13] drm/i915: Precompute gamma_mode
On Fri, Jan 11, 2019 at 07:08:13PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We shouldn't be computing gamma mode during the commit phase.
> Move it to the check phase.
>
> Signed-off-by: Ville Syrjälä
Looks like this also drops the posting reads, but I don't see anything
in the bspec that indicates those were necessary in the first place.
> ---
> drivers/gpu/drm/i915/intel_color.c | 44 +-
> 1 file changed, 25 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index 37fd9ddf762e..b10e66ce3970 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -375,8 +375,7 @@ static void haswell_load_luts(struct intel_crtc_state
> *crtc_state)
> reenable_ips = true;
> }
>
> - crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
> - I915_WRITE(GAMMA_MODE(crtc->pipe), GAMMA_MODE_MODE_8BIT);
> + I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
>
> i9xx_load_luts(crtc_state);
>
> @@ -476,9 +475,7 @@ static void broadwell_load_luts(struct intel_crtc_state
> *crtc_state)
> bdw_load_gamma_lut(crtc_state,
> INTEL_INFO(dev_priv)->color.degamma_lut_size);
>
> - crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
> - I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);
> - POSTING_READ(GAMMA_MODE(pipe));
> + I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
>
> /*
>* Reset the index, otherwise it prevents the legacy palette to be
> @@ -532,9 +529,7 @@ static void glk_load_luts(struct intel_crtc_state
> *crtc_state)
>
> bdw_load_gamma_lut(crtc_state, 0);
>
> - crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
> - I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT);
> - POSTING_READ(GAMMA_MODE(pipe));
> + I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
> }
>
> /* Loads the palette/gamma unit for the CRTC on CherryView. */
> @@ -608,29 +603,40 @@ void intel_color_load_luts(struct intel_crtc_state
> *crtc_state)
> int intel_color_check(struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> + const struct drm_property_blob *degamma_lut =
> crtc_state->base.degamma_lut;
> size_t gamma_length, degamma_length;
>
> degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>
> /*
> - * We allow both degamma & gamma luts at the right size or
> - * NULL.
> + * We also allow no degamma lut/ctm and a gamma lut at the legacy
> + * size (256 entries).
>*/
Minor nit: now that the order of tests is swapped, you probably want
to move the "also" from this comment down to the one below.
Otherwise,
Reviewed-by: Matt Roper
> - if ((!crtc_state->base.degamma_lut ||
> - drm_color_lut_size(crtc_state->base.degamma_lut) ==
> degamma_length) &&
> - (!crtc_state->base.gamma_lut ||
> - drm_color_lut_size(crtc_state->base.gamma_lut) == gamma_length))
> + if (crtc_state_is_legacy_gamma(crtc_state)) {
> + crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
> return 0;
> + }
>
> /*
> - * We also allow no degamma lut/ctm and a gamma lut at the legacy
> - * size (256 entries).
> + * We allow both degamma & gamma luts at the right size or
> + * NULL.
>*/
> - if (crtc_state_is_legacy_gamma(crtc_state))
> - return 0;
> + if (degamma_lut && drm_color_lut_size(degamma_lut) != degamma_length)
> + return -EINVAL;
> +
> + if (gamma_lut && drm_color_lut_size(gamma_lut) != gamma_length)
> + return -EINVAL;
> +
> + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
> + else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> + crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
> + else
> + crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
>
> - return -EINVAL;
> + return 0;
> }
>
> void intel_color_init(struct intel_crtc *crtc)
> --
> 2.19.2
>
--
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IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/cmdparser: whitelist needed predicate registers for Anv (rev2)
== Series Details == Series: drm/i915/cmdparser: whitelist needed predicate registers for Anv (rev2) URL : https://patchwork.freedesktop.org/series/55083/ State : success == Summary == CI Bug Log - changes from CI_DRM_5404_full -> Patchwork_11284_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_11284_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@pi-ringfull-render: - shard-skl: NOTRUN -> FAIL [fdo#103158] +1 * igt@i915_selftest@live_workarounds: - shard-iclb: PASS -> DMESG-FAIL [fdo#108954] * igt@kms_atomic_transition@plane-all-transition-nonblocking-fencing: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#109225] * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] - shard-hsw: PASS -> DMESG-WARN [fdo#107956] * igt@kms_color@pipe-a-degamma: - shard-skl: PASS -> FAIL [fdo#104782] / [fdo#108145] * igt@kms_color@pipe-c-ctm-blue-to-red: - shard-apl: PASS -> INCOMPLETE [fdo#103927] * igt@kms_cursor_crc@cursor-128x42-offscreen: - shard-skl: NOTRUN -> FAIL [fdo#103232] * igt@kms_cursor_crc@cursor-256x85-sliding: - shard-glk: PASS -> FAIL [fdo#103232] +1 * igt@kms_cursor_crc@cursor-64x64-random: - shard-iclb: NOTRUN -> FAIL [fdo#103232] * igt@kms_fbcon_fbt@psr: - shard-skl: NOTRUN -> FAIL [fdo#107882] * igt@kms_flip@2x-flip-vs-panning-vs-hang-interruptible: - shard-hsw: PASS -> INCOMPLETE [fdo#103540] * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: NOTRUN -> FAIL [fdo#105363] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render: - shard-apl: PASS -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@fbc-1p-rte: - shard-apl: PASS -> FAIL [fdo#103167] / [fdo#105682] * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite: - shard-glk: PASS -> FAIL [fdo#103167] +3 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render: - shard-iclb: PASS -> DMESG-FAIL [fdo#107724] * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +3 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen: - shard-iclb: PASS -> FAIL [fdo#103167] +2 * igt@kms_panel_fitting@legacy: - shard-skl: NOTRUN -> FAIL [fdo#105456] * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping: - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] - shard-iclb: NOTRUN -> FAIL [fdo#108948] * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: - shard-skl: NOTRUN -> FAIL [fdo#108145] +2 * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: PASS -> FAIL [fdo#107815] * igt@kms_plane_multiple@atomic-pipe-a-tiling-yf: - shard-glk: PASS -> FAIL [fdo#103166] * igt@kms_plane_multiple@atomic-pipe-c-tiling-none: - shard-iclb: PASS -> FAIL [fdo#103166] * igt@kms_rmfb@rmfb-ioctl: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] +10 Possible fixes * igt@gem_ctx_isolation@vecs0-dirty-switch: - shard-apl: INCOMPLETE [fdo#103927] -> PASS * igt@kms_cursor_crc@cursor-128x128-random: - shard-skl: FAIL [fdo#103232] -> PASS * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-skl: INCOMPLETE [fdo#104108] -> PASS * igt@kms_cursor_crc@cursor-256x85-random: - shard-glk: FAIL [fdo#103232] -> PASS * igt@kms_cursor_crc@cursor-64x21-random: - shard-apl: FAIL [fdo#103232] -> PASS +5 * igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled: - shard-skl: FAIL [fdo#103184] / [fdo#108472] -> PASS * igt@kms_fbcon_fbt@fbc-suspend: - shard-iclb: INCOMPLETE [fdo#107713] -> PASS * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: - shard-apl: FAIL [fdo#103167] -> PASS +1 * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu: - shard-glk: FAIL [fdo#103167] -> PASS +1 * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-iclb: FAIL [fdo#105683] / [fdo#108040] -> PASS +1 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render: - shard-iclb: FAIL [fdo#103167] -> PASS +5 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: - shard-skl: INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS * igt@kms_plane@plane-position-covered-pipe-a-planes: - shard-iclb: FAIL [fdo#103166] -> PASS +2 *
Re: [Intel-gfx] [PATCH v2] drm/i915/cmdparser: whitelist needed predicate registers for Anv
On 11/01/2019 18:40, Lionel Landwerlin wrote:
There is no reason not to whitelist those registers. In particular
MI_PREDICATE_RESULT can be loaded outside of MI_PREDICATE through
other registers to predicate other commands.
v2: Define MI_PREDICATE_DATA_UDW (Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 6 +-
drivers/gpu/drm/i915/i915_reg.h| 3 +++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 95478db9998b..c5bf14c3f540 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -549,6 +549,8 @@ static const struct drm_i915_reg_descriptor
gen7_render_regs[] = {
REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
REG64(MI_PREDICATE_SRC0),
REG64(MI_PREDICATE_SRC1),
+ REG64(MI_PREDICATE_DATA),
+ REG32(MI_PREDICATE_RESULT),
As Ville mentioned on IRC, I should probably add RESULT_2 too.
REG32(GEN7_3DPRIM_END_OFFSET),
REG32(GEN7_3DPRIM_START_VERTEX),
REG32(GEN7_3DPRIM_VERTEX_COUNT),
@@ -1382,6 +1384,8 @@ int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv)
*the parser enabled.
* 9. Don't whitelist or handle oacontrol specially, as ownership
*for oacontrol state is moving to i915-perf.
+* 10. Whitelist predicate data/result registers for conditional
+* rendering in Anv.
*/
- return 9;
+ return 10;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ca8026ec0655..408dd59cdbdc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -461,6 +461,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
#define MI_PREDICATE_SRC1 _MMIO(0x2408)
#define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
+#define MI_PREDICATE_DATA _MMIO(0x2410)
+#define MI_PREDICATE_DATA_UDW _MMIO(0x2414)
+#define MI_PREDICATE_RESULT_MMIO(0x2418)
#define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
#define LOWER_SLICE_ENABLED (1 << 0)
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Prevent concurrent GGTT update and use on Braswell (again)
== Series Details == Series: drm/i915: Prevent concurrent GGTT update and use on Braswell (again) URL : https://patchwork.freedesktop.org/series/55086/ State : success == Summary == CI Bug Log - changes from CI_DRM_5404_full -> Patchwork_11283_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_11283_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_caching@read-writes: - shard-glk: PASS -> INCOMPLETE [fdo#103359] / [k.org#198133] * igt@gem_exec_schedule@pi-ringfull-vebox: - shard-skl: NOTRUN -> FAIL [fdo#103158] * igt@i915_suspend@forcewake: - shard-snb: PASS -> INCOMPLETE [fdo#105411] * igt@kms_atomic@plane_primary_legacy: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] +10 * igt@kms_available_modes_crc@available_mode_test_crc: - shard-apl: PASS -> FAIL [fdo#106641] * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c: - shard-hsw: PASS -> DMESG-WARN [fdo#107956] * igt@kms_color@pipe-a-degamma: - shard-skl: PASS -> FAIL [fdo#104782] / [fdo#108145] * igt@kms_cursor_crc@cursor-256x85-sliding: - shard-glk: PASS -> FAIL [fdo#103232] +1 * igt@kms_cursor_crc@cursor-64x64-dpms: - shard-apl: NOTRUN -> FAIL [fdo#103232] * igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled: - shard-iclb: PASS -> WARN [fdo#108336] * igt@kms_fbcon_fbt@psr: - shard-skl: NOTRUN -> FAIL [fdo#107882] * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-apl: PASS -> FAIL [fdo#102887] / [fdo#105363] - shard-glk: PASS -> FAIL [fdo#105363] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc: - shard-glk: PASS -> FAIL [fdo#103167] +3 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-apl: PASS -> FAIL [fdo#103167] +2 * igt@kms_frontbuffer_tracking@fbc-1p-rte: - shard-apl: PASS -> FAIL [fdo#103167] / [fdo#105682] * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-gtt: - shard-iclb: PASS -> DMESG-FAIL [fdo#107724] +6 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +8 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen: - shard-iclb: PASS -> FAIL [fdo#103167] +7 * igt@kms_panel_fitting@legacy: - shard-skl: NOTRUN -> FAIL [fdo#105456] * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping: - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] - shard-iclb: NOTRUN -> FAIL [fdo#108948] * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: - shard-skl: NOTRUN -> FAIL [fdo#108145] +1 * igt@kms_plane_multiple@atomic-pipe-a-tiling-x: - shard-apl: PASS -> FAIL [fdo#103166] +2 - shard-iclb: PASS -> FAIL [fdo#103166] +1 * igt@kms_plane_multiple@atomic-pipe-b-tiling-none: - shard-glk: PASS -> FAIL [fdo#103166] +1 * igt@kms_rotation_crc@multiplane-rotation-cropping-top: - shard-glk: PASS -> DMESG-WARN [fdo#105763] / [fdo#106538] * igt@perf@short-reads: - shard-glk: PASS -> FAIL [fdo#103183] * igt@pm_rpm@cursor: - shard-skl: PASS -> INCOMPLETE [fdo#107807] Possible fixes * igt@gem_ctx_isolation@vecs0-dirty-switch: - shard-apl: INCOMPLETE [fdo#103927] -> PASS * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: - shard-skl: DMESG-WARN [fdo#107956] -> PASS * igt@kms_color@pipe-b-degamma: - shard-apl: FAIL [fdo#104782] -> PASS * igt@kms_cursor_crc@cursor-256x85-random: - shard-glk: FAIL [fdo#103232] -> PASS * igt@kms_cursor_crc@cursor-64x21-random: - shard-apl: FAIL [fdo#103232] -> PASS +3 * igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled: - shard-skl: FAIL [fdo#103184] / [fdo#108472] -> PASS * igt@kms_draw_crc@draw-method-xrgb-mmap-gtt-xtiled: - shard-glk: FAIL [fdo#107791] -> PASS * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render: - shard-apl: FAIL [fdo#103167] -> PASS +3 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-iclb: FAIL [fdo#103167] -> PASS +2 * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu: - shard-glk: FAIL [fdo#103167] -> PASS +1 * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-iclb: FAIL [fdo#105683] / [fdo#108040] -> PASS +1 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: - shard-skl: INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS *
Re: [Intel-gfx] [v5 6/6] drm/i915/icl: Add degamma and gamma lut size to gen11 caps
On Tue, Jan 08, 2019 at 01:07:33PM +0530, Uma Shankar wrote:
> Add the degamma and gamma lut sizes to gen11 capability
> structure.
>
> Note: Currently this doesn't account for the extended range gamma
> entries and this will be addressed with new segmented gamma ABI
> in a future patch.
>
> v2: Reorder the patch as per Maarten's suggestion.
>
> v3: Rebase
>
> v4: Updated commit message with a note as per Matt's suggestion.
>
> v5: No Change.
>
> Signed-off-by: Uma Shankar
On one of the earlier patches, we suggested using the new degamma
loading function for glk/cnl as well. If you do that, you'll also
probably want to update the degamma_lut_size for GLK as well, although
that can be done as a separate patch if you like.
The values here look correct for ICL, so
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_pci.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index dd4aff2..14e5bb4 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -639,7 +639,8 @@
> }, \
> GEN(11), \
> .ddb_size = 2048, \
> - .has_logical_ring_elsq = 1
> + .has_logical_ring_elsq = 1, \
> + .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
>
> static const struct intel_device_info intel_icelake_11_info = {
> GEN11_FEATURES,
> --
> 1.9.1
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [v5 5/6] drm/i915/icl: Enable ICL Pipe CSC block
On Tue, Jan 08, 2019 at 01:07:32PM +0530, Uma Shankar wrote:
> Enable ICL pipe csc hardware. CSC block is enabled
> in CSC_MODE register instead of PLANE_COLOR_CTL.
>
> ToDO: Extend the ABI to accept 32 bit coefficient values
> instead of 16bit for future platforms.
>
> v2: Addressed Maarten's review comments.
>
> v3: Addressed Matt's review comments. Removed rmw patterns
> as suggested by Matt.
>
> v4: Addressed Matt's review comments.
>
> v5: Addressed Ville's review comments.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/i915_reg.h| 10 +++---
> drivers/gpu/drm/i915/intel_color.c | 12 ++--
> 2 files changed, 17 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f29eef7..5a262c0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9861,10 +9861,14 @@ enum skl_power_gate {
> #define _PIPE_A_CSC_COEFF_BU 0x4901c
> #define _PIPE_A_CSC_COEFF_RV_GV 0x49020
> #define _PIPE_A_CSC_COEFF_BV 0x49024
> +
> #define _PIPE_A_CSC_MODE 0x49028
> -#define CSC_BLACK_SCREEN_OFFSET(1 << 2)
> -#define CSC_POSITION_BEFORE_GAMMA (1 << 1)
> -#define CSC_MODE_YUV_TO_RGB(1 << 0)
> +#define ICL_CSC_ENABLE (1 << 31)
> +#define ICL_OUTPUT_CSC_ENABLE (1 << 30)
> +#define CSC_BLACK_SCREEN_OFFSET (1 << 2)
> +#define CSC_POSITION_BEFORE_GAMMA (1 << 1)
> +#define CSC_MODE_YUV_TO_RGB (1 << 0)
> +
> #define _PIPE_A_CSC_PREOFF_HI0x49030
> #define _PIPE_A_CSC_PREOFF_ME0x49034
> #define _PIPE_A_CSC_PREOFF_LO0x49038
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index 9cd4646..c3e4ff6 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -134,7 +134,11 @@ static void ilk_load_ycbcr_conversion_matrix(struct
> intel_crtc *crtc)
> I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI);
> I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), POSTOFF_RGB_TO_YUV_ME);
> I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO);
> - I915_WRITE(PIPE_CSC_MODE(pipe), 0);
> +
> + if (INTEL_GEN(dev_priv) >= 11)
> + I915_WRITE(PIPE_CSC_MODE(pipe), ICL_OUTPUT_CSC_ENABLE);
For gen11+, shouldn't we be programming OUTPUT_CSC_COEFF instead of
CSC_COEFF if we set this bit?
> + else
> + I915_WRITE(PIPE_CSC_MODE(pipe), 0);
> }
>
> static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state)
> @@ -242,7 +246,10 @@ static void ilk_load_csc_matrix(struct intel_crtc_state
> *crtc_state)
> I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
> I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
>
> - I915_WRITE(PIPE_CSC_MODE(pipe), 0);
> + if (INTEL_GEN(dev_priv) >= 11)
> + I915_WRITE(PIPE_CSC_MODE(pipe), ICL_CSC_ENABLE);
> + else
> + I915_WRITE(PIPE_CSC_MODE(pipe), 0);
I might be misinterpreting how the hardware works, but my impression was
that we had two distinct CSC units now on gen11+. So we could use the
traditional CSC registers to hold the userspace-provided CTM and the new
output CSC registers to hold the fixed RGB->YUV matrix, and they could
both be used at the same time if necessary. It looks like this function
is still assuming that the two are mutually exclusive and that if we
need RGB->YUV we never bother programming the userspace matrix. Is that
intentional or an oversight? Aside from the register definitions
themselves, the bspec seems to be pretty sparse on how the whole
pipeline goes together...
Matt
> } else {
> uint32_t mode = CSC_MODE_YUV_TO_RGB;
>
> @@ -700,6 +707,7 @@ void intel_color_init(struct intel_crtc *crtc)
> dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
> dev_priv->display.load_luts = glk_load_luts;
> } else if (IS_ICELAKE(dev_priv)) {
> + dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
> dev_priv->display.load_luts = icl_load_luts;
> } else {
> dev_priv->display.load_luts = i9xx_load_luts;
> --
> 1.9.1
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Try to sanitize bogus DPLL state left over by broken SNB BIOSen (rev2)
== Series Details == Series: drm/i915: Try to sanitize bogus DPLL state left over by broken SNB BIOSen (rev2) URL : https://patchwork.freedesktop.org/series/54942/ State : success == Summary == CI Bug Log - changes from CI_DRM_5404_full -> Patchwork_11281_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_11281_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@pi-ringfull-render: - shard-skl: NOTRUN -> FAIL [fdo#103158] +1 * igt@kms_available_modes_crc@available_mode_test_crc: - shard-apl: PASS -> FAIL [fdo#106641] * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] - shard-hsw: PASS -> DMESG-WARN [fdo#107956] * igt@kms_ccs@pipe-c-bad-pixel-format: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] +15 * igt@kms_chv_cursor_fail@pipe-a-64x64-left-edge: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +13 * igt@kms_cursor_crc@cursor-128x42-offscreen: - shard-skl: NOTRUN -> FAIL [fdo#103232] * igt@kms_cursor_crc@cursor-128x42-onscreen: - shard-apl: PASS -> FAIL [fdo#103232] +1 * igt@kms_cursor_crc@cursor-256x256-suspend: - shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232] * igt@kms_cursor_crc@cursor-256x85-sliding: - shard-glk: PASS -> FAIL [fdo#103232] +1 * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-untiled: - shard-iclb: PASS -> WARN [fdo#108336] +1 * igt@kms_fbcon_fbt@psr: - shard-skl: NOTRUN -> FAIL [fdo#107882] * igt@kms_flip@2x-flip-vs-panning-vs-hang-interruptible: - shard-hsw: PASS -> INCOMPLETE [fdo#103540] * igt@kms_flip@flip-vs-expired-vblank: - shard-glk: PASS -> FAIL [fdo#102887] / [fdo#105363] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc: - shard-glk: PASS -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-apl: PASS -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary: - shard-iclb: PASS -> DMESG-FAIL [fdo#107724] +7 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite: - shard-iclb: PASS -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move: - shard-iclb: NOTRUN -> FAIL [fdo#103167] * igt@kms_panel_fitting@legacy: - shard-skl: NOTRUN -> FAIL [fdo#105456] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-skl: NOTRUN -> INCOMPLETE [fdo#104108] / [fdo#107773] * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping: - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] - shard-iclb: NOTRUN -> FAIL [fdo#108948] * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: NOTRUN -> FAIL [fdo#103166] * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: - shard-skl: NOTRUN -> FAIL [fdo#108145] +1 * igt@kms_plane_multiple@atomic-pipe-a-tiling-x: - shard-apl: PASS -> FAIL [fdo#103166] +3 * igt@kms_plane_multiple@atomic-pipe-b-tiling-none: - shard-glk: PASS -> FAIL [fdo#103166] +2 * igt@kms_plane_multiple@atomic-pipe-c-tiling-none: - shard-iclb: PASS -> FAIL [fdo#103166] +1 * igt@kms_psr@no_drrs: - shard-iclb: PASS -> FAIL [fdo#108341] * igt@kms_rotation_crc@multiplane-rotation-cropping-top: - shard-glk: PASS -> DMESG-FAIL [fdo#105763] / [fdo#106538] Possible fixes * igt@gem_ctx_isolation@vecs0-dirty-switch: - shard-apl: INCOMPLETE [fdo#103927] -> PASS * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-skl: INCOMPLETE [fdo#104108] -> PASS * igt@kms_cursor_crc@cursor-256x85-random: - shard-apl: FAIL [fdo#103232] -> PASS +3 - shard-glk: FAIL [fdo#103232] -> PASS * igt@kms_draw_crc@draw-method-xrgb-mmap-gtt-xtiled: - shard-glk: FAIL [fdo#107791] -> PASS * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: - shard-apl: FAIL [fdo#103167] -> PASS +2 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-iclb: FAIL [fdo#103167] -> PASS +9 * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu: - shard-glk: FAIL [fdo#103167] -> PASS * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-iclb: FAIL [fdo#105683] / [fdo#108040] -> PASS +1 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: - shard-skl: INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS *
Re: [Intel-gfx] [PATCH v4 1/2] drm: Add color management LUT validation helper (v4)
Dave, Daniel - any concerns if we merge this drm core patch through the
Intel tree? The second patch in the series doesn't apply cleanly in
drm-misc-next.
Matt
On Mon, Dec 17, 2018 at 02:44:14PM -0800, Matt Roper wrote:
> Some hardware may place additional restrictions on the gamma/degamma
> curves described by our LUT properties. E.g., that a gamma curve never
> decreases or that the red/green/blue channels of a LUT's entries must be
> equal. Let's add a helper function that drivers can use to test that a
> userspace-provided LUT is valid and doesn't violate hardware
> requirements.
>
> v2:
> - Combine into a single helper that just takes a bitmask of the tests
>to apply. (Brian Starkey)
> - Add additional check (always performed) that LUT property blob size
>is always a multiple of the LUT entry size. (stolen from ARM driver)
>
> v3:
> - Drop the LUT size check again since
>drm_atomic_replace_property_blob_from_id() already covers this for
>us. (Alexandru Gheorghe)
>
> v4:
> - Use an enum to describe possible test values rather than #define's;
>this is cleaner to provide kerneldoc for. (Daniel Vetter)
> - s/DRM_COLOR_LUT_INCREASING/DRM_COLOR_LUT_NON_DECREASING/. (Ville)
>
> Cc: Uma Shankar
> Cc: Swati Sharma
> Cc: Brian Starkey
> Cc: Daniel Vetter
> Cc: Ville Syrjälä
> Signed-off-by: Matt Roper
> Reviewed-by(v1): Brian Starkey
> Reviewed-by: Alexandru Gheorghe
> Reviewed-by: Uma Shankar
> ---
> drivers/gpu/drm/drm_color_mgmt.c | 44
>
> include/drm/drm_color_mgmt.h | 29 ++
> 2 files changed, 73 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_color_mgmt.c
> b/drivers/gpu/drm/drm_color_mgmt.c
> index 07dcf47daafe..968ca7c91ad8 100644
> --- a/drivers/gpu/drm/drm_color_mgmt.c
> +++ b/drivers/gpu/drm/drm_color_mgmt.c
> @@ -462,3 +462,47 @@ int drm_plane_create_color_properties(struct drm_plane
> *plane,
> return 0;
> }
> EXPORT_SYMBOL(drm_plane_create_color_properties);
> +
> +/**
> + * drm_color_lut_check - check validity of lookup table
> + * @lut: property blob containing LUT to check
> + * @tests: bitmask of tests to run
> + *
> + * Helper to check whether a userspace-provided lookup table is valid and
> + * satisfies hardware requirements. Drivers pass a bitmask indicating which
> of
> + * the tests in _color_lut_tests should be performed.
> + *
> + * Returns 0 on success, -EINVAL on failure.
> + */
> +int drm_color_lut_check(struct drm_property_blob *lut,
> + uint32_t tests)
> +{
> + struct drm_color_lut *entry;
> + int i;
> +
> + if (!lut || !tests)
> + return 0;
> +
> + entry = lut->data;
> + for (i = 0; i < drm_color_lut_size(lut); i++) {
> + if (tests & DRM_COLOR_LUT_EQUAL_CHANNELS) {
> + if (entry[i].red != entry[i].blue ||
> + entry[i].red != entry[i].green) {
> + DRM_DEBUG_KMS("All LUT entries must have equal
> r/g/b\n");
> + return -EINVAL;
> + }
> + }
> +
> + if (i > 0 && tests & DRM_COLOR_LUT_NON_DECREASING) {
> + if (entry[i].red < entry[i - 1].red ||
> + entry[i].green < entry[i - 1].green ||
> + entry[i].blue < entry[i - 1].blue) {
> + DRM_DEBUG_KMS("LUT entries must never
> decrease.\n");
> + return -EINVAL;
> + }
> + }
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_color_lut_check);
> diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
> index 90ef9996d9a4..6affbda6d9cb 100644
> --- a/include/drm/drm_color_mgmt.h
> +++ b/include/drm/drm_color_mgmt.h
> @@ -69,4 +69,33 @@ int drm_plane_create_color_properties(struct drm_plane
> *plane,
> u32 supported_ranges,
> enum drm_color_encoding default_encoding,
> enum drm_color_range default_range);
> +
> +/**
> + * enum drm_color_lut_tests - hw-specific LUT tests to perform
> + *
> + * The drm_color_lut_check() function takes a bitmask of the values here to
> + * determine which tests to apply to a userspace-provided LUT.
> + */
> +enum drm_color_lut_tests {
> + /**
> + * @DRM_COLOR_LUT_EQUAL_CHANNELS:
> + *
> + * Checks whether the entries of a LUT all have equal values for the
> + * red, green, and blue channels. Intended for hardware that only
> + * accepts a single value per LUT entry and assumes that value applies
> + * to all three color components.
> + */
> + DRM_COLOR_LUT_EQUAL_CHANNELS = BIT(0),
> +
> + /**
> + * @DRM_COLOR_LUT_NON_DECREASING:
> + *
> + * Checks whether the entries of a LUT are always flat or increasing
> + * (never
Re: [Intel-gfx] [v5 4/6] drm/i915/icl: Add icl pipe degamma and gamma support
On Tue, Jan 08, 2019 at 01:07:31PM +0530, Uma Shankar wrote:
> Add support for icl pipe degamma and gamma.
>
> v2: Removed a POSTING_READ and corrected the Bit
> Definition as per Maarten's comments.
>
> v3: Addressed Matt's review comments. Removed rmw patterns
> as suggested by Matt.
>
> v4: Fixed Matt's review comments.
>
> v5: Corrected macro alignment as per Jani Nikula's comments.
> Addressed Ville and Matt's review comments.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/i915_reg.h| 12 ---
> drivers/gpu/drm/i915/intel_color.c | 65
> ++
> 2 files changed, 72 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 44958d9..f29eef7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7088,11 +7088,13 @@ enum {
> #define _GAMMA_MODE_A0x4a480
> #define _GAMMA_MODE_B0x4ac80
> #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
> -#define GAMMA_MODE_MODE_MASK (3 << 0)
> -#define GAMMA_MODE_MODE_8BIT (0 << 0)
> -#define GAMMA_MODE_MODE_10BIT(1 << 0)
> -#define GAMMA_MODE_MODE_12BIT(2 << 0)
> -#define GAMMA_MODE_MODE_SPLIT(3 << 0)
> +#define PRE_CSC_GAMMA_ENABLE(1 << 31)
> +#define POST_CSC_GAMMA_ENABLE (1 << 30)
> +#define GAMMA_MODE_MODE_MASK(3 << 0)
> +#define GAMMA_MODE_MODE_8BIT(0 << 0)
> +#define GAMMA_MODE_MODE_10BIT (1 << 0)
> +#define GAMMA_MODE_MODE_12BIT (2 << 0)
> +#define GAMMA_MODE_MODE_SPLIT (3 << 0)
>
> /* DMC/CSR */
> #define CSR_PROGRAM(i) _MMIO(0x8 + (i) * 4)
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index 9a72e64..9cd4646 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -520,6 +520,69 @@ static void glk_load_luts(struct intel_crtc_state
> *crtc_state)
> POSTING_READ(GAMMA_MODE(pipe));
> }
>
> +static void icl_load_degamma_lut(struct intel_crtc_state *crtc_state)
As Ville noted, I think the degamma LUT works the same way on GLK-ICL;
the gamma part may be different (and there's extra stuff like the extra
output CSC on ICL), but for degamma specifically I think the code you
wrote below could just be used to replace the current body of
glk_load_degamma_lut rather than adding it as a separate function.
Since GLK-ICL only support equal r/g/b values, we also need to land the
LUT validation patches I wrote in December. Those are fully reviewed so
I'll do that as soon as I get an ack from Dave/Daniel to merge the drm
core patch through the Intel tree.
Matt
> +{
> + struct drm_device *dev = crtc_state->base.crtc->dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> + const uint32_t lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> + uint32_t i;
> +
> + /*
> + * When setting the auto-increment bit, the hardware seems to
> + * ignore the index bits, so we need to reset it to index 0
> + * separately.
> + */
> + I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);
> + I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT);
> +
> + if (crtc_state->base.degamma_lut) {
> + struct drm_color_lut *lut = crtc_state->base.degamma_lut->data;
> +
> + for (i = 0; i < lut_size; i++) {
> + /*
> + * First 33 entries represent range from 0 to 1.0
> + * 34th and 35th entry will represent extended range
> + * inputs 3.0 and 7.0 respectively, currently clamped
> + * at 1.0. Since the precision is 16bit, the user value
> + * can be directly filled to register.
> + * ToDo: Extend to max 7.0.
> + */
> + I915_WRITE(PRE_CSC_GAMC_DATA(pipe), lut[i].green);
> + }
> + } else {
> + /* load a linear table. */
> + for (i = 0; i < lut_size; i++) {
> + uint32_t v = (i * (1 << 16)) / (lut_size - 1);
> +
> + I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
> + }
> + }
> +
> + /* Clamp values > 1.0. */
> + while (i++ < 35)
> + I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16));
> +}
> +
> +static void icl_load_luts(struct intel_crtc_state *crtc_state)
> +{
> + struct drm_crtc *crtc = crtc_state->base.crtc;
> + struct drm_device *dev = crtc_state->base.crtc->dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + enum pipe pipe = to_intel_crtc(crtc)->pipe;
> +
> + if (crtc_state_is_legacy_gamma(crtc_state)) {
> + haswell_load_luts(crtc_state);
> + return;
> + }
> +
> +
[Intel-gfx] ✓ Fi.CI.IGT: success for Enable/disable gamma/csc dynamically and fix C8
== Series Details == Series: Enable/disable gamma/csc dynamically and fix C8 URL : https://patchwork.freedesktop.org/series/55081/ State : success == Summary == CI Bug Log - changes from CI_DRM_5404_full -> Patchwork_11280_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_11280_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@pi-ringfull-render: - shard-skl: NOTRUN -> FAIL [fdo#103158] * igt@kms_atomic_transition@plane-all-transition-nonblocking-fencing: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#109225] +1 * igt@kms_available_modes_crc@available_mode_test_crc: - shard-apl: PASS -> FAIL [fdo#106641] - shard-skl: NOTRUN -> FAIL [fdo#106641] * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] - shard-hsw: PASS -> DMESG-WARN [fdo#107956] * igt@kms_cursor_crc@cursor-256x256-random: - shard-glk: PASS -> FAIL [fdo#103232] +20 * igt@kms_cursor_crc@cursor-64x64-random: - shard-iclb: NOTRUN -> FAIL [fdo#103232] * igt@kms_fbcon_fbt@psr: - shard-skl: NOTRUN -> FAIL [fdo#107882] * igt@kms_flip@modeset-vs-vblank-race-interruptible: - shard-glk: PASS -> FAIL [fdo#103060] +1 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render: - shard-apl: PASS -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc: - shard-glk: PASS -> FAIL [fdo#103167] +2 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render: - shard-iclb: PASS -> DMESG-FAIL [fdo#107724] * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +6 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen: - shard-iclb: PASS -> FAIL [fdo#103167] +4 * igt@kms_panel_fitting@legacy: - shard-skl: NOTRUN -> FAIL [fdo#105456] * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping: - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] - shard-iclb: NOTRUN -> FAIL [fdo#108948] * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: - shard-skl: NOTRUN -> FAIL [fdo#108145] +2 * igt@kms_plane_multiple@atomic-pipe-b-tiling-y: - shard-glk: PASS -> FAIL [fdo#103166] +3 - shard-iclb: PASS -> FAIL [fdo#103166] +3 * igt@kms_plane_multiple@atomic-pipe-c-tiling-none: - shard-apl: PASS -> FAIL [fdo#103166] * igt@kms_plane_multiple@atomic-pipe-c-tiling-y: - shard-iclb: NOTRUN -> FAIL [fdo#103166] * igt@kms_rmfb@rmfb-ioctl: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] +15 * igt@kms_rotation_crc@multiplane-rotation-cropping-top: - shard-glk: PASS -> DMESG-FAIL [fdo#105763] / [fdo#106538] * igt@kms_sysfs_edid_timing: - shard-iclb: PASS -> FAIL [fdo#100047] * igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend: - shard-iclb: PASS -> INCOMPLETE [fdo#107713] +1 * igt@pm_rpm@gem-pread: - shard-skl: NOTRUN -> INCOMPLETE [fdo#107807] +1 * igt@pm_rpm@system-suspend: - shard-iclb: PASS -> INCOMPLETE [fdo#107713] / [fdo#108840] Possible fixes * igt@gem_ctx_isolation@vecs0-dirty-switch: - shard-apl: INCOMPLETE [fdo#103927] -> PASS * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b: - shard-skl: DMESG-WARN [fdo#107956] -> PASS * igt@kms_color@pipe-b-degamma: - shard-apl: FAIL [fdo#104782] -> PASS * igt@kms_cursor_crc@cursor-128x128-random: - shard-skl: FAIL [fdo#103232] -> PASS * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-skl: INCOMPLETE [fdo#104108] -> PASS * igt@kms_cursor_crc@cursor-64x21-random: - shard-apl: FAIL [fdo#103232] -> PASS +2 * igt@kms_fbcon_fbt@fbc-suspend: - shard-iclb: INCOMPLETE [fdo#107713] -> PASS * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: - shard-apl: FAIL [fdo#103167] -> PASS +4 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-iclb: FAIL [fdo#103167] -> PASS +6 * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu: - shard-glk: FAIL [fdo#103167] -> PASS * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-iclb: FAIL [fdo#105683] / [fdo#108040] -> PASS +1 * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-render: - shard-skl: FAIL [fdo#103167] -> PASS +4 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: - shard-skl:
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/4] drm/i915/psr: Allow PSR2 to be enabled when debugfs asks
== Series Details ==
Series: series starting with [v3,1/4] drm/i915/psr: Allow PSR2 to be enabled
when debugfs asks
URL : https://patchwork.freedesktop.org/series/55097/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5405 -> Patchwork_11286
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/55097/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_11286:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_psr@cursor_plane_move:
- fi-icl-u2: PASS -> {SKIP} +3
- fi-icl-u3: PASS -> {SKIP} +3
Known issues
Here are the changes found in Patchwork_11286 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload-no-display:
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602]
* igt@i915_module_load@reload-with-fault-injection:
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#105602]
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: PASS -> FAIL [fdo#103167]
Possible fixes
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#109241]: https://bugs.freedesktop.org/show_bug.cgi?id=109241
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
Participating hosts (48 -> 42)
--
Missing(6): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5405 -> Patchwork_11286
CI_DRM_5405: 92073deda0323ec6b2dd4066dd253235a54afa74 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4763: 805a99409542d7d72dda3b6dcd284a8869a3de16 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11286: d846a8d030ccbf675c6b2c72f6808df25c6fac28 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d846a8d030cc drm/i915/debugfs: Print PSR selective update status register values
109b612e485c drm/i915: Add PSR2 selective update status registers and bits
definitions
c20be7cef94a drm/i915: Refactor PSR status debugfs
7523c994baac drm/i915/psr: Allow PSR2 to be enabled when debugfs asks
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11286/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] drm/i915: Watchdog timeout: IRQ handler for gen8+
On 1/11/2019 09:31, Antonio Argenziano wrote: On 11/01/19 00:22, Tvrtko Ursulin wrote: On 11/01/2019 00:47, Antonio Argenziano wrote: On 07/01/19 08:58, Tvrtko Ursulin wrote: On 07/01/2019 13:57, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-01-07 13:43:29) On 07/01/2019 11:58, Tvrtko Ursulin wrote: [snip] Note about future interaction with preemption: Preemption could happen in a command sequence prior to watchdog counter getting disabled, resulting in watchdog being triggered following preemption (e.g. when watchdog had been enabled in the low priority batch). The driver will need to explicitly disable the watchdog counter as part of the preemption sequence. Does the series take care of preemption? I did not find that it does. Oh. I hoped that the watchdog was saved as part of the context... Then despite preemption, the timeout would resume from where we left off as soon as it was back on the gpu. If the timeout remaining was context saved it would be much simpler (at least on first glance), please say it is. I made my comments going only by the text from the commit message and the absence of any preemption special handling. Having read the spec, the situation seems like this: * Watchdog control and threshold register are context saved and restored. * On a context switch watchdog counter is reset to zero and automatically disabled until enabled by a context restore or explicitly. So it sounds the commit message could be wrong that special handling is needed from this direction. But read till the end on the restriction listed. * Watchdog counter is reset to zero and is not accumulated across multiple submission of the same context (due preemption). I read this as - after preemption contexts gets a new full timeout allocation. Or in other words, if a context is preempted N times, it's cumulative watchdog timeout will be N * set value. This could be theoretically exploitable to bypass the timeout. If a client sets up two contexts with prio -1 and -2, and keeps submitting periodical no-op batches against prio -1 context, while prio -2 is it's own hog, then prio -2 context defeats the watchdog timer. I think.. would appreciate is someone challenged this conclusion. I think you are right that is a possibility but, is that a problem? The client can just not set the threshold to bypass the timeout. Also because you need the hanging batch to be simply preemptible, you cannot disrupt any work from another client that is higher priority. This is But I think higher priority client can have the same effect on the lower priority purely by accident, no? As a real world example, user kicks off an background transcoding job, which happens to use prio -2, and uses the watchdog timer. At the same time user watches a video from a player of normal priority. This causes periodic, say 24Hz, preemption events, due frame decoding activity on the same engine as the transcoding client. Does this defeat the watchdog timer for the former is the question? Then the questions of can we do something about it and whether it really isn't a problem? I guess it depends if you consider that timeout as the maximum lifespan a workload can have or max contiguous active time. I believe the intended purpose of the watchdog is to prevent broken bitstreams hanging the transcoder/player. That is, it is a form of error detection used by the media driver to handle bad user input. So if there is a way for the watchdog to be extended indefinitely under normal situations, that would be a problem. It means the transcoder will not detect the broken input data in a timely manner and effectively hang rather than skip over to the next packet. And note that broken input data can be caused by something as innocent as a dropped packet due to high network contention. No need for any malicious activity at all. John. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 21/21] drm/i915: Mark up Ironlake ips with rpm wakerefs
On 1/10/2019 02:11, Chris Wilson wrote:
Currently Ironlake operates under the assumption that rpm awake (and its
error checking is disabled). As such, we have missed a few places where we
access registers without taking the rpm wakeref and thus trigger
warnings. intel_ips being one culprit.
As this involved adding a potentially sleeping rpm_get, we have to
rearrange the spinlocks slightly and so switch to acquiring a device-ref
under the spinlock rather than hold the spinlock for the whole
operation. To be consistent, we make the change in pattern common to the
intel_ips interface even though this adds a few more atomic operations
than necessary in a few cases.
v2: Sagar noted the mb around setting mch_dev were overkill as we only
need ordering there, and that i915_emon_status was still using
struct_mutex for no reason, but lacked rpm.
Signed-off-by: Chris Wilson
Cc: Jani Nikula
---
drivers/gpu/drm/i915/i915_debugfs.c | 32 ++
drivers/gpu/drm/i915/i915_drv.c | 3 +
drivers/gpu/drm/i915/intel_pm.c | 172 ++--
3 files changed, 102 insertions(+), 105 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 96717a23b32f..c0263c233faa 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1741,32 +1741,24 @@ static int i915_sr_status(struct seq_file *m, void
*unused)
static int i915_emon_status(struct seq_file *m, void *unused)
{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct drm_device *dev = _priv->drm;
- unsigned long temp, chipset, gfx;
+ struct drm_i915_private *i915 = node_to_i915(m->private);
intel_wakeref_t wakeref;
- int ret;
- if (!IS_GEN(dev_priv, 5))
+ if (!IS_GEN(i915, 5))
return -ENODEV;
- ret = mutex_lock_interruptible(>struct_mutex);
- if (ret)
- return ret;
+ with_intel_runtime_pm(i915, wakeref) {
+ unsigned long temp, chipset, gfx;
- wakeref = intel_runtime_pm_get(dev_priv);
-
- temp = i915_mch_val(dev_priv);
- chipset = i915_chipset_val(dev_priv);
- gfx = i915_gfx_val(dev_priv);
- mutex_unlock(>struct_mutex);
+ temp = i915_mch_val(i915);
+ chipset = i915_chipset_val(i915);
+ gfx = i915_gfx_val(i915);
- intel_runtime_pm_put(dev_priv, wakeref);
-
- seq_printf(m, "GMCH temp: %ld\n", temp);
- seq_printf(m, "Chipset power: %ld\n", chipset);
- seq_printf(m, "GFX power: %ld\n", gfx);
- seq_printf(m, "Total power: %ld\n", chipset + gfx);
+ seq_printf(m, "GMCH temp: %ld\n", temp);
+ seq_printf(m, "Chipset power: %ld\n", chipset);
+ seq_printf(m, "GFX power: %ld\n", gfx);
+ seq_printf(m, "Total power: %ld\n", chipset + gfx);
+ }
I would have left the variable declarations and printfs outside of the
pm hold. No need to keep the power on while doing a bunch of string
manipulations.
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5731f992cf44..dafbbfadd1ad 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1780,6 +1780,9 @@ void i915_driver_unload(struct drm_device *dev)
i915_driver_unregister(dev_priv);
+ /* Flush any external code that still may be under the RCU lock */
+ synchronize_rcu();
+
if (i915_gem_suspend(dev_priv))
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ab7257720c7e..7613ae72df3d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6203,10 +6203,6 @@ void intel_init_ipc(struct drm_i915_private *dev_priv)
*/
DEFINE_SPINLOCK(mchdev_lock);
-/* Global for IPS driver to get at the current i915 device. Protected by
- * mchdev_lock. */
-static struct drm_i915_private *i915_mch_dev;
-
bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
{
u16 rgvswctl;
@@ -7849,16 +7845,17 @@ static unsigned long __i915_chipset_val(struct
drm_i915_private *dev_priv)
unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
{
- unsigned long val;
+ intel_wakeref_t wakeref;
+ unsigned long val = 0;
if (!IS_GEN(dev_priv, 5))
return 0;
- spin_lock_irq(_lock);
-
- val = __i915_chipset_val(dev_priv);
-
- spin_unlock_irq(_lock);
+ with_intel_runtime_pm(dev_priv, wakeref) {
+ spin_lock_irq(_lock);
+ val = __i915_chipset_val(dev_priv);
+ spin_unlock_irq(_lock);
+ }
return val;
}
@@ -7935,14 +7932,16 @@ static void __i915_update_gfx_val(struct
drm_i915_private *dev_priv)
void i915_update_gfx_val(struct drm_i915_private *dev_priv)
{
+
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/4] drm/i915/psr: Allow PSR2 to be enabled when debugfs asks
== Series Details == Series: series starting with [v3,1/4] drm/i915/psr: Allow PSR2 to be enabled when debugfs asks URL : https://patchwork.freedesktop.org/series/55097/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7523c994baac drm/i915/psr: Allow PSR2 to be enabled when debugfs asks -:48: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'José Roberto de Souza ' total: 0 errors, 1 warnings, 0 checks, 21 lines checked c20be7cef94a drm/i915: Refactor PSR status debugfs -:22: WARNING:BAD_SIGN_OFF: Use a single space after To: #22: To: -:22: ERROR:BAD_SIGN_OFF: Unrecognized email address: '' #22: To: -:197: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'José Roberto de Souza ' total: 1 errors, 2 warnings, 0 checks, 145 lines checked 109b612e485c drm/i915: Add PSR2 selective update status registers and bits definitions -:33: WARNING:LONG_LINE: line over 100 characters #33: FILE: drivers/gpu/drm/i915/i915_reg.h:4278: +#define _PSR2_SU_STATUS(index) _MMIO(_PICK_EVEN((index), _PSR2_SU_STATUS_0, _PSR2_SU_STATUS_1)) -:41: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'José Roberto de Souza ' total: 0 errors, 2 warnings, 0 checks, 15 lines checked d846a8d030cc drm/i915/debugfs: Print PSR selective update status register values -:58: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'José Roberto de Souza ' total: 0 errors, 1 warnings, 0 checks, 29 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 3/4] drm/i915: Add PSR2 selective update status registers and bits definitions
This register contains how many blocks was sent in the past selective
updates.
Those registers are not kept set all the times but polling it after flip
can show the values corresponding to the last 8 frames.
v2: Improved macros(Dhinakaran)
Cc: Rodrigo Vivi
Cc: Dhinakaran Pandiyan
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 44958d994bfa..f9712d05314b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4272,6 +4272,15 @@ enum {
#define EDP_PSR2_STATUS_STATE_MASK (0xf << 28)
#define EDP_PSR2_STATUS_STATE_SHIFT28
+#define _PSR2_SU_STATUS_0 0x6F914
+#define _PSR2_SU_STATUS_1 0x6F918
+#define _PSR2_SU_STATUS_2 0x6F91C
+#define _PSR2_SU_STATUS(index) _MMIO(_PICK_EVEN((index),
_PSR2_SU_STATUS_0, _PSR2_SU_STATUS_1))
+#define PSR2_SU_STATUS(frame) (_PSR2_SU_STATUS((frame) / 3))
+#define PSR2_SU_STATUS_SHIFT(frame)(((frame) % 3) * 10)
+#define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
+#define PSR2_SU_STATUS_FRAMES 8
+
/* VGA port control */
#define ADPA _MMIO(0x61100)
#define PCH_ADPA_MMIO(0xe1100)
--
2.20.1
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[Intel-gfx] [PATCH v3 2/4] drm/i915: Refactor PSR status debugfs
The old debugfs fields was not following a naming partern and it was
a bit confusing.
So it went from:
~$ sudo more /sys/kernel/debug/dri/0/i915_edp_psr_status
Sink_Support: yes
PSR mode: PSR1
Enabled: yes
Busy frontbuffer bits: 0x000
Main link in standby mode: no
HW Enabled & Active bit: yes
Source PSR status: 0x24050006 [SRDONACK]
To:
~$ sudo more /sys/kernel/debug/dri/0/i915_edp_psr_status
Sink support: yes [0x03]
PSR mode: PSR1 enabled
Source PSR ctl: enabled [0x81f00e26]
Source PSR status: IDLE [0x04010006]
Busy frontbuffer bits: 0x
The 'Main link in standby mode' was removed as it is not useful but
if needed by someone the information is still in the register value
of 'Source PSR ctl' inside of the brackets, PSR mode and Enabled was
squashed into PSR mode, some renames and reorders and we have this
cleaner version. This will also make easy to parse debugfs for IGT
tests.
v2: Printing sink PSR version with only 2 hex digits as it is a byte
Cc: Rodrigo Vivi
Cc: Dhinakaran Pandiyan
Suggested-by: Dhinakaran Pandiyan
Reviewed-by: Dhinakaran Pandiyan
Acked-by: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_debugfs.c | 98 +++--
1 file changed, 50 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index d460ef522d9c..f8668cb05d64 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2499,7 +2499,8 @@ DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
static void
psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
{
- u32 val, psr_status;
+ u32 val, status_val;
+ const char *status = "unknown";
if (dev_priv->psr.psr2_enabled) {
static const char * const live_status[] = {
@@ -2515,14 +2516,11 @@ psr_source_status(struct drm_i915_private *dev_priv,
struct seq_file *m)
"BUF_ON",
"TG_ON"
};
- psr_status = I915_READ(EDP_PSR2_STATUS);
- val = (psr_status & EDP_PSR2_STATUS_STATE_MASK) >>
- EDP_PSR2_STATUS_STATE_SHIFT;
- if (val < ARRAY_SIZE(live_status)) {
- seq_printf(m, "Source PSR status: 0x%x [%s]\n",
- psr_status, live_status[val]);
- return;
- }
+ val = I915_READ(EDP_PSR2_STATUS);
+ status_val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
+ EDP_PSR2_STATUS_STATE_SHIFT;
+ if (status_val < ARRAY_SIZE(live_status))
+ status = live_status[status_val];
} else {
static const char * const live_status[] = {
"IDLE",
@@ -2534,74 +2532,78 @@ psr_source_status(struct drm_i915_private *dev_priv,
struct seq_file *m)
"SRDOFFACK",
"SRDENT_ON",
};
- psr_status = I915_READ(EDP_PSR_STATUS);
- val = (psr_status & EDP_PSR_STATUS_STATE_MASK) >>
- EDP_PSR_STATUS_STATE_SHIFT;
- if (val < ARRAY_SIZE(live_status)) {
- seq_printf(m, "Source PSR status: 0x%x [%s]\n",
- psr_status, live_status[val]);
- return;
- }
+ val = I915_READ(EDP_PSR_STATUS);
+ status_val = (val & EDP_PSR_STATUS_STATE_MASK) >>
+ EDP_PSR_STATUS_STATE_SHIFT;
+ if (status_val < ARRAY_SIZE(live_status))
+ status = live_status[status_val];
}
- seq_printf(m, "Source PSR status: 0x%x [%s]\n", psr_status, "unknown");
+ seq_printf(m, "Source PSR status: %s [0x%08x]\n", status, val);
}
static int i915_edp_psr_status(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
- u32 psrperf = 0;
- bool enabled = false;
- bool sink_support;
+ struct i915_psr *psr = _priv->psr;
+ const char *status;
+ bool enabled;
+ u32 val;
if (!HAS_PSR(dev_priv))
return -ENODEV;
- sink_support = dev_priv->psr.sink_support;
- seq_printf(m, "Sink_Support: %s\n", yesno(sink_support));
- if (!sink_support)
+ seq_printf(m, "Sink support: %s", yesno(psr->sink_support));
+ if (psr->dp)
+ seq_printf(m, " [0x%02x]", psr->dp->psr_dpcd[0]);
+ seq_puts(m, "\n");
+
+ if (!psr->sink_support)
return 0;
intel_runtime_pm_get(dev_priv);
+ mutex_lock(>lock);
- mutex_lock(_priv->psr.lock);
- seq_printf(m, "PSR mode: %s\n",
- dev_priv->psr.psr2_enabled ? "PSR2" : "PSR1");
- seq_printf(m, "Enabled: %s\n", yesno(dev_priv->psr.enabled));
-
[Intel-gfx] [PATCH v3 4/4] drm/i915/debugfs: Print PSR selective update status register values
The value of this registers will be used to test if PSR2 is doing
selective update and if the number of blocks match with the expected.
v2:
- Using new macros
- Changed the string output
v3:
- reading PSR2_SU_STATUS registers together(Dhinakaran)
- printing SU blocks of frames with 0 updates(Dhinakaran)
Cc: Rodrigo Vivi
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_debugfs.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index f8668cb05d64..5817ae0fb5f8 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2600,6 +2600,29 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
seq_printf(m, "Last exit at: %lld\n", psr->last_exit);
}
+ if (psr->psr2_enabled) {
+ u32 su_frames_val[3];
+ u8 frame;
+
+ /*
+* Reading all 3 registers before hand to minimize crossing a
+* frame boundary between register reads
+*/
+ for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3)
+ su_frames_val[frame / 3] =
I915_READ(PSR2_SU_STATUS(frame));
+
+ seq_puts(m, "Frame:\tPSR2 SU blocks:\n");
+
+ for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++) {
+ u32 su_blocks;
+
+ su_blocks = su_frames_val[frame / 3] &
+ PSR2_SU_STATUS_MASK(frame);
+ su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame);
+ seq_printf(m, "%d\t%d\n", frame, su_blocks);
+ }
+ }
+
unlock:
mutex_unlock(>lock);
intel_runtime_pm_put(dev_priv);
--
2.20.1
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[Intel-gfx] [PATCH v3 1/4] drm/i915/psr: Allow PSR2 to be enabled when debugfs asks
For now PSR2 is still disabled by default for all platforms but is
our intention to let debugfs to enable it for debug and tests
proporses, so intel_psr2_enabled() that is also used by debugfs to
decide if PSR2 is going to be enabled needs to take in consideration
the debug field.
v2: Using the switch/case that intel_psr2_enabled() already had to
handle this(DK)
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 0f6b2b4702e3..d28b9106fb96 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -70,17 +70,17 @@ static bool psr_global_enabled(u32 debug)
static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state)
{
- /* Disable PSR2 by default for all platforms */
- if (i915_modparams.enable_psr == -1)
- return false;
-
/* Cannot enable DSC and PSR2 simultaneously */
WARN_ON(crtc_state->dsc_params.compression_enable &&
crtc_state->has_psr2);
switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
+ case I915_PSR_DEBUG_DISABLE:
case I915_PSR_DEBUG_FORCE_PSR1:
return false;
+ case I915_PSR_DEBUG_DEFAULT:
+ if (i915_modparams.enable_psr <= 0)
+ return false;
default:
return crtc_state->has_psr2;
}
--
2.20.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: GTT remapping for display
== Series Details ==
Series: drm/i915: GTT remapping for display
URL : https://patchwork.freedesktop.org/series/55095/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5405 -> Patchwork_11285
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/55095/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_11285 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_selftest@live_hangcheck:
- fi-skl-iommu: PASS -> INCOMPLETE [fdo#108602] / [fdo#108744]
Possible fixes
* igt@i915_selftest@live_hangcheck:
- fi-bwr-2160:DMESG-FAIL [fdo#108735] -> PASS
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: FAIL [fdo#108767] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
[fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
[fdo#109241]: https://bugs.freedesktop.org/show_bug.cgi?id=109241
Participating hosts (48 -> 42)
--
Missing(6): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5405 -> Patchwork_11285
CI_DRM_5405: 92073deda0323ec6b2dd4066dd253235a54afa74 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4763: 805a99409542d7d72dda3b6dcd284a8869a3de16 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11285: 8de5d269d35a7b61cbcb16e99f2e5b83bea04917 @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11285/build_32bit.log
CALLscripts/checksyscalls.sh
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/i915_vma.o
In file included from ./include/drm/drm_mm.h:49:0,
from drivers/gpu/drm/i915/i915_vma.h:31,
from drivers/gpu/drm/i915/i915_vma.c:25:
drivers/gpu/drm/i915/selftests/i915_vma.c: In function ‘assert_remapped’:
drivers/gpu/drm/i915/selftests/i915_vma.c:436:18: error: format ‘%llx’ expects
argument of type ‘long long unsigned int’, but argument 7 has type ‘dma_addr_t
{aka unsigned int}’ [-Werror=format=]
DRM_DEBUG_KMS("sg %p %d %d %d %llx\n", sg, n, x, y, src);
^
./include/drm/drm_print.h:362:22: note: in definition of macro ‘DRM_DEBUG_KMS’
drm_dbg(DRM_UT_KMS, fmt, ##__VA_ARGS__)
^~~
drivers/gpu/drm/i915/selftests/i915_vma.c:445:18: error: format ‘%llx’ expects
argument of type ‘long long unsigned int’, but argument 4 has type ‘dma_addr_t
{aka unsigned int}’ [-Werror=format=]
DRM_DEBUG_KMS("sg %p dma %llx off = %d\n", sg, sg_dma_address(sg), offset);
^
./include/drm/drm_print.h:362:22: note: in definition of macro ‘DRM_DEBUG_KMS’
drm_dbg(DRM_UT_KMS, fmt, ##__VA_ARGS__)
^~~
cc1: all warnings being treated as errors
scripts/Makefile.build:276: recipe for target 'drivers/gpu/drm/i915/i915_vma.o'
failed
make[4]: *** [drivers/gpu/drm/i915/i915_vma.o] Error 1
scripts/Makefile.build:492: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:492: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:492: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1042: recipe for target 'drivers' failed
make: *** [drivers] Error 2
== Linux commits ==
8de5d269d35a drm/i915: Bump gen7+ fb size limits to 16kx16k
1541975fafd0 drm/i915: Bump gen4+ fb stride limit to 256KiB
dd746017e751 drm/i915: Overcome display engine stride limits via GTT remapping
7d5558eb88e7 drm/i915/selftests: Add live vma selftest
0b54a3a5a2f8 drm/i915/selftests: Add mock selftest for remapped vmas
ff6533f795e4 drm/i915: Add a new "remapped" gtt_view
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11285/
___
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: GTT remapping for display
== Series Details == Series: drm/i915: GTT remapping for display URL : https://patchwork.freedesktop.org/series/55095/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Add a new "remapped" gtt_view +drivers/gpu/drm/i915/i915_gem_gtt.c:3630:34: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:3630:34: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/../i915_drv.h:3546:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3550:16: warning: expression using sizeof(void) Commit: drm/i915/selftests: Add mock selftest for remapped vmas Okay! Commit: drm/i915/selftests: Add live vma selftest Okay! Commit: drm/i915: Overcome display engine stride limits via GTT remapping Okay! Commit: drm/i915: Bump gen4+ fb stride limit to 256KiB Okay! Commit: drm/i915: Bump gen7+ fb size limits to 16kx16k Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GTT remapping for display
== Series Details ==
Series: drm/i915: GTT remapping for display
URL : https://patchwork.freedesktop.org/series/55095/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ff6533f795e4 drm/i915: Add a new "remapped" gtt_view
-:97: CHECK:LINE_SPACING: Please don't use multiple blank lines
#97: FILE: drivers/gpu/drm/i915/i915_gem.c:6066:
+
+
-:245: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#245: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:195:
+ BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 9*sizeof(unsigned
int));
^
total: 0 errors, 0 warnings, 2 checks, 286 lines checked
0b54a3a5a2f8 drm/i915/selftests: Add mock selftest for remapped vmas
-:79: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#79: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:438:
+ if (left < PAGE_SIZE || left & (PAGE_SIZE-1)) {
^
-:98: CHECK:LINE_SPACING: Please don't use multiple blank lines
#98: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:457:
+
+
-:134: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional
statements (8, 8)
#134: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:511:
+ for (t = types; *t; t++) {
for (a = planes; a->width; a++) {
-:178: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code
refactoring
#178: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:581:
+ if (view.type ==
I915_GGTT_VIEW_ROTATED)
-:179: WARNING:LONG_LINE: line over 100 characters
#179: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:582:
+ sg =
assert_rotated(obj, , n, sg);
-:180: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code
refactoring
#180: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:583:
+ else
-:181: WARNING:LONG_LINE: line over 100 characters
#181: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:584:
+ sg =
assert_remapped(obj, , n, sg);
total: 0 errors, 5 warnings, 2 checks, 172 lines checked
7d5558eb88e7 drm/i915/selftests: Add live vma selftest
dd746017e751 drm/i915: Overcome display engine stride limits via GTT remapping
1541975fafd0 drm/i915: Bump gen4+ fb stride limit to 256KiB
-:41: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#41: FILE: drivers/gpu/drm/i915/intel_display.c:2478:
+ return 256*1024;
^
total: 0 errors, 0 warnings, 1 checks, 19 lines checked
8de5d269d35a drm/i915: Bump gen7+ fb size limits to 16kx16k
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[Intel-gfx] [PATCH v2 6/6] drm/i915: Bump gen7+ fb size limits to 16kx16k
From: Ville Syrjälä
With gtt remapping in place we can use arbitrarily large
framebuffers. Let's bump the limits to 16kx16k on gen7+.
The limit was chosen to match the maximum 2D surface size
of the 3D engine.
With the remapping we could easily go higher than that for the
display engine. However the modesetting ddx will blindly assume
it can handle whatever is reported via kms. The oversized
buffer dimensions are not caught by glamor nor Mesa until
finally an assert will trip when genxml attempts to pack the
SURFACE_STATE. So we pick a safe limit to avoid the X server
from crashing (or potentially misbehaving if the genxml asserts
are compiled out).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 543dcb4431d2..14de70eb105d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15331,16 +15331,22 @@ int intel_modeset_init(struct drm_device *dev)
}
}
- /* maximum framebuffer dimensions */
- if (IS_GEN(dev_priv, 2)) {
- dev->mode_config.max_width = 2048;
- dev->mode_config.max_height = 2048;
+ /*
+* Maximum framebuffer dimensions, chosen to match
+* the maximum render engine surface size on gen4+.
+*/
+ if (INTEL_GEN(dev_priv) >= 7) {
+ dev->mode_config.max_width = 16384;
+ dev->mode_config.max_height = 16384;
+ } else if (INTEL_GEN(dev_priv) >= 4) {
+ dev->mode_config.max_width = 8192;
+ dev->mode_config.max_height = 8192;
} else if (IS_GEN(dev_priv, 3)) {
dev->mode_config.max_width = 4096;
dev->mode_config.max_height = 4096;
} else {
- dev->mode_config.max_width = 8192;
- dev->mode_config.max_height = 8192;
+ dev->mode_config.max_width = 2048;
+ dev->mode_config.max_height = 2048;
}
if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 4/6] drm/i915: Overcome display engine stride limits via GTT remapping
From: Ville Syrjälä
The display engine stride limits are getting in our way. On SKL+
we are limited to 8k pixels, which is easily exceeded with three
4k displays. To overcome this limitation we can remap the pages
in the GTT to provide the display engine with a view of memory
with a smaller stride.
The code is mostly already there as We already play tricks with
the plane surface address and x/y offsets.
A few caveats apply:
* linear buffers need the fb stride to be page aligned, as
otherwise the remapped lines wouldn't start at the same
spot
* compressed buffers can't be remapped due to the new
ccs hash mode causing the virtual address of the pages
to affect the interpretation of the compressed data. IIRC
the old hash was limited to the low 12 bits so if we were
using that mode we could remap. As it stands we just refuse
to remapp with compressed fbs.
* no remapping gen2/3 as we'd need a fence for the remapped
vma, which we currently don't have. Need to deal with the
fence POT requirements, and do something about the gen2
gtt page size vs tile size difference
v2: Rebase due to is_ccs_modifier()
Fix up the skl+ stride_mult mess
memset() the gtt_view because otherwise we could leave
junk in plane[1] when going from 2 plane to 1 plane format
v3: intel_check_plane_stride() was split out
v4: Drop the aligned viewport stuff, it was meant for ccs which
can't be remapped anyway
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 332 ---
1 file changed, 255 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index db487d52c5ee..120eb6bd856d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1860,7 +1860,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
int color_plane)
switch (fb->modifier) {
case DRM_FORMAT_MOD_LINEAR:
- return cpp;
+ return intel_tile_size(dev_priv);
case I915_FORMAT_MOD_X_TILED:
if (IS_GEN(dev_priv, 2))
return 128;
@@ -1903,11 +1903,8 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
int color_plane)
static unsigned int
intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
{
- if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
- return 1;
- else
- return intel_tile_size(to_i915(fb->dev)) /
- intel_tile_width_bytes(fb, color_plane);
+ return intel_tile_size(to_i915(fb->dev)) /
+ intel_tile_width_bytes(fb, color_plane);
}
/* Return the tile dimensions in pixel units */
@@ -2164,16 +2161,8 @@ void intel_add_fb_offsets(int *x, int *y,
int color_plane)
{
- const struct intel_framebuffer *intel_fb =
to_intel_framebuffer(state->base.fb);
- unsigned int rotation = state->base.rotation;
-
- if (drm_rotation_90_or_270(rotation)) {
- *x += intel_fb->rotated[color_plane].x;
- *y += intel_fb->rotated[color_plane].y;
- } else {
- *x += intel_fb->normal[color_plane].x;
- *y += intel_fb->normal[color_plane].y;
- }
+ *x += state->color_plane[color_plane].x;
+ *y += state->color_plane[color_plane].y;
}
static u32 intel_adjust_tile_offset(int *x, int *y,
@@ -2453,6 +2442,82 @@ bool is_ccs_modifier(u64 modifier)
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
+static
+u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
+ u32 pixel_format, u64 modifier)
+{
+ struct intel_crtc *crtc;
+ struct intel_plane *plane;
+
+ /*
+* We assume the primary plane for pipe A has
+* the highest stride limits of them all.
+*/
+ crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
+ plane = to_intel_plane(crtc->base.primary);
+
+ return plane->max_stride(plane, pixel_format, modifier,
+DRM_MODE_ROTATE_0);
+}
+
+static
+u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
+ u32 pixel_format, u64 modifier)
+{
+ return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
+}
+
+static u32
+intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
+{
+ struct drm_i915_private *dev_priv = to_i915(fb->dev);
+
+ if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
+ u32 max_stride = intel_plane_fb_max_stride(dev_priv,
+ fb->format->format,
+ fb->modifier);
+
+ /*
+* To make remapping with linear generally feasible
+* we need the stride to be page aligned.
+*/
+ if (fb->pitches[color_plane] >
[Intel-gfx] [PATCH v2 3/6] drm/i915/selftests: Add live vma selftest
From: Ville Syrjälä
Add a live selftest to excercise rotated/remapped vmas. We simply
write through the rotated/remapped vma, and confirm that the data
appears in the right page when read through the normal vma.
Not sure what the fallout of making all rotated/remapped vmas
mappable/fenceable would be, hence I just hacked it in the test.
v2: Grab rpm reference (Chris)
GEM_BUG_ON(view.type not as expected) (Chris)
Allow CAN_FENCE for rotated/remapped vmas (Chris)
Update intel_plane_uses_fence() to ask for a fence
only for normal vmas on gen4+
Cc: Chris Wilson
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_vma.c | 8 -
drivers/gpu/drm/i915/intel_display.c | 4 +-
.../drm/i915/selftests/i915_live_selftests.h | 1 +
drivers/gpu/drm/i915/selftests/i915_vma.c | 140 ++
4 files changed, 144 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 9a039c36dc0c..865290751633 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -463,14 +463,6 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
GEM_BUG_ON(!vma->fence_size);
- /*
-* Explicitly disable for rotated VMA since the display does not
-* need the fence and the VMA is not accessible to other users.
-*/
- if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED ||
- vma->ggtt_view.type == I915_GGTT_VIEW_REMAPPED)
- return;
-
fenceable = (vma->node.size >= vma->fence_size &&
IS_ALIGNED(vma->node.start, vma->fence_alignment));
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c17a1723a589..db487d52c5ee 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2022,7 +2022,9 @@ static bool intel_plane_uses_fence(const struct
intel_plane_state *plane_state)
struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- return INTEL_GEN(dev_priv) < 4 || plane->has_fbc;
+ return INTEL_GEN(dev_priv) < 4 ||
+ (plane->has_fbc &&
+plane_state->view.type == I915_GGTT_VIEW_NORMAL);
}
struct i915_vma *
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index a15713cae3b3..095e25e92a36 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -15,6 +15,7 @@ selftest(workarounds, intel_workarounds_live_selftests)
selftest(requests, i915_request_live_selftests)
selftest(objects, i915_gem_object_live_selftests)
selftest(dmabuf, i915_gem_dmabuf_live_selftests)
+selftest(vma, i915_vma_live_selftests)
selftest(coherency, i915_gem_coherency_live_selftests)
selftest(gtt, i915_gem_gtt_live_selftests)
selftest(gem, i915_gem_live_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c
b/drivers/gpu/drm/i915/selftests/i915_vma.c
index 063143fa51bf..9fff70179add 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -826,3 +826,143 @@ int i915_vma_mock_selftests(void)
return err;
}
+static int igt_vma_remapped_gtt(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ const struct intel_remapped_plane_info planes[] = {
+ { .width = 1, .height = 1, .stride = 1 },
+ { .width = 2, .height = 2, .stride = 2 },
+ { .width = 4, .height = 4, .stride = 4 },
+ { .width = 8, .height = 8, .stride = 8 },
+
+ { .width = 3, .height = 5, .stride = 3 },
+ { .width = 3, .height = 5, .stride = 4 },
+ { .width = 3, .height = 5, .stride = 5 },
+
+ { .width = 5, .height = 3, .stride = 5 },
+ { .width = 5, .height = 3, .stride = 7 },
+ { .width = 5, .height = 3, .stride = 9 },
+
+ { .width = 4, .height = 6, .stride = 6 },
+ { .width = 6, .height = 4, .stride = 6 },
+ { }
+ }, *p;
+ enum i915_ggtt_view_type types[] = {
+ I915_GGTT_VIEW_ROTATED,
+ I915_GGTT_VIEW_REMAPPED,
+ 0,
+ }, *t;
+ struct drm_i915_gem_object *obj;
+ int err = 0;
+
+ obj = i915_gem_object_create_internal(i915, 10 * 10 * PAGE_SIZE);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ mutex_lock(>drm.struct_mutex);
+
+ intel_runtime_pm_get(i915);
+
+ for (t = types; *t; t++) {
+ for (p = planes; p->width; p++) {
+ struct i915_ggtt_view view = {
+ .type = *t,
+ .rotated.plane[0] = *p,
+
[Intel-gfx] [PATCH v2 5/6] drm/i915: Bump gen4+ fb stride limit to 256KiB
From: Ville Syrjälä
With gtt remapping plugged in we can simply raise the stride
limit on gen4+. Let's just arbitraily pick 256 KiB as the limit.
No remapping CCS because the virtual address of each page actually
matters due to the new hash mode
(WaCompressedResourceDisplayNewHashMode:skl,kbl etc.), and no remapping
on gen2/3 due to lack of fence on the remapped vma.
v2: Rebase due to is_ccs_modifier()
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 120eb6bd856d..543dcb4431d2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2464,6 +2464,19 @@ static
u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier)
{
+ /*
+* Arbitrary limit for gen4+. We can deal with any page
+* aligned stride via GTT remapping. Gen2/3 need a fence
+* for tiled scanout which the remapped vma won't have,
+* so we don't allow remapping on those platforms.
+*
+* Also the new hash mode we use for CCS isn't compatible
+* with remapping as the virtual address of the pages
+* affects the compressed data.
+*/
+ if (INTEL_GEN(dev_priv) >= 4 && !is_ccs_modifier(modifier))
+ return 256*1024;
+
return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
}
--
2.19.2
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/6] drm/i915: Add a new "remapped" gtt_view
From: Ville Syrjälä
To overcome display engine stride limits we'll want to remap the
pages in the GTT. To that end we need a new gtt_view type which
is just like the "rotated" type except not rotated.
v2: Use intel_remapped_plane_info base type
s/unused/unused_mbz/ (Chris)
Separate BUILD_BUG_ON()s (Chris)
Use I915_GTT_PAGE_SIZE (Chris)
v3: Use i915_gem_object_get_dma_address() (Chris)
Trim the sg (Tvrtko)
v4: Actually trim this time. Limit the max length
to one row of pages to keep things simple
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_debugfs.c | 12
drivers/gpu/drm/i915/i915_drv.h | 4 ++
drivers/gpu/drm/i915/i915_gem.c | 17 -
drivers/gpu/drm/i915/i915_gem_gtt.c | 88 +++
drivers/gpu/drm/i915/i915_gem_gtt.h | 25 +--
drivers/gpu/drm/i915/i915_vma.c | 6 +-
drivers/gpu/drm/i915/i915_vma.h | 3 +
drivers/gpu/drm/i915/intel_display.c | 11 +++
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/selftests/i915_vma.c | 6 +-
10 files changed, 163 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index d460ef522d9c..cab7771799ad 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -196,6 +196,18 @@ describe_obj(struct seq_file *m, struct
drm_i915_gem_object *obj)
vma->ggtt_view.rotated.plane[1].offset);
break;
+ case I915_GGTT_VIEW_REMAPPED:
+ seq_printf(m, ", remapped [(%ux%u, stride=%u,
offset=%u), (%ux%u, stride=%u, offset=%u)]",
+
vma->ggtt_view.remapped.plane[0].width,
+
vma->ggtt_view.remapped.plane[0].height,
+
vma->ggtt_view.remapped.plane[0].stride,
+
vma->ggtt_view.remapped.plane[0].offset,
+
vma->ggtt_view.remapped.plane[1].width,
+
vma->ggtt_view.remapped.plane[1].height,
+
vma->ggtt_view.remapped.plane[1].stride,
+
vma->ggtt_view.remapped.plane[1].offset);
+ break;
+
default:
MISSING_CASE(vma->ggtt_view.type);
break;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5df26ccda8a4..cef76cf343c4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2845,6 +2845,10 @@ i915_gem_object_get_dirty_page(struct
drm_i915_gem_object *obj,
unsigned int n);
dma_addr_t
+i915_gem_object_get_dma_address_len(struct drm_i915_gem_object *obj,
+ unsigned long n,
+ unsigned int *len);
+dma_addr_t
i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
unsigned long n);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ea85da393662..f65d81f4f3d7 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -6041,16 +6041,29 @@ i915_gem_object_get_dirty_page(struct
drm_i915_gem_object *obj,
}
dma_addr_t
-i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
- unsigned long n)
+i915_gem_object_get_dma_address_len(struct drm_i915_gem_object *obj,
+ unsigned long n,
+ unsigned int *len)
{
struct scatterlist *sg;
unsigned int offset;
sg = i915_gem_object_get_sg(obj, n, );
+
+ if (len)
+ *len = sg_dma_len(sg) - (offset << PAGE_SHIFT);
+
return sg_dma_address(sg) + (offset << PAGE_SHIFT);
}
+dma_addr_t
+i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
+ unsigned long n)
+{
+ return i915_gem_object_get_dma_address_len(obj, n, NULL);
+}
+
+
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align)
{
struct sg_table *pages;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a8807fbed0aa..be5dbbb1b6ff 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3605,6 +3605,89 @@ intel_rotate_pages(struct intel_rotation_info *rot_info,
return ERR_PTR(ret);
}
+static struct scatterlist *
+remap_pages(struct drm_i915_gem_object *obj, unsigned int offset,
+ unsigned int width, unsigned int height,
+ unsigned int stride,
+
[Intel-gfx] [PATCH v2 2/6] drm/i915/selftests: Add mock selftest for remapped vmas
From: Ville Syrjälä
Extend the rotated vma mock selftest to cover remapped vmas as
well.
TODO: reindent the loops I guess? Left like this for now to
ease review
v2: Include the vma type in the error message (Chris)
v3: Deal with trimmed sg
Cc: Chris Wilson
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/selftests/i915_vma.c | 105 --
1 file changed, 97 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c
b/drivers/gpu/drm/i915/selftests/i915_vma.c
index 4fc49c27f13c..063143fa51bf 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -58,7 +58,7 @@ static bool assert_vma(struct i915_vma *vma,
static struct i915_vma *
checked_vma_instance(struct drm_i915_gem_object *obj,
struct i915_address_space *vm,
-struct i915_ggtt_view *view)
+const struct i915_ggtt_view *view)
{
struct i915_vma *vma;
bool ok = true;
@@ -395,13 +395,81 @@ assert_rotated(struct drm_i915_gem_object *obj,
return sg;
}
+static unsigned long remapped_index(const struct intel_remapped_info *r,
+ unsigned int n,
+ unsigned int x,
+ unsigned int y)
+{
+ return (r->plane[n].stride * y +
+ r->plane[n].offset + x);
+}
+
+static struct scatterlist *
+assert_remapped(struct drm_i915_gem_object *obj,
+ const struct intel_remapped_info *r, unsigned int n,
+ struct scatterlist *sg)
+{
+ unsigned int x, y;
+ unsigned int left = 0;
+ unsigned int offset;
+
+ for (y = 0; y < r->plane[n].height; y++) {
+ for (x = 0; x < r->plane[n].width; x++) {
+ unsigned long src_idx;
+ dma_addr_t src;
+
+ if (!sg) {
+ pr_err("Invalid sg table: too short at plane
%d, (%d, %d)!\n",
+ n, x, y);
+ return ERR_PTR(-EINVAL);
+ }
+ if (!left) {
+ offset = 0;
+ left = sg_dma_len(sg);
+ }
+
+ DRM_DEBUG_KMS("sg %p start left %d\n", sg, left);
+
+ src_idx = remapped_index(r, n, x, y);
+ src = i915_gem_object_get_dma_address(obj, src_idx);
+
+ DRM_DEBUG_KMS("sg %p %d %d %d %llx\n", sg, n, x, y,
src);
+
+ if (left < PAGE_SIZE || left & (PAGE_SIZE-1)) {
+ pr_err("Invalid sg.length, found %d, expected
%lu for remapped page (%d, %d) [src index %lu]\n",
+ sg_dma_len(sg), PAGE_SIZE,
+ x, y, src_idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ DRM_DEBUG_KMS("sg %p dma %llx off = %d\n", sg,
sg_dma_address(sg), offset);
+
+ if (sg_dma_address(sg) + offset != src) {
+ pr_err("Invalid address for remapped page (%d,
%d) [src index %lu]\n",
+ x, y, src_idx);
+ return ERR_PTR(-EINVAL);
+ }
+ DRM_DEBUG_KMS("sg %p end left %d\n", sg, left);
+
+ left -= PAGE_SIZE;
+ offset += PAGE_SIZE;
+
+
+ if (!left)
+ sg = sg_next(sg);
+ }
+ }
+
+ return sg;
+}
+
static unsigned int rotated_size(const struct intel_remapped_plane_info *a,
const struct intel_remapped_plane_info *b)
{
return a->width * a->height + b->width * b->height;
}
-static int igt_vma_rotate(void *arg)
+static int igt_vma_rotate_remap(void *arg)
{
struct drm_i915_private *i915 = arg;
struct i915_address_space *vm = >ggtt.vm;
@@ -424,6 +492,11 @@ static int igt_vma_rotate(void *arg)
{ .width = 6, .height = 4, .stride = 6 },
{ }
}, *a, *b;
+ enum i915_ggtt_view_type types[] = {
+ I915_GGTT_VIEW_ROTATED,
+ I915_GGTT_VIEW_REMAPPED,
+ 0,
+ }, *t;
const unsigned int max_pages = 64;
int err = -ENOMEM;
@@ -435,6 +508,7 @@ static int igt_vma_rotate(void *arg)
if (IS_ERR(obj))
goto out;
+ for (t = types; *t; t++) {
for (a = planes; a->width; a++) {
for (b = planes + ARRAY_SIZE(planes); b-- != planes; ) {
struct i915_ggtt_view view;
@@ -445,7 +519,7 @@ static int igt_vma_rotate(void *arg)
GEM_BUG_ON(max_offset > max_pages);
[Intel-gfx] [PATCH v2 0/6] drm/i915: GTT remapping for display
From: Ville Syrjälä Another year, another gtt remapping series. Main changes: - Actually trim the sg a bit - Drop the earlier aligned viewport tricks since they were there for ccs which we can't remap anyway - Maybe something else I forgot already Series available here: git://github.com/vsyrjala/linux.git fb_vma_remap_13 Ville Syrjälä (6): drm/i915: Add a new "remapped" gtt_view drm/i915/selftests: Add mock selftest for remapped vmas drm/i915/selftests: Add live vma selftest drm/i915: Overcome display engine stride limits via GTT remapping drm/i915: Bump gen4+ fb stride limit to 256KiB drm/i915: Bump gen7+ fb size limits to 16kx16k drivers/gpu/drm/i915/i915_debugfs.c | 12 + drivers/gpu/drm/i915/i915_drv.h | 4 + drivers/gpu/drm/i915/i915_gem.c | 17 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 88 drivers/gpu/drm/i915/i915_gem_gtt.h | 25 +- drivers/gpu/drm/i915/i915_vma.c | 10 +- drivers/gpu/drm/i915/i915_vma.h | 3 + drivers/gpu/drm/i915/intel_display.c | 378 ++ drivers/gpu/drm/i915/intel_drv.h | 1 + .../drm/i915/selftests/i915_live_selftests.h | 1 + drivers/gpu/drm/i915/selftests/i915_vma.c | 251 +++- 11 files changed, 682 insertions(+), 108 deletions(-) -- 2.19.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cmdparser: whitelist needed predicate registers for Anv (rev2)
== Series Details ==
Series: drm/i915/cmdparser: whitelist needed predicate registers for Anv (rev2)
URL : https://patchwork.freedesktop.org/series/55083/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5404 -> Patchwork_11284
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/55083/revisions/2/mbox/
Known issues
Here are the changes found in Patchwork_11284 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_selftest@live_contexts:
- fi-icl-u2: NOTRUN -> DMESG-FAIL [fdo#108569]
* igt@i915_selftest@live_gem:
- fi-bdw-gvtdvm: PASS -> DMESG-WARN [fdo#108797]
Possible fixes
* igt@i915_selftest@live_hangcheck:
- fi-bwr-2160:DMESG-FAIL [fdo#108735] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735
[fdo#108797]: https://bugs.freedesktop.org/show_bug.cgi?id=108797
[fdo#109241]: https://bugs.freedesktop.org/show_bug.cgi?id=109241
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109316]: https://bugs.freedesktop.org/show_bug.cgi?id=109316
Participating hosts (45 -> 42)
--
Additional (3): fi-byt-j1900 fi-icl-u2 fi-hsw-peppy
Missing(6): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5404 -> Patchwork_11284
CI_DRM_5404: c51dc608699b2dcfe6d2f6981773f98d1b9f0c86 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4763: 805a99409542d7d72dda3b6dcd284a8869a3de16 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11284: bb84d5cf2f147c0fc38abb16565c00d72cc29770 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
bb84d5cf2f14 drm/i915/cmdparser: whitelist needed predicate registers for Anv
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11284/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Prevent concurrent GGTT update and use on Braswell (again)
== Series Details ==
Series: drm/i915: Prevent concurrent GGTT update and use on Braswell (again)
URL : https://patchwork.freedesktop.org/series/55086/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5404 -> Patchwork_11283
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/55086/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_11283 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_contexts:
- fi-icl-u2: NOTRUN -> DMESG-FAIL [fdo#108569]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
Possible fixes
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: FAIL [fdo#108767] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109316]: https://bugs.freedesktop.org/show_bug.cgi?id=109316
Participating hosts (45 -> 40)
--
Additional (3): fi-byt-j1900 fi-icl-u2 fi-hsw-peppy
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-bwr-2160 fi-glk-j4005 fi-ivb-3520m fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5404 -> Patchwork_11283
CI_DRM_5404: c51dc608699b2dcfe6d2f6981773f98d1b9f0c86 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4763: 805a99409542d7d72dda3b6dcd284a8869a3de16 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11283: 69d208d23911636c0c68c37653c572bad0a917b9 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
69d208d23911 drm/i915: Prevent concurrent GGTT update and use on Braswell
(again)
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11283/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/cmdparser: whitelist needed predicate registers for Anv
There is no reason not to whitelist those registers. In particular
MI_PREDICATE_RESULT can be loaded outside of MI_PREDICATE through
other registers to predicate other commands.
v2: Define MI_PREDICATE_DATA_UDW (Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 6 +-
drivers/gpu/drm/i915/i915_reg.h| 3 +++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 95478db9998b..c5bf14c3f540 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -549,6 +549,8 @@ static const struct drm_i915_reg_descriptor
gen7_render_regs[] = {
REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
REG64(MI_PREDICATE_SRC0),
REG64(MI_PREDICATE_SRC1),
+ REG64(MI_PREDICATE_DATA),
+ REG32(MI_PREDICATE_RESULT),
REG32(GEN7_3DPRIM_END_OFFSET),
REG32(GEN7_3DPRIM_START_VERTEX),
REG32(GEN7_3DPRIM_VERTEX_COUNT),
@@ -1382,6 +1384,8 @@ int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv)
*the parser enabled.
* 9. Don't whitelist or handle oacontrol specially, as ownership
*for oacontrol state is moving to i915-perf.
+* 10. Whitelist predicate data/result registers for conditional
+* rendering in Anv.
*/
- return 9;
+ return 10;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ca8026ec0655..408dd59cdbdc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -461,6 +461,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
#define MI_PREDICATE_SRC1 _MMIO(0x2408)
#define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
+#define MI_PREDICATE_DATA _MMIO(0x2410)
+#define MI_PREDICATE_DATA_UDW _MMIO(0x2414)
+#define MI_PREDICATE_RESULT_MMIO(0x2418)
#define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
#define LOWER_SLICE_ENABLED (1 << 0)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Prevent concurrent GGTT update and use on Braswell (again)
== Series Details ==
Series: drm/i915: Prevent concurrent GGTT update and use on Braswell (again)
URL : https://patchwork.freedesktop.org/series/55086/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
69d208d23911 drm/i915: Prevent concurrent GGTT update and use on Braswell
(again)
-:14: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 5bab6f60cb4d ("drm/i915:
Serialise updates to GGTT with access through GGTT on Braswell")'
#14:
commit 5bab6f60cb4d1417ad7c599166bcfec87529c1a2
-:22: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 4509276ee824 ("drm/i915: Remove
Braswell GGTT update w/a")'
#22:
commit 4509276ee824bb967885c095c610767e42345c36
-:35: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#35:
References: 5bab6f60cb4d ("drm/i915: Serialise updates to GGTT with access
through GGTT on Braswell")
-:35: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 5bab6f60cb4d ("drm/i915:
Serialise updates to GGTT with access through GGTT on Braswell")'
#35:
References: 5bab6f60cb4d ("drm/i915: Serialise updates to GGTT with access
through GGTT on Braswell")
-:36: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 4509276ee824 ("drm/i915: Remove
Braswell GGTT update w/a")'
#36:
References: 4509276ee824 ("drm/i915: Remove Braswell GGTT update w/a")
total: 4 errors, 1 warnings, 0 checks, 9 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/cmdparser: whitelist needed predicate registers for Anv
== Series Details ==
Series: drm/i915/cmdparser: whitelist needed predicate registers for Anv
URL : https://patchwork.freedesktop.org/series/55083/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/i915_cmd_parser.o
drivers/gpu/drm/i915/i915_cmd_parser.c:552:8: error: ‘MI_PREDICATE_DATA_UDW’
undeclared here (not in a function); did you mean ‘MI_PREDICATE_SRC1_UDW’?
REG64(MI_PREDICATE_DATA),
^
drivers/gpu/drm/i915/i915_cmd_parser.c:530:12: note: in definition of macro
‘REG64’
{ .addr = _reg ## _UDW }
^~~~
scripts/Makefile.build:276: recipe for target
'drivers/gpu/drm/i915/i915_cmd_parser.o' failed
make[4]: *** [drivers/gpu/drm/i915/i915_cmd_parser.o] Error 1
scripts/Makefile.build:492: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:492: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:492: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1042: recipe for target 'drivers' failed
make: *** [drivers] Error 2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Try to sanitize bogus DPLL state left over by broken SNB BIOSen (rev2)
== Series Details ==
Series: drm/i915: Try to sanitize bogus DPLL state left over by broken SNB
BIOSen (rev2)
URL : https://patchwork.freedesktop.org/series/54942/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5404 -> Patchwork_11281
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/54942/revisions/2/mbox/
Known issues
Here are the changes found in Patchwork_11281 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_contexts:
- fi-icl-u2: NOTRUN -> DMESG-FAIL [fdo#108569]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
Possible fixes
* igt@i915_selftest@live_hangcheck:
- fi-bwr-2160:DMESG-FAIL [fdo#108735] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109316]: https://bugs.freedesktop.org/show_bug.cgi?id=109316
Participating hosts (45 -> 42)
--
Additional (3): fi-byt-j1900 fi-icl-u2 fi-hsw-peppy
Missing(6): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-bdw-samus fi-skl-6600u
Build changes
-
* Linux: CI_DRM_5404 -> Patchwork_11281
CI_DRM_5404: c51dc608699b2dcfe6d2f6981773f98d1b9f0c86 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4763: 805a99409542d7d72dda3b6dcd284a8869a3de16 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11281: 5bbd1b55d21a134a33ba9ddb833b173b86da23b7 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5bbd1b55d21a drm/i915: Try to sanitize bogus DPLL state left over by broken SNB
BIOSen
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11281/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Prevent concurrent GGTT update and use on Braswell (again)
On Braswell, under heavy stress, if we update the GGTT while
simultaneously accessing another region inside the GTT, we are returned
the wrong values. To prevent this we stop the machine to update the GGTT
entries so that no memory traffic can occur at the same time.
This was first spotted in
commit 5bab6f60cb4d1417ad7c599166bcfec87529c1a2
Author: Chris Wilson
Date: Fri Oct 23 18:43:32 2015 +0100
drm/i915: Serialise updates to GGTT with access through GGTT on Braswell
but removed again in forlorn hope with
commit 4509276ee824bb967885c095c610767e42345c36
Author: Chris Wilson
Date: Mon Feb 20 12:47:18 2017 +
drm/i915: Remove Braswell GGTT update w/a
However, gem_concurrent_blit is once again only stable with the patch
applied and CI is detecting the odd failure in forked gem_mmap_gtt tests
(which smell like the same issue).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105591
Testcase: igt/gem_concurrent_blit
Testcase: igt/gem_mmap_gtt/*forked*
References: 5bab6f60cb4d ("drm/i915: Serialise updates to GGTT with access
through GGTT on Braswell")
References: 4509276ee824 ("drm/i915: Remove Braswell GGTT update w/a")
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a8807fbed0aa..9241328b58f2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3227,7 +3227,8 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
/* Serialize GTT updates with aperture access on BXT if VT-d is on. */
- if (intel_ggtt_update_needs_vtd_wa(dev_priv)) {
+ if (intel_ggtt_update_needs_vtd_wa(dev_priv) ||
+ IS_CHERRYVIEW(dev_priv) /* fails with concurrent use/update */) {
ggtt->vm.insert_entries = bxt_vtd_ggtt_insert_entries__BKL;
ggtt->vm.insert_page= bxt_vtd_ggtt_insert_page__BKL;
if (ggtt->vm.clear_range != nop_clear_range)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/cmdparser: whitelist needed predicate registers for Anv
There is no reason not to whitelist those registers. In particular
MI_PREDICATE_RESULT can be loaded outside of MI_PREDICATE through
other registers to predicate other commands.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 6 +-
drivers/gpu/drm/i915/i915_reg.h| 2 ++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 95478db9998b..c5bf14c3f540 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -549,6 +549,8 @@ static const struct drm_i915_reg_descriptor
gen7_render_regs[] = {
REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
REG64(MI_PREDICATE_SRC0),
REG64(MI_PREDICATE_SRC1),
+ REG64(MI_PREDICATE_DATA),
+ REG32(MI_PREDICATE_RESULT),
REG32(GEN7_3DPRIM_END_OFFSET),
REG32(GEN7_3DPRIM_START_VERTEX),
REG32(GEN7_3DPRIM_VERTEX_COUNT),
@@ -1382,6 +1384,8 @@ int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv)
*the parser enabled.
* 9. Don't whitelist or handle oacontrol specially, as ownership
*for oacontrol state is moving to i915-perf.
+* 10. Whitelist predicate data/result registers for conditional
+* rendering in Anv.
*/
- return 9;
+ return 10;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ca8026ec0655..5c05d73eec8f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -461,6 +461,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
#define MI_PREDICATE_SRC1 _MMIO(0x2408)
#define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
+#define MI_PREDICATE_DATA _MMIO(0x2410)
+#define MI_PREDICATE_RESULT_MMIO(0x2418)
#define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
#define LOWER_SLICE_ENABLED (1 << 0)
--
2.20.1
___
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[Intel-gfx] [PATCH v2] drm/i915: Try to sanitize bogus DPLL state left over by broken SNB BIOSen
From: Ville Syrjälä
Certain SNB machines (eg. ASUS K53SV) seem to have a broken BIOS
which misprograms the hardware badly when encountering a suitably
high resolution display. The programmed pipe timings are somewhat
bonkers and the DPLL is totally misprogrammed (P divider == 0).
That will result in atomic commit timeouts as apparently the pipe
is sufficiently stuck to not signal vblank interrupts.
IIRC something like this was also observed on some other SNB
machine years ago (might have been a Dell XPS 8300) but a BIOS
update cured it. Sadly looks like this was never fixed for the
ASUS K53SV as the latest BIOS (K53SV.320 11/11/2011) is still
broken.
The quickest way to deal with this seems to be to shut down
the pipe+ports+DPLL. Unfortunately doing this during the
normal sanitization phase isn't quite soon enough as we
already spew several WARNs about the bogus hardware state.
But it's better than hanging the boot for a few dozen seconds.
Since this is limited to a few old machines it doesn't seem
entirely worthwile to try and rework the readout+sanitization
code to handle it more gracefully.
v2: Fix potential NULL deref (kbuild test robot)
Constify has_bogus_dpll_config()
Cc: sta...@vger.kernel.org # v4.20+
Cc: Daniel Kamil Kozar
Reported-by: Daniel Kamil Kozar
Tested-by: Daniel Kamil Kozar
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109245
Fixes: 516a49cc1946 ("drm/i915: Fix assert_plane() warning on bootup with
external display")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 50
1 file changed, 44 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5dc0de89c49e..6cd6048b4731 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15438,16 +15438,45 @@ static void intel_sanitize_crtc(struct intel_crtc
*crtc,
}
}
+static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+
+ /*
+* Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
+* the hardware when a high res displays plugged in. DPLL P
+* divider is zero, and the pipe timings are bonkers. We'll
+* try to disable everything in that case.
+*
+* FIXME would be nice to be able to sanitize this state
+* without several WARNs, but for now let's take the easy
+* road.
+*/
+ return IS_GEN(dev_priv, 6) &&
+ crtc_state->base.active &&
+ crtc_state->shared_dpll &&
+ crtc_state->port_clock == 0;
+}
+
static void intel_sanitize_encoder(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_connector *connector;
+ struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
+ struct intel_crtc_state *crtc_state = crtc ?
+ to_intel_crtc_state(crtc->base.state) : NULL;
/* We need to check both for a crtc link (meaning that the
* encoder is active and trying to read from a pipe) and the
* pipe itself being active. */
- bool has_active_crtc = encoder->base.crtc &&
- to_intel_crtc(encoder->base.crtc)->active;
+ bool has_active_crtc = crtc_state &&
+ crtc_state->base.active;
+
+ if (crtc_state && has_bogus_dpll_config(crtc_state)) {
+ DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling
pipe %c\n",
+ pipe_name(crtc->pipe));
+ has_active_crtc = false;
+ }
connector = intel_encoder_find_connector(encoder);
if (connector && !has_active_crtc) {
@@ -15458,16 +15487,25 @@ static void intel_sanitize_encoder(struct
intel_encoder *encoder)
/* Connector is active, but has no active pipe. This is
* fallout from our resume register restoring. Disable
* the encoder manually again. */
- if (encoder->base.crtc) {
- struct drm_crtc_state *crtc_state =
encoder->base.crtc->state;
+ if (crtc_state) {
+ struct drm_encoder *best_encoder;
DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
encoder->base.base.id,
encoder->base.name);
+
+ /* avoid oopsing in case the hooks consult best_encoder
*/
+ best_encoder = connector->base.state->best_encoder;
+ connector->base.state->best_encoder = >base;
+
if (encoder->disable)
- encoder->disable(encoder,
to_intel_crtc_state(crtc_state), connector->base.state);
+
[Intel-gfx] ✓ Fi.CI.BAT: success for Enable/disable gamma/csc dynamically and fix C8
== Series Details ==
Series: Enable/disable gamma/csc dynamically and fix C8
URL : https://patchwork.freedesktop.org/series/55081/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5404 -> Patchwork_11280
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/55081/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_11280 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_contexts:
- fi-icl-u2: NOTRUN -> DMESG-FAIL [fdo#108569]
* igt@pm_rpm@basic-rte:
- fi-bsw-kefka: PASS -> FAIL [fdo#108800]
Possible fixes
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: FAIL [fdo#108767] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109316]: https://bugs.freedesktop.org/show_bug.cgi?id=109316
Participating hosts (45 -> 40)
--
Additional (3): fi-byt-j1900 fi-icl-u2 fi-hsw-peppy
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-bdw-5557u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-bdw-samus fi-skl-6600u
Build changes
-
* Linux: CI_DRM_5404 -> Patchwork_11280
CI_DRM_5404: c51dc608699b2dcfe6d2f6981773f98d1b9f0c86 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4763: 805a99409542d7d72dda3b6dcd284a8869a3de16 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11280: cb493c538af7fb058a44b179ee6b9b771282ce3f @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cb493c538af7 drm/i915: Disable pipe gamma when C8 pixel format is used
00cf0ace1712 drm/i915: Turn off pipe CSC when it's not needed
da7ea155c150 drm/i915: Turn off pipe gamma when it's not needed.
88de7f4faa5a drm/i915: Track pipe csc enable in crtc state
7fb08d2ae464 drm/i915: Track pipe gamma enable/disable in crtc state
d957bacac7cd drm/i915: Populate gamma_mode for all platforms
544c73d70496 drm/i915: Move LUT programming to happen after vblank waits
eb35618583b0 drm/i915: Split color mgmt based on single vs. double buffered
registers
e4f2442c4803 drm/i915: Pull GAMMA_MODE write out from haswell_load_luts()
9c79ce51c6e6 drm/i915: Constify the state arguments to the color management
stuff
c0564fda1b3b drm/i915: Precompute gamma_mode
43cec2bfb86d drm/i915: Split the gamma/csc enable bits from the plane_ctl()
function
066d50880adb drm/i915: Clean up intel_plane_atomic_check_with_state()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11280/
___
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Re: [Intel-gfx] drm/i915: Watchdog timeout: IRQ handler for gen8+
On 11/01/19 00:22, Tvrtko Ursulin wrote: On 11/01/2019 00:47, Antonio Argenziano wrote: On 07/01/19 08:58, Tvrtko Ursulin wrote: On 07/01/2019 13:57, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-01-07 13:43:29) On 07/01/2019 11:58, Tvrtko Ursulin wrote: [snip] Note about future interaction with preemption: Preemption could happen in a command sequence prior to watchdog counter getting disabled, resulting in watchdog being triggered following preemption (e.g. when watchdog had been enabled in the low priority batch). The driver will need to explicitly disable the watchdog counter as part of the preemption sequence. Does the series take care of preemption? I did not find that it does. Oh. I hoped that the watchdog was saved as part of the context... Then despite preemption, the timeout would resume from where we left off as soon as it was back on the gpu. If the timeout remaining was context saved it would be much simpler (at least on first glance), please say it is. I made my comments going only by the text from the commit message and the absence of any preemption special handling. Having read the spec, the situation seems like this: * Watchdog control and threshold register are context saved and restored. * On a context switch watchdog counter is reset to zero and automatically disabled until enabled by a context restore or explicitly. So it sounds the commit message could be wrong that special handling is needed from this direction. But read till the end on the restriction listed. * Watchdog counter is reset to zero and is not accumulated across multiple submission of the same context (due preemption). I read this as - after preemption contexts gets a new full timeout allocation. Or in other words, if a context is preempted N times, it's cumulative watchdog timeout will be N * set value. This could be theoretically exploitable to bypass the timeout. If a client sets up two contexts with prio -1 and -2, and keeps submitting periodical no-op batches against prio -1 context, while prio -2 is it's own hog, then prio -2 context defeats the watchdog timer. I think.. would appreciate is someone challenged this conclusion. I think you are right that is a possibility but, is that a problem? The client can just not set the threshold to bypass the timeout. Also because you need the hanging batch to be simply preemptible, you cannot disrupt any work from another client that is higher priority. This is But I think higher priority client can have the same effect on the lower priority purely by accident, no? As a real world example, user kicks off an background transcoding job, which happens to use prio -2, and uses the watchdog timer. At the same time user watches a video from a player of normal priority. This causes periodic, say 24Hz, preemption events, due frame decoding activity on the same engine as the transcoding client. Does this defeat the watchdog timer for the former is the question? Then the questions of can we do something about it and whether it really isn't a problem? I guess it depends if you consider that timeout as the maximum lifespan a workload can have or max contiguous active time. Maybe it is not disrupting higher priority clients but it is causing an time unbound power drain. pretty much the same behavior of hangcheck IIRC so something we already accept. You mean today hangcheck wouldn't notice a hanging batch in the same scenario as above? If so it sounds like a huge gap we need to try and fix. My understanding of it is that we only keep a record of what was running the last time hangcheck was run so it is possible to trick it into resetting when a preemption occurs but I could be missing something. And finally there is one programming restriction which says: * SW must not preempt the workload which has watchdog enabled. Either it must: a) disable preemption for that workload completely, or b) disable the watchdog via mmio write before any write to ELSP This seems it contradiction with the statement that the counter gets disabled on context switch and stays disabled. I did not spot anything like this in the series. So it would seem the commit message is correct after all. It would be good if someone could re-read the bspec text on register 0x2178 to double check what I wrote. The way I read it is that the restriction applies only to some platforms where the 'normal' description doesn't apply. You are right. Are the listed parts in the field so the series would have to handle this or we can ignore it? I think there is something we need to handle e.g. BXT. Antonio Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable/disable gamma/csc dynamically and fix C8
== Series Details == Series: Enable/disable gamma/csc dynamically and fix C8 URL : https://patchwork.freedesktop.org/series/55081/ State : warning == Summary == $ dim checkpatch origin/drm-tip 066d50880adb drm/i915: Clean up intel_plane_atomic_check_with_state() 43cec2bfb86d drm/i915: Split the gamma/csc enable bits from the plane_ctl() function c0564fda1b3b drm/i915: Precompute gamma_mode 9c79ce51c6e6 drm/i915: Constify the state arguments to the color management stuff e4f2442c4803 drm/i915: Pull GAMMA_MODE write out from haswell_load_luts() eb35618583b0 drm/i915: Split color mgmt based on single vs. double buffered registers 544c73d70496 drm/i915: Move LUT programming to happen after vblank waits d957bacac7cd drm/i915: Populate gamma_mode for all platforms -:34: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #34: FILE: drivers/gpu/drm/i915/i915_reg.h:5588: +#define PIPECONF_GAMMA_MODE(x) ((x)<<24) /* pass in GAMMA_MODE_MODE_* */ ^ total: 0 errors, 0 warnings, 1 checks, 146 lines checked 7fb08d2ae464 drm/i915: Track pipe gamma enable/disable in crtc state 88de7f4faa5a drm/i915: Track pipe csc enable in crtc state da7ea155c150 drm/i915: Turn off pipe gamma when it's not needed. 00cf0ace1712 drm/i915: Turn off pipe CSC when it's not needed cb493c538af7 drm/i915: Disable pipe gamma when C8 pixel format is used ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/13] drm/i915: Turn off pipe CSC when it's not needed
From: Ville Syrjälä
As with pipe gamma we can avoid the potential precision loss from
the pipe csc unit when there is no need to use it. And again
we need the same logic for updating the planes.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_color.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index a8b7428a64bf..789b04bb51d2 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -659,7 +659,8 @@ intel_color_add_affected_planes(struct intel_crtc_state
*new_crtc_state)
intel_atomic_get_old_crtc_state(state, crtc);
struct intel_plane *plane;
- if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable)
+ if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable &&
+ new_crtc_state->csc_enable == old_crtc_state->csc_enable)
return 0;
for_each_intel_plane_on_crtc(_priv->drm, crtc, plane) {
@@ -684,6 +685,7 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
const struct drm_property_blob *degamma_lut =
crtc_state->base.degamma_lut;
size_t gamma_length, degamma_length;
+ bool limited_color_range = false;
int ret;
degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
@@ -693,7 +695,11 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
if (INTEL_GEN(dev_priv) >= 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
- crtc_state->csc_enable = true;
+ limited_color_range = crtc_state->limited_color_range;
+
+ crtc_state->csc_enable =
+ crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
+ crtc_state->base.ctm || limited_color_range;
ret = intel_color_add_affected_planes(crtc_state);
if (ret)
--
2.19.2
___
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[Intel-gfx] [PATCH 08/13] drm/i915: Populate gamma_mode for all platforms
From: Ville Syrjälä
On pre-HSW gamma mode is configured via PIPECONF. The bits are
the same except shifted up, so we can reuse just store them in
crtc_state->gamma_mode in the HSW+ way, allowing us to share
some code later.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 10 -
drivers/gpu/drm/i915/intel_color.c | 60 +---
drivers/gpu/drm/i915/intel_display.c | 14 ++-
3 files changed, 66 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 44958d994bfa..9d17ba199be4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5578,9 +5578,15 @@ enum {
#define PIPECONF_SINGLE_WIDE 0
#define PIPECONF_PIPE_UNLOCKED 0
#define PIPECONF_PIPE_LOCKED (1 << 25)
-#define PIPECONF_PALETTE 0
-#define PIPECONF_GAMMA (1 << 24)
#define PIPECONF_FORCE_BORDER(1 << 25)
+#define PIPECONF_GAMMA_MODE_MASK_I9XX(1 << 24) /* gmch */
+#define PIPECONF_GAMMA_MODE_MASK_ILK (3 << 24) /* ilk-ivb */
+#define PIPECONF_GAMMA_MODE_8BIT (0 << 24) /* gmch,ilk-ivb */
+#define PIPECONF_GAMMA_MODE_10BIT(1 << 24) /* gmch,ilk-ivb */
+#define PIPECONF_GAMMA_MODE_12BIT(2 << 24) /* ilk-ivb */
+#define PIPECONF_GAMMA_MODE_SPLIT(3 << 24) /* ivb */
+#define PIPECONF_GAMMA_MODE(x) ((x)<<24) /* pass in GAMMA_MODE_MODE_*
*/
+#define PIPECONF_GAMMA_MODE_SHIFT24
#define PIPECONF_INTERLACE_MASK (7 << 21)
#define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
/* Note that pre-gen3 does not support interlaced display directly. Panel
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 0c0da7ed0fd7..6fdbfa8c4008 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -351,6 +351,32 @@ static void i9xx_load_luts(const struct intel_crtc_state
*crtc_state)
i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
}
+static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 val;
+
+ val = I915_READ(PIPECONF(pipe));
+ val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX;
+ val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
+ I915_WRITE(PIPECONF(pipe), val);
+}
+
+static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 val;
+
+ val = I915_READ(PIPECONF(pipe));
+ val &= ~PIPECONF_GAMMA_MODE_MASK_ILK;
+ val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
+ I915_WRITE(PIPECONF(pipe), val);
+}
+
static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -585,8 +611,7 @@ void intel_color_commit(const struct intel_crtc_state
*crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
- if (dev_priv->display.color_commit)
- dev_priv->display.color_commit(crtc_state);
+ dev_priv->display.color_commit(crtc_state);
}
int intel_color_check(struct intel_crtc_state *crtc_state)
@@ -634,20 +659,25 @@ void intel_color_init(struct intel_crtc *crtc)
drm_mode_crtc_set_gamma_size(>base, 256);
- if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->display.load_luts = cherryview_load_luts;
- } else if (IS_HASWELL(dev_priv)) {
- dev_priv->display.load_luts = i9xx_load_luts;
- dev_priv->display.color_commit = hsw_color_commit;
- } else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
- IS_BROXTON(dev_priv)) {
- dev_priv->display.load_luts = broadwell_load_luts;
- dev_priv->display.color_commit = hsw_color_commit;
- } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
- dev_priv->display.load_luts = glk_load_luts;
- dev_priv->display.color_commit = hsw_color_commit;
+ if (HAS_GMCH_DISPLAY(dev_priv)) {
+ if (IS_CHERRYVIEW(dev_priv))
+ dev_priv->display.load_luts = cherryview_load_luts;
+ else
+ dev_priv->display.load_luts = i9xx_load_luts;
+
+ dev_priv->display.color_commit = i9xx_color_commit;
} else {
- dev_priv->display.load_luts = i9xx_load_luts;
+ if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ dev_priv->display.load_luts = glk_load_luts;
+ else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
+
[Intel-gfx] [PATCH 13/13] drm/i915: Disable pipe gamma when C8 pixel format is used
From: Ville Syrjälä
Planes scanning out C8 will want to use the legacy lut as
their palette. That means the LUT content are unikely to
be useful for gamma correction on other planes. Thus we
should disable pipe gamma for all the other planes. And
we should reject any non legacy LUT configurations when
C8 planes are present.
Fixes the appearance of the hw cursor when running
X -depth 8.
Note that CHV with it's independent CGM degamma/gamma LUTs
could probably use the CGM for gamma correction even when
the legacy LUT is used for C8. But that would require a
new uapi for configuring the legacy LUT and CGM LUTs at
the same time. Totally not worth it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 5 +
drivers/gpu/drm/i915/intel_color.c| 8 +++-
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 50be2c5dd76e..f311763867c4 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -119,6 +119,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
new_crtc_state->active_planes &= ~BIT(plane->id);
new_crtc_state->nv12_planes &= ~BIT(plane->id);
+ new_crtc_state->c8_planes &= ~BIT(plane->id);
new_plane_state->base.visible = false;
if (!new_plane_state->base.crtc && !old_plane_state->base.crtc)
@@ -136,6 +137,10 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
new_plane_state->base.fb->format->format == DRM_FORMAT_NV12)
new_crtc_state->nv12_planes |= BIT(plane->id);
+ if (new_plane_state->base.visible &&
+ new_plane_state->base.fb->format->format == DRM_FORMAT_C8)
+ new_crtc_state->c8_planes |= BIT(plane->id);
+
if (new_plane_state->base.visible || old_plane_state->base.visible)
new_crtc_state->update_planes |= BIT(plane->id);
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 789b04bb51d2..c8d12653d77f 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -691,7 +691,13 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
- crtc_state->gamma_enable = gamma_lut || degamma_lut;
+ /* C8 needs the legacy LUT all to itself */
+ if (crtc_state->c8_planes &&
+ !crtc_state_is_legacy_gamma(crtc_state))
+ return -EINVAL;
+
+ crtc_state->gamma_enable = (gamma_lut || degamma_lut) &&
+ !crtc_state->c8_planes;
if (INTEL_GEN(dev_priv) >= 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a4496f799af3..4d9ea05a6825 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -930,6 +930,7 @@ struct intel_crtc_state {
/* bitmask of visible planes (enum plane_id) */
u8 active_planes;
u8 nv12_planes;
+ u8 c8_planes;
/* bitmask of planes that will be updated during the commit */
u8 update_planes;
--
2.19.2
___
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[Intel-gfx] [PATCH 11/13] drm/i915: Turn off pipe gamma when it's not needed.
From: Ville Syrjälä
The pipe internal precision is higher than what we currently program to
the degamma/gamma LUTs. We can get a higher quality image by bypassing
the LUTs when they're not needed. Let's do that.
Each plane has its own control bit for this, so we have to update
all active planes. The way we've done this we don't actually have
to run through the whole .check_plane() thing. And we actually
do the .color_check() after .check_plane() so we couldn't even do
that without shuffling the code around.
Additionally on pre-skl we have to update the primary plane regardless
of whether it's active or not on account of the primayr plane gamma
enable bit also affecting the pipe bottom color.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_color.c | 55 --
1 file changed, 53 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 8d7ea902a34b..a8b7428a64bf 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -633,27 +633,78 @@ void intel_color_commit(const struct intel_crtc_state
*crtc_state)
dev_priv->display.color_commit(crtc_state);
}
+static bool need_plane_update(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+
+ /*
+* On pre-SKL the pipe gamma enable and pipe csc enable for
+* the pipe bottom color are configured via the primary plane.
+* We have to reconfigure that even if the plane is inactive.
+*/
+ return crtc_state->active_planes & BIT(plane->id) ||
+ (INTEL_GEN(dev_priv) < 9 &&
+plane->id == PLANE_PRIMARY);
+}
+
+static int
+intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_atomic_state *state =
+ to_intel_atomic_state(new_crtc_state->base.state);
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+ struct intel_plane *plane;
+
+ if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable)
+ return 0;
+
+ for_each_intel_plane_on_crtc(_priv->drm, crtc, plane) {
+ struct intel_plane_state *plane_state;
+
+ if (!need_plane_update(plane, new_crtc_state))
+ continue;
+
+ plane_state = intel_atomic_get_plane_state(state, plane);
+ if (IS_ERR(plane_state))
+ return PTR_ERR(plane_state);
+
+ new_crtc_state->update_planes |= BIT(plane->id);
+ }
+
+ return 0;
+}
+
int intel_color_check(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
const struct drm_property_blob *degamma_lut =
crtc_state->base.degamma_lut;
size_t gamma_length, degamma_length;
+ int ret;
degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
- crtc_state->gamma_enable = true;
+ crtc_state->gamma_enable = gamma_lut || degamma_lut;
if (INTEL_GEN(dev_priv) >= 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
crtc_state->csc_enable = true;
+ ret = intel_color_add_affected_planes(crtc_state);
+ if (ret)
+ return ret;
+
/*
* We also allow no degamma lut/ctm and a gamma lut at the legacy
* size (256 entries).
*/
- if (crtc_state_is_legacy_gamma(crtc_state)) {
+ if (!crtc_state->gamma_enable ||
+ crtc_state_is_legacy_gamma(crtc_state)) {
crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
return 0;
}
--
2.19.2
___
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[Intel-gfx] [PATCH 03/13] drm/i915: Precompute gamma_mode
From: Ville Syrjälä
We shouldn't be computing gamma mode during the commit phase.
Move it to the check phase.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_color.c | 44 +-
1 file changed, 25 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 37fd9ddf762e..b10e66ce3970 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -375,8 +375,7 @@ static void haswell_load_luts(struct intel_crtc_state
*crtc_state)
reenable_ips = true;
}
- crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
- I915_WRITE(GAMMA_MODE(crtc->pipe), GAMMA_MODE_MODE_8BIT);
+ I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
i9xx_load_luts(crtc_state);
@@ -476,9 +475,7 @@ static void broadwell_load_luts(struct intel_crtc_state
*crtc_state)
bdw_load_gamma_lut(crtc_state,
INTEL_INFO(dev_priv)->color.degamma_lut_size);
- crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
- I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);
- POSTING_READ(GAMMA_MODE(pipe));
+ I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
/*
* Reset the index, otherwise it prevents the legacy palette to be
@@ -532,9 +529,7 @@ static void glk_load_luts(struct intel_crtc_state
*crtc_state)
bdw_load_gamma_lut(crtc_state, 0);
- crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
- I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT);
- POSTING_READ(GAMMA_MODE(pipe));
+ I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
}
/* Loads the palette/gamma unit for the CRTC on CherryView. */
@@ -608,29 +603,40 @@ void intel_color_load_luts(struct intel_crtc_state
*crtc_state)
int intel_color_check(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
+ const struct drm_property_blob *degamma_lut =
crtc_state->base.degamma_lut;
size_t gamma_length, degamma_length;
degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
/*
-* We allow both degamma & gamma luts at the right size or
-* NULL.
+* We also allow no degamma lut/ctm and a gamma lut at the legacy
+* size (256 entries).
*/
- if ((!crtc_state->base.degamma_lut ||
-drm_color_lut_size(crtc_state->base.degamma_lut) ==
degamma_length) &&
- (!crtc_state->base.gamma_lut ||
-drm_color_lut_size(crtc_state->base.gamma_lut) == gamma_length))
+ if (crtc_state_is_legacy_gamma(crtc_state)) {
+ crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
return 0;
+ }
/*
-* We also allow no degamma lut/ctm and a gamma lut at the legacy
-* size (256 entries).
+* We allow both degamma & gamma luts at the right size or
+* NULL.
*/
- if (crtc_state_is_legacy_gamma(crtc_state))
- return 0;
+ if (degamma_lut && drm_color_lut_size(degamma_lut) != degamma_length)
+ return -EINVAL;
+
+ if (gamma_lut && drm_color_lut_size(gamma_lut) != gamma_length)
+ return -EINVAL;
+
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
+ else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
+ crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
+ else
+ crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
- return -EINVAL;
+ return 0;
}
void intel_color_init(struct intel_crtc *crtc)
--
2.19.2
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[Intel-gfx] [PATCH 09/13] drm/i915: Track pipe gamma enable/disable in crtc state
From: Ville Syrjälä
Track whether pipe gamma is enabled or disabled. For now we
stick to the current behaviour of always enabling gamma. But
we do get working state readout for this now. On SKL+ we use
the pipe bottom color as our hardware state. On pre-SKL we
read the state back from the primary plane control register.
That only really correct for g4x+, as older platforms never
gamma correct pipe bottom color. But doing the readout the
same way on all platforms is fine, and there is no other way
to do it really.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 8
drivers/gpu/drm/i915/intel_color.c | 24 +++-
drivers/gpu/drm/i915/intel_display.c | 56 ++--
drivers/gpu/drm/i915/intel_drv.h | 3 ++
drivers/gpu/drm/i915/intel_sprite.c | 17 +++--
5 files changed, 92 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9d17ba199be4..7f0913bc1b47 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5707,6 +5707,14 @@ enum {
#define PIPEMISC_DITHER_TYPE_SP (0 << 2)
#define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
+/* SKL+ pipe bottom color */
+#define _PIPE_BOTTOM_COLOR_A 0x70034
+#define _PIPE_BOTTOM_COLOR_B 0x71034
+#define PIPE_BOTTOM_GAMMA_ENABLE (1 << 31)
+#define PIPE_BOTTOM_CSC_ENABLE (1 << 30)
+#define PIPE_BOTTOM_COLOR_MASK 0x3FFF
+#define PIPE_BOTTOM_COLOR(pipe)_MMIO_PIPE2(pipe,
_PIPE_BOTTOM_COLOR_A)
+
#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE +
0x70028)
#define PIPEB_LINE_COMPARE_INT_EN(1 << 29)
#define PIPEB_HLINE_INT_EN (1 << 28)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 6fdbfa8c4008..313b281204fa 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -387,6 +387,24 @@ static void hsw_color_commit(const struct intel_crtc_state
*crtc_state)
ilk_load_csc_matrix(crtc_state);
}
+static void skl_color_commit(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 val;
+
+ val = 0;
+ if (crtc_state->gamma_enable)
+ val |= PIPE_BOTTOM_GAMMA_ENABLE;
+ val |= PIPE_BOTTOM_CSC_ENABLE;
+ I915_WRITE(PIPE_BOTTOM_COLOR(pipe), val);
+
+ I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
+
+ ilk_load_csc_matrix(crtc_state);
+}
+
static void bdw_load_degamma_lut(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -624,6 +642,8 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ crtc_state->gamma_enable = true;
+
/*
* We also allow no degamma lut/ctm and a gamma lut at the legacy
* size (256 entries).
@@ -674,7 +694,9 @@ void intel_color_init(struct intel_crtc *crtc)
else
dev_priv->display.load_luts = i9xx_load_luts;
- if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 9)
+ dev_priv->display.color_commit = skl_color_commit;
+ else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
dev_priv->display.color_commit = hsw_color_commit;
else
dev_priv->display.color_commit = ilk_color_commit;
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 90afcae91b30..896ce95790cb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3186,7 +3186,8 @@ static u32 i9xx_plane_ctl_crtc(const struct
intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 dspcntr = 0;
- dspcntr |= DISPPLANE_GAMMA_ENABLE;
+ if (crtc_state->gamma_enable)
+ dspcntr |= DISPPLANE_GAMMA_ENABLE;
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
@@ -3664,7 +3665,9 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state
*crtc_state)
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
return plane_ctl;
- plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
+ if (crtc_state->gamma_enable)
+ plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
+
plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
return plane_ctl;
@@ -3717,7 +3720,9 @@ u32 glk_plane_color_ctl_crtc(const struct
[Intel-gfx] [PATCH 02/13] drm/i915: Split the gamma/csc enable bits from the plane_ctl() function
From: Ville Syrjälä
On g4x+ the pipe gamma enable bit for the primary plane affects
the pipe bottom color as well. The same for the pipe csc enable
bit on ilk+. Thus we must configure those bits correctly even
when the primary plane is disabled.
To make the feasible let's split those settings from the
plane_ctl() function into a seprate funciton that we can
call from the ->disable_plane() hook as well.
For consistency we'll do that on all the plane types. While
that has no real benefits at this time, it'll become useful
when we start to control the pipe gamma/csc enable bits
dynamically when we overhaul the color management code.
On pre-g4x there doesn't appear to be any way to gamma
correct the pipe bottom color, but sticking to the same
pattern doesn't hurt. And it'll still help us to do
crtc state readout correctly for the pipe gamma enable
bit for the color management overhaul.
An alternative apporach would be to still precompute these
bits into plane_state->ctl, but that would require that we
run through the plane check even when the plane isn't logically
enabled on any crtc. Currently that condition causes us to
short circuit the entire thing and not call ->check_plane().
There would also be some chicken and egg problems with
->check_plane() vs. crtc color state check that would
requite splitting certain things into multiple steps.
So all in all this seems like the easier route.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 128 ---
drivers/gpu/drm/i915/intel_drv.h | 3 +-
drivers/gpu/drm/i915/intel_sprite.c | 54 ---
3 files changed, 139 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5dc0de89c49e..a3871db4703b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3180,28 +3180,38 @@ i9xx_plane_max_stride(struct intel_plane *plane,
}
}
+static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 dspcntr = 0;
+
+ dspcntr |= DISPPLANE_GAMMA_ENABLE;
+
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+ dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
+
+ if (INTEL_GEN(dev_priv) < 5)
+ dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
+
+ return dspcntr;
+}
+
static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv =
to_i915(plane_state->base.plane->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
const struct drm_framebuffer *fb = plane_state->base.fb;
unsigned int rotation = plane_state->base.rotation;
u32 dspcntr;
- dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
+ dspcntr = DISPLAY_PLANE_ENABLE;
if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
- if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
- dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
-
- if (INTEL_GEN(dev_priv) < 5)
- dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
-
switch (fb->format->format) {
case DRM_FORMAT_C8:
dspcntr |= DISPPLANE_8BPP;
@@ -3329,11 +3339,13 @@ static void i9xx_update_plane(struct intel_plane *plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
u32 linear_offset;
- u32 dspcntr = plane_state->ctl;
int x = plane_state->color_plane[0].x;
int y = plane_state->color_plane[0].y;
unsigned long irqflags;
u32 dspaddr_offset;
+ u32 dspcntr;
+
+ dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
@@ -3393,10 +3405,23 @@ static void i9xx_disable_plane(struct intel_plane
*plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
unsigned long irqflags;
+ u32 dspcntr;
+
+ /*
+* DSPCNTR pipe gamma enable on g4x+ and pipe csc
+* enable on ilk+ affect the pipe bottom color as
+* well, so we must configure them even if the plane
+* is disabled.
+*
+* On pre-g4x there is no way to gamma correct the
+* pipe bottom color but we'll keep on doing this
+* anyway.
+*/
+ dspcntr = i9xx_plane_ctl_crtc(crtc_state);
spin_lock_irqsave(_priv->uncore.lock, irqflags);
- I915_WRITE_FW(DSPCNTR(i9xx_plane), 0);
+
[Intel-gfx] [PATCH 10/13] drm/i915: Track pipe csc enable in crtc state
From: Ville Syrjälä
Just like we did for pipe gamma, let's also track the pipe csc
state. The hardware only exists on ILK+, and currently we always
enable it on hsw+ and never on any other platforms. Just like
with pipe gamma, the primary plane control register is used
for the readout on pre-SKL, and the pipe bottom color register
on SKL+.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
drivers/gpu/drm/i915/intel_color.c | 7 ++-
drivers/gpu/drm/i915/intel_display.c | 18 ++
drivers/gpu/drm/i915/intel_drv.h | 3 +++
drivers/gpu/drm/i915/intel_sprite.c | 6 --
5 files changed, 29 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7f0913bc1b47..8848721dd691 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6120,7 +6120,7 @@ enum {
#define MCURSOR_PIPE_SELECT_SHIFT28
#define MCURSOR_PIPE_SELECT(pipe)((pipe) << 28)
#define MCURSOR_GAMMA_ENABLE (1 << 26)
-#define MCURSOR_PIPE_CSC_ENABLE (1 << 24)
+#define MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
#define MCURSOR_ROTATE_180 (1 << 15)
#define MCURSOR_TRICKLE_FEED_DISABLE (1 << 14)
#define _CURABASE 0x70084
@@ -6175,7 +6175,7 @@ enum {
#define DISPPLANE_RGBA888(0xf << 26)
#define DISPPLANE_STEREO_ENABLE (1 << 25)
#define DISPPLANE_STEREO_DISABLE 0
-#define DISPPLANE_PIPE_CSC_ENABLE(1 << 24)
+#define DISPPLANE_PIPE_CSC_ENABLE(1 << 24) /* ilk+ */
#define DISPPLANE_SEL_PIPE_SHIFT 24
#define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT)
#define DISPPLANE_SEL_PIPE(pipe) ((pipe) <<
DISPPLANE_SEL_PIPE_SHIFT)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 313b281204fa..8d7ea902a34b 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -397,7 +397,8 @@ static void skl_color_commit(const struct intel_crtc_state
*crtc_state)
val = 0;
if (crtc_state->gamma_enable)
val |= PIPE_BOTTOM_GAMMA_ENABLE;
- val |= PIPE_BOTTOM_CSC_ENABLE;
+ if (crtc_state->csc_enable)
+ val |= PIPE_BOTTOM_CSC_ENABLE;
I915_WRITE(PIPE_BOTTOM_COLOR(pipe), val);
I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
@@ -644,6 +645,10 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
crtc_state->gamma_enable = true;
+ if (INTEL_GEN(dev_priv) >= 9 ||
+ IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
+ crtc_state->csc_enable = true;
+
/*
* We also allow no degamma lut/ctm and a gamma lut at the legacy
* size (256 entries).
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 896ce95790cb..2e66b398167e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3189,7 +3189,7 @@ static u32 i9xx_plane_ctl_crtc(const struct
intel_crtc_state *crtc_state)
if (crtc_state->gamma_enable)
dspcntr |= DISPPLANE_GAMMA_ENABLE;
- if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+ if (crtc_state->csc_enable)
dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
if (INTEL_GEN(dev_priv) < 5)
@@ -3668,7 +3668,8 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state
*crtc_state)
if (crtc_state->gamma_enable)
plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
- plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
+ if (crtc_state->csc_enable)
+ plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
return plane_ctl;
}
@@ -3723,7 +3724,8 @@ u32 glk_plane_color_ctl_crtc(const struct
intel_crtc_state *crtc_state)
if (crtc_state->gamma_enable)
plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
- plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
+ if (crtc_state->csc_enable)
+ plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
return plane_color_ctl;
}
@@ -8052,6 +8054,10 @@ static void i9xx_get_pipe_color_config(struct
intel_crtc_state *crtc_state)
if (tmp & DISPPLANE_GAMMA_ENABLE)
crtc_state->gamma_enable = true;
+
+ if (!HAS_GMCH_DISPLAY(dev_priv) &&
+ tmp & DISPPLANE_PIPE_CSC_ENABLE)
+ crtc_state->csc_enable = true;
}
static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
@@ -9812,6 +9818,9 @@ static bool haswell_get_pipe_config(struct intel_crtc
*crtc,
if (tmp & PIPE_BOTTOM_GAMMA_ENABLE)
pipe_config->gamma_enable = true;
+
+ if (tmp & PIPE_BOTTOM_CSC_ENABLE)
+ pipe_config->csc_enable = true;
} else {
i9xx_get_pipe_color_config(pipe_config);
}
@@
[Intel-gfx] [PATCH 06/13] drm/i915: Split color mgmt based on single vs. double buffered registers
From: Ville Syrjälä
Split the color managemnt hooks along the single vs. double
buffered registers line. Of the currently progammed registers
GAMMA_MODE and the ilk+ pipe CSC are double buffered, the
LUTS and CHV CGM block are single buffered.
The double buffered register will be programmed during the
normal pipe update with evasion, and also during pipe enable
so that the settings will already be correct when the pipe
starts up before the planes are enabled.
The single buffered registers are currently programmed before
the vblank evade. Which is totally wrong, but we'll correct
that later.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_color.c | 49 +---
drivers/gpu/drm/i915/intel_display.c | 16 +
drivers/gpu/drm/i915/intel_drv.h | 2 +-
4 files changed, 34 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7182a580002c..354858b2019b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -320,7 +320,7 @@ struct drm_i915_display_funcs {
/* display clock increase/decrease */
/* pll clock increase/decrease */
- void (*load_csc_matrix)(const struct intel_crtc_state *crtc_state);
+ void (*color_commit)(const struct intel_crtc_state *crtc_state);
void (*load_luts)(const struct intel_crtc_state *crtc_state);
};
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index df3567686c45..f9e0855162f3 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -304,14 +304,6 @@ static void cherryview_load_csc_matrix(const struct
intel_crtc_state *crtc_state
I915_WRITE(CGM_PIPE_MODE(pipe), mode);
}
-void intel_color_set_csc(const struct intel_crtc_state *crtc_state)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
-
- if (dev_priv->display.load_csc_matrix)
- dev_priv->display.load_csc_matrix(crtc_state);
-}
-
/* Loads the legacy palette/gamma unit for the CRTC. */
static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
const struct drm_property_blob *blob)
@@ -359,6 +351,16 @@ static void i9xx_load_luts(const struct intel_crtc_state
*crtc_state)
i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
}
+static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+ I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
+
+ ilk_load_csc_matrix(crtc_state);
+}
+
/* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
static void haswell_load_luts(const struct intel_crtc_state *crtc_state)
{
@@ -376,8 +378,6 @@ static void haswell_load_luts(const struct intel_crtc_state
*crtc_state)
reenable_ips = true;
}
- I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
-
i9xx_load_luts(crtc_state);
if (reenable_ips)
@@ -485,8 +485,6 @@ static void broadwell_load_luts(const struct
intel_crtc_state *crtc_state)
*/
I915_WRITE(PREC_PAL_INDEX(pipe), 0);
}
-
- I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
}
static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
@@ -539,8 +537,6 @@ static void glk_load_luts(const struct intel_crtc_state
*crtc_state)
*/
I915_WRITE(PREC_PAL_INDEX(pipe), 0);
}
-
- I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
}
static void cherryview_load_luts(const struct intel_crtc_state *crtc_state)
@@ -551,10 +547,9 @@ static void cherryview_load_luts(const struct
intel_crtc_state *crtc_state)
const struct drm_property_blob *degamma_lut =
crtc_state->base.degamma_lut;
enum pipe pipe = crtc->pipe;
+ cherryview_load_csc_matrix(crtc_state);
+
if (crtc_state_is_legacy_gamma(crtc_state)) {
- /* Turn off degamma/gamma on CGM block. */
- I915_WRITE(CGM_PIPE_MODE(pipe),
- (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0));
i9xx_load_luts_internal(crtc_state, gamma_lut);
return;
}
@@ -595,11 +590,6 @@ static void cherryview_load_luts(const struct
intel_crtc_state *crtc_state)
}
}
- I915_WRITE(CGM_PIPE_MODE(pipe),
- (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0) |
- (degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
- (gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
-
/*
* Also program a linear LUT in the legacy block (behind the
* CGM block).
@@ -614,6 +604,14 @@ void
[Intel-gfx] [PATCH 00/13] Enable/disable gamma/csc dynamically and fix C8
From: Ville Syrjälä I figured I'd post this before we get too deep in the rabbit hole with the icl stuff. This is just the first part of my color mgmt stuff I've had cooking for far too long. The rest has to do with expanding the support for higher precision gamma modes and the pipe csc to all possible platforms, but that part is not ready yet. Entire series available here: git://github.com/vsyrjala/linux.git gamma_mode_10_base Ville Syrjälä (13): drm/i915: Clean up intel_plane_atomic_check_with_state() drm/i915: Split the gamma/csc enable bits from the plane_ctl() function drm/i915: Precompute gamma_mode drm/i915: Constify the state arguments to the color management stuff drm/i915: Pull GAMMA_MODE write out from haswell_load_luts() drm/i915: Split color mgmt based on single vs. double buffered registers drm/i915: Move LUT programming to happen after vblank waits drm/i915: Populate gamma_mode for all platforms drm/i915: Track pipe gamma enable/disable in crtc state drm/i915: Track pipe csc enable in crtc state drm/i915: Turn off pipe gamma when it's not needed. drm/i915: Turn off pipe CSC when it's not needed drm/i915: Disable pipe gamma when C8 pixel format is used drivers/gpu/drm/i915/i915_drv.h | 4 +- drivers/gpu/drm/i915/i915_reg.h | 22 +- drivers/gpu/drm/i915/intel_atomic_plane.c | 41 +-- drivers/gpu/drm/i915/intel_color.c| 386 ++ drivers/gpu/drm/i915/intel_display.c | 257 +++--- drivers/gpu/drm/i915/intel_drv.h | 14 +- drivers/gpu/drm/i915/intel_sprite.c | 67 +++- 7 files changed, 563 insertions(+), 228 deletions(-) -- 2.19.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/13] drm/i915: Clean up intel_plane_atomic_check_with_state()
From: Ville Syrjälä
Rename some of the state variables in
intel_plane_atomic_check_with_state() to make it less confusing.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 36 +++
1 file changed, 17 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 683a75dad4fb..50be2c5dd76e 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -110,41 +110,39 @@ intel_plane_destroy_state(struct drm_plane *plane,
}
int intel_plane_atomic_check_with_state(const struct intel_crtc_state
*old_crtc_state,
- struct intel_crtc_state *crtc_state,
+ struct intel_crtc_state *new_crtc_state,
const struct intel_plane_state
*old_plane_state,
- struct intel_plane_state *intel_state)
+ struct intel_plane_state
*new_plane_state)
{
- struct drm_plane *plane = intel_state->base.plane;
- struct drm_plane_state *state = _state->base;
- struct intel_plane *intel_plane = to_intel_plane(plane);
+ struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
int ret;
- crtc_state->active_planes &= ~BIT(intel_plane->id);
- crtc_state->nv12_planes &= ~BIT(intel_plane->id);
- intel_state->base.visible = false;
+ new_crtc_state->active_planes &= ~BIT(plane->id);
+ new_crtc_state->nv12_planes &= ~BIT(plane->id);
+ new_plane_state->base.visible = false;
- /* If this is a cursor plane, no further checks are needed. */
- if (!intel_state->base.crtc && !old_plane_state->base.crtc)
+ if (!new_plane_state->base.crtc && !old_plane_state->base.crtc)
return 0;
- ret = intel_plane->check_plane(crtc_state, intel_state);
+ ret = plane->check_plane(new_crtc_state, new_plane_state);
if (ret)
return ret;
/* FIXME pre-g4x don't work like this */
- if (state->visible)
- crtc_state->active_planes |= BIT(intel_plane->id);
+ if (new_plane_state->base.visible)
+ new_crtc_state->active_planes |= BIT(plane->id);
- if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
- crtc_state->nv12_planes |= BIT(intel_plane->id);
+ if (new_plane_state->base.visible &&
+ new_plane_state->base.fb->format->format == DRM_FORMAT_NV12)
+ new_crtc_state->nv12_planes |= BIT(plane->id);
- if (state->visible || old_plane_state->base.visible)
- crtc_state->update_planes |= BIT(intel_plane->id);
+ if (new_plane_state->base.visible || old_plane_state->base.visible)
+ new_crtc_state->update_planes |= BIT(plane->id);
return intel_plane_atomic_calc_changes(old_crtc_state,
- _state->base,
+ _crtc_state->base,
old_plane_state,
- state);
+ _plane_state->base);
}
static int intel_plane_atomic_check(struct drm_plane *plane,
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/13] drm/i915: Constify the state arguments to the color management stuff
From: Ville Syrjälä
Pass the crtc state etc. as const to the color management commit
functions. And while at it polish some of the local variables.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h| 4 +-
drivers/gpu/drm/i915/intel_color.c | 128 -
drivers/gpu/drm/i915/intel_drv.h | 4 +-
3 files changed, 73 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5df26ccda8a4..7182a580002c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -320,8 +320,8 @@ struct drm_i915_display_funcs {
/* display clock increase/decrease */
/* pll clock increase/decrease */
- void (*load_csc_matrix)(struct intel_crtc_state *crtc_state);
- void (*load_luts)(struct intel_crtc_state *crtc_state);
+ void (*load_csc_matrix)(const struct intel_crtc_state *crtc_state);
+ void (*load_luts)(const struct intel_crtc_state *crtc_state);
};
#define CSR_VERSION(major, minor) ((major) << 16 | (minor))
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index b10e66ce3970..0dfd104b89d7 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -74,12 +74,12 @@
#define ILK_CSC_COEFF_1_0 \
((7 << 12) | ILK_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
-static bool lut_is_legacy(struct drm_property_blob *lut)
+static bool lut_is_legacy(const struct drm_property_blob *lut)
{
return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH;
}
-static bool crtc_state_is_legacy_gamma(struct intel_crtc_state *crtc_state)
+static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state
*crtc_state)
{
return !crtc_state->base.degamma_lut &&
!crtc_state->base.ctm &&
@@ -115,8 +115,8 @@ static u64 *ctm_mult_by_limited(u64 *result, const u64
*input)
static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
{
- int pipe = crtc->pipe;
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
@@ -137,13 +137,14 @@ static void ilk_load_ycbcr_conversion_matrix(struct
intel_crtc *crtc)
I915_WRITE(PIPE_CSC_MODE(pipe), 0);
}
-static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state)
+static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- int i, pipe = crtc->pipe;
- uint16_t coeffs[9] = { 0, };
bool limited_color_range = false;
+ enum pipe pipe = crtc->pipe;
+ u16 coeffs[9] = {};
+ int i;
/*
* FIXME if there's a gamma LUT after the CSC, we should
@@ -256,15 +257,15 @@ static void ilk_load_csc_matrix(struct intel_crtc_state
*crtc_state)
/*
* Set up the pipe CSC unit on CherryView.
*/
-static void cherryview_load_csc_matrix(struct intel_crtc_state *crtc_state)
+static void cherryview_load_csc_matrix(const struct intel_crtc_state
*crtc_state)
{
- struct drm_device *dev = crtc_state->base.crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- int pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
uint32_t mode;
if (crtc_state->base.ctm) {
- struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
+ const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
uint16_t coeffs[9] = { 0, };
int i;
@@ -303,18 +304,17 @@ static void cherryview_load_csc_matrix(struct
intel_crtc_state *crtc_state)
I915_WRITE(CGM_PIPE_MODE(pipe), mode);
}
-void intel_color_set_csc(struct intel_crtc_state *crtc_state)
+void intel_color_set_csc(const struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = crtc_state->base.crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
if (dev_priv->display.load_csc_matrix)
dev_priv->display.load_csc_matrix(crtc_state);
}
/* Loads the legacy palette/gamma unit for the CRTC. */
-static void i9xx_load_luts_internal(struct intel_crtc_state *crtc_state,
- struct drm_property_blob *blob)
+static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
+ const struct drm_property_blob *blob)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv =
[Intel-gfx] [PATCH 07/13] drm/i915: Move LUT programming to happen after vblank waits
From: Ville Syrjälä
The LUTs are single buffered so we should program them after
the double buffered pipe updates have been latched by the
hardware.
We'll also fix up the IPS vs. split gamma w/a to do the IPS
disable like everyone else. Note that this is currently dead
code as we don't use the split gamma mode on HSW, but that
will be fixed up shortly.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_color.c | 25 +--
drivers/gpu/drm/i915/intel_display.c | 47
2 files changed, 42 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index f9e0855162f3..0c0da7ed0fd7 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -361,29 +361,6 @@ static void hsw_color_commit(const struct intel_crtc_state
*crtc_state)
ilk_load_csc_matrix(crtc_state);
}
-/* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
-static void haswell_load_luts(const struct intel_crtc_state *crtc_state)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- bool reenable_ips = false;
-
- /*
-* Workaround : Do not read or write the pipe palette/gamma data while
-* GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
-*/
- if (IS_HASWELL(dev_priv) && crtc_state->ips_enabled &&
- (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
- hsw_disable_ips(crtc_state);
- reenable_ips = true;
- }
-
- i9xx_load_luts(crtc_state);
-
- if (reenable_ips)
- hsw_enable_ips(crtc_state);
-}
-
static void bdw_load_degamma_lut(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -660,7 +637,7 @@ void intel_color_init(struct intel_crtc *crtc)
if (IS_CHERRYVIEW(dev_priv)) {
dev_priv->display.load_luts = cherryview_load_luts;
} else if (IS_HASWELL(dev_priv)) {
- dev_priv->display.load_luts = haswell_load_luts;
+ dev_priv->display.load_luts = i9xx_load_luts;
dev_priv->display.color_commit = hsw_color_commit;
} else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
IS_BROXTON(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 96c78566b8e6..1caee4128974 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5299,24 +5299,54 @@ intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc)
static bool hsw_pre_update_disable_ips(const struct intel_crtc_state
*old_crtc_state,
const struct intel_crtc_state
*new_crtc_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
if (!old_crtc_state->ips_enabled)
return false;
if (needs_modeset(_crtc_state->base))
return true;
+ /*
+* Workaround : Do not read or write the pipe palette/gamma data while
+* GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
+*
+* Disable IPS before we program the LUT.
+*/
+ if (IS_HASWELL(dev_priv) &&
+ (new_crtc_state->base.color_mgmt_changed ||
+new_crtc_state->update_pipe) &&
+ new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
+ return true;
+
return !new_crtc_state->ips_enabled;
}
static bool hsw_post_update_enable_ips(const struct intel_crtc_state
*old_crtc_state,
const struct intel_crtc_state
*new_crtc_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
if (!new_crtc_state->ips_enabled)
return false;
if (needs_modeset(_crtc_state->base))
return true;
+ /*
+* Workaround : Do not read or write the pipe palette/gamma data while
+* GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
+*
+* Re-enable IPS after the LUT has been programmed.
+*/
+ if (IS_HASWELL(dev_priv) &&
+ (new_crtc_state->base.color_mgmt_changed ||
+new_crtc_state->update_pipe) &&
+ new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
+ return true;
+
/*
* We can't read out IPS on broadwell, assume the worst and
* forcibly enable IPS on the first fastset.
@@ -11050,7 +11080,7 @@ static int intel_crtc_atomic_check(struct drm_crtc
*crtc,
return ret;
}
- if
[Intel-gfx] [PATCH 05/13] drm/i915: Pull GAMMA_MODE write out from haswell_load_luts()
From: Ville Syrjälä
For bdw+ let's move the GAMMA_MODE write for the legacy LUT
mode into the .load_luts() funciton directly, rather than
relying on haswell_load_luts(). We'll be getting rid of
haswell_load_luts() entirely soon, and it's anyway cleaner
to have the GAMMA_MODE write in a single place.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_color.c | 36 +-
1 file changed, 20 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 0dfd104b89d7..df3567686c45 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -473,21 +473,20 @@ static void broadwell_load_luts(const struct
intel_crtc_state *crtc_state)
enum pipe pipe = crtc->pipe;
if (crtc_state_is_legacy_gamma(crtc_state)) {
- haswell_load_luts(crtc_state);
- return;
- }
+ i9xx_load_luts(crtc_state);
+ } else {
+ bdw_load_degamma_lut(crtc_state);
+ bdw_load_gamma_lut(crtc_state,
+
INTEL_INFO(dev_priv)->color.degamma_lut_size);
- bdw_load_degamma_lut(crtc_state);
- bdw_load_gamma_lut(crtc_state,
- INTEL_INFO(dev_priv)->color.degamma_lut_size);
+ /*
+* Reset the index, otherwise it prevents the legacy palette to
be
+* written properly.
+*/
+ I915_WRITE(PREC_PAL_INDEX(pipe), 0);
+ }
I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
-
- /*
-* Reset the index, otherwise it prevents the legacy palette to be
-* written properly.
-*/
- I915_WRITE(PREC_PAL_INDEX(pipe), 0);
}
static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
@@ -530,11 +529,16 @@ static void glk_load_luts(const struct intel_crtc_state
*crtc_state)
glk_load_degamma_lut(crtc_state);
if (crtc_state_is_legacy_gamma(crtc_state)) {
- haswell_load_luts(crtc_state);
- return;
- }
+ i9xx_load_luts(crtc_state);
+ } else {
+ bdw_load_gamma_lut(crtc_state, 0);
- bdw_load_gamma_lut(crtc_state, 0);
+ /*
+* Reset the index, otherwise it prevents the legacy palette to
be
+* written properly.
+*/
+ I915_WRITE(PREC_PAL_INDEX(pipe), 0);
+ }
I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
}
--
2.19.2
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v5 1/6] drm/i915: Check for Null for color lut callbacks
>-Original Message- >From: Roper, Matthew D >Sent: Friday, January 11, 2019 3:57 AM >To: Shankar, Uma >Cc: intel-gfx@lists.freedesktop.org; Lankhorst, Maarten >; Syrjala, Ville ; >Sharma, >Shashank >Subject: Re: [v5 1/6] drm/i915: Check for Null for color lut callbacks > >On Tue, Jan 08, 2019 at 01:07:28PM +0530, Uma Shankar wrote: >> Check if de-gamma/gamma lut callback is assigned before calling the >> same. >> >> Signed-off-by: Uma Shankar > >Is it possible for this test to fail? intel_color_init() seems to always >assign a value >(even for platforms that don't actually support color management). > >It seem like if you're going to make this change, you'd also want to update >intel_color_init() to only set the load_luts for platforms where we actually >have >color management? Yeah, I was trying to add this check to avoid any processing if call-backs are not registered. Currently that is not the case so can be dropped and added later if such a case arise. Touching and disabling it for legacy platforms, requires to get details from GEN2 onwards and can break older platforms if not done right. Will drop this change. Regards, Uma Shankar > >Matt > >> --- >> drivers/gpu/drm/i915/intel_color.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_color.c >> b/drivers/gpu/drm/i915/intel_color.c >> index 37fd9dd..4ff4db6 100644 >> --- a/drivers/gpu/drm/i915/intel_color.c >> +++ b/drivers/gpu/drm/i915/intel_color.c >> @@ -602,7 +602,8 @@ void intel_color_load_luts(struct intel_crtc_state >*crtc_state) >> struct drm_device *dev = crtc_state->base.crtc->dev; >> struct drm_i915_private *dev_priv = to_i915(dev); >> >> -dev_priv->display.load_luts(crtc_state); >> +if (dev_priv->display.load_luts) >> +dev_priv->display.load_luts(crtc_state); >> } >> >> int intel_color_check(struct intel_crtc_state *crtc_state) >> -- >> 1.9.1 >> > >-- >Matt Roper >Graphics Software Engineer >IoTG Platform Enabling & Development >Intel Corporation >(916) 356-2795 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v5 2/6] drm/i915: Sanitize crtc gamma mode
>-Original Message-
>From: Roper, Matthew D
>Sent: Friday, January 11, 2019 4:08 AM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Lankhorst, Maarten
>; Syrjala, Ville ;
>Sharma,
>Shashank
>Subject: Re: [v5 2/6] drm/i915: Sanitize crtc gamma mode
>
>On Tue, Jan 08, 2019 at 01:07:29PM +0530, Uma Shankar wrote:
>> Sanitize crtc gamma mode and update the mode in driver in case BIOS
>> has setup a different gamma mode as to what is expected by driver.
>> There is restriction on HSW platform not to read/write color LUT's if
>> ips is enabled. Handled the same accordingly.
>>
>> Credits-to: Matt Roper
>> Signed-off-by: Uma Shankar
>> ---
>> drivers/gpu/drm/i915/intel_display.c | 17 +
>> 1 file changed, 17 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 696e6f5..03c8f68 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -15401,6 +15401,23 @@ static void intel_sanitize_crtc(struct intel_crtc
>*crtc,
>> }
>> }
>>
>> +/*
>> + * Sanitize gamma mode incase BIOS leaves it in SPLIT GAMMA MODE
>> + * Workaround HSW : Do not read or write the pipe palette/gamma data
>> + * while GAMMA_MODE is configured for split gamma and IPS_CTL has
>IPS
>> + * enabled.
>> + */
>
>The other thing that might be worth noting here is that we don't actually try
>to
>read out the LUT's and CTM that the BIOS setup, so at the moment they stick
>around for a while until the get unexpectedly
>clobbered by a subsequent modeset or fastset. The change here will
>basically force them to be reset to standard/linear values at startup.
>
>Maybe in the future we'll try to actually read out and preserve the contents
>of the
>actual LUT's and CTM that the BIOS had setup, but we don't do that yet today,
>so
>the change here at least makes the behavior a little bit more consistent than
>what
>it has been.
>
>Up to you whether you want to try to describe that in either the comment and/or
>commit message.
Sure Matt, I will update the commit message to reflect this as well.
>> +if (IS_HASWELL(dev_priv)) {
>> +if (crtc_state->ips_enabled)
>
>It looks like both hsw_disable_ips() and hsw_enable_ips() have this test
>inside of
>them already, so we can just call them unconditionally here.
>
Yes, this can be dropped. Will do that.
>Aside from that,
>
>Reviewed-by: Matt Roper
>
Thanks Matt for the review and valuable comments.
Regards,
Uma Shankar
>> +hsw_disable_ips(crtc_state);
>> +
>> +intel_color_set_csc(crtc_state);
>> +intel_color_load_luts(crtc_state);
>> +
>> +if (crtc_state->ips_enabled)
>> +hsw_enable_ips(crtc_state);
>> +}
>> +
>> /* Adjust the state of the output pipe according to whether we
>> * have active connectors/encoders. */
>> if (crtc_state->base.active && !intel_crtc_has_encoders(crtc))
>> --
>> 1.9.1
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>IoTG Platform Enabling & Development
>Intel Corporation
>(916) 356-2795
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Re: [Intel-gfx] [PATCH v24 5/6] drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only)
On 08/01/2019 16:29, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
We want to allow userspace to reconfigure the subslice configuration on a
per context basis.
This is required for the functional requirement of shutting down non-VME
enabled sub-slices on Gen11 parts.
To do so, we expose a context parameter to allow adjustment of the RPCS
register stored within the context image (and currently not accessible via
LRI).
If the context is adjusted before first use or whilst idle, the adjustment
is for "free"; otherwise if the context is active we queue a request to do
so (using the kernel context), following all other activity by that
context, which is also marked as barrier for all following submission
against the same context.
Since the overhead of device re-configuration during context switching can
be significant, especially in multi-context workloads, we limit this new
uAPI to only support the Gen11 VME use case. In this use case either the
device is fully enabled, and exactly one slice and half of the subslices
are enabled.
Example usage:
struct drm_i915_gem_context_param_sseu sseu = { };
struct drm_i915_gem_context_param arg =
{ .param = I915_CONTEXT_PARAM_SSEU,
.ctx_id = gem_context_create(fd),
.size = sizeof(sseu),
.value = to_user_pointer()
};
/* Query device defaults. */
gem_context_get_param(fd, );
/* Set VME configuration on a 1x6x8 part. */
sseu.slice_mask = 0x1;
sseu.subslice_mask = 0xe0;
gem_context_set_param(fd, );
v2: Fix offset of CTX_R_PWR_CLK_STATE in intel_lr_context_set_sseu() (Lionel)
v3: Add ability to program this per engine (Chris)
v4: Move most get_sseu() into i915_gem_context.c (Lionel)
v5: Validate sseu configuration against the device's capabilities (Lionel)
v6: Change context powergating settings through MI_SDM on kernel context (Chris)
v7: Synchronize the requests following a powergating setting change using a
global
dependency (Chris)
Iterate timelines through dev_priv.gt.active_rings (Tvrtko)
Disable RPCS configuration setting for non capable users (Lionel/Tvrtko)
v8: s/union intel_sseu/struct intel_sseu/ (Lionel)
s/dev_priv/i915/ (Tvrtko)
Change uapi class/instance fields to u16 (Tvrtko)
Bump mask fields to 64bits (Lionel)
Don't return EPERM when dynamic sseu is disabled (Tvrtko)
v9: Import context image into kernel context's ppgtt only when
reconfiguring powergated slice/subslices (Chris)
Use aliasing ppgtt when needed (Michel)
Tvrtko Ursulin:
v10:
* Update for upstream changes.
* Request submit needs a RPM reference.
* Reject on !FULL_PPGTT for simplicity.
* Pull out get/set param to helpers for readability and less indent.
* Use i915_request_await_dma_fence in add_global_barrier to skip waits
on the same timeline and avoid GEM_BUG_ON.
* No need to explicitly assign a NULL pointer to engine in legacy mode.
* No need to move gen8_make_rpcs up.
* Factored out global barrier as prep patch.
* Allow to only CAP_SYS_ADMIN if !Gen11.
v11:
* Remove engine vfunc in favour of local helper. (Chris Wilson)
* Stop retiring requests before updates since it is not needed
(Chris Wilson)
* Implement direct CPU update path for idle contexts. (Chris Wilson)
* Left side dependency needs only be on the same context timeline.
(Chris Wilson)
* It is sufficient to order the timeline. (Chris Wilson)
* Reject !RCS configuration attempts with -ENODEV for now.
v12:
* Rebase for make_rpcs.
v13:
* Centralize SSEU normalization to make_rpcs.
* Type width checking (uAPI <-> implementation).
* Gen11 restrictions uAPI checks.
* Gen11 subslice count differences handling.
Chris Wilson:
* args->size handling fixes.
* Update context image from GGTT.
* Postpone context image update to pinning.
* Use i915_gem_active_raw instead of last_request_on_engine.
v14:
* Add activity tracker on intel_context to fix the lifetime issues
and simplify the code. (Chris Wilson)
v15:
* Fix context pin leak if no space in ring by simplifying the
context pinning sequence.
v16:
* Rebase for context get/set param locking changes.
* Just -ENODEV on !Gen11. (Joonas)
v17:
* Fix one Gen11 subslice enablement rule.
* Handle error from i915_sw_fence_await_sw_fence_gfp. (Chris Wilson)
v18:
* Update commit message. (Joonas)
* Restrict uAPI to VME use case. (Joonas)
v19:
* Rebase.
v20:
* Rebase for ce->active_tracker.
v21:
* Rebase for IS_GEN changes.
v22:
* Reserve uAPI for flags straight away. (Chris Wilson)
v23:
* Rebase for RUNTIME_INFO.
v24:
* Added some headline docs for the uapi usage. (Joonas/Chris)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100899
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107634
Issue: https://github.com/intel/media-driver/issues/267
Signed-off-by: Chris Wilson
[Intel-gfx] ✓ Fi.CI.IGT: success for Enable Y2xx and Y4xx (xx:10/12/16 bits) packed formats for ICL
== Series Details ==
Series: Enable Y2xx and Y4xx (xx:10/12/16 bits) packed formats for ICL
URL : https://patchwork.freedesktop.org/series/55035/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5401_full -> Patchwork_11279_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_11279_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11279_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_11279_full:
### IGT changes ###
Warnings
* igt@pm_rc6_residency@rc6-accuracy:
- shard-kbl: {SKIP} -> PASS
Known issues
Here are the changes found in Patchwork_11279_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_fence_thrash@bo-copy:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
* igt@gem_pwrite_pread@uncached-copy-performance:
- shard-glk: PASS -> INCOMPLETE [fdo#103359] / [k.org#198133]
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-hsw: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_color@pipe-b-degamma:
- shard-skl: PASS -> FAIL [fdo#104782]
* igt@kms_color@pipe-c-ctm-red-to-blue:
- shard-skl: PASS -> FAIL [fdo#107201]
* igt@kms_cursor_crc@cursor-128x128-dpms:
- shard-skl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_flip_tiling@flip-yf-tiled:
- shard-skl: PASS -> FAIL [fdo#108145]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
- shard-skl: NOTRUN -> FAIL [fdo#105683]
* igt@kms_panel_fitting@legacy:
- shard-skl: NOTRUN -> FAIL [fdo#105456]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] +1
* igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
- shard-iclb: NOTRUN -> FAIL [fdo#108948]
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: PASS -> FAIL [fdo#107815]
* igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
- shard-glk: PASS -> FAIL [fdo#103166]
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: PASS -> DMESG-FAIL [fdo#108950]
- shard-apl: PASS -> DMESG-FAIL [fdo#108950]
* igt@kms_sysfs_edid_timing:
- shard-skl: NOTRUN -> FAIL [fdo#100047]
* igt@pm_rpm@drm-resources-equal:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
Possible fixes
* igt@kms_atomic_transition@plane-all-transition-fencing:
- shard-apl: DMESG-WARN [fdo#103558] / [fdo#105602] / [fdo#109225]
-> PASS
* igt@kms_available_modes_crc@available_mode_test_crc:
- shard-apl: FAIL [fdo#106641] -> PASS
* igt@kms_color@pipe-c-legacy-gamma:
- shard-apl: FAIL [fdo#104782] -> PASS
* igt@kms_cursor_crc@cursor-64x64-onscreen:
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- shard-apl: DMESG-WARN [fdo#103558] / [fdo#105602] -> PASS +31
* igt@kms_draw_crc@draw-method-xrgb2101010-blt-ytiled:
- shard-skl: FAIL [fdo#103184] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
- shard-apl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
- shard-glk: FAIL [fdo#103167] -> PASS +4
* igt@kms_plane@pixel-format-pipe-a-planes:
- shard-apl: FAIL [fdo#103166] -> PASS
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-apl: FAIL [fdo#108948] -> PASS
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-glk: FAIL [fdo#103166] -> PASS +1
Warnings
* igt@kms_plane_multiple@atomic-pipe-a-tiling-none:
- shard-apl: DMESG-WARN [fdo#103558] / [fdo#105602] -> FAIL
[fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-apl: DMESG-FAIL [fdo#103166] / [fdo#103558] / [fdo#105602]
-> FAIL [fdo#103166]
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#103166]:
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Infoframe precompute/check (rev6)
On Fri, Jan 11, 2019 at 07:16:16AM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Infoframe precompute/check (rev6)
> URL : https://patchwork.freedesktop.org/series/49983/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5397_full -> Patchwork_11276_full
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_11276_full absolutely need to
> be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_11276_full, please notify your bug team to allow
> them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_11276_full:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@kms_plane_lowres@pipe-b-tiling-yf:
> - shard-apl: PASS -> DMESG-WARN
<3> [1056.140888] [drm:intel_dp_start_link_train [i915]] *ERROR* failed to
start channel equalization
<3> [1056.516144] [drm:lspcon_write_infoframe [i915]] *ERROR* DPCD write failed
at:0x5c0
<3> [1056.516228] [drm:lspcon_write_infoframe [i915]] *ERROR* Failed to write
AVI infoframes
<3> [1057.297289] [drm:lspcon_wait_mode [i915]] *ERROR* LSPCON mode hasn't
settled
Unrelated, and we seem to have several related bugs.
>
>
> Warnings
>
> * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite:
> - shard-hsw: {SKIP} -> PASS
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_11276_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gem_exec_schedule@pi-ringfull-bsd:
> - shard-iclb: NOTRUN -> FAIL [fdo#103158]
>
> * igt@kms_atomic_transition@plane-all-transition:
> - shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#109225]
>
> * igt@kms_busy@extended-modeset-hang-newfb-render-a:
> - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
>
> * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
> - shard-kbl: NOTRUN -> DMESG-WARN [fdo#107956]
>
> * igt@kms_chv_cursor_fail@pipe-c-128x128-left-edge:
> - shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +6
>
> * igt@kms_content_protection@legacy:
> - shard-kbl: NOTRUN -> FAIL [fdo#108597]
>
> * igt@kms_cursor_crc@cursor-128x128-suspend:
> - shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
>
> * igt@kms_cursor_crc@cursor-64x21-sliding:
> - shard-skl: NOTRUN -> FAIL [fdo#103232] +1
>
> * igt@kms_cursor_crc@cursor-64x64-dpms:
> - shard-iclb: NOTRUN -> FAIL [fdo#103232]
>
> * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
> - shard-iclb: PASS -> FAIL [fdo#103355]
>
> * igt@kms_draw_crc@draw-method-xrgb2101010-blt-ytiled:
> - shard-iclb: PASS -> WARN [fdo#108336] +2
>
> * igt@kms_flip@dpms-vs-vblank-race:
> - shard-glk: PASS -> FAIL [fdo#103060]
>
> * igt@kms_flip@flip-vs-expired-vblank:
> - shard-glk: PASS -> FAIL [fdo#102887] / [fdo#105363]
>
> * igt@kms_flip@flip-vs-modeset-vs-hang-interruptible:
> - shard-iclb: PASS -> DMESG-WARN [fdo#107724] +7
>
> * igt@kms_flip_tiling@flip-changes-tiling-yf:
> - shard-skl: NOTRUN -> FAIL [fdo#108228] / [fdo#108303]
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt:
> - shard-skl: NOTRUN -> FAIL [fdo#105682] +1
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
> - shard-apl: PASS -> FAIL [fdo#103167] +1
>
> * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt:
> - shard-glk: PASS -> FAIL [fdo#103167]
>
> * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-blt:
> - shard-iclb: PASS -> DMESG-FAIL [fdo#107724] +1
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
> - shard-skl: NOTRUN -> FAIL [fdo#103167] +2
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move:
> - shard-iclb: PASS -> FAIL [fdo#103167] +1
>
> * igt@kms_frontbuffer_tracking@psr-suspend:
> - shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#106978] /
> [fdo#107773]
>
> * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
> - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885]
>
> * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
> - shard-iclb: PASS -> INCOMPLETE [fdo#107713]
>
> * igt@kms_plane@plane-position-covered-pipe-a-planes:
> - shard-iclb: NOTRUN -> FAIL [fdo#103166]
>
> * igt@kms_plane@plane-position-covered-pipe-c-planes:
> - shard-glk: PASS ->
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_tiled_wc: Reuse common gem_get_tiling
On 11/01/2019 13:57, Chris Wilson wrote:
get_tiling == gem_get_tiling + igt_require; so do that instead of
opencoding the ioctl.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/i915/gem_tiled_wc.c | 23 +--
1 file changed, 1 insertion(+), 22 deletions(-)
diff --git a/tests/i915/gem_tiled_wc.c b/tests/i915/gem_tiled_wc.c
index 65ac38510..21390729d 100644
--- a/tests/i915/gem_tiled_wc.c
+++ b/tests/i915/gem_tiled_wc.c
@@ -104,27 +104,6 @@ calculate_expected(int offset)
return (base_y + tile_y) * WIDTH + base_x + tile_x;
}
-static void
-get_tiling(int fd, uint32_t handle, uint32_t *tiling, uint32_t *swizzle)
-{
- struct drm_i915_gem_get_tiling2 {
- uint32_t handle;
- uint32_t tiling_mode;
- uint32_t swizzle_mode;
- uint32_t phys_swizzle_mode;
- } arg;
-#define DRM_IOCTL_I915_GEM_GET_TILING2 DRM_IOWR (DRM_COMMAND_BASE +
DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2)
-
- memset(, 0, sizeof(arg));
- arg.handle = handle;
-
- do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, );
- igt_require(arg.phys_swizzle_mode == arg.swizzle_mode);
-
- *tiling = arg.tiling_mode;
- *swizzle = arg.swizzle_mode;
-}
-
igt_simple_main
{
int fd;
@@ -136,7 +115,7 @@ igt_simple_main
gem_require_mmap_wc(fd);
handle = create_bo(fd);
- get_tiling(fd, handle, , );
+ igt_require(gem_get_tiling(fd, handle, , ));
if (IS_GEN2(intel_get_drm_devid(fd))) {
tile_height = 16;
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
___
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Re: [Intel-gfx] [PATCH i-g-t v2] i915/gem_tiled_pread: Skip on unknown swizzling
On 11/01/2019 13:54, Chris Wilson wrote: If we do not know the underlying swizzle on the HW, we do not know the full tiling pattern and cannot predict the expected results. This is often because the swizzle varies between pages and is not as constant as we naively expected. v2: gem_get_tiling() does the physical==reported check, we just need to add an acquire Signed-off-by: Chris Wilson Cc: --- tests/i915/gem_tiled_pread_pwrite.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/i915/gem_tiled_pread_pwrite.c b/tests/i915/gem_tiled_pread_pwrite.c index 313daa388..fcf0780af 100644 --- a/tests/i915/gem_tiled_pread_pwrite.c +++ b/tests/i915/gem_tiled_pread_pwrite.c @@ -122,7 +122,7 @@ igt_simple_main current_tiling_mode = I915_TILING_X; handle = create_bo_and_fill(fd); - gem_get_tiling(fd, handle, , ); + igt_require(gem_get_tiling(fd, handle, , )); gem_read(fd, handle, 0, linear, sizeof(linear)); Reviewed-by: Tvrtko Ursulin Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915/gem_tiled_wc: Reuse common gem_get_tiling
get_tiling == gem_get_tiling + igt_require; so do that instead of
opencoding the ioctl.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/i915/gem_tiled_wc.c | 23 +--
1 file changed, 1 insertion(+), 22 deletions(-)
diff --git a/tests/i915/gem_tiled_wc.c b/tests/i915/gem_tiled_wc.c
index 65ac38510..21390729d 100644
--- a/tests/i915/gem_tiled_wc.c
+++ b/tests/i915/gem_tiled_wc.c
@@ -104,27 +104,6 @@ calculate_expected(int offset)
return (base_y + tile_y) * WIDTH + base_x + tile_x;
}
-static void
-get_tiling(int fd, uint32_t handle, uint32_t *tiling, uint32_t *swizzle)
-{
- struct drm_i915_gem_get_tiling2 {
- uint32_t handle;
- uint32_t tiling_mode;
- uint32_t swizzle_mode;
- uint32_t phys_swizzle_mode;
- } arg;
-#define DRM_IOCTL_I915_GEM_GET_TILING2 DRM_IOWR (DRM_COMMAND_BASE +
DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2)
-
- memset(, 0, sizeof(arg));
- arg.handle = handle;
-
- do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, );
- igt_require(arg.phys_swizzle_mode == arg.swizzle_mode);
-
- *tiling = arg.tiling_mode;
- *swizzle = arg.swizzle_mode;
-}
-
igt_simple_main
{
int fd;
@@ -136,7 +115,7 @@ igt_simple_main
gem_require_mmap_wc(fd);
handle = create_bo(fd);
- get_tiling(fd, handle, , );
+ igt_require(gem_get_tiling(fd, handle, , ));
if (IS_GEN2(intel_get_drm_devid(fd))) {
tile_height = 16;
--
2.20.1
___
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[Intel-gfx] [PATCH i-g-t v2] i915/gem_tiled_pread: Skip on unknown swizzling
If we do not know the underlying swizzle on the HW, we do not know the full tiling pattern and cannot predict the expected results. This is often because the swizzle varies between pages and is not as constant as we naively expected. v2: gem_get_tiling() does the physical==reported check, we just need to add an acquire Signed-off-by: Chris Wilson Cc: --- tests/i915/gem_tiled_pread_pwrite.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/i915/gem_tiled_pread_pwrite.c b/tests/i915/gem_tiled_pread_pwrite.c index 313daa388..fcf0780af 100644 --- a/tests/i915/gem_tiled_pread_pwrite.c +++ b/tests/i915/gem_tiled_pread_pwrite.c @@ -122,7 +122,7 @@ igt_simple_main current_tiling_mode = I915_TILING_X; handle = create_bo_and_fill(fd); - gem_get_tiling(fd, handle, , ); + igt_require(gem_get_tiling(fd, handle, , )); gem_read(fd, handle, 0, linear, sizeof(linear)); -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 20/21] drm/i915: Complain if hsw_get_pipe_config acquires the same power well twice
Chris Wilson writes:
> As we only release each power well once, we assume that each transcoder
> maps to a different domain. Complain if this is not so.
>
> Signed-off-by: Chris Wilson
> Cc: Jani Nikula
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/intel_display.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 36c56d1637b8..7c974cf064fd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9569,6 +9569,8 @@ static bool hsw_get_transcoder_state(struct intel_crtc
> *crtc,
> power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
> if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
> return false;
> +
> + WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
> *power_domain_mask |= BIT_ULL(power_domain);
>
> tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
> @@ -9596,6 +9598,8 @@ static bool bxt_get_dsi_transcoder_state(struct
> intel_crtc *crtc,
> power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
> if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
> continue;
> +
> + WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
> *power_domain_mask |= BIT_ULL(power_domain);
>
> /*
> @@ -9712,7 +9716,9 @@ static bool haswell_get_pipe_config(struct intel_crtc
> *crtc,
>
> power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
> if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
> + WARN_ON(power_domain_mask & BIT_ULL(power_domain));
> power_domain_mask |= BIT_ULL(power_domain);
> +
> if (INTEL_GEN(dev_priv) >= 9)
> skylake_get_pfit_config(crtc, pipe_config);
> else
> --
> 2.20.1
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Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_tiled_pread: Skip on unknown swizzling
On 07/01/2019 11:28, Chris Wilson wrote:
If we do not know the underlying swizzle on the HW, we do not know the
full tiling pattern and cannot predict the expected results. This is
often because the swizzle varies between pages and is not as constant as
we naively expected.
Signed-off-by: Chris Wilson
---
tests/i915/gem_tiled_pread_basic.c | 23 ++-
tests/i915/gem_tiled_pread_pwrite.c | 23 ++-
2 files changed, 44 insertions(+), 2 deletions(-)
diff --git a/tests/i915/gem_tiled_pread_basic.c
b/tests/i915/gem_tiled_pread_basic.c
index 425bb07e7..48b1b37e2 100644
--- a/tests/i915/gem_tiled_pread_basic.c
+++ b/tests/i915/gem_tiled_pread_basic.c
@@ -61,6 +61,27 @@ static int tile_width;
static int tile_height;
static int tile_size;
+static void
+get_tiling(int fd, uint32_t handle, uint32_t *tiling, uint32_t *swizzle)
+{
+ struct drm_i915_gem_get_tiling2 {
+ uint32_t handle;
+ uint32_t tiling_mode;
+ uint32_t swizzle_mode;
+ uint32_t phys_swizzle_mode;
+ } arg;
+#define DRM_IOCTL_I915_GEM_GET_TILING2 DRM_IOWR (DRM_COMMAND_BASE +
DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2)
+
+ memset(, 0, sizeof(arg));
+ arg.handle = handle;
+
+ do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, );
+ igt_require(arg.phys_swizzle_mode == arg.swizzle_mode);
+
+ *tiling = arg.tiling_mode;
+ *swizzle = arg.swizzle_mode;
+}
Awooga! Third copy consolidates. ;)
Common gem_get_tiling and igt_require in the callers? Hm wait,
gem_get_tiling looks identical. What's the catch?
Regards,
Tvrtko
+
static uint32_t
create_bo(int fd)
{
@@ -125,7 +146,7 @@ igt_simple_main
fd = drm_open_driver(DRIVER_INTEL);
handle = create_bo(fd);
- igt_require(gem_get_tiling(fd, handle, , ));
+ get_tiling(fd, handle, , );
devid = intel_get_drm_devid(fd);
diff --git a/tests/i915/gem_tiled_pread_pwrite.c b/tests/i915/gem_tiled_pread_pwrite.c
index 313daa388..59afae896 100644
--- a/tests/i915/gem_tiled_pread_pwrite.c
+++ b/tests/i915/gem_tiled_pread_pwrite.c
@@ -69,6 +69,27 @@ static uint32_t current_tiling_mode;
#define PAGE_SIZE 4096
+static void
+get_tiling(int fd, uint32_t handle, uint32_t *tiling, uint32_t *swizzle)
+{
+ struct drm_i915_gem_get_tiling2 {
+ uint32_t handle;
+ uint32_t tiling_mode;
+ uint32_t swizzle_mode;
+ uint32_t phys_swizzle_mode;
+ } arg;
+#define DRM_IOCTL_I915_GEM_GET_TILING2 DRM_IOWR (DRM_COMMAND_BASE +
DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2)
+
+ memset(, 0, sizeof(arg));
+ arg.handle = handle;
+
+ do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, );
+ igt_require(arg.phys_swizzle_mode == arg.swizzle_mode);
+
+ *tiling = arg.tiling_mode;
+ *swizzle = arg.swizzle_mode;
+}
+
static uint32_t
create_bo_and_fill(int fd)
{
@@ -122,7 +143,7 @@ igt_simple_main
current_tiling_mode = I915_TILING_X;
handle = create_bo_and_fill(fd);
- gem_get_tiling(fd, handle, , );
+ get_tiling(fd, handle, , );
gem_read(fd, handle, 0, linear, sizeof(linear));
___
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Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_ppgtt: Convert stress test to run for a fixed duration
On 08/01/2019 14:50, Chris Wilson wrote:
Currently blt-vs-render runs for a fixed loop count, and exceeds 360s
on a slow Skylake-y. It really doesn't tell us anything useful about low
likelihood events after the first few seconds it takes to fill memory,
so limit it to 30s (and hope that repeated runs in CI is enough to
exercise the even rarer corner cases).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108039
Signed-off-by: Chris Wilson
---
tests/i915/gem_ppgtt.c | 55 ++
1 file changed, 39 insertions(+), 16 deletions(-)
diff --git a/tests/i915/gem_ppgtt.c b/tests/i915/gem_ppgtt.c
index c2e4ca679..11ca31e74 100644
--- a/tests/i915/gem_ppgtt.c
+++ b/tests/i915/gem_ppgtt.c
@@ -85,7 +85,9 @@ static void scratch_buf_fini(struct igt_buf *buf)
memset(buf, 0, sizeof(*buf));
}
-static void fork_rcs_copy(int target, drm_intel_bo **dst, int count, unsigned flags)
+static void fork_rcs_copy(int timeout, uint32_t final,
+ drm_intel_bo **dst, int count,
+ unsigned flags)
#define CREATE_CONTEXT 0x1
{
igt_render_copyfunc_t render_copy;
@@ -117,6 +119,8 @@ static void fork_rcs_copy(int target, drm_intel_bo **dst,
int count, unsigned fl
igt_fork(child, count) {
struct intel_batchbuffer *batch;
struct igt_buf buf = {};
+ struct igt_buf src;
+ unsigned long i;
batch = intel_batchbuffer_alloc(dst[child]->bufmgr,
devid);
@@ -135,23 +139,29 @@ static void fork_rcs_copy(int target, drm_intel_bo **dst,
int count, unsigned fl
buf.size = SIZE;
buf.bpp = 32;
- for (int i = 0; i <= target; i++) {
- struct igt_buf src;
-
+ i = 0;
+ igt_until_timeout(timeout) {
scratch_buf_init(, dst[child]->bufmgr,
-i | child << 16);
-
+i++ | child << 16);
render_copy(batch, NULL,
, 0, 0,
WIDTH, HEIGHT,
, 0, 0);
-
scratch_buf_fini();
}
+
+ scratch_buf_init(, dst[child]->bufmgr,
+final | child << 16);
+ render_copy(batch, NULL,
+ , 0, 0,
+ WIDTH, HEIGHT,
+ , 0, 0);
+ scratch_buf_fini();
}
}
-static void fork_bcs_copy(int target, drm_intel_bo **dst, int count)
+static void fork_bcs_copy(int timeout, uint32_t final,
+ drm_intel_bo **dst, int count)
{
int devid;
@@ -169,18 +179,20 @@ static void fork_bcs_copy(int target, drm_intel_bo **dst, int count)
igt_fork(child, count) {
struct intel_batchbuffer *batch;
+ drm_intel_bo *src[2];
+ unsigned long i;
+
batch = intel_batchbuffer_alloc(dst[child]->bufmgr,
devid);
igt_assert(batch);
- for (int i = 0; i <= target; i++) {
- drm_intel_bo *src[2];
-
+ i = 0;
+ igt_until_timeout(timeout) {
src[0] = create_bo(dst[child]->bufmgr,
~0);
src[1] = create_bo(dst[child]->bufmgr,
- i | child << 16);
+ i++ | child << 16);
intel_copy_bo(batch, src[0], src[1], SIZE);
intel_copy_bo(batch, dst[child], src[0], SIZE);
@@ -188,6 +200,17 @@ static void fork_bcs_copy(int target, drm_intel_bo **dst,
int count)
drm_intel_bo_unreference(src[1]);
drm_intel_bo_unreference(src[0]);
}
+
+ src[0] = create_bo(dst[child]->bufmgr,
+ ~0);
+ src[1] = create_bo(dst[child]->bufmgr,
+ final | child << 16);
+
+ intel_copy_bo(batch, src[0], src[1], SIZE);
+ intel_copy_bo(batch, dst[child], src[0], SIZE);
+
+ drm_intel_bo_unreference(src[1]);
+ drm_intel_bo_unreference(src[0]);
}
}
@@ -314,8 +337,8 @@ int main(int argc, char **argv)
igt_subtest("blt-vs-render-ctx0") {
drm_intel_bo *bcs[1], *rcs[N_CHILD];
- fork_bcs_copy(0x4000, bcs, 1);
- fork_rcs_copy(0x8000 / N_CHILD, rcs, N_CHILD, 0);
+ fork_bcs_copy(30, 0x4000, bcs, 1);
+ fork_rcs_copy(30, 0x8000 / N_CHILD, rcs, N_CHILD, 0);
igt_waitchildren();
@@ -326,8 +349,8 @@ int main(int argc, char **argv)
Re: [Intel-gfx] [PATCH 3/3] drm/i915/icl: Enabling Y2xx and Y4xx (xx:10/12/16) formats for universal planes
On 11.1.2019 7.30, swati2.sha...@intel.com wrote:
From: Swati Sharma
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/intel_display.c | 30 ++
drivers/gpu/drm/i915/intel_sprite.c | 61 ++--
2 files changed, 89 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 1cc441f..e7a86c6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2633,6 +2633,18 @@ int skl_format_to_fourcc(int format, bool rgb_order,
bool alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_Y210:
+ return DRM_FORMAT_Y210;
+ case PLANE_CTL_FORMAT_Y212:
+ return DRM_FORMAT_Y212;
+ case PLANE_CTL_FORMAT_Y216:
+ return DRM_FORMAT_Y216;
+ case PLANE_CTL_FORMAT_Y410:
+ return DRM_FORMAT_Y410;
+ case PLANE_CTL_FORMAT_Y412:
+ return DRM_FORMAT_Y412;
+ case PLANE_CTL_FORMAT_Y416:
+ return DRM_FORMAT_Y416;
default:
case PLANE_CTL_FORMAT_XRGB_:
if (rgb_order) {
@@ -3529,6 +3541,18 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
case DRM_FORMAT_NV12:
return PLANE_CTL_FORMAT_NV12;
+ case DRM_FORMAT_Y210:
+ return PLANE_CTL_FORMAT_Y210;
+ case DRM_FORMAT_Y212:
+ return PLANE_CTL_FORMAT_Y212;
+ case DRM_FORMAT_Y216:
+ return PLANE_CTL_FORMAT_Y216;
+ case DRM_FORMAT_Y410:
+ return PLANE_CTL_FORMAT_Y410;
+ case DRM_FORMAT_Y412:
+ return PLANE_CTL_FORMAT_Y412;
+ case DRM_FORMAT_Y416:
+ return PLANE_CTL_FORMAT_Y416;
default:
MISSING_CASE(pixel_format);
}
@@ -5022,6 +5046,12 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_Y210:
+ case DRM_FORMAT_Y212:
+ case DRM_FORMAT_Y216:
+ case DRM_FORMAT_Y410:
+ case DRM_FORMAT_Y412:
+ case DRM_FORMAT_Y416:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format
0x%x\n",
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 8f3982c..f1bc46d 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1750,6 +1750,27 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device
*dev, void *data,
DRM_FORMAT_VYUY,
};
+static const uint32_t icl_plane_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_Y210,
+ DRM_FORMAT_Y212,
+ DRM_FORMAT_Y216,
+ DRM_FORMAT_Y410,
+ DRM_FORMAT_Y412,
+ DRM_FORMAT_Y416,
+};
+
static const uint32_t skl_planar_formats[] = {
DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
@@ -1766,6 +1787,28 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device
*dev, void *data,
DRM_FORMAT_NV12,
};
+static const uint32_t icl_planar_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_Y210,
+ DRM_FORMAT_Y212,
+ DRM_FORMAT_Y216,
+ DRM_FORMAT_Y410,
+ DRM_FORMAT_Y412,
+ DRM_FORMAT_Y416,
+};
+
static const uint64_t skl_plane_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
@@ -1904,6 +1947,12 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+ case DRM_FORMAT_Y210:
+ case DRM_FORMAT_Y212:
+ case DRM_FORMAT_Y216:
+ case DRM_FORMAT_Y410:
+ case DRM_FORMAT_Y412:
+ case DRM_FORMAT_Y416:
case DRM_FORMAT_NV12:
if (modifier == I915_FORMAT_MOD_Yf_TILED)
return true;
@@ -2045,8 +2094,16 @@ struct intel_plane *
plane->update_slave = icl_update_slave;
if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
- formats = skl_planar_formats;
-
[Intel-gfx] [PATCH i-g-t] Make force work with multiple drivers available
The force option allows users to specify which driver they want that IGT
uses. Nonetheless, if the user has two or more loaded drivers in his
system, the force option will not work as expected because IGT will take
the first driver found at /dev/dri. This problem can be reproduced in a
QEMU VM that using Bochs and VKMS. This patch handles this scenario by
ensuring that IGT uses the forced module specified via IGT_FORCE_DRIVER.
Signed-off-by: Rodrigo Siqueira
---
lib/drmtest.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/lib/drmtest.c b/lib/drmtest.c
index 35914c50..7c124ac6 100644
--- a/lib/drmtest.c
+++ b/lib/drmtest.c
@@ -250,10 +250,8 @@ static int open_device(const char *name, unsigned int
chipset)
goto err;
forced = forced_driver();
- if (forced && chipset == DRIVER_ANY && !strcmp(forced, dev_name)) {
- igt_debug("Force option used: Using driver %s\n", dev_name);
- return fd;
- }
+ if (forced && chipset == DRIVER_ANY && strcmp(forced, dev_name))
+ goto err;
for (int start = 0, end = ARRAY_SIZE(modules) - 1; start < end; ){
int mid = start + (end - start) / 2;
@@ -277,6 +275,12 @@ err:
static int __search_and_open(const char *base, int offset, unsigned int
chipset)
{
+ const char *forced;
+
+ forced = forced_driver();
+ if (forced)
+ igt_info("Force option used: Using driver %s\n", forced);
+
for (int i = 0; i < 16; i++) {
char name[80];
int fd;
--
2.20.1
___
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Re: [Intel-gfx] [PATCH 17/21] drm/i915: Track the wakeref used to initialise display power domains
Chris Wilson writes:
> On module load and unload, we grab the POWER_DOMAIN_INIT powerwells and
> transfer them to the runtime-pm code. We can use our wakeref tracking to
> verify that the wakeref is indeed passed from init to enable, and
> disable to fini; and across suspend.
>
> Signed-off-by: Chris Wilson
> Cc: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 3 +
> drivers/gpu/drm/i915/i915_drv.h | 2 +
> drivers/gpu/drm/i915/intel_runtime_pm.c | 151 +---
> 3 files changed, 88 insertions(+), 68 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index b7dcacf2a5d3..96717a23b32f 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2699,6 +2699,9 @@ static int i915_runtime_pm_status(struct seq_file *m,
> void *unused)
> if (!HAS_RUNTIME_PM(dev_priv))
> seq_puts(m, "Runtime power management not supported\n");
>
> + seq_printf(m, "Runtime power management: %s\n",
> +enableddisabled(!dev_priv->power_domains.wakeref));
> +
> seq_printf(m, "GPU idle: %s (epoch %u)\n",
> yesno(!dev_priv->gt.awake), dev_priv->gt.epoch);
> seq_printf(m, "IRQs disabled: %s\n",
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 44c1b21febba..259b91b62ff2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -822,6 +822,8 @@ struct i915_power_domains {
> bool display_core_suspended;
> int power_well_count;
>
> + intel_wakeref_t wakeref;
> +
> struct mutex lock;
> int domain_use_count[POWER_DOMAIN_NUM];
> struct i915_power_well *power_wells;
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index fd2fc10dd1e4..8d38f3e7fad1 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -4009,7 +4009,7 @@ static void intel_power_domains_verify_state(struct
> drm_i915_private *dev_priv);
>
> /**
> * intel_power_domains_init_hw - initialize hardware power domain state
> - * @dev_priv: i915 device instance
> + * @i915: i915 device instance
> * @resume: Called from resume code paths or not
> *
> * This function initializes the hardware power domain state and enables all
> @@ -4023,30 +4023,31 @@ static void intel_power_domains_verify_state(struct
> drm_i915_private *dev_priv);
> * intel_power_domains_enable()) and must be paired with
> * intel_power_domains_fini_hw().
> */
> -void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool
> resume)
> +void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
> {
> - struct i915_power_domains *power_domains = _priv->power_domains;
> + struct i915_power_domains *power_domains = >power_domains;
>
> power_domains->initializing = true;
>
> - if (IS_ICELAKE(dev_priv)) {
> - icl_display_core_init(dev_priv, resume);
> - } else if (IS_CANNONLAKE(dev_priv)) {
> - cnl_display_core_init(dev_priv, resume);
> - } else if (IS_GEN9_BC(dev_priv)) {
> - skl_display_core_init(dev_priv, resume);
> - } else if (IS_GEN9_LP(dev_priv)) {
> - bxt_display_core_init(dev_priv, resume);
> - } else if (IS_CHERRYVIEW(dev_priv)) {
> + if (IS_ICELAKE(i915)) {
> + icl_display_core_init(i915, resume);
> + } else if (IS_CANNONLAKE(i915)) {
> + cnl_display_core_init(i915, resume);
> + } else if (IS_GEN9_BC(i915)) {
> + skl_display_core_init(i915, resume);
> + } else if (IS_GEN9_LP(i915)) {
> + bxt_display_core_init(i915, resume);
> + } else if (IS_CHERRYVIEW(i915)) {
> mutex_lock(_domains->lock);
> - chv_phy_control_init(dev_priv);
> + chv_phy_control_init(i915);
> mutex_unlock(_domains->lock);
> - } else if (IS_VALLEYVIEW(dev_priv)) {
> + } else if (IS_VALLEYVIEW(i915)) {
> mutex_lock(_domains->lock);
> - vlv_cmnlane_wa(dev_priv);
> + vlv_cmnlane_wa(i915);
> mutex_unlock(_domains->lock);
> - } else if (IS_IVYBRIDGE(dev_priv) || INTEL_GEN(dev_priv) >= 7)
> - intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
> + } else if (IS_IVYBRIDGE(i915) || INTEL_GEN(i915) >= 7) {
> + intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915));
> + }
>
> /*
>* Keep all power wells enabled for any dependent HW access during
> @@ -4054,18 +4055,20 @@ void intel_power_domains_init_hw(struct
> drm_i915_private *dev_priv, bool resume)
>* resources powered until display HW readout is complete. We drop
>* this reference in intel_power_domains_enable().
>*/
> - intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
> +
Re: [Intel-gfx] [PATCH 1/3] drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc
On 11-Jan-19 6:17 PM, Juha-Pekka Heikkila wrote:
On 11.1.2019 7.30, swati2.sha...@intel.com wrote:
From: Swati Sharma
The following pixel formats are packed format that follows 4:2:2
chroma sampling. For memory represenation each component is
allocated 16 bits each. Thus each pixel occupies 32bit.
Y210: For each component, valid data occupies MSB 10 bits.
LSB 6 bits are filled with zeroes.
Y212: For each component, valid data occupies MSB 12 bits.
LSB 4 bits are filled with zeroes.
Y216: For each component valid data occupies 16 bits,
doesn't require any padding bits.
First 16 bits stores the Y value and the next 16 bits stores one
of the chroma samples alternatively. The first luma sample will
be accompanied by first U sample and second luma sample is
accompanied by the first V sample.
The following pixel formats are packed format that follows 4:4:4
chroma sampling. Channels are arranged in the order UYVA in
increasing memory order.
Y410: Each color component occupies 10 bits and X component
takes 2 bits, thus each pixel occupies 32 bits.
Y412: Each color component is 16 bits where valid data
occupies MSB 12 bits. LSB 4 bits are filled with zeroes.
Thus, each pixel occupies 64 bits.
Y416: Each color component occupies 16 bits for valid data,
doesn't require any padding bits. Thus, each pixel
occupies 64 bits.
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/drm_fourcc.c | 6 ++
include/uapi/drm/drm_fourcc.h | 18 +-
2 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index d90ee03..639ab93 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -226,6 +226,12 @@ const struct drm_format_info
*__drm_format_info(u32 format)
{ .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes
= 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_XYUV, .depth = 0, .num_planes
= 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes
= 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
.is_yuv = true },
+ { .format = DRM_FORMAT_Y210, .depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv =
true },
+ { .format = DRM_FORMAT_Y212, .depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv =
true },
+ { .format = DRM_FORMAT_Y216, .depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv =
true },
+ { .format = DRM_FORMAT_Y410, .depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv =
true },
+ { .format = DRM_FORMAT_Y412, .depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv =
true },
+ { .format = DRM_FORMAT_Y416, .depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv =
true },
{ .format = DRM_FORMAT_Y0L0, .depth = 0, .num_planes
= 1,
.char_per_block = { 8, 0, 0 }, .block_w = { 2, 0, 0 },
.block_h = { 2, 0, 0 },
.hsub = 2, .vsub = 2, .has_alpha = true, .is_yuv = true },
diff --git a/include/uapi/drm/drm_fourcc.h
b/include/uapi/drm/drm_fourcc.h
index 0b44260..97249a5 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -151,7 +151,23 @@
#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /*
[31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /*
[31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
-#define DRM_FORMAT_XYUV fourcc_code('X', 'Y', 'U', 'V')
/* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_XYUV fourcc_code('X', 'Y', 'U', 'V') /*
[31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
+
+/*
+ * packed Y2xx indicate for each component, xx valid data occupy msb
+ * 16-xx padding occupy lsb
+ */
+#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /*
[63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 10:6:10:6:10:6:10:6 little endian */
+#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /*
[63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 12:4:12:4:12:4:12:4 little endian */
+#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /*
[63:0] Y0:Cb0:Y1:Cr1 16:16:16:16 little endian */
+
+/*
+ * packed Y4xx indicate for each component, xx valid data occupy msb
+ * 16-xx padding occupy lsb except Y410
+ */
+#define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /*
[31:0] X:V:Y:U 2:10:10:10 little endian */
+#define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /*
[64:0] X:x:V:x:Y:x:U:x 12:4:12:4:12:4:12:4 little endian */
+#define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /*
[64:0] X:V:Y:U 16:16:16:16 little endian */
^^
[63:0] maybe?
ohh sorry.
Re: [Intel-gfx] [PATCH 2/3] drm/i915/icl: Add Y2xx and Y4xx (xx:10/12/16) plane control definitions
On 11.1.2019 7.30, swati2.sha...@intel.com wrote:
From: Swati Sharma
Added needed plane control flag definitions for Y2xx and Y4xx (10, 12 and
16 bits)
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 44958d9..7150bc5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6546,6 +6546,12 @@ enum {
#define PLANE_CTL_FORMAT_RGB_565(14 << 24)
#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
+#define PLANE_CTL_FORMAT_Y210 (1 << 23)
+#define PLANE_CTL_FORMAT_Y212 (3 << 23)
+#define PLANE_CTL_FORMAT_Y216 (5 << 23)
+#define PLANE_CTL_FORMAT_Y410 (7 << 23)
+#define PLANE_CTL_FORMAT_Y412 (9 << 23)
+#define PLANE_CTL_FORMAT_Y416 (0xb << 23)
#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
#define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
#define PLANE_CTL_KEY_ENABLE_DESTINATION(2 << 21)
Reviewed-by: Juha-Pekka Heikkila
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Re: [Intel-gfx] [PATCH 1/3] drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc
On 11.1.2019 7.30, swati2.sha...@intel.com wrote:
From: Swati Sharma
The following pixel formats are packed format that follows 4:2:2
chroma sampling. For memory represenation each component is
allocated 16 bits each. Thus each pixel occupies 32bit.
Y210: For each component, valid data occupies MSB 10 bits.
LSB 6 bits are filled with zeroes.
Y212: For each component, valid data occupies MSB 12 bits.
LSB 4 bits are filled with zeroes.
Y216: For each component valid data occupies 16 bits,
doesn't require any padding bits.
First 16 bits stores the Y value and the next 16 bits stores one
of the chroma samples alternatively. The first luma sample will
be accompanied by first U sample and second luma sample is
accompanied by the first V sample.
The following pixel formats are packed format that follows 4:4:4
chroma sampling. Channels are arranged in the order UYVA in
increasing memory order.
Y410: Each color component occupies 10 bits and X component
takes 2 bits, thus each pixel occupies 32 bits.
Y412: Each color component is 16 bits where valid data
occupies MSB 12 bits. LSB 4 bits are filled with zeroes.
Thus, each pixel occupies 64 bits.
Y416: Each color component occupies 16 bits for valid data,
doesn't require any padding bits. Thus, each pixel
occupies 64 bits.
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/drm_fourcc.c | 6 ++
include/uapi/drm/drm_fourcc.h | 18 +-
2 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index d90ee03..639ab93 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -226,6 +226,12 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_VYUY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_XYUV,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_AYUV,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
.is_yuv = true },
+ { .format = DRM_FORMAT_Y210,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_Y212,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_Y216,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_Y410,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_Y412,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_Y416,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_Y0L0,.depth = 0,
.num_planes = 1,
.char_per_block = { 8, 0, 0 }, .block_w = { 2, 0, 0 },
.block_h = { 2, 0, 0 },
.hsub = 2, .vsub = 2, .has_alpha = true, .is_yuv = true },
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 0b44260..97249a5 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -151,7 +151,23 @@
#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /*
[31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
-#define DRM_FORMAT_XYUVfourcc_code('X', 'Y', 'U', 'V') /*
[31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_XYUVfourcc_code('X', 'Y', 'U', 'V') /* [31:0]
X:Y:Cb:Cr 8:8:8:8 little endian */
+
+/*
+ * packed Y2xx indicate for each component, xx valid data occupy msb
+ * 16-xx padding occupy lsb
+ */
+#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0]
Y0:x:Cb0:x:Y1:x:Cr1:x 10:6:10:6:10:6:10:6 little endian */
+#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0]
Y0:x:Cb0:x:Y1:x:Cr1:x 12:4:12:4:12:4:12:4 little endian */
+#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0]
Y0:Cb0:Y1:Cr1 16:16:16:16 little endian */
+
+/*
+ * packed Y4xx indicate for each component, xx valid data occupy msb
+ * 16-xx padding occupy lsb except Y410
+ */
+#define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0]
X:V:Y:U 2:10:10:10 little endian */
+#define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [64:0]
X:x:V:x:Y:x:U:x 12:4:12:4:12:4:12:4 little endian */
+#define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /*
[Intel-gfx] ✓ Fi.CI.IGT: success for MST refcounting/atomic helpers cleanup (rev7)
== Series Details ==
Series: MST refcounting/atomic helpers cleanup (rev7)
URL : https://patchwork.freedesktop.org/series/54030/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5400_full -> Patchwork_11278_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_11278_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11278_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_11278_full:
### IGT changes ###
Warnings
* igt@tools_test@tools_test:
- shard-glk: {SKIP} -> PASS
Known issues
Here are the changes found in Patchwork_11278_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-skl: NOTRUN -> TIMEOUT [fdo#108039]
* igt@kms_atomic@plane_primary_legacy:
- shard-apl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602]
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-glk: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-snb: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-kbl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_color@pipe-c-gamma:
- shard-skl: PASS -> FAIL [fdo#104782] / [fdo#108228]
* igt@kms_color@pipe-c-legacy-gamma:
- shard-apl: PASS -> FAIL [fdo#104782]
* igt@kms_cursor_crc@cursor-128x128-sliding:
- shard-apl: PASS -> FAIL [fdo#103232] +1
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-skl: PASS -> INCOMPLETE [fdo#104108]
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_draw_crc@draw-method-xrgb2101010-blt-ytiled:
- shard-skl: PASS -> FAIL [fdo#103184]
* igt@kms_flip_tiling@flip-changes-tiling-yf:
- shard-skl: PASS -> FAIL [fdo#108228] / [fdo#108303]
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-render:
- shard-skl: PASS -> FAIL [fdo#103167] +2
* igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] +1
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-glk: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- shard-apl: PASS -> FAIL [fdo#103166] +1
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: PASS -> DMESG-FAIL [fdo#108950]
* igt@kms_rotation_crc@primary-rotation-90:
- shard-kbl: PASS -> DMESG-WARN [fdo#103313] / [fdo#105345]
* igt@kms_setmode@basic:
- shard-kbl: PASS -> FAIL [fdo#99912]
* igt@pm_rpm@drm-resources-equal:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
Possible fixes
* igt@gem_ctx_isolation@vecs0-s3:
- shard-skl: INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-skl: TIMEOUT [fdo#108039] -> PASS
* igt@gem_workarounds@suspend-resume-fd:
- shard-glk: INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
- shard-kbl: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_chv_cursor_fail@pipe-b-64x64-right-edge:
- shard-skl: FAIL [fdo#104671] -> PASS
* igt@kms_color@pipe-c-ctm-max:
- shard-apl: FAIL [fdo#108147] -> PASS
* igt@kms_color@pipe-c-degamma:
- shard-apl: FAIL [fdo#104782] -> PASS
* igt@kms_cursor_crc@cursor-256x85-random:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_draw_crc@draw-method-xrgb-mmap-cpu-ytiled:
- shard-skl: FAIL [fdo#107791] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
- shard-skl: FAIL [fdo#103167] -> PASS +2
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: FAIL [fdo#103167] -> PASS +2
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
- shard-glk: FAIL [fdo#103167] -> PASS +1
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: FAIL [fdo#107815] / [fdo#108145] -> PASS
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: FAIL [fdo#107815] -> PASS
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-apl: FAIL [fdo#103166] -> PASS +1
Warnings
*
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/hangman: Read a dummy byte to check sysfs existence
On 11/01/2019 10:35, Chris Wilson wrote:
sysfs doesn't give the driver an open() callback, so we can only report
the unavailability of HW on the first read; so check read() after checking
open().
Fixes: 93f0ad4b835e ("i915/hangman: Skip if disabled by the kernel")
Signed-off-by: Chris Wilson
---
tests/i915/hangman.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/tests/i915/hangman.c b/tests/i915/hangman.c
index ffbd0b057..5f63bfc4b 100644
--- a/tests/i915/hangman.c
+++ b/tests/i915/hangman.c
@@ -45,14 +45,20 @@ static int sysfs = -1;
static bool has_error_state(int dir)
{
+ bool result;
int fd;
fd = openat(dir, "error", O_RDONLY);
if (fd < 0)
return false;
+ if (read(fd, , sizeof(result)) < 0)
+ result = false;
+ else
+ result = true;
+
close(fd);
- return true;
+ return result;
}
static void assert_entry(const char *s, bool expect)
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/cnl: Fix CNL macros for Voltage Swing programming (rev2)
== Series Details ==
Series: drm/i915/cnl: Fix CNL macros for Voltage Swing programming (rev2)
URL : https://patchwork.freedesktop.org/series/54092/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5400_full -> Patchwork_11277_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_11277_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11277_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_11277_full:
### IGT changes ###
Warnings
* igt@kms_pipe_crc_basic@read-crc-pipe-a:
- shard-snb: PASS -> {SKIP} +1
* igt@pm_rc6_residency@rc6-accuracy:
- shard-kbl: PASS -> {SKIP}
* igt@tools_test@tools_test:
- shard-glk: {SKIP} -> PASS
Known issues
Here are the changes found in Patchwork_11277_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@read_all_entries_display_off:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] +1
* igt@gem_exec_schedule@pi-ringfull-bsd:
- shard-iclb: NOTRUN -> FAIL [fdo#103158]
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-skl: NOTRUN -> TIMEOUT [fdo#108039]
* igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108228] /
[fdo#108470]
* igt@kms_atomic_transition@plane-all-transition-fencing:
- shard-apl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] /
[fdo#109225]
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-glk: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-snb: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-kbl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_ccs@pipe-a-crc-primary-basic:
- shard-iclb: NOTRUN -> FAIL [fdo#107725] +1
* igt@kms_chv_cursor_fail@pipe-b-128x128-left-edge:
- shard-skl: NOTRUN -> FAIL [fdo#104671]
* igt@kms_cursor_crc@cursor-256x256-dpms:
- shard-skl: NOTRUN -> FAIL [fdo#103232] +1
* igt@kms_cursor_crc@cursor-256x256-random:
- shard-apl: PASS -> FAIL [fdo#103232] +4
* igt@kms_cursor_crc@cursor-64x64-dpms:
- shard-glk: PASS -> FAIL [fdo#103232]
- shard-iclb: NOTRUN -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- shard-apl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +31
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
- shard-iclb: PASS -> FAIL [fdo#105683] / [fdo#108040]
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-render:
- shard-skl: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-iclb: NOTRUN -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move:
- shard-iclb: PASS -> FAIL [fdo#103167] +1
* igt@kms_plane@pixel-format-pipe-a-planes:
- shard-glk: PASS -> FAIL [fdo#103166]
* igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] +1
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-iclb: PASS -> INCOMPLETE [fdo#107713]
* igt@kms_plane@plane-position-covered-pipe-b-planes:
- shard-iclb: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-glk: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- shard-apl: PASS -> FAIL [fdo#103166] +2
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-iclb: NOTRUN -> FAIL [fdo#103166]
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: PASS -> DMESG-FAIL [fdo#108950]
* igt@kms_setmode@basic:
- shard-kbl: PASS -> FAIL [fdo#99912]
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-hsw: PASS -> FAIL [fdo#104894]
*
[Intel-gfx] [PATCH i-g-t] i915/hangman: Read a dummy byte to check sysfs existence
sysfs doesn't give the driver an open() callback, so we can only report
the unavailability of HW on the first read; so check read() after checking
open().
Fixes: 93f0ad4b835e ("i915/hangman: Skip if disabled by the kernel")
Signed-off-by: Chris Wilson
---
tests/i915/hangman.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/tests/i915/hangman.c b/tests/i915/hangman.c
index ffbd0b057..5f63bfc4b 100644
--- a/tests/i915/hangman.c
+++ b/tests/i915/hangman.c
@@ -45,14 +45,20 @@ static int sysfs = -1;
static bool has_error_state(int dir)
{
+ bool result;
int fd;
fd = openat(dir, "error", O_RDONLY);
if (fd < 0)
return false;
+ if (read(fd, , sizeof(result)) < 0)
+ result = false;
+ else
+ result = true;
+
close(fd);
- return true;
+ return result;
}
static void assert_entry(const char *s, bool expect)
--
2.20.1
___
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Re: [Intel-gfx] [PATCH i-g-t] intel-ci/blacklist: Exclude gem_exec_parse lri
On Mon, Jan 07, 2019 at 04:40:15PM +, Chris Wilson wrote: > These exercise a certain HW misfeature, no longer protected by the > kernel cmdparser due to obsolete userspace requirements. > > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen > --- > tests/intel-ci/blacklist.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/tests/intel-ci/blacklist.txt b/tests/intel-ci/blacklist.txt > index 73d127603..0c6b87695 100644 > --- a/tests/intel-ci/blacklist.txt > +++ b/tests/intel-ci/blacklist.txt > @@ -35,6 +35,7 @@ igt@gem_exec_gttfill@(?!.*basic).* > igt@gem_exec_latency(@.*)? > igt@gem_exec_lut_handle(@.*)? > igt@gem_exec_nop@(?!.*(basic|signal-all)).* > +igt@gem_exec_parse@.*lri.* > igt@gem_exec_reloc@(?!.*basic).* > igt@gem_exec_suspend@(?!.*basic).* > igt@gem_exec_whisper@(?!normal$).* Put this in a separate section with a comment (commit message seems sufficient) that explains why it's blacklisted. With that, Acked-by: Petri Latvala ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL v2] drm-misc-fixes
On Thu, Jan 10, 2019 at 03:00:45PM +0100, Maarten Lankhorst wrote: > Hi Dave/Daniel, > > Some patches were pushed today to drm-misc-fixes, and I think it would be nice > if they are part of the pull req for v5.0-rc2. :) > > drm-misc-fixes-2019-01-10-1: > Second pull request, drm-misc-fixes for v5.0-rc2: > - Fix fb-helper to work correctly with SDL 1.2 bugs. > - Fix lockdep warning in the atomic ioctl and setproperty. > From first pull request: > - Fixes for the tc358767 bridge to work correctly with > tc358867 using a DP connector. > - Make resume work on amdgpu when a DP-MST display is unplugged. > The following changes since commit bfeffd155283772bbe78c6a05dec7c0128ee500c: Applied, thanks. -Daniel > > Linux 5.0-rc1 (2019-01-06 17:08:20 -0800) > > are available in the Git repository at: > > git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2019-01-10-1 > > for you to fetch changes up to 4089e272ac61603931beb024d4d640de2cb390e0: > > gpu/drm: Fix lock held when returning to user space. (2019-01-10 11:31:58 > +0100) > > > Second pull request, drm-misc-fixes for v5.0-rc2: > - Fix fb-helper to work correctly with SDL 1.2 bugs. > - Fix lockdep warning in the atomic ioctl and setproperty. > From first pull request: > - Fixes for the tc358767 bridge to work correctly with > tc358867 using a DP connector. > - Make resume work on amdgpu when a DP-MST display is unplugged. > > > Ivan Mironov (2): > drm/fb-helper: Partially bring back workaround for bugs of SDL 1.2 > drm/fb-helper: Ignore the value of fb_var_screeninfo.pixclock > > Lyude Paul (3): > drm/amdgpu: Don't ignore rc from drm_dp_mst_topology_mgr_resume() > drm/amdgpu: Don't fail resume process if resuming atomic state fails > drm/dp_mst: Add __must_check to drm_dp_mst_topology_mgr_resume() > > Tetsuo Handa (1): > gpu/drm: Fix lock held when returning to user space. > > Tomi Valkeinen (7): > drm/bridge: tc358767: add bus flags > drm/bridge: tc358767: add defines for DP1_SRCCTRL & PHY_2LANE > drm/bridge: tc358767: fix single lane configuration > drm/bridge: tc358767: fix initial DP0/1_SRCCTRL value > drm/bridge: tc358767: reject modes which require too much BW > drm/bridge: tc358767: fix output H/V syncs > drm/bridge: tc358767: use DP connector if no panel set > > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 37 -- > drivers/gpu/drm/bridge/tc358767.c | 48 ++-- > drivers/gpu/drm/drm_atomic_uapi.c | 3 +- > drivers/gpu/drm/drm_fb_helper.c | 133 > +- > drivers/gpu/drm/drm_mode_object.c | 4 +- > include/drm/drm_dp_mst_helper.h | 3 +- > 6 files changed, 147 insertions(+), 81 deletions(-) -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL] drm-intel-fixes
On Fri, Jan 11, 2019 at 11:18:22AM +0200, Jani Nikula wrote: > > Hi Dave & Daniel - > > drm-intel-fixes-2019-01-11: > i915 fixes for v5.0-rc2: > - Disable PSR for Apple panels > - Broxton ERR_PTR error state fix > - Kabylake VECS workaround fix > - Unwind failure on pinning the gen7 ppgtt > - GVT workload request allocation fix Applied, thanks. -Daniel > > BR, > Jani. > > The following changes since commit bfeffd155283772bbe78c6a05dec7c0128ee500c: > > Linux 5.0-rc1 (2019-01-06 17:08:20 -0800) > > are available in the Git repository at: > > git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2019-01-11 > > for you to fetch changes up to f299e0bdbaeb60fd8829f42e53a7457cc5a6f4a2: > > drm: Fix documentation generation for DP_DPCD_QUIRK_NO_PSR (2019-01-10 > 15:12:48 +0200) > > > i915 fixes for v5.0-rc2: > - Disable PSR for Apple panels > - Broxton ERR_PTR error state fix > - Kabylake VECS workaround fix > - Unwind failure on pinning the gen7 ppgtt > - GVT workload request allocation fix > > > Chris Wilson (2): > drm/i915: Skip the ERR_PTR error state > drm/i915: Unwind failure on pinning the gen7 ppgtt > > Daniele Ceraolo Spurio (1): > drm/i915: init per-engine WAs for all engines > > Jani Nikula (1): > Merge tag 'gvt-fixes-2019-01-09' of https://github.com/intel/gvt-linux > into drm-intel-fixes > > José Roberto de Souza (2): > drm/i915: Disable PSR in Apple panels > drm: Fix documentation generation for DP_DPCD_QUIRK_NO_PSR > > Zhenyu Wang (1): > drm/i915/gvt: Fix workload request allocation before request add > > drivers/gpu/drm/drm_dp_helper.c | 2 ++ > drivers/gpu/drm/i915/gvt/scheduler.c | 64 > +++ > drivers/gpu/drm/i915/gvt/scheduler.h | 1 + > drivers/gpu/drm/i915/i915_debugfs.c | 12 +-- > drivers/gpu/drm/i915/i915_gem_gtt.c | 15 ++-- > drivers/gpu/drm/i915/i915_gpu_error.c | 23 - > drivers/gpu/drm/i915/i915_sysfs.c | 4 ++- > drivers/gpu/drm/i915/intel_lrc.c | 3 +- > drivers/gpu/drm/i915/intel_psr.c | 6 > include/drm/drm_dp_helper.h | 7 > 10 files changed, 98 insertions(+), 39 deletions(-) > > -- > Jani Nikula, Intel Open Source Graphics Center -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave & Daniel - drm-intel-fixes-2019-01-11: i915 fixes for v5.0-rc2: - Disable PSR for Apple panels - Broxton ERR_PTR error state fix - Kabylake VECS workaround fix - Unwind failure on pinning the gen7 ppgtt - GVT workload request allocation fix BR, Jani. The following changes since commit bfeffd155283772bbe78c6a05dec7c0128ee500c: Linux 5.0-rc1 (2019-01-06 17:08:20 -0800) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2019-01-11 for you to fetch changes up to f299e0bdbaeb60fd8829f42e53a7457cc5a6f4a2: drm: Fix documentation generation for DP_DPCD_QUIRK_NO_PSR (2019-01-10 15:12:48 +0200) i915 fixes for v5.0-rc2: - Disable PSR for Apple panels - Broxton ERR_PTR error state fix - Kabylake VECS workaround fix - Unwind failure on pinning the gen7 ppgtt - GVT workload request allocation fix Chris Wilson (2): drm/i915: Skip the ERR_PTR error state drm/i915: Unwind failure on pinning the gen7 ppgtt Daniele Ceraolo Spurio (1): drm/i915: init per-engine WAs for all engines Jani Nikula (1): Merge tag 'gvt-fixes-2019-01-09' of https://github.com/intel/gvt-linux into drm-intel-fixes José Roberto de Souza (2): drm/i915: Disable PSR in Apple panels drm: Fix documentation generation for DP_DPCD_QUIRK_NO_PSR Zhenyu Wang (1): drm/i915/gvt: Fix workload request allocation before request add drivers/gpu/drm/drm_dp_helper.c | 2 ++ drivers/gpu/drm/i915/gvt/scheduler.c | 64 +++ drivers/gpu/drm/i915/gvt/scheduler.h | 1 + drivers/gpu/drm/i915/i915_debugfs.c | 12 +-- drivers/gpu/drm/i915/i915_gem_gtt.c | 15 ++-- drivers/gpu/drm/i915/i915_gpu_error.c | 23 - drivers/gpu/drm/i915/i915_sysfs.c | 4 ++- drivers/gpu/drm/i915/intel_lrc.c | 3 +- drivers/gpu/drm/i915/intel_psr.c | 6 include/drm/drm_dp_helper.h | 7 10 files changed, 98 insertions(+), 39 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] drm/i915: Watchdog timeout: IRQ handler for gen8+
On 11/01/2019 00:47, Antonio Argenziano wrote: On 07/01/19 08:58, Tvrtko Ursulin wrote: On 07/01/2019 13:57, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-01-07 13:43:29) On 07/01/2019 11:58, Tvrtko Ursulin wrote: [snip] Note about future interaction with preemption: Preemption could happen in a command sequence prior to watchdog counter getting disabled, resulting in watchdog being triggered following preemption (e.g. when watchdog had been enabled in the low priority batch). The driver will need to explicitly disable the watchdog counter as part of the preemption sequence. Does the series take care of preemption? I did not find that it does. Oh. I hoped that the watchdog was saved as part of the context... Then despite preemption, the timeout would resume from where we left off as soon as it was back on the gpu. If the timeout remaining was context saved it would be much simpler (at least on first glance), please say it is. I made my comments going only by the text from the commit message and the absence of any preemption special handling. Having read the spec, the situation seems like this: * Watchdog control and threshold register are context saved and restored. * On a context switch watchdog counter is reset to zero and automatically disabled until enabled by a context restore or explicitly. So it sounds the commit message could be wrong that special handling is needed from this direction. But read till the end on the restriction listed. * Watchdog counter is reset to zero and is not accumulated across multiple submission of the same context (due preemption). I read this as - after preemption contexts gets a new full timeout allocation. Or in other words, if a context is preempted N times, it's cumulative watchdog timeout will be N * set value. This could be theoretically exploitable to bypass the timeout. If a client sets up two contexts with prio -1 and -2, and keeps submitting periodical no-op batches against prio -1 context, while prio -2 is it's own hog, then prio -2 context defeats the watchdog timer. I think.. would appreciate is someone challenged this conclusion. I think you are right that is a possibility but, is that a problem? The client can just not set the threshold to bypass the timeout. Also because you need the hanging batch to be simply preemptible, you cannot disrupt any work from another client that is higher priority. This is But I think higher priority client can have the same effect on the lower priority purely by accident, no? As a real world example, user kicks off an background transcoding job, which happens to use prio -2, and uses the watchdog timer. At the same time user watches a video from a player of normal priority. This causes periodic, say 24Hz, preemption events, due frame decoding activity on the same engine as the transcoding client. Does this defeat the watchdog timer for the former is the question? Then the questions of can we do something about it and whether it really isn't a problem? Maybe it is not disrupting higher priority clients but it is causing an time unbound power drain. pretty much the same behavior of hangcheck IIRC so something we already accept. You mean today hangcheck wouldn't notice a hanging batch in the same scenario as above? If so it sounds like a huge gap we need to try and fix. And finally there is one programming restriction which says: * SW must not preempt the workload which has watchdog enabled. Either it must: a) disable preemption for that workload completely, or b) disable the watchdog via mmio write before any write to ELSP This seems it contradiction with the statement that the counter gets disabled on context switch and stays disabled. I did not spot anything like this in the series. So it would seem the commit message is correct after all. It would be good if someone could re-read the bspec text on register 0x2178 to double check what I wrote. The way I read it is that the restriction applies only to some platforms where the 'normal' description doesn't apply. You are right. Are the listed parts in the field so the series would have to handle this or we can ignore it? Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
