[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: Use mul_u32_u32() more (rev2)

== Series Details == Series: series starting with [1/2] drm/i915: Use mul_u32_u32() more (rev2) URL : https://patchwork.freedesktop.org/series/59180/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6017_full -> Patchwork_12909_full

[Intel-gfx] ✗ Fi.CI.IGT: failure for dma-buf: add struct dma_buf_attach_info v2

== Series Details == Series: dma-buf: add struct dma_buf_attach_info v2 URL : https://patchwork.freedesktop.org/series/60107/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6017_full -> Patchwork_12908_full Summary ---

[Intel-gfx] ✗ Fi.CI.BAT: failure for Refactor to expand subslice mask (rev6)

== Series Details == Series: Refactor to expand subslice mask (rev6) URL : https://patchwork.freedesktop.org/series/59742/ State : failure == Summary == Applying: drm/i915: Use local variable for SSEU info in GETPARAM ioctl Applying: drm/i915: Add macro for SSEU stride calculation Applying:

[Intel-gfx] [PATCH 1/6] drm/i915: Use local variable for SSEU info in GETPARAM ioctl

In the GETPARAM ioctl handler, use a local variable to consolidate usage of SSEU runtime info. v2: add const to sseu_dev_info variable Cc: Daniele Ceraolo Spurio Signed-off-by: Stuart Summers --- drivers/gpu/drm/i915/i915_drv.c | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-)

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Use local variable for SSEU info in GETPARAM ioctl

On Tue, 2019-04-30 at 11:58 +0300, Jani Nikula wrote: > On Mon, 29 Apr 2019, Stuart Summers wrote: > > In the GETPARAM ioctl handler, use a local variable to consolidate > > usage of SSEU runtime info. > > > > Cc: Daniele Ceraolo Spurio > > Signed-off-by: Stuart Summers > > --- > >

[Intel-gfx] ✓ Fi.CI.BAT: success for Refactor to expand subslice mask (rev5)

== Series Details == Series: Refactor to expand subslice mask (rev5) URL : https://patchwork.freedesktop.org/series/59742/ State : success == Summary == CI Bug Log - changes from CI_DRM_6020 -> Patchwork_12917 Summary ---

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Refactor to expand subslice mask (rev5)

== Series Details == Series: Refactor to expand subslice mask (rev5) URL : https://patchwork.freedesktop.org/series/59742/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Use local variable for SSEU info in GETPARAM ioctl Okay! Commit:

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev5)

== Series Details == Series: Refactor to expand subslice mask (rev5) URL : https://patchwork.freedesktop.org/series/59742/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2699899bf520 drm/i915: Use local variable for SSEU info in GETPARAM ioctl 5c73378a02c2 drm/i915: Add macro

[Intel-gfx] [PATCH 6/6] drm/i915: Expand subslice mask

Currently, the subslice_mask runtime parameter is stored as an array of subslices per slice. Expand the subslice mask array to better match what is presented to userspace through the I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is then calculated: slice * subslice stride + subslice

[Intel-gfx] [PATCH 3/6] drm/i915: Move calculation of subslices per slice to new function

Add a new function to return the number of subslices per slice to consolidate code usage. v2: rebase on changes to move sseu struct to intel_sseu.h Cc: Daniele Ceraolo Spurio Signed-off-by: Stuart Summers --- drivers/gpu/drm/i915/gt/intel_sseu.h | 6 ++

[Intel-gfx] [PATCH 1/6] drm/i915: Use local variable for SSEU info in GETPARAM ioctl

In the GETPARAM ioctl handler, use a local variable to consolidate usage of SSEU runtime info. Cc: Daniele Ceraolo Spurio Signed-off-by: Stuart Summers --- drivers/gpu/drm/i915/i915_drv.c | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git

Re: [Intel-gfx] [PATCH] dma-buf: add struct dma_buf_attach_info v2

Hi "Christian, I love your patch! Perhaps something to improve: [auto build test WARNING on linus/master] [also build test WARNING on v5.1-rc7 next-20190430] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0d

[Intel-gfx] [PATCH 0/6] Refactor to expand subslice mask

This patch series contains a few code clean-up patches, followed by a patch which changes the storage of the subslice mask to better match the userspace access through the I915_QUERY_TOPOLOGY_INFO ioctl. The index into the subslice_mask array is then calculated: slice * subslice stride +

[Intel-gfx] [PATCH 5/6] drm/i915: Remove inline from sseu helper functions

Additionally, ensure these are all prefixed with intel_sseu_* to match the convention of other functions in i915. Signed-off-by: Stuart Summers --- drivers/gpu/drm/i915/gt/intel_sseu.c | 54 +++ drivers/gpu/drm/i915/gt/intel_sseu.h | 57 +++-

[Intel-gfx] [PATCH 2/6] drm/i915: Add macro for SSEU stride calculation

Subslice stride and EU stride are calculated multiple times in i915_query. Move this calculation to a macro to reduce code duplication. v2: update headers in intel_sseu.h Cc: Daniele Ceraolo Spurio Signed-off-by: Stuart Summers --- drivers/gpu/drm/i915/gt/intel_sseu.h | 2 ++

[Intel-gfx] [PATCH 4/6] drm/i915: Move sseu helper functions to intel_sseu.h

v2: fix spacing from checkpatch warning Signed-off-by: Stuart Summers --- drivers/gpu/drm/i915/gt/intel_sseu.h | 47 drivers/gpu/drm/i915/intel_device_info.h | 47 2 files changed, 47 insertions(+), 47 deletions(-) diff --git

[Intel-gfx] ✗ Fi.CI.IGT: failure for i915: disable framebuffer compression on GeminiLake

== Series Details == Series: i915: disable framebuffer compression on GeminiLake URL : https://patchwork.freedesktop.org/series/60090/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6014_full -> Patchwork_12904_full Summary

Re: [Intel-gfx] [PATCH] drm/i915/icl: Fix setting 10 bit deep color mode

On Tue, Apr 30, 2019 at 06:05:18PM +0300, Ville Syrjälä wrote: > On Mon, Apr 29, 2019 at 05:00:28PM -0700, Aditya Swarup wrote: > > From: Ville Syrjälä > > > > There is a bug in hdmi_deep_color_possible() - we compare pipe_bpp > > <= 8*3 which returns true every time for hdmi_deep_color_possible

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/csr: alpha_support doesn't depend on csr or vice versa (rev2)

== Series Details == Series: drm/i915/csr: alpha_support doesn't depend on csr or vice versa (rev2) URL : https://patchwork.freedesktop.org/series/60062/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6014_full -> Patchwork_12903_full

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Enable pipe HDR mode on ICL if only HDR planes are used

On Tue, Apr 30, 2019 at 07:13:36PM +0530, Sharma, Shashank wrote: > > On 4/30/2019 4:09 PM, Ville Syrjälä wrote: > > On Tue, Apr 30, 2019 at 10:22:40AM +0530, Sharma, Shashank wrote: > >> On 4/26/2019 8:07 PM, Ville Syrjälä wrote: > >>> On Fri, Apr 26, 2019 at 06:40:11PM +0530, Sharma, Shashank

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix 90/270 degree rotated RGB565 src coord checks (rev2)

== Series Details == Series: drm/i915: Fix 90/270 degree rotated RGB565 src coord checks (rev2) URL : https://patchwork.freedesktop.org/series/59956/ State : success == Summary == CI Bug Log - changes from CI_DRM_6018 -> Patchwork_12916

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Fix 90/270 degree rotated RGB565 src coord checks (rev2)

== Series Details == Series: drm/i915: Fix 90/270 degree rotated RGB565 src coord checks (rev2) URL : https://patchwork.freedesktop.org/series/59956/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Fix 90/270 degree rotated RGB565 src coord

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix 90/270 degree rotated RGB565 src coord checks (rev2)

== Series Details == Series: drm/i915: Fix 90/270 degree rotated RGB565 src coord checks (rev2) URL : https://patchwork.freedesktop.org/series/59956/ State : warning == Summary == $ dim checkpatch origin/drm-tip 53aadb3c2bf5 drm/i915: Fix 90/270 degree rotated RGB565 src coord checks -:47:

Re: [Intel-gfx] [PATCH] dma-buf: add struct dma_buf_attach_info v2

On Tue, Apr 30, 2019 at 01:10:02PM +0200, Christian König wrote: > Add a structure for the parameters of dma_buf_attach, this makes it much > easier > to add new parameters later on. I don't understand this reasoning. What are the "new parameters" that are being proposed, and why do we need to

[Intel-gfx] [PATCH v2] drm/i915: Fix 90/270 degree rotated RGB565 src coord checks

From: Ville Syrjälä Supposedly both src coordinates have to even when doing 90/270 degree rotation with RGB565. This is definitely true for the X coordinate (we just get a black screen when it is odd). My experiments didn't show any misbehaviour with an odd Y coordinate, but let's trust the spec

Re: [Intel-gfx] [PATCH v2 6/6] drm/i915: Set DP min_bpp to 8*3 for non-RGB output formats

On Thu, Apr 11, 2019 at 08:33:08PM +, Sripada, Radhakrishna wrote: > On Thu, 2019-04-11 at 21:27 +0300, Ville Syrjälä wrote: > > On Tue, Apr 09, 2019 at 02:04:01PM -0700, Dhinakaran Pandiyan wrote: > > > On Tue, 2019-04-09 at 23:38 +0300, Ville Syrjälä wrote: > > > > On Tue, Apr 09, 2019 at

[Intel-gfx] ✓ Fi.CI.BAT: success for Enable Multi-segmented-gamma for ICL

== Series Details == Series: Enable Multi-segmented-gamma for ICL URL : https://patchwork.freedesktop.org/series/60126/ State : success == Summary == CI Bug Log - changes from CI_DRM_6018 -> Patchwork_12915 Summary --- **SUCCESS**

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/execlists: Flush the tasklet on parking

== Series Details == Series: series starting with [1/5] drm/i915/execlists: Flush the tasklet on parking URL : https://patchwork.freedesktop.org/series/60125/ State : success == Summary == CI Bug Log - changes from CI_DRM_6018 -> Patchwork_12914

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Drop the _INCOMPLETE for has_infoframe

== Series Details == Series: drm/i915: Drop the _INCOMPLETE for has_infoframe URL : https://patchwork.freedesktop.org/series/60120/ State : success == Summary == CI Bug Log - changes from CI_DRM_6018 -> Patchwork_12913 Summary ---

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable Multi-segmented-gamma for ICL

== Series Details == Series: Enable Multi-segmented-gamma for ICL URL : https://patchwork.freedesktop.org/series/60126/ State : warning == Summary == $ dim checkpatch origin/drm-tip dc4b88abc4e0 drm/i915: Change gamma/degamma_lut_size data type to u32 8811262cd9fa drm/i915/icl: Add register

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Add N & CTS values for 10/12 bit deep color

On 4/30/19 2:25 AM, Jani Nikula wrote: On Thu, 04 Apr 2019, Aditya Swarup wrote: On Tue, Apr 02, 2019 at 05:14:40AM -0700, Aditya Swarup wrote: Adding N & CTS values for 10/12 bit deep color from Appendix C table in HDMI 2.0 spec. The correct values for N is not chosen automatically by

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Don't skip audio enable if ELD is bogus

== Series Details == Series: series starting with [1/2] drm/i915: Don't skip audio enable if ELD is bogus URL : https://patchwork.freedesktop.org/series/60119/ State : success == Summary == CI Bug Log - changes from CI_DRM_6017 -> Patchwork_12912

Re: [Intel-gfx] [PATCH] dma-buf: add struct dma_buf_attach_info v2

linux/commits/Christian-K-nig/dma-buf-add-struct-dma_buf_attach_info-v2/20190430-221017 config: xtensa-allyesconfig (attached as .config) compiler: xtensa-linux-gcc (GCC) 8.1.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross

[Intel-gfx] [PATCH v2 4/4] drm/i915/icl: Add Multi-segmented gamma support

ICL introduces a new gamma correction mode in display engine, called multi-segmented-gamma mode. This mode allows users to program the darker region of the gamma curve with sueprfine precision. An example use case for this is HDR curves (like PQ ST-2084). If we plot a gamma correction curve from

[Intel-gfx] [PATCH v2 3/4] drm/i915: Rename ivb_load_lut_10_max

This patch renames function ivb_load_lut_10_max to ivb_load_lut_ext_max. Cc: Uma Shankar Suggested-by: Ville Syrjala Signed-off-by: Shashank Sharma --- drivers/gpu/drm/i915/intel_color.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git

[Intel-gfx] [PATCH v2 2/4] drm/i915/icl: Add register definitions for Multi Segmented gamma

From: Uma Shankar Add macros to define multi segmented gamma registers V2: Addressed Ville's comments: Add gen-lable before bit definition Addressed Jani's comment - Use REG_GENMASK() and REG_BIT() Cc: Ville Syrjälä Cc: Jani Nikula Cc: Maarten Lankhorst Signed-off-by:

[Intel-gfx] [PATCH v2 1/4] drm/i915: Change gamma/degamma_lut_size data type to u32

Currently, data type of gamma_lut_size & degamma_lut_size elements in intel_device_info is u16, which means it can accommodate maximum 64k values. In case of ICL multisegmented gamma, the size of gamma LUT is 256K. This patch changes the data type of both of these elements to u32. Cc: Ville

[Intel-gfx] [PATCH v2 0/4] Enable Multi-segmented-gamma for ICL

This patch series enables programming of Multi-segmented-gamma palette for ICL. Shashank Sharma (3): drm/i915: Change gamma/degamma_lut_size data type to u32 drm/i915: Rename ivb_load_lut_10_max drm/i915/icl: Add Multi-segmented gamma support Uma Shankar (1): drm/i915/icl: Add register

[Intel-gfx] [PATCH 1/5] drm/i915/execlists: Flush the tasklet on parking

Tidy up the cleanup sequence by always ensure that the tasklet is flushed on parking (before we cleanup). The parking provides a convenient point to ensure that the backend is truly idle. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_lrc.c | 25 +++--

[Intel-gfx] [PATCH 2/5] drm/i915: Leave engine parking to the engines

Drop the check in GEM parking that the engines were already parked. The intention here was that before we dropped the GT wakeref, we were sure that no more interrupts could be raised -- however, we have already dropped the wakeref by this point and the warning is no longer valid. Signed-off-by:

[Intel-gfx] [PATCH 3/5] drm/i915: Remove delay for idle_work

The original intent for the delay before running the idle_work was to provide a hysteresis to avoid ping-ponging the device runtime-pm. Since then we have also pulled in some memory management and general device management for parking. But with the inversion of the wakeref handling, GEM is no

[Intel-gfx] [PATCH 5/5] drm/i915: Stop spinning for DROP_IDLE (debugfs/i915_drop_caches)

If the user is racing a call to debugfs/i915_drop_caches with ongoing submission from another thread/process, we may never end up idling the GPU and be uninterruptibly spinning in debugfs/i915_drop_caches trying to catch an idle moment. Just flush the work once, that should be enough to park the

[Intel-gfx] [PATCH 4/5] drm/i915: Cancel retire_worker on parking

Replace the racy continuation check within retire_work with a definite kill-switch on idling. The race was being exposed by gem_concurrent_blit where the retire_worker would be terminated too early leaving us spinning in debugfs/i915_drop_caches with nothing flushing the retirement queue.

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: Don't skip audio enable if ELD is bogus

== Series Details == Series: series starting with [1/2] drm/i915: Don't skip audio enable if ELD is bogus URL : https://patchwork.freedesktop.org/series/60119/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Don't skip audio enable if ELD is

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Don't skip audio enable if ELD is bogus

== Series Details == Series: series starting with [1/2] drm/i915: Don't skip audio enable if ELD is bogus URL : https://patchwork.freedesktop.org/series/60119/ State : warning == Summary == $ dim checkpatch origin/drm-tip e685e5944a53 drm/i915: Don't skip audio enable if ELD is bogus

Re: [Intel-gfx] [PATCH] drm/i915/icl: Fix setting 10 bit deep color mode

On Mon, Apr 29, 2019 at 05:00:28PM -0700, Aditya Swarup wrote: > From: Ville Syrjälä > > There is a bug in hdmi_deep_color_possible() - we compare pipe_bpp > <= 8*3 which returns true every time for hdmi_deep_color_possible 12 bit > deep color mode test in intel_hdmi_compute_config().(Even when

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Corrupt DSI picture fix for GeminiLake (rev3)

== Series Details == Series: drm/i915: Corrupt DSI picture fix for GeminiLake (rev3) URL : https://patchwork.freedesktop.org/series/60084/ State : success == Summary == CI Bug Log - changes from CI_DRM_6017 -> Patchwork_12911 Summary

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Corrupt DSI picture fix for GeminiLake (rev3)

== Series Details == Series: drm/i915: Corrupt DSI picture fix for GeminiLake (rev3) URL : https://patchwork.freedesktop.org/series/60084/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Corrupt DSI picture fix for GeminiLake

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: add single combo phy init/unit functions

== Series Details == Series: drm/i915: add single combo phy init/unit functions URL : https://patchwork.freedesktop.org/series/60112/ State : success == Summary == CI Bug Log - changes from CI_DRM_6017 -> Patchwork_12910 Summary ---

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/icl: Fix setting 10 bit deep color mode

== Series Details == Series: drm/i915/icl: Fix setting 10 bit deep color mode URL : https://patchwork.freedesktop.org/series/60080/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6012_full -> Patchwork_12901_full Summary

[Intel-gfx] [PATCH] drm/i915: Drop the _INCOMPLETE for has_infoframe

From: Ville Syrjälä We have full infoframe readout now so we can replace the PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_infoframe) with the normal PIPE_CONF_CHECK_BOOL(has_infoframe). Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1

[Intel-gfx] [PATCH 1/2] drm/i915: Don't skip audio enable if ELD is bogus

From: Ville Syrjälä We've already committed to enabling audio when intel_audio_codec_enable() is called. We can't back out even if the ELD has turned sour in the meantime. So just spew some debug log and plow ahead. Otherwise the state checker gets unhappy when audio isn't enabled when it is

[Intel-gfx] [PATCH 2/2] drm/i915: hsw+ audio regs are per-transocder

From: Ville Syrjälä s/pipe/transcoder/ when dealing with hsw+ audio registers. This won't actually make any real difference since there is no audio on the EDP transcoder. But this should avoid a bit of confusion when cross checking against the spec. Signed-off-by: Ville Syrjälä ---

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Use mul_u32_u32() more (rev2)

== Series Details == Series: series starting with [1/2] drm/i915: Use mul_u32_u32() more (rev2) URL : https://patchwork.freedesktop.org/series/59180/ State : success == Summary == CI Bug Log - changes from CI_DRM_6017 -> Patchwork_12909

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Move sseu helper functions to intel_sseu.h

On Tue, 2019-04-30 at 12:02 +0300, Jani Nikula wrote: > On Mon, 29 Apr 2019, Stuart Summers wrote: > > Signed-off-by: Stuart Summers > > --- > > drivers/gpu/drm/i915/gt/intel_sseu.h | 47 > > > > drivers/gpu/drm/i915/intel_device_info.h | 47 > >

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Expand subslice mask

On Tue, 2019-04-30 at 12:03 +0300, Jani Nikula wrote: > On Mon, 29 Apr 2019, Stuart Summers wrote: > > Currently, the subslice_mask runtime parameter is stored as an > > array of subslices per slice. Expand the subslice mask array to > > better match what is presented to userspace through the > >

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: Use mul_u32_u32() more (rev2)

== Series Details == Series: series starting with [1/2] drm/i915: Use mul_u32_u32() more (rev2) URL : https://patchwork.freedesktop.org/series/59180/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Use mul_u32_u32() more

[Intel-gfx] ✓ Fi.CI.BAT: success for dma-buf: add struct dma_buf_attach_info v2

== Series Details == Series: dma-buf: add struct dma_buf_attach_info v2 URL : https://patchwork.freedesktop.org/series/60107/ State : success == Summary == CI Bug Log - changes from CI_DRM_6017 -> Patchwork_12908 Summary ---

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for dma-buf: add struct dma_buf_attach_info v2

== Series Details == Series: dma-buf: add struct dma_buf_attach_info v2 URL : https://patchwork.freedesktop.org/series/60107/ State : warning == Summary == $ dim checkpatch origin/drm-tip e090409de568 dma-buf: add struct dma_buf_attach_info v2 -:9: WARNING:COMMIT_LOG_LONG_LINE: Possible

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Wait for the struct_mutex on idling

== Series Details == Series: series starting with [1/2] drm/i915: Wait for the struct_mutex on idling URL : https://patchwork.freedesktop.org/series/60098/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6017 -> Patchwork_12907

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color (rev8)

== Series Details == Series: drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color (rev8) URL : https://patchwork.freedesktop.org/series/58912/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6012_full -> Patchwork_12900_full

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Enable pipe HDR mode on ICL if only HDR planes are used

On 4/30/2019 4:09 PM, Ville Syrjälä wrote: On Tue, Apr 30, 2019 at 10:22:40AM +0530, Sharma, Shashank wrote: On 4/26/2019 8:07 PM, Ville Syrjälä wrote: On Fri, Apr 26, 2019 at 06:40:11PM +0530, Sharma, Shashank wrote: On 4/13/2019 12:00 AM, Ville Syrjala wrote: From: Ville Syrjälä The

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] drm/i915: Wait for the struct_mutex on idling (rev2)

== Series Details == Series: series starting with [1/5] drm/i915: Wait for the struct_mutex on idling (rev2) URL : https://patchwork.freedesktop.org/series/60072/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6017 -> Patchwork_12906

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Cancel retire_worker on parking

On 30/04/2019 10:44, Chris Wilson wrote: Replace the racy continuation check within retire_work with a definite kill-switch on idling. The race was being exposed by gem_concurrent_blit where the retire_worker would be terminated too early leaving us spinning in debugfs/i915_drop_caches with

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915: Wait for the struct_mutex on idling (rev2)

== Series Details == Series: series starting with [1/5] drm/i915: Wait for the struct_mutex on idling (rev2) URL : https://patchwork.freedesktop.org/series/60072/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Wait for the struct_mutex on

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/3] drm/i915: Fix the pipe state timing mismatch warnings

== Series Details == Series: series starting with [v2,1/3] drm/i915: Fix the pipe state timing mismatch warnings URL : https://patchwork.freedesktop.org/series/60094/ State : failure == Summary == Applying: drm/i915: Fix the pipe state timing mismatch warnings Applying: drm/i915: Fix pipe

Re: [Intel-gfx] [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format

> -Original Message- > From: Nikula, Jani > Sent: Tuesday, April 30, 2019 6:16 PM > To: Kulkarni, Vandita ; intel- > g...@lists.freedesktop.org > Cc: Syrjala, Ville > Subject: Re: [Intel-gfx] [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, > output format > > On Tue, 30 Apr 2019,

[Intel-gfx] [PATCH v4] drm/i915: Corrupt DSI picture fix for GeminiLake

Currently due to regression CI machine displays show corrupt picture. Problem is when CDCLK is as low as 79200, picture gets unstable, while DSI and DE pll values were confirmed to be correct. Limiting to 158400 as agreed with Ville. We could not come up with any better solution yet, as PLL

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/icl: Factor out combo PHY lane power setup helper

On Tue, Apr 30, 2019 at 03:44:00PM +0300, Jani Nikula wrote: > On Thu, 25 Apr 2019, Imre Deak wrote: > > Factor out the combo PHY lane power configuration code to a separate > > helper; it will be also needed by the next patch adding the same > > configuration for DDI ports. > > > > Add support

Re: [Intel-gfx] [PATCH v3] drm/i915: Corrupt DSI picture fix for GeminiLake

On Tue, 30 Apr 2019, Stanislav Lisovskiy wrote: > Currently due to regression CI machine > displays show corrupt picture. > Problem is when CDCLK is as low as 79200, picture gets > unstable, while DSI and DE pll values were > confirmed to be correct. > Limiting to 158400 as agreed with Ville. > >

Re: [Intel-gfx] [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format

On Tue, 30 Apr 2019, "Kulkarni, Vandita" wrote: >> -Original Message- >> From: Nikula, Jani >> Sent: Tuesday, April 30, 2019 3:03 PM >> To: Kulkarni, Vandita ; intel- >> g...@lists.freedesktop.org >> Cc: Syrjala, Ville ; Shankar, Uma >> ; Kulkarni, Vandita >> Subject: Re: [v2 2/3]

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/icl: Factor out combo PHY lane power setup helper

On Thu, 25 Apr 2019, Imre Deak wrote: > Factor out the combo PHY lane power configuration code to a separate > helper; it will be also needed by the next patch adding the same > configuration for DDI ports. > > Add support for DDI ports and lane reversal as preparation for the next > patch. > >

Re: [Intel-gfx] [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format

> -Original Message- > From: Nikula, Jani > Sent: Tuesday, April 30, 2019 3:03 PM > To: Kulkarni, Vandita ; intel- > g...@lists.freedesktop.org > Cc: Syrjala, Ville ; Shankar, Uma > ; Kulkarni, Vandita > Subject: Re: [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output > format

[Intel-gfx] [PATCH] drm/i915: add single combo phy init/unit functions

Work on the principle that files should prefer not to expose platform specific functions. v2: Rebase Cc: Imre Deak Reviewed-by: Chris Wilson Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_combo_phy.c | 24 drivers/gpu/drm/i915/intel_combo_phy.h | 6

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Wait for the struct_mutex on idling

On 30/04/2019 10:44, Chris Wilson wrote: When the system is idling, contention for struct_mutex should be low and so we will be more efficient to wait for a contended mutex than reschedule. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_pm.c | 8 +--- 1 file changed, 1

Re: [Intel-gfx] [PATCH 00/21] drm/i915: the great header refactoring, part two

On Tue, 30 Apr 2019, Chris Wilson wrote: > Quoting Jani Nikula (2019-04-29 13:29:18) >> Continue the header refactoring started in part one [1]. >> >> BR, >> Jani. >> >> [1] https://patchwork.freedesktop.org/series/59022/ >> >> >> Jani Nikula (21): >> drm/i915: ensure more headers remain

[Intel-gfx] [PATCH v3] drm/i915: Corrupt DSI picture fix for GeminiLake

Currently due to regression CI machine displays show corrupt picture. Problem is when CDCLK is as low as 79200, picture gets unstable, while DSI and DE pll values were confirmed to be correct. Limiting to 158400 as agreed with Ville. We could not come up with any better solution yet, as PLL

[Intel-gfx] ✓ Fi.CI.BAT: success for i915: disable framebuffer compression on GeminiLake

== Series Details == Series: i915: disable framebuffer compression on GeminiLake URL : https://patchwork.freedesktop.org/series/60090/ State : success == Summary == CI Bug Log - changes from CI_DRM_6014 -> Patchwork_12904 Summary ---

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/csr: alpha_support doesn't depend on csr or vice versa (rev2)

== Series Details == Series: drm/i915/csr: alpha_support doesn't depend on csr or vice versa (rev2) URL : https://patchwork.freedesktop.org/series/60062/ State : success == Summary == CI Bug Log - changes from CI_DRM_6014 -> Patchwork_12903

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/5] drm/i915: Wait for the struct_mutex on idling

== Series Details == Series: series starting with [1/5] drm/i915: Wait for the struct_mutex on idling URL : https://patchwork.freedesktop.org/series/60072/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6012_full -> Patchwork_12899_full

[Intel-gfx] [PATCH] dma-buf: add struct dma_buf_attach_info v2

Add a structure for the parameters of dma_buf_attach, this makes it much easier to add new parameters later on. v2: rebase cleanup and fix all new implementations as well Signed-off-by: Christian König --- drivers/dma-buf/dma-buf.c | 13 +++--

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Corrupt DSI picture fix for GeminiLake

== Series Details == Series: drm/i915: Corrupt DSI picture fix for GeminiLake URL : https://patchwork.freedesktop.org/series/60084/ State : success == Summary == CI Bug Log - changes from CI_DRM_6014 -> Patchwork_12902 Summary ---

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Enable pipe HDR mode on ICL if only HDR planes are used

On Tue, Apr 30, 2019 at 10:22:40AM +0530, Sharma, Shashank wrote: > > On 4/26/2019 8:07 PM, Ville Syrjälä wrote: > > On Fri, Apr 26, 2019 at 06:40:11PM +0530, Sharma, Shashank wrote: > >> On 4/13/2019 12:00 AM, Ville Syrjala wrote: > >>> From: Ville Syrjälä > >>> > >>> The pipe has a special HDR

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Corrupt DSI picture fix for GeminiLake

== Series Details == Series: drm/i915: Corrupt DSI picture fix for GeminiLake URL : https://patchwork.freedesktop.org/series/60084/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Corrupt DSI picture fix for GeminiLake

Re: [Intel-gfx] [PATCH v2] drm/i915: Corrupt DSI picture fix for GeminiLake

HI, > -Original Message- > From: Lisovskiy, Stanislav > Sent: tiistai 30. huhtikuuta 2019 11.01 > To: intel-gfx@lists.freedesktop.org; jani.nik...@linux.intel.com > Cc: Saarinen, Jani ; Peres, Martin > > Subject: Re: [Intel-gfx] [PATCH v2] drm/i915: Corrupt DSI picture fix for >

Re: [Intel-gfx] [PATCH 00/21] drm/i915: the great header refactoring, part two

Quoting Jani Nikula (2019-04-29 13:29:18) > Continue the header refactoring started in part one [1]. > > BR, > Jani. > > [1] https://patchwork.freedesktop.org/series/59022/ > > > Jani Nikula (21): > drm/i915: ensure more headers remain self-contained > drm/i915: make intel_bios.h

Re: [Intel-gfx] [PATCH 19/21] drm/i915: move some leftovers to intel_pm.h from i915_drv.h

Quoting Joonas Lahtinen (2019-04-30 08:24:07) > Quoting Jani Nikula (2019-04-29 16:03:33) > > On Mon, 29 Apr 2019, Chris Wilson wrote: > > > Quoting Jani Nikula (2019-04-29 13:29:37) > > >> Commit 696173b064c6 ("drm/i915: extract intel_pm.h from intel_drv.h") > > >> missed the declarations in

[Intel-gfx] [PATCH 1/2] drm/i915: Wait for the struct_mutex on idling

When the system is idling, contention for struct_mutex should be low and so we will be more efficient to wait for a contended mutex than reschedule. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_pm.c | 8 +--- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git

[Intel-gfx] [PATCH 2/2] drm/i915: Cancel retire_worker on parking

Replace the racy continuation check within retire_work with a definite kill-switch on idling. The race was being exposed by gem_concurrent_blit where the retire_worker would be terminated too early leaving us spinning in debugfs/i915_drop_caches with nothing flushing the retirement queue.

[Intel-gfx] [PATCH v2] drm/i915: Only reschedule the submission tasklet if preemption is possible

If we couple the scheduler more tightly with the execlists policy, we can apply the preemption policy to the question of whether we need to kick the tasklet at all for this priority bump. v2: Rephrase it as a core i915 policy and not an execlists foible. Signed-off-by: Chris Wilson Cc: Tvrtko

Re: [Intel-gfx] [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format

On Tue, 30 Apr 2019, Vandita Kulkarni wrote: > Read back the pixel fomrat register and get the bpp. > > v2: Read the PIPE_MISC register (Jani). > > Signed-off-by: Vandita Kulkarni > --- > drivers/gpu/drm/i915/icl_dsi.c | 3 +++ > drivers/gpu/drm/i915/intel_dsi.h | 1 + >

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Add N & CTS values for 10/12 bit deep color

On Thu, 04 Apr 2019, Aditya Swarup wrote: > On Tue, Apr 02, 2019 at 05:14:40AM -0700, Aditya Swarup wrote: >> Adding N & CTS values for 10/12 bit deep color from Appendix C >> table in HDMI 2.0 spec. The correct values for N is not chosen >> automatically by hardware for deep color modes. >> >>

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Enable pipe HDR mode on ICL if only HDR planes are used

>-Original Message- >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of >Ville >Syrjälä >Sent: Friday, April 26, 2019 8:07 PM >To: Sharma, Shashank >Cc: intel-gfx@lists.freedesktop.org >Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915: Enable pipe HDR mode on

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Disable semaphore busywaits on saturated systems

Quoting Tvrtko Ursulin (2019-04-30 09:55:59) > > On 29/04/2019 19:00, Chris Wilson wrote: > So I am still leaning towards being cautious and just abandoning > semaphores for now. Fwiw, we have another 4 weeks to pull the plug for 5.2. -Chris ___

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Disable semaphore busywaits on saturated systems

Quoting Tvrtko Ursulin (2019-04-30 09:55:59) > > On 29/04/2019 19:00, Chris Wilson wrote: > > Asking the GPU to busywait on a memory address, perhaps not unexpectedly > > in hindsight for a shared system, leads to bus contention that affects > > CPU programs trying to concurrently access memory.

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Expand subslice mask

On Mon, 29 Apr 2019, Stuart Summers wrote: > Currently, the subslice_mask runtime parameter is stored as an > array of subslices per slice. Expand the subslice mask array to > better match what is presented to userspace through the > I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is >

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Move sseu helper functions to intel_sseu.h

On Mon, 29 Apr 2019, Stuart Summers wrote: > Signed-off-by: Stuart Summers > --- > drivers/gpu/drm/i915/gt/intel_sseu.h | 47 > drivers/gpu/drm/i915/intel_device_info.h | 47 > 2 files changed, 47 insertions(+), 47 deletions(-) > > diff

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Disable semaphore busywaits on saturated systems

On 29/04/2019 19:00, Chris Wilson wrote: Asking the GPU to busywait on a memory address, perhaps not unexpectedly in hindsight for a shared system, leads to bus contention that affects CPU programs trying to concurrently access memory. This can manifest as a drop in transcode throughput on

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Use local variable for SSEU info in GETPARAM ioctl

On Mon, 29 Apr 2019, Stuart Summers wrote: > In the GETPARAM ioctl handler, use a local variable to consolidate > usage of SSEU runtime info. > > Cc: Daniele Ceraolo Spurio > Signed-off-by: Stuart Summers > --- > drivers/gpu/drm/i915/i915_drv.c | 11 ++- > 1 file changed, 6

Re: [Intel-gfx] [PATCH 2/3] drm/i915/icl: Add register definitions for Multi Segmented gamma

On 4/29/2019 7:42 PM, Jani Nikula wrote: On Fri, 26 Apr 2019, Shashank Sharma wrote: From: Uma Shankar Add macros to define multi segmented gamma registers Cc: Ville Syrjälä Cc: Maarten Lankhorst Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_reg.h | 17 + 1

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