On Fri, May 17, 2019 at 5:35 PM Chris Wilson wrote:
>
> Quoting Jani Nikula (2019-05-16 20:48:16)
> > diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
> > index 8a1f64f17740..c2839de06485 100644
> > --- a/scripts/Makefile.lib
> > +++ b/scripts/Makefile.lib
> > @@ -66,6 +66,9 @@ extra-y +=
On Fri, May 17, 2019 at 4:48 AM Jani Nikula wrote:
>
> Sometimes it's useful to be able to explicitly ensure certain headers
> remain self-contained, i.e. that they are compilable as standalone
> units, by including and/or forward declaring everything they depend on.
>
> Add special target
== Series Details ==
Series: Extend BT2020 support in iCSC and fixes (rev3)
URL : https://patchwork.freedesktop.org/series/60480/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6096_full -> Patchwork_13033_full
Summary
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer (rev14)
URL : https://patchwork.freedesktop.org/series/25091/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6096_full -> Patchwork_13032_full
== Series Details ==
Series: drm/i915: Tolerate file owned GEM contexts on hot unbind
URL : https://patchwork.freedesktop.org/series/60782/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6095_full -> Patchwork_13031_full
== Series Details ==
Series: drm/i915/huc: Don't try to check HuC status if it's not loaded
URL : https://patchwork.freedesktop.org/series/60807/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6097 -> Patchwork_13037
On Fri, 17 May 2019 23:52:37 +0200, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2019-05-17 22:40:28)
If we never attempted to load HuC firmware, or we already wedged
or reset GuC/HuC, then there is no reason to wake up the device
to check one bit in the register that will be for sure
The patch looks fine to me.
On Thu, May 16, 2019 at 10:41:56PM +0530, Anshuman Gupta wrote:
> This reverts commit 99b69db57544ec7ed427607f1a2a1858a7d43b61
> Core-for-CI:ICL_only Disable ACPI idle driver.
>
> This hack has been provided considering the Bug assessment
> that ACPI idle driver page
Quoting Michal Wajdeczko (2019-05-17 22:40:28)
> If we never attempted to load HuC firmware, or we already wedged
> or reset GuC/HuC, then there is no reason to wake up the device
> to check one bit in the register that will be for sure cleared.
>
> Suggested-by: Chris Wilson
> Signed-off-by:
If we never attempted to load HuC firmware, or we already wedged
or reset GuC/HuC, then there is no reason to wake up the device
to check one bit in the register that will be for sure cleared.
Suggested-by: Chris Wilson
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Tony Ye
---
Nit: Commit message V4 and Patch Subject V3
Acked-by: Clint Taylor
-Clint
On 5/3/19 12:08 PM, Ville Syrjala wrote:
From: Ville Syrjälä
ICL has so many planes that it can easily exceed the maximum
effective memory bandwidth of the system. We must therefore check
that we don't exceed that
On Fri, 17 May 2019 22:08:56 +0200, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2019-05-17 19:01:06)
On Fri, 17 May 2019 19:14:01 +0200, Chris Wilson
wrote:
> Quoting Michal Wajdeczko (2019-05-17 18:11:07)
>> On Fri, 17 May 2019 18:31:31 +0200, Chris Wilson
>> wrote:
>>
>> > Quoting
== Series Details ==
Series: series starting with [01/14] drm/i915: Pass intel_atomic_state to cdclk
funcs
URL : https://patchwork.freedesktop.org/series/60803/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6096 -> Patchwork_13036
Quoting Michal Wajdeczko (2019-05-17 19:01:06)
> On Fri, 17 May 2019 19:14:01 +0200, Chris Wilson
> wrote:
>
> > Quoting Michal Wajdeczko (2019-05-17 18:11:07)
> >> On Fri, 17 May 2019 18:31:31 +0200, Chris Wilson
> >> wrote:
> >>
> >> > Quoting Michal Wajdeczko (2019-05-17 17:22:25)
> >> >>
== Series Details ==
Series: series starting with [01/14] drm/i915: Pass intel_atomic_state to cdclk
funcs
URL : https://patchwork.freedesktop.org/series/60803/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Pass intel_atomic_state to cdclk
Quoting Tvrtko Ursulin (2019-05-17 12:25:26)
> From: Tvrtko Ursulin
>
> On Icelake second vcs engine is vcs2 instead of vcs1 so add some logical
> to physical instance remapping based on engine discovery to support it.
>
> Signed-off-by: Tvrtko Ursulin
It does the trick for now, but still
Quoting Tvrtko Ursulin (2019-05-17 12:51:06)
>
> On 17/05/2019 12:39, Andi Shyti wrote:
> > Hi Tvrtko,
> >
> >> +static int
> >> +__i915_query(int i915, struct drm_i915_query *q)
> >> +{
> >> +if (igt_ioctl(i915, DRM_IOCTL_I915_QUERY, q))
> >> +return -errno;
> >> +return 0;
Quoting Tvrtko Ursulin (2019-05-17 12:25:22)
> From: Tvrtko Ursulin
>
> To allow exercising the SSEU configuration in combination with Virtual
> Engine, allow RCS to be specified in the engine map and use appropriate
> index based addressing when applying SSEU configuration to it.
Heh, I
Quoting Tvrtko Ursulin (2019-05-17 12:25:21)
> From: Tvrtko Ursulin
>
> A new workload command ('S') is added which allows per context slice
> (re-)configuration.
>
> v2:
> * Only query device SSEU on first use. (Chris)
>
> Signed-off-by: Tvrtko Ursulin
Fair enough,
Reviewed-by: Chris
Quoting Tvrtko Ursulin (2019-05-17 12:25:20)
> From: Tvrtko Ursulin
>
> A new command line switch ('-s') is added which toggles the low slice
> count mode for workloads following on the command line.
>
> This enables easy benchmarking of the effect of running the existing media
> workloads in
Quoting Tvrtko Ursulin (2019-05-17 12:25:17)
> From: Tvrtko Ursulin
>
> Engine bonds are an i915 uAPI applicable to load balanced contexts with
> engine map. They allow expression rules of engine selection between two
> contexts when submissions are also tied with submit fences.
>
> Please
== Series Details ==
Series: series starting with [1/3] drm/i915/gvt: Set return value for
ppgtt_populate error path
URL : https://patchwork.freedesktop.org/series/60769/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6093_full -> Patchwork_13030_full
Quoting Tvrtko Ursulin (2019-05-17 12:25:16)
> From: Tvrtko Ursulin
>
> A new workload command for enabling a load balanced context map (aka
> Virtual Engine). Example usage:
>
> B.1
>
> This turns on load balancing for context one, assuming it has already been
> configured with an engine
Quoting Tvrtko Ursulin (2019-05-17 12:25:13)
> From: Tvrtko Ursulin
>
> Support new i915 uAPI for configuring contexts with engine maps.
>
> Please refer to the README file for more detailed explanation.
>
> v2:
> * Allow defining engine maps by class.
>
> Signed-off-by: Tvrtko Ursulin
>
From: Ville Syrjälä
Constify a bunch of the arguments of various state dumping
functions. Makes it clear they don't mutate the states.
And fix up some indent fails while at it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 20 +++-
From: Ville Syrjälä
Stop dumping plane->state for planes. That is the old state most of the
time and dumping stale information only serves to confuse people.
Instead dump the new state just for the planes included in the
operation. For now we'll include only the planes for the modeset/fastset
From: Ville Syrjälä
Switch to using intel_ types instead of drm_ types. Avoids
ugly casts and nasty aliasing variables with different types.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 66 +---
1 file changed, 31 insertions(+), 35
From: Ville Syrjälä
Currently we're only dumping the failed crtc state if
intel_modeset_pipe_config() fails. Let's do the state
dump if anything else fails afterwards. The downside
is that we lose the immediate knowledge which crtc caused
the failure (unless a lower level function indicates it
From: Ville Syrjälä
Currently we're not dumping out whether the crtc is actually
active or in dpms off state. Let's include that in the dumps.
And while at it compress out a few lines from the state dump.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 13 +
From: Ville Syrjälä
We already pass the crtc's state to intel_modeset_pipe_config()
so passing the crtc as well is redundant.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
From: Ville Syrjälä
Pass around intel_atomic_state rather than drm_atomic_state.
This avoids some extra casts and annoing aliasing variables.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 23 +++
1 file changed, 11 insertions(+), 12 deletions(-)
From: Ville Syrjälä
Pass around intel_atomic_state rather than drm_atomic_state.
This avoids some extra casts and annoing aliasing variables.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git
From: Ville Syrjälä
Pass around intel_atomic_state rather than drm_atomic_state.
This avoids some extra casts and annoing aliasing variables.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_cdclk.c | 167 ---
From: Ville Syrjälä
Currently we're dumping the crtc states before they have
been fully calculated. Move the dumping to the end of
.atomic_check() so we get a fully up to date dump.
Let's also do the dump for fully disabled pipes, but we'll
limit that to just saying that the pipe is disabled
From: Ville Syrjälä
Thanks to using the short names for platoforms all the cdclk
vfunc assignemtns now fit within 80 cols. Remove the extra
line wraps.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_cdclk.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
From: Ville Syrjälä
Switch to using intel_ types instead of drm_ types. Avoids
ugly casts and nasty aliasing variables with different types.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 77 ++--
1 file changed, 38 insertions(+), 39
From: Ville Syrjälä
Pass around intel_atomic_state rather than drm_atomic_state.
This avoids some extra casts and annoing aliasing variables.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 40 +---
1 file changed, 18 insertions(+), 22
From: Ville Syrjälä
We already pass the crtc's state to intel_dump_pipe_config()
so passing the crtc as well is redundant.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git
Quoting Tvrtko Ursulin (2019-05-17 12:25:06)
> From: Tvrtko Ursulin
>
> Use the 'completed?' tracepoint field to detect more robustly when a
> request has been preempted and remove it from the engine database if so.
>
> Otherwise the script can hit a scenario where the same global seqno will
>
Quoting Tvrtko Ursulin (2019-05-17 12:25:05)
> From: Tvrtko Ursulin
>
> Add virtual/queue timelines to both stdout and HTML output.
>
> A new timeline is created for each queue/virtual engine to display
> associated requests in queued and runnable states. Once requests are
> submitted to a real
Quoting Tvrtko Ursulin (2019-05-17 12:25:03)
> From: Tvrtko Ursulin
>
> gem_wsim uses the sw_fence timeline and confuses the script.
sw_sync
How does this fare with clflush fences (which are .driver="i915") and
all of the future .driver="i915" fences?
Looks like we are still prone to hitting
Quoting Michal Wajdeczko (2019-05-17 17:22:23)
> We should not attempt to unwind GuC hardware/firmware setup
> if we already have sanitized GuC.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Chris Wilson
> Cc: Daniele Ceraolo Spurio
> ---
> drivers/gpu/drm/i915/intel_uc.c | 3 +++
> 1 file
Quoting Michal Wajdeczko (2019-05-17 19:01:06)
> On Fri, 17 May 2019 19:14:01 +0200, Chris Wilson
> wrote:
>
> > Quoting Michal Wajdeczko (2019-05-17 18:11:07)
> >> On Fri, 17 May 2019 18:31:31 +0200, Chris Wilson
> >> wrote:
> >>
> >> > Quoting Michal Wajdeczko (2019-05-17 17:22:25)
> >> >>
On Mon, May 13, 2019 at 05:13:10PM +0300, Ville Syrjälä wrote:
> On Fri, May 10, 2019 at 05:42:09PM -0700, Matt Roper wrote:
> > On Fri, May 03, 2019 at 10:08:31PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > ICL has so many planes that it can easily exceed the maximum
> > >
On Fri, 17 May 2019 19:14:01 +0200, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2019-05-17 18:11:07)
On Fri, 17 May 2019 18:31:31 +0200, Chris Wilson
wrote:
> Quoting Michal Wajdeczko (2019-05-17 17:22:25)
>> We may skip reset preparation steps if GuC is already sanitized.
>>
>>
== Series Details ==
Series: drm/i915: added i2c symlink to hdmi connector
URL : https://patchwork.freedesktop.org/series/60794/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6096 -> Patchwork_13034
Summary
---
Quoting Michal Wajdeczko (2019-05-17 18:11:07)
> On Fri, 17 May 2019 18:31:31 +0200, Chris Wilson
> wrote:
>
> > Quoting Michal Wajdeczko (2019-05-17 17:22:25)
> >> We may skip reset preparation steps if GuC is already sanitized.
> >>
> >> Signed-off-by: Michal Wajdeczko
> >> Cc: Chris Wilson
Quoting Michal Wajdeczko (2019-05-17 17:54:53)
> On Fri, 17 May 2019 18:27:44 +0200, Chris Wilson
> wrote:
>
> > Quoting Michal Wajdeczko (2019-05-17 17:22:27)
> >> When we reset engines using ALL_ENGINES mask, we will do
> >> full GPU reset and GuC will be also affected. Let GuC be
> >>
On Fri, 17 May 2019 18:31:31 +0200, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2019-05-17 17:22:25)
We may skip reset preparation steps if GuC is already sanitized.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_uc.c | 3
== Series Details ==
Series: Extend BT2020 support in iCSC and fixes (rev3)
URL : https://patchwork.freedesktop.org/series/60480/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6096 -> Patchwork_13033
Summary
---
Quoting Michal Wajdeczko (2019-05-17 17:54:53)
> On Fri, 17 May 2019 18:27:44 +0200, Chris Wilson
> wrote:
>
> > Quoting Michal Wajdeczko (2019-05-17 17:22:27)
> >> When we reset engines using ALL_ENGINES mask, we will do
> >> full GPU reset and GuC will be also affected. Let GuC be
> >>
On Fri, 17 May 2019 18:30:40 +0200, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2019-05-17 17:22:24)
Knowing that GuC will be reset soon, we may stop all communication
immediately without doing graceful cleanup as it is not needed.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc:
On Fri, May 17, 2019 at 09:44:46AM -0700, Rodrigo Vivi wrote:
> On Fri, May 17, 2019 at 07:34:23PM +0300, Ville Syrjälä wrote:
> > On Fri, May 17, 2019 at 09:17:39AM -0700, Rodrigo Vivi wrote:
> > > On Thu, May 16, 2019 at 03:49:19PM +, Summers, Stuart wrote:
> > > > On Thu, 2019-05-16 at
Quoting Michal Wajdeczko (2019-05-17 17:54:53)
> On Fri, 17 May 2019 18:27:44 +0200, Chris Wilson
> wrote:
>
> > Quoting Michal Wajdeczko (2019-05-17 17:22:27)
> >> When we reset engines using ALL_ENGINES mask, we will do
> >> full GPU reset and GuC will be also affected. Let GuC be
> >>
On Fri, 17 May 2019 18:27:44 +0200, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2019-05-17 17:22:27)
When we reset engines using ALL_ENGINES mask, we will do
full GPU reset and GuC will be also affected. Let GuC be
prepared for upcoming reset.
Signed-off-by: Michal Wajdeczko
Cc: Chris
On Fri, May 17, 2019 at 07:34:23PM +0300, Ville Syrjälä wrote:
> On Fri, May 17, 2019 at 09:17:39AM -0700, Rodrigo Vivi wrote:
> > On Thu, May 16, 2019 at 03:49:19PM +, Summers, Stuart wrote:
> > > On Thu, 2019-05-16 at 18:42 +0300, Jani Nikula wrote:
> > > > On Thu, 16 May 2019, "Summers,
On Fri, May 17, 2019 at 07:21:09PM +0300, Oleg Vasilev wrote:
> Currently, the i2c adapter was available only under DP connectors.
>
> This patch adds i2c adapter symlink to hdmi connector in order to make
> this behaviour consistent.
>
> The initial motivation of this patch was to make igt i2c
Quoting Michal Wajdeczko (2019-05-17 17:22:26)
> +void intel_guc_submission_stop(struct intel_guc *guc)
> +{
> + struct drm_i915_private *i915 = guc_to_i915(guc);
> +
> + GEM_BUG_ON(i915->gt.awake); /* GT should be parked first */
How is this true for reset? Note, it's an unlocked
On Fri, May 17, 2019 at 09:17:39AM -0700, Rodrigo Vivi wrote:
> On Thu, May 16, 2019 at 03:49:19PM +, Summers, Stuart wrote:
> > On Thu, 2019-05-16 at 18:42 +0300, Jani Nikula wrote:
> > > On Thu, 16 May 2019, "Summers, Stuart"
> > > wrote:
> > > > On Thu, 2019-05-16 at 12:59 +0300, Jani
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer (rev14)
URL : https://patchwork.freedesktop.org/series/25091/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6096 -> Patchwork_13032
Summary
Quoting Michal Wajdeczko (2019-05-17 17:22:25)
> We may skip reset preparation steps if GuC is already sanitized.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Chris Wilson
> Cc: Daniele Ceraolo Spurio
> ---
> drivers/gpu/drm/i915/intel_uc.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff
Quoting Michal Wajdeczko (2019-05-17 17:22:24)
> Knowing that GuC will be reset soon, we may stop all communication
> immediately without doing graceful cleanup as it is not needed.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Chris Wilson
> Cc: Daniele Ceraolo Spurio
> ---
>
Quoting Michal Wajdeczko (2019-05-17 17:22:27)
> When we reset engines using ALL_ENGINES mask, we will do
> full GPU reset and GuC will be also affected. Let GuC be
> prepared for upcoming reset.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Chris Wilson
> Cc: Daniele Ceraolo Spurio
> ---
>
We should not attempt to unwind GuC hardware/firmware setup
if we already have sanitized GuC.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_uc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uc.c
Misc GuC fixes for upcoming 32.0.3
Michal Wajdeczko (7):
drm/i915/uc: Use GuC firmware status helper
drm/i915/uc: Explicitly sanitize GuC/HuC on failure and finish
drm/i915/uc: Skip GuC HW unwinding if GuC is already dead
drm/i915/uc: Stop talking with GuC when resetting
drm/i915/uc:
We already have helper function for checking GuC firmware
load status. Replace existing open-coded checks.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_uc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
Knowing that GuC will be reset soon, we may stop all communication
immediately without doing graceful cleanup as it is not needed.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_ct.h | 5 +
drivers/gpu/drm/i915/intel_uc.c
Explicitly sanitize GuC/HuC on load failure and when we finish
using them to make sure our fw state tracking is always correct.
While around, use new helper in uc_reset_prepare.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_uc.c |
Knowing that GuC will be reset soon, perform only minimal
cleanup actions (ie. doorbells) without talking with GuC.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_submission.c | 25 +
We may skip reset preparation steps if GuC is already sanitized.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_uc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uc.c
When we reset engines using ALL_ENGINES mask, we will do
full GPU reset and GuC will be also affected. Let GuC be
prepared for upcoming reset.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_reset.c | 4
1 file changed, 4
Currently, the i2c adapter was available only under DP connectors.
This patch adds i2c adapter symlink to hdmi connector in order to make
this behaviour consistent.
The initial motivation of this patch was to make igt i2c subtest
patch [1] work on all connectors.
[1]:
On Thu, May 16, 2019 at 03:49:19PM +, Summers, Stuart wrote:
> On Thu, 2019-05-16 at 18:42 +0300, Jani Nikula wrote:
> > On Thu, 16 May 2019, "Summers, Stuart"
> > wrote:
> > > On Thu, 2019-05-16 at 12:59 +0300, Jani Nikula wrote:
> > > > On Tue, 14 May 2019, Rodrigo Vivi wrote:
> > > > >
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer (rev14)
URL : https://patchwork.freedesktop.org/series/25091/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7c0463e5827f drm: Add HDR source metadata property
-:62: CHECK:PARENTHESIS_ALIGNMENT:
Input CSC Co-efficients for BT601 and BT709 YCbCR to RGB
conversion were slightly off. Fixed the same.
v2: Fixed the co-eficients as there was issue with reference
matrix, spotted by Ville.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_sprite.c | 24
1 file
Fixed Y Pre-offset in case of Full Range YCbCr.
Reviewed-by: Ville Syrjälä
Suggested-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_sprite.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
Currently input csc for YCbCR to RGB conversion handles only
BT601 and Bt709. Extending it to support BT2020 as well.
v2: Fixed the co-efficients for LR to FR conversion,
as suggested by Ville.
v3: Fixed Y Pre-offset in case of Full Range YCbCr as suggested
by Ville.
v4: Split the v2 and v3
This series adds support for BT2020 YCbCr to RGB conversion
using input CSC. This also fixes issues with BT601 and BT709
coefficients.
v2: Fixed Ville's review comments.
v3: Rebase.
Uma Shankar (3):
drm/i915/icl: Handle YCbCr to RGB conversion for BT2020 case
drm/i915/icl: Fix Y pre-offset
From: Ville Syrjälä
This patch enables infoframes on GLK+ to be
used to send HDR metadata to HDMI sink.
v2: Addressed Shashank's review comment.
v3: Addressed Shashank's review comment.
v4: Added Shashank's RB.
v5: Dropped hdr_metadata_change check while modeset, as per
Ville's suggestion.
Enable writing of HDR metadata infoframe to panel.
The data will be provid by usersapace compositors, based
on blending policies and passsed to driver through a blob
property.
v2: Rebase
v3: Fixed a warning message
v4: Addressed Shashank's review comments
v5: Rebase. Added infoframe
Attach HDR metadata property to connector object.
v2: Rebase
v3: Updated the property name as per updated name
while creating hdr metadata property
v4: Added platform check as suggested by Ville.
Signed-off-by: Uma Shankar
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/i915/intel_hdmi.c |
Quoting Daniele Ceraolo Spurio (2019-05-17 16:27:26)
>
>
> On 5/16/19 3:42 PM, Chris Wilson wrote:
> > Quoting Chris Wilson (2019-05-16 23:10:10)
> >> Quoting Chris Wilson (2019-05-16 23:07:43)
> >>> Quoting Daniele Ceraolo Spurio (2019-05-16 22:56:31)
> diff --git
On 5/16/19 3:42 PM, Chris Wilson wrote:
Quoting Chris Wilson (2019-05-16 23:10:10)
Quoting Chris Wilson (2019-05-16 23:07:43)
Quoting Daniele Ceraolo Spurio (2019-05-16 22:56:31)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.h
b/drivers/gpu/drm/i915/intel_runtime_pm.h
index
On 15/05/2019 14:00, Chris Wilson wrote:
The handling of the no-preemption priority level imposes the restriction
that we need to maintain the implied ordering even though preemption is
disabled. Otherwise we may end up with an AB-BA deadlock across multiple
engine due to a real preemption
== Series Details ==
Series: drm/i915: Tolerate file owned GEM contexts on hot unbind
URL : https://patchwork.freedesktop.org/series/60782/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6095 -> Patchwork_13031
Summary
Quoting Janusz Krzysztofik (2019-05-17 15:06:17)
> From: Janusz Krzysztofik
>
> During i915_driver_unload(), GEM contexts are verified restrictively
> inside i915_gem_fini() if they don't consume shared resources which
> should be cleaned up before the driver is released. If those checks
>
On 15/05/2019 14:00, Chris Wilson wrote:
With the disappearance of NEWCLIENT, we no longer need to provide the
priority boost on preemption in order to prevent repeated gazumping,
and we can remove the dead code.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
On 17/05/2019 14:30, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-05-17 13:55:48)
On 15/05/2019 14:00, Chris Wilson wrote:
Commit 1413b2bc0717 ("drm/i915: Trim NEWCLIENT boosting") had the
intended consequence of not allowing a sequence of work that merely
crossed into a new engine the
On Thu, May 16, 2019 at 07:40:10PM +0530, Uma Shankar wrote:
> Attach HDR metadata property to connector object.
>
> v2: Rebase
>
> v3: Updated the property name as per updated name
> while creating hdr metadata property
>
> Signed-off-by: Uma Shankar
> Reviewed-by: Shashank Sharma
> ---
>
From: Janusz Krzysztofik
During i915_driver_unload(), GEM contexts are verified restrictively
inside i915_gem_fini() if they don't consume shared resources which
should be cleaned up before the driver is released. If those checks
don't result in kernel panic, one more check is performed at the
On Thu, May 16, 2019 at 07:40:11PM +0530, Uma Shankar wrote:
> Enable writing of HDR metadata infoframe to panel.
> The data will be provid by usersapace compositors, based
> on blending policies and passsed to driver through a blob
> property.
>
> v2: Rebase
>
> v3: Fixed a warning message
>
>
On Thu, May 16, 2019 at 07:40:13PM +0530, Uma Shankar wrote:
> From: Ville Syrjälä
>
> This patch enables infoframes on GLK+ to be
> used to send HDR metadata to HDMI sink.
>
> v2: Addressed Shashank's review comment.
>
> v3: Addressed Shashank's review comment.
>
> v4: Added Shashank's RB.
>
From: Ville Syrjälä
Probe the GAMMA_LUT/GAMMA_LUT_SIZE props and utilize them when
the running with > 8bpc.
v2: s/sna_crtc_id/__sna_crtc_id/ in DBG since we have a sna_crtc
v3: Fix the vg "bluered" typo (Mario)
This time I even build tested with vg support
Cc: Mario Kleiner
Signed-off-by:
On Thu, May 16, 2019 at 09:54:55PM +0200, Mario Kleiner wrote:
> On Fri, Apr 26, 2019 at 6:32 PM Ville Syrjala
> wrote:
> >
> > From: Ville Syrjälä
> >
> > Probe the GAMMA_LUT/GAMMA_LUT_SIZE props and utilize them when
> > the running with > 8bpc.
> >
> > v2: s/sna_crtc_id/__sna_crtc_id/ in DBG
== Series Details ==
Series: series starting with [1/3] drm/i915/gvt: Set return value for
ppgtt_populate error path
URL : https://patchwork.freedesktop.org/series/60769/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6093 -> Patchwork_13030
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, May 17, 2019 6:54 PM
>To: Shankar, Uma
>Cc: Peres, Martin ; intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Add HDR Metadata Parsing and
>handling
>in DRM
Quoting Tvrtko Ursulin (2019-05-17 13:55:48)
>
> On 15/05/2019 14:00, Chris Wilson wrote:
> > Commit 1413b2bc0717 ("drm/i915: Trim NEWCLIENT boosting") had the
> > intended consequence of not allowing a sequence of work that merely
> > crossed into a new engine the privilege to be promoted to
Op 10-05-2019 om 03:53 schreef Gwan-gyeong Mun:
> Function intel_pixel_encoding_setup_vsc handles vsc header and data block
> setup for pixel encoding / colorimetry format.
>
> Setup VSC header and data block in function intel_pixel_encoding_setup_vsc
> for pixel encoding / colorimetry format as
On Fri, May 17, 2019 at 01:17:05PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Peres, Martin
> >Sent: Friday, May 17, 2019 6:39 PM
> >To: Ville Syrjälä ; Shankar, Uma
> >
> >Cc: intel-gfx@lists.freedesktop.org
> >Subject: Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Add HDR
Quoting Tvrtko Ursulin (2019-05-17 12:52:36)
>
> On 17/05/2019 12:38, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-05-17 12:25:16)
> >> @@ -184,3 +186,19 @@ Example:
> >> M.1.VCS
> >>
> >> This sets up the engine map to all available VCS class engines.
> >> +
> >> +Context load
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