On Tue, Aug 20, 2019 at 12:13:59PM +0900, Sergey Senozhatsky wrote:
> Always put_filesystem() in i915_gemfs_init().
>
> Signed-off-by: Sergey Senozhatsky
> ---
> - v2: rebased (i915 does not remount gemfs anymore)
Which means it real doesn't need its mount anyore, and thus can use
plain old
== Series Details ==
Series: series starting with [1/2] drm/i915: Don't deballoon unused ggtt
drm_mm_node in linux guest
URL : https://patchwork.freedesktop.org/series/65450/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7d059cfb5e5c drm/i915: Don't deballoon unused ggtt
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Use 0 for the unordered context
URL : https://patchwork.freedesktop.org/series/65431/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6741_full -> Patchwork_14086_full
The following call trace may exist in linux guest dmesg when guest i915
driver is unloaded.
[ 90.776610] [drm:vgt_deballoon_space.isra.0 [i915]] deballoon space: range
[0x0 - 0x0] 0 KiB.
[ 90.776621] BUG: unable to handle kernel NULL pointer dereference at
00c0
[ 90.776691] IP:
vgpu ballon info consists of four drm_mm_node which is used to reserve
ggtt space, then linux guest won't use these reserved ggtt space.
Each vgpu has its own ballon info, so move ballon info into
i915_virtual_gpu structure.
Signed-off-by: Xiong Zhang
---
drivers/gpu/drm/i915/i915_drv.h | 14
On Mon, 2019-08-19 at 21:59 -0700, Daniele Ceraolo Spurio wrote:
>
> On 8/19/2019 9:25 PM, Summers, Stuart wrote:
> > On Mon, 2019-08-19 at 18:23 -0700, Daniele Ceraolo Spurio wrote:
> > > First uc firmware release for EHL.
> > >
> > > Signed-off-by: Daniele Ceraolo Spurio <
> > >
== Series Details ==
Series: drm/i915/gen11: Add Wa_1604278689:icl,ehl (rev2)
URL : https://patchwork.freedesktop.org/series/65276/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6741_full -> Patchwork_14085_full
Summary
On 8/19/2019 9:25 PM, Summers, Stuart wrote:
On Mon, 2019-08-19 at 18:23 -0700, Daniele Ceraolo Spurio wrote:
First uc firmware release for EHL.
Signed-off-by: Daniele Ceraolo Spurio <
daniele.ceraolospu...@intel.com>
Cc: Matt Roper
Cc: Anusha Srivatsa
Cc: Michal Wajdeczko
---
On Mon, 2019-08-19 at 18:23 -0700, Daniele Ceraolo Spurio wrote:
> First uc firmware release for EHL.
>
> Signed-off-by: Daniele Ceraolo Spurio <
> daniele.ceraolospu...@intel.com>
> Cc: Matt Roper
> Cc: Anusha Srivatsa
> Cc: Michal Wajdeczko
> ---
> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c |
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On
>Behalf Of Lucas De Marchi
>Sent: Thursday, August 15, 2019 5:25 AM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH] drm/i915/tgl: disable DDIC
>
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Dynamically allocate s0ix
struct for VLV
URL : https://patchwork.freedesktop.org/series/65445/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6741 -> Patchwork_14091
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Dynamically allocate s0ix
struct for VLV
URL : https://patchwork.freedesktop.org/series/65445/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b14576485d52 drm/i915: Dynamically allocate s0ix struct for VLV
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
between commit:
70d6894d1456 ("drm/i915: Serialize against vma moves")
from the drm-intel tree and commit:
52791eeec1d9 ("dma-buf: rename reservation_object to
== Series Details ==
Series: drm/i915/uc: define GuC and HuC FWs for EHL
URL : https://patchwork.freedesktop.org/series/65444/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6741 -> Patchwork_14090
Summary
---
With the introduction of display uncore, we want to categorize registers
between display and non-display. To help us getting it right, it will
be useful to move the display registers to a new file that can be used
without including i915_reg.h. To allow that, move all the basic register
type
This is only required for a single platform so no need to reserve the
memory on all of them.
This removes the last direct dependency of i915_drv.h on i915_reg.h
(apart from the i915_reg_t definition).
v2: drop unneeded diff, keep the vlv prefix, call functions
unconditionally (Jani), fwd
== Series Details ==
Series: drm/i915: Use 0 for the unordered context (rev2)
URL : https://patchwork.freedesktop.org/series/65381/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6739_full -> Patchwork_14084_full
Summary
First uc firmware release for EHL.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Matt Roper
Cc: Anusha Srivatsa
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git
First firmware release for EHL.
The following changes since commit 07b925b450bfb4cf3e141c612ec5b104658cd020:
Install only listed firmware files (2019-08-15 07:46:53 -0400)
are available in the Git repository at:
https://cgit.freedesktop.org/drm/drm-firmware/ ehl_firmwares
for you to fetch
== Series Details ==
Series: drm/i915: Select DMABUF_SELFTESTS for the default i915.ko debug build
URL : https://patchwork.freedesktop.org/series/65429/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6739_full -> Patchwork_14083_full
On Sun, 2019-08-18 at 10:49 +0100, Chris Wilson wrote:
> If we try to idle while another thread is submitting, we will be
> forced
> to wait until that other thread is finished -- effectively
> serialising
> the parallel workloads, defeating said purpose.
>
> Signed-off-by: Chris Wilson
Hi Anusha,
Could you take a look at these failures and make sure they are not caused by
this patch
so I can merge this?
Manasi
On Fri, Aug 16, 2019 at 02:24:38PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/dp/dsc: Add Support for all BPCs supported by TGL (rev4)
> URL :
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65437/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6741 -> Patchwork_14089
Summary
---
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65437/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f217c83c161f drm/i915: Use variable for debugfs device status
ebb026770255 drm/i915: Add function to set
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65435/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6741 -> Patchwork_14088
Summary
---
Refactor instdone loops to use the new intel_sseu_has_subslice
function.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 3 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 31 ++--
drivers/gpu/drm/i915/gt/intel_hangcheck.c| 3 +-
Use a local variable to find SSEU runtime information
in various debugfs functions.
v2: Remove extra line breaks per feedback from Chris
Signed-off-by: Stuart Summers
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 +++---
1 file changed, 11
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice
Add a new function to set a range of subslices for a
specified slice based on a given mask.
v2: Use local variable for subslice_mask on HSW and
clean up a few other subslice_mask local variable
changes
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 10
Add a new function to determine whether a particular slice
has a given subslice.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 10 ++
drivers/gpu/drm/i915/intel_device_info.c | 9 -
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git
Add a new function to copy subslices for a specified slice
between intel_sseu structures for the purpose of determining
power-gate status.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/i915_debugfs.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git
Add a new parameter, ss_stride, to the runtime info
structure. This is used to mirror the userspace concept
of subslice stride, which is a range of subslices per slice.
This patch simply adds the definition and updates usage
in the QUERY_TOPOLOGY_INFO handler.
Signed-off-by: Stuart Summers
---
Add a new SSEU runtime parameter, eu_stride, which is
used to mirror the userspace concept of a range of EUs
per subslice.
This patch simply adds the parameter and updates usage
in the QUERY_TOPOLOGY_INFO handler.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 1 +
Add a new function to allow each platform to set maximum
slice, subslice, and EU information to reduce code duplication.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 8 +
drivers/gpu/drm/i915/gt/intel_sseu.h | 3 ++
drivers/gpu/drm/i915/i915_debugfs.c
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice
On Mon, 2019-08-19 at 14:18 -0700, Stuart Summers wrote:
> Currently, the subslice_mask runtime parameter is stored as an
> array of subslices per slice. Expand the subslice mask array to
> better match what is presented to userspace through the
> I915_QUERY_TOPOLOGY_INFO ioctl. The index into
On Fri, 2019-08-16 at 12:55 +0300, Imre Deak wrote:
> To work around a DMC/Punit issue on ICL where the driver's
> ICL_PORT_COMP_DW8/IREFGEN PHY setting is lost when entering/exiting
> DC6
> state, make sure to reinit the PHY whenever disabling DC states.
> Similarly the driver's PHY/DBUF/CDCLK
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65435/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2b168aaac70c drm/i915: Use variable for debugfs device status
189acfa9994c drm/i915: Add function to set
On Mon, 2019-08-19 at 16:21 +0200, Maarten Lankhorst wrote:
> Op 16-08-2019 om 10:04 schreef Lucas De Marchi:
> > From: José Roberto de Souza
> >
> > On TGL some registers moved from DDI to transcoder and the
> > DisplayPort training sequence has a separate BSpec page.
> >
> > I started adding
Add a new function to determine whether a particular slice
has a given subslice.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 10 ++
drivers/gpu/drm/i915/intel_device_info.c | 9 -
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice
Add a new SSEU runtime parameter, eu_stride, which is
used to mirror the userspace concept of a range of EUs
per subslice.
This patch simply adds the parameter and updates usage
in the QUERY_TOPOLOGY_INFO handler.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 1 +
Refactor instdone loops to use the new intel_sseu_has_subslice
function.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 3 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 31 ++--
drivers/gpu/drm/i915/gt/intel_hangcheck.c| 3 +-
Add a new function to copy subslices for a specified slice
between intel_sseu structures for the purpose of determining
power-gate status.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/i915_debugfs.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git
Add a new function to allow each platform to set maximum
slice, subslice, and EU information to reduce code duplication.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 8 +
drivers/gpu/drm/i915/gt/intel_sseu.h | 3 ++
drivers/gpu/drm/i915/i915_debugfs.c
Add a new parameter, ss_stride, to the runtime info
structure. This is used to mirror the userspace concept
of subslice stride, which is a range of subslices per slice.
This patch simply adds the definition and updates usage
in the QUERY_TOPOLOGY_INFO handler.
Signed-off-by: Stuart Summers
---
Use a local variable to find SSEU runtime information
in various debugfs functions.
v2: Remove extra line breaks per feedback from Chris
Signed-off-by: Stuart Summers
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 +++---
1 file changed, 11
Add a new function to set a range of subslices for a
specified slice based on a given mask.
v2: Use local variable for subslice_mask on HSW and
clean up a few other subslice_mask local variable
changes
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 10
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice
== Series Details ==
Series: drm/i915: Assume exclusive access to objects inside resume
URL : https://patchwork.freedesktop.org/series/65434/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6741 -> Patchwork_14087
Summary
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Use 0 for the unordered context
URL : https://patchwork.freedesktop.org/series/65431/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6741 -> Patchwork_14086
== Series Details ==
Series: drm/i915/gen11: Add Wa_1604278689:icl,ehl (rev2)
URL : https://patchwork.freedesktop.org/series/65276/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6741 -> Patchwork_14085
Summary
---
Sending PR for TGl 2.04 -
The following changes since commit 07b925b450bfb4cf3e141c612ec5b104658cd020:
Install only listed firmware files (2019-08-15 07:46:53 -0400)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-firmware TGLDMC
for you to fetch changes up
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Use 0 for the unordered context
URL : https://patchwork.freedesktop.org/series/65431/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2a0a0dac3f5d drm/i915: Generalise the clflush dma-worker
-:194:
Inside gtt_restore_mappings() we currently take the obj->resv->lock, but
in the future we need to avoid taking this fs-reclaim tainted lock as we
need to extend the coverage of the vm->mutex. Take advantage of the
single-threaded nature of the early resume phase, and do a single
wbinvd() to flush
On Mon, 19 Aug 2019 at 17:45, Chris Wilson wrote:
>
> Inside gtt_restore_mappings() we currently take the obj->resv->lock, but
> in the future we need to avoid taking this fs-reclaim tainted lock as we
> need to extend the coverage of the vm->mutex. Take advantage of the
> single-threaded nature
== Series Details ==
Series: drm/i915: Use 0 for the unordered context (rev2)
URL : https://patchwork.freedesktop.org/series/65381/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6739 -> Patchwork_14084
Summary
---
On Mon, 19 Aug 2019 at 18:19, Chris Wilson wrote:
>
> Include the DMABUF_SELFTESTS as part of the standard build for IGT, so
> that they can be run by igt/dmabuf
>
> Testcase: igt/dmabuf
> Signed-off-by: Chris Wilson
> Cc: Tomi Sarvela
Reviewed-by: Matthew Auld
Since commit 078dec3326e2 ("dma-buf: add dma_fence_get_stub") the 0
fence context became an impossible match as it is used for an always
signaled fence. We can simplify our timeline tracking by knowing that 0
always means no match.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
Extract the dma-fence worker used by clflush for wider use, as we
anticipate using workers coupled to dma-fences more frequently.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 123
== Series Details ==
Series: drm/i915: Select DMABUF_SELFTESTS for the default i915.ko debug build
URL : https://patchwork.freedesktop.org/series/65429/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6739 -> Patchwork_14083
Quoting Matthew Auld (2019-08-19 19:16:20)
> On Mon, 19 Aug 2019 at 17:45, Chris Wilson wrote:
> >
> > Extract the dma-fence worker used by clflush for wider use, as we
> > anticipate using workers coupled to dma-fences more frequently.
> >
> > Signed-off-by: Chris Wilson
>
>
>
> > +
> >
Looks good.
Reviewed-by: Umesh Nerlige Ramappa
On Fri, Aug 16, 2019 at 01:04:57AM -0700, Lucas De Marchi wrote:
From: Lionel Landwerlin
The way our hardware is designed doesn't seem to let us use the
MI_RECORD_PERF_COUNT command without setting up a circular buffer.
In the case where the
On Mon, Aug 19, l we need is to add2019 at 4:15 AM Michal Wajdeczko
wrote:
>
> On Mon, 19 Aug 2019 10:09:15 +0200, Martin Peres
> wrote:
>
> > On 18/08/2019 18:51, Michal Wajdeczko wrote:
> >> We hope that now all issues related to missing uC firmwares
> >> are fixed and that driver can continue
On Mon, 19 Aug 2019 at 17:45, Chris Wilson wrote:
>
> Extract the dma-fence worker used by clflush for wider use, as we
> anticipate using workers coupled to dma-fences more frequently.
>
> Signed-off-by: Chris Wilson
> +
> +static const char *get_timeline_name(struct dma_fence *fence)
> +{
>
== Series Details ==
Series: drm/i915/selftests: Serialize against vma moves (rev2)
URL : https://patchwork.freedesktop.org/series/65412/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6735_full -> Patchwork_14080_full
From the bspec:
"SW must always program the FBC_RT_BASE_ADDR_REGISTER_* register
in Render Engine to a reserved value (0x_) such that the
programmed value doesn’t match the render target surface address
programmed. This would disable render engine from
> -Original Message-
> From: De Marchi, Lucas
> Sent: Monday, August 19, 2019 11:04 AM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; Souza, Jose
> Subject: Re: [PATCH v2 04/40] drm/i915/tgl: update DMC firmware to 2.04
>
> On Mon, Aug 19, 2019 at 10:55:56AM -0700,
On Mon, Aug 19, 2019 at 10:55:56AM -0700, Anusha Srivatsa wrote:
-Original Message-
From: De Marchi, Lucas
Sent: Saturday, August 17, 2019 2:38 AM
To: intel-gfx@lists.freedesktop.org
Cc: Souza, Jose ; Srivatsa, Anusha
Subject: [PATCH v2 04/40] drm/i915/tgl: update DMC firmware to
> -Original Message-
> From: De Marchi, Lucas
> Sent: Saturday, August 17, 2019 2:38 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Souza, Jose ; Srivatsa, Anusha
>
> Subject: [PATCH v2 04/40] drm/i915/tgl: update DMC firmware to 2.04
>
> 2 important fixes:
> - vblank counter is now
Since commit 078dec3326e2 ("dma-buf: add dma_fence_get_stub") the 0
fence context became an impossible match as it is used for an always
signaled fence. We can simplify our timeline tracking by knowing that 0
always means no match.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
On Mon, Aug 19, 2019 at 06:26:08AM -0700, Shankar, Uma wrote:
-Original Message-
From: Lucas De Marchi [mailto:lucas.de.mar...@gmail.com]
Sent: Friday, August 16, 2019 8:44 PM
To: Shankar, Uma
Cc: De Marchi, Lucas ; intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH]
On Mon, 19 Aug 2019 at 17:45, Chris Wilson wrote:
>
> Since commit 078dec3326e2 ("dma-buf: add dma_fence_get_stub") the 0
> fence context became an impossible match as it is used for an always
> signaled fence. We can simplify our timeline tracking by knowing that 0
> always means no match.
>
>
Quoting Patchwork (2019-08-19 18:23:51)
> == Series Details ==
>
> Series: series starting with [01/10] drm/i915: Use 0 for the unordered context
> URL : https://patchwork.freedesktop.org/series/65426/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6737 ->
== Series Details ==
Series: series starting with [01/10] drm/i915: Use 0 for the unordered context
URL : https://patchwork.freedesktop.org/series/65426/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6737 -> Patchwork_14082
Include the DMABUF_SELFTESTS as part of the standard build for IGT, so
that they can be run by igt/dmabuf
Testcase: igt/dmabuf
Signed-off-by: Chris Wilson
Cc: Tomi Sarvela
---
drivers/gpu/drm/i915/Kconfig.debug | 1 +
1 file changed, 1 insertion(+)
diff --git
On Sat, Aug 17, 2019 at 02:38:23AM -0700, Lucas De Marchi wrote:
> The current SKUs added for Tiger Lake don't have DDIC hooked up, even
> though it is supported by the SoC. The current state for these SKUs is
> problematic since while enabling the combo phy, PORT_COMP_DW* return
> 0x,
Quoting Chris Wilson (2019-08-19 10:59:26)
> In light of recent review slip ups, the absence of a suite of tests for
> dma-buf became apparent. Given the current plethora of testing
> frameworks, opt for one already in use by Intel's CI and so allow easy
> hook up into igt.
>
> We introduce a new
== Series Details ==
Series: series starting with [1/3] dma-buf: Introduce selftesting framework
URL : https://patchwork.freedesktop.org/series/65403/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6735_full -> Patchwork_14079_full
== Series Details ==
Series: series starting with [01/10] drm/i915: Use 0 for the unordered context
URL : https://patchwork.freedesktop.org/series/65426/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f3745550c94b drm/i915: Use 0 for the unordered context
18f8647117cd drm/i915:
On Mon, Aug 19, 2019 at 07:13:56PM +0300, Ville Syrjälä wrote:
> On Thu, Aug 15, 2019 at 02:58:59PM -0700, Matt Roper wrote:
> > From the bspec:
> >
> > "SW must always program the FBC_RT_BASE_ADDR_REGISTER_* register
> > in Render Engine to a reserved value (0x_) such
Since we want to revoke the ggtt vma from only under the ggtt->mutex, we
need to move protection of the userfault tracking from the struct_mutex
to the ggtt->mutex.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 10 +++---
drivers/gpu/drm/i915/i915_debugfs.c
When under severe stress for GTT mappable space, the LRU eviction model
falls off a cliff. We spend all our time scanning the much large
non-mappable vma searching for something within the mappable zone we can
evict. Turn this on its head by only using the full vma if it is already
pinned in the
Avoid calling i915_vma_put_fence() by using our alternate paths that
bind a secondary vma avoiding the original fenced vma. For the few
instances where we need to release the fence (i.e. on binding when the
GGTT range becomes invalid), replace the put_fence with a revoke_fence.
Signed-off-by:
The premise here is to simply avoiding having to acquire the vm->mutex
inside vma create/destroy to update the vm->unbound_lists, to avoid some
nasty lock recursions later.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c
We can reduce the locking for fence registers from the dev->struct_mutex
to a local mutex. We could introduce a mutex for the sole purpose of
tracking the fence acquisition, except there is a little bit of overlap
with the fault tracking, so use the i915_ggtt.mutex as it covers both.
Inside gtt_restore_mappings() we currently take the obj->resv->lock, but
in the future we need to avoid taking this fs-reclaim tainted lock as we
need to extend the coverage of the vm->mutex. Take advantage of the
single-threaded nature of the early resume phase, and do a single
wbinvd() to flush
Extract the dma-fence worker used by clflush for wider use, as we
anticipate using workers coupled to dma-fences more frequently.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 117 +++-
Since commit 078dec3326e2 ("dma-buf: add dma_fence_get_stub") the 0
fence context became an impossible match as it is used for an always
signaled fence. We can simplify our timeline tracking by knowing that 0
always means no match.
Signed-off-by: Chris Wilson
---
Add an atomic counter and always take the spinlock around the pin/unpin
events, so that we can perform the list manipulation concurrently.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c| 3 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
Before we acquire the vma for GPU activity, ensure that the underlying
object is not already in the process of being freed.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_vma.c | 3 +--
drivers/gpu/drm/i915/i915_vma.h | 8
2 files changed, 9 insertions(+), 2 deletions(-)
On Tue, Jul 23, 2019 at 03:13:37PM +0200, Daniel Vetter wrote:
> Noticed while reviewing code. I'm not sure whether this might or might
> not explain some of the missed vblank hilarity we've been seeing. I
> think those all go through the vblank completion event, which has
> unconditional barriers
On Thu, Aug 08, 2019 at 07:25:47PM +0300, Imre Deak wrote:
> The conversion during HDMI HW readout from port_clock to crtc_clock was
> missed when HDMI 10bpc support was added, so fix that.
>
> v2:
> - Unscrew the non-HDMI case.
>
> Fixes: cd9e11a8bf25 ("drm/i915/icl: Add 10-bit support for
On Mon, Jul 29, 2019 at 12:11:58PM -0700, Manasi Navare wrote:
> On Thu, Jul 18, 2019 at 05:43:39PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The DP port/pipe goes wonky if we try to use timings with
> > hdisplay==4096 on pre-HSW platforms. The link fails to train
> > and the
On Thu, Aug 15, 2019 at 02:58:59PM -0700, Matt Roper wrote:
> From the bspec:
>
> "SW must always program the FBC_RT_BASE_ADDR_REGISTER_* register
> in Render Engine to a reserved value (0x_) such that the
> programmed value doesn’t match the render target surface
== Series Details ==
Series: drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ (rev3)
URL : https://patchwork.freedesktop.org/series/63432/
State : failure
== Summary ==
Applying: drm/i915: enum transcoder and pipe are moved into i915_drm.h
Applying: misc/mei_hdcp: Adding the transcoder detail in
From Gen12 onwards, HDCP HW block is implemented within transcoders.
Till Gen11 HDCP HW block was part of DDI.
Hence required changes in HW programming is handled here.
As ME FW needs the transcoder detail on which HDCP is enabled
on Gen12+ platform, we are populating the detail in
ME FW takes the transcoder details for Gen12+ platforms, as HDCP HW
block is moved to transcoders.
hdcp_port_data is extended with enum transcoder. Payload structure is
modified and populated from the hdcp_port_data.
Signed-off-by: Ramalingam C
---
drivers/misc/mei/hdcp/mei_hdcp.c | 27
Enabling the HDCP1.4 and 2.2 on TGL by supporting the HW block movement
from DDI into transcoder.
v6:
Extending the I915-MEI HDCP interface to include the transcoder.
For register programming, transcoder is used instead of PIPE. Just
readability improvement
pipe and transcoder
For the reusability of the enum transcoder and enum pipe in other driver
modules (like mei_hdcp), enum port definition is moved from I915 local
header intel_display.h to drm/i915_drm.h
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/display/intel_display.h | 44 ---
1 - 100 of 159 matches
Mail list logo
