vgpu ppgtt notification was split into 2 steps, the first step is to
update PVINFO's pdp register and then write PVINFO's g2v_notify register
with action code to tirgger ppgtt notification to GVT side.
currently these steps were not atomic operations due to no any protection,
so it is easy to ente
== Series Details ==
Series: drm/i915: Hold irq-off for the entire fake lock period
URL : https://patchwork.freedesktop.org/series/65613/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6765_full -> Patchwork_14140_full
Summa
== Series Details ==
Series: drm/i915/tgl: Advanced preparser support for GPU relocs
URL : https://patchwork.freedesktop.org/series/65658/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6770 -> Patchwork_14152
Summary
--
== Series Details ==
Series: drm/i915/dp: Support for DP HDR outputs
URL : https://patchwork.freedesktop.org/series/65656/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6770 -> Patchwork_14151
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915/tgl: Advanced preparser support for GPU relocs
URL : https://patchwork.freedesktop.org/series/65658/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
68a96483d2c1 drm/i915/tgl: Advanced preparser support for GPU relocs
-:121: WARNING:LINE_SPAC
== Series Details ==
Series: drm/i915/dp: Support for DP HDR outputs
URL : https://patchwork.freedesktop.org/series/65656/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f56779e2a694 drm/i915/dp: Extend program of VSC Header and DB for Colorimetry
Format
b8e7c747d444 drm/i915/d
== Series Details ==
Series: drm/i915: Kill the undead i915_gem_batch_pool.c
URL : https://patchwork.freedesktop.org/series/65593/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6763_full -> Patchwork_14137_full
Summary
TGL has an improved CS pre-parser that can now pre-fetch commands across
batch boundaries. This improves performances when lots of small batches
are used, but has an impact on self-modifying code. If we want to modify
the content of a batch from another ring/batch, we need to either
guarantee that
== Series Details ==
Series: drm/i915/tgl: Enabling DSC on Pipe A for TGL (rev2)
URL : https://patchwork.freedesktop.org/series/65216/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6769 -> Patchwork_14150
Summary
---
Hi,
On 8/22/19 10:29 PM, Janusz Krzysztofik wrote:
When a perfectly working i915 device is hot unplugged (via sysfs) and
hot re-plugged again, its dev->archdata.iommu field is not populated
again with an IOMMU pointer. As a result, the device probe fails on
DMA mapping error during scratch page
On Fri, 23 Aug 2019 at 05:29, Rodrigo Vivi wrote:
>
> Hi Dave and Daniel,
>
> Here goes the final pull request targeting 5.4.
For some reason patchwork hasn't picked this up. or if it has I can't
see it. Not sure whether it was the earlier patch code in it or
something else malformed.
Dave.
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Call dma_set_max_seg_size() in
i915_ggtt_probe_hw() (rev2)
URL : https://patchwork.freedesktop.org/series/65643/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6769 -> Patchwork_14149
== Series Details ==
Series: series starting with dma_resv: prime lockdep annotations (rev3)
URL : https://patchwork.freedesktop.org/series/65575/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6763_full -> Patchwork_14136_full
==
It attaches the colorspace connector property to a DisplayPort connector.
Based on colorspace change, modeset will be triggered to switch to a new
colorspace.
Based on colorspace property value create a VSC SDP packet with appropriate
colorspace. This would help to enable wider color gamut like BT
When BT.2020 Colorimetry output is used for DP, we should program BT.2020
Colorimetry to MSA and VSC SDP. It adds output_colorspace to
intel_crtc_state struct as a place holder of pipe's output colorspace.
In order to distinguish needed colorimetry for VSC SDP, it adds
intel_dp_needs_vsc_colorimetr
It attaches HDR metadata property to DP connector on GLK+.
It enables HDR metadata infoframe sdp on GLK+ to be used to send
HDR metadata to DP sink.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/
Function intel_dp_setup_hdr_metadata_infoframe_sdp handles Infoframe SDP
header and data block setup for HDR Static Metadata. It enables writing of
HDR metadata infoframe SDP to panel. Support for HDR video was introduced
in DisplayPort 1.4. It implements the CTA-861-G standard for transport of
sta
In order to use colorspace property to Display Port connectors, it extends
DRM_MODE_CONNECTOR_DisplayPort connector_type on
drm_mode_create_colorspace_property function.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/drm_connector.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
d
It refactors and renames a function which handled vsc sdp header and data
block setup for supporting colorimetry format.
Function intel_dp_setup_vsc_sdp handles vsc sdp header and data block
setup for pixel encoding / colorimetry format.
In order to use colorspace information of a connector, it add
Support for HDR10 video was introduced in DisplayPort 1.4.
On GLK+ platform, in order to use DisplayPort HDR10, we need to support
BT.2020 colorimetry and HDR Static metadata.
It implements the CTA-861-G standard for transport of static HDR metadata.
It enables writing of HDR metadata infoframe SDP
DSC was not supported on Pipe A for previous platforms. Tigerlake onwards,
all the pipes support DSC. Hence, the DSC and FEC restriction on
Pipe A needs to be removed.
v2: Changes in the logic around removing the restriction around
Pipe A (Manasi, Lucas)
Cc: Manasi Navare
Signed-off-by: Madh
On Thu, Aug 22, 2019 at 04:28:15PM +0300, Mika Kuoppala wrote:
Lucas De Marchi writes:
From: Michel Thierry
GAM registers located in the 0x4xxx range have been relocated to 0xCxxx;
this is to make space for global MOCS registers.
HSD: 399379
Cc: Daniele Ceraolo Spurio
Signed-off-by: Michel
Ville/Maarten/Daniel,
This is a simple rename patch as suggested by danvet, can any one of you review
this?
So that rest of Maarten's patches can also use these new functions.
Manasi
On Mon, Jun 24, 2019 at 02:08:43PM -0700, Manasi Navare wrote:
> This patch has no functional changes. This ju
Now that we've fixed i915 so that it sets a max SG segment length and
gotten rid of the relevant warnings, let's enable
CONFIG_DMA_API_DEBUG_SG for intel-ci so that we can catch issues like
this in the future as well.
Changes since v2:
* Also select DMA_API_DEBUG - Chris Wilson
Signed-off-by: Lyu
On Fri, Aug 16, 2019 at 05:50:41PM -0700, Matt Roper wrote:
Our pin mapping tables for ICP and MCC currently only list the standard
GPIO pins used for various output ports. Even through ICP's standard
pin usage only utilizes pins 1, 2, and 9-12, and MCC's standard pin
usage only uses pins 1, 2,
On Tue, 20 Aug 2019 22:24:40 +0200 Daniel Vetter wrote:
> Hi Peter,
>
> Iirc you've been involved at least somewhat in discussing this. -mm folks
> are a bit undecided whether these new non_block semantics are a good idea.
> Michal Hocko still is in support, but Andrew Morton and Jason Gunthorpe
Quoting Lyude Paul (2019-08-22 21:31:27)
> Now that we've fixed i915 so that it sets a max SG segment length and
> gotten rid of the relevant warnings, let's enable
> CONFIG_DMA_API_DEBUG_SG for intel-ci so that we can catch issues like
> this in the future as well.
>
> Signed-off-by: Lyude Paul
Quoting Stuart Summers (2019-08-22 19:32:09)
> Add a subslice stride calculation when setting subslices. This
> aligns more closely with the userspace expectation of the subslice
> mask structure.
>
> v2: Use local variable for subslice_mask on HSW and
> clean up a few other subslice_mask loca
Quoting Stuart Summers (2019-08-22 19:32:08)
> Add a new function to set a set of subslices for a given
> slice.
>
> v2: Fix typo in subslice_mask assignment
>
> Signed-off-by: Stuart Summers
Simple enough for even me to understand,
Reviewed-by: Chris Wilson
-Chris
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Call dma_set_max_seg_size() in
i915_ggtt_probe_hw()
URL : https://patchwork.freedesktop.org/series/65643/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6768 -> Patchwork_14148
===
On 8/20/19 11:00 AM, Daniele Ceraolo Spurio wrote:
On 8/20/19 8:42 AM, Michal Wajdeczko wrote:
On Tue, 20 Aug 2019 04:01:47 +0200, Daniele Ceraolo Spurio
wrote:
diff --git a/drivers/gpu/drm/i915/intel_reg_types.h
b/drivers/gpu/drm/i915/intel_reg_types.h
new file mode 100644
index 0
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: Track ggtt fence reservations
under its own mutex (rev2)
URL : https://patchwork.freedesktop.org/series/65591/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6760_full -> Patchwork_14135_full
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Call dma_set_max_seg_size() in
i915_ggtt_probe_hw()
URL : https://patchwork.freedesktop.org/series/65643/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Call dma_set_max_se
== Series Details ==
Series: drm/i915: Call dma_set_max_seg_size() in i915_ggtt_probe_hw()
URL : https://patchwork.freedesktop.org/series/65642/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6767 -> Patchwork_14147
Summary
On 8/22/19 11:02 AM, john.c.harri...@intel.com wrote:
From: John Harrison
Gen12 introduces a completely new and different scheme for
implementing engine relative MMIO accesses - MI_LRI_MMIO_REMAP. This
requires using the base address of instance zero of the relevant
engine class. And then, it
Hi,
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: 4.18+
The bot has tested the following trees: v5.2.9, v4.19.67.
v5.2.9: Failed to apply! Possible dependencies:
Unable to c
Now that we've fixed i915 so that it sets a max SG segment length and
gotten rid of the relevant warnings, let's enable
CONFIG_DMA_API_DEBUG_SG for intel-ci so that we can catch issues like
this in the future as well.
Signed-off-by: Lyude Paul
Cc: Chris Wilson
---
drivers/gpu/drm/i915/Kconfig.d
Currently, we don't call dma_set_max_seg_size() for i915 because we
intentionally do not limit the segment length that the device supports.
However, this results in a warning being emitted if we try to map
anything larger than SZ_64K on a kernel with CONFIG_DMA_API_DEBUG_SG
enabled:
[7.751926]
On Wed, 2019-08-21 at 13:13 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v8,1/3] drm/i915/psr: Make PSR
> registers relative to transcoders
> URL : https://patchwork.freedesktop.org/series/65507/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes f
...whoops.
Ignore this patch-Chris Wilson had requested that I send a patch along with
this one to enable CONFIG_DMA_API_DEBUG_SG in CI, but I completely forgot to
do that before sending. Will send out a reroll with that in just a moment
On Thu, 2019-08-22 at 16:04 -0400, Lyude Paul wrote:
> Curr
Currently, we don't call dma_set_max_seg_size() for i915 because we
intentionally do not limit the segment length that the device supports.
However, this results in a warning being emitted if we try to map
anything larger than SZ_64K on a kernel with CONFIG_DMA_API_DEBUG_SG
enabled:
[7.751926]
Acked-by: Jason Ekstrand
On Wed, Aug 21, 2019 at 10:20 AM Daniel Vetter
wrote:
> On Wed, Aug 21, 2019 at 3:55 PM Ville Syrjälä
> wrote:
> >
> > On Tue, Aug 20, 2019 at 01:57:44PM -0700, Daniele Ceraolo Spurio wrote:
> > >
> > >
> > > On 8/20/19 12:54 PM, Daniel Vetter wrote:
> > > > The cpu (d
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65639/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6767 -> Patchwork_14146
Summary
---
**SUCCESS*
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65639/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
feeaef8cfa8b drm/i915: Use variable for debugfs device status
0771e1cc9fe8 drm/i915: Add function to set SSE
== Series Details ==
Series: drm/i915: Engine relative MMIO (rev7)
URL : https://patchwork.freedesktop.org/series/57117/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6767 -> Patchwork_14145
Summary
---
**SUCCESS**
When setting up subslice_mask, instead of operating on the slice
array directly, use a local variable to start bits per slice, then
use this to set the per slice array in one step.
Signed-off-by: Stuart Summers
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_device_info.c | 49
Use a local variable to find SSEU runtime information
in various debugfs functions.
v2: Remove extra line breaks per feedback from Chris
Signed-off-by: Stuart Summers
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 +++---
1 file changed, 11 insertion
Add a new parameter, ss_stride, to the runtime info
structure. This is used to mirror the userspace concept
of subslice stride, which is a range of subslices per slice.
This patch simply adds the definition and updates usage
in the QUERY_TOPOLOGY_INFO handler.
v2: Add GEM_BUG_ON to make sure ss_s
Add a new function to set a set of subslices for a given
slice.
v2: Fix typo in subslice_mask assignment
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 6 ++
drivers/gpu/drm/i915/gt/intel_sseu.h | 3 +++
drivers/gpu/drm/i915/intel_device_info.c | 18 +
etter match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice index / 8
Note this is the second iteration of an original patch to implement
the same. There are a couple of minor code changes
Add a new function to allow each platform to set maximum
slice, subslice, and EU information to reduce code duplication.
Signed-off-by: Stuart Summers
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 8 +
drivers/gpu/drm/i915/gt/intel_sseu.h | 3 ++
drivers/gp
Add a new function to copy subslices for a specified slice
between intel_sseu structures for the purpose of determining
power-gate status. Note that currently ss_stride has a max
of 1.
Signed-off-by: Stuart Summers
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 17 +
Refactor instdone loops to use the new intel_sseu_has_subslice
function.
Signed-off-by: Stuart Summers
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 3 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 30 +---
drivers/gpu/drm/i915/gt/intel_hangch
Add a new SSEU runtime parameter, eu_stride, which is
used to mirror the userspace concept of a range of EUs
per subslice.
This patch simply adds the parameter and updates usage
in the QUERY_TOPOLOGY_INFO handler.
v2: Add GEM_BUG_ON to make sure eu_stride is valid
Signed-off-by: Stuart Summers
Add a new function to determine whether a particular slice
has a given subslice.
Signed-off-by: Stuart Summers
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 16
drivers/gpu/drm/i915/intel_device_info.c | 9 -
2 files changed, 20 insertions(+)
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice i
Add a subslice stride calculation when setting subslices. This
aligns more closely with the userspace expectation of the subslice
mask structure.
v2: Use local variable for subslice_mask on HSW and
clean up a few other subslice_mask local variable
changes
v3: Add GEM_BUG_ON for ss_stride t
== Series Details ==
Series: drm/i915: Engine relative MMIO (rev7)
URL : https://patchwork.freedesktop.org/series/57117/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2eab059bc87e drm/i915: Engine relative MMIO
-:108: ERROR:COMPLEX_MACRO: Macros with complex values should be en
From: John Harrison
With virtual engines, it is no longer possible to know which specific
physical engine a given request will be executed on at the time that
request is generated. This means that the request itself must be engine
agnostic - any direct register writes must be relative to the engi
From: John Harrison
Gen12 introduces a completely new and different scheme for
implementing engine relative MMIO accesses - MI_LRI_MMIO_REMAP. This
requires using the base address of instance zero of the relevant
engine class. And then, it is only valid if the register in
question falls within a
From: John Harrison
Newer hardware has support for making LRI accesses to MMIO registers
relative to the engine that is executing the LRI instruction. This is
required for things like hardware based load balancing across engines.
John Harrison (2):
drm/i915: Engine relative MMIO
drm/i915: En
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: Track ggtt fence reservations
under its own mutex
URL : https://patchwork.freedesktop.org/series/65585/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6759_full -> Patchwork_14134_full
===
On Thu, 2019-08-22 at 21:37 +0530, Gupta, Anshuman wrote:
>
> On 8/22/2019 1:36 AM, Souza, Jose wrote:
> > On Wed, 2019-08-21 at 10:06 +0530, Anshuman Gupta wrote:
> > > On 2019-08-20 at 15:33:23 -0700, José Roberto de Souza wrote:
> > > > PSR registers are a mess, some have the full address while
== Series Details ==
Series: drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ (rev7)
URL : https://patchwork.freedesktop.org/series/63432/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6766 -> Patchwork_14144
Summary
---
Verified from B.Specs:7723 and B.Spec:8041
On 8/16/2019 1:34 PM, Lucas De Marchi wrote:
From: José Roberto de Souza
From BDW+ the PSR registers moved from DDIA to transcoder, so any port
with a eDP panel connected can have PSR, so lets remove this limitation.
Cc: Dhinakaran Pandiyan
Cc: Rod
== Series Details ==
Series: series starting with drm/i915: Switch obj->mm.lock lockdep annotations
on its head (rev2)
URL : https://patchwork.freedesktop.org/series/65467/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6766 -> Patchwork_14143
=
== Series Details ==
Series: iommu/vt-d: Fix IOMMU field not populated on device hot re-plug
URL : https://patchwork.freedesktop.org/series/65627/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6766 -> Patchwork_14142
Summar
== Series Details ==
Series: series starting with drm/i915: Switch obj->mm.lock lockdep annotations
on its head (rev2)
URL : https://patchwork.freedesktop.org/series/65467/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
93bdacc163d4 drm/i915: Switch obj->mm.lock lockdep annotat
== Series Details ==
Series: drm/i915/dp: Fix DSC enable code to use cpu_transcoder instead of
encoder->type
URL : https://patchwork.freedesktop.org/series/65625/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6766 -> Patchwork_14141
===
From Gen12 onwards, HDCP HW block is implemented within transcoders.
Till Gen11 HDCP HW block was part of DDI.
Hence required changes in HW programming is handled here.
As ME FW needs the transcoder detail on which HDCP is enabled
on Gen12+ platform, we are populating the detail in hdcp_port_data
I915 needs to send the index of the transcoder as per ME FW.
To support this, define enum mei_fw_ddi and add as a member into
the struct hdcp_port_data.
Signed-off-by: Ramalingam C
Acked-by: Jani Nikula
---
include/drm/i915_mei_hdcp_interface.h | 13 +
1 file changed, 13 insertions(
For gen12+ platform we need to pass the transcoder info
as part of the port info into ME FW.
This change fills the payload for ME FW from hdcp_port_data.
Signed-off-by: Ramalingam C
Acked-by: Jani Nikula
---
drivers/misc/mei/hdcp/mei_hdcp.c | 11 +++
drivers/misc/mei/hdcp/mei_hdcp.h |
Handled the need for exposing enum port to mei_hdcp driver, by
converting the port into ddi index as per ME FW and sending to mei_hdcp.
Hence move enum port definition into I915 driver itself.
v2:
intel_display.h is included in intel_hdcp.h
v3:
enum port is declared in headers.
Signed-off-by
On gen12+ platforms, HDCP HW is associated to the transcoder.
Hence on every modeset update associated transcoder into the
intel_hdcp of the port.
v2:
s/trans/cpu_transcoder [Jani]
Signed-off-by: Ramalingam C
Acked-by: Jani Nikula
---
.../drm/i915/display/intel_display_types.h| 7 +++
d
I915 converts it's port value into ddi index defiend by ME FW
and pass it as a member of hdcp_port_data structure.
Hence expose the enum mei_fw_ddi to I915 through
i915_mei_interface.h.
Signed-off-by: Ramalingam C
Acked-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 15 +++
Enabling the HDCP1.4 and 2.2 on TGL by supporting the HW block movement
from DDI into transcoder.
v9:
s/trans/cpu_transcoder
enum port and transcoders are declared at few headers.
Ramalingam C (6):
drm/i915: mei_hdcp: I915 sends ddi index as per ME FW
drm: Move port definition back to i91
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch]
> Sent: Thursday, August 22, 2019 7:50 AM
> To: Intel Graphics Development
> Cc: Daniel Vetter ; Chris Wilson wilson.co.uk>; Tang, CQ ; Ursulin, Tvrtko
> ; Joonas Lahtinen
> ; Vetter, Daniel
> Subject: [PATCH] d
Quoting Mika Kuoppala (2019-08-22 14:31:53)
> Lucas De Marchi writes:
> > +static void gen8_init_reg_state(u32 *regs,
> > + struct intel_context *ce,
> > + struct intel_engine_cs *engine,
> > + struct intel_ring *r
The trouble with having a plain nesting flag for locks which do not
naturally nest (unlike block devices and their partitions, which is
the original motivation for nesting levels) is that lockdep will
never spot a true deadlock if you screw up.
This patch is an attempt at trying better, by highlig
== Series Details ==
Series: series starting with [1/3] dma_resv: prime lockdep annotations
URL : https://patchwork.freedesktop.org/series/65575/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6759_full -> Patchwork_14132_full
===
Op 21-08-2019 om 23:59 schreef Manasi Navare:
> This patch fixes the intel_configure_pps_for_dsc_encoder() function to use
> cpu_transcoder instead of encoder->type to select the correct DSC registers
> that was wrongly used in the original patch for one DSC register isntance.
>
> Fixes: 7182414e25
On Thu, 22 Aug 2019 08:40:33 +0200, Arkadiusz Hiler
wrote:
On Mon, Aug 19, 2019 at 11:09:15AM +0300, Martin Peres wrote:
On 18/08/2019 18:51, Michal Wajdeczko wrote:
> We hope that now all issues related to missing uC firmwares
> are fixed and that driver can continue to load without GuC
> o
On Thu, 22 Aug 2019, Ramalingam C wrote:
> On gen12+ platforms, HDCP HW is associated to the transcoder.
> Hence on every modeset associated transcoder is updated into the
> intel_hdcp.
>
> Signed-off-by: Ramalingam C
> ---
> .../drm/i915/display/intel_display_types.h| 7 +++
> drivers/gpu/
On Wed, 2019-08-21 at 23:56 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-08-21 00:05:42)
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > index a82cea95c2f2..99bee06cdbdb 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_
Chris Wilson writes:
> Sadly lockdep records when the irqs are reenabled and then marks up the
> fake lock as being irq-unsafe. Our hand is forced and so we must mark up
> the entire fake lock critical section as irq-off.
>
Tricky tweaks are tricky. It was not so easy
to lure lockdep to do our b
Hi,
On 8/21/2019 11:57 PM, Chris Wilson wrote:
Quoting Animesh Manna (2019-08-21 07:32:25)
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. Will be using for bulk register programming
e.g. gamma lut programming, HDR meta data programming.
Cc: Shashank
On Wed, 2019-08-21 at 23:49 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-08-21 00:05:44)
> > Currently, the subslice_mask runtime parameter is stored as an
> > array of subslices per slice. Expand the subslice mask array to
> > better match what is presented to userspace through the
>
Quoting Chris Wilson (2019-08-22 09:59:17)
> You have to cut it off at the neck, otherwise it just reappears in the
> next merge, like commit 3f866026f0ce ("Merge drm/drm-next
> into drm-intel-next-queued")
>
> References: 3f866026f0ce ("Merge drm/drm-next into drm-intel-next-queued")
> Signed-off
On 8/17/19 2:38 AM, Lucas De Marchi wrote:
From: Michel Thierry
Gen12 has subtle changes in the reg state context offsets (some fields
are gone, some are in a different location), compared to previous Gens.
The simplest approach seems to be keeping Gen12 (and future platform)
changes apart f
Chris Wilson writes:
> Quoting Lucas De Marchi (2019-08-17 10:38:48)
>> From: Daniele Ceraolo Spurio
>>
>> Re-use Gen11 context size for now.
>>
>> [ Lucas: add HACK since this is a temporary patch that needs to be
>> confirmed: we need to check BSpec 46255 and recompute ]
>
> We can drop th
On Wed, 21 Aug 2019, Chris Wilson wrote:
> Quoting Animesh Manna (2019-08-21 07:32:26)
>> Existing mmio-reg-write need intel_uncore handle which is part
>> of dev_priv structure and the same design is followed by
>> adding dsb handle in dev_priv for programming registers through DSB.
>>
>> I915_W
Lucas De Marchi writes:
> From: Michel Thierry
>
> Gen12 has subtle changes in the reg state context offsets (some fields
> are gone, some are in a different location), compared to previous Gens.
>
> The simplest approach seems to be keeping Gen12 (and future platform)
> changes apart from the p
On 19/08/2019 21:22, Lucas De Marchi wrote:
> On Mon, Aug 19, l we need is to add2019 at 4:15 AM Michal Wajdeczko
> wrote:
>>
>> On Mon, 19 Aug 2019 10:09:15 +0200, Martin Peres
>> wrote:
>>
>>> On 18/08/2019 18:51, Michal Wajdeczko wrote:
We hope that now all issues related to missing uC fi
On Wed, Aug 21, 2019 at 10:38:35PM +0200, Daniel Vetter wrote:
> Oops.
>
> Fixes: 9edbf1fa600a ("drm: Add API for capturing frame CRCs")
> Cc: Tomeu Vizoso
> Cc: Emil Velikov
> Cc: Benjamin Gaignard
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/drm_debugfs_crc.c | 2 +-
> 1 file chan
On Wed, 2019-08-21 at 10:06 +0530, Anshuman Gupta wrote:
> On 2019-08-20 at 15:33:23 -0700, José Roberto de Souza wrote:
> > PSR registers are a mess, some have the full address while others
> > just
> > have the additional offset from psr_mmio_base.
> >
> > For BDW+ psr_mmio_base is nothing more
On 8/22/19 4:24 PM, Thomas Hellström (VMware) wrote:
On 8/22/19 4:02 PM, Koenig, Christian wrote:
Am 22.08.19 um 15:06 schrieb Daniel Vetter:
On Thu, Aug 22, 2019 at 07:56:56AM +, Koenig, Christian wrote:
Am 22.08.19 um 08:49 schrieb Daniel Vetter:
With nouveau fixed all ttm-using drives
When a perfectly working i915 device is hot unplugged (via sysfs) and
hot re-plugged again, its dev->archdata.iommu field is not populated
again with an IOMMU pointer. As a result, the device probe fails on
DMA mapping error during scratch page setup.
It looks like that happens because devices ar
On Thu, Aug 22, 2019 at 4:24 PM Jason Gunthorpe wrote:
>
> On Thu, Aug 22, 2019 at 10:42:39AM +0200, Daniel Vetter wrote:
>
> > > RDMA has a mutex:
> > >
> > > ib_umem_notifier_invalidate_range_end
> > > rbt_ib_umem_for_each_in_range
> > >invalidate_range_start_trampoline
> > > ib_umem_n
On 8/22/19 4:02 PM, Koenig, Christian wrote:
Am 22.08.19 um 15:06 schrieb Daniel Vetter:
On Thu, Aug 22, 2019 at 07:56:56AM +, Koenig, Christian wrote:
Am 22.08.19 um 08:49 schrieb Daniel Vetter:
With nouveau fixed all ttm-using drives have the correct nesting of
mmap_sem vs dma_resv, and
Op 21-08-2019 om 23:32 schreef José Roberto de Souza:
> On TGL some registers moved from DDI to transcoder and the
> DisplayPort training sequence has a separate BSpec page.
>
> I started adding 'ifs' to the original intel_ddi_pre_enable_dp() but
> it was becoming really hard to follow, so a new an
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