On 9/18/2019 1:27 PM, Animesh Manna wrote:
Added docbook info regarding Display State Buffer(DSB) which
is added from gen12 onwards to batch submit display HW programming.
v1: Initial version as RFC.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
On 9/18/2019 1:27 PM, Animesh Manna wrote:
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commit function will trigger the execution of the batch buffer. All
the registers will be updated
== Series Details ==
Series: drm/i915: fix SFC reset flow (rev2)
URL : https://patchwork.freedesktop.org/series/66779/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6917 -> Patchwork_14451
Summary
---
**SUCCESS**
== Series Details ==
Series: TGL TC enabling (rev2)
URL : https://patchwork.freedesktop.org/series/66695/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6917 -> Patchwork_14450
Summary
---
**SUCCESS**
No
== Series Details ==
Series: TGL TC enabling (rev2)
URL : https://patchwork.freedesktop.org/series/66695/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8a9f0a714a82 drm/i915/tgl: Add missing ddi clock select during DP init sequence
b46c2208ba4d drm/i915/tgl: Finish modular FIA
== Series Details ==
Series: series starting with [1/2] drm/i915: Future-proof DDC pin mapping
URL : https://patchwork.freedesktop.org/series/66887/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6917 -> Patchwork_14449
== Series Details ==
Series: drm/i915/tgl: Implement Wa_1406941453
URL : https://patchwork.freedesktop.org/series/66886/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6917 -> Patchwork_14448
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915: Add TigerLake bandwidth checking (rev3)
URL : https://patchwork.freedesktop.org/series/66817/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6915_full -> Patchwork_14443_full
Summary
Our assumption that the we can ask the HW to lock the SFC even if not
currently in use does not match the HW commitment. The expectation from
the HW is that SW will not try to lock the SFC if the engine is not
using it and if we do that the behavior is undefined; on ICL the HW
ends up to returning
On Wed, Sep 18, 2019 at 5:07 PM José Roberto de Souza
wrote:
>
> From: Clinton A Taylor
>
> Commit 24a7bfe0c2d7 ("drm/i915: Keep the TypeC port mode fixed when the
> port is active") added this new hook while in parallel TGL upstream was
> happening and this was missed.
>
> Without this driver
On Wed, Sep 18, 2019 at 5:07 PM José Roberto de Souza
wrote:
>
> If platform supports and has modular FIA is enabled, the registers
> bits also change, example: reading TC3 registers with modular FIA
> enabled, driver should read from FIA2 but with TC1 bits offsets.
>
> It is described in BSpec
On 2019-09-17 05:11:55, Radhakrishna Sripada wrote:
> return PLANE_CTL_TILED_Y |
> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> return PLANE_CTL_TILED_Y |
> PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
> @@ -9897,9
On Wed, 2019-09-18 at 16:56 -0700, Matt Roper wrote:
> The MCC hpd table is just a subset of the ICP table; we can eliminate
> it
> and use the ICP table everywhere. The extra pins in the table won't
> be
> a problem for MCC since we still supply an appropriate hotplug
> trigger
> mask anywhere
On Wed, 2019-09-18 at 16:56 -0700, Matt Roper wrote:
> We generally assume future platforms will inherit the behavior of the
> most recent platforms, so update our DDC pin mapping defaults to
> match
> how ICP/TGP behave (i.e., pins starting from GMBUS_PIN_1_BXT for
> combo
> PHY's and pins
On Thu, 2019-09-05 at 13:35 -0700, Matt Roper wrote:
> These new cdclk values should be accounted for in the voltage level
> selection (we can use the same voltage level as 307.2 and 312 rather
> than bumping up up to the next higher level).
Just checked this page and there is change draft in
From: Lucas De Marchi
The disable function can be the same as for MG phy since the same
registers are used. The others are different as registers changed,
also adding a empty dkl_pll_write() to be implemented later.
v2:
Setting the right HIP_INDEX_REG bits (José)
Signed-off-by: José Roberto de
From: Vandita Kulkarni
These are the registers needed to program Dekel phy. Some register
definitions will be reused from MG PHY definitions, so adding a
comment on those.
Bspec: 49295
Signed-off-by: Vandita Kulkarni
Signed-off-by: Clinton A Taylor
Signed-off-by: Lucas De Marchi
Extending ICL mg calculations to also support dkl calculations.
BSpec: 49204
Signed-off-by: Vandita Kulkarni
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi.c | 29 +++-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 148 +++---
2 files
Adding a enable parameters allow us to share most of the code between
enable and disable functions.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi.c | 71
1 file changed, 22 insertions(+), 49 deletions(-)
diff --git
From: Lucas De Marchi
Now that TC support was added, initialize DDIs.
Signed-off-by: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git
From: Vandita Kulkarni
Add a new function to write to dkl phy pll registers. As per the
bspec all the registers are read modify write.
Signed-off-by: Vandita Kulkarni
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 65
New step added for TGL, required for us to check the TC
microcontroller health after power on TC aux.
BSpec: 49294
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display_power.c | 13 +
1 file changed, 13 insertions(+)
diff --git
From: Clinton A Taylor
Added DKL Phy sequences and helpers functions to program voltage
swing, clock gating and dp mode.
It is not written in DP enabling sequence but "PHY Clockgating
programming" states that clock gating should be enabled after the
link training but doing so causes all the
Version 2 of https://patchwork.freedesktop.org/series/66695/
Most important change is the drop of the usage of the hardcoded table with the
registers values to DKL PLL registers, a bug in the calculation was fixed and
a step that is not on the BSpec was added to make it work on HW and match with
From: Clinton A Taylor
Step 4.b was complete missed because it is only required to TC and TBT.
Bspec: 49190
Signed-off-by: Clinton A Taylor
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
If platform supports and has modular FIA is enabled, the registers
bits also change, example: reading TC3 registers with modular FIA
enabled, driver should read from FIA2 but with TC1 bits offsets.
It is described in BSpec 50231 for DFLEXDPSP, other registers don't
have the BSpec description but
From: Clinton A Taylor
Commit 24a7bfe0c2d7 ("drm/i915: Keep the TypeC port mode fixed when the
port is active") added this new hook while in parallel TGL upstream was
happening and this was missed.
Without this driver will crash when TC DDI is added and driver is
preparing to do a full modeset.
Link training is failling when running link at 2.7GHz and 1.62GHz and
following BSpec pll algorithm.
Comparing the values calculated and the ones from the reference table
it looks like MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO should not always set
to 5. For DP ports ICL mg pll algorithm sets it to 10 or
From: Clinton A Taylor
Add a helper function to return pin map for use during dkl phy
DP_MODE settings, PORT_TX_DFLEXPA1 exist on ICL but we don't need it.
The user of this function will come in future TC patches.
Signed-off-by: Clinton A Taylor
Signed-off-by: José Roberto de Souza
---
We generally assume future platforms will inherit the behavior of the
most recent platforms, so update our DDC pin mapping defaults to match
how ICP/TGP behave (i.e., pins starting from GMBUS_PIN_1_BXT for combo
PHY's and pins starting from GMBUS_PIN_9_TC1_ICP for TC PHY's). MCC's
non-standard
The MCC hpd table is just a subset of the ICP table; we can eliminate it
and use the ICP table everywhere. The extra pins in the table won't be
a problem for MCC since we still supply an appropriate hotplug trigger
mask anywhere the pin table is used.
Cc: José Roberto de Souza
Signed-off-by:
Hi Daniele,
Thanks for the review. Can you help me merge this pathc?
Thanks,
Radhakrishna(RK) Sripada
> -Original Message-
> From: Ceraolo Spurio, Daniele
> Sent: Wednesday, September 11, 2019 11:12 AM
> To: Sripada, Radhakrishna ; intel-
> g...@lists.freedesktop.org
> Cc: Summers,
From: Michel Thierry
Enable Small PL for power benefit.
Signed-off-by: Michel Thierry
Signed-off-by: Lucas De Marchi
Reviewed-by: Stuart Summers
Reviewed-by: Radhakrishna Sripada
Link:
https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-18-lucas.demar...@intel.com
Link:
From: David Francis
With DSC, bpp can be fractional in multiples of 1/16.
Change drm_dp_calc_pbn_mode to reflect this, adding a new
parameter bool dsc. When this parameter is true, treat the
bpp parameter as having units not of bits per pixel, but
1/16 of a bit per pixel
v2: Don't add separate
On 9/18/19 10:31 AM, Stuart Summers wrote:
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110559
What's the planned usage here? TGL HW only supports slice-level
power-gating and with only 1 slice on TGL we don't really have a choice
of what to program, do we?
Daniele
Cc:
On Wed, 2019-09-18 at 19:31 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Allow set context SSEU on platforms after gen 11
> URL : https://patchwork.freedesktop.org/series/66870/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6917 ->
On Tue, 2019-09-10 at 09:13 +0100, Tvrtko Ursulin wrote:
> On 10/09/2019 05:53, Summers, Stuart wrote:
> > On Fri, 2019-09-06 at 19:13 +0100, Chris Wilson wrote:
> > > Quoting Tvrtko Ursulin (2019-09-02 14:42:44)
> > > >
> > > > On 24/07/2019 14:05, Tvrtko Ursulin wrote:
> > > > >
> > > > > On
On Wed, Sep 18, 2019 at 07:02:18PM +0300, Ville Syrjälä wrote:
> On Wed, Sep 18, 2019 at 11:24:09AM -0400, Sean Paul wrote:
> > On Wed, Sep 18, 2019 at 06:07:07PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Modern platforms allow the transcoders hdisplay/vdisplay to exceed
On Sat, 2019-09-14 at 00:26 -0700, Lucas De Marchi wrote:
> On Fri, Sep 13, 2019 at 3:33 PM José Roberto de Souza
> wrote:
> > It was always modifing register space of the first phy in the
> > HIP_INDEX_REG for all ports while it should shift 8 bits for each
> > port inside of HIP_INDEX_REG.
> >
== Series Details ==
Series: drm/i915: Allow set context SSEU on platforms after gen 11
URL : https://patchwork.freedesktop.org/series/66870/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6917 -> Patchwork_14447
Summary
== Series Details ==
Series: DSB enablement. (rev7)
URL : https://patchwork.freedesktop.org/series/63013/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6912_full -> Patchwork_14439_full
Summary
---
**SUCCESS**
No
On Wed, Sep 18, 2019 at 09:57:29AM +0200, Maarten Lankhorst wrote:
> Op 18-09-2019 om 02:33 schreef Manasi Navare:
> > After the state is committed, we readout the HW registers and compare
> > the HW state with the SW state that we just committed.
> > For Transcdoer port sync, we add
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On ILK-IVB the pipe colorspace is configured via PIPECONF
> (as opposed to PIPEMISC in BDW+). Let's configure+readout
> that stuff correctly.
>
> Enablling YCbCr 4:4:4 output will now be a simple matter of
Typo:
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On HSW the pipe colorspace is configured via PIPECONF
> (as opposed to PIPEMISC in BDW+). Let's configure+readout
> that stuff correctly.
>
> Enablling YCbCr 4:4:4 output will now be a simple matter of
Typo:
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Make intel_get_crtc_ycbcr_config() simpler and rename it
> to bdw_get_pipemisc_output_format() to better reflect what
> it does.
>
> Also toss in some comments to document that the 4:2:0 PIPECONF
> bits are glk+
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Now that we have standard defines for the MSA MISC bits lets use
> them on HSW+ where we program these directly into the TRANS_MSA_MISC
> register.
>
> Signed-off-by: Ville Syrjälä
> ---
>
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Since HSW the PIPECONF progressive vs. interlaced selection is done
> with just two bits instead of the earlier three. Let's not look at
> the
> extra bit on HSW+. Also gen2 doesn't support interlaced displays at
>
On Thu, 2019-07-18 at 19:45 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> crtc_state->limited_color_range only applies to RGB output but
> we're currently setting it even for YCbCr output. That will
> lead to conflicting MSA and PIPECONF settings which can mess
> up the image. Let's make
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Pull the code for computing the limited color range
> setting into a small helper. We'll add a bit more to it
> later.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 30
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Looks like we're currently setting the MSA to xvYCC BT.709 instead
> of the YCbCr BT.601 claimed by the comment. But even that comment
> is wrong since we configure the CSC matrix to BT.709.
>
> Let's remove the
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Add definitions for the MSA (Main Stream Attribute) MISC bits. On
> some hardware you can program these directly into a register.
>
> Signed-off-by: Ville Syrjälä
> ---
> include/drm/drm_dp_helper.h | 42
>
On Wed, Sep 18, 2019 at 09:11:36PM +0300, Ville Syrjälä wrote:
> On Wed, Sep 18, 2019 at 10:50:39AM -0700, Manasi Navare wrote:
> > On Wed, Sep 18, 2019 at 07:09:43AM +0530, srinivasa...@intel.com wrote:
> > > From: Srinivasan S
> > >
> > > This patch avoids DP MST payload error message in
On Wed, Sep 18, 2019 at 10:50:39AM -0700, Manasi Navare wrote:
> On Wed, Sep 18, 2019 at 07:09:43AM +0530, srinivasa...@intel.com wrote:
> > From: Srinivasan S
> >
> > This patch avoids DP MST payload error message in dmesg, as it is trying
> > to read the payload from the disconnected DP MST
Hi Dave, Daniel,
Here is a drm-misc-next-fixes PR, with two fixes that should go in
this current merge window.
Thanks!
Maxime
drm-misc-next-fixes-2019-09-18:
- One fix for the KMS object lifetime checks with DP drivers
- One revert for an ADV7511 probe breakage on older systems
The
On Wed, Sep 18, 2019 at 07:09:43AM +0530, srinivasa...@intel.com wrote:
> From: Srinivasan S
>
> This patch avoids DP MST payload error message in dmesg, as it is trying
> to read the payload from the disconnected DP MST device. After the unplug
> the connector status is disconnected and we
On Wed, 2019-09-18 at 11:23 +0530, Gaurav K Singh wrote:
> During S0ix/S3 suspend stress test on Cometlake chromebook,
> after few iterations we are seeing failure wrt PSR link CRC
> Error and stress test stops. This S0ix test is failing only
> when there is a CRC mismatch. In case of CRC
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110559
Cc: Tvrtko Ursulin
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
On Wed, Sep 18, 2019 at 11:21:01AM +0300, Lionel Landwerlin wrote:
On 16/09/2019 22:17, Umesh Nerlige Ramappa wrote:
On Sun, Sep 15, 2019 at 02:24:41PM +0300, Lionel Landwerlin wrote:
On 14/09/2019 02:06, Umesh Nerlige Ramappa wrote:
OA perf unit supports non-power of 2 report sizes. Enable
On Wed, Sep 18, 2019 at 04:16:28PM +0100, Chris Wilson wrote:
> drmConnectorFree is called inside the loop and after. Not unsurprisingly
> this leads to a use-after-free and memcorruption.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111710
> Signed-off-by: Chris Wilson
> Cc:
== Series Details ==
Series: series starting with [1/2] drm/i915: Bump skl+ max plane width to 5k
for linear/x-tiled (rev2)
URL : https://patchwork.freedesktop.org/series/66286/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6915 -> Patchwork_14446
On 18/09/2019 17:10, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-09-18 16:54:36)
On 17/09/2019 16:17, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-09-17 15:59:25)
On 16/09/2019 12:38, Chris Wilson wrote:
When using virtual engines, the rq->engine is not stable until we hold
the
On Wed, Sep 18, 2019 at 07:02:18PM +0300, Ville Syrjälä wrote:
> On Wed, Sep 18, 2019 at 11:24:09AM -0400, Sean Paul wrote:
> > On Wed, Sep 18, 2019 at 06:07:07PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Modern platforms allow the transcoders hdisplay/vdisplay to exceed
Quoting Chris Wilson (2019-09-18 17:10:26)
> Quoting Tvrtko Ursulin (2019-09-18 16:54:36)
> >
> > On 17/09/2019 16:17, Chris Wilson wrote:
> > > Quoting Tvrtko Ursulin (2019-09-17 15:59:25)
> > >>
> > >> On 16/09/2019 12:38, Chris Wilson wrote:
> > >>> When using virtual engines, the rq->engine
Quoting Tvrtko Ursulin (2019-09-18 16:54:36)
>
> On 17/09/2019 16:17, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-09-17 15:59:25)
> >>
> >> On 16/09/2019 12:38, Chris Wilson wrote:
> >>> When using virtual engines, the rq->engine is not stable until we hold
> >>> the engine->active.lock
On Wed, Sep 18, 2019 at 11:24:09AM -0400, Sean Paul wrote:
> On Wed, Sep 18, 2019 at 06:07:07PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Modern platforms allow the transcoders hdisplay/vdisplay to exceed the
> > planes' max resolution. This has the nasty implication that modes
== Series Details ==
Series: drm/i915/cml: Add second PCH ID for CMP (rev2)
URL : https://patchwork.freedesktop.org/series/66782/
State : failure
== Summary ==
Applying: drm/i915/cml: Add second PCH ID for CMP
Using index info to reconstruct a base tree...
M
On 17/09/2019 16:17, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-09-17 15:59:25)
On 16/09/2019 12:38, Chris Wilson wrote:
When using virtual engines, the rq->engine is not stable until we hold
the engine->active.lock (as the virtual engine may be exchanged with the
sibling). Since
== Series Details ==
Series: series starting with [1/4] drm/i915: Verify the engine after acquiring
the active.lock
URL : https://patchwork.freedesktop.org/series/66867/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6915 -> Patchwork_1
On Thu, Sep 05, 2019 at 04:50:43PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The officially validated plane width limit is 4k on skl+, however
> we already had people using 5k displays before we started to enforce
> the limit. Also it seems Windows allows 5k resolutions as well
>
On Wed, Sep 18, 2019 at 06:07:07PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Modern platforms allow the transcoders hdisplay/vdisplay to exceed the
> planes' max resolution. This has the nasty implication that modes on the
> connectors' mode list may not be usable when the user asks
drmConnectorFree is called inside the loop and after. Not unsurprisingly
this leads to a use-after-free and memcorruption.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111710
Signed-off-by: Chris Wilson
Cc: Manasi Navare
---
tests/kms_dp_tiled_display.c | 28
== Series Details ==
Series: series starting with [1/4] drm/i915: Verify the engine after acquiring
the active.lock
URL : https://patchwork.freedesktop.org/series/66867/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Verify the engine after
On Wed, Sep 18, 2019 at 10:51:54AM +0200, Maarten Lankhorst wrote:
> Op 17-09-2019 om 18:37 schreef Manasi Navare:
> > On Tue, Sep 17, 2019 at 05:04:28PM +0200, Maarten Lankhorst wrote:
> >> Op 09-09-2019 om 05:43 schreef Manasi Navare:
> >>> This clears the transcoder port sync bits of the
== Series Details ==
Series: series starting with [1/4] drm/i915: Verify the engine after acquiring
the active.lock
URL : https://patchwork.freedesktop.org/series/66867/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ddffe8da3c9b drm/i915: Verify the engine after acquiring the
From: Ville Syrjälä
Modern platforms allow the transcoders hdisplay/vdisplay to exceed the
planes' max resolution. This has the nasty implication that modes on the
connectors' mode list may not be usable when the user asks for a
fullscreen plane. Seeing as that is the most common use case it
On Wed, Sep 18, 2019 at 07:28:29AM -0700, Manasi Navare wrote:
> On Thu, Sep 05, 2019 at 04:50:44PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Modern platforms allow the transcoders hdisplay/vdisplay to exceed the
> > planes' max resolution. This has the nasty implication that
== Series Details ==
Series: drm/i915: Add TigerLake bandwidth checking (rev3)
URL : https://patchwork.freedesktop.org/series/66817/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6915 -> Patchwork_14443
Summary
---
The CMP PCH ID we have in the driver is correct for the CML-U machines
we have in our CI system, but the CML-S and CML-H CI machines appear to
use a different PCH ID, leading our driver to detect no PCH for them.
Cc: Rodrigo Vivi
Cc: Anusha Srivatsa
References: 729ae330a0f2e2 ("drm/i915/cml:
The request->timeline is only valid until the request is retired (i.e.
before it is completed). Upon retiring the request, the context may be
unpinned and freed, and along with it the timeline may be freed. We
therefore need to be very careful when chasing rq->timeline that the
pointer does not
As not only is the signal->timeline volatile, so will be acquiring the
timeline's HWSP. We must first carefully acquire the timeline from the
signaling request and then lock the timeline. With the removal of the
struct_mutex serialisation of request construction, we can have multiple
timelines
As we need to take a walk back along the signaler timeline to find the
fence before upon which we want to wait, we need to lock that timeline
to prevent it being modified as we walk. Similarly, we also need to
acquire a reference to the earlier fence while it still exists!
Though we lack the
When using virtual engines, the rq->engine is not stable until we hold
the engine->active.lock (as the virtual engine may be exchanged with the
sibling). Since commit 22b7a426bbe1 ("drm/i915/execlists: Preempt-to-busy")
we may retire a request concurrently with resubmitting it to HW, we need
to be
On Thu, Sep 05, 2019 at 04:50:44PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Modern platforms allow the transcoders hdisplay/vdisplay to exceed the
> planes' max resolution. This has the nasty implication that modes on the
> connectors' mode list may not be usable when the user asks
== Series Details ==
Series: drm/i915: Add TigerLake bandwidth checking (rev3)
URL : https://patchwork.freedesktop.org/series/66817/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2ff98c4e712a drm/i915: Add TigerLake bandwidth checking
-:31: WARNING:BRACES: braces {} are not
On Mon, Sep 16, 2019 at 10:11:45AM +0300, Gwan-gyeong Mun wrote:
> When BT.2020 Colorimetry output is used for DP, we should program BT.2020
> Colorimetry to MSA and VSC SDP. It adds output_colorspace to
> intel_crtc_state struct as a place holder of pipe's output colorspace.
> In order to
On Mon, Sep 16, 2019 at 10:11:49AM +0300, Gwan-gyeong Mun wrote:
> Function intel_dp_setup_hdr_metadata_infoframe_sdp handles Infoframe SDP
> header and data block setup for HDR Static Metadata. It enables writing of
> HDR metadata infoframe SDP to panel. Support for HDR video was introduced
> in
Op 05-09-2019 om 15:50 schreef Ville Syrjala:
> From: Ville Syrjälä
>
> The officially validated plane width limit is 4k on skl+, however
> we already had people using 5k displays before we started to enforce
> the limit. Also it seems Windows allows 5k resolutions as well
> (though not sure if
On Mon, Sep 16, 2019 at 10:11:46AM +0300, Gwan-gyeong Mun wrote:
> Because between HDMI and DP have different colorspaces, it renames
> drm_mode_create_colorspace_property() function to
> drm_mode_create_hdmi_colorspace_property() function for HDMI connector.
> And it adds
Op 05-09-2019 om 15:50 schreef Ville Syrjala:
> From: Ville Syrjälä
>
> Modern platforms allow the transcoders hdisplay/vdisplay to exceed the
> planes' max resolution. This has the nasty implication that modes on the
> connectors' mode list may not be usable when the user asks for a
> fullscreen
Hi All,
A gentle ping.
Andrzej
W dniu 26.08.2019 o 21:25, Andrzej Pietrasiewicz pisze:
I'm resending the patches which have somehow got lost: one patch
from Geert and 13 patches from me.
Geert's patch updates the error message to reflect the actually
called function's name.
Most of patches
On 18/09/2019 14:44, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-09-18 14:38:06)
On 17/09/2019 16:39, Chris Wilson wrote:
As we need to take a walk back along the signaler timeline to find the
fence before upon which we want to wait, we need to lock that timeline
to prevent it being
Quoting Tvrtko Ursulin (2019-09-18 14:38:06)
>
> On 17/09/2019 16:39, Chris Wilson wrote:
> > As we need to take a walk back along the signaler timeline to find the
> > fence before upon which we want to wait, we need to lock that timeline
> > to prevent it being modified as we walk. Similarly,
On 17/09/2019 19:29, Daniele Ceraolo Spurio wrote:
On 9/17/2019 3:22 AM, Tvrtko Ursulin wrote:
On 16/09/2019 22:41, Daniele Ceraolo Spurio wrote:
Our assumption that the we can ask the HW to lock the SFC even if not
currently in use does not match the HW commitment. The expectation from
On Mon, 2019-07-08 at 15:53 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Allow drivers to call drm_atomic_helper_check_modeset() without
> having the crtc helper funcs specified. i915 doesn't need those
> anymore.
>
> Signed-off-by: Ville Syrjälä
> ---
>
On 17/09/2019 16:39, Chris Wilson wrote:
As we need to take a walk back along the signaler timeline to find the
fence before upon which we want to wait, we need to lock that timeline
to prevent it being modified as we walk. Similarly, we also need to
acquire a reference to the earlier fence
Added bandwidth calculation algorithm and checks,
similar way as it was done for ICL, some constants
were corrected according to BSpec.
Signed-off-by: Stanislav Lisovskiy
v2: Start using same icl_get_bw_info function to avoid
code duplication. Moved mpagesize to memory info
related
On Wed, Sep 18, 2019 at 12:22:01PM +0300, Stanislav Lisovskiy wrote:
> Added bandwidth calculation algorithm and checks,
> similar way as it was done for ICL, some constants
> were corrected according to BSpec.
>
> Signed-off-by: Stanislav Lisovskiy
>
> v2: Start using same icl_get_bw_info
== Series Details ==
Series: drm/i915: Expose engine properties via sysfs (rev2)
URL : https://patchwork.freedesktop.org/series/66849/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bcb994854973 drm/i915: Expose engine properties via sysfs
-:36: WARNING:FILE_PATH_CHANGES:
== Series Details ==
Series: drm/i915: Fix S0ix/S3 suspend stress issue
URL : https://patchwork.freedesktop.org/series/66839/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6911_full -> Patchwork_14438_full
Summary
---
== Series Details ==
Series: drm/i915/dp: Fix DP MST error after unplugging TypeC cable
URL : https://patchwork.freedesktop.org/series/66837/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6911_full -> Patchwork_14437_full
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