[Intel-gfx] ✗ Fi.CI.IGT: failure for LMEM basics (rev3)
== Series Details ==
Series: LMEM basics (rev3)
URL : https://patchwork.freedesktop.org/series/67350/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7011_full -> Patchwork_14674_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14674_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14674_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14674_full:
### IGT changes ###
Possible regressions
* igt@gem_ctx_isolation@vecs0-dirty-switch:
- shard-skl: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-skl8/igt@gem_ctx_isolat...@vecs0-dirty-switch.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14674/shard-skl3/igt@gem_ctx_isolat...@vecs0-dirty-switch.html
* igt@i915_selftest@live_hangcheck:
- shard-hsw: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-hsw7/igt@i915_selftest@live_hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14674/shard-hsw6/igt@i915_selftest@live_hangcheck.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_ctx_isolation@vcs2-dirty-create:
- {shard-tglb}: NOTRUN -> [SKIP][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14674/shard-tglb6/igt@gem_ctx_isolat...@vcs2-dirty-create.html
New tests
-
New tests have been introduced between CI_DRM_7011_full and
Patchwork_14674_full:
### New IGT tests (2) ###
* igt@i915_selftest@live_memory_region:
- Statuses : 8 pass(s)
- Exec time: [0.36, 2.27] s
* igt@i915_selftest@mock_memory_region:
- Statuses : 8 pass(s)
- Exec time: [0.97, 15.48] s
Known issues
Here are the changes found in Patchwork_14674_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: [PASS][6] -> [DMESG-WARN][7] ([fdo#108566]) +7
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-apl3/igt@gem_ctx_isolat...@rcs0-s3.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14674/shard-apl6/igt@gem_ctx_isolat...@rcs0-s3.html
* igt@gem_exec_schedule@preempt-contexts-bsd2:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#109276]) +14 similar
issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-iclb2/igt@gem_exec_sched...@preempt-contexts-bsd2.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14674/shard-iclb5/igt@gem_exec_sched...@preempt-contexts-bsd2.html
* igt@gem_exec_schedule@preempt-queue-contexts-bsd:
- shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#111325]) +1 similar
issue
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-iclb6/igt@gem_exec_sched...@preempt-queue-contexts-bsd.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14674/shard-iclb2/igt@gem_exec_sched...@preempt-queue-contexts-bsd.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-snb: [PASS][12] -> [DMESG-WARN][13] ([fdo#111870])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-snb1/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14674/shard-snb4/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-hsw: [PASS][14] -> [FAIL][15] ([fdo#103355])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-hsw8/igt@kms_cursor_leg...@cursor-vs-flip-toggle.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14674/shard-hsw6/igt@kms_cursor_leg...@cursor-vs-flip-toggle.html
* igt@kms_cursor_legacy@pipe-c-single-bo:
- shard-iclb: [PASS][16] -> [INCOMPLETE][17] ([fdo#107713]) +1
similar issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-iclb8/igt@kms_cursor_leg...@pipe-c-single-bo.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14674/shard-iclb7/igt@kms_cursor_leg...@pipe-c-single-bo.html
* igt@kms_flip@dpms-vs-vblank-race-interruptible:
- shard-apl: [PASS][18] -> [INCOMPLETE][19] ([fdo#103927]) +2
similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-apl7/igt@kms_f...@dpms-vs-vblank-race-interruptible.html
[19]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/4] drm/edid: Make drm_get_cea_aspect_ratio() static
== Series Details ==
Series: series starting with [1/4] drm/edid: Make drm_get_cea_aspect_ratio()
static
URL : https://patchwork.freedesktop.org/series/67600/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7011_full -> Patchwork_14671_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14671_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14671_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14671_full:
### IGT changes ###
Possible regressions
* igt@gem_ctx_isolation@vcs0-dirty-switch:
- shard-apl: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-apl2/igt@gem_ctx_isolat...@vcs0-dirty-switch.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14671/shard-apl1/igt@gem_ctx_isolat...@vcs0-dirty-switch.html
* igt@gem_ctx_isolation@vcs0-s3:
- shard-kbl: [PASS][3] -> [FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-kbl1/igt@gem_ctx_isolat...@vcs0-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14671/shard-kbl4/igt@gem_ctx_isolat...@vcs0-s3.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_cursor_edge_walk@pipe-c-128x128-left-edge:
- {shard-tglb}: [PASS][5] -> [INCOMPLETE][6] +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-tglb3/igt@kms_cursor_edge_w...@pipe-c-128x128-left-edge.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14671/shard-tglb5/igt@kms_cursor_edge_w...@pipe-c-128x128-left-edge.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render:
- {shard-tglb}: NOTRUN -> [INCOMPLETE][7] +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14671/shard-tglb5/igt@kms_frontbuffer_track...@fbc-rgb565-draw-render.html
New tests
-
New tests have been introduced between CI_DRM_7011_full and
Patchwork_14671_full:
### New Piglit tests (1) ###
* spec@glsl-1.20@execution@tex-miplevel-selection gl2:texture(bias) 3d:
- Statuses : 1 fail(s)
- Exec time: [8.64] s
Known issues
Here are the changes found in Patchwork_14671_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@bcs0-s3:
- shard-apl: [PASS][8] -> [DMESG-WARN][9] ([fdo#108566]) +3
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-apl4/igt@gem_ctx_isolat...@bcs0-s3.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14671/shard-apl6/igt@gem_ctx_isolat...@bcs0-s3.html
* igt@gem_exec_schedule@preempt-contexts-bsd2:
- shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#109276]) +12 similar
issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-iclb2/igt@gem_exec_sched...@preempt-contexts-bsd2.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14671/shard-iclb3/igt@gem_exec_sched...@preempt-contexts-bsd2.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#111325]) +5 similar
issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-iclb8/igt@gem_exec_sched...@reorder-wide-bsd.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14671/shard-iclb2/igt@gem_exec_sched...@reorder-wide-bsd.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-hsw: [PASS][14] -> [DMESG-WARN][15] ([fdo#111870])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-hsw1/igt@gem_userptr_bl...@dmabuf-unsync.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14671/shard-hsw6/igt@gem_userptr_bl...@dmabuf-unsync.html
* igt@i915_selftest@live_hangcheck:
- shard-snb: [PASS][16] -> [INCOMPLETE][17] ([fdo#105411])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-snb6/igt@i915_selftest@live_hangcheck.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14671/shard-snb7/igt@i915_selftest@live_hangcheck.html
* igt@i915_suspend@debugfs-reader:
- shard-skl: [PASS][18] -> [INCOMPLETE][19] ([fdo#104108] /
[fdo#111867])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-skl10/igt@i915_susp...@debugfs-reader.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14671/shard-skl8/igt@i915_susp...@debugfs-reader.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-hsw: [PASS][20] -> [DMESG-WARN][21]
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: customize DPCD brightness control for specific panel
== Series Details ==
Series: drm/i915: customize DPCD brightness control for specific panel
URL : https://patchwork.freedesktop.org/series/67595/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7011_full -> Patchwork_14670_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14670_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14670_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14670_full:
### IGT changes ###
Possible regressions
* igt@gem_ctx_isolation@vcs0-dirty-switch:
- shard-apl: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-apl2/igt@gem_ctx_isolat...@vcs0-dirty-switch.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14670/shard-apl2/igt@gem_ctx_isolat...@vcs0-dirty-switch.html
* igt@gem_ctx_isolation@vcs0-s3:
- shard-kbl: [PASS][3] -> [FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-kbl1/igt@gem_ctx_isolat...@vcs0-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14670/shard-kbl7/igt@gem_ctx_isolat...@vcs0-s3.html
* igt@gem_ctx_isolation@vecs0-dirty-switch:
- shard-skl: [PASS][5] -> [FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-skl8/igt@gem_ctx_isolat...@vecs0-dirty-switch.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14670/shard-skl1/igt@gem_ctx_isolat...@vecs0-dirty-switch.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_ctx_isolation@bcs0-s3:
- {shard-tglb}: NOTRUN -> [INCOMPLETE][7]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14670/shard-tglb7/igt@gem_ctx_isolat...@bcs0-s3.html
* igt@gem_exec_nop@basic-parallel:
- {shard-tglb}: [PASS][8] -> [INCOMPLETE][9] +2 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-tglb7/igt@gem_exec_...@basic-parallel.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14670/shard-tglb8/igt@gem_exec_...@basic-parallel.html
Known issues
Here are the changes found in Patchwork_14670_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_eio@reset-stress:
- shard-snb: [PASS][10] -> [FAIL][11] ([fdo#109661])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-snb2/igt@gem_...@reset-stress.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14670/shard-snb2/igt@gem_...@reset-stress.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#111325]) +7 similar
issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-iclb8/igt@gem_exec_sched...@reorder-wide-bsd.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14670/shard-iclb1/igt@gem_exec_sched...@reorder-wide-bsd.html
* igt@gem_softpin@noreloc-interruptible:
- shard-apl: [PASS][14] -> [INCOMPLETE][15] ([fdo#103927]) +1
similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-apl3/igt@gem_soft...@noreloc-interruptible.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14670/shard-apl1/igt@gem_soft...@noreloc-interruptible.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-snb: [PASS][16] -> [DMESG-WARN][17] ([fdo#111870])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-snb1/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14670/shard-snb2/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][18] -> [FAIL][19] ([fdo#105363])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-skl9/igt@kms_f...@flip-vs-expired-vblank.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14670/shard-skl8/igt@kms_f...@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack:
- shard-snb: [PASS][20] -> [SKIP][21] ([fdo#109271]) +1 similar
issue
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/shard-snb1/igt@kms_frontbuffer_track...@fbc-1p-shrfb-fliptrack.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14670/shard-snb6/igt@kms_frontbuffer_track...@fbc-1p-shrfb-fliptrack.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite:
- shard-iclb:
Re: [Intel-gfx] [PATCH v3 11/11] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
On Fri, Oct 04, 2019 at 05:17:07PM -0700, Dhinakaran Pandiyan wrote:
> On Fri, 2019-10-04 at 16:52 -0700, Matt Roper wrote:
> > On Fri, Sep 27, 2019 at 03:28:37PM -0700, Radhakrishna Sripada wrote:
> > > Render Decompression is supported with Y-Tiled main surface. The CCS is
> > > linear and has 4 bits of data for each main surface cache line pair, a
> > > ratio of 1:256. Additional Clear Color information is passed from the
> > > user-space through an offset in the GEM BO. Add a new modifier to identify
> > > and parse new Clear Color information and extend Gen12 render
> > > decompression
> > > functionality to the newly added modifier.
> > >
> > > v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
> > > plane config(Matt). Fix Lookup error.
> > > v3: Fix the panic while running kms_cube
> > >
> > > Cc: Dhinakaran Pandiyan
> > > Cc: Ville Syrjala
> > > Cc: Shashank Sharma
> > > Cc: Rafael Antognolli
> > > Cc: Matt Roper
> > > Cc: Nanley G Chery
> > > Signed-off-by: Radhakrishna Sripada
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 52 +++
> > > .../drm/i915/display/intel_display_types.h| 3 ++
> > > drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++-
> > > drivers/gpu/drm/i915/i915_reg.h | 12 +
> > > 4 files changed, 77 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 4971c296f951..822237e98f00 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -1919,6 +1919,10 @@ intel_tile_width_bytes(const struct
> > > drm_framebuffer *fb, int color_plane)
> > > if (color_plane == 1)
> > > return 64;
> > > /* fall through */
> > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > + if (color_plane == 1 || color_plane == 2)
> > > + return 64;
> > > + /* fall through */
> > > case I915_FORMAT_MOD_Y_TILED:
> > > if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
> > > return 128;
> > > @@ -2060,6 +2064,7 @@ static unsigned int intel_surf_alignment(const
> > > struct drm_framebuffer *fb,
> > > return 256 * 1024;
> > > return 0;
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > return 16 * 1024;
> > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > > @@ -2265,6 +2270,8 @@ static bool is_surface_linear(u64 modifier, int
> > > color_plane)
> > > return true;
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > > return color_plane == 1;
> > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > + return color_plane == 1 || color_plane == 2;
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > > return color_plane == 1 || color_plane == 3;
> > > default:
> > > @@ -2458,6 +2465,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
> > > fb_modifier)
> > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > return I915_TILING_Y;
> > > default:
> > > return I915_TILING_NONE;
> > > @@ -2511,6 +2519,25 @@ static const struct drm_format_info
> > > gen12_ccs_formats[] = {
> > > .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
> > > };
> > >
> > > +/*
> > > + * Gen-12 compression uses 4 bits of CCS data for each cache line pair
> > > in the
> > > + * main surface. And each 64B CCS cache line represents an area of 4x1
> > > Y-tiles
> > > + * in the main surface. With 4 byte pixels and each Y-tile having
> > > dimensions of
> > > + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32
> > > pixels in
> > > + * the main surface. Additional surface is used to pass the Clear Color
> > > + * structure for the driver to program the DE.
> > > + */
> >
> > Rather than duplicating the previous comment's text I'd just say
> >
> > "Same as gen12_ccs_formats[] above, but with an additional surface used
> > to pass..."
> >
> > > +static const struct drm_format_info gen12_ccs_cc_formats[] = {
> > > + { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 3,
> > > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> > > + { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 3,
> > > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> > > + { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 3,
> > > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> > > + { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 3,
> > > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> > > +};
> > > +
> > >
Re: [Intel-gfx] [PATCH v3 11/11] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
On Fri, 2019-10-04 at 16:52 -0700, Matt Roper wrote:
> On Fri, Sep 27, 2019 at 03:28:37PM -0700, Radhakrishna Sripada wrote:
> > Render Decompression is supported with Y-Tiled main surface. The CCS is
> > linear and has 4 bits of data for each main surface cache line pair, a
> > ratio of 1:256. Additional Clear Color information is passed from the
> > user-space through an offset in the GEM BO. Add a new modifier to identify
> > and parse new Clear Color information and extend Gen12 render decompression
> > functionality to the newly added modifier.
> >
> > v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
> > plane config(Matt). Fix Lookup error.
> > v3: Fix the panic while running kms_cube
> >
> > Cc: Dhinakaran Pandiyan
> > Cc: Ville Syrjala
> > Cc: Shashank Sharma
> > Cc: Rafael Antognolli
> > Cc: Matt Roper
> > Cc: Nanley G Chery
> > Signed-off-by: Radhakrishna Sripada
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 52 +++
> > .../drm/i915/display/intel_display_types.h| 3 ++
> > drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++-
> > drivers/gpu/drm/i915/i915_reg.h | 12 +
> > 4 files changed, 77 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 4971c296f951..822237e98f00 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1919,6 +1919,10 @@ intel_tile_width_bytes(const struct drm_framebuffer
> > *fb, int color_plane)
> > if (color_plane == 1)
> > return 64;
> > /* fall through */
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > + if (color_plane == 1 || color_plane == 2)
> > + return 64;
> > + /* fall through */
> > case I915_FORMAT_MOD_Y_TILED:
> > if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
> > return 128;
> > @@ -2060,6 +2064,7 @@ static unsigned int intel_surf_alignment(const struct
> > drm_framebuffer *fb,
> > return 256 * 1024;
> > return 0;
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > return 16 * 1024;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > @@ -2265,6 +2270,8 @@ static bool is_surface_linear(u64 modifier, int
> > color_plane)
> > return true;
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > return color_plane == 1;
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > + return color_plane == 1 || color_plane == 2;
> > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > return color_plane == 1 || color_plane == 3;
> > default:
> > @@ -2458,6 +2465,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
> > fb_modifier)
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > return I915_TILING_Y;
> > default:
> > return I915_TILING_NONE;
> > @@ -2511,6 +2519,25 @@ static const struct drm_format_info
> > gen12_ccs_formats[] = {
> > .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
> > };
> >
> > +/*
> > + * Gen-12 compression uses 4 bits of CCS data for each cache line pair in
> > the
> > + * main surface. And each 64B CCS cache line represents an area of 4x1
> > Y-tiles
> > + * in the main surface. With 4 byte pixels and each Y-tile having
> > dimensions of
> > + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32
> > pixels in
> > + * the main surface. Additional surface is used to pass the Clear Color
> > + * structure for the driver to program the DE.
> > + */
>
> Rather than duplicating the previous comment's text I'd just say
>
> "Same as gen12_ccs_formats[] above, but with an additional surface used
> to pass..."
>
> > +static const struct drm_format_info gen12_ccs_cc_formats[] = {
> > + { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 3,
> > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> > + { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 3,
> > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> > + { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 3,
> > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> > + { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 3,
> > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> > +};
> > +
> > static const struct drm_format_info *
> > lookup_format_info(const struct drm_format_info formats[],
> >int num_formats, u32 format)
> > @@ -2538,6 +2565,10 @@ intel_get_format_info(const struct
Re: [Intel-gfx] [PATCH v2 10/11] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
On Mon, 2019-09-23 at 17:03 -0700, Radhakrishna Sripada wrote:
> Gen12 display can decompress surfaces compressed by render engine with Clear
> Color, add
> a new modifier as the driver needs to know the surface was compressed by
> render engine.
>
> V2: Description changes as suggested by Rafael.
>
> Cc: Ville Syrjala
> Cc: Dhinakaran Pandiyan
> Cc: Kalyan Kondapally
> Cc: Rafael Antognolli
> Cc: Nanley Chery
> Signed-off-by: Radhakrishna Sripada
> ---
> include/uapi/drm/drm_fourcc.h | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index c4a4e0fdbee5..99c61ee9b61f 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -434,6 +434,17 @@ extern "C" {
> */
> #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
>
> +/*
> + * Intel color control surfaces Clear Color(CCS_CC) for Gen-12 render
> compression.
> + *
> + * The main surface is Y-tiled and is at plane index 0 whereas CCS_CC is
> linear
> + * and at index 1.
Clear color data is fixed size - 64b, that should be in the documentation here.
> The clear color is stored at index 2, and the pitch should
> + * be ignored. A CCS_CC cache line corresponds to an area of 4x1 tiles in the
That's a CCS cache line, not a CCS_CC cache line, right?
> + * main surface. The main surface pitch is required to be a multiple of 4
> tile
> + * widths.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> +
> /*
> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> *
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 9/9] Gen-12 display can decompress surfaces compressed by the media engine.
On Fri, 2019-10-04 at 18:36 +0300, Ville Syrjälä wrote:
> On Thu, Sep 26, 2019 at 03:55:12AM -0700, Dhinakaran Pandiyan wrote:
> > Detect the modifier corresponding to media compression to enable
> > display decompression for YUV and xRGB packed formats. A new modifier is
> > added so that the driver can distinguish between media and render
> > compressed buffers. Unlike render decompression, plane 6 and plane 7 do not
> > support media decompression.
> >
> > v2: Fix checkpatch warnings on code style (Lucas)
> >
> > From DK:
> > Separate modifier array for planes that cannot decompress media (Ville)
> >
> > v3: Support planar formats
> > v4: Switch plane order
> >
> > Cc: Nanley G Chery
> > Cc: Ville Syrjälä
> > Cc: Matt Roper
> > Signed-off-by: Dhinakaran Pandiyan
> > Signed-off-by: Lucas De Marchi
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 290 +-
> > .../drm/i915/display/intel_display_types.h| 2 +-
> > drivers/gpu/drm/i915/display/intel_sprite.c | 55 +++-
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 4 files changed, 267 insertions(+), 81 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 8ea55d67442c..df3ebaa167ab 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1888,6 +1888,22 @@ static void intel_disable_pipe(const struct
> > intel_crtc_state
> > *old_crtc_state)
> > intel_wait_for_pipe_off(old_crtc_state);
> > }
> >
> > +bool is_ccs_modifier(u64 modifier)
> > +{
> > + return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> > + modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > + modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > +}
> > +
> > +static bool is_ccs_plane(const struct drm_framebuffer *fb, int color_plane)
> > +{
> > + if (!is_ccs_modifier(fb->modifier))
> > + return false;
>
> A comment here could help clarify things for the reader. Eg.:
> /*
> * [0] RGB
> * [1] RGB CCS
> * or
> * [0] Y
> * [1] CbCr
> * [2] Y CCS
> * [3] CbCr CCS
> */
>
Will do.
> > +
> > + return color_plane >= fb->format->num_planes / 2;
> > +}
> > +
> > static unsigned int intel_tile_size(const struct drm_i915_private
> > *dev_priv)
> > {
> > return IS_GEN(dev_priv, 2) ? 2048 : 4096;
> > @@ -1908,11 +1924,13 @@ intel_tile_width_bytes(const struct drm_framebuffer
> > *fb, int
> > color_plane)
> > else
> > return 512;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > - if (color_plane == 1)
> > + if (is_ccs_plane(fb, color_plane))
> > return 128;
> > /* fall through */
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > + /* fall through */
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > - if (color_plane == 1)
> > + if (is_ccs_plane(fb, color_plane))
> > return 64;
> > /* fall through */
> > case I915_FORMAT_MOD_Y_TILED:
> > @@ -1921,7 +1939,7 @@ intel_tile_width_bytes(const struct drm_framebuffer
> > *fb, int color_plane)
> > else
> > return 512;
> > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > - if (color_plane == 1)
> > + if (is_ccs_plane(fb, color_plane))
> > return 128;
> > /* fall through */
> > case I915_FORMAT_MOD_Yf_TILED:
> > @@ -1949,8 +1967,9 @@ static unsigned int
> > intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
> > {
> > switch (fb->modifier) {
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > - if (color_plane == 1)
> > + if (is_ccs_plane(fb, color_plane))
> > return 1;
> > /* fall through */
> > default:
> > @@ -2055,6 +2074,7 @@ static unsigned int intel_surf_alignment(const struct
> > drm_framebuffer *fb,
> > if (INTEL_GEN(dev_priv) >= 9)
> > return 256 * 1024;
> > return 0;
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > return 16 * 1024;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > @@ -2254,10 +2274,17 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
> > return new_offset;
> > }
> >
> > -static bool is_surface_linear(u64 modifier, int color_plane)
> > +static bool is_surface_linear(const struct drm_framebuffer *fb, int
> > color_plane)
> > {
> > - return modifier == DRM_FORMAT_MOD_LINEAR ||
> > - (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane
> > == 1);
> > + switch (fb->modifier) {
> > + case DRM_FORMAT_MOD_LINEAR:
> > + return true;
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>
Re: [Intel-gfx] [PATCH v3 11/11] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
On Fri, Sep 27, 2019 at 03:28:37PM -0700, Radhakrishna Sripada wrote:
> Render Decompression is supported with Y-Tiled main surface. The CCS is
> linear and has 4 bits of data for each main surface cache line pair, a
> ratio of 1:256. Additional Clear Color information is passed from the
> user-space through an offset in the GEM BO. Add a new modifier to identify
> and parse new Clear Color information and extend Gen12 render decompression
> functionality to the newly added modifier.
>
> v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
> plane config(Matt). Fix Lookup error.
> v3: Fix the panic while running kms_cube
>
> Cc: Dhinakaran Pandiyan
> Cc: Ville Syrjala
> Cc: Shashank Sharma
> Cc: Rafael Antognolli
> Cc: Matt Roper
> Cc: Nanley G Chery
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 52 +++
> .../drm/i915/display/intel_display_types.h| 3 ++
> drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++-
> drivers/gpu/drm/i915/i915_reg.h | 12 +
> 4 files changed, 77 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 4971c296f951..822237e98f00 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1919,6 +1919,10 @@ intel_tile_width_bytes(const struct drm_framebuffer
> *fb, int color_plane)
> if (color_plane == 1)
> return 64;
> /* fall through */
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> + if (color_plane == 1 || color_plane == 2)
> + return 64;
> + /* fall through */
> case I915_FORMAT_MOD_Y_TILED:
> if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
> return 128;
> @@ -2060,6 +2064,7 @@ static unsigned int intel_surf_alignment(const struct
> drm_framebuffer *fb,
> return 256 * 1024;
> return 0;
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return 16 * 1024;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> @@ -2265,6 +2270,8 @@ static bool is_surface_linear(u64 modifier, int
> color_plane)
> return true;
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> return color_plane == 1;
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> + return color_plane == 1 || color_plane == 2;
> case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> return color_plane == 1 || color_plane == 3;
> default:
> @@ -2458,6 +2465,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
> fb_modifier)
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return I915_TILING_Y;
> default:
> return I915_TILING_NONE;
> @@ -2511,6 +2519,25 @@ static const struct drm_format_info
> gen12_ccs_formats[] = {
> .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
> };
>
> +/*
> + * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
> + * main surface. And each 64B CCS cache line represents an area of 4x1
> Y-tiles
> + * in the main surface. With 4 byte pixels and each Y-tile having dimensions
> of
> + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32
> pixels in
> + * the main surface. Additional surface is used to pass the Clear Color
> + * structure for the driver to program the DE.
> + */
Rather than duplicating the previous comment's text I'd just say
"Same as gen12_ccs_formats[] above, but with an additional surface used
to pass..."
> +static const struct drm_format_info gen12_ccs_cc_formats[] = {
> + { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 3,
> + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> + { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 3,
> + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> + { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 3,
> + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> + { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 3,
> + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> +};
> +
> static const struct drm_format_info *
> lookup_format_info(const struct drm_format_info formats[],
> int num_formats, u32 format)
> @@ -2538,6 +2565,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2
> *cmd)
> return lookup_format_info(gen12_ccs_formats,
> ARRAY_SIZE(gen12_ccs_formats),
>
Re: [Intel-gfx] [PATCH v4 9/9] Gen-12 display can decompress surfaces compressed by the media engine.
On Fri, 2019-10-04 at 13:27 -0700, Matt Roper wrote:
> On Thu, Sep 26, 2019 at 03:55:12AM -0700, Dhinakaran Pandiyan wrote:
> > Detect the modifier corresponding to media compression to enable
> > display decompression for YUV and xRGB packed formats. A new modifier is
> > added so that the driver can distinguish between media and render
> > compressed buffers. Unlike render decompression, plane 6 and plane 7 do not
> > support media decompression.
> >
> > v2: Fix checkpatch warnings on code style (Lucas)
> >
> > From DK:
> > Separate modifier array for planes that cannot decompress media (Ville)
> >
> > v3: Support planar formats
> > v4: Switch plane order
> >
> > Cc: Nanley G Chery
> > Cc: Ville Syrjälä
> > Cc: Matt Roper
> > Signed-off-by: Dhinakaran Pandiyan
> > Signed-off-by: Lucas De Marchi
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 290 +-
> > .../drm/i915/display/intel_display_types.h| 2 +-
> > drivers/gpu/drm/i915/display/intel_sprite.c | 55 +++-
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 4 files changed, 267 insertions(+), 81 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 8ea55d67442c..df3ebaa167ab 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1888,6 +1888,22 @@ static void intel_disable_pipe(const struct
> > intel_crtc_state
> > *old_crtc_state)
> > intel_wait_for_pipe_off(old_crtc_state);
> > }
> >
> > +bool is_ccs_modifier(u64 modifier)
> > +{
> > + return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> > + modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > + modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > +}
> > +
> > +static bool is_ccs_plane(const struct drm_framebuffer *fb, int color_plane)
> > +{
> > + if (!is_ccs_modifier(fb->modifier))
> > + return false;
> > +
> > + return color_plane >= fb->format->num_planes / 2;
> > +}
>
> This appears to contradict what you indicated on the modifier patch:
>
> + * Y-tile widths. For semi-planar formats like NV12, CCS plane follows the
> + * Y and UV planes i.e., planes 0 and 2 are used for Y and UV surfaces,
> + * planes 1 and 3 for the respective CCS.
>
> Based on that comment I'd expect something more like (color_plane % 2).
I need to update the comment in the modifier patch, thanks for catching this.
The major change in
this version is
for planar formats: planes 2 and 3 will be used for CCS instead of 1 and 3.
for packed formats: plane 1 will be used for CCS
>
>
> > +
> > static unsigned int intel_tile_size(const struct drm_i915_private
> > *dev_priv)
> > {
> > return IS_GEN(dev_priv, 2) ? 2048 : 4096;
> > @@ -1908,11 +1924,13 @@ intel_tile_width_bytes(const struct drm_framebuffer
> > *fb, int
> > color_plane)
> > else
> > return 512;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > - if (color_plane == 1)
> > + if (is_ccs_plane(fb, color_plane))
> > return 128;
> > /* fall through */
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > + /* fall through */
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > - if (color_plane == 1)
> > + if (is_ccs_plane(fb, color_plane))
> > return 64;
> > /* fall through */
> > case I915_FORMAT_MOD_Y_TILED:
> > @@ -1921,7 +1939,7 @@ intel_tile_width_bytes(const struct drm_framebuffer
> > *fb, int color_plane)
> > else
> > return 512;
> > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > - if (color_plane == 1)
> > + if (is_ccs_plane(fb, color_plane))
> > return 128;
> > /* fall through */
> > case I915_FORMAT_MOD_Yf_TILED:
> > @@ -1949,8 +1967,9 @@ static unsigned int
> > intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
> > {
> > switch (fb->modifier) {
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > - if (color_plane == 1)
> > + if (is_ccs_plane(fb, color_plane))
> > return 1;
> > /* fall through */
> > default:
> > @@ -2055,6 +2074,7 @@ static unsigned int intel_surf_alignment(const struct
> > drm_framebuffer *fb,
> > if (INTEL_GEN(dev_priv) >= 9)
> > return 256 * 1024;
> > return 0;
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > return 16 * 1024;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > @@ -2254,10 +2274,17 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
> > return new_offset;
> > }
> >
> > -static bool is_surface_linear(u64
[Intel-gfx] [PATCH v3 2/2] drm/i915/tgl: Read SAGV block time from PCODE
Starting from TGL, we now need to read the SAGV block time via a PCODE
mailbox, rather than having a static value.
BSpec: 49326
v2: Fix up pcode val data type (Ville), tighten variable scope (Ville)
Cc: Ville Syrjälä
Cc: Stanislav Lisovskiy
Cc: Lucas De Marchi
Signed-off-by: James Ausmus
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 15 ++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6d67bd238cfe..030f0c37f64b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8870,6 +8870,7 @@ enum {
#define GEN9_SAGV_DISABLE 0x0
#define GEN9_SAGV_IS_DISABLED 0x1
#define GEN9_SAGV_ENABLE 0x3
+#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US0x23
#define GEN6_PCODE_DATA_MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0ffcafe97216..e2aca3e81d28 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3645,7 +3645,20 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
static void
skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
{
- if (IS_GEN(dev_priv, 11)) {
+ if (INTEL_GEN(dev_priv) >= 12) {
+ u32 val = 0;
+ int ret;
+
+ ret = sandybridge_pcode_read(dev_priv,
+
GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
+, NULL);
+ if (!ret) {
+ dev_priv->sagv_block_time_us = val;
+ return;
+ }
+
+ DRM_DEBUG_DRIVER("Couldn't read SAGV block time!\n");
+ } else if (IS_GEN(dev_priv, 11)) {
dev_priv->sagv_block_time_us = 10;
return;
} else if (IS_GEN(dev_priv, 10)) {
--
2.22.1
___
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[Intel-gfx] [PATCH v3 1/2] drm/i915: Move SAGV block time to dev_priv
In prep for newer platforms having more complicated ways to determine
the SAGV block time, move the variable to dev_priv, and extract the
setting to an initial setup function. While we're at it, update the if
ladder to follow the new gen -> old gen order preference, and warn on
any non-specified gen.
v2: Shorten the function name (Ville), return directly (Ville), move
sagv_block_time_us value to dev_priv (Ville)
v3: Change sagv_block_time_us to u32 (Lucas), Change fallback value to
-1 (Lucas), use intel_has_sagv for setup check rather than hand-rolling
(Lucas)
Cc: Ville Syrjälä
Cc: Stanislav Lisovskiy
Cc: Lucas De Marchi
Signed-off-by: James Ausmus
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 33 -
2 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cde4c7fb5570..1d9a9e827261 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1560,6 +1560,8 @@ struct drm_i915_private {
I915_SAGV_NOT_CONTROLLED
} sagv_status;
+ u32 sagv_block_time_us;
+
struct {
/*
* Raw watermark latency values:
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bfcf03ab5245..0ffcafe97216 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3642,6 +3642,26 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
}
+static void
+skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
+{
+ if (IS_GEN(dev_priv, 11)) {
+ dev_priv->sagv_block_time_us = 10;
+ return;
+ } else if (IS_GEN(dev_priv, 10)) {
+ dev_priv->sagv_block_time_us = 20;
+ return;
+ } else if (IS_GEN(dev_priv, 9)) {
+ dev_priv->sagv_block_time_us = 30;
+ return;
+ } else {
+ MISSING_CASE(INTEL_GEN(dev_priv));
+ }
+
+ /* Default to an unusable block time */
+ dev_priv->sagv_block_time_us = -1;
+}
+
/*
* SAGV dynamically adjusts the system agent voltage and clock frequencies
* depending on power and performance requirements. The display engine access
@@ -3730,18 +3750,10 @@ bool intel_can_enable_sagv(struct intel_atomic_state
*state)
struct intel_crtc_state *crtc_state;
enum pipe pipe;
int level, latency;
- int sagv_block_time_us;
if (!intel_has_sagv(dev_priv))
return false;
- if (IS_GEN(dev_priv, 9))
- sagv_block_time_us = 30;
- else if (IS_GEN(dev_priv, 10))
- sagv_block_time_us = 20;
- else
- sagv_block_time_us = 10;
-
/*
* If there are no active CRTCs, no additional checks need be performed
*/
@@ -3788,7 +3800,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state
*state)
* incur memory latencies higher than sagv_block_time_us we
* can't enable SAGV.
*/
- if (latency < sagv_block_time_us)
+ if (latency < dev_priv->sagv_block_time_us)
return false;
}
@@ -9013,6 +9025,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
else if (IS_GEN(dev_priv, 5))
i915_ironlake_get_mem_freq(dev_priv);
+ if (intel_has_sagv(dev_priv))
+ skl_setup_sagv_block_time(dev_priv);
+
/* For FIFO watermark updates */
if (INTEL_GEN(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
--
2.22.1
___
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Re: [Intel-gfx] [PATCH v3 02/21] drm/i915: introduce intel_memory_region
Quoting Matthew Auld (2019-10-04 18:04:33) > +struct drm_i915_gem_object * > +i915_gem_object_create_region(struct intel_memory_region *mem, > + resource_size_t size, > + unsigned int flags) Ok, while dma_addr_t can technically exceed resource_size_t (which itself is phys_add_t), that is off no practical value? I do worry about that for 4+G cards on pure 32b machines. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Move SAGV block time to dev_priv
On Fri, Oct 04, 2019 at 01:53:57PM -0700, Lucas De Marchi wrote:
> On Fri, Sep 27, 2019 at 03:24:26PM -0700, James Ausmus wrote:
> >In prep for newer platforms having more complicated ways to determine
> >the SAGV block time, move the variable to dev_priv, and extract the
> >setting to an initial setup function. While we're at it, update the if
> >ladder to follow the new gen -> old gen order preference, and warn on
> >any non-specified gen.
> >
> >v2: Shorten the function name (Ville), return directly (Ville), move
> >sagv_block_time_us value to dev_priv (Ville)
> >
> >Cc: Ville Syrjälä
> >Cc: Stanislav Lisovskiy
> >Cc: Lucas De Marchi
> >Signed-off-by: James Ausmus
> >---
> >
> >Ville - with the amount of v1..v2 change in this first patch, I wasn't
> >comfortable applying your R-b, could you take another look? Patch 2 just
> >has the trivial changes you suggested, so I kept that one.
> >
> > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> > drivers/gpu/drm/i915/intel_pm.c | 33 -
> > 2 files changed, 26 insertions(+), 9 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/i915_drv.h
> >b/drivers/gpu/drm/i915/i915_drv.h
> >index 337d8306416a..87a835a0210b 100644
> >--- a/drivers/gpu/drm/i915/i915_drv.h
> >+++ b/drivers/gpu/drm/i915/i915_drv.h
> >@@ -1579,6 +1579,8 @@ struct drm_i915_private {
> > I915_SAGV_NOT_CONTROLLED
> > } sagv_status;
> >
> >+int sagv_block_time_us;
> >+
> > struct {
> > /*
> > * Raw watermark latency values:
> >diff --git a/drivers/gpu/drm/i915/intel_pm.c
> >b/drivers/gpu/drm/i915/intel_pm.c
> >index bfcf03ab5245..b413a7f3bc5d 100644
> >--- a/drivers/gpu/drm/i915/intel_pm.c
> >+++ b/drivers/gpu/drm/i915/intel_pm.c
> >@@ -3642,6 +3642,26 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
> > dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
> > }
> >
> >+static void
> >+skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
> >+{
> >+if (IS_GEN(dev_priv, 11)) {
> >+dev_priv->sagv_block_time_us = 10;
> >+return;
> >+} else if (IS_GEN(dev_priv, 10)) {
> >+dev_priv->sagv_block_time_us = 20;
> >+return;
> >+} else if (IS_GEN(dev_priv, 9)) {
> >+dev_priv->sagv_block_time_us = 30;
> >+return;
> >+} else {
> >+MISSING_CASE(INTEL_GEN(dev_priv));
> >+}
> >+
> >+/* Default to an unusable block time */
> >+dev_priv->sagv_block_time_us = 1000;
>
> I would actually make sagv_block_time_us unsigned and assign -1 here.
> But making it unsigned would mean cascade that down to the wm
> calculations. Humn... Maybe there's a reason for that to be signed that
> I'm not seeing.
Hmm - yeah, I don't see a reason why it needs to be signed either.
Hadn't looked in to it previously, was just following the existing code.
:)
I'll switch that up and send a v3.
>
>
> >+}
> >+
> > /*
> > * SAGV dynamically adjusts the system agent voltage and clock frequencies
> > * depending on power and performance requirements. The display engine
> > access
> >@@ -3730,18 +3750,10 @@ bool intel_can_enable_sagv(struct intel_atomic_state
> >*state)
> > struct intel_crtc_state *crtc_state;
> > enum pipe pipe;
> > int level, latency;
> >-int sagv_block_time_us;
> >
> > if (!intel_has_sagv(dev_priv))
> > return false;
> >
> >-if (IS_GEN(dev_priv, 9))
> >-sagv_block_time_us = 30;
> >-else if (IS_GEN(dev_priv, 10))
> >-sagv_block_time_us = 20;
> >-else
> >-sagv_block_time_us = 10;
> >-
> > /*
> > * If there are no active CRTCs, no additional checks need be performed
> > */
> >@@ -3788,7 +3800,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state
> >*state)
> > * incur memory latencies higher than sagv_block_time_us we
> > * can't enable SAGV.
> > */
> >-if (latency < sagv_block_time_us)
> >+if (latency < dev_priv->sagv_block_time_us)
> > return false;
> > }
> >
> >@@ -9013,6 +9025,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
> > else if (IS_GEN(dev_priv, 5))
> > i915_ironlake_get_mem_freq(dev_priv);
> >
> >+if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> >+skl_setup_sagv_block_time(dev_priv);
>
> Do we want to use intel_has_sagv() here?
Yeah, that would make sense, will fix up.
Thanks!
-James
>
> >+
> > /* For FIFO watermark updates */
> > if (INTEL_GEN(dev_priv) >= 9) {
> > skl_setup_wm_latency(dev_priv);
> >--
> >2.22.1
> >
___
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Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/tgl: Read SAGV block time from PCODE
On Fri, Oct 04, 2019 at 01:55:46PM -0700, Lucas De Marchi wrote:
> On Fri, Sep 27, 2019 at 03:24:27PM -0700, James Ausmus wrote:
> >Starting from TGL, we now need to read the SAGV block time via a PCODE
> >mailbox, rather than having a static value.
> >
> >BSpec: 49326
> >
> >v2: Fix up pcode val data type (Ville), tighten variable scope (Ville)
> >
> >Cc: Ville Syrjälä
> >Cc: Stanislav Lisovskiy
> >Cc: Lucas De Marchi
> >Signed-off-by: James Ausmus
> >Reviewed-by: Ville Syrjälä
> >---
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_pm.c | 15 ++-
> > 2 files changed, 15 insertions(+), 1 deletion(-)
> >
> >diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >b/drivers/gpu/drm/i915/i915_reg.h
> >index 058aa5ca8b73..6a45df9dad9c 100644
> >--- a/drivers/gpu/drm/i915/i915_reg.h
> >+++ b/drivers/gpu/drm/i915/i915_reg.h
> >@@ -8869,6 +8869,7 @@ enum {
> > #define GEN9_SAGV_DISABLE 0x0
> > #define GEN9_SAGV_IS_DISABLED 0x1
> > #define GEN9_SAGV_ENABLE0x3
> >+#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
> > #define GEN6_PCODE_DATA _MMIO(0x138128)
> > #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT8
> > #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
> >diff --git a/drivers/gpu/drm/i915/intel_pm.c
> >b/drivers/gpu/drm/i915/intel_pm.c
> >index b413a7f3bc5d..13721ba44013 100644
> >--- a/drivers/gpu/drm/i915/intel_pm.c
> >+++ b/drivers/gpu/drm/i915/intel_pm.c
> >@@ -3645,7 +3645,20 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
> > static void
> > skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
> > {
> >-if (IS_GEN(dev_priv, 11)) {
> >+if (INTEL_GEN(dev_priv) >= 12) {
>
> sagv will still never be enabled for TGL. Are you going to revert
> 8ffa4392a32e ("drm/i915/tgl: disable SAGV temporarily")
> in a separete patch?
Yes, that's the idea - we land these two patches, then once HSD
1409542895 gets resolved, we revert 8ffa4392a32e and everything Just
Works. ;)
-James
>
> Lucas De Marchi
>
> >+u32 val = 0;
> >+int ret;
> >+
> >+ret = sandybridge_pcode_read(dev_priv,
> >+
> >GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
> >+ , NULL);
> >+if (!ret) {
> >+dev_priv->sagv_block_time_us = val;
> >+return;
> >+}
> >+
> >+DRM_DEBUG_DRIVER("Couldn't read SAGV block time!\n");
> >+} else if (IS_GEN(dev_priv, 11)) {
> > dev_priv->sagv_block_time_us = 10;
> > return;
> > } else if (IS_GEN(dev_priv, 10)) {
> >--
> >2.22.1
> >
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Appease lockdep
== Series Details ==
Series: drm/i915/selftests: Appease lockdep
URL : https://patchwork.freedesktop.org/series/67622/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7012 -> Patchwork_14678
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14678/index.html
Known issues
Here are the changes found in Patchwork_14678 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7012/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14678/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_flink_basic@basic:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +2
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7012/fi-icl-u3/igt@gem_flink_ba...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14678/fi-icl-u3/igt@gem_flink_ba...@basic.html
Possible fixes
* igt@gem_ctx_switch@rcs0:
- fi-bxt-dsi: [INCOMPLETE][5] ([fdo#103927]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7012/fi-bxt-dsi/igt@gem_ctx_swi...@rcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14678/fi-bxt-dsi/igt@gem_ctx_swi...@rcs0.html
* igt@gem_mmap_gtt@basic-write-no-prefault:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7012/fi-icl-u3/igt@gem_mmap_...@basic-write-no-prefault.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14678/fi-icl-u3/igt@gem_mmap_...@basic-write-no-prefault.html
* igt@i915_selftest@live_hangcheck:
- {fi-icl-guc}: [DMESG-FAIL][9] ([fdo#111678]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7012/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14678/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111678]: https://bugs.freedesktop.org/show_bug.cgi?id=111678
Participating hosts (52 -> 43)
--
Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy
fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7012 -> Patchwork_14678
CI-20190529: 20190529
CI_DRM_7012: 42dcf5adc9c45f6f2f28e23b815ab723f96edca0 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5212: d17a484b3c22706b2b004ef1577f367d79235e43 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14678: 4c82f2976a87b7b5d72b1ce2deb5ee157d357350 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4c82f2976a87 drm/i915/selftests: Appease lockdep
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14678/index.html
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/3] drm/i915/vga: rename intel_vga_msr_write() to intel_vga_reset_io_mem()
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/vga: rename
intel_vga_msr_write() to intel_vga_reset_io_mem()
URL : https://patchwork.freedesktop.org/series/67592/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7007_full -> Patchwork_14668_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14668_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14668_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14668_full:
### IGT changes ###
Possible regressions
* igt@gem_exec_reloc@basic-wc-cpu-active:
- shard-skl: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7007/shard-skl7/igt@gem_exec_re...@basic-wc-cpu-active.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14668/shard-skl1/igt@gem_exec_re...@basic-wc-cpu-active.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_eio@kms}:
- {shard-tglb}: NOTRUN -> [INCOMPLETE][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14668/shard-tglb6/igt@gem_...@kms.html
* igt@gem_tiled_wc:
- {shard-tglb}: [PASS][4] -> [INCOMPLETE][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7007/shard-tglb7/igt@gem_tiled_wc.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14668/shard-tglb5/igt@gem_tiled_wc.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- {shard-tglb}: [INCOMPLETE][6] ([fdo#111832]) -> [INCOMPLETE][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7007/shard-tglb3/igt@kms_vbl...@pipe-b-ts-continuation-dpms-suspend.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14668/shard-tglb1/igt@kms_vbl...@pipe-b-ts-continuation-dpms-suspend.html
Known issues
Here are the changes found in Patchwork_14668_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@read_all_entries_display_on:
- shard-skl: [PASS][8] -> [DMESG-WARN][9] ([fdo#106107]) +1
similar issue
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7007/shard-skl8/igt@debugfs_test@read_all_entries_display_on.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14668/shard-skl6/igt@debugfs_test@read_all_entries_display_on.html
* igt@gem_ctx_switch@legacy-default-heavy-queue:
- shard-apl: [PASS][10] -> [INCOMPLETE][11] ([fdo#103927]) +1
similar issue
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7007/shard-apl7/igt@gem_ctx_swi...@legacy-default-heavy-queue.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14668/shard-apl4/igt@gem_ctx_swi...@legacy-default-heavy-queue.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#110854])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7007/shard-iclb1/igt@gem_exec_balan...@smoke.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14668/shard-iclb6/igt@gem_exec_balan...@smoke.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#109276]) +20 similar
issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7007/shard-iclb1/igt@gem_exec_sched...@preempt-queue-bsd1.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14668/shard-iclb6/igt@gem_exec_sched...@preempt-queue-bsd1.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][16] -> [SKIP][17] ([fdo#111325]) +4 similar
issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7007/shard-iclb8/igt@gem_exec_sched...@preemptive-hang-bsd.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14668/shard-iclb1/igt@gem_exec_sched...@preemptive-hang-bsd.html
* igt@gem_tiled_wc:
- shard-iclb: [PASS][18] -> [INCOMPLETE][19] ([fdo#107713])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7007/shard-iclb4/igt@gem_tiled_wc.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14668/shard-iclb7/igt@gem_tiled_wc.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-snb: [PASS][20] -> [DMESG-WARN][21] ([fdo#111870]) +1
similar issue
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7007/shard-snb2/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14668/shard-snb2/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/tgl: Read SAGV block time from PCODE
On Fri, Sep 27, 2019 at 03:24:27PM -0700, James Ausmus wrote:
Starting from TGL, we now need to read the SAGV block time via a PCODE
mailbox, rather than having a static value.
BSpec: 49326
v2: Fix up pcode val data type (Ville), tighten variable scope (Ville)
Cc: Ville Syrjälä
Cc: Stanislav Lisovskiy
Cc: Lucas De Marchi
Signed-off-by: James Ausmus
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 15 ++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 058aa5ca8b73..6a45df9dad9c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8869,6 +8869,7 @@ enum {
#define GEN9_SAGV_DISABLE 0x0
#define GEN9_SAGV_IS_DISABLED 0x1
#define GEN9_SAGV_ENABLE0x3
+#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US0x23
#define GEN6_PCODE_DATA _MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b413a7f3bc5d..13721ba44013 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3645,7 +3645,20 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
static void
skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
{
- if (IS_GEN(dev_priv, 11)) {
+ if (INTEL_GEN(dev_priv) >= 12) {
sagv will still never be enabled for TGL. Are you going to revert
8ffa4392a32e ("drm/i915/tgl: disable SAGV temporarily")
in a separete patch?
Lucas De Marchi
+ u32 val = 0;
+ int ret;
+
+ ret = sandybridge_pcode_read(dev_priv,
+
GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
+, NULL);
+ if (!ret) {
+ dev_priv->sagv_block_time_us = val;
+ return;
+ }
+
+ DRM_DEBUG_DRIVER("Couldn't read SAGV block time!\n");
+ } else if (IS_GEN(dev_priv, 11)) {
dev_priv->sagv_block_time_us = 10;
return;
} else if (IS_GEN(dev_priv, 10)) {
--
2.22.1
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Appease lockdep
== Series Details ==
Series: drm/i915/selftests: Appease lockdep
URL : https://patchwork.freedesktop.org/series/67622/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4c82f2976a87 drm/i915/selftests: Appease lockdep
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#12:
<4>[ 673.483344] 88845db885a0 (_request_get(rq)->submit/1){-...}, at:
__i915_sw_fence_complete+0x1b2/0x250 [i915]
total: 0 errors, 1 warnings, 0 checks, 13 lines checked
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Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Move SAGV block time to dev_priv
On Fri, Sep 27, 2019 at 03:24:26PM -0700, James Ausmus wrote:
In prep for newer platforms having more complicated ways to determine
the SAGV block time, move the variable to dev_priv, and extract the
setting to an initial setup function. While we're at it, update the if
ladder to follow the new gen -> old gen order preference, and warn on
any non-specified gen.
v2: Shorten the function name (Ville), return directly (Ville), move
sagv_block_time_us value to dev_priv (Ville)
Cc: Ville Syrjälä
Cc: Stanislav Lisovskiy
Cc: Lucas De Marchi
Signed-off-by: James Ausmus
---
Ville - with the amount of v1..v2 change in this first patch, I wasn't
comfortable applying your R-b, could you take another look? Patch 2 just
has the trivial changes you suggested, so I kept that one.
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 33 -
2 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 337d8306416a..87a835a0210b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1579,6 +1579,8 @@ struct drm_i915_private {
I915_SAGV_NOT_CONTROLLED
} sagv_status;
+ int sagv_block_time_us;
+
struct {
/*
* Raw watermark latency values:
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bfcf03ab5245..b413a7f3bc5d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3642,6 +3642,26 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
}
+static void
+skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
+{
+ if (IS_GEN(dev_priv, 11)) {
+ dev_priv->sagv_block_time_us = 10;
+ return;
+ } else if (IS_GEN(dev_priv, 10)) {
+ dev_priv->sagv_block_time_us = 20;
+ return;
+ } else if (IS_GEN(dev_priv, 9)) {
+ dev_priv->sagv_block_time_us = 30;
+ return;
+ } else {
+ MISSING_CASE(INTEL_GEN(dev_priv));
+ }
+
+ /* Default to an unusable block time */
+ dev_priv->sagv_block_time_us = 1000;
I would actually make sagv_block_time_us unsigned and assign -1 here.
But making it unsigned would mean cascade that down to the wm
calculations. Humn... Maybe there's a reason for that to be signed that
I'm not seeing.
+}
+
/*
* SAGV dynamically adjusts the system agent voltage and clock frequencies
* depending on power and performance requirements. The display engine access
@@ -3730,18 +3750,10 @@ bool intel_can_enable_sagv(struct intel_atomic_state
*state)
struct intel_crtc_state *crtc_state;
enum pipe pipe;
int level, latency;
- int sagv_block_time_us;
if (!intel_has_sagv(dev_priv))
return false;
- if (IS_GEN(dev_priv, 9))
- sagv_block_time_us = 30;
- else if (IS_GEN(dev_priv, 10))
- sagv_block_time_us = 20;
- else
- sagv_block_time_us = 10;
-
/*
* If there are no active CRTCs, no additional checks need be performed
*/
@@ -3788,7 +3800,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state
*state)
* incur memory latencies higher than sagv_block_time_us we
* can't enable SAGV.
*/
- if (latency < sagv_block_time_us)
+ if (latency < dev_priv->sagv_block_time_us)
return false;
}
@@ -9013,6 +9025,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
else if (IS_GEN(dev_priv, 5))
i915_ironlake_get_mem_freq(dev_priv);
+ if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10)
+ skl_setup_sagv_block_time(dev_priv);
Do we want to use intel_has_sagv() here?
+
/* For FIFO watermark updates */
if (INTEL_GEN(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
--
2.22.1
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Re: [Intel-gfx] [RFC v3 5/9] drm/i915: Extract framebufer CCS offset checks into a function
On Mon, Sep 23, 2019 at 03:29:31AM -0700, Dhinakaran Pandiyan wrote:
> intel_fill_fb_info() has grown quite large and wrapping the offset checks
> into a separate function makes the loop a bit easier to follow.
>
> Cc: Ville Syrjälä
> Cc: Matt Roper
> Signed-off-by: Dhinakaran Pandiyan
I agree with Ville's comments, but otherwise,
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 69
> 1 file changed, 40 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 6fec43cdddf4..7447001c1f85 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2682,6 +2682,43 @@ static bool intel_plane_needs_remap(const struct
> intel_plane_state *plane_state)
> return stride > max_stride;
> }
>
> +static int
> +intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
> +{
> + struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> + int hsub = fb->format->hsub;
> + int vsub = fb->format->vsub;
> + int tile_width, tile_height;
> + int ccs_x, ccs_y;
> + int main_x, main_y;
> +
> + intel_tile_dims(fb, 1, _width, _height);
> +
> + tile_width *= hsub;
> + tile_height *= vsub;
> +
> + ccs_x = (x * hsub) % tile_width;
> + ccs_y = (y * vsub) % tile_height;
> + main_x = intel_fb->normal[0].x % tile_width;
> + main_y = intel_fb->normal[0].y % tile_height;
> +
> + /*
> + * CCS doesn't have its own x/y offset register, so the intra CCS tile
> + * x/y offsets must match between CCS and the main surface.
> + */
> + if (main_x != ccs_x || main_y != ccs_y) {
> + DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main
> %d,%d ccs %d,%d)\n",
> + main_x, main_y,
> + ccs_x, ccs_y,
> + intel_fb->normal[0].x,
> + intel_fb->normal[0].y,
> + x, y);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> static int
> intel_fill_fb_info(struct drm_i915_private *dev_priv,
> struct drm_framebuffer *fb)
> @@ -2713,35 +2750,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
> }
>
> if (is_ccs_modifier(fb->modifier) && i == 1) {
> - int hsub = fb->format->hsub;
> - int vsub = fb->format->vsub;
> - int tile_width, tile_height;
> - int main_x, main_y;
> - int ccs_x, ccs_y;
> -
> - intel_tile_dims(fb, i, _width, _height);
> -
> - tile_width *= hsub;
> - tile_height *= vsub;
> -
> - ccs_x = (x * hsub) % tile_width;
> - ccs_y = (y * vsub) % tile_height;
> - main_x = intel_fb->normal[0].x % tile_width;
> - main_y = intel_fb->normal[0].y % tile_height;
> -
> - /*
> - * CCS doesn't have its own x/y offset register, so the
> intra CCS tile
> - * x/y offsets must match between CCS and the main
> surface.
> - */
> - if (main_x != ccs_x || main_y != ccs_y) {
> - DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs
> %d,%d) full (main %d,%d ccs %d,%d)\n",
> - main_x, main_y,
> - ccs_x, ccs_y,
> - intel_fb->normal[0].x,
> - intel_fb->normal[0].y,
> - x, y);
> - return -EINVAL;
> - }
> + ret = intel_fb_check_ccs_xy(fb, x, y);
> + if (ret)
> + return ret;
> }
>
> /*
> --
> 2.17.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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[Intel-gfx] [PATCH] drm/i915/selftests: Appease lockdep
Disable irqs around updating the context image to keep lockdep happy:
<4>[ 673.483340] WARNING: possible irq lock inversion dependency detected
<4>[ 673.483342] 5.4.0-rc1-CI-Trybot_5118+ #1 Tainted: G U
<4>[ 673.483342]
<4>[ 673.483343] swapper/2/0 just changed the state of lock:
<4>[ 673.483344] 88845db885a0 (_request_get(rq)->submit/1){-...}, at:
__i915_sw_fence_complete+0x1b2/0x250 [i915]
<4>[ 673.483387] but this lock took another, HARDIRQ-unsafe lock in the past:
<4>[ 673.483388] (>pin_mutex/2){+...}
<4>[ 673.483389]
and interrupts could create inverse lock ordering between
them.
<4>[ 673.483390]
other info that might help us debug this:
<4>[ 673.483390] Chain exists of:
_request_get(rq)->submit/1 --> >active.lock
--> >pin_mutex/2
<4>[ 673.483392] Possible interrupt unsafe locking scenario:
<4>[ 673.483392]CPU0CPU1
<4>[ 673.483393]
<4>[ 673.483393] lock(>pin_mutex/2);
<4>[ 673.483394]local_irq_disable();
<4>[ 673.483395]
lock(_request_get(rq)->submit/1);
<4>[ 673.483396]lock(>active.lock);
<4>[ 673.483396]
<4>[ 673.483397] lock(_request_get(rq)->submit/1);
<4>[ 673.483398]
*** DEADLOCK ***
<4>[ 673.483398] 2 locks held by swapper/2/0:
<4>[ 673.483399] #0: 8883f61ac9b0 (&(>irq_lock)->rlock){-.-.}, at:
gen11_gt_irq_handler+0x42/0x280 [i915]
<4>[ 673.483433] #1: 88845db8c418 (&(>lock)->rlock){-.-.}, at:
intel_engine_breadcrumbs_irq+0x34a/0x5a0 [i915]
<4>[ 673.483463]
the shortest dependencies between 2nd lock and 1st lock:
<4>[ 673.483466] -> (>pin_mutex/2){+...} ops: 614520 {
<4>[ 673.483468] HARDIRQ-ON-W at:
<4>[ 673.483471] lock_acquire+0xa7/0x1c0
<4>[ 673.483501] live_unlite_restore+0x1d8/0x6c0 [i915]
<4>[ 673.483543] __i915_subtests+0xb8/0x210 [i915]
<4>[ 673.483581] __run_selftests+0x112/0x170 [i915]
<4>[ 673.483615] i915_live_selftests+0x2c/0x60 [i915]
<4>[ 673.483644] i915_pci_probe+0x93/0x1b0 [i915]
<4>[ 673.483646] pci_device_probe+0x9e/0x120
<4>[ 673.483648] really_probe+0xea/0x420
<4>[ 673.483649] driver_probe_device+0x10b/0x120
<4>[ 673.483651] device_driver_attach+0x4a/0x50
<4>[ 673.483652] __driver_attach+0x97/0x130
<4>[ 673.483653] bus_for_each_dev+0x74/0xc0
<4>[ 673.483654] bus_add_driver+0x142/0x220
<4>[ 673.483655] driver_register+0x56/0xf0
<4>[ 673.483657] do_one_initcall+0x58/0x2ff
<4>[ 673.483659] do_init_module+0x56/0x1f8
<4>[ 673.483660] load_module+0x243e/0x29f0
<4>[ 673.483661] __do_sys_finit_module+0xe9/0x110
<4>[ 673.483662] do_syscall_64+0x4f/0x210
<4>[ 673.483665]
entry_SYSCALL_64_after_hwframe+0x49/0xbe
<4>[ 673.483665] INITIAL USE at:
<4>[ 673.483667]lock_acquire+0xa7/0x1c0
<4>[ 673.483698]live_unlite_restore+0x1d8/0x6c0 [i915]
<4>[ 673.483733]__i915_subtests+0xb8/0x210 [i915]
<4>[ 673.483764]__run_selftests+0x112/0x170 [i915]
<4>[ 673.483793]i915_live_selftests+0x2c/0x60 [i915]
<4>[ 673.483821]i915_pci_probe+0x93/0x1b0 [i915]
<4>[ 673.483822]pci_device_probe+0x9e/0x120
<4>[ 673.483824]really_probe+0xea/0x420
<4>[ 673.483825]driver_probe_device+0x10b/0x120
<4>[ 673.483826]device_driver_attach+0x4a/0x50
<4>[ 673.483827]__driver_attach+0x97/0x130
<4>[ 673.483828]bus_for_each_dev+0x74/0xc0
<4>[ 673.483829]bus_add_driver+0x142/0x220
<4>[ 673.483830]driver_register+0x56/0xf0
<4>[ 673.483831]do_one_initcall+0x58/0x2ff
<4>[ 673.483833]do_init_module+0x56/0x1f8
<4>[ 673.483834]load_module+0x243e/0x29f0
<4>[ 673.483835]__do_sys_finit_module+0xe9/0x110
<4>[ 673.483836]do_syscall_64+0x4f/0x210
<4>[ 673.483837]
entry_SYSCALL_64_after_hwframe+0x49/0xbe
<4>[ 673.483838]}
<4>[ 673.483868]... key at: []
__key.70113+0x2/0xffef2ed0 [i915]
<4>[ 673.483869]... acquired at:
<4>[ 673.483935]
Re: [Intel-gfx] [PATCH v4 9/9] Gen-12 display can decompress surfaces compressed by the media engine.
On Thu, Sep 26, 2019 at 03:55:12AM -0700, Dhinakaran Pandiyan wrote:
> Detect the modifier corresponding to media compression to enable
> display decompression for YUV and xRGB packed formats. A new modifier is
> added so that the driver can distinguish between media and render
> compressed buffers. Unlike render decompression, plane 6 and plane 7 do not
> support media decompression.
>
> v2: Fix checkpatch warnings on code style (Lucas)
>
> From DK:
> Separate modifier array for planes that cannot decompress media (Ville)
>
> v3: Support planar formats
> v4: Switch plane order
>
> Cc: Nanley G Chery
> Cc: Ville Syrjälä
> Cc: Matt Roper
> Signed-off-by: Dhinakaran Pandiyan
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 290 +-
> .../drm/i915/display/intel_display_types.h| 2 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 55 +++-
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 4 files changed, 267 insertions(+), 81 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 8ea55d67442c..df3ebaa167ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1888,6 +1888,22 @@ static void intel_disable_pipe(const struct
> intel_crtc_state *old_crtc_state)
> intel_wait_for_pipe_off(old_crtc_state);
> }
>
> +bool is_ccs_modifier(u64 modifier)
> +{
> + return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> +modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> +modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> +modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> +}
> +
> +static bool is_ccs_plane(const struct drm_framebuffer *fb, int color_plane)
> +{
> + if (!is_ccs_modifier(fb->modifier))
> + return false;
> +
> + return color_plane >= fb->format->num_planes / 2;
> +}
This appears to contradict what you indicated on the modifier patch:
+ * Y-tile widths. For semi-planar formats like NV12, CCS plane follows the
+ * Y and UV planes i.e., planes 0 and 2 are used for Y and UV surfaces,
+ * planes 1 and 3 for the respective CCS.
Based on that comment I'd expect something more like (color_plane % 2).
> +
> static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
> {
> return IS_GEN(dev_priv, 2) ? 2048 : 4096;
> @@ -1908,11 +1924,13 @@ intel_tile_width_bytes(const struct drm_framebuffer
> *fb, int color_plane)
> else
> return 512;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> - if (color_plane == 1)
> + if (is_ccs_plane(fb, color_plane))
> return 128;
> /* fall through */
> + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> + /* fall through */
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> - if (color_plane == 1)
> + if (is_ccs_plane(fb, color_plane))
> return 64;
> /* fall through */
> case I915_FORMAT_MOD_Y_TILED:
> @@ -1921,7 +1939,7 @@ intel_tile_width_bytes(const struct drm_framebuffer
> *fb, int color_plane)
> else
> return 512;
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> - if (color_plane == 1)
> + if (is_ccs_plane(fb, color_plane))
> return 128;
> /* fall through */
> case I915_FORMAT_MOD_Yf_TILED:
> @@ -1949,8 +1967,9 @@ static unsigned int
> intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
> {
> switch (fb->modifier) {
> + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> - if (color_plane == 1)
> + if (is_ccs_plane(fb, color_plane))
> return 1;
> /* fall through */
> default:
> @@ -2055,6 +2074,7 @@ static unsigned int intel_surf_alignment(const struct
> drm_framebuffer *fb,
> if (INTEL_GEN(dev_priv) >= 9)
> return 256 * 1024;
> return 0;
> + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> return 16 * 1024;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> @@ -2254,10 +2274,17 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
> return new_offset;
> }
>
> -static bool is_surface_linear(u64 modifier, int color_plane)
> +static bool is_surface_linear(const struct drm_framebuffer *fb, int
> color_plane)
> {
> - return modifier == DRM_FORMAT_MOD_LINEAR ||
> -(modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane
> == 1);
> + switch (fb->modifier) {
> + case DRM_FORMAT_MOD_LINEAR:
> + return true;
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + case
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Fix annotation for decoupling virtual request
== Series Details ==
Series: drm/i915/execlists: Fix annotation for decoupling virtual request
URL : https://patchwork.freedesktop.org/series/67621/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7011 -> Patchwork_14677
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14677/index.html
Known issues
Here are the changes found in Patchwork_14677 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-short:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +2
similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/fi-icl-u3/igt@gem_mmap_...@basic-short.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14677/fi-icl-u3/igt@gem_mmap_...@basic-short.html
* igt@i915_module_load@reload:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/fi-blb-e6850/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14677/fi-blb-e6850/igt@i915_module_l...@reload.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#111407])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14677/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_mmap_gtt@basic-small-bo-tiledy:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledy.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14677/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledy.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][9] ([fdo#102614]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14677/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (52 -> 42)
--
Missing(10): fi-kbl-soraka fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u
fi-byt-squawks fi-bsw-cyan fi-skl-6260u fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7011 -> Patchwork_14677
CI-20190529: 20190529
CI_DRM_7011: 7d13733c2a87909eef8bc945ecbf4d47e0b67133 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5212: d17a484b3c22706b2b004ef1577f367d79235e43 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14677: a0822b4ea3010ae1a4dd125e638e6468efff8579 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a0822b4ea301 drm/i915/execlists: Fix annotation for decoupling virtual request
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14677/index.html
___
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Re: [Intel-gfx] [PATCH 2/4] drm/i915/color: move check of gamma_enable to specific func/platform
On Fri, Oct 04, 2019 at 01:56:08PM +0530, Swati Sharma wrote:
> Moved common code to check gamma_enable to specific funcs per platform
> in bit_precision func. icl doesn't support that and chv has separate
> enable knob for CGM LUT.
>
> Signed-off-by: Swati Sharma
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 23 +-
> 1 file changed, 18 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 8f02313a7fef..44ce75f051ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1420,6 +1420,9 @@ static int icl_color_check(struct intel_crtc_state
> *crtc_state)
>
> static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> switch (crtc_state->gamma_mode) {
> case GAMMA_MODE_MODE_8BIT:
> return 8;
> @@ -1433,6 +1436,9 @@ static int i9xx_gamma_precision(const struct
> intel_crtc_state *crtc_state)
>
> static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
> return 0;
>
> @@ -1449,14 +1455,24 @@ static int ilk_gamma_precision(const struct
> intel_crtc_state *crtc_state)
>
> static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> - if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
> - return 10;
> + if (crtc_state->cgm_mode) {
> + if ((crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) == 0)
> + return 0;
> + else
> + return 10;
> + }
> +
> + if (!crtc_state->gamma_enable)
> + return 0;
> else
> return i9xx_gamma_precision(crtc_state);
Again could simplify to just:
if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
return 10;
else
return i9xx_gamma_precision(crtc_state);
> }
>
> static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> switch (crtc_state->gamma_mode) {
> case GAMMA_MODE_MODE_8BIT:
> return 8;
> @@ -1473,9 +1489,6 @@ int intel_color_get_gamma_bit_precision(const struct
> intel_crtc_state *crtc_stat
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - if (!crtc_state->gamma_enable)
> - return 0;
> -
> if (HAS_GMCH(dev_priv)) {
> if (IS_CHERRYVIEW(dev_priv))
> return chv_gamma_precision(crtc_state);
> --
> 2.23.0
--
Ville Syrjälä
Intel
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] [v2] drm/i915/color: fix broken gamma state-checker during boot
On Fri, Oct 04, 2019 at 01:56:07PM +0530, Swati Sharma wrote:
> Premature gamma lut prepration and loading which was getting
> reflected in first modeset causing different colors on
> screen during boot.
>
> Issue: In BIOS, gamma is disabled by default. However, legacy read_luts()
> was setting crtc_state->base.gamma_lut and gamma_lut was programmed
> with junk values which led to visual artifacts (different
> colored screens instead of usual black during boot).
>
> Fix: Calling read_luts() only when gamma is enabled which will happen
> after first modeset.
>
> This fix is independent from the revert 1b8588741fdc ("Revert
> "drm/i915/color: Extract icl_read_luts()"") and should fix different colors
> on screen in legacy platforms too.
>
> -Added gamma_enable checks inside read_luts() [Ville/Jani N]
> -Corrected gamma enable check for CHV [Ville]
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111809
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111885
> Signed-off-by: Swati Sharma
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 27 +++---
> 1 file changed, 24 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 9ab34902663e..8f02313a7fef 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1613,6 +1613,9 @@ i9xx_read_lut_8(const struct intel_crtc_state
> *crtc_state)
>
> static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return;
> +
> crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> }
>
> @@ -1659,6 +1662,9 @@ i965_read_lut_10p6(const struct intel_crtc_state
> *crtc_state)
>
> static void i965_read_luts(struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return;
> +
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> else
> @@ -1701,10 +1707,19 @@ chv_read_cgm_lut(const struct intel_crtc_state
> *crtc_state)
>
> static void chv_read_luts(struct intel_crtc_state *crtc_state)
> {
> - if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> - crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> - else
> + if (crtc_state->cgm_mode) {
> + if ((crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) == 0)
> + return;
> +
> crtc_state->base.gamma_lut = chv_read_cgm_lut(crtc_state);
> + }
> +
> + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
> + if (!crtc_state->gamma_enable)
> + return;
> +
> + crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> + }
I'd simply make this something like:
if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) {
crtc_state->base.gamma_lut = chv_read_cgm_lut(crtc_state);
} else {
i965_read_luts(crtc_state);
}
> }
>
> static struct drm_property_blob *
> @@ -1742,6 +1757,9 @@ ilk_read_lut_10(const struct intel_crtc_state
> *crtc_state)
>
> static void ilk_read_luts(struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return;
We should check
if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
return;
here so we don't read the hw degamma into the state gmama_lut.
> +
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> else
> @@ -1788,6 +1806,9 @@ glk_read_lut_10(const struct intel_crtc_state
> *crtc_state, u32 prec_index)
>
> static void glk_read_luts(struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return;
> +
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> else
> --
> 2.23.0
--
Ville Syrjälä
Intel
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/execlists: Fix annotation for decoupling virtual request
== Series Details ==
Series: drm/i915/execlists: Fix annotation for decoupling virtual request
URL : https://patchwork.freedesktop.org/series/67621/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a0822b4ea301 drm/i915/execlists: Fix annotation for decoupling virtual request
-:16: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#16:
<4>[ 723.763294] 93a7b53221d8 (>active.lock){..-.}, at:
execlists_submit_request+0x2b/0x1e0 [i915]
total: 0 errors, 1 warnings, 0 checks, 9 lines checked
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/stolen: make the object creation interface consistent
== Series Details ==
Series: drm/i915/stolen: make the object creation interface consistent
URL : https://patchwork.freedesktop.org/series/67615/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7011 -> Patchwork_14676
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14676 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14676, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14676/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14676:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_workarounds:
- fi-skl-6260u: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/fi-skl-6260u/igt@i915_selftest@live_workarounds.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14676/fi-skl-6260u/igt@i915_selftest@live_workarounds.html
Known issues
Here are the changes found in Patchwork_14676 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap@basic-small-bo:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/fi-icl-u3/igt@gem_m...@basic-small-bo.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14676/fi-icl-u3/igt@gem_m...@basic-small-bo.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713] /
[fdo#108569])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14676/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][7] -> [FAIL][8] ([fdo#111407])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14676/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_mmap_gtt@basic-small-bo-tiledy:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +1
similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledy.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14676/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledy.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][11] ([fdo#102614]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14676/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
Participating hosts (52 -> 44)
--
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-bwr-2160 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7011 -> Patchwork_14676
CI-20190529: 20190529
CI_DRM_7011: 7d13733c2a87909eef8bc945ecbf4d47e0b67133 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5212: d17a484b3c22706b2b004ef1577f367d79235e43 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14676: f3d3262fb84d2386d4b1d4d24bf632d278f3e5b8 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f3d3262fb84d drm/i915/stolen: make the object creation interface consistent
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14676/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/execlists: Fix annotation for decoupling virtual request
As we may signal a request and take the engine->active.lock within the
signaler, the engine submission paths have to use a nested annotation on
their requests -- but we guarantee that we can never submit on the same
engine as the signaling fence.
<4>[ 723.763281] WARNING: possible circular locking dependency detected
<4>[ 723.763285] 5.3.0-g80fa0e042cdb-drmtip_379+ #1 Tainted: G U
<4>[ 723.763288] --
<4>[ 723.763291] gem_exec_await/1388 is trying to acquire lock:
<4>[ 723.763294] 93a7b53221d8 (>active.lock){..-.}, at:
execlists_submit_request+0x2b/0x1e0 [i915]
<4>[ 723.763378]
but task is already holding lock:
<4>[ 723.763381] 93a7c25f6d20 (_request_get(rq)->submit/1){-.-.}, at:
__i915_sw_fence_complete+0x1b2/0x250 [i915]
<4>[ 723.763420]
which lock already depends on the new lock.
<4>[ 723.763423]
the existing dependency chain (in reverse order) is:
<4>[ 723.763427]
-> #2 (_request_get(rq)->submit/1){-.-.}:
<4>[ 723.763434]_raw_spin_lock_irqsave_nested+0x39/0x50
<4>[ 723.763478]__i915_sw_fence_complete+0x1b2/0x250 [i915]
<4>[ 723.763513]intel_engine_breadcrumbs_irq+0x3aa/0x5e0 [i915]
<4>[ 723.763600]cs_irq_handler+0x49/0x50 [i915]
<4>[ 723.763659]gen11_gt_irq_handler+0x17b/0x280 [i915]
<4>[ 723.763690]gen11_irq_handler+0x54/0xf0 [i915]
<4>[ 723.763695]__handle_irq_event_percpu+0x41/0x2d0
<4>[ 723.763699]handle_irq_event_percpu+0x2b/0x70
<4>[ 723.763702]handle_irq_event+0x2f/0x50
<4>[ 723.763706]handle_edge_irq+0xee/0x1a0
<4>[ 723.763709]do_IRQ+0x7e/0x160
<4>[ 723.763712]ret_from_intr+0x0/0x1d
<4>[ 723.763717]__slab_alloc.isra.28.constprop.33+0x4f/0x70
<4>[ 723.763720]kmem_cache_alloc+0x28d/0x2f0
<4>[ 723.763724]vm_area_dup+0x15/0x40
<4>[ 723.763727]dup_mm+0x2dd/0x550
<4>[ 723.763730]copy_process+0xf21/0x1ef0
<4>[ 723.763734]_do_fork+0x71/0x670
<4>[ 723.763737]__se_sys_clone+0x6e/0xa0
<4>[ 723.763741]do_syscall_64+0x4f/0x210
<4>[ 723.763744]entry_SYSCALL_64_after_hwframe+0x49/0xbe
<4>[ 723.763747]
-> #1 (&(>lock)->rlock#2){-.-.}:
<4>[ 723.763752]_raw_spin_lock+0x2a/0x40
<4>[ 723.763789]__unwind_incomplete_requests+0x3eb/0x450 [i915]
<4>[ 723.763825]__execlists_submission_tasklet+0x9ec/0x1d60 [i915]
<4>[ 723.763864]execlists_submission_tasklet+0x34/0x50 [i915]
<4>[ 723.763874]tasklet_action_common.isra.5+0x47/0xb0
<4>[ 723.763878]__do_softirq+0xd8/0x4ae
<4>[ 723.763881]irq_exit+0xa9/0xc0
<4>[ 723.763883]smp_apic_timer_interrupt+0xb7/0x280
<4>[ 723.763887]apic_timer_interrupt+0xf/0x20
<4>[ 723.763892]cpuidle_enter_state+0xae/0x450
<4>[ 723.763895]cpuidle_enter+0x24/0x40
<4>[ 723.763899]do_idle+0x1e7/0x250
<4>[ 723.763902]cpu_startup_entry+0x14/0x20
<4>[ 723.763905]start_secondary+0x15f/0x1b0
<4>[ 723.763908]secondary_startup_64+0xa4/0xb0
<4>[ 723.763911]
-> #0 (>active.lock){..-.}:
<4>[ 723.763916]__lock_acquire+0x15d8/0x1ea0
<4>[ 723.763919]lock_acquire+0xa6/0x1c0
<4>[ 723.763922]_raw_spin_lock_irqsave+0x33/0x50
<4>[ 723.763956]execlists_submit_request+0x2b/0x1e0 [i915]
<4>[ 723.764002]submit_notify+0xa8/0x13c [i915]
<4>[ 723.764035]__i915_sw_fence_complete+0x81/0x250 [i915]
<4>[ 723.764054]i915_sw_fence_wake+0x51/0x64 [i915]
<4>[ 723.764054]__i915_sw_fence_complete+0x1ee/0x250 [i915]
<4>[ 723.764054]dma_i915_sw_fence_wake_timer+0x14/0x20 [i915]
<4>[ 723.764054]dma_fence_signal_locked+0x9e/0x1c0
<4>[ 723.764054]dma_fence_signal+0x1f/0x40
<4>[ 723.764054]vgem_fence_signal_ioctl+0x67/0xc0 [vgem]
<4>[ 723.764054]drm_ioctl_kernel+0x83/0xf0
<4>[ 723.764054]drm_ioctl+0x2f3/0x3b0
<4>[ 723.764054]do_vfs_ioctl+0xa0/0x6f0
<4>[ 723.764054]ksys_ioctl+0x35/0x60
<4>[ 723.764054]__x64_sys_ioctl+0x11/0x20
<4>[ 723.764054]do_syscall_64+0x4f/0x210
<4>[ 723.764054]entry_SYSCALL_64_after_hwframe+0x49/0xbe
<4>[ 723.764054]
other info that might help us debug this:
<4>[ 723.764054] Chain exists of:
>active.lock --> &(>lock)->rlock#2 -->
_request_get(rq)->submit/1
<4>[ 723.764054] Possible unsafe locking scenario:
<4>[ 723.764054]CPU0CPU1
<4>[ 723.764054]
<4>[ 723.764054] lock(_request_get(rq)->submit/1);
<4>[ 723.764054]lock(&(>lock)->rlock#2);
<4>[ 723.764054]
lock(_request_get(rq)->submit/1);
<4>[ 723.764054] lock(>active.lock);
<4>[ 723.764054]
***
Re: [Intel-gfx] [PATCH] drm/i915: customize DPCD brightness control for specific panel
On Fri, 04 Oct 2019, Adam Jackson wrote:
> On Sat, 2019-10-05 at 05:58 +0800, Lee Shawn C wrote:
>> This panel (manufacturer is SDC, product ID is 0x4141)
>> used manufacturer defined DPCD register to control brightness
>> that not defined in eDP spec so far. This change follow panel
>> vendor's instruction to support brightness adjustment.
>
> I'm sure this works, but this smells a little funny to me.
That was kindly put. ;)
>> +/* Samsung eDP panel */
>> +{ "SDC", 0x4141, EDID_QUIRK_NON_STD_BRIGHTNESS_CONTROL },
>
> It feels a bit like a layering violation to identify eDP behavior
> changes based on EDID. But I'm not sure there's any obvious way to
> identify this device by its DPCD. The Sink OUI (from the linked
> bugzilla) seems to be 0011F8, which doesn't match up to anything in my
> oui.txt...
We have the DPCD quirk stuff in drm_dp_helper.c, but IIUC in this case
there's only the OUI, and the device id etc. are all zeros. Otherwise I
think that would be the natural thing to do, and all this could be
better hidden away in i915.
>
>> @@ -1953,6 +1956,7 @@ static u32 edid_get_quirks(const struct edid *edid)
>>
>> return 0;
>> }
>> +EXPORT_SYMBOL(edid_get_quirks);
>
> If we're going to export this it should probably get a drm_ prefix.
>
>> +#define DPCD_EDP_GETSET_CTRL_PARAMS 0x344
>> +#define DPCD_EDP_CONTENT_LUMINANCE 0x346
>> +#define DPCD_EDP_PANEL_LUMINANCE_OVERRIDE 0x34a
>> +#define DPCD_EDP_BRIGHTNESS_NITS0x354
>> +#define DPCD_EDP_BRIGHTNESS_OPTIMIZATION0x358
>> +
>> +#define EDP_CUSTOMIZE_MAX_BRIGHTNESS_LEVEL (512)
>
> This also seems a bit weird, the 0x300-0x3FF registers belong to the
> _source_ DP device. But then later...
>
>> +/* write source OUI */
>> +write_val[0] = 0x00;
>> +write_val[1] = 0xaa;
>> +write_val[2] = 0x01;
>
> Oh hey, you're writing (an) Intel OUI to the Source OUI, so now it
> makes sense that you're writing to registers whose behavior the source
> defines. But this does raise the question: is this just a convention
> between Intel and this particular panel? Would we expect this to work
> with other similar panels? Is there any way to know to expect this
> convention from DPCD instead?
For one thing, it's not standard. I honestly don't know, but I'd assume
you wouldn't find behaviour with Intel OUI in non-Intel designs... and a
quirk of some sort seems like the only way to make this work.
I suppose we could start off with a DPCD quirk that only looks at the
sink OUI, and then, if needed, limit by DMI matching or by checking for
some DPCD registers (what, I am not sure, perhaps write the source OUI
and see how it behaves).
That would avoid the mildly annoying change in the EDID quirk interface
and how it's being used.
Thoughts?
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] drm/i915/stolen: make the object creation interface consistent
From: CQ Tang
Our other backends return an actual error value upon failure. Do the
same for stolen objects, which currently just return NULL on failure.
Signed-off-by: CQ Tang
Signed-off-by: Matthew Auld
Cc: Chris Wilson
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20191004170452.15410-2-matthew.a...@intel.com
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_fbdev.c | 4 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 45 +++-
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 8 ++--
drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 2 +-
7 files changed, 36 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 5acc39f32d0c..c15975a410bc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3066,7 +3066,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
base_aligned,
base_aligned,
size_aligned);
- if (!obj)
+ if (IS_ERR(obj))
return false;
switch (plane_config->tiling) {
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 97cde017670a..3d1061470e76 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -141,10 +141,10 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
/* If the FB is too big, just don't use it since fbdev is not very
* important and we should probably use that space with FBC or other
* features. */
- obj = NULL;
+ obj = ERR_PTR(-ENODEV);
if (size * 2 < dev_priv->stolen_usable_size)
obj = i915_gem_object_create_stolen(dev_priv, size);
- if (obj == NULL)
+ if (IS_ERR(obj))
obj = i915_gem_object_create_shmem(dev_priv, size);
if (IS_ERR(obj)) {
DRM_ERROR("failed to allocate framebuffer\n");
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c
b/drivers/gpu/drm/i915/display/intel_overlay.c
index daea112cbb87..2360f19f9694 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -1291,7 +1291,7 @@ static int get_registers(struct intel_overlay *overlay,
bool use_phys)
int err;
obj = i915_gem_object_create_stolen(i915, PAGE_SIZE);
- if (obj == NULL)
+ if (IS_ERR(obj))
obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
if (IS_ERR(obj))
return PTR_ERR(obj);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index fad98a921cde..c76260ce13e3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -553,10 +553,11 @@ _i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
{
struct drm_i915_gem_object *obj;
unsigned int cache_level;
+ int err = -ENOMEM;
obj = i915_gem_object_alloc();
- if (obj == NULL)
- return NULL;
+ if (!obj)
+ goto err;
drm_gem_private_object_init(_priv->drm, >base, stolen->size);
i915_gem_object_init(obj, _gem_object_stolen_ops);
@@ -566,14 +567,16 @@ _i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
cache_level = HAS_LLC(dev_priv) ? I915_CACHE_LLC : I915_CACHE_NONE;
i915_gem_object_set_cache_coherency(obj, cache_level);
- if (i915_gem_object_pin_pages(obj))
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
goto cleanup;
return obj;
cleanup:
i915_gem_object_free(obj);
- return NULL;
+err:
+ return ERR_PTR(err);
}
struct drm_i915_gem_object *
@@ -585,28 +588,32 @@ i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
int ret;
if (!drm_mm_initialized(_priv->mm.stolen))
- return NULL;
+ return ERR_PTR(-ENODEV);
if (size == 0)
- return NULL;
+ return ERR_PTR(-EINVAL);
stolen = kzalloc(sizeof(*stolen), GFP_KERNEL);
if (!stolen)
- return NULL;
+ return ERR_PTR(-ENOMEM);
ret = i915_gem_stolen_insert_node(dev_priv, stolen, size, 4096);
if (ret) {
- kfree(stolen);
- return NULL;
+ obj = ERR_PTR(ret);
+ goto err_free;
}
obj = _i915_gem_object_create_stolen(dev_priv, stolen);
- if
[Intel-gfx] ✓ Fi.CI.BAT: success for LMEM basics (rev3)
== Series Details == Series: LMEM basics (rev3) URL : https://patchwork.freedesktop.org/series/67350/ State : success == Summary == CI Bug Log - changes from CI_DRM_7011 -> Patchwork_14674 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14674/index.html New tests - New tests have been introduced between CI_DRM_7011 and Patchwork_14674: ### New IGT tests (1) ### * igt@i915_selftest@live_memory_region: - Statuses : 43 pass(s) - Exec time: [0.39, 2.59] s Known issues Here are the changes found in Patchwork_14674 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14674/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html * igt@gem_exec_suspend@basic-s4-devices: - fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14674/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html Possible fixes * igt@gem_mmap_gtt@basic-small-bo-tiledy: - fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14674/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledy.html [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 Participating hosts (52 -> 44) -- Missing(8): fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7011 -> Patchwork_14674 CI-20190529: 20190529 CI_DRM_7011: 7d13733c2a87909eef8bc945ecbf4d47e0b67133 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5212: d17a484b3c22706b2b004ef1577f367d79235e43 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14674: 9db91fb25dfffa036289696db0609e06a0b7a1ff @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 9db91fb25dff HAX drm/i915: add the fake lmem region 625162b64039 drm/i915/selftests: check for missing aperture eca4aec7ec7e drm/i915: don't allocate the ring in stolen if we lack aperture bd4af504601f drm/i915: Don't try to place HWS in non-existing mappable region dacd250f584e drm/i915: error capture with no ggtt slot 69132ab6cb6e drm/i915: set num_fence_regs to 0 if there is no aperture 955419c5d802 drm/i915: do not map aperture if it is not available. a4c11ba258ec drm/i915: define i915_ggtt_has_aperture fe16f6f25391 drm/i915: treat stolen as a region 164771ef0b1f drm/i915: treat shmem as a region 2797cf97e640 drm/i915: enumerate and init each supported region 0dfe20962fb0 drm/i915/selftests: extend coverage to include LMEM huge-pages 5e5781be3c3c drm/i915/selftests: add write-dword test for LMEM aa7fd71d6788 drm/i915/lmem: support kernel mapping 94b66fcc5efd drm/i915: setup io-mapping for LMEM 97b8c777c4d0 drm/i915: support creating LMEM objects 6c7235302062 drm/i915: Add memory region information to device_info 0339d6513672 drm/i915/region: support volatile objects c846cb7cad7d drm/i915/region: support contiguous allocations 49d114bc9547 drm/i915: introduce intel_memory_region 230ce2751c83 drm/i915/stolen: make the object creation interface consistent == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14674/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for gpu: Fix Kconfig indentation (rev2)
== Series Details == Series: gpu: Fix Kconfig indentation (rev2) URL : https://patchwork.freedesktop.org/series/67121/ State : failure == Summary == Applying: gpu: Fix Kconfig indentation error: sha1 information is lacking or useless (drivers/gpu/drm/amd/display/Kconfig). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 gpu: Fix Kconfig indentation When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for LMEM basics (rev3)
== Series Details == Series: LMEM basics (rev3) URL : https://patchwork.freedesktop.org/series/67350/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/stolen: make the object creation interface consistent Okay! Commit: drm/i915: introduce intel_memory_region Okay! Commit: drm/i915/region: support contiguous allocations Okay! Commit: drm/i915/region: support volatile objects Okay! Commit: drm/i915: Add memory region information to device_info Okay! Commit: drm/i915: support creating LMEM objects Okay! Commit: drm/i915: setup io-mapping for LMEM Okay! Commit: drm/i915/lmem: support kernel mapping +drivers/gpu/drm/i915/gem/i915_gem_pages.c:177:42:expected void [noderef] *vaddr +drivers/gpu/drm/i915/gem/i915_gem_pages.c:177:42:got void *[assigned] ptr +drivers/gpu/drm/i915/gem/i915_gem_pages.c:177:42: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gem/i915_gem_pages.c:254:51:expected void * +drivers/gpu/drm/i915/gem/i915_gem_pages.c:254:51:got void [noderef] * +drivers/gpu/drm/i915/gem/i915_gem_pages.c:254:51: warning: incorrect type in return expression (different address spaces) +drivers/gpu/drm/i915/gem/i915_gem_pages.c:337:42:expected void [noderef] *vaddr +drivers/gpu/drm/i915/gem/i915_gem_pages.c:337:42:got void *[assigned] ptr +drivers/gpu/drm/i915/gem/i915_gem_pages.c:337:42: warning: incorrect type in argument 1 (different address spaces) Commit: drm/i915/selftests: add write-dword test for LMEM - +drivers/gpu/drm/i915/selftests/intel_memory_region.c:308:49: error: incompatible types in conditional expression (different address spaces) Commit: drm/i915/selftests: extend coverage to include LMEM huge-pages Okay! Commit: drm/i915: enumerate and init each supported region Okay! Commit: drm/i915: treat shmem as a region Okay! Commit: drm/i915: treat stolen as a region Okay! Commit: drm/i915: define i915_ggtt_has_aperture Okay! Commit: drm/i915: do not map aperture if it is not available. Okay! Commit: drm/i915: set num_fence_regs to 0 if there is no aperture Okay! Commit: drm/i915: error capture with no ggtt slot - +drivers/gpu/drm/i915/i915_gpu_error.c:1027:55:expected void *src +drivers/gpu/drm/i915/i915_gpu_error.c:1027:55:got void [noderef] *[assigned] s +drivers/gpu/drm/i915/i915_gpu_error.c:1027:55: warning: incorrect type in argument 2 (different address spaces) Commit: drm/i915: Don't try to place HWS in non-existing mappable region Okay! Commit: drm/i915: don't allocate the ring in stolen if we lack aperture Okay! Commit: drm/i915/selftests: check for missing aperture Okay! Commit: HAX drm/i915: add the fake lmem region Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/edid: Make drm_get_cea_aspect_ratio() static
== Series Details ==
Series: series starting with [1/4] drm/edid: Make drm_get_cea_aspect_ratio()
static
URL : https://patchwork.freedesktop.org/series/67600/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7011 -> Patchwork_14671
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14671/index.html
Known issues
Here are the changes found in Patchwork_14671 that come from known issues:
### IGT changes ###
Possible fixes
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][1] ([fdo#102614]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14671/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#109644]: https://bugs.freedesktop.org/show_bug.cgi?id=109644
[fdo#110464]: https://bugs.freedesktop.org/show_bug.cgi?id=110464
[fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
Participating hosts (52 -> 43)
--
Missing(9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-byt-clapper fi-icl-u3 fi-icl-y fi-icl-dsi fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7011 -> Patchwork_14671
CI-20190529: 20190529
CI_DRM_7011: 7d13733c2a87909eef8bc945ecbf4d47e0b67133 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5212: d17a484b3c22706b2b004ef1577f367d79235e43 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14671: 8fd224dba45f7a3dd151c161891e9c24c922 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8fd224dba45f drm/edid: Prep for HDMI VIC aspect ratio (WIP)
7e309f526aeb drm/edid: Fix HDMI VIC handling
efc34735a84d drm/edid: Extract drm_mode_cea_vic()
e1654b257fee drm/edid: Make drm_get_cea_aspect_ratio() static
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14671/index.html
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH TRIVIAL v2] gpu: Fix Kconfig indentation
Adjust indentation from spaces to tab (+optional two spaces) as in coding style with command like: $ sed -e 's/^/\t/' -i */Kconfig Signed-off-by: Krzysztof Kozlowski --- Changes since v1: 1. Fix also DRM_AMD_DC_HDCP (new arrival since v1). --- drivers/gpu/drm/Kconfig | 10 +- drivers/gpu/drm/amd/display/Kconfig | 32 ++--- drivers/gpu/drm/bridge/Kconfig | 8 +- drivers/gpu/drm/i915/Kconfig | 12 +- drivers/gpu/drm/i915/Kconfig.debug | 144 +++ drivers/gpu/drm/lima/Kconfig | 2 +- drivers/gpu/drm/mgag200/Kconfig | 8 +- drivers/gpu/drm/nouveau/Kconfig | 2 +- drivers/gpu/drm/omapdrm/displays/Kconfig | 6 +- drivers/gpu/drm/omapdrm/dss/Kconfig | 12 +- drivers/gpu/drm/rockchip/Kconfig | 8 +- drivers/gpu/drm/udl/Kconfig | 2 +- drivers/gpu/vga/Kconfig | 2 +- 13 files changed, 124 insertions(+), 124 deletions(-) diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index e67c194c2aca..7cb6e4eb99e8 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -207,8 +207,8 @@ config DRM_RADEON tristate "ATI Radeon" depends on DRM && PCI && MMU select FW_LOADER -select DRM_KMS_HELPER -select DRM_TTM + select DRM_KMS_HELPER + select DRM_TTM select POWER_SUPPLY select HWMON select BACKLIGHT_CLASS_DEVICE @@ -226,9 +226,9 @@ config DRM_AMDGPU tristate "AMD GPU" depends on DRM && PCI && MMU select FW_LOADER -select DRM_KMS_HELPER + select DRM_KMS_HELPER select DRM_SCHED -select DRM_TTM + select DRM_TTM select POWER_SUPPLY select HWMON select BACKLIGHT_CLASS_DEVICE @@ -266,7 +266,7 @@ config DRM_VKMS If M is selected the module will be called vkms. config DRM_ATI_PCIGART -bool + bool source "drivers/gpu/drm/exynos/Kconfig" diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index 1bbe762ee6ba..313183b80032 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -23,16 +23,16 @@ config DRM_AMD_DC_DCN2_0 depends on DRM_AMD_DC && X86 depends on DRM_AMD_DC_DCN1_0 help - Choose this option if you want to have - Navi support for display engine + Choose this option if you want to have + Navi support for display engine config DRM_AMD_DC_DCN2_1 -bool "DCN 2.1 family" -depends on DRM_AMD_DC && X86 -depends on DRM_AMD_DC_DCN2_0 -help -Choose this option if you want to have -Renoir support for display engine + bool "DCN 2.1 family" + depends on DRM_AMD_DC && X86 + depends on DRM_AMD_DC_DCN2_0 + help + Choose this option if you want to have + Renoir support for display engine config DRM_AMD_DC_DSC_SUPPORT bool "DSC support" @@ -41,16 +41,16 @@ config DRM_AMD_DC_DSC_SUPPORT depends on DRM_AMD_DC_DCN1_0 depends on DRM_AMD_DC_DCN2_0 help - Choose this option if you want to have - Dynamic Stream Compression support + Choose this option if you want to have + Dynamic Stream Compression support config DRM_AMD_DC_HDCP -bool "Enable HDCP support in DC" -depends on DRM_AMD_DC -help - Choose this option - if you want to support - HDCP authentication + bool "Enable HDCP support in DC" + depends on DRM_AMD_DC + help +Choose this option +if you want to support +HDCP authentication config DEBUG_KERNEL_DC bool "Enable kgdb break in DC" diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 1cc9f502c1f2..a5aa7ec16000 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -60,10 +60,10 @@ config DRM_MEGACHIPS_STDP_GE_B850V3_FW select DRM_KMS_HELPER select DRM_PANEL ---help--- - This is a driver for the display bridges of - GE B850v3 that convert dual channel LVDS - to DP++. This is used with the i.MX6 imx-ldb - driver. You are likely to say N here. + This is a driver for the display bridges of + GE B850v3 that convert dual channel LVDS + to DP++. This is used with the i.MX6 imx-ldb + driver. You are likely to say N here. config DRM_NXP_PTN3460 tristate "NXP PTN3460 DP/LVDS bridge" diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index 0d21402945ab..3c6d57df262d 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -76,7 +76,7 @@ config DRM_I915_CAPTURE_ERROR This option enables capturing the GPU state when a hang is detected. This
Re: [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Add Sphinx-compatible references to struct fields
On Thu, Oct 03, 2019 at 06:45:56PM -, Patchwork wrote: > == Series Details == > > Series: drm/i915: Add Sphinx-compatible references to struct fields > URL : https://patchwork.freedesktop.org/series/67550/ > State : failure > > == Summary == > > Applying: drm/i915: Add Sphinx-compatible references to struct fields > Using index info to reconstruct a base tree... > M drivers/gpu/drm/i915/i915_drv.h > Falling back to patching base and 3-way merge... > Auto-merging drivers/gpu/drm/i915/i915_drv.h > CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_drv.h I'm not sure what's wrong here. The patch applies cleanly to v5.4-rc1 and linux-next. Maybe patchwork is applying it to an older base? Thanks, Jonathan Neuschäfer signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for LMEM basics (rev3)
== Series Details ==
Series: LMEM basics (rev3)
URL : https://patchwork.freedesktop.org/series/67350/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
230ce2751c83 drm/i915/stolen: make the object creation interface consistent
-:89: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!obj"
#89: FILE: drivers/gpu/drm/i915/gem/i915_gem_stolen.c:602:
+ if (obj == NULL) {
total: 0 errors, 0 warnings, 1 checks, 150 lines checked
49d114bc9547 drm/i915: introduce intel_memory_region
-:59: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#59:
new file mode 100644
-:600: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment
#600: FILE: drivers/gpu/drm/i915/intel_memory_region.h:44:
+ struct mutex mm_lock;
total: 0 errors, 1 warnings, 1 checks, 775 lines checked
c846cb7cad7d drm/i915/region: support contiguous allocations
-:317: WARNING:LINE_SPACING: Missing a blank line after declarations
#317: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:130:
+ LIST_HEAD(holes);
+ I915_RND_STATE(prng);
total: 0 errors, 1 warnings, 0 checks, 393 lines checked
0339d6513672 drm/i915/region: support volatile objects
6c7235302062 drm/i915: Add memory region information to device_info
97b8c777c4d0 drm/i915: support creating LMEM objects
-:35: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#35:
new file mode 100644
-:137: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#137: FILE: drivers/gpu/drm/i915/intel_memory_region.c:10:
+#define REGION_MAP(type, inst) \
+ BIT((type) + INTEL_MEMORY_TYPE_SHIFT) | BIT(inst)
total: 1 errors, 1 warnings, 0 checks, 262 lines checked
94b66fcc5efd drm/i915: setup io-mapping for LMEM
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 34 lines checked
aa7fd71d6788 drm/i915/lmem: support kernel mapping
-:200: WARNING:LINE_SPACING: Missing a blank line after declarations
#200: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:282:
+ struct drm_i915_gem_object *obj;
+ I915_RND_STATE(prng);
total: 0 errors, 1 warnings, 0 checks, 273 lines checked
5e5781be3c3c drm/i915/selftests: add write-dword test for LMEM
-:19: CHECK:LINE_SPACING: Please don't use multiple blank lines
#19: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:10:
+
-:88: WARNING:LINE_SPACING: Missing a blank line after declarations
#88: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:312:
+ struct intel_context *ce;
+ I915_RND_STATE(prng);
-:168: WARNING:LINE_SPACING: Missing a blank line after declarations
#168: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:406:
+ struct drm_file *file;
+ I915_RND_STATE(prng);
total: 0 errors, 2 warnings, 1 checks, 198 lines checked
0dfe20962fb0 drm/i915/selftests: extend coverage to include LMEM huge-pages
-:8: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 151 lines checked
2797cf97e640 drm/i915: enumerate and init each supported region
164771ef0b1f drm/i915: treat shmem as a region
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 352 lines checked
fe16f6f25391 drm/i915: treat stolen as a region
a4c11ba258ec drm/i915: define i915_ggtt_has_aperture
955419c5d802 drm/i915: do not map aperture if it is not available.
-:38: CHECK:SPACING: No space is necessary after a cast
#38: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:3042:
+ (struct resource)
DEFINE_RES_MEM(pci_resource_start(pdev, 2),
total: 0 errors, 0 warnings, 1 checks, 51 lines checked
69132ab6cb6e drm/i915: set num_fence_regs to 0 if there is no aperture
dacd250f584e drm/i915: error capture with no ggtt slot
bd4af504601f drm/i915: Don't try to place HWS in non-existing mappable region
eca4aec7ec7e drm/i915: don't allocate the ring in stolen if we lack aperture
625162b64039 drm/i915/selftests: check for missing aperture
9db91fb25dff HAX drm/i915: add the fake lmem region
-:49: WARNING:PREFER_PR_LEVEL: Prefer [subsystem eg:
netdev]_info([subsystem]dev, ... then dev_info(dev, ... then pr_info(... to
printk(KERN_INFO ...
#49: FILE: arch/x86/kernel/early-quirks.c:624:
+ printk(KERN_INFO "Intel graphics fake LMEM starts at %pa\n",
total: 0 errors, 1 warnings, 0 checks, 228 lines checked
___
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[Intel-gfx] ✗ Fi.CI.BUILD: failure for Enable bigjoiner support, second approach. (rev2)
== Series Details == Series: Enable bigjoiner support, second approach. (rev2) URL : https://patchwork.freedesktop.org/series/67590/ State : failure == Summary == Applying: HAX to make DSC work on the icelake test system Applying: drm/i915: Fix for_each_intel_plane_mask definition Applying: drm/i915: Introduce and use intel_atomic_crtc_state_for_each_plane_state. Applying: drm/i915: Remove cursor use of properties for coordinates Applying: drm/i915: Use intel_plane_state in prepare and cleanup plane_fb Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_display.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/display/intel_display.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_display.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0005 drm/i915: Use intel_plane_state in prepare and cleanup plane_fb When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Use helpers for drm_mm_node booleans
== Series Details == Series: drm/i915: Use helpers for drm_mm_node booleans URL : https://patchwork.freedesktop.org/series/67602/ State : failure == Summary == Applying: drm/i915: Use helpers for drm_mm_node booleans Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c M drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c M drivers/gpu/drm/i915/i915_gem.c M drivers/gpu/drm/i915/i915_gem_evict.c M drivers/gpu/drm/i915/i915_vma.c M drivers/gpu/drm/i915/i915_vma.h Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_vma.h Auto-merging drivers/gpu/drm/i915/i915_vma.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_vma.c Auto-merging drivers/gpu/drm/i915/i915_gem_evict.c Auto-merging drivers/gpu/drm/i915/i915_gem.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_gem.c Auto-merging drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915: Use helpers for drm_mm_node booleans When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Move SAGV block time to dev_priv
On Fri, Sep 27, 2019 at 03:24:26PM -0700, James Ausmus wrote:
> In prep for newer platforms having more complicated ways to determine
> the SAGV block time, move the variable to dev_priv, and extract the
> setting to an initial setup function. While we're at it, update the if
> ladder to follow the new gen -> old gen order preference, and warn on
> any non-specified gen.
>
> v2: Shorten the function name (Ville), return directly (Ville), move
> sagv_block_time_us value to dev_priv (Ville)
>
> Cc: Ville Syrjälä
> Cc: Stanislav Lisovskiy
> Cc: Lucas De Marchi
> Signed-off-by: James Ausmus
> ---
>
> Ville - with the amount of v1..v2 change in this first patch, I wasn't
> comfortable applying your R-b, could you take another look? Patch 2 just
> has the trivial changes you suggested, so I kept that one.
Review ping. :)
Thanks!
-James
>
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/intel_pm.c | 33 -
> 2 files changed, 26 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 337d8306416a..87a835a0210b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1579,6 +1579,8 @@ struct drm_i915_private {
> I915_SAGV_NOT_CONTROLLED
> } sagv_status;
>
> + int sagv_block_time_us;
> +
> struct {
> /*
>* Raw watermark latency values:
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index bfcf03ab5245..b413a7f3bc5d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3642,6 +3642,26 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
> dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
> }
>
> +static void
> +skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
> +{
> + if (IS_GEN(dev_priv, 11)) {
> + dev_priv->sagv_block_time_us = 10;
> + return;
> + } else if (IS_GEN(dev_priv, 10)) {
> + dev_priv->sagv_block_time_us = 20;
> + return;
> + } else if (IS_GEN(dev_priv, 9)) {
> + dev_priv->sagv_block_time_us = 30;
> + return;
> + } else {
> + MISSING_CASE(INTEL_GEN(dev_priv));
> + }
> +
> + /* Default to an unusable block time */
> + dev_priv->sagv_block_time_us = 1000;
> +}
> +
> /*
> * SAGV dynamically adjusts the system agent voltage and clock frequencies
> * depending on power and performance requirements. The display engine access
> @@ -3730,18 +3750,10 @@ bool intel_can_enable_sagv(struct intel_atomic_state
> *state)
> struct intel_crtc_state *crtc_state;
> enum pipe pipe;
> int level, latency;
> - int sagv_block_time_us;
>
> if (!intel_has_sagv(dev_priv))
> return false;
>
> - if (IS_GEN(dev_priv, 9))
> - sagv_block_time_us = 30;
> - else if (IS_GEN(dev_priv, 10))
> - sagv_block_time_us = 20;
> - else
> - sagv_block_time_us = 10;
> -
> /*
>* If there are no active CRTCs, no additional checks need be performed
>*/
> @@ -3788,7 +3800,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state
> *state)
>* incur memory latencies higher than sagv_block_time_us we
>* can't enable SAGV.
>*/
> - if (latency < sagv_block_time_us)
> + if (latency < dev_priv->sagv_block_time_us)
> return false;
> }
>
> @@ -9013,6 +9025,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
> else if (IS_GEN(dev_priv, 5))
> i915_ironlake_get_mem_freq(dev_priv);
>
> + if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> + skl_setup_sagv_block_time(dev_priv);
> +
> /* For FIFO watermark updates */
> if (INTEL_GEN(dev_priv) >= 9) {
> skl_setup_wm_latency(dev_priv);
> --
> 2.22.1
>
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: customize DPCD brightness control for specific panel
== Series Details == Series: drm/i915: customize DPCD brightness control for specific panel URL : https://patchwork.freedesktop.org/series/67595/ State : success == Summary == CI Bug Log - changes from CI_DRM_7011 -> Patchwork_14670 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14670/index.html Known issues Here are the changes found in Patchwork_14670 that come from known issues: ### IGT changes ### Issues hit * igt@gem_basic@create-fd-close: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/fi-icl-u3/igt@gem_ba...@create-fd-close.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14670/fi-icl-u3/igt@gem_ba...@create-fd-close.html * igt@gem_ctx_create@basic-files: - fi-icl-u3: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] / [fdo#109100]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14670/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html * igt@kms_chamelium@dp-edid-read: - fi-kbl-7500u: [PASS][5] -> [WARN][6] ([fdo#109483]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14670/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][7] -> [FAIL][8] ([fdo#111045] / [fdo#111096]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7011/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14670/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100 [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483 [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 Participating hosts (52 -> 42) -- Missing(10): fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-kbl-guc fi-gdg-551 fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7011 -> Patchwork_14670 CI-20190529: 20190529 CI_DRM_7011: 7d13733c2a87909eef8bc945ecbf4d47e0b67133 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5212: d17a484b3c22706b2b004ef1577f367d79235e43 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14670: 84d67190854beb3f0c5d0809b82646bc3250cac3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 84d67190854b drm/i915: customize DPCD brightness control for specific panel == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14670/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 18/21] drm/i915: Don't try to place HWS in non-existing mappable region
Quoting Matthew Auld (2019-10-04 18:04:49) > From: Michal Wajdeczko > > HWS placement restrictions can't just rely on HAS_LLC flag. > > Signed-off-by: Michal Wajdeczko > Signed-off-by: Matthew Auld > Cc: Daniele Ceraolo Spurio > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 80fd072ac719..f6799ef9915a 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -513,7 +513,8 @@ static int pin_ggtt_status_page(struct intel_engine_cs > *engine, > unsigned int flags; > > flags = PIN_GLOBAL; > - if (!HAS_LLC(engine->i915)) > + if (!HAS_LLC(engine->i915) && > + i915_ggtt_has_aperture(>i915->ggtt)) engine->gt->ggtt is the preferred abstracted route. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: customize DPCD brightness control for specific panel
== Series Details ==
Series: drm/i915: customize DPCD brightness control for specific panel
URL : https://patchwork.freedesktop.org/series/67595/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
84d67190854b drm/i915: customize DPCD brightness control for specific panel
-:88: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u8' over 'uint8_t'
#88: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:39:
+ uint8_t read_val[2] = { 0x0 };
-:93: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#93: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:44:
+ DRM_DEBUG_KMS("Failed to read DPCD register %x\n",
+ DPCD_EDP_BRIGHTNESS_NITS);
-:106: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u8' over 'uint8_t'
#106: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:57:
+ uint8_t new_vals[4];
-:121: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#121: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:72:
+static void intel_dp_aux_enable_customize_backlight(const struct
intel_crtc_state *crtc_state,
+ const struct drm_connector_state
*conn_state)
-:125: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u8' over 'uint8_t'
#125: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:76:
+ uint8_t read_val[4], i;
-:126: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u8' over 'uint8_t'
#126: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:77:
+ uint8_t write_val[8] = {0x00, 0x00, 0xF0, 0x01, 0x90, 0x01, 0x00, 0x00};
-:128: WARNING:LONG_LINE: line over 100 characters
#128: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:79:
+ if (drm_dp_dpcd_write(_dp->aux,
DPCD_EDP_PANEL_LUMINANCE_OVERRIDE, write_val, sizeof(write_val)) < 0)
-:133: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#133: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:84:
+ DRM_DEBUG_KMS("Failed to write %x\n",
+ DPCD_EDP_BRIGHTNESS_OPTIMIZATION);
-:143: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#143: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:94:
+ DRM_DEBUG_KMS("Failed to read %x\n",
+ DPCD_EDP_GETSET_CTRL_PARAMS);
-:147: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#147: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:98:
+ DRM_DEBUG_KMS("Failed to write %x\n",
+ DPCD_EDP_GETSET_CTRL_PARAMS);
-:151: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#151: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:102:
+ DRM_DEBUG_KMS("Failed to read %x\n",
+ DPCD_EDP_GETSET_CTRL_PARAMS);
-:153: WARNING:LONG_LINE: line over 100 characters
#153: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:104:
+ if (drm_dp_dpcd_read(_dp->aux, DPCD_EDP_CONTENT_LUMINANCE,
_val, sizeof(read_val)) < 0)
-:155: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#155: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:106:
+ DRM_DEBUG_KMS("Failed to read %x\n",
+ DPCD_EDP_CONTENT_LUMINANCE);
-:158: WARNING:LONG_LINE: line over 100 characters
#158: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:109:
+ if (drm_dp_dpcd_write(_dp->aux, DPCD_EDP_CONTENT_LUMINANCE,
read_val, sizeof(read_val)) < 0)
-:160: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#160: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:111:
+ DRM_DEBUG_KMS("Failed to write %x\n",
+ DPCD_EDP_CONTENT_LUMINANCE);
-:164: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#164: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:115:
+ DRM_DEBUG_KMS("Failed to read %x\n",
+ DPCD_EDP_GETSET_CTRL_PARAMS);
-:182: WARNING:LONG_LINE: line over 100 characters
#182: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:133:
+static void intel_dp_aux_disable_customize_backlight(const struct
drm_connector_state *old_conn_state)
-:186: WARNING:RETURN_VOID: void function return statements are not generally
useful
#186: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:137:
+ return;
+}
-:196: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#196: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:340:
+static int intel_dp_aux_setup_customize_backlight(struct intel_connector
*connector,
+ enum pipe pipe)
total: 0 errors, 5 warnings, 14 checks, 211 lines checked
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[Intel-gfx] [PATCH v3 17/21] drm/i915: error capture with no ggtt slot
From: Daniele Ceraolo Spurio
If the aperture is not available in HW we can't use a ggtt slot and wc
copy, so fall back to regular kmap.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 19
drivers/gpu/drm/i915/i915_gpu_error.c | 66 ++-
2 files changed, 65 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ad123b84880d..235028ad684f 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2661,7 +2661,8 @@ static void ggtt_release_guc_top(struct i915_ggtt *ggtt)
static void cleanup_init_ggtt(struct i915_ggtt *ggtt)
{
ggtt_release_guc_top(ggtt);
- drm_mm_remove_node(>error_capture);
+ if (drm_mm_node_allocated(>error_capture))
+ drm_mm_remove_node(>error_capture);
}
static int init_ggtt(struct i915_ggtt *ggtt)
@@ -2692,13 +2693,15 @@ static int init_ggtt(struct i915_ggtt *ggtt)
if (ret)
return ret;
- /* Reserve a mappable slot for our lockless error capture */
- ret = drm_mm_insert_node_in_range(>vm.mm, >error_capture,
- PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
- 0, ggtt->mappable_end,
- DRM_MM_INSERT_LOW);
- if (ret)
- return ret;
+ if (ggtt->mappable_end) {
+ /* Reserve a mappable slot for our lockless error capture */
+ ret = drm_mm_insert_node_in_range(>vm.mm,
>error_capture,
+ PAGE_SIZE, 0,
I915_COLOR_UNEVICTABLE,
+ 0, ggtt->mappable_end,
+ DRM_MM_INSERT_LOW);
+ if (ret)
+ return ret;
+ }
/*
* The upper portion of the GuC address space has a sizeable hole
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 5cf4eed5add8..26c3d9c75ab5 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -40,6 +40,7 @@
#include "display/intel_overlay.h"
#include "gem/i915_gem_context.h"
+#include "gem/i915_gem_lmem.h"
#include "i915_drv.h"
#include "i915_gpu_error.h"
@@ -235,6 +236,7 @@ struct compress {
struct pagevec pool;
struct z_stream_s zstream;
void *tmp;
+ bool wc;
};
static bool compress_init(struct compress *c)
@@ -292,7 +294,7 @@ static int compress_page(struct compress *c,
struct z_stream_s *zstream = >zstream;
zstream->next_in = src;
- if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
+ if (c->wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
zstream->next_in = c->tmp;
zstream->avail_in = PAGE_SIZE;
@@ -367,6 +369,7 @@ static void err_compression_marker(struct
drm_i915_error_state_buf *m)
struct compress {
struct pagevec pool;
+ bool wc;
};
static bool compress_init(struct compress *c)
@@ -389,7 +392,7 @@ static int compress_page(struct compress *c,
if (!ptr)
return -ENOMEM;
- if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE))
+ if (!(c->wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE)))
memcpy(ptr, src, PAGE_SIZE);
dst->pages[dst->page_count++] = ptr;
@@ -970,7 +973,6 @@ i915_error_object_create(struct drm_i915_private *i915,
struct drm_i915_error_object *dst;
unsigned long num_pages;
struct sgt_iter iter;
- dma_addr_t dma;
int ret;
might_sleep();
@@ -996,17 +998,54 @@ i915_error_object_create(struct drm_i915_private *i915,
dst->page_count = 0;
dst->unused = 0;
+ compress->wc = i915_gem_object_is_lmem(vma->obj) ||
+ drm_mm_node_allocated(>error_capture);
+
ret = -EINVAL;
- for_each_sgt_daddr(dma, iter, vma->pages) {
+ if (drm_mm_node_allocated(>error_capture)) {
void __iomem *s;
+ dma_addr_t dma;
- ggtt->vm.insert_page(>vm, dma, slot, I915_CACHE_NONE, 0);
+ for_each_sgt_daddr(dma, iter, vma->pages) {
+ ggtt->vm.insert_page(>vm, dma, slot,
+I915_CACHE_NONE, 0);
- s = io_mapping_map_wc(>iomap, slot, PAGE_SIZE);
- ret = compress_page(compress, (void __force *)s, dst);
- io_mapping_unmap(s);
- if (ret)
- break;
+ s = io_mapping_map_wc(>iomap, slot, PAGE_SIZE);
+ ret = compress_page(compress, (void __force *)s, dst);
+ io_mapping_unmap(s);
+
[Intel-gfx] [PATCH v3 13/21] drm/i915: treat stolen as a region
Convert stolen memory over to a region object. Still leaves open the
question with what to do with pre-allocated objects...
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 65 +++---
drivers/gpu/drm/i915/gem/i915_gem_stolen.h | 3 +-
drivers/gpu/drm/i915/i915_gem_gtt.c| 14 +
drivers/gpu/drm/i915/i915_pci.c| 2 +-
4 files changed, 61 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 2a34355b738f..a452f992e71c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -10,6 +10,7 @@
#include
#include
+#include "gem/i915_gem_region.h"
#include "i915_drv.h"
#include "i915_gem_stolen.h"
@@ -150,7 +151,7 @@ static int i915_adjust_stolen(struct drm_i915_private
*dev_priv,
return 0;
}
-void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv)
+static void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv)
{
if (!drm_mm_initialized(_priv->mm.stolen))
return;
@@ -355,7 +356,7 @@ static void icl_get_stolen_reserved(struct drm_i915_private
*i915,
}
}
-int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
+static int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
{
resource_size_t reserved_base, stolen_top;
resource_size_t reserved_total, reserved_size;
@@ -539,6 +540,9 @@ i915_gem_object_release_stolen(struct drm_i915_gem_object
*obj)
i915_gem_stolen_remove_node(dev_priv, stolen);
kfree(stolen);
+
+ if (obj->mm.region)
+ i915_gem_object_release_memory_region(obj);
}
static const struct drm_i915_gem_object_ops i915_gem_object_stolen_ops = {
@@ -548,8 +552,9 @@ static const struct drm_i915_gem_object_ops
i915_gem_object_stolen_ops = {
};
static struct drm_i915_gem_object *
-_i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
- struct drm_mm_node *stolen)
+__i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
+ struct drm_mm_node *stolen,
+ struct intel_memory_region *mem)
{
struct drm_i915_gem_object *obj;
unsigned int cache_level;
@@ -566,6 +571,9 @@ _i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
cache_level = HAS_LLC(dev_priv) ? I915_CACHE_LLC : I915_CACHE_NONE;
i915_gem_object_set_cache_coherency(obj, cache_level);
+ if (mem)
+ i915_gem_object_init_memory_region(obj, mem, 0);
+
if (i915_gem_object_pin_pages(obj))
goto cleanup;
@@ -576,10 +584,12 @@ _i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
return NULL;
}
-struct drm_i915_gem_object *
-i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
- resource_size_t size)
+static struct drm_i915_gem_object *
+_i915_gem_object_create_stolen(struct intel_memory_region *mem,
+ resource_size_t size,
+ unsigned int flags)
{
+ struct drm_i915_private *dev_priv = mem->i915;
struct drm_i915_gem_object *obj;
struct drm_mm_node *stolen;
int ret;
@@ -598,7 +608,7 @@ i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
if (ret)
goto err_free;
- obj = _i915_gem_object_create_stolen(dev_priv, stolen);
+ obj = __i915_gem_object_create_stolen(dev_priv, stolen, mem);
if (obj == NULL) {
ret = -ENOMEM;
goto err_remove;
@@ -613,6 +623,43 @@ i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
return ERR_PTR(ret);
}
+struct drm_i915_gem_object *
+i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
+ resource_size_t size)
+{
+ return
i915_gem_object_create_region(dev_priv->mm.regions[INTEL_MEMORY_STOLEN],
+size, I915_BO_ALLOC_CONTIGUOUS);
+}
+
+static int init_stolen(struct intel_memory_region *mem)
+{
+ /*
+* Initialise stolen early so that we may reserve preallocated
+* objects for the BIOS to KMS transition.
+*/
+ return i915_gem_init_stolen(mem->i915);
+}
+
+static void release_stolen(struct intel_memory_region *mem)
+{
+ i915_gem_cleanup_stolen(mem->i915);
+}
+
+static const struct intel_memory_region_ops i915_region_stolen_ops = {
+ .init = init_stolen,
+ .release = release_stolen,
+ .create_object = _i915_gem_object_create_stolen,
+};
+
+struct intel_memory_region *i915_gem_stolen_setup(struct drm_i915_private
*i915)
+{
+ return intel_memory_region_create(i915,
+ intel_graphics_stolen_res.start,
+
[Intel-gfx] [PATCH v3 18/21] drm/i915: Don't try to place HWS in non-existing mappable region
From: Michal Wajdeczko HWS placement restrictions can't just rely on HAS_LLC flag. Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Auld Cc: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 80fd072ac719..f6799ef9915a 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -513,7 +513,8 @@ static int pin_ggtt_status_page(struct intel_engine_cs *engine, unsigned int flags; flags = PIN_GLOBAL; - if (!HAS_LLC(engine->i915)) + if (!HAS_LLC(engine->i915) && + i915_ggtt_has_aperture(>i915->ggtt)) /* * On g33, we cannot place HWS above 256MiB, so * restrict its pinning to the low mappable arena. -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 14/21] drm/i915: define i915_ggtt_has_aperture
From: Daniele Ceraolo Spurio
The following patches in the series will use it to avoid certain
operations when the mappable aperture is not available in HW.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 0a18fdfe63ff..62b586c4cf71 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -570,6 +570,11 @@ void i915_ggtt_disable_guc(struct i915_ggtt *ggtt);
int i915_init_ggtt(struct drm_i915_private *dev_priv);
void i915_ggtt_driver_release(struct drm_i915_private *dev_priv);
+static inline bool i915_ggtt_has_aperture(struct i915_ggtt *ggtt)
+{
+ return ggtt->mappable_end > 0;
+}
+
int i915_ppgtt_init_hw(struct intel_gt *gt);
struct i915_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 12/21] drm/i915: treat shmem as a region
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 5 +-
drivers/gpu/drm/i915/gem/i915_gem_region.c| 14 +++-
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 74 ++-
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_gem.c | 9 ---
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 +-
drivers/gpu/drm/i915/i915_pci.c | 29 ++--
.../gpu/drm/i915/selftests/mock_gem_device.c | 6 +-
8 files changed, 99 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
index 768356908160..8043ff63d73f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
@@ -16,6 +16,7 @@
#include "gt/intel_gt.h"
#include "i915_drv.h"
#include "i915_gem_object.h"
+#include "i915_gem_region.h"
#include "i915_scatterlist.h"
static int i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
@@ -191,8 +192,10 @@ int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj, int align)
/* Perma-pin (until release) the physical set of pages */
__i915_gem_object_pin_pages(obj);
- if (!IS_ERR_OR_NULL(pages))
+ if (!IS_ERR_OR_NULL(pages)) {
i915_gem_shmem_ops.put_pages(obj, pages);
+ i915_gem_object_release_memory_region(obj);
+ }
mutex_unlock(>mm.lock);
return 0;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index 663254b3da21..0c03c2c40dbc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -6,6 +6,7 @@
#include "intel_memory_region.h"
#include "i915_gem_region.h"
#include "i915_drv.h"
+#include "i915_trace.h"
void
i915_gem_object_put_pages_buddy(struct drm_i915_gem_object *obj,
@@ -146,11 +147,22 @@ i915_gem_object_create_region(struct intel_memory_region
*mem,
GEM_BUG_ON(!size);
GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_MIN_ALIGNMENT));
+ /*
+* There is a prevalence of the assumption that we fit the object's
+* page count inside a 32bit _signed_ variable. Let's document this and
+* catch if we ever need to fix it. In the meantime, if you do spot
+* such a local variable, please consider fixing!
+*/
+
if (size >> PAGE_SHIFT > INT_MAX)
return ERR_PTR(-E2BIG);
if (overflows_type(size, obj->base.size))
return ERR_PTR(-E2BIG);
- return mem->ops->create_object(mem, size, flags);
+ obj = mem->ops->create_object(mem, size, flags);
+ if (!IS_ERR(obj))
+ trace_i915_gem_object_create(obj);
+
+ return obj;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 4c4954e8ce0a..f468a3424df4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -7,7 +7,9 @@
#include
#include
+#include "gem/i915_gem_region.h"
#include "i915_drv.h"
+#include "i915_gemfs.h"
#include "i915_gem_object.h"
#include "i915_scatterlist.h"
#include "i915_trace.h"
@@ -26,6 +28,7 @@ static void check_release_pagevec(struct pagevec *pvec)
static int shmem_get_pages(struct drm_i915_gem_object *obj)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct intel_memory_region *mem = obj->mm.region;
const unsigned long page_count = obj->base.size / PAGE_SIZE;
unsigned long i;
struct address_space *mapping;
@@ -52,7 +55,7 @@ static int shmem_get_pages(struct drm_i915_gem_object *obj)
* If there's no chance of allocating enough pages for the whole
* object, bail early.
*/
- if (page_count > totalram_pages())
+ if (obj->base.size > resource_size(>region))
return -ENOMEM;
st = kmalloc(sizeof(*st), GFP_KERNEL);
@@ -417,6 +420,8 @@ shmem_pwrite(struct drm_i915_gem_object *obj,
static void shmem_release(struct drm_i915_gem_object *obj)
{
+ i915_gem_object_release_memory_region(obj);
+
fput(obj->base.filp);
}
@@ -434,9 +439,9 @@ const struct drm_i915_gem_object_ops i915_gem_shmem_ops = {
.release = shmem_release,
};
-static int create_shmem(struct drm_i915_private *i915,
- struct drm_gem_object *obj,
- size_t size)
+static int __create_shmem(struct drm_i915_private *i915,
+ struct drm_gem_object *obj,
+ size_t size)
{
unsigned long flags = VM_NORESERVE;
struct file *filp;
@@ -455,31 +460,23 @@ static int create_shmem(struct drm_i915_private *i915,
return 0;
}
-struct drm_i915_gem_object *
-i915_gem_object_create_shmem(struct drm_i915_private *i915, u64 size)
+static struct
[Intel-gfx] [PATCH v3 21/21] HAX drm/i915: add the fake lmem region
Intended for upstream testing so that we can still exercise the LMEM
plumbing and !HAS_MAPPABLE_APERTURE paths. Smoke tested on Skull Canyon
device. This works by allocating an intel_memory_region for a reserved
portion of system memory, which we treat like LMEM. For the LMEMBAR we
steal the aperture and 1:1 it map to the stolen region.
To enable simply set i915_fake_lmem_start= on the kernel cmdline with the
start of reserved region(see memmap=). The size of the region we can
use is determined by the size of the mappable aperture, so the size of
reserved region should be >= mappable_end.
eg. memmap=2G$16G i915_fake_lmem_start=0x4
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
arch/x86/kernel/early-quirks.c | 26 +++
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 3 +
drivers/gpu/drm/i915/i915_drv.c| 8 ++
drivers/gpu/drm/i915/i915_gem_gtt.c| 3 +
drivers/gpu/drm/i915/intel_memory_region.h | 6 ++
drivers/gpu/drm/i915/intel_region_lmem.c | 90 ++
drivers/gpu/drm/i915/intel_region_lmem.h | 5 ++
include/drm/i915_drm.h | 3 +
8 files changed, 144 insertions(+)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 6f6b1d04dadf..9b04655e3926 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -603,6 +603,32 @@ static void __init intel_graphics_quirks(int num, int
slot, int func)
}
}
+struct resource intel_graphics_fake_lmem_res __ro_after_init =
DEFINE_RES_MEM(0, 0);
+EXPORT_SYMBOL(intel_graphics_fake_lmem_res);
+
+static int __init early_i915_fake_lmem_init(char *s)
+{
+ u64 start;
+ int ret;
+
+ if (*s == '=')
+ s++;
+
+ ret = kstrtoull(s, 16, );
+ if (ret)
+ return ret;
+
+ intel_graphics_fake_lmem_res.start = start;
+ intel_graphics_fake_lmem_res.end = SZ_2G; /* Placeholder; depends on
aperture size */
+
+ printk(KERN_INFO "Intel graphics fake LMEM starts at %pa\n",
+ _graphics_fake_lmem_res.start);
+
+ return 0;
+}
+
+early_param("i915_fake_lmem_start", early_i915_fake_lmem_init);
+
static void __init force_disable_hpet(int num, int slot, int func)
{
#ifdef CONFIG_HPET_TIMER
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index fd8b63dd154d..b48f95ba336f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -23,6 +23,7 @@ void __iomem *i915_gem_object_lmem_io_map_page(struct
drm_i915_gem_object *obj,
resource_size_t offset;
offset = i915_gem_object_get_dma_address(obj, n);
+ offset -= obj->mm.region->region.start;
return io_mapping_map_wc(>mm.region->iomap, offset, PAGE_SIZE);
}
@@ -33,6 +34,7 @@ void __iomem *i915_gem_object_lmem_io_map_page_atomic(struct
drm_i915_gem_object
resource_size_t offset;
offset = i915_gem_object_get_dma_address(obj, n);
+ offset -= obj->mm.region->region.start;
return io_mapping_map_atomic_wc(>mm.region->iomap, offset);
}
@@ -46,6 +48,7 @@ void __iomem *i915_gem_object_lmem_io_map(struct
drm_i915_gem_object *obj,
GEM_BUG_ON(!i915_gem_object_is_contiguous(obj));
offset = i915_gem_object_get_dma_address(obj, n);
+ offset -= obj->mm.region->region.start;
return io_mapping_map_wc(>mm.region->iomap, offset, size);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 024da582ba0f..fdd548299156 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1526,6 +1526,14 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
+ /* Check if we support fake LMEM -- enable for live selftests */
+ if (INTEL_GEN(dev_priv) >= 9 && i915_selftest.live &&
+ intel_graphics_fake_lmem_res.start) {
+ mkwrite_device_info(dev_priv)->memory_regions =
+ REGION_SMEM | REGION_LMEM | REGION_STOLEN;
+ GEM_BUG_ON(!HAS_LMEM(dev_priv));
+ }
+
ret = pci_enable_device(pdev);
if (ret)
goto out_fini;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 235028ad684f..146b2c0573e8 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2778,6 +2778,9 @@ int i915_gem_init_memory_regions(struct drm_i915_private
*i915)
case INTEL_STOLEN:
mem = i915_gem_stolen_setup(i915);
break;
+ case INTEL_LMEM:
+ mem = intel_setup_fake_lmem(i915);
+ break;
}
if (IS_ERR(mem)) {
[Intel-gfx] [PATCH v3 04/21] drm/i915/region: support volatile objects
Volatile objects are marked as DONTNEED while pinned, therefore once
unpinned the backing store can be discarded. This is limited to kernel
internal objects.
Signed-off-by: Matthew Auld
Signed-off-by: CQ Tang
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_internal.c| 17 +
drivers/gpu/drm/i915/gem/i915_gem_object.h | 12
.../gpu/drm/i915/gem/i915_gem_object_types.h| 9 -
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 6 ++
drivers/gpu/drm/i915/gem/i915_gem_region.c | 13 +
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 12
drivers/gpu/drm/i915/intel_memory_region.c | 4
drivers/gpu/drm/i915/intel_memory_region.h | 5 +
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 5 ++---
9 files changed, 63 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
index 0c41e04ab8fa..5ae694c24df4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
@@ -117,13 +117,6 @@ static int i915_gem_object_get_pages_internal(struct
drm_i915_gem_object *obj)
goto err;
}
- /* Mark the pages as dontneed whilst they are still pinned. As soon
-* as they are unpinned they are allowed to be reaped by the shrinker,
-* and the caller is expected to repopulate - the contents of this
-* object are only valid whilst active and pinned.
-*/
- obj->mm.madv = I915_MADV_DONTNEED;
-
__i915_gem_object_set_pages(obj, st, sg_page_sizes);
return 0;
@@ -143,7 +136,6 @@ static void i915_gem_object_put_pages_internal(struct
drm_i915_gem_object *obj,
internal_free_pages(pages);
obj->mm.dirty = false;
- obj->mm.madv = I915_MADV_WILLNEED;
}
static const struct drm_i915_gem_object_ops i915_gem_object_internal_ops = {
@@ -188,6 +180,15 @@ i915_gem_object_create_internal(struct drm_i915_private
*i915,
drm_gem_private_object_init(>drm, >base, size);
i915_gem_object_init(obj, _gem_object_internal_ops);
+ /*
+* Mark the object as volatile, such that the pages are marked as
+* dontneed whilst they are still pinned. As soon as they are unpinned
+* they are allowed to be reaped by the shrinker, and the caller is
+* expected to repopulate - the contents of this object are only valid
+* whilst active and pinned.
+*/
+ i915_gem_object_set_volatile(obj);
+
obj->read_domains = I915_GEM_DOMAIN_CPU;
obj->write_domain = I915_GEM_DOMAIN_CPU;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index dfd16d65630f..c5e14c9c805c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -145,6 +145,18 @@ i915_gem_object_is_contiguous(const struct
drm_i915_gem_object *obj)
return obj->flags & I915_BO_ALLOC_CONTIGUOUS;
}
+static inline bool
+i915_gem_object_is_volatile(const struct drm_i915_gem_object *obj)
+{
+ return obj->flags & I915_BO_ALLOC_VOLATILE;
+}
+
+static inline void
+i915_gem_object_set_volatile(struct drm_i915_gem_object *obj)
+{
+ obj->flags |= I915_BO_ALLOC_VOLATILE;
+}
+
static inline bool
i915_gem_object_type_has(const struct drm_i915_gem_object *obj,
unsigned long flags)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index c6a712cf7d7a..a387e3ee728b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -121,7 +121,8 @@ struct drm_i915_gem_object {
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
-#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS)
+#define I915_BO_ALLOC_VOLATILE BIT(1)
+#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | I915_BO_ALLOC_VOLATILE)
/*
* Is the object to be mapped as read-only to the GPU
@@ -172,6 +173,12 @@ struct drm_i915_gem_object {
* List of memory region blocks allocated for this object.
*/
struct list_head blocks;
+ /**
+* Element within memory_region->objects or region->purgeable
+* if the object is marked as DONTNEED. Access is protected by
+* region->obj_lock.
+*/
+ struct list_head region_link;
struct sg_table *pages;
void *mapping;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 2e941f093a20..b0ec0959c13f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -18,6 +18,9 @@ void __i915_gem_object_set_pages(struct
[Intel-gfx] [PATCH v3 15/21] drm/i915: do not map aperture if it is not available.
From: Daniele Ceraolo Spurio
Skip both setup and cleanup of the aperture mapping if the HW doesn't
have an aperture bar.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 32 ++---
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 44900596fec6..ad123b84880d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2823,7 +2823,9 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
i915_address_space_fini(>vm);
arch_phys_wc_del(ggtt->mtrr);
- io_mapping_fini(>iomap);
+
+ if (ggtt->iomap.size)
+ io_mapping_fini(>iomap);
}
/**
@@ -3034,10 +3036,13 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
int err;
/* TODO: We're not aware of mappable constraints on gen8 yet */
- ggtt->gmadr =
- (struct resource) DEFINE_RES_MEM(pci_resource_start(pdev, 2),
-pci_resource_len(pdev, 2));
- ggtt->mappable_end = resource_size(>gmadr);
+ /* FIXME: We probably need to add do device_info or runtime_info */
+ if (!HAS_LMEM(dev_priv)) {
+ ggtt->gmadr =
+ (struct resource)
DEFINE_RES_MEM(pci_resource_start(pdev, 2),
+pci_resource_len(pdev,
2));
+ ggtt->mappable_end = resource_size(>gmadr);
+ }
err = pci_set_dma_mask(pdev, DMA_BIT_MASK(39));
if (!err)
@@ -3260,14 +3265,17 @@ static int ggtt_init_hw(struct i915_ggtt *ggtt)
if (!HAS_LLC(i915) && !HAS_PPGTT(i915))
ggtt->vm.mm.color_adjust = i915_ggtt_color_adjust;
- if (!io_mapping_init_wc(>iomap,
- ggtt->gmadr.start,
- ggtt->mappable_end)) {
- ggtt->vm.cleanup(>vm);
- return -EIO;
- }
+ if (ggtt->mappable_end) {
+ if (!io_mapping_init_wc(>iomap,
+ ggtt->gmadr.start,
+ ggtt->mappable_end)) {
+ ggtt->vm.cleanup(>vm);
+ return -EIO;
+ }
- ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start, ggtt->mappable_end);
+ ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start,
+ ggtt->mappable_end);
+ }
i915_ggtt_init_fences(ggtt);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 00/21] LMEM basics
The basic LMEM bits, minus the uAPI, pruning, etc. The goal is to support basic LMEM object creation within the kernel. From there we can start with the dumb buffer support, and then the other display related bits. Quick respin with a bunch of minor tweaks + rebasing on the now merged struct_mutex removal patches. Abdiel Janulgue (4): drm/i915: Add memory region information to device_info drm/i915: setup io-mapping for LMEM drm/i915/lmem: support kernel mapping drm/i915: enumerate and init each supported region CQ Tang (1): drm/i915/stolen: make the object creation interface consistent Daniele Ceraolo Spurio (4): drm/i915: define i915_ggtt_has_aperture drm/i915: do not map aperture if it is not available. drm/i915: set num_fence_regs to 0 if there is no aperture drm/i915: error capture with no ggtt slot Matthew Auld (11): drm/i915: introduce intel_memory_region drm/i915/region: support contiguous allocations drm/i915/region: support volatile objects drm/i915: support creating LMEM objects drm/i915/selftests: add write-dword test for LMEM drm/i915/selftests: extend coverage to include LMEM huge-pages drm/i915: treat shmem as a region drm/i915: treat stolen as a region drm/i915: don't allocate the ring in stolen if we lack aperture drm/i915/selftests: check for missing aperture HAX drm/i915: add the fake lmem region Michal Wajdeczko (1): drm/i915: Don't try to place HWS in non-existing mappable region arch/x86/kernel/early-quirks.c| 26 + drivers/gpu/drm/i915/Makefile | 4 + drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/display/intel_fbdev.c| 4 +- drivers/gpu/drm/i915/display/intel_overlay.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_internal.c | 17 +- drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 68 ++ drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 31 + drivers/gpu/drm/i915/gem/i915_gem_object.h| 18 + .../gpu/drm/i915/gem/i915_gem_object_types.h | 29 +- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 28 +- drivers/gpu/drm/i915/gem/i915_gem_phys.c | 5 +- drivers/gpu/drm/i915/gem/i915_gem_region.c| 168 + drivers/gpu/drm/i915/gem/i915_gem_region.h| 29 + drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 74 ++- drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 99 ++- drivers/gpu/drm/i915/gem/i915_gem_stolen.h| 3 +- .../gpu/drm/i915/gem/selftests/huge_pages.c | 218 ++- .../i915/gem/selftests/i915_gem_coherency.c | 5 +- .../drm/i915/gem/selftests/i915_gem_mman.c| 6 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 +- drivers/gpu/drm/i915/gt/intel_gt.c| 2 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 8 +- drivers/gpu/drm/i915/gt/intel_ringbuffer.c| 6 +- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 14 +- drivers/gpu/drm/i915/i915_drv.c | 8 + drivers/gpu/drm/i915/i915_drv.h | 13 + drivers/gpu/drm/i915/i915_gem.c | 9 - drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 117 +++- drivers/gpu/drm/i915/i915_gem_gtt.h | 5 + drivers/gpu/drm/i915/i915_gpu_error.c | 66 +- drivers/gpu/drm/i915/i915_pci.c | 29 +- drivers/gpu/drm/i915/intel_device_info.h | 2 + drivers/gpu/drm/i915/intel_memory_region.c| 212 ++ drivers/gpu/drm/i915/intel_memory_region.h| 125 drivers/gpu/drm/i915/intel_region_lmem.c | 157 + drivers/gpu/drm/i915/intel_region_lmem.h | 16 + drivers/gpu/drm/i915/selftests/i915_gem.c | 4 + drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 8 +- .../drm/i915/selftests/i915_live_selftests.h | 1 + .../drm/i915/selftests/i915_mock_selftests.h | 1 + .../drm/i915/selftests/intel_memory_region.c | 602 ++ .../gpu/drm/i915/selftests/mock_gem_device.c | 9 +- drivers/gpu/drm/i915/selftests/mock_region.c | 59 ++ drivers/gpu/drm/i915/selftests/mock_region.h | 16 + include/drm/i915_drm.h| 3 + 47 files changed, 2186 insertions(+), 151 deletions(-) create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_lmem.c create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_lmem.h create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_region.c create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_region.h create mode 100644 drivers/gpu/drm/i915/intel_memory_region.c create mode 100644 drivers/gpu/drm/i915/intel_memory_region.h create mode 100644 drivers/gpu/drm/i915/intel_region_lmem.c create mode 100644 drivers/gpu/drm/i915/intel_region_lmem.h create mode 100644 drivers/gpu/drm/i915/selftests/intel_memory_region.c create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.c create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.h -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org
[Intel-gfx] [PATCH v3 19/21] drm/i915: don't allocate the ring in stolen if we lack aperture
Since we have no way access it from the CPU. For such cases just fallback to internal objects. Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c index 311fdc0a21bc..9ed6f52d178f 100644 --- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c @@ -1273,7 +1273,9 @@ static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size) struct drm_i915_gem_object *obj; struct i915_vma *vma; - obj = i915_gem_object_create_stolen(i915, size); + obj = ERR_PTR(-ENODEV); + if (i915_ggtt_has_aperture(ggtt)) + obj = i915_gem_object_create_stolen(i915, size); if (IS_ERR(obj)) obj = i915_gem_object_create_internal(i915, size); if (IS_ERR(obj)) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 01/21] drm/i915/stolen: make the object creation interface consistent
From: CQ Tang
Our other backends return an actual error value upon failure. Do the
same for stolen objects, which currently just return NULL on failure.
Signed-off-by: CQ Tang
Signed-off-by: Matthew Auld
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_fbdev.c | 4 +--
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 36 +++-
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 8 ++---
drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 2 +-
7 files changed, 30 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 5acc39f32d0c..c15975a410bc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3066,7 +3066,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
base_aligned,
base_aligned,
size_aligned);
- if (!obj)
+ if (IS_ERR(obj))
return false;
switch (plane_config->tiling) {
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 97cde017670a..3d1061470e76 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -141,10 +141,10 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
/* If the FB is too big, just don't use it since fbdev is not very
* important and we should probably use that space with FBC or other
* features. */
- obj = NULL;
+ obj = ERR_PTR(-ENODEV);
if (size * 2 < dev_priv->stolen_usable_size)
obj = i915_gem_object_create_stolen(dev_priv, size);
- if (obj == NULL)
+ if (IS_ERR(obj))
obj = i915_gem_object_create_shmem(dev_priv, size);
if (IS_ERR(obj)) {
DRM_ERROR("failed to allocate framebuffer\n");
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c
b/drivers/gpu/drm/i915/display/intel_overlay.c
index daea112cbb87..2360f19f9694 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -1291,7 +1291,7 @@ static int get_registers(struct intel_overlay *overlay,
bool use_phys)
int err;
obj = i915_gem_object_create_stolen(i915, PAGE_SIZE);
- if (obj == NULL)
+ if (IS_ERR(obj))
obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
if (IS_ERR(obj))
return PTR_ERR(obj);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index fad98a921cde..2a34355b738f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -585,28 +585,32 @@ i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
int ret;
if (!drm_mm_initialized(_priv->mm.stolen))
- return NULL;
+ return ERR_PTR(-ENODEV);
if (size == 0)
- return NULL;
+ return ERR_PTR(-EINVAL);
stolen = kzalloc(sizeof(*stolen), GFP_KERNEL);
if (!stolen)
- return NULL;
+ return ERR_PTR(-ENOMEM);
ret = i915_gem_stolen_insert_node(dev_priv, stolen, size, 4096);
- if (ret) {
- kfree(stolen);
- return NULL;
- }
+ if (ret)
+ goto err_free;
obj = _i915_gem_object_create_stolen(dev_priv, stolen);
- if (obj)
- return obj;
+ if (obj == NULL) {
+ ret = -ENOMEM;
+ goto err_remove;
+ }
+ return obj;
+
+err_remove:
i915_gem_stolen_remove_node(dev_priv, stolen);
+err_free:
kfree(stolen);
- return NULL;
+ return ERR_PTR(ret);
}
struct drm_i915_gem_object *
@@ -622,7 +626,7 @@ i915_gem_object_create_stolen_for_preallocated(struct
drm_i915_private *dev_priv
int ret;
if (!drm_mm_initialized(_priv->mm.stolen))
- return NULL;
+ return ERR_PTR(-ENODEV);
DRM_DEBUG_DRIVER("creating preallocated stolen object:
stolen_offset=%pa, gtt_offset=%pa, size=%pa\n",
_offset, _offset, );
@@ -631,11 +635,11 @@ i915_gem_object_create_stolen_for_preallocated(struct
drm_i915_private *dev_priv
if (WARN_ON(size == 0) ||
WARN_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE)) ||
WARN_ON(!IS_ALIGNED(stolen_offset, I915_GTT_MIN_ALIGNMENT)))
- return NULL;
+ return ERR_PTR(-EINVAL);
stolen = kzalloc(sizeof(*stolen),
[Intel-gfx] [PATCH v3 11/21] drm/i915: enumerate and init each supported region
From: Abdiel Janulgue
Nothing to enumerate yet...
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 70 +--
.../gpu/drm/i915/selftests/mock_gem_device.c | 6 ++
3 files changed, 72 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ff8e21e585a3..0233265405b4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2351,6 +2351,9 @@ int __must_check i915_gem_evict_for_node(struct
i915_address_space *vm,
unsigned int flags);
int i915_gem_evict_vm(struct i915_address_space *vm);
+void i915_gem_cleanup_memory_regions(struct drm_i915_private *i915);
+int i915_gem_init_memory_regions(struct drm_i915_private *i915);
+
/* i915_gem_internal.c */
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7b15bb891970..450ec8779252 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2744,6 +2744,66 @@ int i915_init_ggtt(struct drm_i915_private *i915)
return 0;
}
+void i915_gem_cleanup_memory_regions(struct drm_i915_private *i915)
+{
+ int i;
+
+ i915_gem_cleanup_stolen(i915);
+
+ for (i = 0; i < ARRAY_SIZE(i915->mm.regions); i++) {
+ struct intel_memory_region *region = i915->mm.regions[i];
+
+ if (region)
+ intel_memory_region_put(region);
+ }
+}
+
+int i915_gem_init_memory_regions(struct drm_i915_private *i915)
+{
+ int err, i;
+
+ /*
+* Initialise stolen early so that we may reserve preallocated
+* objects for the BIOS to KMS transition.
+*/
+ /* XXX: stolen will become a region at some point */
+ err = i915_gem_init_stolen(i915);
+ if (err)
+ return err;
+
+ for (i = 0; i < ARRAY_SIZE(i915->mm.regions); i++) {
+ struct intel_memory_region *mem = NULL;
+ u32 type;
+
+ if (!HAS_REGION(i915, BIT(i)))
+ continue;
+
+ type = MEMORY_TYPE_FROM_REGION(intel_region_map[i]);
+ switch (type) {
+ default:
+ break;
+ }
+
+ if (IS_ERR(mem)) {
+ err = PTR_ERR(mem);
+ DRM_ERROR("Failed to setup region(%d) type=%d\n", err,
type);
+ goto out_cleanup;
+ }
+
+ mem->id = intel_region_map[i];
+ mem->type = type;
+ mem->instance =
MEMORY_INSTANCE_FROM_REGION(intel_region_map[i]);
+
+ i915->mm.regions[i] = mem;
+ }
+
+ return 0;
+
+out_cleanup:
+ i915_gem_cleanup_memory_regions(i915);
+ return err;
+}
+
static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
{
struct i915_vma *vma, *vn;
@@ -2781,6 +2841,8 @@ void i915_ggtt_driver_release(struct drm_i915_private
*i915)
{
struct pagevec *pvec;
+ i915_gem_cleanup_memory_regions(i915);
+
fini_aliasing_ppgtt(>ggtt);
ggtt_cleanup_hw(>ggtt);
@@ -2790,8 +2852,6 @@ void i915_ggtt_driver_release(struct drm_i915_private
*i915)
set_pages_array_wb(pvec->pages, pvec->nr);
__pagevec_release(pvec);
}
-
- i915_gem_cleanup_stolen(i915);
}
static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
@@ -3240,11 +3300,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
if (ret)
return ret;
- /*
-* Initialise stolen early so that we may reserve preallocated
-* objects for the BIOS to KMS transition.
-*/
- ret = i915_gem_init_stolen(dev_priv);
+ ret = i915_gem_init_memory_regions(dev_priv);
if (ret)
goto out_gtt_cleanup;
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 8264d38fa690..6d47f0aeac0c 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -74,6 +74,8 @@ static void mock_device_release(struct drm_device *dev)
i915_gemfs_fini(i915);
+ i915_gem_cleanup_memory_regions(i915);
+
drm_mode_config_cleanup(>drm);
drm_dev_fini(>drm);
@@ -196,6 +198,10 @@ struct drm_i915_private *mock_gem_device(void)
WARN_ON(i915_gemfs_init(i915));
+ err = i915_gem_init_memory_regions(i915);
+ if (err)
+ goto err_context;
+
return i915;
err_context:
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
[Intel-gfx] [PATCH v3 03/21] drm/i915/region: support contiguous allocations
Some kernel internal objects may need to be allocated as a contiguous
block, also thinking ahead the various kernel io_mapping interfaces seem
to expect it, although this is purely a limitation in the kernel
API...so perhaps something to be improved.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
Cc: Michael J Ruhl
---
drivers/gpu/drm/i915/gem/i915_gem_object.h| 6 +
.../gpu/drm/i915/gem/i915_gem_object_types.h | 4 +
drivers/gpu/drm/i915/gem/i915_gem_region.c| 15 +-
drivers/gpu/drm/i915/gem/i915_gem_region.h| 3 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 71
drivers/gpu/drm/i915/intel_memory_region.c| 9 +-
drivers/gpu/drm/i915/intel_memory_region.h| 3 +-
.../drm/i915/selftests/intel_memory_region.c | 165 ++
drivers/gpu/drm/i915/selftests/mock_region.c | 2 +-
9 files changed, 239 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 086a9bf5adcc..dfd16d65630f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -139,6 +139,12 @@ i915_gem_object_is_readonly(const struct
drm_i915_gem_object *obj)
return obj->base.vma_node.readonly;
}
+static inline bool
+i915_gem_object_is_contiguous(const struct drm_i915_gem_object *obj)
+{
+ return obj->flags & I915_BO_ALLOC_CONTIGUOUS;
+}
+
static inline bool
i915_gem_object_type_has(const struct drm_i915_gem_object *obj,
unsigned long flags)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 11390586cfe1..c6a712cf7d7a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -119,6 +119,10 @@ struct drm_i915_gem_object {
I915_SELFTEST_DECLARE(struct list_head st_link);
+ unsigned long flags;
+#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
+#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS)
+
/*
* Is the object to be mapped as read-only to the GPU
* Only honoured if hardware has relevant pte bit
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index 5fc6e4540f82..04cb9f72945e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -23,10 +23,10 @@ i915_gem_object_get_pages_buddy(struct drm_i915_gem_object
*obj)
{
struct intel_memory_region *mem = obj->mm.region;
struct list_head *blocks = >mm.blocks;
- unsigned int flags = I915_ALLOC_MIN_PAGE_SIZE;
resource_size_t size = obj->base.size;
resource_size_t prev_end;
struct i915_buddy_block *block;
+ unsigned int flags;
struct sg_table *st;
struct scatterlist *sg;
unsigned int sg_page_sizes;
@@ -42,6 +42,10 @@ i915_gem_object_get_pages_buddy(struct drm_i915_gem_object
*obj)
return -ENOMEM;
}
+ flags = I915_ALLOC_MIN_PAGE_SIZE;
+ if (obj->flags & I915_BO_ALLOC_CONTIGUOUS)
+ flags |= I915_ALLOC_CONTIGUOUS;
+
ret = __intel_memory_region_get_pages_buddy(mem, size, flags, blocks);
if (ret)
goto err_free_sg;
@@ -56,7 +60,8 @@ i915_gem_object_get_pages_buddy(struct drm_i915_gem_object
*obj)
list_for_each_entry(block, blocks, link) {
u64 block_size, offset;
- block_size = i915_buddy_block_size(>mm, block);
+ block_size = min_t(u64, size,
+ i915_buddy_block_size(>mm, block));
offset = i915_buddy_block_offset(block);
GEM_BUG_ON(overflows_type(block_size, sg->length));
@@ -98,10 +103,12 @@ i915_gem_object_get_pages_buddy(struct drm_i915_gem_object
*obj)
}
void i915_gem_object_init_memory_region(struct drm_i915_gem_object *obj,
- struct intel_memory_region *mem)
+ struct intel_memory_region *mem,
+ unsigned long flags)
{
INIT_LIST_HEAD(>mm.blocks);
obj->mm.region = intel_memory_region_get(mem);
+ obj->flags = flags;
}
void i915_gem_object_release_memory_region(struct drm_i915_gem_object *obj)
@@ -116,6 +123,8 @@ i915_gem_object_create_region(struct intel_memory_region
*mem,
{
struct drm_i915_gem_object *obj;
+ GEM_BUG_ON(flags & ~I915_BO_ALLOC_FLAGS);
+
if (!mem)
return ERR_PTR(-ENODEV);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.h
b/drivers/gpu/drm/i915/gem/i915_gem_region.h
index ebddc86d78f7..f2ff6f8bff74 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.h
@@ -17,7 +17,8 @@ void i915_gem_object_put_pages_buddy(struct
drm_i915_gem_object *obj,
[Intel-gfx] [PATCH v3 06/21] drm/i915: support creating LMEM objects
We currently define LMEM, or local memory, as just another memory
region, like system memory or stolen, which we can expose to userspace
and can be mapped to the CPU via some BAR.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/Makefile | 2 +
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 29 +
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 23 ++
drivers/gpu/drm/i915/i915_drv.h | 5 +++
drivers/gpu/drm/i915/intel_memory_region.c| 10 +
drivers/gpu/drm/i915/intel_memory_region.h| 30 +
drivers/gpu/drm/i915/intel_region_lmem.c | 43 +++
drivers/gpu/drm/i915/intel_region_lmem.h | 11 +
.../drm/i915/selftests/i915_live_selftests.h | 1 +
.../drm/i915/selftests/intel_memory_region.c | 40 +
10 files changed, 194 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_lmem.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_lmem.h
create mode 100644 drivers/gpu/drm/i915/intel_region_lmem.c
create mode 100644 drivers/gpu/drm/i915/intel_region_lmem.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 6f0817bcc688..3154874e32b0 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -117,6 +117,7 @@ gem-y += \
gem/i915_gem_internal.o \
gem/i915_gem_object.o \
gem/i915_gem_object_blt.o \
+ gem/i915_gem_lmem.o \
gem/i915_gem_mman.o \
gem/i915_gem_pages.o \
gem/i915_gem_phys.o \
@@ -145,6 +146,7 @@ i915-y += \
i915_scheduler.o \
i915_trace_points.o \
i915_vma.o \
+ intel_region_lmem.o \
intel_wopcm.o
# general-purpose microcontroller (GuC) support
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
new file mode 100644
index ..aadd5d5a69da
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "intel_memory_region.h"
+#include "gem/i915_gem_region.h"
+#include "gem/i915_gem_lmem.h"
+#include "i915_drv.h"
+
+const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
+ .get_pages = i915_gem_object_get_pages_buddy,
+ .put_pages = i915_gem_object_put_pages_buddy,
+ .release = i915_gem_object_release_memory_region,
+};
+
+bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
+{
+ return obj->ops == _gem_lmem_obj_ops;
+}
+
+struct drm_i915_gem_object *
+i915_gem_object_create_lmem(struct drm_i915_private *i915,
+ resource_size_t size,
+ unsigned int flags)
+{
+ return
i915_gem_object_create_region(i915->mm.regions[INTEL_MEMORY_LMEM],
+size, flags);
+}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
new file mode 100644
index ..ebc15fe24f58
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef __I915_GEM_LMEM_H
+#define __I915_GEM_LMEM_H
+
+#include
+
+struct drm_i915_private;
+struct drm_i915_gem_object;
+
+extern const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops;
+
+bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
+
+struct drm_i915_gem_object *
+i915_gem_object_create_lmem(struct drm_i915_private *i915,
+ resource_size_t size,
+ unsigned int flags);
+
+#endif /* !__I915_GEM_LMEM_H */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b7be46faef2d..ff8e21e585a3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -100,6 +100,8 @@
#include "i915_vma.h"
#include "i915_irq.h"
+#include "intel_region_lmem.h"
+
#include "intel_gvt.h"
/* General customization:
@@ -679,6 +681,8 @@ struct i915_gem_mm {
*/
struct vfsmount *gemfs;
+ struct intel_memory_region *regions[INTEL_MEMORY_UNKNOWN];
+
struct notifier_block oom_notifier;
struct notifier_block vmap_notifier;
struct shrinker shrinker;
@@ -2130,6 +2134,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
+#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
#define HAS_GT_UC(dev_priv)(INTEL_INFO(dev_priv)->has_gt_uc)
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c
b/drivers/gpu/drm/i915/intel_memory_region.c
index fe808899cbf8..920f9590f410 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -6,6 +6,16 @@
#include
[Intel-gfx] [PATCH v3 16/21] drm/i915: set num_fence_regs to 0 if there is no aperture
From: Daniele Ceraolo Spurio We can't fence anything without aperture. Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Stuart Summers Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c index 487b7261f7ed..911aab45fce3 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c @@ -831,8 +831,10 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt) detect_bit_6_swizzle(i915); - if (INTEL_GEN(i915) >= 7 && - !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) + if (!i915_ggtt_has_aperture(ggtt)) + num_fences = 0; + else if (INTEL_GEN(i915) >= 7 && +!(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) num_fences = 32; else if (INTEL_GEN(i915) >= 4 || IS_I945G(i915) || IS_I945GM(i915) || -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 08/21] drm/i915/lmem: support kernel mapping
From: Abdiel Janulgue
We can create LMEM objects, but we also need to support mapping them
into kernel space for internal use.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Signed-off-by: Steve Hampson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 36 ++
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 8 ++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 9 +-
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 22 +++-
.../drm/i915/selftests/intel_memory_region.c | 115 ++
5 files changed, 182 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index aadd5d5a69da..fd8b63dd154d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -9,11 +9,47 @@
#include "i915_drv.h"
const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
+ .flags = I915_GEM_OBJECT_HAS_IOMEM,
+
.get_pages = i915_gem_object_get_pages_buddy,
.put_pages = i915_gem_object_put_pages_buddy,
.release = i915_gem_object_release_memory_region,
};
+/* XXX: Time to vfunc your life up? */
+void __iomem *i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj,
+ unsigned long n)
+{
+ resource_size_t offset;
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return io_mapping_map_wc(>mm.region->iomap, offset, PAGE_SIZE);
+}
+
+void __iomem *i915_gem_object_lmem_io_map_page_atomic(struct
drm_i915_gem_object *obj,
+ unsigned long n)
+{
+ resource_size_t offset;
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return io_mapping_map_atomic_wc(>mm.region->iomap, offset);
+}
+
+void __iomem *i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
+ unsigned long n,
+ unsigned long size)
+{
+ resource_size_t offset;
+
+ GEM_BUG_ON(!i915_gem_object_is_contiguous(obj));
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return io_mapping_map_wc(>mm.region->iomap, offset, size);
+}
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
{
return obj->ops == _gem_lmem_obj_ops;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
index ebc15fe24f58..31a6462bdbb6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -13,6 +13,14 @@ struct drm_i915_gem_object;
extern const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops;
+void __iomem *i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
+ unsigned long n, unsigned long size);
+void __iomem *i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj,
+ unsigned long n);
+void __iomem *
+i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj,
+ unsigned long n);
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index a387e3ee728b..96008374a412 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -31,10 +31,11 @@ struct i915_lut_handle {
struct drm_i915_gem_object_ops {
unsigned int flags;
#define I915_GEM_OBJECT_HAS_STRUCT_PAGEBIT(0)
-#define I915_GEM_OBJECT_IS_SHRINKABLE BIT(1)
-#define I915_GEM_OBJECT_IS_PROXY BIT(2)
-#define I915_GEM_OBJECT_NO_GGTTBIT(3)
-#define I915_GEM_OBJECT_ASYNC_CANCEL BIT(4)
+#define I915_GEM_OBJECT_HAS_IOMEM BIT(1)
+#define I915_GEM_OBJECT_IS_SHRINKABLE BIT(2)
+#define I915_GEM_OBJECT_IS_PROXY BIT(3)
+#define I915_GEM_OBJECT_NO_GGTTBIT(4)
+#define I915_GEM_OBJECT_ASYNC_CANCEL BIT(5)
/* Interface between the GEM object and its backing storage.
* get_pages() is called once prior to the use of the associated set
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index b0ec0959c13f..cf7f5a3cb210 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -7,6 +7,7 @@
#include "i915_drv.h"
#include "i915_gem_object.h"
#include "i915_scatterlist.h"
+#include "i915_gem_lmem.h"
void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
struct sg_table *pages,
@@ -172,7 +173,9 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object
*obj)
void *ptr;
ptr = page_mask_bits(obj->mm.mapping);
- if (is_vmalloc_addr(ptr))
+
[Intel-gfx] [PATCH v3 02/21] drm/i915: introduce intel_memory_region
Support memory regions, as defined by a given (start, end), and allow
creating GEM objects which are backed by said region. The immediate goal
here is to have something to represent our device memory, but later on
we also want to represent every memory domain with a region, so stolen,
shmem, and of course device. At some point we are probably going to want
use a common struct here, such that we are better aligned with say TTM.
Signed-off-by: Matthew Auld
Signed-off-by: Abdiel Janulgue
Signed-off-by: Niranjana Vishwanathapura
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/Makefile | 2 +
.../gpu/drm/i915/gem/i915_gem_object_types.h | 9 +
drivers/gpu/drm/i915/gem/i915_gem_region.c| 134
drivers/gpu/drm/i915/gem/i915_gem_region.h| 28 +++
.../gpu/drm/i915/gem/selftests/huge_pages.c | 78 +++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_memory_region.c| 191 ++
drivers/gpu/drm/i915/intel_memory_region.h| 83
.../drm/i915/selftests/i915_mock_selftests.h | 1 +
.../drm/i915/selftests/intel_memory_region.c | 115 +++
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
drivers/gpu/drm/i915/selftests/mock_region.c | 59 ++
drivers/gpu/drm/i915/selftests/mock_region.h | 16 ++
13 files changed, 718 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_region.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_region.h
create mode 100644 drivers/gpu/drm/i915/intel_memory_region.c
create mode 100644 drivers/gpu/drm/i915/intel_memory_region.h
create mode 100644 drivers/gpu/drm/i915/selftests/intel_memory_region.c
create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.c
create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 06e1876d0250..6f0817bcc688 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -50,6 +50,7 @@ i915-y += i915_drv.o \
i915_utils.o \
intel_csr.o \
intel_device_info.o \
+ intel_memory_region.o \
intel_pch.o \
intel_pm.o \
intel_runtime_pm.o \
@@ -120,6 +121,7 @@ gem-y += \
gem/i915_gem_pages.o \
gem/i915_gem_phys.o \
gem/i915_gem_pm.o \
+ gem/i915_gem_region.o \
gem/i915_gem_shmem.o \
gem/i915_gem_shrinker.o \
gem/i915_gem_stolen.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index c00b4f077f9e..11390586cfe1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -160,6 +160,15 @@ struct drm_i915_gem_object {
atomic_t pages_pin_count;
atomic_t shrink_pin;
+ /**
+* Memory region for this object.
+*/
+ struct intel_memory_region *region;
+ /**
+* List of memory region blocks allocated for this object.
+*/
+ struct list_head blocks;
+
struct sg_table *pages;
void *mapping;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
new file mode 100644
index ..5fc6e4540f82
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "intel_memory_region.h"
+#include "i915_gem_region.h"
+#include "i915_drv.h"
+
+void
+i915_gem_object_put_pages_buddy(struct drm_i915_gem_object *obj,
+ struct sg_table *pages)
+{
+ __intel_memory_region_put_pages_buddy(obj->mm.region, >mm.blocks);
+
+ obj->mm.dirty = false;
+ sg_free_table(pages);
+ kfree(pages);
+}
+
+int
+i915_gem_object_get_pages_buddy(struct drm_i915_gem_object *obj)
+{
+ struct intel_memory_region *mem = obj->mm.region;
+ struct list_head *blocks = >mm.blocks;
+ unsigned int flags = I915_ALLOC_MIN_PAGE_SIZE;
+ resource_size_t size = obj->base.size;
+ resource_size_t prev_end;
+ struct i915_buddy_block *block;
+ struct sg_table *st;
+ struct scatterlist *sg;
+ unsigned int sg_page_sizes;
+ unsigned long i;
+ int ret;
+
+ st = kmalloc(sizeof(*st), GFP_KERNEL);
+ if (!st)
+ return -ENOMEM;
+
+ if (sg_alloc_table(st, size >> ilog2(mem->mm.chunk_size), GFP_KERNEL)) {
+ kfree(st);
+ return -ENOMEM;
+ }
+
+ ret = __intel_memory_region_get_pages_buddy(mem, size, flags, blocks);
+ if (ret)
+ goto err_free_sg;
+
+ GEM_BUG_ON(list_empty(blocks));
+
+ sg = st->sgl;
+ st->nents = 0;
+ sg_page_sizes = 0;
+ i = 0;
+
+
[Intel-gfx] [PATCH v3 20/21] drm/i915/selftests: check for missing aperture
We may be missing support for the mappable aperture on some platforms.
Signed-off-by: Matthew Auld
Cc: Daniele Ceraolo Spurio
---
.../drm/i915/gem/selftests/i915_gem_coherency.c| 5 -
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 6 ++
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 14 ++
drivers/gpu/drm/i915/selftests/i915_gem.c | 4
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 3 +++
5 files changed, 27 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
index 549810f70aeb..e82255526782 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
@@ -259,7 +259,10 @@ static bool always_valid(struct drm_i915_private *i915)
static bool needs_fence_registers(struct drm_i915_private *i915)
{
- return !intel_gt_is_wedged(>gt);
+ if (intel_gt_is_wedged(>gt))
+ return false;
+
+ return i915->ggtt.num_fences;
}
static bool needs_mi_store_dword(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index cfa52c525691..468603fa6218 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -301,6 +301,9 @@ static int igt_partial_tiling(void *arg)
int tiling;
int err;
+ if (!i915_ggtt_has_aperture(>ggtt))
+ return 0;
+
/* We want to check the page mapping and fencing of a large object
* mmapped through the GTT. The object we create is larger than can
* possibly be mmaped as a whole, and so we must use partial GGTT vma.
@@ -431,6 +434,9 @@ static int igt_smoke_tiling(void *arg)
IGT_TIMEOUT(end);
int err;
+ if (!i915_ggtt_has_aperture(>ggtt))
+ return 0;
+
/*
* igt_partial_tiling() does an exhastive check of partial tiling
* chunking, but will undoubtably run out of time. Here, we do a
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index e8a40df79bd0..c7896d4bf7ae 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -1149,8 +1149,12 @@ static int __igt_reset_evict_vma(struct intel_gt *gt,
struct i915_request *rq;
struct evict_vma arg;
struct hang h;
+ unsigned int pin_flags;
int err;
+ if (!gt->ggtt->num_fences && flags & EXEC_OBJECT_NEEDS_FENCE)
+ return 0;
+
if (!engine || !intel_engine_can_store_dword(engine))
return 0;
@@ -1186,10 +1190,12 @@ static int __igt_reset_evict_vma(struct intel_gt *gt,
goto out_obj;
}
- err = i915_vma_pin(arg.vma, 0, 0,
- i915_vma_is_ggtt(arg.vma) ?
- PIN_GLOBAL | PIN_MAPPABLE :
- PIN_USER);
+ pin_flags = i915_vma_is_ggtt(arg.vma) ? PIN_GLOBAL : PIN_USER;
+
+ if (flags & EXEC_OBJECT_NEEDS_FENCE)
+ pin_flags |= PIN_MAPPABLE;
+
+ err = i915_vma_pin(arg.vma, 0, 0, pin_flags);
if (err) {
i915_request_add(rq);
goto out_obj;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c
b/drivers/gpu/drm/i915/selftests/i915_gem.c
index bfa40a5b6d98..6f80a92c967b 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem.c
@@ -42,6 +42,10 @@ static void trash_stolen(struct drm_i915_private *i915)
unsigned long page;
u32 prng = 0x12345678;
+ /* XXX: fsck. needs some more thought... */
+ if (!i915_ggtt_has_aperture(ggtt))
+ return;
+
for (page = 0; page < size; page += PAGE_SIZE) {
const dma_addr_t dma = i915->dsm.start + page;
u32 __iomem *s;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index ebe735df6504..4037e2cdca43 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1148,6 +1148,9 @@ static int igt_ggtt_page(void *arg)
unsigned int *order, n;
int err;
+ if (!i915_ggtt_has_aperture(ggtt))
+ return 0;
+
obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
if (IS_ERR(obj))
return PTR_ERR(obj);
--
2.20.1
___
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Intel-gfx@lists.freedesktop.org
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[Intel-gfx] [PATCH v3 09/21] drm/i915/selftests: add write-dword test for LMEM
Simple test writing to dwords across an object, using various engines in
a randomized order, checking that our writes land from the cpu.
Signed-off-by: Matthew Auld
---
.../drm/i915/selftests/intel_memory_region.c | 167 ++
1 file changed, 167 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index 48244d885521..76c0ab0aa78c 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -7,13 +7,16 @@
#include "../i915_selftest.h"
+
#include "mock_drm.h"
#include "mock_gem_device.h"
#include "mock_region.h"
+#include "gem/i915_gem_context.h"
#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_region.h"
#include "gem/i915_gem_object_blt.h"
+#include "gem/selftests/igt_gem_utils.h"
#include "gem/selftests/mock_context.h"
#include "gt/intel_gt.h"
#include "selftests/igt_flush_test.h"
@@ -254,6 +257,125 @@ static int igt_mock_contiguous(void *arg)
return err;
}
+static int igt_gpu_write_dw(struct intel_context *ce,
+ struct i915_vma *vma,
+ u32 dword,
+ u32 value)
+{
+ return igt_gpu_fill_dw(ce, vma, dword * sizeof(u32),
+ vma->size >> PAGE_SHIFT, value);
+}
+
+static int igt_cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+{
+ unsigned long n;
+ int err;
+
+ i915_gem_object_lock(obj);
+ err = i915_gem_object_set_to_wc_domain(obj, false);
+ i915_gem_object_unlock(obj);
+ if (err)
+ return err;
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ return err;
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) {
+ u32 __iomem *base;
+ u32 read_val;
+
+ base = i915_gem_object_lmem_io_map_page_atomic(obj, n);
+
+ read_val = ioread32(base + dword);
+ io_mapping_unmap_atomic(base);
+ if (read_val != val) {
+ pr_err("n=%lu base[%u]=%u, val=%u\n",
+ n, dword, read_val, val);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ return err;
+}
+
+static int igt_gpu_write(struct i915_gem_context *ctx,
+struct drm_i915_gem_object *obj)
+{
+ struct drm_i915_private *i915 = ctx->i915;
+ struct i915_address_space *vm = ctx->vm ?: >ggtt.vm;
+ struct i915_gem_engines *engines;
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+ I915_RND_STATE(prng);
+ IGT_TIMEOUT(end_time);
+ unsigned int count;
+ struct i915_vma *vma;
+ int *order;
+ int i, n;
+ int err = 0;
+
+ GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
+
+ n = 0;
+ count = 0;
+ for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
+ count++;
+ if (!intel_engine_can_store_dword(ce->engine))
+ continue;
+
+ n++;
+ }
+ i915_gem_context_unlock_engines(ctx);
+ if (!n)
+ return 0;
+
+ order = i915_random_order(count * count, );
+ if (!order)
+ return -ENOMEM;
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out_free;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto out_free;
+
+ i = 0;
+ engines = i915_gem_context_lock_engines(ctx);
+ do {
+ u32 rng = prandom_u32_state();
+ u32 dword = offset_in_page(rng) / 4;
+
+ ce = engines->engines[order[i] % engines->num_engines];
+ i = (i + 1) % (count * count);
+ if (!ce || !intel_engine_can_store_dword(ce->engine))
+ continue;
+
+ err = igt_gpu_write_dw(ce, vma, dword, rng);
+ if (err)
+ break;
+
+ err = igt_cpu_check(obj, dword, rng);
+ if (err)
+ break;
+ } while (!__igt_timeout(end_time, NULL));
+ i915_gem_context_unlock_engines(ctx);
+
+out_free:
+ kfree(order);
+
+ if (err == -ENOMEM)
+ err = 0;
+
+ return err;
+}
+
static int igt_lmem_create(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -275,6 +397,50 @@ static int igt_lmem_create(void *arg)
return err;
}
+static int igt_lmem_write_gpu(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem_object *obj;
+ struct i915_gem_context *ctx;
+ struct drm_file *file;
+ I915_RND_STATE(prng);
+ u32 sz;
+ int err;
+
+
[Intel-gfx] [PATCH v3 10/21] drm/i915/selftests: extend coverage to include LMEM huge-pages
Signed-off-by: Matthew Auld
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 121 +-
1 file changed, 120 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index f27772f6779a..d4892769b739 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -9,6 +9,7 @@
#include "i915_selftest.h"
#include "gem/i915_gem_region.h"
+#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_pm.h"
#include "gt/intel_gt.h"
@@ -981,7 +982,7 @@ static int gpu_write(struct intel_context *ce,
vma->size >> PAGE_SHIFT, val);
}
-static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+static int __cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32
val)
{
unsigned int needs_flush;
unsigned long n;
@@ -1013,6 +1014,51 @@ static int cpu_check(struct drm_i915_gem_object *obj,
u32 dword, u32 val)
return err;
}
+static int __cpu_check_lmem(struct drm_i915_gem_object *obj, u32 dword, u32
val)
+{
+ unsigned long n;
+ int err;
+
+ i915_gem_object_lock(obj);
+ err = i915_gem_object_set_to_wc_domain(obj, false);
+ i915_gem_object_unlock(obj);
+ if (err)
+ return err;
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ return err;
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) {
+ u32 __iomem *base;
+ u32 read_val;
+
+ base = i915_gem_object_lmem_io_map_page_atomic(obj, n);
+
+ read_val = ioread32(base + dword);
+ io_mapping_unmap_atomic(base);
+ if (read_val != val) {
+ pr_err("n=%lu base[%u]=%u, val=%u\n",
+ n, dword, read_val, val);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ return err;
+}
+
+static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+{
+ if (i915_gem_object_has_struct_page(obj))
+ return __cpu_check_shmem(obj, dword, val);
+ else if (i915_gem_object_is_lmem(obj))
+ return __cpu_check_lmem(obj, dword, val);
+
+ return -ENODEV;
+}
+
static int __igt_write_huge(struct intel_context *ce,
struct drm_i915_gem_object *obj,
u64 size, u64 offset,
@@ -1397,6 +1443,78 @@ static int igt_ppgtt_gemfs_huge(void *arg)
return err;
}
+static int igt_ppgtt_lmem_huge(void *arg)
+{
+ struct i915_gem_context *ctx = arg;
+ struct drm_i915_private *i915 = ctx->i915;
+ struct drm_i915_gem_object *obj;
+ static const unsigned int sizes[] = {
+ SZ_64K,
+ SZ_512K,
+ SZ_1M,
+ SZ_2M,
+ };
+ int i;
+ int err;
+
+ if (!HAS_LMEM(i915)) {
+ pr_info("device lacks LMEM support, skipping\n");
+ return 0;
+ }
+
+ /*
+* Sanity check that the HW uses huge pages correctly through LMEM
+* -- ensure that our writes land in the right place.
+*/
+
+ for (i = 0; i < ARRAY_SIZE(sizes); ++i) {
+ unsigned int size = sizes[i];
+
+ obj = i915_gem_object_create_lmem(i915, size,
I915_BO_ALLOC_CONTIGUOUS);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ if (err == -E2BIG) {
+ pr_info("object too big for region!\n");
+ return 0;
+ }
+
+ return err;
+ }
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ goto out_put;
+
+ if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_64K) {
+ pr_info("LMEM unable to allocate huge-page(s) with
size=%u\n",
+ size);
+ goto out_unpin;
+ }
+
+ err = igt_write_huge(ctx, obj);
+ if (err) {
+ pr_err("LMEM write-huge failed with size=%u\n", size);
+ goto out_unpin;
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
+ i915_gem_object_put(obj);
+ }
+
+ return 0;
+
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+out_put:
+ i915_gem_object_put(obj);
+
+ if (err == -ENOMEM)
+ err = 0;
+
+ return err;
+}
+
static int igt_ppgtt_pin_update(void *arg)
{
struct i915_gem_context *ctx = arg;
@@ -1758,6 +1876,7 @@ int i915_gem_huge_page_live_selftests(struct
drm_i915_private *i915)
[Intel-gfx] [PATCH v3 05/21] drm/i915: Add memory region information to device_info
From: Abdiel Janulgue
Exposes available regions for the platform. Shared memory will
always be available.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dcbc6e6394fc..b7be46faef2d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2129,6 +2129,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
+#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
+
#define HAS_GT_UC(dev_priv)(INTEL_INFO(dev_priv)->has_gt_uc)
/* Having GuC is not the same as using GuC */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 0cdc2465534b..e9940f932d26 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -160,6 +160,8 @@ struct intel_device_info {
unsigned int page_sizes; /* page sizes supported by the HW */
+ u32 memory_regions; /* regions supported by the HW */
+
u32 display_mmio_offset;
u8 pipe_mask;
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 07/21] drm/i915: setup io-mapping for LMEM
From: Abdiel Janulgue
Signed-off-by: Abdiel Janulgue
Cc: Matthew Auld
---
drivers/gpu/drm/i915/intel_region_lmem.c | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
b/drivers/gpu/drm/i915/intel_region_lmem.c
index 7a3f96e1f766..051069664074 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -36,8 +36,32 @@ lmem_create_object(struct intel_memory_region *mem,
return obj;
}
+static void
+region_lmem_release(struct intel_memory_region *mem)
+{
+ io_mapping_fini(>iomap);
+ intel_memory_region_release_buddy(mem);
+}
+
+static int
+region_lmem_init(struct intel_memory_region *mem)
+{
+ int ret;
+
+ if (!io_mapping_init_wc(>iomap,
+ mem->io_start,
+ resource_size(>region)))
+ return -EIO;
+
+ ret = intel_memory_region_init_buddy(mem);
+ if (ret)
+ io_mapping_fini(>iomap);
+
+ return ret;
+}
+
const struct intel_memory_region_ops intel_region_lmem_ops = {
- .init = intel_memory_region_init_buddy,
- .release = intel_memory_region_release_buddy,
+ .init = region_lmem_init,
+ .release = region_lmem_release,
.create_object = lmem_create_object,
};
--
2.20.1
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/5] drm/i915/execlists: Skip redundant resubmission (rev2)
== Series Details ==
Series: series starting with [1/5] drm/i915/execlists: Skip redundant
resubmission (rev2)
URL : https://patchwork.freedesktop.org/series/67566/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7003_full -> Patchwork_14665_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14665_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14665_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14665_full:
### IGT changes ###
Possible regressions
* igt@gem_mmap_gtt@hang:
- shard-kbl: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-kbl1/igt@gem_mmap_...@hang.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14665/shard-kbl2/igt@gem_mmap_...@hang.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_mmap_gtt@hang:
- {shard-tglb}: NOTRUN -> [DMESG-WARN][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14665/shard-tglb6/igt@gem_mmap_...@hang.html
Known issues
Here are the changes found in Patchwork_14665_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#110854])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb2/igt@gem_exec_balan...@smoke.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14665/shard-iclb6/igt@gem_exec_balan...@smoke.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#109276]) +15 similar
issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb1/igt@gem_exec_sched...@preempt-queue-bsd1.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14665/shard-iclb7/igt@gem_exec_sched...@preempt-queue-bsd1.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#111325]) +7 similar
issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb5/igt@gem_exec_sched...@reorder-wide-bsd.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14665/shard-iclb1/igt@gem_exec_sched...@reorder-wide-bsd.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-snb: [PASS][10] -> [DMESG-WARN][11] ([fdo#111870])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-snb5/igt@gem_userptr_bl...@dmabuf-unsync.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14665/shard-snb1/igt@gem_userptr_bl...@dmabuf-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-apl: [PASS][12] -> [DMESG-WARN][13] ([fdo#109385] /
[fdo#111870]) +1 similar issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-apl4/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14665/shard-apl1/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-skl: [PASS][14] -> [DMESG-WARN][15] ([fdo#111870]) +1
similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-skl3/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14665/shard-skl10/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
- shard-iclb: [PASS][16] -> [DMESG-WARN][17] ([fdo#111870]) +1
similar issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb5/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14665/shard-iclb1/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
* igt@gem_userptr_blits@sync-unmap:
- shard-glk: [PASS][18] -> [DMESG-WARN][19] ([fdo#111870])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-glk1/igt@gem_userptr_bl...@sync-unmap.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14665/shard-glk6/igt@gem_userptr_bl...@sync-unmap.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][20] -> [DMESG-WARN][21] ([fdo#108566]) +2
similar issues
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-apl1/igt@gem_workarou...@suspend-resume-context.html
[21]:
Re: [Intel-gfx] [PATCH v10 1/6] drm/i915/tgl: Add DC3CO required register and bits
On 2019-10-04 at 18:48:08 +0300, Ville Syrjälä wrote:
> On Thu, Oct 03, 2019 at 01:47:33PM +0530, Anshuman Gupta wrote:
> > Adding following definition to i915_reg.h
> > 1. DC_STATE_EN register DC3CO bit fields and masks.
> >DC3CO enable bit will be used by driver to make DC3CO
> >ready for DMC f/w and status bit will be used as DC3CO
> >entry status.
> > 2. Transcoder EXITLINE register and its bit fields and mask.
> >Transcoder EXITLINE enable bit represents PSR2 idle frame
> >reset should be applied at exit line and exitlines mask
> >represent required number of scanlines at which DC3CO
> >exit happens.
> >
> >B.Specs:49196
> >
> > v1: Use of REG_BIT and using extra space for EXITLINE_ macro
> > definition. [Animesh]
> >
> > Cc: Jani Nikula
> > Cc: Imre Deak
> > Cc: Animesh Manna
> > Reviewed-by: Animesh Manna
> > Reviewed-by: Imre Deak
> > Signed-off-by: Anshuman Gupta
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 8
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index eefd789b9a28..8fd93008214b 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4144,6 +4144,7 @@ enum {
> > #define _VTOTAL_A 0x6000c
> > #define _VBLANK_A 0x60010
> > #define _VSYNC_A 0x60014
> > +#define _EXITLINE_A0x60018
> > #define _PIPEASRC 0x6001c
> > #define _BCLRPAT_A 0x60020
> > #define _VSYNCSHIFT_A 0x60028
> > @@ -4190,11 +4191,16 @@ enum {
> > #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
> > #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
> > #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
> > +#define EXITLINE(trans)_MMIO_TRANS2(trans, _EXITLINE_A)
> > #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
> > #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
> > #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
> > #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
> >
> > +#define EXITLINE_ENABLE REG_BIT(31)
> > +#define EXITLINE_MASKREG_GENMASK(12, 0)
> > +#define EXITLINE_SHIFT 0
>
> Why are these defines hanging mid-air?
If i understand your comment correctly, the place these EXITLINE
bit defines is not correct, and it should be moved after
EXITLINE(trans) define, am i correct ?
>
> > +
> > /*
> > * HSW+ eDP PSR registers
> > *
> > @@ -10288,6 +10294,8 @@ enum skl_power_gate {
> > /* GEN9 DC */
> > #define DC_STATE_EN_MMIO(0x45504)
> > #define DC_STATE_DISABLE 0
> > +#define DC_STATE_EN_DC3CO REG_BIT(30)
> > +#define DC_STATE_DC3CO_STATUS REG_BIT(29)
> > #define DC_STATE_EN_UPTO_DC5 (1 << 0)
> > #define DC_STATE_EN_DC9 (1 << 3)
> > #define DC_STATE_EN_UPTO_DC6 (2 << 0)
> > --
> > 2.21.0
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
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[Intel-gfx] ✗ Fi.CI.IGT: failure for TGL HAX drm/i915/tgl: Interrupts are overrated (rev7)
== Series Details == Series: TGL HAX drm/i915/tgl: Interrupts are overrated (rev7) URL : https://patchwork.freedesktop.org/series/67558/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7003_full -> Patchwork_14664_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14664_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14664_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14664_full: ### IGT changes ### Possible regressions * igt@gem_mmap_gtt@hang: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-kbl1/igt@gem_mmap_...@hang.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14664/shard-kbl7/igt@gem_mmap_...@hang.html * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic: - shard-iclb: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb3/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14664/shard-iclb4/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html Known issues Here are the changes found in Patchwork_14664_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110841]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb5/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14664/shard-iclb1/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#110854]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb2/igt@gem_exec_balan...@smoke.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14664/shard-iclb6/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@preempt-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#111325]) +7 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb5/igt@gem_exec_sched...@preempt-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14664/shard-iclb1/igt@gem_exec_sched...@preempt-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +19 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb1/igt@gem_exec_sched...@preempt-queue-bsd1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14664/shard-iclb6/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#104108]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-skl6/igt@gem_soft...@noreloc-s3.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14664/shard-skl10/igt@gem_soft...@noreloc-s3.html * igt@gem_userptr_blits@map-fixed-invalidate-busy: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([fdo#109385] / [fdo#111870]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-apl6/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14664/shard-apl6/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([fdo#111870]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-skl3/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14664/shard-skl3/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html - shard-iclb: [PASS][19] -> [DMESG-WARN][20] ([fdo#111870]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb5/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14664/shard-iclb1/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([fdo#108566]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-apl8/igt@kms_cursor_...@pipe-c-cursor-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14664/shard-apl8/igt@kms_cursor_...@pipe-c-cursor-suspend.html *
Re: [Intel-gfx] [PATCH 09/24] drm/i915: Handle a few more cases for crtc hw/uapi split
On Fri, Oct 04, 2019 at 05:51:16PM +0200, Maarten Lankhorst wrote:
> Op 04-10-2019 om 15:31 schreef Ville Syrjälä:
> > On Fri, Oct 04, 2019 at 01:34:59PM +0200, Maarten Lankhorst wrote:
> >> We are still looking at drm_crtc_state in a few places, convert those
> >> to use intel_crtc_state instead. Look at uapi/hw where appropriate.
> >>
> >> Signed-off-by: Maarten Lankhorst
> >> Reviewed-by: Matt Roper
> >> ---
> >> drivers/gpu/drm/i915/display/intel_display.c | 14 +++---
> >> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> >> drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
> >> 3 files changed, 10 insertions(+), 10 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> >> b/drivers/gpu/drm/i915/display/intel_display.c
> >> index f555ff6b1f6a..fcd295ed80ed 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >> @@ -16126,8 +16126,8 @@ static int intel_initial_commit(struct drm_device
> >> *dev)
> >> {
> >>struct drm_atomic_state *state = NULL;
> >>struct drm_modeset_acquire_ctx ctx;
> >> - struct drm_crtc *crtc;
> >> - struct drm_crtc_state *crtc_state;
> >> + struct intel_crtc *crtc;
> >> + struct intel_crtc_state *crtc_state;
> > I'd prefer to lift most of this patch to before we do that state split
> > so it can be pushed out of the way.
>
> If you apply
>
> https://lists.freedesktop.org/archives/intel-gfx/2019-September/214268.html
>
> and I put this before the hw split patch, do I get your r-b up to [PATCH
> 12/24] drm/i915: Split plane hw and uapi state ?
Haven't gotten that far yet.
--
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Re: [Intel-gfx] [PATCH 09/24] drm/i915: Handle a few more cases for crtc hw/uapi split
Op 04-10-2019 om 15:31 schreef Ville Syrjälä:
> On Fri, Oct 04, 2019 at 01:34:59PM +0200, Maarten Lankhorst wrote:
>> We are still looking at drm_crtc_state in a few places, convert those
>> to use intel_crtc_state instead. Look at uapi/hw where appropriate.
>>
>> Signed-off-by: Maarten Lankhorst
>> Reviewed-by: Matt Roper
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 14 +++---
>> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
>> drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
>> 3 files changed, 10 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index f555ff6b1f6a..fcd295ed80ed 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -16126,8 +16126,8 @@ static int intel_initial_commit(struct drm_device
>> *dev)
>> {
>> struct drm_atomic_state *state = NULL;
>> struct drm_modeset_acquire_ctx ctx;
>> -struct drm_crtc *crtc;
>> -struct drm_crtc_state *crtc_state;
>> +struct intel_crtc *crtc;
>> +struct intel_crtc_state *crtc_state;
> I'd prefer to lift most of this patch to before we do that state split
> so it can be pushed out of the way.
If you apply
https://lists.freedesktop.org/archives/intel-gfx/2019-September/214268.html
and I put this before the hw split patch, do I get your r-b up to [PATCH 12/24]
drm/i915: Split plane hw and uapi state ?
~Maarten
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Re: [Intel-gfx] [PATCH v10 1/6] drm/i915/tgl: Add DC3CO required register and bits
On Thu, Oct 03, 2019 at 01:47:33PM +0530, Anshuman Gupta wrote:
> Adding following definition to i915_reg.h
> 1. DC_STATE_EN register DC3CO bit fields and masks.
>DC3CO enable bit will be used by driver to make DC3CO
>ready for DMC f/w and status bit will be used as DC3CO
>entry status.
> 2. Transcoder EXITLINE register and its bit fields and mask.
>Transcoder EXITLINE enable bit represents PSR2 idle frame
>reset should be applied at exit line and exitlines mask
>represent required number of scanlines at which DC3CO
>exit happens.
>
>B.Specs:49196
>
> v1: Use of REG_BIT and using extra space for EXITLINE_ macro
> definition. [Animesh]
>
> Cc: Jani Nikula
> Cc: Imre Deak
> Cc: Animesh Manna
> Reviewed-by: Animesh Manna
> Reviewed-by: Imre Deak
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/i915_reg.h | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index eefd789b9a28..8fd93008214b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4144,6 +4144,7 @@ enum {
> #define _VTOTAL_A0x6000c
> #define _VBLANK_A0x60010
> #define _VSYNC_A 0x60014
> +#define _EXITLINE_A 0x60018
> #define _PIPEASRC0x6001c
> #define _BCLRPAT_A 0x60020
> #define _VSYNCSHIFT_A0x60028
> @@ -4190,11 +4191,16 @@ enum {
> #define VTOTAL(trans)_MMIO_TRANS2(trans, _VTOTAL_A)
> #define VBLANK(trans)_MMIO_TRANS2(trans, _VBLANK_A)
> #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
> +#define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A)
> #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
> #define VSYNCSHIFT(trans)_MMIO_TRANS2(trans, _VSYNCSHIFT_A)
> #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
> #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
>
> +#define EXITLINE_ENABLEREG_BIT(31)
> +#define EXITLINE_MASK REG_GENMASK(12, 0)
> +#define EXITLINE_SHIFT 0
Why are these defines hanging mid-air?
> +
> /*
> * HSW+ eDP PSR registers
> *
> @@ -10288,6 +10294,8 @@ enum skl_power_gate {
> /* GEN9 DC */
> #define DC_STATE_EN _MMIO(0x45504)
> #define DC_STATE_DISABLE0
> +#define DC_STATE_EN_DC3CO REG_BIT(30)
> +#define DC_STATE_DC3CO_STATUS REG_BIT(29)
> #define DC_STATE_EN_UPTO_DC5(1 << 0)
> #define DC_STATE_EN_DC9 (1 << 3)
> #define DC_STATE_EN_UPTO_DC6(2 << 0)
> --
> 2.21.0
>
> ___
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Re: [Intel-gfx] [PATCH v4 9/9] Gen-12 display can decompress surfaces compressed by the media engine.
On Thu, Sep 26, 2019 at 03:55:12AM -0700, Dhinakaran Pandiyan wrote:
> Detect the modifier corresponding to media compression to enable
> display decompression for YUV and xRGB packed formats. A new modifier is
> added so that the driver can distinguish between media and render
> compressed buffers. Unlike render decompression, plane 6 and plane 7 do not
> support media decompression.
>
> v2: Fix checkpatch warnings on code style (Lucas)
>
> From DK:
> Separate modifier array for planes that cannot decompress media (Ville)
>
> v3: Support planar formats
> v4: Switch plane order
>
> Cc: Nanley G Chery
> Cc: Ville Syrjälä
> Cc: Matt Roper
> Signed-off-by: Dhinakaran Pandiyan
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 290 +-
> .../drm/i915/display/intel_display_types.h| 2 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 55 +++-
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 4 files changed, 267 insertions(+), 81 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 8ea55d67442c..df3ebaa167ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1888,6 +1888,22 @@ static void intel_disable_pipe(const struct
> intel_crtc_state *old_crtc_state)
> intel_wait_for_pipe_off(old_crtc_state);
> }
>
> +bool is_ccs_modifier(u64 modifier)
> +{
> + return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> +modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> +modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> +modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> +}
> +
> +static bool is_ccs_plane(const struct drm_framebuffer *fb, int color_plane)
> +{
> + if (!is_ccs_modifier(fb->modifier))
> + return false;
A comment here could help clarify things for the reader. Eg.:
/*
* [0] RGB
* [1] RGB CCS
* or
* [0] Y
* [1] CbCr
* [2] Y CCS
* [3] CbCr CCS
*/
> +
> + return color_plane >= fb->format->num_planes / 2;
> +}
> +
> static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
> {
> return IS_GEN(dev_priv, 2) ? 2048 : 4096;
> @@ -1908,11 +1924,13 @@ intel_tile_width_bytes(const struct drm_framebuffer
> *fb, int color_plane)
> else
> return 512;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> - if (color_plane == 1)
> + if (is_ccs_plane(fb, color_plane))
> return 128;
> /* fall through */
> + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> + /* fall through */
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> - if (color_plane == 1)
> + if (is_ccs_plane(fb, color_plane))
> return 64;
> /* fall through */
> case I915_FORMAT_MOD_Y_TILED:
> @@ -1921,7 +1939,7 @@ intel_tile_width_bytes(const struct drm_framebuffer
> *fb, int color_plane)
> else
> return 512;
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> - if (color_plane == 1)
> + if (is_ccs_plane(fb, color_plane))
> return 128;
> /* fall through */
> case I915_FORMAT_MOD_Yf_TILED:
> @@ -1949,8 +1967,9 @@ static unsigned int
> intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
> {
> switch (fb->modifier) {
> + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> - if (color_plane == 1)
> + if (is_ccs_plane(fb, color_plane))
> return 1;
> /* fall through */
> default:
> @@ -2055,6 +2074,7 @@ static unsigned int intel_surf_alignment(const struct
> drm_framebuffer *fb,
> if (INTEL_GEN(dev_priv) >= 9)
> return 256 * 1024;
> return 0;
> + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> return 16 * 1024;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> @@ -2254,10 +2274,17 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
> return new_offset;
> }
>
> -static bool is_surface_linear(u64 modifier, int color_plane)
> +static bool is_surface_linear(const struct drm_framebuffer *fb, int
> color_plane)
> {
> - return modifier == DRM_FORMAT_MOD_LINEAR ||
> -(modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane
> == 1);
> + switch (fb->modifier) {
> + case DRM_FORMAT_MOD_LINEAR:
> + return true;
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> + return is_ccs_plane(fb, color_plane);
> + default:
> + return false;
> + }
> }
>
> static u32 intel_adjust_aligned_offset(int *x, int *y,
>
Re: [Intel-gfx] [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake
Chris Wilson writes:
> There's very little variation in non-privileged registers for Tigerlake,
> so we can mostly inherit the set from gen11. There is no whitelist at
> present, so we do not need to add any special registers.
>
> v2: Add COMMON_SLICE_CHICKEN2, GEN9_SLICE_COMMON_ECO_CHICKEN1 and a
> variety of huc readonly status registers.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
> ---
> tests/i915/gem_ctx_isolation.c | 30 +-
> 1 file changed, 25 insertions(+), 5 deletions(-)
>
> diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> index df1d655ae..58b824e84 100644
> --- a/tests/i915/gem_ctx_isolation.c
> +++ b/tests/i915/gem_ctx_isolation.c
> @@ -55,10 +55,11 @@ enum {
> #define GEN9 (ALL << 9)
> #define GEN10 (ALL << 10)
> #define GEN11 (ALL << 11)
> +#define GEN12 (ALL << 12)
>
> #define NOCTX 0
>
> -#define LAST_KNOWN_GEN 11
> +#define LAST_KNOWN_GEN 12
>
> static const struct named_register {
> const char *name;
> @@ -116,9 +117,9 @@ static const struct named_register {
> { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
> { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
> { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
> - { "L3_Config", GEN8, RCS0, 0x7034 },
> - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0x },
> - { "TD_CTL2", GEN8, RCS0, 0xe404 },
> + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 },
> + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0x },
> + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 },
> { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
> { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
> { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
> @@ -142,7 +143,9 @@ static const struct named_register {
> /* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
> { "CTX_PREEMPT", NOCTX /* GEN9 */, RCS0, 0x2248 },
> { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true },
> + { "COMMON_SLICE_CHICKEN2", GEN9, RCS0, 0x7014, .masked = true },
> { "HDC_CHICKEN1", GEN_RANGE(9, 9), RCS0, 0x7304, .masked = true },
> + { "SLICE_COMMON_ECO_CHICKEN1", GEN_RANGE(9, 11), 0x731c, .masked = true
> },
> { "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask =
> ~0x10 },
> { "HALF_SLICE_CHICKEN7", GEN_RANGE(11, 11), RCS0, 0xe194, .masked =
> true },
> { "SAMPLER_MODE", GEN_RANGE(11, 11), RCS0, 0xe18c, .masked = true },
> @@ -178,6 +181,23 @@ static const struct named_register {
> { "VCS3 timestamp", GEN11, ~0u, 0x1d4358 },
> { "VECS timestamp", GEN11, ~0u, 0x1c8358 },
>
> + /* huc read only */
> + { "BSD0 0x2000", GEN11, ~0u, 0x1c + 0x2000 },
> + { "BSD0 0x2000", GEN11, ~0u, 0x1c + 0x2014 },
> + { "BSD0 0x2000", GEN11, ~0u, 0x1c + 0x23b0 },
> +
> + { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2000 },
> + { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2014 },
> + { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x23b0 },
> +
> + { "BSD2 0x2000", GEN11, ~0u, 0x1d + 0x2000 },
> + { "BSD2 0x2000", GEN11, ~0u, 0x1d + 0x2014 },
> + { "BSD2 0x2000", GEN11, ~0u, 0x1d + 0x23b0 },
> +
> + { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2000 },
> + { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2014 },
> + { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x23b0 },
> +
> {}
> };
>
> @@ -852,7 +872,7 @@ igt_main
> gen = intel_gen(intel_get_drm_devid(fd));
>
> igt_warn_on_f(gen > LAST_KNOWN_GEN,
> - "GEN not recognized! Test needs to be
> updated to run.");
> + "GEN not recognized! Test needs to be updated to
> run.\n");
> igt_skip_on(gen > LAST_KNOWN_GEN);
> }
>
> --
> 2.23.0
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for fix broken state checker and enable state checker for icl+
== Series Details ==
Series: fix broken state checker and enable state checker for icl+
URL : https://patchwork.freedesktop.org/series/67586/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7003_full -> Patchwork_14663_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14663_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14663_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14663_full:
### IGT changes ###
Possible regressions
* igt@gem_exec_reloc@basic-wc-cpu-active:
- shard-skl: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-skl10/igt@gem_exec_re...@basic-wc-cpu-active.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-skl5/igt@gem_exec_re...@basic-wc-cpu-active.html
* igt@gem_mmap_gtt@hang:
- shard-kbl: [PASS][3] -> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-kbl1/igt@gem_mmap_...@hang.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-kbl7/igt@gem_mmap_...@hang.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_cursor_legacy@all-pipes-forked-bo:
- {shard-tglb}: [PASS][5] -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-tglb7/igt@kms_cursor_leg...@all-pipes-forked-bo.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-tglb6/igt@kms_cursor_leg...@all-pipes-forked-bo.html
* igt@kms_plane_lowres@pipe-c-tiling-yf:
- {shard-tglb}: [SKIP][7] ([fdo#111615]) -> [INCOMPLETE][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-tglb1/igt@kms_plane_low...@pipe-c-tiling-yf.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-tglb1/igt@kms_plane_low...@pipe-c-tiling-yf.html
Known issues
Here are the changes found in Patchwork_14663_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#110841])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb5/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-iclb4/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#111325]) +7 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb5/igt@gem_exec_sched...@reorder-wide-bsd.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-iclb4/igt@gem_exec_sched...@reorder-wide-bsd.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-snb: [PASS][13] -> [DMESG-WARN][14] ([fdo#110789] /
[fdo#111870])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-snb5/igt@gem_userptr_bl...@dmabuf-unsync.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-snb5/igt@gem_userptr_bl...@dmabuf-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-skl: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870]) +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-skl3/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-skl6/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
- shard-iclb: [PASS][17] -> [DMESG-WARN][18] ([fdo#111870])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-iclb5/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-iclb4/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
* igt@gem_workarounds@suspend-resume:
- shard-skl: [PASS][19] -> [INCOMPLETE][20] ([fdo#104108] /
[fdo#107773])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-skl4/igt@gem_workarou...@suspend-resume.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14663/shard-skl3/igt@gem_workarou...@suspend-resume.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [PASS][21] -> [DMESG-WARN][22] ([fdo#108566]) +3
similar issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7003/shard-apl3/igt@i915_susp...@fence-restore-tiled2untiled.html
Re: [Intel-gfx] [PATCH] drm/i915: customize DPCD brightness control for specific panel
On Sat, 2019-10-05 at 05:58 +0800, Lee Shawn C wrote:
> This panel (manufacturer is SDC, product ID is 0x4141)
> used manufacturer defined DPCD register to control brightness
> that not defined in eDP spec so far. This change follow panel
> vendor's instruction to support brightness adjustment.
I'm sure this works, but this smells a little funny to me.
> + /* Samsung eDP panel */
> + { "SDC", 0x4141, EDID_QUIRK_NON_STD_BRIGHTNESS_CONTROL },
It feels a bit like a layering violation to identify eDP behavior
changes based on EDID. But I'm not sure there's any obvious way to
identify this device by its DPCD. The Sink OUI (from the linked
bugzilla) seems to be 0011F8, which doesn't match up to anything in my
oui.txt...
> @@ -1953,6 +1956,7 @@ static u32 edid_get_quirks(const struct edid *edid)
>
> return 0;
> }
> +EXPORT_SYMBOL(edid_get_quirks);
If we're going to export this it should probably get a drm_ prefix.
> +#define DPCD_EDP_GETSET_CTRL_PARAMS 0x344
> +#define DPCD_EDP_CONTENT_LUMINANCE 0x346
> +#define DPCD_EDP_PANEL_LUMINANCE_OVERRIDE0x34a
> +#define DPCD_EDP_BRIGHTNESS_NITS 0x354
> +#define DPCD_EDP_BRIGHTNESS_OPTIMIZATION 0x358
> +
> +#define EDP_CUSTOMIZE_MAX_BRIGHTNESS_LEVEL (512)
This also seems a bit weird, the 0x300-0x3FF registers belong to the
_source_ DP device. But then later...
> + /* write source OUI */
> + write_val[0] = 0x00;
> + write_val[1] = 0xaa;
> + write_val[2] = 0x01;
Oh hey, you're writing (an) Intel OUI to the Source OUI, so now it
makes sense that you're writing to registers whose behavior the source
defines. But this does raise the question: is this just a convention
between Intel and this particular panel? Would we expect this to work
with other similar panels? Is there any way to know to expect this
convention from DPCD instead?
- ajax
___
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[Intel-gfx] [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake
There's very little variation in non-privileged registers for Tigerlake,
so we can mostly inherit the set from gen11. There is no whitelist at
present, so we do not need to add any special registers.
v2: Add COMMON_SLICE_CHICKEN2, GEN9_SLICE_COMMON_ECO_CHICKEN1 and a
variety of huc readonly status registers.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
tests/i915/gem_ctx_isolation.c | 30 +-
1 file changed, 25 insertions(+), 5 deletions(-)
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index df1d655ae..58b824e84 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -55,10 +55,11 @@ enum {
#define GEN9 (ALL << 9)
#define GEN10 (ALL << 10)
#define GEN11 (ALL << 11)
+#define GEN12 (ALL << 12)
#define NOCTX 0
-#define LAST_KNOWN_GEN 11
+#define LAST_KNOWN_GEN 12
static const struct named_register {
const char *name;
@@ -116,9 +117,9 @@ static const struct named_register {
{ "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
{ "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
{ "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
- { "L3_Config", GEN8, RCS0, 0x7034 },
- { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0x },
- { "TD_CTL2", GEN8, RCS0, 0xe404 },
+ { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 },
+ { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0x },
+ { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 },
{ "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
{ "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
{ "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
@@ -142,7 +143,9 @@ static const struct named_register {
/* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
{ "CTX_PREEMPT", NOCTX /* GEN9 */, RCS0, 0x2248 },
{ "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true },
+ { "COMMON_SLICE_CHICKEN2", GEN9, RCS0, 0x7014, .masked = true },
{ "HDC_CHICKEN1", GEN_RANGE(9, 9), RCS0, 0x7304, .masked = true },
+ { "SLICE_COMMON_ECO_CHICKEN1", GEN_RANGE(9, 11), 0x731c, .masked = true
},
{ "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask =
~0x10 },
{ "HALF_SLICE_CHICKEN7", GEN_RANGE(11, 11), RCS0, 0xe194, .masked =
true },
{ "SAMPLER_MODE", GEN_RANGE(11, 11), RCS0, 0xe18c, .masked = true },
@@ -178,6 +181,23 @@ static const struct named_register {
{ "VCS3 timestamp", GEN11, ~0u, 0x1d4358 },
{ "VECS timestamp", GEN11, ~0u, 0x1c8358 },
+ /* huc read only */
+ { "BSD0 0x2000", GEN11, ~0u, 0x1c + 0x2000 },
+ { "BSD0 0x2000", GEN11, ~0u, 0x1c + 0x2014 },
+ { "BSD0 0x2000", GEN11, ~0u, 0x1c + 0x23b0 },
+
+ { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2000 },
+ { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2014 },
+ { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x23b0 },
+
+ { "BSD2 0x2000", GEN11, ~0u, 0x1d + 0x2000 },
+ { "BSD2 0x2000", GEN11, ~0u, 0x1d + 0x2014 },
+ { "BSD2 0x2000", GEN11, ~0u, 0x1d + 0x23b0 },
+
+ { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2000 },
+ { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2014 },
+ { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x23b0 },
+
{}
};
@@ -852,7 +872,7 @@ igt_main
gen = intel_gen(intel_get_drm_devid(fd));
igt_warn_on_f(gen > LAST_KNOWN_GEN,
- "GEN not recognized! Test needs to be
updated to run.");
+ "GEN not recognized! Test needs to be updated to
run.\n");
igt_skip_on(gen > LAST_KNOWN_GEN);
}
--
2.23.0
___
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Re: [Intel-gfx] [RFC v3 5/9] drm/i915: Extract framebufer CCS offset checks into a function
On Mon, Sep 23, 2019 at 03:29:31AM -0700, Dhinakaran Pandiyan wrote:
> intel_fill_fb_info() has grown quite large and wrapping the offset checks
> into a separate function makes the loop a bit easier to follow.
>
> Cc: Ville Syrjälä
> Cc: Matt Roper
> Signed-off-by: Dhinakaran Pandiyan
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 69
> 1 file changed, 40 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 6fec43cdddf4..7447001c1f85 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2682,6 +2682,43 @@ static bool intel_plane_needs_remap(const struct
> intel_plane_state *plane_state)
> return stride > max_stride;
> }
>
> +static int
> +intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
fb can be const
> +{
> + struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> + int hsub = fb->format->hsub;
> + int vsub = fb->format->vsub;
> + int tile_width, tile_height;
> + int ccs_x, ccs_y;
> + int main_x, main_y;
> +
> + intel_tile_dims(fb, 1, _width, _height);
> +
> + tile_width *= hsub;
> + tile_height *= vsub;
> +
> + ccs_x = (x * hsub) % tile_width;
> + ccs_y = (y * vsub) % tile_height;
> + main_x = intel_fb->normal[0].x % tile_width;
> + main_y = intel_fb->normal[0].y % tile_height;
> +
> + /*
> + * CCS doesn't have its own x/y offset register, so the intra CCS tile
> + * x/y offsets must match between CCS and the main surface.
> + */
Formatting fail with the comment?
Reviewed-by: Ville Syrjälä
> + if (main_x != ccs_x || main_y != ccs_y) {
> + DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main
> %d,%d ccs %d,%d)\n",
> + main_x, main_y,
> + ccs_x, ccs_y,
> + intel_fb->normal[0].x,
> + intel_fb->normal[0].y,
> + x, y);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> static int
> intel_fill_fb_info(struct drm_i915_private *dev_priv,
> struct drm_framebuffer *fb)
> @@ -2713,35 +2750,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
> }
>
> if (is_ccs_modifier(fb->modifier) && i == 1) {
> - int hsub = fb->format->hsub;
> - int vsub = fb->format->vsub;
> - int tile_width, tile_height;
> - int main_x, main_y;
> - int ccs_x, ccs_y;
> -
> - intel_tile_dims(fb, i, _width, _height);
> -
> - tile_width *= hsub;
> - tile_height *= vsub;
> -
> - ccs_x = (x * hsub) % tile_width;
> - ccs_y = (y * vsub) % tile_height;
> - main_x = intel_fb->normal[0].x % tile_width;
> - main_y = intel_fb->normal[0].y % tile_height;
> -
> - /*
> - * CCS doesn't have its own x/y offset register, so the
> intra CCS tile
> - * x/y offsets must match between CCS and the main
> surface.
> - */
> - if (main_x != ccs_x || main_y != ccs_y) {
> - DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs
> %d,%d) full (main %d,%d ccs %d,%d)\n",
> - main_x, main_y,
> - ccs_x, ccs_y,
> - intel_fb->normal[0].x,
> - intel_fb->normal[0].y,
> - x, y);
> - return -EINVAL;
> - }
> + ret = intel_fb_check_ccs_xy(fb, x, y);
> + if (ret)
> + return ret;
> }
>
> /*
> --
> 2.17.1
--
Ville Syrjälä
Intel
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/20] drm/i915: Only track bound elements of the GTT
== Series Details ==
Series: series starting with [01/20] drm/i915: Only track bound elements of the
GTT
URL : https://patchwork.freedesktop.org/series/67594/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7008 -> Patchwork_14669
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14669 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14669, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14669/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14669:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_workarounds:
- fi-glk-dsi: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7008/fi-glk-dsi/igt@i915_selftest@live_workarounds.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14669/fi-glk-dsi/igt@i915_selftest@live_workarounds.html
Known issues
Here are the changes found in Patchwork_14669 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_switch@legacy-render:
- fi-icl-u2: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] /
[fdo#111381])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7008/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14669/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_exec_fence@nb-await-default:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +3
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7008/fi-icl-u3/igt@gem_exec_fe...@nb-await-default.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14669/fi-icl-u3/igt@gem_exec_fe...@nb-await-default.html
Possible fixes
* igt@gem_exec_gttfill@basic:
- fi-apl-guc: [DMESG-WARN][7] ([fdo#109385] / [fdo#111652 ]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7008/fi-apl-guc/igt@gem_exec_gttf...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14669/fi-apl-guc/igt@gem_exec_gttf...@basic.html
* igt@gem_exec_reloc@basic-cpu:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +1
similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7008/fi-icl-u3/igt@gem_exec_re...@basic-cpu.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14669/fi-icl-u3/igt@gem_exec_re...@basic-cpu.html
* igt@i915_selftest@live_gem_contexts:
- {fi-tgl-u}: [INCOMPLETE][11] ([fdo#111831]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7008/fi-tgl-u/igt@i915_selftest@live_gem_contexts.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14669/fi-tgl-u/igt@i915_selftest@live_gem_contexts.html
* igt@i915_selftest@live_gtt:
- {fi-icl-guc}: [INCOMPLETE][13] ([fdo#107713]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7008/fi-icl-guc/igt@i915_selftest@live_gtt.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14669/fi-icl-guc/igt@i915_selftest@live_gtt.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#111045] / [fdo#111096]) ->
[FAIL][16] ([fdo#111407])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7008/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14669/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109385]: https://bugs.freedesktop.org/show_bug.cgi?id=109385
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111652 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111652
[fdo#111831]: https://bugs.freedesktop.org/show_bug.cgi?id=111831
Participating hosts (52 -> 42)
--
Missing(10): fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-skl-guc
fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-icl-y fi-icl-dsi fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7008 -> Patchwork_14669
CI-20190529: 20190529
CI_DRM_7008:
Re: [Intel-gfx] [PATCH] drm/i915: Use helpers for drm_mm_node booleans
On 04/10/2019 15:22, Chris Wilson wrote:
A subset of 71724f708997 ("drm/mm: Use helpers for drm_mm_node booleans")
in order to prepare drm-intel-next-queued for subsequent patches before
we can backmerge 71724f708997 itself.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++--
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c| 12 ++--
drivers/gpu/drm/i915/i915_gem_evict.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c| 2 +-
drivers/gpu/drm/i915/i915_vma.h| 4 ++--
6 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 8fbb454cfd6b..228ce24ea280 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -968,7 +968,7 @@ static void reloc_cache_reset(struct reloc_cache *cache)
intel_gt_flush_ggtt_writes(ggtt->vm.gt);
io_mapping_unmap_atomic((void __iomem *)vaddr);
- if (cache->node.allocated) {
+ if (drm_mm_node_allocated(>node)) {
ggtt->vm.clear_range(>vm,
cache->node.start,
cache->node.size);
@@ -1061,7 +1061,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj,
}
offset = cache->node.start;
- if (cache->node.allocated) {
+ if (drm_mm_node_allocated(>node)) {
ggtt->vm.insert_page(>vm,
i915_gem_object_get_dma_address(obj, page),
offset, I915_CACHE_NONE, 0);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index bb878119f06c..bb4889d2346d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -387,7 +387,7 @@ static u32 uc_fw_ggtt_offset(struct intel_uc_fw *uc_fw,
struct i915_ggtt *ggtt)
{
struct drm_mm_node *node = >uc_fw;
- GEM_BUG_ON(!node->allocated);
+ GEM_BUG_ON(!drm_mm_node_allocated(node));
GEM_BUG_ON(upper_32_bits(node->start));
GEM_BUG_ON(upper_32_bits(node->start + node->size - 1));
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1426e506700d..fa8e028ac0b5 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -356,7 +356,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
ret = insert_mappable_node(ggtt, , PAGE_SIZE);
if (ret)
goto out_unlock;
- GEM_BUG_ON(!node.allocated);
+ GEM_BUG_ON(!drm_mm_node_allocated());
}
mutex_unlock(>drm.struct_mutex);
@@ -393,7 +393,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
unsigned page_offset = offset_in_page(offset);
unsigned page_length = PAGE_SIZE - page_offset;
page_length = remain < page_length ? remain : page_length;
- if (node.allocated) {
+ if (drm_mm_node_allocated()) {
ggtt->vm.insert_page(>vm,
i915_gem_object_get_dma_address(obj,
offset >> PAGE_SHIFT),
node.start, I915_CACHE_NONE, 0);
@@ -415,7 +415,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
i915_gem_object_unlock_fence(obj, fence);
out_unpin:
mutex_lock(>drm.struct_mutex);
- if (node.allocated) {
+ if (drm_mm_node_allocated()) {
ggtt->vm.clear_range(>vm, node.start, node.size);
remove_mappable_node();
} else {
@@ -566,7 +566,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
ret = insert_mappable_node(ggtt, , PAGE_SIZE);
if (ret)
goto out_rpm;
- GEM_BUG_ON(!node.allocated);
+ GEM_BUG_ON(!drm_mm_node_allocated());
}
mutex_unlock(>drm.struct_mutex);
@@ -604,7 +604,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
unsigned int page_offset = offset_in_page(offset);
unsigned int page_length = PAGE_SIZE - page_offset;
page_length = remain < page_length ? remain : page_length;
- if (node.allocated) {
+ if (drm_mm_node_allocated()) {
/* flush the write before we modify the GGTT */
intel_gt_flush_ggtt_writes(ggtt->vm.gt);
ggtt->vm.insert_page(>vm,
@@ -636,7 +636,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
out_unpin:
mutex_lock(>drm.struct_mutex);
intel_gt_flush_ggtt_writes(ggtt->vm.gt);
- if
[Intel-gfx] [PATCH] semi-hax: drm/i915: Always verify ddb allocation
And only verify cursor allocation when cursor plane is active.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 46e3e8296251..6bdff08cf9c9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13369,7 +13369,7 @@ static void verify_wm_state(struct intel_crtc *crtc,
* allocation. In that case since the ddb allocation will be updated
* once the plane becomes visible, we can skip this check
*/
- if (1) {
+ if (I915_READ(CURCNTR(pipe)) & MCURSOR_MODE) {
struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
hw_plane_wm = >wm.planes[PLANE_CURSOR];
@@ -13665,10 +13665,11 @@ intel_modeset_verify_crtc(struct intel_crtc *crtc,
struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state)
{
+ verify_wm_state(crtc, new_crtc_state);
+
if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
return;
- verify_wm_state(crtc, new_crtc_state);
verify_connector_state(state, crtc);
verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Use helpers for drm_mm_node booleans
A subset of 71724f708997 ("drm/mm: Use helpers for drm_mm_node booleans")
in order to prepare drm-intel-next-queued for subsequent patches before
we can backmerge 71724f708997 itself.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++--
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c| 12 ++--
drivers/gpu/drm/i915/i915_gem_evict.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c| 2 +-
drivers/gpu/drm/i915/i915_vma.h| 4 ++--
6 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 8fbb454cfd6b..228ce24ea280 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -968,7 +968,7 @@ static void reloc_cache_reset(struct reloc_cache *cache)
intel_gt_flush_ggtt_writes(ggtt->vm.gt);
io_mapping_unmap_atomic((void __iomem *)vaddr);
- if (cache->node.allocated) {
+ if (drm_mm_node_allocated(>node)) {
ggtt->vm.clear_range(>vm,
cache->node.start,
cache->node.size);
@@ -1061,7 +1061,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj,
}
offset = cache->node.start;
- if (cache->node.allocated) {
+ if (drm_mm_node_allocated(>node)) {
ggtt->vm.insert_page(>vm,
i915_gem_object_get_dma_address(obj, page),
offset, I915_CACHE_NONE, 0);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index bb878119f06c..bb4889d2346d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -387,7 +387,7 @@ static u32 uc_fw_ggtt_offset(struct intel_uc_fw *uc_fw,
struct i915_ggtt *ggtt)
{
struct drm_mm_node *node = >uc_fw;
- GEM_BUG_ON(!node->allocated);
+ GEM_BUG_ON(!drm_mm_node_allocated(node));
GEM_BUG_ON(upper_32_bits(node->start));
GEM_BUG_ON(upper_32_bits(node->start + node->size - 1));
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1426e506700d..fa8e028ac0b5 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -356,7 +356,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
ret = insert_mappable_node(ggtt, , PAGE_SIZE);
if (ret)
goto out_unlock;
- GEM_BUG_ON(!node.allocated);
+ GEM_BUG_ON(!drm_mm_node_allocated());
}
mutex_unlock(>drm.struct_mutex);
@@ -393,7 +393,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
unsigned page_offset = offset_in_page(offset);
unsigned page_length = PAGE_SIZE - page_offset;
page_length = remain < page_length ? remain : page_length;
- if (node.allocated) {
+ if (drm_mm_node_allocated()) {
ggtt->vm.insert_page(>vm,
i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
node.start, I915_CACHE_NONE, 0);
@@ -415,7 +415,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
i915_gem_object_unlock_fence(obj, fence);
out_unpin:
mutex_lock(>drm.struct_mutex);
- if (node.allocated) {
+ if (drm_mm_node_allocated()) {
ggtt->vm.clear_range(>vm, node.start, node.size);
remove_mappable_node();
} else {
@@ -566,7 +566,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
ret = insert_mappable_node(ggtt, , PAGE_SIZE);
if (ret)
goto out_rpm;
- GEM_BUG_ON(!node.allocated);
+ GEM_BUG_ON(!drm_mm_node_allocated());
}
mutex_unlock(>drm.struct_mutex);
@@ -604,7 +604,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
unsigned int page_offset = offset_in_page(offset);
unsigned int page_length = PAGE_SIZE - page_offset;
page_length = remain < page_length ? remain : page_length;
- if (node.allocated) {
+ if (drm_mm_node_allocated()) {
/* flush the write before we modify the GGTT */
intel_gt_flush_ggtt_writes(ggtt->vm.gt);
ggtt->vm.insert_page(>vm,
@@ -636,7 +636,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
out_unpin:
mutex_lock(>drm.struct_mutex);
intel_gt_flush_ggtt_writes(ggtt->vm.gt);
- if (node.allocated) {
+ if
[Intel-gfx] [PATCH 4/4] drm/edid: Prep for HDMI VIC aspect ratio (WIP)
From: Ville Syrjälä
I think this should provide most of necessary logic for
adding aspecr ratios to the HDMI 4k modes.
Cc: Wayne Lin
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 37 +++--
1 file changed, 31 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index c7f9f7ca75a2..c76814edc784 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3210,6 +3210,11 @@ static enum hdmi_picture_aspect
drm_get_cea_aspect_ratio(const u8 video_code)
return edid_cea_modes[video_code].picture_aspect_ratio;
}
+static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
+{
+ return edid_4k_modes[video_code].picture_aspect_ratio;
+}
+
/*
* Calculate the alternate clock for HDMI modes (those from the HDMI vendor
* specific block).
@@ -3236,6 +3241,9 @@ static u8 drm_match_hdmi_mode_clock_tolerance(const
struct drm_display_mode *to_
if (!to_match->clock)
return 0;
+ if (to_match->picture_aspect_ratio)
+ match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
+
for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
const struct drm_display_mode *hdmi_mode = _4k_modes[vic];
unsigned int clock1, clock2;
@@ -3271,6 +3279,9 @@ static u8 drm_match_hdmi_mode(const struct
drm_display_mode *to_match)
if (!to_match->clock)
return 0;
+ if (to_match->picture_aspect_ratio)
+ match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
+
for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
const struct drm_display_mode *hdmi_mode = _4k_modes[vic];
unsigned int clock1, clock2;
@@ -5218,6 +5229,7 @@ drm_hdmi_avi_infoframe_from_display_mode(struct
hdmi_avi_infoframe *frame,
const struct drm_display_mode *mode)
{
enum hdmi_picture_aspect picture_aspect;
+ u8 vic, hdmi_vic;
int err;
if (!frame || !mode)
@@ -5230,7 +5242,8 @@ drm_hdmi_avi_infoframe_from_display_mode(struct
hdmi_avi_infoframe *frame,
if (mode->flags & DRM_MODE_FLAG_DBLCLK)
frame->pixel_repeat = 1;
- frame->video_code = drm_mode_cea_vic(connector, mode);
+ vic = drm_mode_cea_vic(connector, mode);
+ hdmi_vic = drm_mode_hdmi_vic(connector, mode);
frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
@@ -5244,11 +5257,15 @@ drm_hdmi_avi_infoframe_from_display_mode(struct
hdmi_avi_infoframe *frame,
/*
* Populate picture aspect ratio from either
-* user input (if specified) or from the CEA mode list.
+* user input (if specified) or from the CEA/HDMI mode lists.
*/
picture_aspect = mode->picture_aspect_ratio;
- if (picture_aspect == HDMI_PICTURE_ASPECT_NONE)
- picture_aspect = drm_get_cea_aspect_ratio(frame->video_code);
+ if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
+ if (vic)
+ picture_aspect = drm_get_cea_aspect_ratio(vic);
+ else if (hdmi_vic)
+ picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
+ }
/*
* The infoframe can't convey anything but none, 4:3
@@ -5256,12 +5273,20 @@ drm_hdmi_avi_infoframe_from_display_mode(struct
hdmi_avi_infoframe *frame,
* we can only satisfy it by specifying the right VIC.
*/
if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
- if (picture_aspect !=
- drm_get_cea_aspect_ratio(frame->video_code))
+ if (vic) {
+ if (picture_aspect != drm_get_cea_aspect_ratio(vic))
+ return -EINVAL;
+ } else if (hdmi_vic) {
+ if (picture_aspect !=
drm_get_hdmi_aspect_ratio(hdmi_vic))
+ return -EINVAL;
+ } else {
return -EINVAL;
+ }
+
picture_aspect = HDMI_PICTURE_ASPECT_NONE;
}
+ frame->video_code = vic;
frame->picture_aspect = picture_aspect;
frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/4] drm/edid: Make drm_get_cea_aspect_ratio() static
From: Ville Syrjälä
drm_get_cea_aspect_ratio() is not used outside drm_edid.c.
Make it static.
Cc: Wayne Lin
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 10 +-
include/drm/drm_edid.h | 1 -
2 files changed, 1 insertion(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 0552175313cb..3df8267adab9 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3205,18 +3205,10 @@ static bool drm_valid_cea_vic(u8 vic)
return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
}
-/**
- * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
- * the input VIC from the CEA mode list
- * @video_code: ID given to each of the CEA modes
- *
- * Returns picture aspect ratio
- */
-enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
+static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
{
return edid_cea_modes[video_code].picture_aspect_ratio;
}
-EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
/*
* Calculate the alternate clock for HDMI modes (those from the HDMI vendor
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index b9719418c3d2..efce675abf07 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -481,7 +481,6 @@ int drm_add_edid_modes(struct drm_connector *connector,
struct edid *edid);
int drm_add_override_edid_modes(struct drm_connector *connector);
u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
-enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code);
bool drm_detect_hdmi_monitor(struct edid *edid);
bool drm_detect_monitor_audio(struct edid *edid);
enum hdmi_quantization_range
--
2.21.0
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/4] drm/edid: Fix HDMI VIC handling
From: Ville Syrjälä
Extract drm_mode_hdmi_vic() to correctly calculate the final HDMI
VIC for us. Currently this is being done a bit differently between
the AVI and HDMI infoframes. Let's get both to agree on this.
We need to allow the case where a mode is both 3D and has a HDMI
VIC. Currently we'll just refuse to generate the HDMI infoframe when
we really should be setting HDMI VIC to 0 and instead enabling 3D
stereo signalling.
If the sink doesn't even support the HDMI infoframe we should
not be picking the HDMI VIC in favor of the CEA VIC, because then
we'll end up not sending either VIC in the end.
Cc: Wayne Lin
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 37 +
1 file changed, 21 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 495b7fb4d9ef..c7f9f7ca75a2 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -5160,11 +5160,25 @@ drm_hdmi_infoframe_set_hdr_metadata(struct
hdmi_drm_infoframe *frame,
}
EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
+static u8 drm_mode_hdmi_vic(struct drm_connector *connector,
+ const struct drm_display_mode *mode)
+{
+ bool has_hdmi_infoframe = connector ?
+ connector->display_info.has_hdmi_infoframe : false;
+
+ if (!has_hdmi_infoframe)
+ return 0;
+
+ /* No HDMI VIC when signalling 3D video format */
+ if (mode->flags & DRM_MODE_FLAG_3D_MASK)
+ return 0;
+
+ return drm_match_hdmi_mode(mode);
+}
+
static u8 drm_mode_cea_vic(struct drm_connector *connector,
const struct drm_display_mode *mode)
{
- u8 vendor_if_vic = drm_match_hdmi_mode(mode);
- bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
u8 vic;
/*
@@ -5173,7 +5187,7 @@ static u8 drm_mode_cea_vic(struct drm_connector
*connector,
* VIC in AVI infoframes. Lets check if this mode is present in
* HDMI 1.4b 4K modes
*/
- if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
+ if (drm_mode_hdmi_vic(connector, mode))
return 0;
vic = drm_match_cea_mode(mode);
@@ -5433,8 +5447,6 @@ drm_hdmi_vendor_infoframe_from_display_mode(struct
hdmi_vendor_infoframe *frame,
bool has_hdmi_infoframe = connector ?
connector->display_info.has_hdmi_infoframe : false;
int err;
- u32 s3d_flags;
- u8 vic;
if (!frame || !mode)
return -EINVAL;
@@ -5442,8 +5454,9 @@ drm_hdmi_vendor_infoframe_from_display_mode(struct
hdmi_vendor_infoframe *frame,
if (!has_hdmi_infoframe)
return -EINVAL;
- vic = drm_match_hdmi_mode(mode);
- s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
+ err = hdmi_vendor_infoframe_init(frame);
+ if (err < 0)
+ return err;
/*
* Even if it's not absolutely necessary to send the infoframe
@@ -5454,15 +5467,7 @@ drm_hdmi_vendor_infoframe_from_display_mode(struct
hdmi_vendor_infoframe *frame,
* mode if the source simply stops sending the infoframe when
* it wants to switch from 3D to 2D.
*/
-
- if (vic && s3d_flags)
- return -EINVAL;
-
- err = hdmi_vendor_infoframe_init(frame);
- if (err < 0)
- return err;
-
- frame->vic = vic;
+ frame->vic = drm_mode_hdmi_vic(connector, mode);
frame->s3d_struct = s3d_structure_from_display_mode(mode);
return 0;
--
2.21.0
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[Intel-gfx] [PATCH 2/4] drm/edid: Extract drm_mode_cea_vic()
From: Ville Syrjälä
Extract the logic to compute the final CEA VIC to a small helper.
We'll reorder it a bit to make future modifications more
straightforward. No function changes.
Cc: Wayne Lin
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 53 +-
1 file changed, 30 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 3df8267adab9..495b7fb4d9ef 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -5160,6 +5160,35 @@ drm_hdmi_infoframe_set_hdr_metadata(struct
hdmi_drm_infoframe *frame,
}
EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
+static u8 drm_mode_cea_vic(struct drm_connector *connector,
+ const struct drm_display_mode *mode)
+{
+ u8 vendor_if_vic = drm_match_hdmi_mode(mode);
+ bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
+ u8 vic;
+
+ /*
+* HDMI spec says if a mode is found in HDMI 1.4b 4K modes
+* we should send its VIC in vendor infoframes, else send the
+* VIC in AVI infoframes. Lets check if this mode is present in
+* HDMI 1.4b 4K modes
+*/
+ if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
+ return 0;
+
+ vic = drm_match_cea_mode(mode);
+
+ /*
+* HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
+* HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
+* have to make sure we dont break HDMI 1.4 sinks.
+*/
+ if (!is_hdmi2_sink(connector) && vic > 64)
+ return 0;
+
+ return vic;
+}
+
/**
* drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
* data from a DRM display mode
@@ -5187,29 +5216,7 @@ drm_hdmi_avi_infoframe_from_display_mode(struct
hdmi_avi_infoframe *frame,
if (mode->flags & DRM_MODE_FLAG_DBLCLK)
frame->pixel_repeat = 1;
- frame->video_code = drm_match_cea_mode(mode);
-
- /*
-* HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
-* HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
-* have to make sure we dont break HDMI 1.4 sinks.
-*/
- if (!is_hdmi2_sink(connector) && frame->video_code > 64)
- frame->video_code = 0;
-
- /*
-* HDMI spec says if a mode is found in HDMI 1.4b 4K modes
-* we should send its VIC in vendor infoframes, else send the
-* VIC in AVI infoframes. Lets check if this mode is present in
-* HDMI 1.4b 4K modes
-*/
- if (frame->video_code) {
- u8 vendor_if_vic = drm_match_hdmi_mode(mode);
- bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
-
- if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
- frame->video_code = 0;
- }
+ frame->video_code = drm_mode_cea_vic(connector, mode);
frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
--
2.21.0
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/20] drm/i915: Only track bound elements of the GTT
== Series Details == Series: series starting with [01/20] drm/i915: Only track bound elements of the GTT URL : https://patchwork.freedesktop.org/series/67594/ State : warning == Summary == $ dim checkpatch origin/drm-tip d11fa436d327 drm/i915: Only track bound elements of the GTT 800905fc6a4b drm/i915: Mark up address spaces that may need to allocate baba5b07 drm/i915: Pull i915_vma_pin under the vm->mutex 6b514f0bd7cd drm/i915: Push the i915_active.retire into a worker c647225bc29e drm/i915: Coordinate i915_active with its own mutex -:1340: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment #1340: FILE: drivers/gpu/drm/i915/i915_active_types.h:49: + struct mutex mutex; total: 0 errors, 0 warnings, 1 checks, 1481 lines checked 45a1ba9acaa8 drm/i915: Move idle barrier cleanup into engine-pm 986ee28a6333 drm/i915: Drop struct_mutex from around i915_retire_requests() 8cb980c09819 drm/i915: Remove the GEM idle worker 543c9b7f416f drm/i915: Merge wait_for_timelines with retire_request b9dcb683e7cd drm/i915/gem: Retire directly for mmap-offset shrinking bcf0f0e37bb4 drm/i915: Move request runtime management onto gt -:236: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #236: new file mode 100644 -:241: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #241: FILE: drivers/gpu/drm/i915/gt/intel_gt_requests.c:1: +/* -:242: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #242: FILE: drivers/gpu/drm/i915/gt/intel_gt_requests.c:2: + * SPDX-License-Identifier: MIT -:370: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #370: FILE: drivers/gpu/drm/i915/gt/intel_gt_requests.h:1: +/* -:371: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #371: FILE: drivers/gpu/drm/i915/gt/intel_gt_requests.h:2: + * SPDX-License-Identifier: MIT total: 0 errors, 5 warnings, 0 checks, 725 lines checked d63202e0c2f3 drm/i915: Move global activity tracking from GEM to GT c1c53b012e89 drm/i915: Remove logical HW ID -:508: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #508: FILE: drivers/gpu/drm/i915/gt/intel_lrc.h:69: +#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */ ^ -:510: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #510: FILE: drivers/gpu/drm/i915/gt/intel_lrc.h:71: +#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */ ^ total: 0 errors, 0 warnings, 2 checks, 723 lines checked c6f2dfae2a75 drm/i915: Move context management under GEM 24264690d400 drm/i915/overlay: Drop struct_mutex guard e4b36ecc353c drm/i915: Drop struct_mutex guard from debugfs/framebuffer_info 53e41a2ba1ae drm/i915: Remove struct_mutex guard for debugfs/opregion a4196eefca08 drm/i915: Drop struct_mutex from suspend state save/restore e2f73f4a716e drm/i915/selftests: Drop vestigal struct_mutex guards 5c3318d1382b drm/i915: Drop struct_mutex from around GEM initialisation ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/4] fix broken state checker and enable state checker for icl+
Hi, > -Original Message- > From: Intel-gfx On Behalf Of Swati > Sharma > Sent: perjantai 4. lokakuuta 2019 11.26 > To: intel-gfx@lists.freedesktop.org > Cc: Nikula, Jani ; Nautiyal, Ankit K > > Subject: [Intel-gfx] [PATCH 0/4] fix broken state checker and enable state > checker > for icl+ > > In this patch series, basically added 3 patches 1. Fixing broken > state-checker during > boot since legacy platforms > i.e. platforms for which state checker was already enabled 2. Moving > gamma_enable checks in bit_precision func() to platform Tested in BSW that was showing fancy colors previously and now booting to console with clean colors. Tested-by: Jani Saarinen > specific func() > 3. Enabling state checker for ICL and TGL > > Swati Sharma (4): > [v2] drm/i915/color: fix broken gamma state-checker during boot > drm/i915/color: move check of gamma_enable to specific func/platform > [v5] drm/i915/color: Extract icl_read_luts() > FOR_TESTING_ONLY: Print rgb values of hw and sw blobs > > drivers/gpu/drm/i915/display/intel_color.c | 166 ++--- > drivers/gpu/drm/i915/i915_reg.h| 6 + > 2 files changed, 152 insertions(+), 20 deletions(-) > > -- > 2.23.0 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: customize DPCD brightness control for specific panel
This panel (manufacturer is SDC, product ID is 0x4141)
used manufacturer defined DPCD register to control brightness
that not defined in eDP spec so far. This change follow panel
vendor's instruction to support brightness adjustment.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97883
Cc: Jani Nikula
Cc: Maarten Lankhorst
Cc: Gustavo Padovan
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/drm_edid.c| 6 +-
drivers/gpu/drm/i915/display/intel_dp.c | 7 +
.../drm/i915/display/intel_dp_aux_backlight.c | 143 +-
include/drm/drm_edid.h| 3 +
4 files changed, 153 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 3c9703b08491..5aee0ebc200e 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -211,6 +211,9 @@ static const struct edid_quirk {
/* OSVR HDK and HDK2 VR Headsets */
{ "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
+
+ /* Samsung eDP panel */
+ { "SDC", 0x4141, EDID_QUIRK_NON_STD_BRIGHTNESS_CONTROL },
};
/*
@@ -1938,7 +1941,7 @@ static bool edid_vendor(const struct edid *edid, const
char *vendor)
*
* This tells subsequent routines what fixes they need to apply.
*/
-static u32 edid_get_quirks(const struct edid *edid)
+u32 edid_get_quirks(const struct edid *edid)
{
const struct edid_quirk *quirk;
int i;
@@ -1953,6 +1956,7 @@ static u32 edid_get_quirks(const struct edid *edid)
return 0;
}
+EXPORT_SYMBOL(edid_get_quirks);
#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 2b1e71f992b0..89193bd2d8ea 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7097,6 +7097,13 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
}
intel_connector->edid = edid;
+ if (edid_get_quirks(intel_connector->edid) ==
+ EDID_QUIRK_NON_STD_BRIGHTNESS_CONTROL) {
+ i915_modparams.enable_dpcd_backlight = true;
+ i915_modparams.fastboot = false;
+ DRM_DEBUG_KMS("Using specific DPCD to control brightness\n");
+ }
+
fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
if (fixed_mode)
downclock_mode = intel_dp_drrs_init(intel_connector,
fixed_mode);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 020422da2ae2..7d9a2249cfb1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -25,6 +25,117 @@
#include "intel_display_types.h"
#include "intel_dp_aux_backlight.h"
+#define DPCD_EDP_GETSET_CTRL_PARAMS0x344
+#define DPCD_EDP_CONTENT_LUMINANCE 0x346
+#define DPCD_EDP_PANEL_LUMINANCE_OVERRIDE 0x34a
+#define DPCD_EDP_BRIGHTNESS_NITS 0x354
+#define DPCD_EDP_BRIGHTNESS_OPTIMIZATION 0x358
+
+#define EDP_CUSTOMIZE_MAX_BRIGHTNESS_LEVEL (512)
+
+static uint32_t intel_dp_aux_get_customize_backlight(struct intel_connector
*connector)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(>encoder->base);
+ uint8_t read_val[2] = { 0x0 };
+
+ if (drm_dp_dpcd_read(_dp->aux, DPCD_EDP_BRIGHTNESS_NITS,
+_val, sizeof(read_val)) < 0) {
+ DRM_DEBUG_KMS("Failed to read DPCD register %x\n",
+ DPCD_EDP_BRIGHTNESS_NITS);
+ return 0;
+ }
+
+ return (read_val[1] << 8 | read_val[0]);
+}
+
+static void
+intel_dp_aux_set_customize_backlight(const struct drm_connector_state
*conn_state, u32 level)
+{
+ struct intel_connector *connector =
to_intel_connector(conn_state->connector);
+ struct intel_dp *intel_dp = enc_to_intel_dp(>encoder->base);
+ struct intel_panel *panel = >panel;
+ uint8_t new_vals[4];
+
+ if (level > panel->backlight.max)
+ level = panel->backlight.max;
+
+ new_vals[0] = level & 0xFF;
+ new_vals[1] = (level & 0xFF00) >> 8;
+ new_vals[2] = 0;
+ new_vals[3] = 0;
+
+ if (drm_dp_dpcd_write(_dp->aux, DPCD_EDP_BRIGHTNESS_NITS,
new_vals, 4) < 0)
+ DRM_DEBUG_KMS("Failed to write aux backlight level\n");
+}
+
+static void intel_dp_aux_enable_customize_backlight(const struct
intel_crtc_state *crtc_state,
+ const struct drm_connector_state
*conn_state)
+{
+ struct intel_connector *connector =
to_intel_connector(conn_state->connector);
+ struct intel_dp *intel_dp = enc_to_intel_dp(>encoder->base);
+ uint8_t read_val[4], i;
+ uint8_t write_val[8] = {0x00, 0x00, 0xF0, 0x01, 0x90, 0x01, 0x00, 0x00};
+
+ if
[Intel-gfx] [PATCH 12/20] drm/i915: Move global activity tracking from GEM to GT
As our global unpark/park keep track of the number of active users, we
can simply move the accounting from the GEM layer to the base GT layer.
It was placed originally inside GEM to benefit from the 100ms extra
delay on idleness, but that has been eliminated and now there is no
substantive difference between the layers. In moving it, we move another
piece of the puzzle out from underneath struct_mutex.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 11 +--
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 5 +
2 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 9194d8464bf7..7c316d4633db 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -10,14 +10,6 @@
#include "gt/intel_gt_requests.h"
#include "i915_drv.h"
-#include "i915_globals.h"
-
-static void i915_gem_park(struct drm_i915_private *i915)
-{
- i915_vma_parked(i915);
-
- i915_globals_park();
-}
static int pm_notifier(struct notifier_block *nb,
unsigned long action,
@@ -28,11 +20,10 @@ static int pm_notifier(struct notifier_block *nb,
switch (action) {
case INTEL_GT_UNPARK:
- i915_globals_unpark();
break;
case INTEL_GT_PARK:
- i915_gem_park(i915);
+ i915_vma_parked(i915);
break;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index d2e80ba64d69..b52e2ba3d092 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -5,6 +5,7 @@
*/
#include "i915_drv.h"
+#include "i915_globals.h"
#include "i915_params.h"
#include "intel_context.h"
#include "intel_engine_pm.h"
@@ -27,6 +28,8 @@ static int __gt_unpark(struct intel_wakeref *wf)
GEM_TRACE("\n");
+ i915_globals_unpark();
+
/*
* It seems that the DMC likes to transition between the DC states a lot
* when there are no connected displays (no active power domains) during
@@ -78,6 +81,8 @@ static int __gt_park(struct intel_wakeref *wf)
GEM_BUG_ON(!wakeref);
intel_display_power_put(i915, POWER_DOMAIN_GT_IRQ, wakeref);
+ i915_globals_park();
+
return 0;
}
--
2.23.0
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[Intel-gfx] [PATCH 17/20] drm/i915: Remove struct_mutex guard for debugfs/opregion
Having a struct_mutex around the read of a BIOS blob serves no purpose.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 77933b23070e..298a3e879e65 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1500,21 +1500,11 @@ static int i915_ring_freq_table(struct seq_file *m,
void *unused)
static int i915_opregion(struct seq_file *m, void *unused)
{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct drm_device *dev = _priv->drm;
- struct intel_opregion *opregion = _priv->opregion;
- int ret;
-
- ret = mutex_lock_interruptible(>struct_mutex);
- if (ret)
- goto out;
+ struct intel_opregion *opregion = _to_i915(m->private)->opregion;
if (opregion->header)
seq_write(m, opregion->header, OPREGION_SIZE);
- mutex_unlock(>struct_mutex);
-
-out:
return 0;
}
--
2.23.0
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[Intel-gfx] [PATCH 05/20] drm/i915: Coordinate i915_active with its own mutex
Forgo the struct_mutex serialisation for i915_active, and interpose its
own mutex handling for active/retire.
This is a multi-layered sleight-of-hand. First, we had to ensure that no
active/retire callbacks accidentally inverted the mutex ordering rules,
nor assumed that they were themselves serialised by struct_mutex. More
challenging though, is the rule over updating elements of the active
rbtree. Instead of the whole i915_active now being serialised by
struct_mutex, allocations/rotations of the tree are serialised by the
i915_active.mutex and individual nodes are serialised by the caller
using the i915_timeline.mutex (we need to use nested spinlocks to
interact with the dma_fence callback lists).
The pain point here is that instead of a single mutex around execbuf, we
now have to take a mutex for active tracker (one for each vma, context,
etc) and a couple of spinlocks for each fence update. The improvement in
fine grained locking allowing for multiple concurrent clients
(eventually!) should be worth it in typical loads.
v2: Add some comments that barely elucidate anything :(
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../gpu/drm/i915/display/intel_frontbuffer.c | 2 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 9 +-
drivers/gpu/drm/i915/gt/intel_context.c | 4 +-
drivers/gpu/drm/i915/gt/intel_engine_pool.c | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 10 +-
drivers/gpu/drm/i915/gt/intel_timeline.c | 7 +-
.../gpu/drm/i915/gt/intel_timeline_types.h| 9 +-
drivers/gpu/drm/i915/gt/selftest_context.c| 16 +-
drivers/gpu/drm/i915/gt/selftest_lrc.c| 10 +-
.../gpu/drm/i915/gt/selftests/mock_timeline.c | 2 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 3 -
drivers/gpu/drm/i915/i915_active.c| 322 +-
drivers/gpu/drm/i915/i915_active.h| 319 -
drivers/gpu/drm/i915/i915_active_types.h | 23 +-
drivers/gpu/drm/i915/i915_gem.c | 42 ++-
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 4 +-
drivers/gpu/drm/i915/i915_request.c | 38 +--
drivers/gpu/drm/i915/i915_request.h | 1 -
drivers/gpu/drm/i915/i915_vma.c | 4 +-
drivers/gpu/drm/i915/selftests/i915_active.c | 32 +-
24 files changed, 298 insertions(+), 572 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
index 6428b8dd70d3..84b164f31895 100644
--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
@@ -257,7 +257,7 @@ intel_frontbuffer_get(struct drm_i915_gem_object *obj)
front->obj = obj;
kref_init(>ref);
atomic_set(>bits, 0);
- i915_active_init(i915, >write,
+ i915_active_init(>write,
frontbuffer_active,
i915_active_may_sleep(frontbuffer_retire));
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c
b/drivers/gpu/drm/i915/display/intel_overlay.c
index 3f4ac1ee7668..e12e1a753af0 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -1360,8 +1360,7 @@ void intel_overlay_setup(struct drm_i915_private
*dev_priv)
overlay->contrast = 75;
overlay->saturation = 146;
- i915_active_init(dev_priv,
->last_flip,
+ i915_active_init(>last_flip,
NULL, intel_overlay_last_flip_retire);
ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv));
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 4cd7d2ecf1d5..9d85aab68d34 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -868,20 +868,18 @@ static int context_barrier_task(struct i915_gem_context
*ctx,
void (*task)(void *data),
void *data)
{
- struct drm_i915_private *i915 = ctx->i915;
struct context_barrier_task *cb;
struct i915_gem_engines_iter it;
struct intel_context *ce;
int err = 0;
- lockdep_assert_held(>drm.struct_mutex);
GEM_BUG_ON(!task);
cb = kmalloc(sizeof(*cb), GFP_KERNEL);
if (!cb)
return -ENOMEM;
- i915_active_init(i915, >base, NULL, cb_retire);
+ i915_active_init(>base, NULL, cb_retire);
err = i915_active_acquire(>base);
if (err) {
kfree(cb);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index e1aab2fd1cd9..c00b4f077f9e 100644
---
[Intel-gfx] [PATCH 19/20] drm/i915/selftests: Drop vestigal struct_mutex guards
We no longer need struct_mutex to serialise request emission, so remove
it from the gt selftests.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 15 +-
.../drm/i915/gem/selftests/i915_gem_context.c | 4 -
.../drm/i915/gem/selftests/i915_gem_mman.c| 2 -
.../drm/i915/gem/selftests/i915_gem_phys.c| 2 -
drivers/gpu/drm/i915/gt/selftest_lrc.c| 148 +++---
.../gpu/drm/i915/gt/selftest_workarounds.c| 11 +-
drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 4 -
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 2 -
8 files changed, 27 insertions(+), 161 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 3314858f3046..e42abddd4a36 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1639,7 +1639,6 @@ int i915_gem_huge_page_mock_selftests(void)
mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;
mkwrite_device_info(dev_priv)->ppgtt_size = 48;
- mutex_lock(_priv->drm.struct_mutex);
ppgtt = i915_ppgtt_create(dev_priv);
if (IS_ERR(ppgtt)) {
err = PTR_ERR(ppgtt);
@@ -1665,9 +1664,7 @@ int i915_gem_huge_page_mock_selftests(void)
i915_vm_put(>vm);
out_unlock:
- mutex_unlock(_priv->drm.struct_mutex);
drm_dev_put(_priv->drm);
-
return err;
}
@@ -1684,7 +1681,6 @@ int i915_gem_huge_page_live_selftests(struct
drm_i915_private *i915)
struct drm_file *file;
struct i915_gem_context *ctx;
struct i915_address_space *vm;
- intel_wakeref_t wakeref;
int err;
if (!HAS_PPGTT(i915)) {
@@ -1699,13 +1695,10 @@ int i915_gem_huge_page_live_selftests(struct
drm_i915_private *i915)
if (IS_ERR(file))
return PTR_ERR(file);
- mutex_lock(>drm.struct_mutex);
- wakeref = intel_runtime_pm_get(>runtime_pm);
-
ctx = live_context(i915, file);
if (IS_ERR(ctx)) {
err = PTR_ERR(ctx);
- goto out_unlock;
+ goto out_file;
}
mutex_lock(>mutex);
@@ -1716,11 +1709,7 @@ int i915_gem_huge_page_live_selftests(struct
drm_i915_private *i915)
err = i915_subtests(tests, ctx);
-out_unlock:
- intel_runtime_pm_put(>runtime_pm, wakeref);
- mutex_unlock(>drm.struct_mutex);
-
+out_file:
mock_file_free(i915, file);
-
return err;
}
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index d44fa9d356f1..fb58c0919ea1 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -307,9 +307,7 @@ static int live_parallel_switch(void *arg)
struct igt_live_test t;
int n;
- mutex_lock(>drm.struct_mutex);
err = igt_live_test_begin(, i915, __func__, "");
- mutex_unlock(>drm.struct_mutex);
if (err)
break;
@@ -341,10 +339,8 @@ static int live_parallel_switch(void *arg)
data[n].tsk = NULL;
}
- mutex_lock(>drm.struct_mutex);
if (igt_live_test_end())
err = -EIO;
- mutex_unlock(>drm.struct_mutex);
}
out:
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 1cd25cfd0246..cfa52c525691 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -669,9 +669,7 @@ static int igt_mmap_offset_exhaustion(void *arg)
goto out;
}
- mutex_lock(>drm.struct_mutex);
err = make_obj_busy(obj);
- mutex_unlock(>drm.struct_mutex);
if (err) {
pr_err("[loop %d] Failed to busy the object\n", loop);
goto err_obj;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c
index 94a15e3f6db8..34932871b3a5 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c
@@ -25,9 +25,7 @@ static int mock_phys_object(void *arg)
goto out;
}
- mutex_lock(>drm.struct_mutex);
err = i915_gem_object_attach_phys(obj, PAGE_SIZE);
- mutex_unlock(>drm.struct_mutex);
if (err) {
pr_err("i915_gem_object_attach_phys failed, err=%d\n", err);
goto out_obj;
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 8dc42c5c7569..393ae5321e1d 100644
---
[Intel-gfx] [PATCH 16/20] drm/i915: Drop struct_mutex guard from debugfs/framebuffer_info
It protects nothing being accessed for the intel_framebuffer, so it's
own locking had better be sufficient.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index b04cebc26eca..77933b23070e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1534,11 +1534,6 @@ static int i915_gem_framebuffer_info(struct seq_file *m,
void *data)
struct drm_device *dev = _priv->drm;
struct intel_framebuffer *fbdev_fb = NULL;
struct drm_framebuffer *drm_fb;
- int ret;
-
- ret = mutex_lock_interruptible(>struct_mutex);
- if (ret)
- return ret;
#ifdef CONFIG_DRM_FBDEV_EMULATION
if (dev_priv->fbdev && dev_priv->fbdev->helper.fb) {
@@ -1573,7 +1568,6 @@ static int i915_gem_framebuffer_info(struct seq_file *m,
void *data)
seq_putc(m, '\n');
}
mutex_unlock(>mode_config.fb_lock);
- mutex_unlock(>struct_mutex);
return 0;
}
--
2.23.0
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Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake
Quoting Mika Kuoppala (2019-10-04 14:51:05)
> Chris Wilson writes:
>
> > There's very little variation in non-privileged registers for Tigerlake,
> > so we can mostly inherit the set from gen11. There is no whitelist at
> > present, so we do not need to add any special registers.
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599
> > Signed-off-by: Chris Wilson
> > ---
> > tests/i915/gem_ctx_isolation.c | 11 ++-
> > 1 file changed, 6 insertions(+), 5 deletions(-)
> >
> > diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> > index df1d655ae..819daafc3 100644
> > --- a/tests/i915/gem_ctx_isolation.c
> > +++ b/tests/i915/gem_ctx_isolation.c
> > @@ -55,10 +55,11 @@ enum {
> > #define GEN9 (ALL << 9)
> > #define GEN10 (ALL << 10)
> > #define GEN11 (ALL << 11)
> > +#define GEN12 (ALL << 12)
> >
> > #define NOCTX 0
> >
> > -#define LAST_KNOWN_GEN 11
> > +#define LAST_KNOWN_GEN 12
> >
> > static const struct named_register {
> > const char *name;
> > @@ -116,9 +117,9 @@ static const struct named_register {
> > { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
> > { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
> > { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
> > - { "L3_Config", GEN8, RCS0, 0x7034 },
> > - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0x },
> > - { "TD_CTL2", GEN8, RCS0, 0xe404 },
> > + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 },
> > + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0x },
> > + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 },
>
> The ignore list needs an update too?
The timestamps? The extra VCS are marked as GEN11+ and we weren't caught
out by noticing the counter change -- so I presume it was ok.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915/vga: rename intel_vga_msr_write() to intel_vga_reset_io_mem()
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/vga: rename
intel_vga_msr_write() to intel_vga_reset_io_mem()
URL : https://patchwork.freedesktop.org/series/67592/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7007 -> Patchwork_14668
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14668/index.html
Known issues
Here are the changes found in Patchwork_14668 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_switch@legacy-render:
- fi-icl-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#111381])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7007/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14668/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
Possible fixes
* igt@gem_ctx_switch@rcs0:
- fi-cml-u2: [INCOMPLETE][3] ([fdo#110566]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7007/fi-cml-u2/igt@gem_ctx_swi...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14668/fi-cml-u2/igt@gem_ctx_swi...@rcs0.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][5] ([fdo#111407]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7007/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14668/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][7] ([fdo#102614]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7007/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14668/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- {fi-icl-dsi}: [DMESG-WARN][9] ([fdo#106107]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7007/fi-icl-dsi/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14668/fi-icl-dsi/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (51 -> 39)
--
Additional (1): fi-pnv-d510
Missing(13): fi-ilk-m540 fi-bsw-n3050 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-skl-6260u fi-icl-u3 fi-icl-y fi-blb-e6850 fi-icl-guc
fi-byt-clapper fi-bdw-samus fi-kbl-r
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7007 -> Patchwork_14668
CI-20190529: 20190529
CI_DRM_7007: 825772b37c954f51a07517d971c862c53012c12d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5211: 1601e1571eb0f29a06b64494040b3ea7859a650f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14668: cda2e2643fa71fd3b4f2a9ad0888b8152e249ef4 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cda2e2643fa7 drm/i915: move gmbus setup down to intel_modeset_init()
b8e3e32314d6 drm/i915: split out i915_switcheroo.[ch] from i915_drv.c
095e27e1a8ba drm/i915/vga: rename intel_vga_msr_write() to
intel_vga_reset_io_mem()
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14668/index.html
___
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Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake
Chris Wilson writes:
> There's very little variation in non-privileged registers for Tigerlake,
> so we can mostly inherit the set from gen11. There is no whitelist at
> present, so we do not need to add any special registers.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599
> Signed-off-by: Chris Wilson
> ---
> tests/i915/gem_ctx_isolation.c | 11 ++-
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> index df1d655ae..819daafc3 100644
> --- a/tests/i915/gem_ctx_isolation.c
> +++ b/tests/i915/gem_ctx_isolation.c
> @@ -55,10 +55,11 @@ enum {
> #define GEN9 (ALL << 9)
> #define GEN10 (ALL << 10)
> #define GEN11 (ALL << 11)
> +#define GEN12 (ALL << 12)
>
> #define NOCTX 0
>
> -#define LAST_KNOWN_GEN 11
> +#define LAST_KNOWN_GEN 12
>
> static const struct named_register {
> const char *name;
> @@ -116,9 +117,9 @@ static const struct named_register {
> { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
> { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
> { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
> - { "L3_Config", GEN8, RCS0, 0x7034 },
> - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0x },
> - { "TD_CTL2", GEN8, RCS0, 0xe404 },
> + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 },
> + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0x },
> + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 },
The ignore list needs an update too?
-Mika
> { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
> { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
> { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
> @@ -852,7 +853,7 @@ igt_main
> gen = intel_gen(intel_get_drm_devid(fd));
>
> igt_warn_on_f(gen > LAST_KNOWN_GEN,
> - "GEN not recognized! Test needs to be
> updated to run.");
> + "GEN not recognized! Test needs to be updated to
> run.");
> igt_skip_on(gen > LAST_KNOWN_GEN);
> }
>
> --
> 2.23.0
>
> ___
> igt-dev mailing list
> igt-...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [Intel-gfx] [PATCH 14/20] drm/i915: Move context management under GEM
On 04/10/2019 14:40, Chris Wilson wrote:
Keep track of the GEM contexts underneath i915->gem.contexts and assign
them their own lock for the purposes of list management.
v2: Focus on lock tracking; ctx->vm is protected by ctx->mutex
v3: Correct split with removal of logical HW ID
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 177 +-
drivers/gpu/drm/i915/gem/i915_gem_context.h | 27 ++-
.../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 3 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 36 ++--
.../drm/i915/gem/selftests/i915_gem_context.c | 168 -
.../gpu/drm/i915/gem/selftests/mock_context.c | 7 +-
drivers/gpu/drm/i915/gt/intel_context.c | 10 +-
drivers/gpu/drm/i915/gt/selftest_context.c| 24 +--
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 39 ++--
drivers/gpu/drm/i915/gt/selftest_lrc.c| 6 +-
.../gpu/drm/i915/gt/selftest_workarounds.c| 22 ++-
drivers/gpu/drm/i915/gvt/scheduler.c | 24 +--
drivers/gpu/drm/i915/i915_debugfs.c | 50 +++--
drivers/gpu/drm/i915/i915_drv.c | 2 -
drivers/gpu/drm/i915/i915_drv.h | 15 +-
drivers/gpu/drm/i915/i915_gem.c | 10 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +-
drivers/gpu/drm/i915/i915_perf.c | 24 ++-
drivers/gpu/drm/i915/i915_sysfs.c | 43 ++---
drivers/gpu/drm/i915/i915_trace.h | 2 +-
drivers/gpu/drm/i915/selftests/i915_gem.c | 8 -
.../gpu/drm/i915/selftests/i915_gem_evict.c | 3 -
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 15 +-
drivers/gpu/drm/i915/selftests/i915_request.c | 12 +-
drivers/gpu/drm/i915/selftests/i915_vma.c | 7 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 6 +-
28 files changed, 394 insertions(+), 354 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index cd4f327b23bd..5d8221c7ba83 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -218,9 +218,12 @@ static struct i915_gem_engines *default_engines(struct
i915_gem_context *ctx)
static void i915_gem_context_free(struct i915_gem_context *ctx)
{
- lockdep_assert_held(>i915->drm.struct_mutex);
GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
+ spin_lock(>i915->gem.contexts.lock);
+ list_del(>link);
+ spin_unlock(>i915->gem.contexts.lock);
+
free_engines(rcu_access_pointer(ctx->engines));
mutex_destroy(>engines_mutex);
@@ -230,67 +233,54 @@ static void i915_gem_context_free(struct i915_gem_context *ctx)
kfree(ctx->name);
put_pid(ctx->pid);
- list_del(>link);
mutex_destroy(>mutex);
kfree_rcu(ctx, rcu);
}
-static void contexts_free(struct drm_i915_private *i915)
+static void contexts_free_all(struct llist_node *list)
{
- struct llist_node *freed = llist_del_all(>contexts.free_list);
struct i915_gem_context *ctx, *cn;
- lockdep_assert_held(>drm.struct_mutex);
-
- llist_for_each_entry_safe(ctx, cn, freed, free_link)
+ llist_for_each_entry_safe(ctx, cn, list, free_link)
i915_gem_context_free(ctx);
}
-static void contexts_free_first(struct drm_i915_private *i915)
+static void contexts_flush_free(struct i915_gem_contexts *gc)
{
- struct i915_gem_context *ctx;
- struct llist_node *freed;
-
- lockdep_assert_held(>drm.struct_mutex);
-
- freed = llist_del_first(>contexts.free_list);
- if (!freed)
- return;
-
- ctx = container_of(freed, typeof(*ctx), free_link);
- i915_gem_context_free(ctx);
+ contexts_free_all(llist_del_all(>free_list));
}
static void contexts_free_worker(struct work_struct *work)
{
- struct drm_i915_private *i915 =
- container_of(work, typeof(*i915), contexts.free_work);
+ struct i915_gem_contexts *gc =
+ container_of(work, typeof(*gc), free_work);
- mutex_lock(>drm.struct_mutex);
- contexts_free(i915);
- mutex_unlock(>drm.struct_mutex);
+ contexts_flush_free(gc);
}
void i915_gem_context_release(struct kref *ref)
{
struct i915_gem_context *ctx = container_of(ref, typeof(*ctx), ref);
- struct drm_i915_private *i915 = ctx->i915;
+ struct i915_gem_contexts *gc = >i915->gem.contexts;
trace_i915_context_free(ctx);
- if (llist_add(>free_link, >contexts.free_list))
- queue_work(i915->wq, >contexts.free_work);
+ if (llist_add(>free_link, >free_list))
+ schedule_work(>free_work);
}
static void context_close(struct i915_gem_context *ctx)
{
[Intel-gfx] [PATCH 20/20] drm/i915: Drop struct_mutex from around GEM initialisation
We no longer need to placate lockdep by holding struct_mutex for our
initialisation, so don't.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2 --
drivers/gpu/drm/i915/i915_gem.c | 9 -
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 7 ---
3 files changed, 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 7c316d4633db..7987b54fb1f5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -174,7 +174,6 @@ void i915_gem_resume(struct drm_i915_private *i915)
{
GEM_TRACE("\n");
- mutex_lock(>drm.struct_mutex);
intel_uncore_forcewake_get(>uncore, FORCEWAKE_ALL);
if (intel_gt_init_hw(>gt))
@@ -198,7 +197,6 @@ void i915_gem_resume(struct drm_i915_private *i915)
out_unlock:
intel_uncore_forcewake_put(>uncore, FORCEWAKE_ALL);
- mutex_unlock(>drm.struct_mutex);
return;
err_wedged:
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f6db415985d5..0ddbd3a5fb8d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1249,7 +1249,6 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
* we hold the forcewake during initialisation these problems
* just magically go away.
*/
- mutex_lock(_priv->drm.struct_mutex);
intel_uncore_forcewake_get(_priv->uncore, FORCEWAKE_ALL);
ret = i915_init_ggtt(dev_priv);
@@ -1319,7 +1318,6 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
goto err_gt;
intel_uncore_forcewake_put(_priv->uncore, FORCEWAKE_ALL);
- mutex_unlock(_priv->drm.struct_mutex);
return 0;
@@ -1330,15 +1328,11 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
* driver doesn't explode during runtime.
*/
err_gt:
- mutex_unlock(_priv->drm.struct_mutex);
-
intel_gt_set_wedged_on_init(_priv->gt);
i915_gem_suspend(dev_priv);
i915_gem_suspend_late(dev_priv);
i915_gem_drain_workqueue(dev_priv);
-
- mutex_lock(_priv->drm.struct_mutex);
err_init_hw:
intel_uc_fini_hw(_priv->gt.uc);
err_uc_init:
@@ -1353,7 +1347,6 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
intel_gt_driver_release(_priv->gt);
err_unlock:
intel_uncore_forcewake_put(_priv->uncore, FORCEWAKE_ALL);
- mutex_unlock(_priv->drm.struct_mutex);
if (ret != -EIO) {
intel_uc_cleanup_firmwares(_priv->gt.uc);
@@ -1406,10 +1399,8 @@ void i915_gem_driver_remove(struct drm_i915_private
*dev_priv)
/* Flush any outstanding unpin_work. */
i915_gem_drain_workqueue(dev_priv);
- mutex_lock(_priv->drm.struct_mutex);
intel_uc_fini_hw(_priv->gt.uc);
intel_uc_fini(_priv->gt.uc);
- mutex_unlock(_priv->drm.struct_mutex);
i915_gem_drain_freed_objects(dev_priv);
}
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 335f37ba98de..70a7026db08d 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -68,10 +68,7 @@ static void mock_device_release(struct drm_device *dev)
drain_workqueue(i915->wq);
i915_gem_drain_freed_objects(i915);
- mutex_lock(>drm.struct_mutex);
mock_fini_ggtt(>ggtt);
- mutex_unlock(>drm.struct_mutex);
-
destroy_workqueue(i915->wq);
i915_gemfs_fini(i915);
@@ -179,8 +176,6 @@ struct drm_i915_private *mock_gem_device(void)
intel_timelines_init(i915);
- mutex_lock(>drm.struct_mutex);
-
mock_init_ggtt(i915, >ggtt);
mkwrite_device_info(i915)->engine_mask = BIT(0);
@@ -197,7 +192,6 @@ struct drm_i915_private *mock_gem_device(void)
goto err_context;
intel_engines_driver_register(i915);
- mutex_unlock(>drm.struct_mutex);
WARN_ON(i915_gemfs_init(i915));
@@ -208,7 +202,6 @@ struct drm_i915_private *mock_gem_device(void)
err_engine:
mock_engine_free(i915->engine[RCS0]);
err_unlock:
- mutex_unlock(>drm.struct_mutex);
intel_timelines_fini(i915);
destroy_workqueue(i915->wq);
err_drv:
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/20] drm/i915: Move request runtime management onto gt
Requests are run from the gt and are tided into the gt runtime power
management, so pull the runtime request management under gt/
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 4 +-
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 28 +---
.../drm/i915/gem/selftests/i915_gem_context.c | 5 +-
.../drm/i915/gem/selftests/i915_gem_mman.c| 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 2 +
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 5 +-
drivers/gpu/drm/i915/gt/intel_gt_requests.c | 123 ++
drivers/gpu/drm/i915/gt/intel_gt_requests.h | 24
drivers/gpu/drm/i915/gt/intel_gt_types.h | 11 ++
drivers/gpu/drm/i915/gt/selftest_timeline.c | 8 +-
drivers/gpu/drm/i915/i915_debugfs.c | 17 +--
drivers/gpu/drm/i915/i915_drv.h | 10 --
drivers/gpu/drm/i915/i915_gem.c | 17 ---
drivers/gpu/drm/i915/i915_gem_evict.c | 14 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +-
drivers/gpu/drm/i915/i915_request.c | 64 +
drivers/gpu/drm/i915/i915_request.h | 7 +-
.../gpu/drm/i915/selftests/igt_flush_test.c | 9 +-
.../gpu/drm/i915/selftests/igt_live_test.c| 5 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 10 +-
21 files changed, 213 insertions(+), 158 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_requests.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_requests.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d2b53b5add81..06e1876d0250 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -83,6 +83,7 @@ gt-y += \
gt/intel_gt_irq.o \
gt/intel_gt_pm.o \
gt/intel_gt_pm_irq.o \
+ gt/intel_gt_requests.o \
gt/intel_hangcheck.o \
gt/intel_lrc.o \
gt/intel_rc6.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 45bbd22c14f1..fd4122d8c0a9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -8,6 +8,7 @@
#include
#include "gt/intel_gt.h"
+#include "gt/intel_gt_requests.h"
#include "i915_drv.h"
#include "i915_gem_gtt.h"
@@ -424,6 +425,7 @@ void i915_gem_object_release_mmap(struct
drm_i915_gem_object *obj)
static int create_mmap_offset(struct drm_i915_gem_object *obj)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct intel_gt *gt = >gt;
int err;
err = drm_gem_create_mmap_offset(>base);
@@ -431,7 +433,7 @@ static int create_mmap_offset(struct drm_i915_gem_object
*obj)
return 0;
/* Attempt to reap some mmap space from dead objects */
- err = i915_retire_requests_timeout(i915, MAX_SCHEDULE_TIMEOUT);
+ err = intel_gt_retire_requests_timeout(gt, MAX_SCHEDULE_TIMEOUT);
if (err)
return err;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 90b211257f2d..9194d8464bf7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -7,31 +7,18 @@
#include "gem/i915_gem_pm.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
+#include "gt/intel_gt_requests.h"
#include "i915_drv.h"
#include "i915_globals.h"
static void i915_gem_park(struct drm_i915_private *i915)
{
- cancel_delayed_work(>gem.retire_work);
-
i915_vma_parked(i915);
i915_globals_park();
}
-static void retire_work_handler(struct work_struct *work)
-{
- struct drm_i915_private *i915 =
- container_of(work, typeof(*i915), gem.retire_work.work);
-
- i915_retire_requests(i915);
-
- queue_delayed_work(i915->wq,
- >gem.retire_work,
- round_jiffies_up_relative(HZ));
-}
-
static int pm_notifier(struct notifier_block *nb,
unsigned long action,
void *data)
@@ -42,9 +29,6 @@ static int pm_notifier(struct notifier_block *nb,
switch (action) {
case INTEL_GT_UNPARK:
i915_globals_unpark();
- queue_delayed_work(i915->wq,
- >gem.retire_work,
- round_jiffies_up_relative(HZ));
break;
case INTEL_GT_PARK:
@@ -59,7 +43,7 @@ static bool switch_to_kernel_context_sync(struct intel_gt *gt)
{
bool result = !intel_gt_is_wedged(gt);
- if (i915_gem_wait_for_idle(gt->i915, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
+ if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
/* XXX hide warning from gem_eio */
if (i915_modparams.reset) {
dev_err(gt->i915->drm.dev,
@@ -122,14 +106,12 @@ void
[Intel-gfx] [PATCH 14/20] drm/i915: Move context management under GEM
Keep track of the GEM contexts underneath i915->gem.contexts and assign
them their own lock for the purposes of list management.
v2: Focus on lock tracking; ctx->vm is protected by ctx->mutex
v3: Correct split with removal of logical HW ID
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 177 +-
drivers/gpu/drm/i915/gem/i915_gem_context.h | 27 ++-
.../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 3 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 36 ++--
.../drm/i915/gem/selftests/i915_gem_context.c | 168 -
.../gpu/drm/i915/gem/selftests/mock_context.c | 7 +-
drivers/gpu/drm/i915/gt/intel_context.c | 10 +-
drivers/gpu/drm/i915/gt/selftest_context.c| 24 +--
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 39 ++--
drivers/gpu/drm/i915/gt/selftest_lrc.c| 6 +-
.../gpu/drm/i915/gt/selftest_workarounds.c| 22 ++-
drivers/gpu/drm/i915/gvt/scheduler.c | 24 +--
drivers/gpu/drm/i915/i915_debugfs.c | 50 +++--
drivers/gpu/drm/i915/i915_drv.c | 2 -
drivers/gpu/drm/i915/i915_drv.h | 15 +-
drivers/gpu/drm/i915/i915_gem.c | 10 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +-
drivers/gpu/drm/i915/i915_perf.c | 24 ++-
drivers/gpu/drm/i915/i915_sysfs.c | 43 ++---
drivers/gpu/drm/i915/i915_trace.h | 2 +-
drivers/gpu/drm/i915/selftests/i915_gem.c | 8 -
.../gpu/drm/i915/selftests/i915_gem_evict.c | 3 -
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 15 +-
drivers/gpu/drm/i915/selftests/i915_request.c | 12 +-
drivers/gpu/drm/i915/selftests/i915_vma.c | 7 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 6 +-
28 files changed, 394 insertions(+), 354 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index cd4f327b23bd..5d8221c7ba83 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -218,9 +218,12 @@ static struct i915_gem_engines *default_engines(struct
i915_gem_context *ctx)
static void i915_gem_context_free(struct i915_gem_context *ctx)
{
- lockdep_assert_held(>i915->drm.struct_mutex);
GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
+ spin_lock(>i915->gem.contexts.lock);
+ list_del(>link);
+ spin_unlock(>i915->gem.contexts.lock);
+
free_engines(rcu_access_pointer(ctx->engines));
mutex_destroy(>engines_mutex);
@@ -230,67 +233,54 @@ static void i915_gem_context_free(struct i915_gem_context
*ctx)
kfree(ctx->name);
put_pid(ctx->pid);
- list_del(>link);
mutex_destroy(>mutex);
kfree_rcu(ctx, rcu);
}
-static void contexts_free(struct drm_i915_private *i915)
+static void contexts_free_all(struct llist_node *list)
{
- struct llist_node *freed = llist_del_all(>contexts.free_list);
struct i915_gem_context *ctx, *cn;
- lockdep_assert_held(>drm.struct_mutex);
-
- llist_for_each_entry_safe(ctx, cn, freed, free_link)
+ llist_for_each_entry_safe(ctx, cn, list, free_link)
i915_gem_context_free(ctx);
}
-static void contexts_free_first(struct drm_i915_private *i915)
+static void contexts_flush_free(struct i915_gem_contexts *gc)
{
- struct i915_gem_context *ctx;
- struct llist_node *freed;
-
- lockdep_assert_held(>drm.struct_mutex);
-
- freed = llist_del_first(>contexts.free_list);
- if (!freed)
- return;
-
- ctx = container_of(freed, typeof(*ctx), free_link);
- i915_gem_context_free(ctx);
+ contexts_free_all(llist_del_all(>free_list));
}
static void contexts_free_worker(struct work_struct *work)
{
- struct drm_i915_private *i915 =
- container_of(work, typeof(*i915), contexts.free_work);
+ struct i915_gem_contexts *gc =
+ container_of(work, typeof(*gc), free_work);
- mutex_lock(>drm.struct_mutex);
- contexts_free(i915);
- mutex_unlock(>drm.struct_mutex);
+ contexts_flush_free(gc);
}
void i915_gem_context_release(struct kref *ref)
{
struct i915_gem_context *ctx = container_of(ref, typeof(*ctx), ref);
- struct drm_i915_private *i915 = ctx->i915;
+ struct i915_gem_contexts *gc = >i915->gem.contexts;
trace_i915_context_free(ctx);
- if (llist_add(>free_link, >contexts.free_list))
- queue_work(i915->wq, >contexts.free_work);
+ if (llist_add(>free_link, >free_list))
+ schedule_work(>free_work);
}
static void context_close(struct i915_gem_context *ctx)
{
- i915_gem_context_set_closed(ctx);
+ struct i915_address_space *vm;
- if (ctx->vm)
-
