This sample driver creates mdev device that simulate virtio net device
over virtio mdev transport. The device is implemented through vringh
and workqueue. A device specific dma ops is to make sure HVA is used
directly as the IOVA. This should be sufficient for kernel virtio
driver to work.
Only 'v
This patch introduces a new mdev transport for virtio. This is used to
use kernel virtio driver to drive the mediated device that is capable
of populating virtqueue directly.
A new virtio-mdev driver will be registered to the mdev bus, when a
new virtio-mdev device is probed, it will register the
This patch implements basic support for mdev driver that supports
virtio transport for kernel virtio driver.
Signed-off-by: Jason Wang
---
drivers/vfio/mdev/mdev_core.c| 20
drivers/vfio/mdev/mdev_private.h | 2 +
include/linux/mdev.h | 6 ++
include/linux/virtio_mdev_o
Currently, except for the create and remove, the rest of
mdev_parent_ops is designed for vfio-mdev driver only and may not help
for kernel mdev driver. With the help of class id, this patch
introduces device specific callbacks inside mdev_device
structure. This allows different set of callback to b
Add support to parse mdev class id table.
Reviewed-by: Parav Pandit
Signed-off-by: Jason Wang
---
drivers/vfio/mdev/vfio_mdev.c | 2 ++
scripts/mod/devicetable-offsets.c | 3 +++
scripts/mod/file2alias.c | 11 +++
3 files changed, 16 insertions(+)
diff --git a/drivers/vf
Mdev bus only supports vfio driver right now, so it doesn't implement
match method. But in the future, we may add drivers other than vfio,
the first driver could be virtio-mdev. This means we need to add
device class id support in bus match method to pair the mdev device
and mdev driver correctly.
Hi all:
There are hardwares that can do virtio datapath offloading while
having its own control path. This path tries to implement a mdev based
unified API to support using kernel virtio driver to drive those
devices. This is done by introducing a new mdev transport for virtio
(virtio_mdev) and re
On Tue, 29 Oct 2019, Daniele Ceraolo Spurio
wrote:
> On 10/29/19 2:23 AM, Jani Nikula wrote:
>> On Wed, 07 Aug 2019, Daniele Ceraolo Spurio
>> wrote:
>>> I've been trying to identify MMIO ranges to clearly define what belongs
>>> to display_uncore to do a check on access, but there are lots of
== Series Details ==
Series: drm/i915: Nuke 'mode' argument to intel_get_load_detect_pipe()
URL : https://patchwork.freedesktop.org/series/68717/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7211_full -> Patchwork_15050_full
===
== Series Details ==
Series: series starting with [RFC,1/2] drm/i915: add display uncore helpers
URL : https://patchwork.freedesktop.org/series/68713/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7211_full -> Patchwork_15049_full
==
== Series Details ==
Series: tgl: MST support
URL : https://patchwork.freedesktop.org/series/68749/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7221 -> Patchwork_15066
Summary
---
**SUCCESS**
No regressions foun
== Series Details ==
Series: drm/i915/gt: Defer engine registration until fully initialised
URL : https://patchwork.freedesktop.org/series/68746/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7221 -> Patchwork_15065
Summary
== Series Details ==
Series: tgl: MST support
URL : https://patchwork.freedesktop.org/series/68749/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Add for_each_new_intel_connector_in_state()
Okay!
Commit: drm/i915: add wrappers to get intel
== Series Details ==
Series: tgl: MST support
URL : https://patchwork.freedesktop.org/series/68749/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
dd2dcb37cff0 drm/i915: Add for_each_new_intel_connector_in_state()
-:26: ERROR:COMPLEX_MACRO: Macros with complex values should be e
== Series Details ==
Series: pcm_lock deadlock
URL : https://patchwork.freedesktop.org/series/68742/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7221 -> Patchwork_15064
Summary
---
**FAILURE**
Serious unknown ch
== Series Details ==
Series: pcm_lock deadlock
URL : https://patchwork.freedesktop.org/series/68742/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d52d1e16a583 pcm_lock deadlock
-:21: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 char
== Series Details ==
Series: drm/i915/dp: Do not switch aux to TBT mode for non-TC ports (rev2)
URL : https://patchwork.freedesktop.org/series/68691/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7221 -> Patchwork_15062
Sum
== Series Details ==
Series: drm/i915/gem: Make context persistence optional (rev3)
URL : https://patchwork.freedesktop.org/series/68515/
State : failure
== Summary ==
Applying: drm/i915/gem: Make context persistence optional
Using index info to reconstruct a base tree...
M drivers/gpu/d
== Series Details ==
Series: drm/i915/lmem: add the fake lmem region
URL : https://patchwork.freedesktop.org/series/68733/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7221 -> Patchwork_15061
Summary
---
**FAILURE**
== Series Details ==
Series: drm/i915/lmem: add the fake lmem region
URL : https://patchwork.freedesktop.org/series/68733/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9fd60b3f26c7 drm/i915/lmem: add the fake lmem region
-:93: CHECK:PARENTHESIS_ALIGNMENT: Alignment should matc
Just avoid the additional read in case DP_TP_CTL is enabled:
read it once and save the value.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 33
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/in
For MST on Tiger Lake there are different moments when we need to
configure the transcoder clock select. For the first link this is in step
7.a of the spec, before training the link. For additional streams this
should be done as part of step 8.b after programming receiver VC Payload
ID.
Bspec: 49
Wrap drm_atomic_get_old_connector_state so we can get the
intel_digital_connector_state and make it easier to migrate to intel
types.
Signed-off-by: Lucas De Marchi
---
.../gpu/drm/i915/display/intel_display_types.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/
Additional code to support more than one display when using MST with
TGL. It's still WIP! From what I could check on my tests we are correctly
tracking the master transcoder and setting it accordingly on
TRANS_DDI_FUNC_CTL and DP_TP_CTL.
I tried also setting MST mode on the slave's DP_TP_CTL. I co
From: José Roberto de Souza
The same macro as for_each_new_connector_in_state() but it uses
intel/i915 types instead of the drm ones.
Signed-off-by: José Roberto de Souza
Reviewed-by: Mika Kahola
Reviewed-by: Lucas De Marchi
Signed-off-by: Lucas De Marchi
Link:
https://patchwork.freedesktop
From: José Roberto de Souza
On TGL the blending of all the streams have moved from DDI to
transcoder, so now every transcoder working over the same MST port must
send its stream to a master transcoder and master will send to DDI
respecting the time slots.
So here it is picking the lowest pipe/tr
== Series Details ==
Series: series starting with [1/2] drm/i915/tgl: Add SFC instdone to error state
URL : https://patchwork.freedesktop.org/series/68732/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7220 -> Patchwork_15060
===
== Series Details ==
Series: drm/i915: Conclude load -> probe naming convention switch (rev2)
URL : https://patchwork.freedesktop.org/series/67454/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7209_full -> Patchwork_15046_full
=
== Series Details ==
Series: drm/i915/tgl: add support to one DP-MST stream (rev3)
URL : https://patchwork.freedesktop.org/series/68671/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7219 -> Patchwork_15059
Summary
---
== Series Details ==
Series: drm/i915: Avoid HPD poll detect triggering a new detect cycle (rev2)
URL : https://patchwork.freedesktop.org/series/68644/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7205_full -> Patchwork_15031_full
=
+Jason
Maybe Jason and/or others have some thoughts on the following? Given the
detailed description of the clear color struct, it seems like we'll have to
define a new modifier if the struct fields change in a future generation.
On negative is that we might have to make new modifiers that provi
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev6)
URL : https://patchwork.freedesktop.org/series/68028/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
AR dri
Only add the engine to the available set of uabi engines once it has
been fully initialised and we know we want it in the public set.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Michał Wajdeczko
Cc: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 ++-
1 file changed, 2 ins
== Series Details ==
Series: drm/i915/display: only include intel_dp_link_training.h where needed
(rev2)
URL : https://patchwork.freedesktop.org/series/68711/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7218 -> Patchwork_15057
===
topic/mst-suspend-resume-reprobe-2019-10-29-2:
UAPI Changes:
Cross-subsystem Changes:
Core Changes:
* Handle UP requests asynchronously in the DP MST helpers, fixing
hotplug notifications and allowing us to implement suspend/resume
reprobing
* Add basic suspend/resume reprobing to the DP MST
On 10/29/19 2:51 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-10-29 21:46:46)
On 10/29/19 2:58 AM, Matthew Auld wrote:
Since we have no way access it from the CPU. For such cases just
fallback to internal objects.
Since the problem is not limited to rings but it applies t
Quoting Daniele Ceraolo Spurio (2019-10-29 21:46:46)
>
>
> On 10/29/19 2:58 AM, Matthew Auld wrote:
> > Since we have no way access it from the CPU. For such cases just
> > fallback to internal objects.
> >
>
> Since the problem is not limited to rings but it applies to all stolen
> objects, w
On 10/29/19 2:44 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-10-29 21:23:16)
On 10/29/19 2:58 AM, Matthew Auld wrote:
From: Daniele Ceraolo Spurio
We can't fence anything without aperture.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
Signed-off-b
== Series Details ==
Series: drm/i915/display: only include intel_dp_link_training.h where needed
(rev2)
URL : https://patchwork.freedesktop.org/series/68711/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
71fa50b34b3d drm/i915/display: only include intel_dp_link_training.h whe
On 10/29/19 2:58 AM, Matthew Auld wrote:
Since we have no way access it from the CPU. For such cases just
fallback to internal objects.
Since the problem is not limited to rings but it applies to all stolen
objects, wouldn't it be better to just skip the stolen initialization or
return an
== Series Details ==
Series: series starting with [1/4] drm/i915/bios: use a flag for vbt hdmi level
shift presence
URL : https://patchwork.freedesktop.org/series/68729/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7218 -> Patchwork_15056
Quoting Daniele Ceraolo Spurio (2019-10-29 21:23:16)
>
>
> On 10/29/19 2:58 AM, Matthew Auld wrote:
> > From: Daniele Ceraolo Spurio
> >
> > We can't fence anything without aperture.
> >
> > Signed-off-by: Daniele Ceraolo Spurio
> > Signed-off-by: Stuart Summers
> > Signed-off-by: Matthew Au
On 10/29/19 2:58 AM, Matthew Auld wrote:
From: Daniele Ceraolo Spurio
We can't fence anything without aperture.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 --
1 file changed, 4 in
On 10/29/19 3:51 AM, Jani Nikula wrote:
Add convenience helpers for the most common uncore operations with
struct drm_i915_private * as context rather than struct intel_uncore *.
The goal is to replace all instances of I915_READ(),
I915_POSTING_READ(), and I915_WRITE() in display/ with these,
On 10/29/19 2:23 AM, Jani Nikula wrote:
On Wed, 07 Aug 2019, Daniele Ceraolo Spurio
wrote:
I've been trying to identify MMIO ranges to clearly define what belongs
to display_uncore to do a check on access, but there are lots of
exceptions and differences across gens (with a few more coming w
== Series Details ==
Series: series starting with [1/7] drm/i915: define i915_ggtt_has_aperture
URL : https://patchwork.freedesktop.org/series/68705/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7208_full -> Patchwork_15045_full
===
> From: Wajdeczko, Michal
> Sent: Tuesday, October 29, 2019 5:33 AM
> To: intel-gfx@lists.freedesktop.org; Hiatt, Don
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/guc: Skip suspend/resume GuC action
> on platforms w/o GuC submission
>
> On Mon, 28 Oct 2019 22:25:27 +0100, wrote:
>
> > From: Don
On Tue, 29 Oct 2019 20:10:50 +0100,
Ville Syrjälä wrote:
>
> Hi Takashi,
>
> I just got this deadlock when I tried to modprobe i915 on an ELK:
>
> [ 203.716416]
> [ 203.716417] WARNING: possible recursive locking detected
> [ 203.716418] 5.4.0-rc5-
Our existing behaviour is to allow contexts and their GPU requests to
persist past the point of closure until the requests are complete. This
allows clients to operate in a 'fire-and-forget' manner where they can
setup a rendering pipeline and hand it over to the display server and
immediately exit
== Series Details ==
Series: series starting with [1/5] drm/i915: Use drm_rect to simplify plane
{crtc, src}_{x, y, w, h} printing
URL : https://patchwork.freedesktop.org/series/68728/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7216 -> Patchwork_15055
=
Reviewed-by: Juha-Pekka Heikkila
On 8.10.2019 19.14, Ville Syrjala wrote:
From: Ville Syrjälä
SNB-BDW support 10:10:10 formats on the sprite planes. Let's expose
them.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 16
1 file changed, 16 i
On Tue, Oct 29, 2019 at 12:39:47PM +0200, Jani Nikula wrote:
> The intel_dp_link_training.h include has no need or place in
> intel_display.h. Include it in intel_display.c instead.
>
> Cc:
>
> Cc: Manasi Navare
> Fixes: eadf6f9170d5 ("drm/i915/display/icl: Enable master-slaves in trans
> port
Reviewed-by: Juha-Pekka Heikkila
On 8.10.2019 19.14, Ville Syrjala wrote:
From: Ville Syrjälä
ICL+ again supports alpha blending with 10bpc pixel formats.
Expose them.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++
1 file changed, 6 insertions(+)
== Series Details ==
Series: series starting with [1/5] drm/i915: Use drm_rect to simplify plane
{crtc, src}_{x, y, w, h} printing
URL : https://patchwork.freedesktop.org/series/68728/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
54b724ada78c drm/i915: Use drm_rect to simplif
On Tue, Oct 29, 2019 at 10:58:52AM -0700, Matt Roper wrote:
> On Mon, Oct 28, 2019 at 01:02:09AM +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: DP AUX updates (rev3)
> > URL : https://patchwork.freedesktop.org/series/68590/
> > State : success
> >
> > == Summary ==
> >
> > CI
On Sun, 2019-10-27 at 20:42 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/5] drm/i915: Add two spaces before
> the SKL_DFSM registers
> URL : https://patchwork.freedesktop.org/series/68594/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from C
On Tue, Oct 29, 2019 at 10:31:02AM -0700, Matt Roper wrote:
We're seeing some failures where an aux transaction still shows as
'busy' well after the timeout limit that the hardware is supposed to
enforce. Improve the error message so that we can see exactly which aux
channel this error happened
== Series Details ==
Series: drm/i915: Stop frobbing crtc->base.mode
URL : https://patchwork.freedesktop.org/series/68725/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7215 -> Patchwork_15054
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915/gt: Make timeslice duration configurable
URL : https://patchwork.freedesktop.org/series/68701/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7208_full -> Patchwork_15044_full
Summary
--
Hi Takashi,
I just got this deadlock when I tried to modprobe i915 on an ELK:
[ 203.716416]
[ 203.716417] WARNING: possible recursive locking detected
[ 203.716418] 5.4.0-rc5-elk+ #206 Not tainted
[ 203.716419] -
On Tue, Oct 29, 2019 at 08:22:18AM +0100, Maarten Lankhorst wrote:
> Use this in all the places where we try to acquire planes after the planes
> atomic_check().
>
> In case of intel_modeset_all_pipes() this is not yet done after atomic_check,
> but seems like it will be in the future. To add some
On Tue, Oct 29, 2019 at 08:22:29AM +0100, Maarten Lankhorst wrote:
> Splitting plane state is easier than splitting crtc_state,
> before plane check we copy the drm properties to hw so we can
> do the same in bigjoiner later on.
>
> We copy the state after we did all the modeset handling, but fort
On Fri, Oct 25, 2019 at 05:13:19PM -0700, José Roberto de Souza wrote:
> The next patches are going to touch this registers so here already
> fixing it for older registers and make it consistent with most of
> the other registers in this file.
>
> Cc: Ramalingam C
LGTM,
Reviewed-by: Radhakrishna
== Series Details ==
Series: series starting with [1/5] dma-buf: add dynamic DMA-buf handling v14
URL : https://patchwork.freedesktop.org/series/68724/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7213 -> Patchwork_15053
S
== Series Details ==
Series: drm/i915/perf: ensure selftests select valid format
URL : https://patchwork.freedesktop.org/series/68723/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7213 -> Patchwork_15052
Summary
---
Quoting Jason Ekstrand (2019-10-29 16:19:09)
>
>
> On Fri, Oct 25, 2019 at 4:29 PM Chris Wilson wrote:
>
> Quoting Jason Ekstrand (2019-10-25 19:22:04)
> > On Thu, Oct 24, 2019 at 6:40 AM Chris Wilson
> wrote:
> >
> > Our existing behaviour is to allow contexts and thei
On Mon, Oct 28, 2019 at 07:57:12AM -0700, Matt Roper wrote:
On Fri, Oct 25, 2019 at 04:13:40PM -0700, Lucas De Marchi wrote:
On Fri, Oct 25, 2019 at 04:06:21PM -0700, Matt Roper wrote:
> TGL's extra ports also bring extra AUX channels.
>
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/
On Mon, Oct 28, 2019 at 01:02:09AM +, Patchwork wrote:
> == Series Details ==
>
> Series: DP AUX updates (rev3)
> URL : https://patchwork.freedesktop.org/series/68590/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7191_full -> Patchwork_14998_full
> =
== Series Details ==
Series: series starting with [1/5] dma-buf: add dynamic DMA-buf handling v14
URL : https://patchwork.freedesktop.org/series/68724/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f64ecc4c07e0 dma-buf: add dynamic DMA-buf handling v14
-:10: WARNING:COMMIT_LOG_
We're seeing some failures where an aux transaction still shows as
'busy' well after the timeout limit that the hardware is supposed to
enforce. Improve the error message so that we can see exactly which aux
channel this error happened on and what the status bits were during this
case that isn't s
On Tue, Oct 29, 2019 at 06:12:26PM +0200, Stanislav Lisovskiy wrote:
> According to BSpec 53998, we should try to
> restrict qgv points, which can't provide
> enough bandwidth for desired display configuration.
>
> Currently we are just comparing against all of
> those and take minimum(worst case)
== Series Details ==
Series: drm/dp: Increase link status size
URL : https://patchwork.freedesktop.org/series/68721/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7211 -> Patchwork_15051
Summary
---
**SUCCESS**
No
Intended for upstream testing so that we can still exercise the LMEM
plumbing and !i915_ggtt_has_aperture paths. Smoke tested on Skull Canyon
device. This works by allocating an intel_memory_region for a reserved
portion of system memory, which we treat like LMEM. For the LMEMBAR we
steal the apert
Quoting Mika Kuoppala (2019-10-29 16:38:41)
> This has been asked from us already. Prepare for the next
> time.
>
> Signed-off-by: Mika Kuoppala
Looks fine, but I do hear you volunteering yourself to do the complete
mmio snapshot :)
Let's assume I actually looked up the register values...
Revie
Newer VBT versions will add an alternate way to read panel DTD
information, so let's split parsing of the general panel information
from the timing data in preparation.
Cc: Jani Nikula
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bios.c | 27 +++
1 file c
VBT revision 229 adds a new "Generic DTD" block 58 and deprecates the
old LFP panel mode data in block 42. Let's start parsing this block to
fill in the panel fixed mode on devices with a >=229 VBT.
v2:
* Update according to the recent updates:
- DTD size is now 16 bits instead of 24
- p
On debugging media workload hangs, sfc instdone
might prove useful in future. Be prepared.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gpu_error.c | 15 +++
drivers/gpu/drm/i915/i915_gpu_error.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 3 +++
3 files changed, 1
This has been asked from us already. Prepare for the next
time.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gpu_error.c | 4
drivers/gpu/drm/i915/i915_gpu_error.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
3 files changed, 6 insertions(+)
diff --git a/drivers/gpu/dr
On Fri, Oct 25, 2019 at 4:29 PM Chris Wilson
wrote:
> Quoting Jason Ekstrand (2019-10-25 19:22:04)
> > On Thu, Oct 24, 2019 at 6:40 AM Chris Wilson
> wrote:
> >
> > Our existing behaviour is to allow contexts and their GPU requests to
> > persist past the point of closure until the reque
Quoting Mika Kuoppala (2019-10-29 16:11:58)
> Chris Wilson writes:
>
> > Execlists uses a scheduling quantum (a timeslice) to alternate execution
> > between ready-to-run contexts of equal priority. This ensures that all
> > users (though only if they of equal importance) have the opportunity to
Currently intel_can_enable_sagv function contains
a mix of workarounds for different platforms
some of them are not valid for gens >= 11 already,
so lets split it into separate functions.
v2:
- Rework watermark calculation algorithm to
attempt to calculate Level 0 watermark
with ad
For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
v2: Fixed wrong PCode reply mask, removed hardcoded
values.
v3: Forbid si
Chris Wilson writes:
> Execlists uses a scheduling quantum (a timeslice) to alternate execution
> between ready-to-run contexts of equal priority. This ensures that all
> users (though only if they of equal importance) have the opportunity to
> run and prevents livelocks where contexts may have i
== Series Details ==
Series: drm/i915: Nuke 'mode' argument to intel_get_load_detect_pipe()
URL : https://patchwork.freedesktop.org/series/68717/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7211 -> Patchwork_15050
Summary
For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can
Currently intel_can_enable_sagv function contains
a mix of workarounds for different platforms
some of them are not valid for gens >= 11 already,
so lets split it into separate functions.
v2:
- Rework watermark calculation algorithm to
attempt to calculate Level 0 watermark
with ad
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
v2: Fixed wrong PCode reply mask, removed hardcoded
values.
v3: Forbid si
== Series Details ==
Series: drm/i915/blt: fixup block_size rounding (rev3)
URL : https://patchwork.freedesktop.org/series/68670/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7206_full -> Patchwork_15039_full
Summary
-
== Series Details ==
Series: series starting with [RFC,1/2] drm/i915: add display uncore helpers
URL : https://patchwork.freedesktop.org/series/68713/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7211 -> Patchwork_15049
Su
On Tue, Oct 29, 2019 at 05:39:28PM +0200, Jani Nikula wrote:
> Bring DSI closer to other ports, and facilitate easier lookup of more
> child device specific data in a unified manner in the future. This may
> cause problems if there are any VBTs in the wild with colliding child
> device ports. In pr
On Tue, Oct 29, 2019 at 08:22:28AM +0100, Maarten Lankhorst wrote:
> Split up plane_state->base to uapi. This is done using the following patch,
> ran after the previous commit that splits out any hw references:
>
> @@
> struct intel_plane_state *T;
> identifier x;
> @@
> -T->base.x
> +T->uapi.x
>
Quoting Lionel Landwerlin (2019-10-29 14:28:26)
> Gen12 only support a single report format :
> I915_OA_FORMAT_A32u40_A4u32_B8_C8
>
> Signed-off-by: Lionel Landwerlin
> Fixes: 00a7f0d7155c ("drm/i915/tgl: Add perf support on TGL")
> ---
> drivers/gpu/drm/i915/selftests/i915_perf.c | 3 ++-
> 1 f
Start parsing child devices to the DDI ports array also on VLV. The
benefit is being able to unify DSI handling between VLV and ICL DSI in
the future.
There are some subtle changes where we start using the VBT more for VLV,
which may cause problems in case of bad VBTs:
- Start using max TMDS cloc
Make DSI initialization similar to other encoders by calling init on
each possible port. This takes a step towards being able to have two
separate DSI displays, though currently this would likely break if there
were two DSI child devices present in the VBT.
Cc: Ville Syrjälä
Signed-off-by: Jani N
The pre-initialized magic value is a bit silly, switch to a flag
instead. While at it, clean up the validity checks. No functional
changes apart from the added checks.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 10 +-
drivers/gpu/drm/i91
Bring DSI closer to other ports, and facilitate easier lookup of more
child device specific data in a unified manner in the future. This may
cause problems if there are any VBTs in the wild with colliding child
device ports. In practice those should have surfaced already by way of
trying to initial
On Tue, Oct 29, 2019 at 08:22:27AM +0100, Maarten Lankhorst wrote:
> Split up plane_state->base to hw. This is done using the following patch:
>
> @@
> struct intel_plane_state *T;
> identifier x =~
> "^(crtc|fb|alpha|pixel_blend_mode|rotation|color_encoding|color_range)$";
> @@
> -T->base.x
> +T
On Tue, Oct 29, 2019 at 01:35:57PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Shankar, Uma
> >Sent: Tuesday, October 29, 2019 6:38 PM
> >To: Ville Syrjala ;
> >intel-gfx@lists.freedesktop.org
> >Subject: RE: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
>
On Tue, Oct 29, 2019 at 03:32:41PM +0200, Jani Nikula wrote:
> On Tue, 29 Oct 2019, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > The current link status contains bytes 0x202 through 0x207, but we also
> > want to make sure to include the DP_ADJUST_REQUEST_POST_CURSOR2 (0x20c)
> > so tha
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