[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dsb: Pre allocate and late cleanup of cmd buffer.
== Series Details == Series: drm/i915/dsb: Pre allocate and late cleanup of cmd buffer. URL : https://patchwork.freedesktop.org/series/72729/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7838_full -> Patchwork_16316_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16316_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16316_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16316_full: ### IGT changes ### Possible regressions * igt@gem_exec_schedule@deep-bsd: - shard-skl: [PASS][1] -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-skl5/igt@gem_exec_sched...@deep-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16316/shard-skl10/igt@gem_exec_sched...@deep-bsd.html Known issues Here are the changes found in Patchwork_16316_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@vcs1-queued: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-iclb4/igt@gem_ctx_persiste...@vcs1-queued.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16316/shard-iclb8/igt@gem_ctx_persiste...@vcs1-queued.html * igt@gem_exec_balancer@hang: - shard-tglb: [PASS][5] -> [TIMEOUT][6] ([fdo#112271]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-tglb3/igt@gem_exec_balan...@hang.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16316/shard-tglb7/igt@gem_exec_balan...@hang.html * igt@gem_exec_schedule@fifo-bsd1: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +11 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-iclb4/igt@gem_exec_sched...@fifo-bsd1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16316/shard-iclb3/igt@gem_exec_sched...@fifo-bsd1.html * igt@gem_exec_schedule@pi-userfault-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([i915#677]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-iclb3/igt@gem_exec_sched...@pi-userfault-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16316/shard-iclb4/igt@gem_exec_sched...@pi-userfault-bsd.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-iclb6/igt@gem_exec_sched...@preemptive-hang-bsd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16316/shard-iclb2/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@gem_partial_pwrite_pread@reads: - shard-hsw: [PASS][13] -> [FAIL][14] ([i915#694]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-hsw4/igt@gem_partial_pwrite_pr...@reads.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16316/shard-hsw5/igt@gem_partial_pwrite_pr...@reads.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-apl: [PASS][15] -> [FAIL][16] ([i915#644]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-apl8/igt@gem_pp...@flink-and-close-vma-leak.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16316/shard-apl7/igt@gem_pp...@flink-and-close-vma-leak.html * igt@i915_selftest@live_blt: - shard-hsw: [PASS][17] -> [DMESG-FAIL][18] ([i915#770]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-hsw1/igt@i915_selftest@live_blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16316/shard-hsw8/igt@i915_selftest@live_blt.html * igt@i915_selftest@mock_sanitycheck: - shard-tglb: [PASS][19] -> [TIMEOUT][20] ([fdo#112126]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-tglb4/igt@i915_selftest@mock_sanitycheck.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16316/shard-tglb2/igt@i915_selftest@mock_sanitycheck.html * igt@kms_color@pipe-a-ctm-0-25: - shard-skl: [PASS][21] -> [DMESG-WARN][22] ([i915#109]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-skl4/igt@kms_co...@pipe-a-ctm-0-25.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16316/shard-skl7/igt@kms_co...@pipe-a-ctm-0-25.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt: - shard-tglb: [PASS][23] -> [SKIP][24] ([i915#668]) [23]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore
== Series Details == Series: drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore URL : https://patchwork.freedesktop.org/series/72724/ State : success == Summary == CI Bug Log - changes from CI_DRM_7838_full -> Patchwork_16315_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_16315_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@vcs1-queued: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-iclb4/igt@gem_ctx_persiste...@vcs1-queued.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16315/shard-iclb5/igt@gem_ctx_persiste...@vcs1-queued.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#112080]) +16 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-iclb4/igt@gem_exec_paral...@vcs1-fds.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16315/shard-iclb3/igt@gem_exec_paral...@vcs1-fds.html * igt@gem_exec_schedule@pi-common-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([i915#677]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-iclb5/igt@gem_exec_sched...@pi-common-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16315/shard-iclb2/igt@gem_exec_sched...@pi-common-bsd.html * igt@gem_exec_schedule@pi-shared-iova-bsd2: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +23 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-iclb4/igt@gem_exec_sched...@pi-shared-iova-bsd2.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16315/shard-iclb3/igt@gem_exec_sched...@pi-shared-iova-bsd2.html * igt@gem_exec_schedule@preempt-queue-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +4 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-iclb5/igt@gem_exec_sched...@preempt-queue-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16315/shard-iclb2/igt@gem_exec_sched...@preempt-queue-bsd.html * igt@gem_partial_pwrite_pread@reads-snoop: - shard-hsw: [PASS][11] -> [FAIL][12] ([i915#694]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-hsw5/igt@gem_partial_pwrite_pr...@reads-snoop.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16315/shard-hsw2/igt@gem_partial_pwrite_pr...@reads-snoop.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-apl: [PASS][13] -> [FAIL][14] ([i915#644]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-apl8/igt@gem_pp...@flink-and-close-vma-leak.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16315/shard-apl7/igt@gem_pp...@flink-and-close-vma-leak.html * igt@gem_softpin@noreloc-s3: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-kbl4/igt@gem_soft...@noreloc-s3.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16315/shard-kbl3/igt@gem_soft...@noreloc-s3.html * igt@i915_pm_dc@dc6-dpms: - shard-iclb: [PASS][17] -> [FAIL][18] ([i915#454]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-iclb4/igt@i915_pm...@dc6-dpms.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16315/shard-iclb3/igt@i915_pm...@dc6-dpms.html * igt@i915_pm_rpm@debugfs-read: - shard-skl: [PASS][19] -> [INCOMPLETE][20] ([i915#151]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-skl7/igt@i915_pm_...@debugfs-read.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16315/shard-skl7/igt@i915_pm_...@debugfs-read.html * igt@i915_selftest@live_blt: - shard-hsw: [PASS][21] -> [DMESG-FAIL][22] ([i915#563]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-hsw1/igt@i915_selftest@live_blt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16315/shard-hsw6/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_execlists: - shard-iclb: [PASS][23] -> [INCOMPLETE][24] ([i915#140]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-iclb3/igt@i915_selftest@live_execlists.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16315/shard-iclb6/igt@i915_selftest@live_execlists.html * igt@kms_flip@plain-flip-fb-recreate-interruptible: - shard-glk: [PASS][25] -> [FAIL][26] ([i915#34]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7838/shard-glk1/igt@kms_f...@plain-flip-fb-recreate-interruptible.html [26]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Skip rmw for masked registers (rev4)
== Series Details == Series: drm/i915/gt: Skip rmw for masked registers (rev4) URL : https://patchwork.freedesktop.org/series/72776/ State : success == Summary == CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16371 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16371/index.html Known issues Here are the changes found in Patchwork_16371 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][1] -> [DMESG-FAIL][2] ([i915#725]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-4770r/igt@i915_selftest@live_blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16371/fi-hsw-4770r/igt@i915_selftest@live_blt.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-j1900: [TIMEOUT][3] ([fdo#112271] / [i915#1084] / [i915#816]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16371/fi-byt-j1900/igt@gem_close_r...@basic-threads.html - fi-byt-n2820: [TIMEOUT][5] ([fdo#112271] / [i915#1084] / [i915#816]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16371/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@gem_exec_suspend@basic-s3: - fi-icl-u2: [FAIL][7] ([fdo#103375]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16371/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html * igt@gem_exec_suspend@basic-s4-devices: - fi-icl-u2: [FAIL][9] ([fdo#111550]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16371/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][11] ([i915#563]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-4770/igt@i915_selftest@live_blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16371/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_execlists: - fi-icl-y: [DMESG-FAIL][13] ([fdo#108569]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-y/igt@i915_selftest@live_execlists.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16371/fi-icl-y/igt@i915_selftest@live_execlists.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][15] ([fdo#111096] / [i915#323]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16371/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Warnings * igt@i915_pm_rpm@basic-rte: - fi-kbl-guc: [FAIL][17] ([i915#579]) -> [SKIP][18] ([fdo#109271]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-guc/igt@i915_pm_...@basic-rte.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16371/fi-kbl-guc/igt@i915_pm_...@basic-rte.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-icl-u2: [FAIL][19] ([fdo#103375]) -> [DMESG-WARN][20] ([IGT#4] / [i915#263]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16371/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [IGT#4]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/4 [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#111550]: https://bugs.freedesktop.org/show_bug.cgi?id=111550 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084 [i915#263]: https://gitlab.freedesktop.org/drm/intel/issues/263 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816 Participating hosts (47 -> 43)
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Implement Wa_1606931601 (rev4)
== Series Details == Series: drm/i915/tgl: Implement Wa_1606931601 (rev4) URL : https://patchwork.freedesktop.org/series/72433/ State : success == Summary == CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16370 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/index.html Known issues Here are the changes found in Patchwork_16370 that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@module-reload: - fi-kbl-guc: [PASS][1] -> [FAIL][2] ([i915#138]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-guc/igt@i915_pm_...@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-kbl-guc/igt@i915_pm_...@module-reload.html - fi-skl-6770hq: [PASS][3] -> [FAIL][4] ([i915#178]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-skl-6770hq/igt@i915_pm_...@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-skl-6770hq/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live_gem_contexts: - fi-hsw-peppy: [PASS][5] -> [DMESG-FAIL][6] ([i915#722]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_gtt: - fi-bxt-dsi: [PASS][7] -> [TIMEOUT][8] ([fdo#112271]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-bxt-dsi/igt@i915_selftest@live_gtt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-bxt-dsi/igt@i915_selftest@live_gtt.html - fi-icl-dsi: [PASS][9] -> [TIMEOUT][10] ([fdo#112271]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-dsi/igt@i915_selftest@live_gtt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-icl-dsi/igt@i915_selftest@live_gtt.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-j1900: [TIMEOUT][11] ([fdo#112271] / [i915#1084] / [i915#816]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-byt-j1900/igt@gem_close_r...@basic-threads.html - fi-byt-n2820: [TIMEOUT][13] ([fdo#112271] / [i915#1084] / [i915#816]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@gem_exec_suspend@basic-s3: - fi-icl-u2: [FAIL][15] ([fdo#103375]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html * igt@gem_exec_suspend@basic-s4-devices: - fi-icl-u2: [FAIL][17] ([fdo#111550]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][19] ([i915#563]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-4770/igt@i915_selftest@live_blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_execlists: - fi-icl-y: [DMESG-FAIL][21] ([fdo#108569]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-y/igt@i915_selftest@live_execlists.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-icl-y/igt@i915_selftest@live_execlists.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][23] ([fdo#111096] / [i915#323]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Warnings * igt@i915_pm_rpm@basic-rte: - fi-kbl-guc: [FAIL][25] ([i915#579]) -> [SKIP][26] ([fdo#109271]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-guc/igt@i915_pm_...@basic-rte.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-kbl-guc/igt@i915_pm_...@basic-rte.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-icl-u2: [FAIL][27] ([fdo#103375]) -> [DMESG-WARN][28] ([IGT#4] /
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Add Wa_1606054188:tgl (rev2)
== Series Details == Series: drm/i915/tgl: Add Wa_1606054188:tgl (rev2) URL : https://patchwork.freedesktop.org/series/72839/ State : success == Summary == CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16369 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16369/index.html Known issues Here are the changes found in Patchwork_16369 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-hsw-peppy: [PASS][1] -> [TIMEOUT][2] ([fdo#112271] / [i915#1084]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-peppy/igt@gem_close_r...@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16369/fi-hsw-peppy/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live_blt: - fi-ivb-3770:[PASS][3] -> [DMESG-FAIL][4] ([i915#725]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-ivb-3770/igt@i915_selftest@live_blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16369/fi-ivb-3770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gtt: - fi-kbl-7500u: [PASS][5] -> [TIMEOUT][6] ([fdo#112271]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-7500u/igt@i915_selftest@live_gtt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16369/fi-kbl-7500u/igt@i915_selftest@live_gtt.html - fi-icl-u2: [PASS][7] -> [TIMEOUT][8] ([fdo#112271]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@i915_selftest@live_gtt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16369/fi-icl-u2/igt@i915_selftest@live_gtt.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-icl-u2: [FAIL][9] ([fdo#103375]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16369/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html * igt@gem_exec_suspend@basic-s4-devices: - fi-icl-u2: [FAIL][11] ([fdo#111550]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16369/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_selftest@live_execlists: - fi-icl-y: [DMESG-FAIL][13] ([fdo#108569]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-y/igt@i915_selftest@live_execlists.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16369/fi-icl-y/igt@i915_selftest@live_execlists.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][15] ([fdo#111096] / [i915#323]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16369/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Warnings * igt@i915_pm_rpm@basic-rte: - fi-kbl-guc: [FAIL][17] ([i915#579]) -> [SKIP][18] ([fdo#109271]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-guc/igt@i915_pm_...@basic-rte.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16369/fi-kbl-guc/igt@i915_pm_...@basic-rte.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][19] ([i915#563]) -> [DMESG-FAIL][20] ([i915#553] / [i915#725]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-4770/igt@i915_selftest@live_blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16369/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-icl-u2: [FAIL][21] ([fdo#103375]) -> [DMESG-WARN][22] ([IGT#4] / [i915#263]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16369/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [IGT#4]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/4 [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#111550]: https://bugs.freedesktop.org/show_bug.cgi?id=111550 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084 [i915#263]: https://gitlab.freedesktop.org/drm/intel/issues/263 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#553]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for In order to readout DP SDPs, refactors the handling of DP SDPs
== Series Details == Series: In order to readout DP SDPs, refactors the handling of DP SDPs URL : https://patchwork.freedesktop.org/series/72853/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16368 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16368 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16368, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16368/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16368: ### IGT changes ### Possible regressions * igt@gem_exec_suspend@basic-s0: - fi-skl-6770hq: [PASS][1] -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-skl-6770hq/igt@gem_exec_susp...@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16368/fi-skl-6770hq/igt@gem_exec_susp...@basic-s0.html - fi-apl-guc: [PASS][3] -> [TIMEOUT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-apl-guc/igt@gem_exec_susp...@basic-s0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16368/fi-apl-guc/igt@gem_exec_susp...@basic-s0.html * igt@runner@aborted: - fi-whl-u: NOTRUN -> [FAIL][5] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16368/fi-whl-u/igt@run...@aborted.html Known issues Here are the changes found in Patchwork_16368 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][6] -> [DMESG-FAIL][7] ([i915#553] / [i915#725]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-4770r/igt@i915_selftest@live_blt.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16368/fi-hsw-4770r/igt@i915_selftest@live_blt.html - fi-ivb-3770:[PASS][8] -> [DMESG-FAIL][9] ([i915#770]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-ivb-3770/igt@i915_selftest@live_blt.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16368/fi-ivb-3770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-kbl-x1275: [PASS][10] -> [DMESG-FAIL][11] ([i915#943]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-x1275/igt@i915_selftest@live_gem_contexts.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16368/fi-kbl-x1275/igt@i915_selftest@live_gem_contexts.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-n2820: [TIMEOUT][12] ([fdo#112271] / [i915#1084] / [i915#816]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16368/fi-byt-n2820/igt@gem_close_r...@basic-threads.html Warnings * igt@i915_pm_rpm@basic-rte: - fi-kbl-guc: [FAIL][14] ([i915#579]) -> [SKIP][15] ([fdo#109271]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-guc/igt@i915_pm_...@basic-rte.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16368/fi-kbl-guc/igt@i915_pm_...@basic-rte.html * igt@runner@aborted: - fi-kbl-soraka: [FAIL][16] ([fdo#109383] / [fdo#111012]) -> [FAIL][17] ([i915#192] / [i915#193] / [i915#194]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-soraka/igt@run...@aborted.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16368/fi-kbl-soraka/igt@run...@aborted.html - fi-cml-s: [FAIL][18] ([fdo#111012] / [fdo#111764] / [i915#577]) -> [FAIL][19] ([i915#577]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-cml-s/igt@run...@aborted.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16368/fi-cml-s/igt@run...@aborted.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109383]: https://bugs.freedesktop.org/show_bug.cgi?id=109383 [fdo#111012]: https://bugs.freedesktop.org/show_bug.cgi?id=111012 [fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#577]: https://gitlab.freedesktop.org/drm/intel/issues/577 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Add Wa_1606054188:tgl (rev2)
== Series Details == Series: drm/i915/tgl: Add Wa_1606054188:tgl (rev2) URL : https://patchwork.freedesktop.org/series/72839/ State : warning == Summary == $ dim checkpatch origin/drm-tip e0d47ccc6c89 drm/i915/tgl: Add Wa_1606054188:tgl -:56: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #56: FILE: drivers/gpu/drm/i915/display/intel_sprite.c:2164: + if (IS_GEN(dev_priv, 12) && + plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE && total: 0 errors, 0 warnings, 1 checks, 34 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for In order to readout DP SDPs, refactors the handling of DP SDPs
== Series Details ==
Series: In order to readout DP SDPs, refactors the handling of DP SDPs
URL : https://patchwork.freedesktop.org/series/72853/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
974c950dba68 drm: add DP 1.4 VSC SDP Payload related enums
b5932d8b337a drm/i915: Add DP VSC SDP payload data to
intel_crtc_state.infoframes
fe36e97597d0 drm/i915/dp: Add compute routine for DP VSC SDP
dab670ba6466 drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP
-:40: WARNING:LONG_LINE: line over 100 characters
#40: FILE: drivers/gpu/drm/i915/display/intel_dp.c:2483:
+ crtc_state->infoframes.enable |=
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
total: 0 errors, 1 warnings, 0 checks, 33 lines checked
4d1d1328db05 drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet)
a1ee3b6d5e37 video/hdmi: Add Unpack only function for DRM infoframe
ee3cca76be12 drm/i915/dp: Read out DP SDPs (Secondary Data Packet)
-:43: ERROR:SPACING: space prohibited before that close parenthesis ')'
#43: FILE: drivers/gpu/drm/i915/display/intel_dp.c:4933:
+ if (sdp->sdp_header.HB0 != 0 )
-:96: WARNING:LINE_SPACING: Missing a blank line after declarations
#96: FILE: drivers/gpu/drm/i915/display/intel_dp.c:4986:
+ const struct dp_sdp *sdp = buffer;
+ if (size < sizeof(struct dp_sdp))
-:99: ERROR:SPACING: space prohibited before that close parenthesis ')'
#99: FILE: drivers/gpu/drm/i915/display/intel_dp.c:4989:
+ if (sdp->sdp_header.HB0 != 0 )
-:159: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#159: FILE: drivers/gpu/drm/i915/display/intel_dp.c:5049:
+
+}
total: 2 errors, 1 warnings, 1 checks, 185 lines checked
71d4541b4e2b drm/i915/dp: Add logging function for DP VSC SDP
-:181: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#181: FILE: drivers/gpu/drm/i915/display/intel_dp.c:5255:
+ dp_sdp_log("colorspace: %s\n",
+ dp_colorspace_get_name(vsc->colorspace));
-:183: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#183: FILE: drivers/gpu/drm/i915/display/intel_dp.c:5257:
+ dp_sdp_log("colorimetry: %s\n",
+ dp_colorimetry_get_name(vsc->colorspace,
vsc->colorimetry));
-:184: ERROR:SPACING: space required after that ',' (ctx:VxV)
#184: FILE: drivers/gpu/drm/i915/display/intel_dp.c:5258:
+ dp_sdp_log("bpc: %u\n",vsc->bpc);
^
-:186: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#186: FILE: drivers/gpu/drm/i915/display/intel_dp.c:5260:
+ dp_sdp_log("dynamic range: %s\n",
+ dp_dynamic_range_get_name(vsc->dynamic_range));
-:188: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#188: FILE: drivers/gpu/drm/i915/display/intel_dp.c:5262:
+ dp_sdp_log("content type: %s\n",
+ dp_content_type_get_name(vsc->content_type));
-:190: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#190: FILE: drivers/gpu/drm/i915/display/intel_dp.c:5264:
+}
+#undef dp_sdp_log
total: 1 errors, 0 warnings, 5 checks, 201 lines checked
36bad01ec45b drm/i915: Include HDMI DRM infoframe in the crtc state dump
5e7f5283440d drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state
dump
4018f46daed3 drm/i915: Include DP VSC SDP in the crtc state dump
598b9e7b6d4b drm/i915: Program DP SDPs with computed configs
ed56d2bf8bf9 drm/i915: Add state readout for DP HDR Metadata Infoframe SDP
2ca13c74b7ea drm/i915: Add state readout for DP VSC SDP
-:76: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible
side-effects?
#76: FILE: drivers/gpu/drm/i915/display/intel_display.c:13869:
+#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
+ if (!intel_compare_dp_vsc_sdp(_config->infoframes.name, \
+ _config->infoframes.name)) { \
+ pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset,
__stringify(name), \
+
_config->infoframes.name, \
+ _config->infoframes.name);
\
+ ret = false; \
+ } \
+} while (0)
-:86: CHECK:LINE_SPACING: Please don't use multiple blank lines
#86: FILE: drivers/gpu/drm/i915/display/intel_display.c:13879:
+
+
total: 0 errors, 0 warnings, 2 checks, 74 lines checked
4b64dff6dce0 drm/i915: Program DP SDPs on pipe updates
2d4bcb15a15d drm/i915: Stop sending DP SDPs on intel_ddi_post_disable_dp()
762cbeda3c0d drm/i915/dp: Add compute routine for DP PSR VSC SDP
89ecb4d12fb1 drm/i915/psr: Use new DP VSC SDP compute routine on PSR
-:13: WARNING:TYPO_SPELLING: 'defintion' may be misspelled - perhaps
'definition'?
#13:
it moves defintion of "struct intel_dp_vsc_sdp" to i915_drv.h .
total: 0 errors, 1 warnings, 0 checks, 180 lines checked
___
Intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Add support for DP 1.4 Compliance edid corruption test (rev4)
== Series Details == Series: drm: Add support for DP 1.4 Compliance edid corruption test (rev4) URL : https://patchwork.freedesktop.org/series/70530/ State : success == Summary == CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16367 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16367/index.html Known issues Here are the changes found in Patchwork_16367 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][1] -> [DMESG-FAIL][2] ([i915#553] / [i915#725]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-4770r/igt@i915_selftest@live_blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16367/fi-hsw-4770r/igt@i915_selftest@live_blt.html * igt@kms_chamelium@dp-edid-read: - fi-cml-u2: [PASS][3] -> [FAIL][4] ([i915#217] / [i915#976]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16367/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-j1900: [TIMEOUT][5] ([fdo#112271] / [i915#1084] / [i915#816]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16367/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@gem_exec_suspend@basic-s3: - fi-icl-u2: [FAIL][7] ([fdo#103375]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16367/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html * igt@gem_exec_suspend@basic-s4-devices: - fi-icl-u2: [FAIL][9] ([fdo#111550]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16367/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_selftest@live_execlists: - fi-icl-y: [DMESG-FAIL][11] ([fdo#108569]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-y/igt@i915_selftest@live_execlists.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16367/fi-icl-y/igt@i915_selftest@live_execlists.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][13] ([fdo#111096] / [i915#323]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16367/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Warnings * igt@gem_close_race@basic-threads: - fi-byt-n2820: [TIMEOUT][15] ([fdo#112271] / [i915#1084] / [i915#816]) -> [TIMEOUT][16] ([fdo#112271] / [i915#816]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16367/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@i915_pm_rpm@basic-rte: - fi-kbl-guc: [FAIL][17] ([i915#579]) -> [SKIP][18] ([fdo#109271]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-guc/igt@i915_pm_...@basic-rte.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16367/fi-kbl-guc/igt@i915_pm_...@basic-rte.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][19] ([i915#563]) -> [DMESG-FAIL][20] ([i915#725]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-4770/igt@i915_selftest@live_blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16367/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-icl-u2: [FAIL][21] ([fdo#103375]) -> [DMESG-WARN][22] ([IGT#4] / [i915#263]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16367/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [IGT#4]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/4 [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#111550]: https://bugs.freedesktop.org/show_bug.cgi?id=111550 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#1084]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915/display: Wake the power well during resume
== Series Details == Series: series starting with [1/4] drm/i915/display: Wake the power well during resume URL : https://patchwork.freedesktop.org/series/72849/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16366 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16366 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16366, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16366: ### IGT changes ### Possible regressions * igt@i915_module_load@reload: - fi-bsw-nick:NOTRUN -> [TIMEOUT][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-bsw-nick/igt@i915_module_l...@reload.html * igt@i915_selftest@live_gt_timelines: - fi-snb-2520m: [PASS][2] -> [TIMEOUT][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-snb-2520m/igt@i915_selftest@live_gt_timelines.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-snb-2520m/igt@i915_selftest@live_gt_timelines.html - fi-hsw-4770:[PASS][4] -> [TIMEOUT][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-4770/igt@i915_selftest@live_gt_timelines.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-hsw-4770/igt@i915_selftest@live_gt_timelines.html - fi-blb-e6850: [PASS][6] -> [TIMEOUT][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-blb-e6850/igt@i915_selftest@live_gt_timelines.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-blb-e6850/igt@i915_selftest@live_gt_timelines.html - fi-gdg-551: NOTRUN -> [TIMEOUT][8] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-gdg-551/igt@i915_selftest@live_gt_timelines.html - fi-bwr-2160:[PASS][9] -> [TIMEOUT][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-bwr-2160/igt@i915_selftest@live_gt_timelines.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-bwr-2160/igt@i915_selftest@live_gt_timelines.html - fi-snb-2600:NOTRUN -> [TIMEOUT][11] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-snb-2600/igt@i915_selftest@live_gt_timelines.html - fi-hsw-4770r: [PASS][12] -> [TIMEOUT][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-4770r/igt@i915_selftest@live_gt_timelines.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-hsw-4770r/igt@i915_selftest@live_gt_timelines.html - fi-elk-e7500: [PASS][14] -> [TIMEOUT][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-elk-e7500/igt@i915_selftest@live_gt_timelines.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-elk-e7500/igt@i915_selftest@live_gt_timelines.html - fi-ivb-3770:[PASS][16] -> [TIMEOUT][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-ivb-3770/igt@i915_selftest@live_gt_timelines.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-ivb-3770/igt@i915_selftest@live_gt_timelines.html * igt@runner@aborted: - fi-hsw-4770r: NOTRUN -> [FAIL][18] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-hsw-4770r/igt@run...@aborted.html - fi-gdg-551: NOTRUN -> [FAIL][19] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-gdg-551/igt@run...@aborted.html - fi-snb-2520m: NOTRUN -> [FAIL][20] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-snb-2520m/igt@run...@aborted.html - fi-hsw-4770:NOTRUN -> [FAIL][21] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-hsw-4770/igt@run...@aborted.html - fi-whl-u: NOTRUN -> [FAIL][22] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-whl-u/igt@run...@aborted.html - fi-ivb-3770:NOTRUN -> [FAIL][23] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-ivb-3770/igt@run...@aborted.html - fi-bxt-dsi: NOTRUN -> [FAIL][24] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-bxt-dsi/igt@run...@aborted.html - fi-elk-e7500: NOTRUN -> [FAIL][25] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-elk-e7500/igt@run...@aborted.html - fi-blb-e6850: NOTRUN -> [FAIL][26] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-blb-e6850/igt@run...@aborted.html Suppressed The following results come from untrusted machines, tests, or statuses.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: Add support for DP 1.4 Compliance edid corruption test (rev4)
== Series Details == Series: drm: Add support for DP 1.4 Compliance edid corruption test (rev4) URL : https://patchwork.freedesktop.org/series/70530/ State : warning == Summary == $ dim checkpatch origin/drm-tip bd9dc1267ab5 drm: Add support for DP 1.4 Compliance edid corruption test -:51: ERROR:CODE_INDENT: code indent should use tabs where possible #51: FILE: drivers/gpu/drm/drm_dp_helper.c:372: +u8 real_edid_checksum)$ -:51: WARNING:LEADING_SPACE: please, no spaces at the start of a line #51: FILE: drivers/gpu/drm/drm_dp_helper.c:372: +u8 real_edid_checksum)$ total: 1 errors, 1 warnings, 0 checks, 105 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/display: Wake the power well during resume
== Series Details == Series: series starting with [1/4] drm/i915/display: Wake the power well during resume URL : https://patchwork.freedesktop.org/series/72849/ State : warning == Summary == $ dim checkpatch origin/drm-tip ced9ffb2a020 drm/i915/display: Wake the power well during resume -:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #10: <4> [135.959936] WARNING: CPU: 1 PID: 3085 at drivers/gpu/drm/i915/intel_uncore.c:1166 __unclaimed_reg_debug+0x69/0x80 [i915] total: 0 errors, 1 warnings, 0 checks, 30 lines checked c6ba1e64e9ab drm/i915: Initialise basic fence before acquiring seqno 8af8c775d115 drm/i915/gt: Warn about the hidden i915_vma_pin in timeline_get_seqno edce88fb05d2 drm/i915/selftests: Add a simple rollover for the kernel context ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] drm/i915/gt: Skip rmw for masked registers
A masked register does not need rmw to update, and it is best not to use
such a sequence.
Reported-by: Ville Syrjälä
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 63 ++-
.../gpu/drm/i915/gt/intel_workarounds_types.h | 4 +-
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
3 files changed, 38 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 8d7c3191137c..857337f323ee 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -116,17 +116,17 @@ static void _wa_add(struct i915_wa_list *wal, const
struct i915_wa *wa)
} else {
wa_ = >list[mid];
- if ((wa->mask & ~wa_->mask) == 0) {
- DRM_ERROR("Discarding overwritten w/a for reg
%04x (mask: %08x, value: %08x)\n",
+ if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) {
+ DRM_ERROR("Discarding overwritten w/a for reg
%04x (clear: %08x, set: %08x)\n",
i915_mmio_reg_offset(wa_->reg),
- wa_->mask, wa_->val);
+ wa_->clr, wa_->set);
- wa_->val &= ~wa->mask;
+ wa_->set &= ~wa->clr;
}
wal->wa_count++;
- wa_->val |= wa->val;
- wa_->mask |= wa->mask;
+ wa_->set |= wa->set;
+ wa_->clr |= wa->clr;
wa_->read |= wa->read;
return;
}
@@ -147,13 +147,13 @@ static void _wa_add(struct i915_wa_list *wal, const
struct i915_wa *wa)
}
}
-static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
- u32 val, u32 read_mask)
+static void wa_add(struct i915_wa_list *wal, i915_reg_t reg,
+ u32 clear, u32 set, u32 read_mask)
{
struct i915_wa wa = {
.reg = reg,
- .mask = mask,
- .val = val,
+ .clr = clear,
+ .set = set,
.read = read_mask,
};
@@ -161,38 +161,43 @@ static void wa_add(struct i915_wa_list *wal, i915_reg_t
reg, u32 mask,
}
static void
-wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
- u32 val)
+wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32
set)
{
- wa_add(wal, reg, mask, val, mask);
+ wa_add(wal, reg, clear, set, clear);
}
static void
-wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
+wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
+{
+ wa_write_masked_or(wal, reg, ~0, set);
+}
+
+static void
+wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
{
- wa_write_masked_or(wal, reg, val, _MASKED_BIT_ENABLE(val));
+ wa_write_masked_or(wal, reg, set, set);
}
static void
-wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
+wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
{
- wa_write_masked_or(wal, reg, ~0, val);
+ wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val);
}
static void
-wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
+wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
{
- wa_write_masked_or(wal, reg, val, val);
+ wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val);
}
#define WA_SET_BIT_MASKED(addr, mask) \
- wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_ENABLE(mask))
+ wa_masked_en(wal, (addr), (mask))
#define WA_CLR_BIT_MASKED(addr, mask) \
- wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_DISABLE(mask))
+ wa_masked_dis(wal, (addr), (mask))
#define WA_SET_FIELD_MASKED(addr, mask, value) \
- wa_write_masked_or(wal, (addr), (mask), _MASKED_FIELD((mask), (value)))
+ wa_write_masked_or(wal, (addr), 0, _MASKED_FIELD((mask), (value)))
static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
@@ -662,7 +667,7 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
*cs++ = MI_LOAD_REGISTER_IMM(wal->count);
for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
*cs++ = i915_mmio_reg_offset(wa->reg);
- *cs++ = wa->val;
+ *cs++ = wa->set;
}
*cs++ = MI_NOOP;
@@ -991,11 +996,10 @@ wal_get_fw_for_rmw(struct intel_uncore *uncore, const
struct i915_wa_list *wal)
static bool
wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char
*from)
{
- if ((cur ^ wa->val) &
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Initialise basic fence before acquiring seqno
== Series Details == Series: series starting with [1/2] drm/i915: Initialise basic fence before acquiring seqno URL : https://patchwork.freedesktop.org/series/72845/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16365 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16365 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16365, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16365/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16365: ### IGT changes ### Possible regressions * igt@i915_selftest@live_workarounds: - fi-kbl-7500u: [PASS][1] -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-7500u/igt@i915_selftest@live_workarounds.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16365/fi-kbl-7500u/igt@i915_selftest@live_workarounds.html Known issues Here are the changes found in Patchwork_16365 that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@module-reload: - fi-skl-6770hq: [PASS][3] -> [FAIL][4] ([i915#178]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-skl-6770hq/igt@i915_pm_...@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16365/fi-skl-6770hq/igt@i915_pm_...@module-reload.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-icl-u2: [FAIL][5] ([fdo#103375]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16365/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html * igt@gem_exec_suspend@basic-s4-devices: - fi-icl-u2: [FAIL][7] ([fdo#111550]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16365/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][9] ([i915#563]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-4770/igt@i915_selftest@live_blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16365/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_execlists: - fi-icl-y: [DMESG-FAIL][11] ([fdo#108569]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-y/igt@i915_selftest@live_execlists.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16365/fi-icl-y/igt@i915_selftest@live_execlists.html Warnings * igt@gem_close_race@basic-threads: - fi-byt-n2820: [TIMEOUT][13] ([fdo#112271] / [i915#1084] / [i915#816]) -> [TIMEOUT][14] ([fdo#112271] / [i915#816]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16365/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@i915_pm_rpm@basic-rte: - fi-kbl-guc: [FAIL][15] ([i915#579]) -> [SKIP][16] ([fdo#109271]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-guc/igt@i915_pm_...@basic-rte.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16365/fi-kbl-guc/igt@i915_pm_...@basic-rte.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-icl-u2: [FAIL][17] ([fdo#103375]) -> [FAIL][18] ([i915#217]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16365/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111550]: https://bugs.freedesktop.org/show_bug.cgi?id=111550 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084 [i915#178]: https://gitlab.freedesktop.org/drm/intel/issues/178 [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217 [i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579 [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816 Participating hosts (47 -> 40)
[Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601
Disable Early Read and Src Swap (bit 14) by setting the chicken
register.
BSpec: 46045,52890
v2: Follow the Bspec implementation for the WA.
v3: Have 2 separate defines for bit 14 and 15.
- Rename register definitions with TGL_ prefix
v4: Bspec changed. Again. Add WA to rcs_ WA list.
Cc: Daniele Ceraolo Spurio
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 8d7c3191137c..b0bcf8c55da0 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -593,6 +593,7 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs
*engine,
wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
FF_MODE2_TDS_TIMER_MASK);
+
}
static void
@@ -1319,6 +1320,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
+ if (IS_TGL_REVID(i915, TGL_REVID_A0, REVID_FOREVER)) {
+ /* Wa_1606931601:tgl */
+ wa_write_or(wal,
+ GEN7_ROW_CHICKEN2,
+ GEN12_EARLY_READ_SRC0_DISABLE);
+ }
if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
/* Wa_1606700617:tgl */
wa_masked_en(wal,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0bd431f6a011..c46bec8ebd17 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9151,6 +9151,7 @@ enum {
#define DOP_CLOCK_GATING_DISABLE (1 << 0)
#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
+#define GEN12_EARLY_READ_SRC0_DISABLE(1 << 14)
#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE(1 << 6)
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v3] drm/i915/tgl: Add Wa_1606054188:tgl
On Tiger Lake we do not support source keying in the pixel formats P010,
P012, P016.
v2: Move WA to end of function. Create helper function for format
check. Less verbose debugging messaging.
v3: whitespace
Bspec: 52890
Cc: Matt Roper
Cc: Manasi Navare
CC: Ville Syrjälä
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/display/intel_sprite.c | 22 +
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 2f277d1fc6f1..71ff9849b5c0 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2070,6 +2070,18 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
return 0;
}
+static bool intel_format_is_p01x(int format)
+{
+ switch (format) {
+ case DRM_FORMAT_P010:
+ case DRM_FORMAT_P012:
+ case DRM_FORMAT_P016:
+ return true;
+ default:
+ return false;
+ }
+}
+
static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
@@ -2143,6 +2155,16 @@ static int skl_plane_check_fb(const struct
intel_crtc_state *crtc_state,
return -EINVAL;
}
+ /* Wa_1606054188:tgl
+*
+* TODO: Add format RGB64i when implemented.
+*
+*/
+ if (IS_GEN(dev_priv, 12) &&
+ plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
+ intel_format_is_p01x(fb->format->format))
+ DRM_DEBUG_KMS("Source color keying not supported with P01x
formats\n");
+
return 0;
}
--
2.21.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Add Wa_1606054188:tgl
== Series Details == Series: drm/i915/tgl: Add Wa_1606054188:tgl URL : https://patchwork.freedesktop.org/series/72839/ State : success == Summary == CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16364 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16364/index.html Known issues Here are the changes found in Patchwork_16364 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_gem_contexts: - fi-hsw-peppy: [PASS][1] -> [DMESG-FAIL][2] ([i915#722]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16364/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [PASS][3] -> [DMESG-WARN][4] ([i915#44]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16364/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-icl-u2: [FAIL][5] ([fdo#103375]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16364/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html * igt@gem_exec_suspend@basic-s4-devices: - fi-icl-u2: [FAIL][7] ([fdo#111550]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16364/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_selftest@live_execlists: - fi-icl-y: [DMESG-FAIL][9] ([fdo#108569]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-y/igt@i915_selftest@live_execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16364/fi-icl-y/igt@i915_selftest@live_execlists.html Warnings * igt@i915_pm_rpm@basic-rte: - fi-kbl-guc: [FAIL][11] ([i915#579]) -> [SKIP][12] ([fdo#109271]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-guc/igt@i915_pm_...@basic-rte.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16364/fi-kbl-guc/igt@i915_pm_...@basic-rte.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][13] ([i915#563]) -> [DMESG-FAIL][14] ([i915#553] / [i915#725]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-4770/igt@i915_selftest@live_blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16364/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-icl-u2: [FAIL][15] ([fdo#103375]) -> [DMESG-WARN][16] ([IGT#4] / [i915#263]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16364/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [IGT#4]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/4 [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111550]: https://bugs.freedesktop.org/show_bug.cgi?id=111550 [i915#263]: https://gitlab.freedesktop.org/drm/intel/issues/263 [i915#44]: https://gitlab.freedesktop.org/drm/intel/issues/44 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579 [i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 Participating hosts (47 -> 38) -- Additional (4): fi-gdg-551 fi-cfl-8109u fi-skl-6700k2 fi-snb-2600 Missing(13): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-snb-2520m fi-kbl-7500u fi-whl-u fi-ivb-3770 fi-byt-n2820 fi-byt-clapper fi-bdw-samus fi-kbl-r Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7853 -> Patchwork_16364 CI-20190529: 20190529 CI_DRM_7853: 1df04205c16923e525efe9c26d6e98612d38c9b3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5409: 93aefe6baa3fabf8c0cabe83e185f7b8f8d8753d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16364: 53bdc3c76702c5244ff81472ccf855a836b956b9 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 53bdc3c76702 drm/i915/tgl: Add Wa_1606054188:tgl
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915/gt: Skip rmw for masked registers (rev2)
== Series Details == Series: series starting with [CI,1/3] drm/i915/gt: Skip rmw for masked registers (rev2) URL : https://patchwork.freedesktop.org/series/72804/ State : success == Summary == CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16362 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16362/index.html Known issues Here are the changes found in Patchwork_16362 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_execlists: - fi-apl-guc: [PASS][1] -> [TIMEOUT][2] ([i915#529]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-apl-guc/igt@i915_selftest@live_execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16362/fi-apl-guc/igt@i915_selftest@live_execlists.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-n2820: [TIMEOUT][3] ([fdo#112271] / [i915#1084] / [i915#816]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16362/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@gem_exec_suspend@basic-s3: - fi-icl-u2: [FAIL][5] ([fdo#103375]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16362/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html * igt@gem_exec_suspend@basic-s4-devices: - fi-icl-u2: [FAIL][7] ([fdo#111550]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16362/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_selftest@live_execlists: - fi-icl-y: [DMESG-FAIL][9] ([fdo#108569]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-y/igt@i915_selftest@live_execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16362/fi-icl-y/igt@i915_selftest@live_execlists.html Warnings * igt@i915_pm_rpm@basic-rte: - fi-kbl-guc: [FAIL][11] ([i915#579]) -> [SKIP][12] ([fdo#109271]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-guc/igt@i915_pm_...@basic-rte.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16362/fi-kbl-guc/igt@i915_pm_...@basic-rte.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][13] ([i915#563]) -> [DMESG-FAIL][14] ([i915#725]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-4770/igt@i915_selftest@live_blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16362/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-icl-u2: [FAIL][15] ([fdo#103375]) -> [DMESG-WARN][16] ([IGT#4] / [i915#263]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16362/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][17] ([fdo#111096] / [i915#323]) -> [FAIL][18] ([fdo#111407]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16362/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [IGT#4]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/4 [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [fdo#111550]: https://bugs.freedesktop.org/show_bug.cgi?id=111550 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084 [i915#263]: https://gitlab.freedesktop.org/drm/intel/issues/263 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#529]: https://gitlab.freedesktop.org/drm/intel/issues/529 [i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816 Participating hosts (47 -> 41) -- Additional (5): fi-cfl-8109u fi-skl-6600u fi-kbl-7560u fi-skl-6700k2 fi-snb-2600 Missing
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Add Wa_1606054188:tgl
== Series Details ==
Series: drm/i915/tgl: Add Wa_1606054188:tgl
URL : https://patchwork.freedesktop.org/series/72839/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
53bdc3c76702 drm/i915/tgl: Add Wa_1606054188:tgl
-:31: ERROR:SWITCH_CASE_INDENT_LEVEL: switch and case should be at the same
indent
#31: FILE: drivers/gpu/drm/i915/display/intel_sprite.c:2075:
+ switch(format){
+ case DRM_FORMAT_P010:
+ case DRM_FORMAT_P012:
+ case DRM_FORMAT_P016:
[...]
+ default:
-:31: ERROR:SPACING: space required before the open brace '{'
#31: FILE: drivers/gpu/drm/i915/display/intel_sprite.c:2075:
+ switch(format){
-:31: ERROR:SPACING: space required before the open parenthesis '('
#31: FILE: drivers/gpu/drm/i915/display/intel_sprite.c:2075:
+ switch(format){
-:53: ERROR:SPACING: space required before the open parenthesis '('
#53: FILE: drivers/gpu/drm/i915/display/intel_sprite.c:2163:
+ if(IS_GEN(dev_priv, 12) &&
total: 4 errors, 0 warnings, 0 checks, 34 lines checked
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[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/3] drm/i915: Introduce encoder->compute_config_late()
== Series Details == Series: series starting with [1/3] drm/i915: Introduce encoder->compute_config_late() URL : https://patchwork.freedesktop.org/series/72836/ State : failure == Summary == Applying: drm/i915: Introduce encoder->compute_config_late() Applying: drm/i915/dp: Compute port sync crtc states post compute_config() error: sha1 information is lacking or useless (drivers/gpu/drm/i915/display/intel_display.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0002 drm/i915/dp: Compute port sync crtc states post compute_config() When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Introduce guc_is_ready (rev2)
== Series Details == Series: drm/i915/guc: Introduce guc_is_ready (rev2) URL : https://patchwork.freedesktop.org/series/72825/ State : success == Summary == CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16361 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16361/index.html Known issues Here are the changes found in Patchwork_16361 that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@module-reload: - fi-skl-6770hq: [PASS][1] -> [FAIL][2] ([i915#178]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-skl-6770hq/igt@i915_pm_...@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16361/fi-skl-6770hq/igt@i915_pm_...@module-reload.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-n2820: [TIMEOUT][3] ([fdo#112271] / [i915#1084] / [i915#816]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16361/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live_execlists: - fi-icl-y: [DMESG-FAIL][5] ([fdo#108569]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-y/igt@i915_selftest@live_execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16361/fi-icl-y/igt@i915_selftest@live_execlists.html Warnings * igt@i915_pm_rpm@basic-rte: - fi-kbl-guc: [FAIL][7] ([i915#579]) -> [SKIP][8] ([fdo#109271]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-guc/igt@i915_pm_...@basic-rte.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16361/fi-kbl-guc/igt@i915_pm_...@basic-rte.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][9] ([i915#563]) -> [DMESG-FAIL][10] ([i915#553] / [i915#725]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-4770/igt@i915_selftest@live_blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16361/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][11] ([fdo#111096] / [i915#323]) -> [FAIL][12] ([fdo#111407]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16361/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084 [i915#178]: https://gitlab.freedesktop.org/drm/intel/issues/178 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816 Participating hosts (47 -> 46) -- Additional (5): fi-gdg-551 fi-cfl-8109u fi-skl-6600u fi-skl-6700k2 fi-snb-2600 Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7853 -> Patchwork_16361 CI-20190529: 20190529 CI_DRM_7853: 1df04205c16923e525efe9c26d6e98612d38c9b3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5409: 93aefe6baa3fabf8c0cabe83e185f7b8f8d8753d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16361: 3040bb3cc8623303df5214f499c34001807caa1c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 3040bb3cc862 drm/i915/guc: Introduce guc_is_ready == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16361/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/18] drm/i915: Include DP VSC SDP in the crtc state dump
Dump out the DP VSC SDP in the normal crtc state dump
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_display.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 593c63f51210..7d298f14799d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12878,6 +12878,16 @@ intel_dump_infoframe(struct drm_i915_private *dev_priv,
hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
}
+static void
+intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
+ const struct intel_dp_vsc_sdp *vsc)
+{
+ if (!drm_debug_enabled(DRM_UT_KMS))
+ return;
+
+ intel_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
+}
+
#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
static const char * const output_type_str[] = {
@@ -13036,6 +13046,9 @@ static void intel_dump_pipe_config(const struct
intel_crtc_state *pipe_config,
if (pipe_config->infoframes.enable &
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
intel_dump_infoframe(dev_priv, _config->infoframes.drm);
+ if (pipe_config->infoframes.enable &
+ intel_hdmi_infoframe_enable(DP_SDP_VSC))
+ intel_dump_dp_vsc_sdp(dev_priv, _config->infoframes.vsc);
drm_dbg_kms(_priv->drm, "requested mode:\n");
drm_mode_debug_printmodeline(_config->hw.mode);
--
2.24.1
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[Intel-gfx] [PATCH 13/18] drm/i915: Add state readout for DP HDR Metadata Infoframe SDP
Added state readout for DP HDR Metadata Infoframe SDP. Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_ddi.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 374ab6a3757c..a9eaf7a6bc15 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4322,6 +4322,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder, pipe_config->fec_enable); } + pipe_config->infoframes.enable |= + intel_hdmi_infoframes_enabled(encoder, pipe_config); + break; case TRANS_DDI_MODE_SELECT_DP_MST: pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); @@ -4333,6 +4336,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder, REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); intel_dp_get_m_n(intel_crtc, pipe_config); + + pipe_config->infoframes.enable |= + intel_hdmi_infoframes_enabled(encoder, pipe_config); break; default: break; @@ -4383,6 +4389,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder, intel_read_infoframe(encoder, pipe_config, HDMI_INFOFRAME_TYPE_DRM, _config->infoframes.drm); + + intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); } static enum intel_output_type -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 17/18] drm/i915/dp: Add compute routine for DP PSR VSC SDP
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it adds a compute routine for PSR VSC SDP.
As PSR routine can not use infoframes.vsc of crtc state, it also adds new
writing of DP SDPs (Secondary Data Packet) for PSR.
PSR routine has its own scenario and timings of writing a VSC SDP.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 53 +
drivers/gpu/drm/i915/display/intel_dp.h | 7
2 files changed, 60 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index e8cf12d14dc3..3571e959cdcc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2463,6 +2463,42 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
*intel_dp,
_state->infoframes.vsc);
}
+void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state,
+ struct intel_dp_vsc_sdp *vsc)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ vsc->sdp_type = DP_SDP_VSC;
+
+ if (dev_priv->psr.psr2_enabled) {
+ if (dev_priv->psr.colorimetry_support &&
+ intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+ /* [PSR2, +Colorimetry] */
+ intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+vsc);
+ } else {
+ /*
+* [PSR2, -Colorimetry]
+* Prepare VSC Header for SU as per eDP 1.4 spec, Table
6-11
+* 3D stereo + PSR/PSR2 + Y-coordinate.
+*/
+ vsc->revision = 0x4;
+ vsc->length = 0xe;
+ }
+ } else {
+ /*
+* [PSR1]
+* Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+* VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
+* higher).
+*/
+ vsc->revision = 0x2;
+ vsc->length = 0x8;
+ }
+}
+
static void
intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_crtc_state
*crtc_state,
const struct drm_connector_state
*conn_state)
@@ -4888,6 +4924,23 @@ static void intel_write_dp_sdp(struct intel_encoder
*encoder,
intel_dig_port->write_infoframe(encoder, crtc_state, type, , len);
}
+void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ struct intel_dp_vsc_sdp *vsc)
+{
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+ struct dp_sdp sdp = {};
+ ssize_t len;
+
+ len = intel_dp_vsc_sdp_pack(vsc, , sizeof(sdp));
+
+ if (WARN_ON(len < 0))
+ return;
+
+ intel_dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
+ , len);
+}
+
void intel_dp_set_infoframes(struct intel_encoder *encoder,
bool enable,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index 6d8003eb59f6..fb63e9a2ee78 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -112,6 +112,13 @@ int intel_dp_link_required(int pixel_clock, int bpp);
int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
+void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state,
+ struct intel_dp_vsc_sdp *vsc);
+void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ struct intel_dp_vsc_sdp *vsc);
void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
--
2.24.1
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[Intel-gfx] [PATCH 12/18] drm/i915: Program DP SDPs with computed configs
In order to use computed config for DP SDPs (DP VSC SDP and DP HDR Metadata
Infoframe SDP), it replaces intel_dp_vsc_enable() function and
intel_dp_hdr_metadata_enable() function to intel_dp_set_infoframes()
function.
Before applying it, routines of program SDP always calculated configs when
they called. And it removes unused functions.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
drivers/gpu/drm/i915/display/intel_dp.c | 226 ---
drivers/gpu/drm/i915/display/intel_dp.h | 6 -
3 files changed, 1 insertion(+), 234 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index c96f629cddc3..374ab6a3757c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3900,8 +3900,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
*encoder,
intel_edp_backlight_on(crtc_state, conn_state);
intel_psr_enable(intel_dp, crtc_state);
- intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
- intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
+ intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
if (crtc_state->has_audio)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index e33488222ac5..e8cf12d14dc3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5263,232 +5263,6 @@ void intel_dp_vsc_sdp_log(const char *level, struct
device *dev,
}
#undef dp_sdp_log
-static void
-intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
-{
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct dp_sdp vsc_sdp = {};
-
- /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
- vsc_sdp.sdp_header.HB0 = 0;
- vsc_sdp.sdp_header.HB1 = 0x7;
-
- /*
-* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
-* Colorimetry Format indication.
-*/
- vsc_sdp.sdp_header.HB2 = 0x5;
-
- /*
-* VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
-* Colorimetry Format indication (HB2 = 05h).
-*/
- vsc_sdp.sdp_header.HB3 = 0x13;
-
- /* DP 1.4a spec, Table 2-120 */
- switch (crtc_state->output_format) {
- case INTEL_OUTPUT_FORMAT_YCBCR444:
- vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
- break;
- case INTEL_OUTPUT_FORMAT_YCBCR420:
- vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
- break;
- case INTEL_OUTPUT_FORMAT_RGB:
- default:
- /* RGB: DB16[7:4] = 0h */
- break;
- }
-
- switch (conn_state->colorspace) {
- case DRM_MODE_COLORIMETRY_BT709_YCC:
- vsc_sdp.db[16] |= 0x1;
- break;
- case DRM_MODE_COLORIMETRY_XVYCC_601:
- vsc_sdp.db[16] |= 0x2;
- break;
- case DRM_MODE_COLORIMETRY_XVYCC_709:
- vsc_sdp.db[16] |= 0x3;
- break;
- case DRM_MODE_COLORIMETRY_SYCC_601:
- vsc_sdp.db[16] |= 0x4;
- break;
- case DRM_MODE_COLORIMETRY_OPYCC_601:
- vsc_sdp.db[16] |= 0x5;
- break;
- case DRM_MODE_COLORIMETRY_BT2020_CYCC:
- case DRM_MODE_COLORIMETRY_BT2020_RGB:
- vsc_sdp.db[16] |= 0x6;
- break;
- case DRM_MODE_COLORIMETRY_BT2020_YCC:
- vsc_sdp.db[16] |= 0x7;
- break;
- case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
- case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
- vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
- break;
- default:
- /* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
-
- /* RGB->YCBCR color conversion uses the BT.709 color space. */
- if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
- vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
- break;
- }
-
- /*
-* For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
-* the following Component Bit Depth values are defined:
-* 001b = 8bpc.
-* 010b = 10bpc.
-* 011b = 12bpc.
-* 100b = 16bpc.
-*/
- switch (crtc_state->pipe_bpp) {
- case 24: /* 8bpc */
- vsc_sdp.db[17] = 0x1;
- break;
- case 30: /* 10bpc */
- vsc_sdp.db[17] = 0x2;
- break;
- case 36: /* 12bpc */
- vsc_sdp.db[17] = 0x3;
- break;
- case 48: /* 16bpc */
-
[Intel-gfx] [PATCH 16/18] drm/i915: Stop sending DP SDPs on intel_ddi_post_disable_dp()
Call intel_dp_set_infoframes(false) function on intel_ddi_post_disable_dp() to make sure not to send VSC SDP and HDR Metadata Infoframe SDP. Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 69073a15edb8..8509cd33569e 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3713,6 +3713,8 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, INTEL_OUTPUT_DP_MST); enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + intel_dp_set_infoframes(encoder, false, old_crtc_state, old_conn_state); + /* * Power down sink before disabling the port, otherwise we end * up getting interrupts from the sink on detecting link loss. -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 14/18] drm/i915: Add state readout for DP VSC SDP
Added state readout for DP VSC SDP and enabled state validation
for DP VSC SDP.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 43
2 files changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index a9eaf7a6bc15..64e4edefa998 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4391,6 +4391,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
_config->infoframes.drm);
intel_read_dp_sdp(encoder, pipe_config,
HDMI_PACKET_TYPE_GAMUT_METADATA);
+ intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
}
static enum intel_output_type
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 7d298f14799d..d13f70596a84 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13503,6 +13503,13 @@ intel_compare_infoframe(const union hdmi_infoframe *a,
return memcmp(a, b, sizeof(*a)) == 0;
}
+static bool
+intel_compare_dp_vsc_sdp(const struct intel_dp_vsc_sdp *a,
+const struct intel_dp_vsc_sdp *b)
+{
+ return memcmp(a, b, sizeof(*a)) == 0;
+}
+
static void
pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
bool fastset, const char *name,
@@ -13528,6 +13535,30 @@ pipe_config_infoframe_mismatch(struct drm_i915_private
*dev_priv,
}
}
+static void
+pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
+ bool fastset, const char *name,
+ const struct intel_dp_vsc_sdp *a,
+ const struct intel_dp_vsc_sdp *b)
+{
+ if (fastset) {
+ if (!drm_debug_enabled(DRM_UT_KMS))
+ return;
+
+ DRM_DEBUG_KMS("fastset mismatch in %s dp sdp\n", name);
+ DRM_DEBUG_KMS("expected:\n");
+ intel_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
+ DRM_DEBUG_KMS("found:\n");
+ intel_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
+ } else {
+ DRM_ERROR("mismatch in %s dp sdp\n", name);
+ DRM_ERROR("expected:\n");
+ intel_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
+ DRM_ERROR("found:\n");
+ intel_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
+ }
+}
+
static void __printf(4, 5)
pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
const char *name, const char *format, ...)
@@ -13729,6 +13760,17 @@ intel_pipe_config_compare(const struct
intel_crtc_state *current_config,
} \
} while (0)
+#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
+ if (!intel_compare_dp_vsc_sdp(_config->infoframes.name, \
+ _config->infoframes.name)) { \
+ pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset,
__stringify(name), \
+
_config->infoframes.name, \
+ _config->infoframes.name);
\
+ ret = false; \
+ } \
+} while (0)
+
+
#define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
if (current_config->name1 != pipe_config->name1) { \
pipe_config_mismatch(fastset, crtc, __stringify(name1), \
@@ -13902,6 +13944,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_INFOFRAME(spd);
PIPE_CONF_CHECK_INFOFRAME(hdmi);
PIPE_CONF_CHECK_INFOFRAME(drm);
+ PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
PIPE_CONF_CHECK_I(master_transcoder);
--
2.24.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/18] drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump
Dump out the DP HDR Metadata Infoframe SDP in the normal crtc state dump. HDMI Dynamic Range and Mastering (DRM) infoframe and DP HDR Metadata Infoframe SDP use the same member variable in infoframes of crtc state. Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 239861bcedba..593c63f51210 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13033,6 +13033,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, if (pipe_config->infoframes.enable & intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) intel_dump_infoframe(dev_priv, _config->infoframes.drm); + if (pipe_config->infoframes.enable & + intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) + intel_dump_infoframe(dev_priv, _config->infoframes.drm); drm_dbg_kms(_priv->drm, "requested mode:\n"); drm_mode_debug_printmodeline(_config->hw.mode); -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 09/18] drm/i915: Include HDMI DRM infoframe in the crtc state dump
Dump out the HDMI Dynamic Range and Mastering (DRM) infoframe in the normal crtc state dump. Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index c0e5002ce64c..239861bcedba 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13030,6 +13030,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, if (pipe_config->infoframes.enable & intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) intel_dump_infoframe(dev_priv, _config->infoframes.hdmi); + if (pipe_config->infoframes.enable & + intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) + intel_dump_infoframe(dev_priv, _config->infoframes.drm); drm_dbg_kms(_priv->drm, "requested mode:\n"); drm_mode_debug_printmodeline(_config->hw.mode); -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 15/18] drm/i915: Program DP SDPs on pipe updates
Call intel_dp_set_infoframes() function on pipe updates to make sure that we send VSC SDP and HDR Metadata Infoframe SDP (when applicable) on fastsets. Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_ddi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 64e4edefa998..69073a15edb8 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4062,6 +4062,7 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder, intel_ddi_set_dp_msa(crtc_state, conn_state); intel_psr_update(intel_dp, crtc_state); + intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); intel_edp_drrs_enable(intel_dp, crtc_state); intel_panel_update_backlight(encoder, crtc_state, conn_state); -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 18/18] drm/i915/psr: Use new DP VSC SDP compute routine on PSR
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it uses a new psr vsc sdp compute routine.
Because PSR routine has its own scenario and timings of writing a VSC SDP,
the current PSR routine needs to have its own intel_dp_vsc_sdp structure
member variable on struct i915_psr.
In order to include "struct intel_dp_vsc_sdp" to "struct i915_psr",
it moves defintion of "struct intel_dp_vsc_sdp" to i915_drv.h .
And in order to calculate colorimetry information, intel_psr_update()
function and intel_psr_enable() function extend a drm_connector_state
argument.
There are no changes to PSR mechanism.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
.../drm/i915/display/intel_display_types.h| 11
drivers/gpu/drm/i915/display/intel_psr.c | 54 ++-
drivers/gpu/drm/i915/display/intel_psr.h | 6 ++-
drivers/gpu/drm/i915/i915_drv.h | 12 +
5 files changed, 33 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 8509cd33569e..00b46c45f6a8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3901,7 +3901,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
*encoder,
intel_dp_stop_link_train(intel_dp);
intel_edp_backlight_on(crtc_state, conn_state);
- intel_psr_enable(intel_dp, crtc_state);
+ intel_psr_enable(intel_dp, crtc_state, conn_state);
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
@@ -4063,7 +4063,7 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder
*encoder,
intel_ddi_set_dp_msa(crtc_state, conn_state);
- intel_psr_update(intel_dp, crtc_state);
+ intel_psr_update(intel_dp, crtc_state, conn_state);
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 81112d63342c..09438a661a97 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -780,17 +780,6 @@ enum intel_output_format {
INTEL_OUTPUT_FORMAT_YCBCR444,
};
-struct intel_dp_vsc_sdp {
- unsigned char sdp_type; /* Secondary-data Packet Type */
- unsigned char revision; /* Revision Number */
- unsigned char length; /* Number of Valid Data Bytes */
- enum dp_colorspace colorspace;
- enum dp_colorimetry colorimetry;
- int bpc;
- enum dp_dynamic_range dynamic_range;
- enum dp_content_type content_type;
-};
-
struct intel_crtc_state {
/*
* uapi (drm) state. This is the software state shown to userspace.
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index e41ed962aa80..a4564607b6c5 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -330,39 +330,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
}
}
-static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
-{
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct dp_sdp psr_vsc;
-
- if (dev_priv->psr.psr2_enabled) {
- /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
- memset(_vsc, 0, sizeof(psr_vsc));
- psr_vsc.sdp_header.HB0 = 0;
- psr_vsc.sdp_header.HB1 = 0x7;
- if (dev_priv->psr.colorimetry_support) {
- psr_vsc.sdp_header.HB2 = 0x5;
- psr_vsc.sdp_header.HB3 = 0x13;
- } else {
- psr_vsc.sdp_header.HB2 = 0x4;
- psr_vsc.sdp_header.HB3 = 0xe;
- }
- } else {
- /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
- memset(_vsc, 0, sizeof(psr_vsc));
- psr_vsc.sdp_header.HB0 = 0;
- psr_vsc.sdp_header.HB1 = 0x7;
- psr_vsc.sdp_header.HB2 = 0x2;
- psr_vsc.sdp_header.HB3 = 0x8;
- }
-
- intel_dig_port->write_infoframe(_dig_port->base,
- crtc_state,
- DP_SDP_VSC, _vsc, sizeof(psr_vsc));
-}
-
static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -841,9 +808,12 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
}
static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
-
[Intel-gfx] [PATCH 08/18] drm/i915/dp: Add logging function for DP VSC SDP
When receiving video it is very useful to be able to log DP VSC SDP.
This greatly simplifies debugging.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 173
drivers/gpu/drm/i915/display/intel_dp.h | 4 +
2 files changed, 177 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 6756030692c8..e33488222ac5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5090,6 +5090,179 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
}
}
+static const char *dp_colorspace_get_name(enum dp_colorspace colorspace)
+{
+ if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
+ return "Invalid";
+
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "RGB";
+ case DP_COLORSPACE_YUV444:
+ return "YUV444";
+ case DP_COLORSPACE_YUV422:
+ return "YUV422";
+ case DP_COLORSPACE_YUV420:
+ return "YUV420";
+ case DP_COLORSPACE_Y_ONLY:
+ return "Y_ONLY";
+ case DP_COLORSPACE_RAW:
+ return "RAW";
+ default:
+ return "Reserved";
+ }
+}
+
+static const char *dp_colorimetry_get_name(enum dp_colorspace colorspace,
+ enum dp_colorimetry colorimetry)
+{
+ if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
+ return "Invalid";
+
+ switch (colorimetry) {
+ case DP_COLORIMETRY_DEFAULT:
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "sRGB";
+ case DP_COLORSPACE_YUV444:
+ case DP_COLORSPACE_YUV422:
+ case DP_COLORSPACE_YUV420:
+ return "BT.601";
+ case DP_COLORSPACE_Y_ONLY:
+ return "DICOM PS3.14";
+ case DP_COLORSPACE_RAW:
+ return "Custom Color Profile";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "Wide Fixed";
+ case DP_COLORSPACE_YUV444:
+ case DP_COLORSPACE_YUV422:
+ case DP_COLORSPACE_YUV420:
+ return "BT.709";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "Wide Float";
+ case DP_COLORSPACE_YUV444:
+ case DP_COLORSPACE_YUV422:
+ case DP_COLORSPACE_YUV420:
+ return "xvYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "OpRGB";
+ case DP_COLORSPACE_YUV444:
+ case DP_COLORSPACE_YUV422:
+ case DP_COLORSPACE_YUV420:
+ return "xvYCC 709";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "DCI-P3";
+ case DP_COLORSPACE_YUV444:
+ case DP_COLORSPACE_YUV422:
+ case DP_COLORSPACE_YUV420:
+ return "sYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "Custom Profile";
+ case DP_COLORSPACE_YUV444:
+ case DP_COLORSPACE_YUV422:
+ case DP_COLORSPACE_YUV420:
+ return "OpYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "BT.2020 RGB";
+ case DP_COLORSPACE_YUV444:
+ case DP_COLORSPACE_YUV422:
+ case DP_COLORSPACE_YUV420:
+ return "BT.2020 CYCC";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_BT2020_YCC:
+ switch (colorspace) {
+
[Intel-gfx] [PATCH 07/18] drm/i915/dp: Read out DP SDPs (Secondary Data Packet)
It adds code to read the DP SDPs from the video DIP and unpack them into
the crtc state.
It adds routines that read out DP VSC SDP and DP HDR Metadata Infoframe SDP
In order to unpack DP VSC SDP, it adds intel_dp_vsc_sdp_unpack() function.
It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
[Table 2-117: VSC SDP Payload for DB16 through DB18]
In order to unpack DP HDR Metadata Infoframe SDP, it adds
intel_dp_hdr_metadata_infoframe_sdp_unpack(). And it follows DP 1.4a spec.
([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and
[Table 2-126: INFOFRAME SDP v1.2 Payload Data Bytes - DB0 through DB31])
and CTA-861-G spec. [Table-42 Dynamic Range and Mastering InfoFrame].
A nameing rule and style of intel_read_dp_sdp() function references
intel_read_infoframe() function of intel_hdmi.c
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 170
drivers/gpu/drm/i915/display/intel_dp.h | 3 +
2 files changed, 173 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 609444cbb29f..6756030692c8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4920,6 +4920,176 @@ void intel_dp_set_infoframes(struct intel_encoder
*encoder,
intel_write_dp_sdp(encoder, crtc_state,
HDMI_PACKET_TYPE_GAMUT_METADATA);
}
+static int intel_dp_vsc_sdp_unpack(struct intel_dp_vsc_sdp *vsc,
+ const void *buffer, size_t size)
+{
+ const struct dp_sdp *sdp = buffer;
+
+ if (size < sizeof(struct dp_sdp))
+ return -EINVAL;
+
+ memset(vsc, 0, size);
+
+ if (sdp->sdp_header.HB0 != 0 )
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB1 != DP_SDP_VSC)
+ return -EINVAL;
+ vsc->sdp_type = sdp->sdp_header.HB1;
+
+ if (sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) {
+ vsc->revision = sdp->sdp_header.HB2;
+ vsc->length = sdp->sdp_header.HB3;
+ } else if (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) {
+ vsc->revision = sdp->sdp_header.HB2;
+ vsc->length = sdp->sdp_header.HB3;
+ } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
+ vsc->revision = sdp->sdp_header.HB2;
+ vsc->length = sdp->sdp_header.HB3;
+ vsc->colorspace = (sdp->db[16] >> 4) & 0xf;
+ vsc->colorimetry = sdp->db[16] & 0xf;
+ vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
+
+ switch (sdp->db[17] & 0x7) {
+ case 0x1:
+ vsc->bpc = 8;
+ break;
+ case 0x2:
+ vsc->bpc = 10;
+ break;
+ case 0x3:
+ vsc->bpc = 12;
+ break;
+ case 0x4:
+ vsc->bpc = 16;
+ break;
+ default:
+ MISSING_CASE(sdp->db[17] & 0x7);
+ return -EINVAL;
+ }
+
+ vsc->content_type = sdp->db[18] & 0x7;
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int
+intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe
*drm_infoframe,
+ const void *buffer, size_t size)
+{
+ int ret;
+
+ const struct dp_sdp *sdp = buffer;
+ if (size < sizeof(struct dp_sdp))
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB0 != 0 )
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
+ return -EINVAL;
+
+ /*
+* Least Significant Eight Bits of (Data Byte Count – 1)
+* 1Dh (i.e., Data Byte Count = 30 bytes).
+*/
+ if (sdp->sdp_header.HB2 != 0x1D)
+ return -EINVAL;
+
+ /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
+ if ((sdp->sdp_header.HB3 & 0x3) != 0)
+ return -EINVAL;
+
+ /* INFOFRAME SDP Version Number */
+ if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
+ return -EINVAL;
+
+ /* CTA Header Byte 2 (INFOFRAME Version Number) */
+ if (sdp->db[0] != 1)
+ return -EINVAL;
+
+ /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
+ if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
+ return -EINVAL;
+
+ ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, >db[2],
+HDMI_DRM_INFOFRAME_SIZE);
+
+ return ret;
+}
+
+static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ struct intel_dp_vsc_sdp *vsc)
+{
+ struct
[Intel-gfx] [PATCH 06/18] video/hdmi: Add Unpack only function for DRM infoframe
It adds an unpack only function for DRM infoframe for dynamic range and
mastering infoframe readout.
It unpacks the information data block contained in the binary buffer into
a structured frame of the HDMI Dynamic Range and Mastering (DRM)
information frame.
In contrast to hdmi_drm_infoframe_unpack() function, it does not verify
a checksum.
It can be used for unpacking a DP HDR Metadata Infoframe SDP case.
DP HDR Metadata Infoframe SDP uses the same Dynamic Range and Mastering
(DRM) information (CTA-861-G spec.) such as HDMI DRM infoframe.
But DP SDP header and payload structure are different from HDMI DRM
Infoframe. Therefore unpacking DRM infoframe for DP requires skipping of
a verifying checksum.
Signed-off-by: Gwan-gyeong Mun
---
drivers/video/hdmi.c | 58 +++-
include/linux/hdmi.h | 2 ++
2 files changed, 43 insertions(+), 17 deletions(-)
diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 9c82e2a0a411..9818836d82b7 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -1775,20 +1775,18 @@ hdmi_vendor_any_infoframe_unpack(union
hdmi_vendor_any_infoframe *frame,
}
/**
- * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
+ * hdmi_drm_infoframe_unpack_only() - unpack binary buffer to a HDMI DRM
infoframe
* @frame: HDMI DRM infoframe
* @buffer: source buffer
* @size: size of buffer
*
- * Unpacks the information contained in binary @buffer into a structured
+ * Unpacks the information data block contained in binary @buffer into a
structured
* @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
- * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
- * specification.
*
* Returns 0 on success or a negative error code on failure.
*/
-static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
-const void *buffer, size_t size)
+int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
+ const void *buffer, size_t size)
{
const u8 *ptr = buffer;
const u8 *temp;
@@ -1797,23 +1795,13 @@ static int hdmi_drm_infoframe_unpack(struct
hdmi_drm_infoframe *frame,
int ret;
int i;
- if (size < HDMI_INFOFRAME_SIZE(DRM))
- return -EINVAL;
-
- if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
- ptr[1] != 1 ||
- ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
- return -EINVAL;
-
- if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
+ if (size < HDMI_DRM_INFOFRAME_SIZE)
return -EINVAL;
ret = hdmi_drm_infoframe_init(frame);
if (ret)
return ret;
- ptr += HDMI_INFOFRAME_HEADER_SIZE;
-
frame->eotf = ptr[0] & 0x7;
frame->metadata_type = ptr[1] & 0x7;
@@ -1837,6 +1825,42 @@ static int hdmi_drm_infoframe_unpack(struct
hdmi_drm_infoframe *frame,
return 0;
}
+EXPORT_SYMBOL(hdmi_drm_infoframe_unpack_only);
+
+/**
+ * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
+ * @frame: HDMI DRM infoframe
+ * @buffer: source buffer
+ * @size: size of buffer
+ *
+ * Unpacks the information contained in binary @buffer into a structured
+ * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
+ * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
+ * specification.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
+const void *buffer, size_t size)
+{
+ const u8 *ptr = buffer;
+ int ret;
+
+ if (size < HDMI_INFOFRAME_SIZE(DRM))
+ return -EINVAL;
+
+ if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
+ ptr[1] != 1 ||
+ ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
+ return -EINVAL;
+
+ if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
+ return -EINVAL;
+
+ ret = hdmi_drm_infoframe_unpack_only(frame, ptr +
HDMI_INFOFRAME_HEADER_SIZE,
+size - HDMI_INFOFRAME_HEADER_SIZE);
+ return ret;
+}
/**
* hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index 9918a6c910c5..afb43efc03e0 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -219,6 +219,8 @@ ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe
*frame, void *buffer,
ssize_t hdmi_drm_infoframe_pack_only(const struct hdmi_drm_infoframe *frame,
void *buffer, size_t size);
int hdmi_drm_infoframe_check(struct hdmi_drm_infoframe *frame);
+int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
+ const void *buffer, size_t size);
enum hdmi_spd_sdi {
[Intel-gfx] [PATCH 04/18] drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP
It stores computed dp hdr metadata infoframe sdp to infoframes.drm of
crtc state. It referenced intel_hdmi_compute_drm_infoframe().
While computing, we'll also fill out the inforames.enable bitmask
appropriately.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 705d36b548b1..64e697445085 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2463,6 +2463,26 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
*intel_dp,
_state->infoframes.vsc);
}
+static void
+intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_crtc_state
*crtc_state,
+ const struct drm_connector_state
*conn_state)
+{
+ int ret;
+ struct hdmi_drm_infoframe *drm_infoframe =
_state->infoframes.drm.drm;
+
+ if (!conn_state->hdr_output_metadata)
+ return;
+
+ ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
+
+ if (ret) {
+ DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
+ return;
+ }
+
+ crtc_state->infoframes.enable |=
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
+}
+
int
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
@@ -2569,6 +2589,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_psr_compute_config(intel_dp, pipe_config);
intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
+ intel_dp_compute_hdr_metadata_infoframe_sdp(pipe_config, conn_state);
return 0;
}
--
2.24.1
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[Intel-gfx] [PATCH 03/18] drm/i915/dp: Add compute routine for DP VSC SDP
It stores computed dp vsc sdp to infoframes.vsc of crtc state.
While computing we'll also fill out the inforames.enable bitmask
appropriately.
The compute routine follows DP 1.4 spec [Table 2-117: VSC SDP Payload for
DB16 through DB18].
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 92 +
1 file changed, 92 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f4dede6253f8..705d36b548b1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2372,6 +2372,97 @@ static bool intel_dp_port_has_audio(struct
drm_i915_private *dev_priv,
return true;
}
+static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state
*crtc_state,
+const struct drm_connector_state
*conn_state,
+struct intel_dp_vsc_sdp *vsc)
+{
+ /*
+* Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
+* Colorimetry Format indication.
+*/
+ vsc->revision = 0x5;
+ vsc->length = 0x13;
+
+ /* DP 1.4a spec, Table 2-120 */
+ switch (crtc_state->output_format) {
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ vsc->colorspace = DP_COLORSPACE_YUV444;
+ break;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ vsc->colorspace = DP_COLORSPACE_YUV420;
+ break;
+ case INTEL_OUTPUT_FORMAT_RGB:
+ default:
+ vsc->colorspace = DP_COLORSPACE_RGB;
+ }
+
+ switch (conn_state->colorspace) {
+ case DRM_MODE_COLORIMETRY_BT709_YCC:
+ vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
+ break;
+ case DRM_MODE_COLORIMETRY_XVYCC_601:
+ vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
+ break;
+ case DRM_MODE_COLORIMETRY_XVYCC_709:
+ vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
+ break;
+ case DRM_MODE_COLORIMETRY_SYCC_601:
+ vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
+ break;
+ case DRM_MODE_COLORIMETRY_OPYCC_601:
+ vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
+ break;
+ case DRM_MODE_COLORIMETRY_BT2020_CYCC:
+ vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
+ break;
+ case DRM_MODE_COLORIMETRY_BT2020_RGB:
+ vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
+ break;
+ case DRM_MODE_COLORIMETRY_BT2020_YCC:
+ vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
+ break;
+ case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
+ case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
+ vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
+ break;
+ default:
+ /*
+* RGB->YCBCR color conversion uses the BT.709
+* color space.
+*/
+ if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
+ else
+ vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
+ break;
+ }
+
+ vsc->bpc = crtc_state->pipe_bpp / 3;
+ /* all YCbCr are always limited range */
+ vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
+ vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
+}
+
+static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
+struct intel_crtc_state *crtc_state,
+const struct drm_connector_state
*conn_state)
+{
+ struct intel_dp_vsc_sdp *vsc = _state->infoframes.vsc;
+
+ /* When PSR is enabled, VSC SDP is handled by PSR routine */
+ if (intel_psr_enabled(intel_dp))
+ return;
+
+ if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
+ return;
+
+ crtc_state->infoframes.enable |=
intel_hdmi_infoframe_enable(DP_SDP_VSC);
+ vsc->sdp_type = DP_SDP_VSC;
+ intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+_state->infoframes.vsc);
+}
+
int
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
@@ -2477,6 +2568,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_dp_set_clock(encoder, pipe_config);
intel_psr_compute_config(intel_dp, pipe_config);
+ intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
return 0;
}
--
2.24.1
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[Intel-gfx] [PATCH 01/18] drm: add DP 1.4 VSC SDP Payload related enums
It adds new enumeration definitions for VSC SDP Payload for Pixel
Encoding/Colorimetry Format.
enum dp_colorspace and enum dp_colorimetry correspond "Pixel Encoding and
Colorimetry Formats". enum dp_dynamic_range corresponds "Dynamic Range".
And enum dp_content_type corresponds "Content Type"
All of them are based on DP 1.4 spec [Table 2-117: VSC SDP Payload for
DB16 through DB18].
Signed-off-by: Gwan-gyeong Mun
---
include/drm/drm_dp_helper.h | 45 +
1 file changed, 45 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 262faf9e5e94..86b1be958a69 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1209,6 +1209,51 @@ struct dp_sdp {
#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
+/* Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through DB18] */
+enum dp_colorspace {
+ DP_COLORSPACE_RGB = 0,
+ DP_COLORSPACE_YUV444 = 0x1,
+ DP_COLORSPACE_YUV422 = 0x2,
+ DP_COLORSPACE_YUV420 = 0x3,
+ DP_COLORSPACE_Y_ONLY = 0x4,
+ DP_COLORSPACE_RAW = 0x5,
+ DP_COLORSPACE_RESERVED = 0x6,
+};
+
+/**
+ * Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through DB18]
+ * and a name of enum member followes DRM_MODE_COLORIMETRY definition.
+ */
+enum dp_colorimetry {
+ DP_COLORIMETRY_DEFAULT = 0, /* sRGB (IEC 61966-2-1) / ITU-R BT.601 */
+ DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
+ DP_COLORIMETRY_BT709_YCC = 0x1,
+ DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
+ DP_COLORIMETRY_XVYCC_601 = 0x2,
+ DP_COLORIMETRY_OPRGB = 0x3,
+ DP_COLORIMETRY_XVYCC_709 = 0x3,
+ DP_COLORIMETRY_DCI_P3_RGB = 0x4,
+ DP_COLORIMETRY_SYCC_601 = 0x4,
+ DP_COLORIMETRY_RGB_CUSTOM = 0x5,
+ DP_COLORIMETRY_OPYCC_601 = 0x5,
+ DP_COLORIMETRY_BT2020_RGB = 0x6,
+ DP_COLORIMETRY_BT2020_CYCC = 0x6,
+ DP_COLORIMETRY_BT2020_YCC = 0x7,
+};
+
+enum dp_dynamic_range {
+ DP_DYNAMIC_RANGE_VESA = 0,
+ DP_DYNAMIC_RANGE_CTA = 1,
+};
+
+enum dp_content_type {
+ DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
+ DP_CONTENT_TYPE_GRAPHICS = 0x01,
+ DP_CONTENT_TYPE_PHOTO = 0x02,
+ DP_CONTENT_TYPE_VIDEO = 0x03,
+ DP_CONTENT_TYPE_GAME = 0x04,
+};
+
int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
static inline int
--
2.24.1
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[Intel-gfx] [PATCH 05/18] drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet)
It adds routines that write DP VSC SDP and DP HDR Metadata Infoframe SDP.
In order to pack DP VSC SDP, it adds intel_dp_vsc_sdp_pack() function.
It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
[Table 2-117: VSC SDP Payload for DB16 through DB18]
In order to pack DP HDR Metadata Infoframe SDP, it adds
intel_dp_hdr_metadata_infoframe_sdp_pack() function.
And it follows DP 1.4a spec.
([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and
[Table 2-126: INFOFRAME SDP v1.2 Payload Data Bytes - DB0 through DB31])
and CTA-861-G spec. [Table-42 Dynamic Range and Mastering InfoFrame].
A machanism and a naming rule of intel_dp_set_infoframes() function
references intel_encoder->set_infoframes() of intel_hdmi.c .
VSC SDP is used for PSR and Pixel Encoding and Colorimetry Formats cases.
Because PSR routine has its own routine of writing a VSC SDP, when the PSR
is enabled, intel_dp_set_infoframes() does not write a VSC SDP.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 190
drivers/gpu/drm/i915/display/intel_dp.h | 3 +
2 files changed, 193 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 64e697445085..609444cbb29f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4730,6 +4730,196 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state
*crtc_state,
return false;
}
+static ssize_t intel_dp_vsc_sdp_pack(const struct intel_dp_vsc_sdp *vsc,
+struct dp_sdp *sdp, size_t size)
+{
+ size_t length = sizeof(struct dp_sdp);
+
+ if (size < length)
+ return -ENOSPC;
+
+ memset(sdp, 0, size);
+
+ /*
+* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
+* VSC SDP Header Bytes
+*/
+ sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
+ sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
+ sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
+ sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
+
+ /* VSC SDP Payload for DB16 through DB18 */
+ /* Pixel Encoding and Colorimetry Formats */
+ sdp->db[16] = (vsc->colorspace & 0xf) << 4; /* DB16[7:4] */
+ sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
+
+ switch (vsc->bpc) {
+ case 8:
+ sdp->db[17] = 0x1; /* DB17[3:0] */
+ break;
+ case 10:
+ sdp->db[17] = 0x2;
+ break;
+ case 12:
+ sdp->db[17] = 0x3;
+ break;
+ case 16:
+ sdp->db[17] = 0x4;
+ break;
+ default:
+ MISSING_CASE(vsc->bpc);
+ break;
+ }
+ /* Dynamic Range and Component Bit Depth */
+ if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
+ sdp->db[17] |= 0x80; /* DB17[7] */
+
+ /* Content Type */
+ sdp->db[18] = vsc->content_type & 0x7;
+
+ return length;
+}
+
+static ssize_t
+intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe
*drm_infoframe,
+struct dp_sdp *sdp,
+size_t size)
+{
+ size_t length = sizeof(struct dp_sdp);
+ const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE +
HDMI_DRM_INFOFRAME_SIZE;
+ unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
+ ssize_t len;
+
+ if (size < length)
+ return -ENOSPC;
+
+ memset(sdp, 0, size);
+
+ len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
+ if (len < 0) {
+ DRM_DEBUG_KMS("buffer size is smaller than hdr metadata
infoframe\n");
+ return -ENOSPC;
+ }
+
+ if (len != infoframe_size) {
+ DRM_DEBUG_KMS("wrong static hdr metadata size\n");
+ return -ENOSPC;
+ }
+
+ /*
+* Set up the infoframe sdp packet for HDR static metadata.
+* Prepare VSC Header for SU as per DP 1.4a spec,
+* Table 2-100 and Table 2-101
+*/
+
+ /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
+ sdp->sdp_header.HB0 = 0;
+ /*
+* Packet Type 80h + Non-audio INFOFRAME Type value
+* HDMI_INFOFRAME_TYPE_DRM: 0x87
+* - 80h + Non-audio INFOFRAME Type value
+* - InfoFrame Type: 0x07
+*[CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
+*/
+ sdp->sdp_header.HB1 = drm_infoframe->type;
+ /*
+* Least Significant Eight Bits of (Data Byte Count – 1)
+* infoframe_size - 1
+*/
+ sdp->sdp_header.HB2 = 0x1D;
+ /* INFOFRAME SDP Version Number */
+ sdp->sdp_header.HB3 = (0x13 << 2);
+ /* CTA Header Byte 2 (INFOFRAME Version Number) */
+
[Intel-gfx] [PATCH 00/18] In order to readout DP SDPs, refactors the handling of DP SDPs
In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes. It adds new compute routines for DP HDR Metadata Infoframe SDP and DP VSC SDP. And new writing routines of DP SDPs (Secondary Data Packet) that uses computed configs. New reading routines of DP SDPs are added for readout. It adds a logging function for DP VSC SDP. When receiving video it is very useful to be able to log DP VSC SDP. This greatly simplifies debugging. In order to use a common VSC SDP Colorimetry calculating code on PSR, it uses a new psr vsc sdp compute routine. Gwan-gyeong Mun (18): drm: add DP 1.4 VSC SDP Payload related enums drm/i915: Add DP VSC SDP payload data to intel_crtc_state.infoframes drm/i915/dp: Add compute routine for DP VSC SDP drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet) video/hdmi: Add Unpack only function for DRM infoframe drm/i915/dp: Read out DP SDPs (Secondary Data Packet) drm/i915/dp: Add logging function for DP VSC SDP drm/i915: Include HDMI DRM infoframe in the crtc state dump drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump drm/i915: Include DP VSC SDP in the crtc state dump drm/i915: Program DP SDPs with computed configs drm/i915: Add state readout for DP HDR Metadata Infoframe SDP drm/i915: Add state readout for DP VSC SDP drm/i915: Program DP SDPs on pipe updates drm/i915: Stop sending DP SDPs on intel_ddi_post_disable_dp() drm/i915/dp: Add compute routine for DP PSR VSC SDP drm/i915/psr: Use new DP VSC SDP compute routine on PSR drivers/gpu/drm/i915/display/intel_ddi.c | 19 +- drivers/gpu/drm/i915/display/intel_display.c | 62 ++ .../drm/i915/display/intel_display_types.h| 1 + drivers/gpu/drm/i915/display/intel_dp.c | 775 ++ drivers/gpu/drm/i915/display/intel_dp.h | 21 +- drivers/gpu/drm/i915/display/intel_psr.c | 54 +- drivers/gpu/drm/i915/display/intel_psr.h | 6 +- drivers/gpu/drm/i915/i915_drv.h | 12 + drivers/video/hdmi.c | 58 +- include/drm/drm_dp_helper.h | 45 + include/linux/hdmi.h | 2 + 11 files changed, 837 insertions(+), 218 deletions(-) -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/18] drm/i915: Add DP VSC SDP payload data to intel_crtc_state.infoframes
In order to support state readout for DP VSC SDP, we need to have a
structure which holds DP VSC SDP payload data such as
"union hdmi_infoframe drm" which is used for DRM infoframe.
And In order to support DP HDR10, we have to support VSC SDP and
HDR Metadata Infoframe SDP. As we will use drm member variable of
intel_crtc_state.infoframes, we only need to add vsc sdp member variable
to intel_crtc_state.infoframes.
Because DP SDP payload type does not have common structure like as
"union hdmi_infoframe", it adds "struct intel_dp_vsc_sdp"
to intel_display_types.h
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_display_types.h | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 33ba93863488..81112d63342c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -780,6 +780,17 @@ enum intel_output_format {
INTEL_OUTPUT_FORMAT_YCBCR444,
};
+struct intel_dp_vsc_sdp {
+ unsigned char sdp_type; /* Secondary-data Packet Type */
+ unsigned char revision; /* Revision Number */
+ unsigned char length; /* Number of Valid Data Bytes */
+ enum dp_colorspace colorspace;
+ enum dp_colorimetry colorimetry;
+ int bpc;
+ enum dp_dynamic_range dynamic_range;
+ enum dp_content_type content_type;
+};
+
struct intel_crtc_state {
/*
* uapi (drm) state. This is the software state shown to userspace.
@@ -1021,6 +1032,7 @@ struct intel_crtc_state {
union hdmi_infoframe spd;
union hdmi_infoframe hdmi;
union hdmi_infoframe drm;
+ struct intel_dp_vsc_sdp vsc;
} infoframes;
/* HDMI scrambling status */
--
2.24.1
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[Intel-gfx] [PATCH 1/2] drm/i915/tracepoints: Don't compile-out low-level tracepoints
Hi! I use GPUVis and now Intel Vtune Profiler. These tools don't work out-of-the-box on all Linux based systems for Intel integrated graphics. It is needed to rebuild at least i915 module. And each time when the kernel is updated it is needed to rebuild i915 module again. > No numbers from (micro-)bechmarks showing how small the impact of doing > this is? I thought John was compiling this data. It will be just a no-op > on the fast path, but a bit more generated code. Have you collected the results? If not, I've done it for you: Benchmark for Metro 2033 Last Light Redux: w/o events: 1st run aver. fps: 36.06 2nd run aver. fps: 35.87 w events: 1st run aver. fps: 36.05 2nd run aver. fps: 35.92 There is no difference. It was run on Intel Core i9-9900K CPU @ 3.60GHz on integrated graphics. > Assuming that will be fine, the only potentially problematic aspect that > comes to mind is the fact meaning of these tracepoints is a bit > different between execlists and guc. But maybe that is thinking to low > level (!) - in fact they are in both cases at points where i915 is >passing/receiving requests to/from hardware so not an issue? In my view, it is not an issue. The real issue now that you cannot collect performance results for Intel GPU on Linux systems without rebuilding the i915 module. You cannot debug performance problems on the system even if you use tools from Intel. Do you have ETA for accepting this patch? Thanks, Egor ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH V5] drm: Add support for DP 1.4 Compliance edid corruption test
On 2020-01-31 3:24 p.m., Jerry (Fangzhi) Zuo wrote:
> Unlike DP 1.2 edid corruption test, DP 1.4 requires to calculate
> real CRC value of the last edid data block, and write it back.
> Current edid CRC calculates routine adds the last CRC byte,
> and check if non-zero.
>
> This behavior is not accurate; actually, we need to return
> the actual CRC value when corruption is detected.
> This commit changes this issue by returning the calculated CRC,
> and initiate the required sequence.
>
> Change since v5
> - Obtain real CRC value before dumping bad edid
>
> Change since v4
> - Fix for CI.CHECKPATCH
>
> Change since v3
> - Fix a minor typo.
>
> Change since v2
> - Rewrite checksum computation routine to avoid duplicated code.
> - Rename to avoid confusion.
>
> Change since v1
> - Have separate routine for returning real CRC.
>
> Signed-off-by: Jerry (Fangzhi) Zuo
Reviewed-by: Harry Wentland
Harry
> ---
> drivers/gpu/drm/drm_dp_helper.c | 35 +
> drivers/gpu/drm/drm_edid.c | 23 ++
> include/drm/drm_connector.h | 6 ++
> include/drm/drm_dp_helper.h | 3 +++
> 4 files changed, 63 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index f629fc5494a4..18b285fa1a42 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -351,6 +351,41 @@ int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
> }
> EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
>
> +/**
> + * drm_dp_send_real_edid_checksum() - send back real edid checksum value
> + * @aux: DisplayPort AUX channel
> + * @real_edid_checksum: real edid checksum for the last block
> + *
> + * Returns true on success
> + */
> +bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
> +u8 real_edid_checksum)
> +{
> + u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0;
> +
> + drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, _test_req, 1);
> + auto_test_req &= DP_AUTOMATED_TEST_REQUEST;
> +
> + drm_dp_dpcd_read(aux, DP_TEST_REQUEST, _edid_read, 1);
> + link_edid_read &= DP_TEST_LINK_EDID_READ;
> +
> + if (!auto_test_req || !link_edid_read) {
> + DRM_DEBUG_KMS("Source DUT does not support TEST_EDID_READ\n");
> + return false;
> + }
> +
> + drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, _test_req, 1);
> +
> + /* send back checksum for the last edid extension block data */
> + drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM, _edid_checksum, 1);
> +
> + test_resp |= DP_TEST_EDID_CHECKSUM_WRITE;
> + drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, _resp, 1);
> +
> + return true;
> +}
> +EXPORT_SYMBOL(drm_dp_send_real_edid_checksum);
> +
> /**
> * drm_dp_downstream_max_clock() - extract branch device max
> * pixel rate for legacy VGA
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 99769d6c9f84..f064e75fb4c5 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -1590,11 +1590,22 @@ static int validate_displayid(u8 *displayid, int
> length, int idx);
> static int drm_edid_block_checksum(const u8 *raw_edid)
> {
> int i;
> - u8 csum = 0;
> - for (i = 0; i < EDID_LENGTH; i++)
> + u8 csum = 0, crc = 0;
> +
> + for (i = 0; i < EDID_LENGTH - 1; i++)
> csum += raw_edid[i];
>
> - return csum;
> + crc = 0x100 - csum;
> +
> + return crc;
> +}
> +
> +static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8
> real_checksum)
> +{
> + if (raw_edid[EDID_LENGTH - 1] != real_checksum)
> + return true;
> + else
> + return false;
> }
>
> static bool drm_edid_is_zero(const u8 *in_edid, int length)
> @@ -1652,7 +1663,7 @@ bool drm_edid_block_valid(u8 *raw_edid, int block, bool
> print_bad_edid,
> }
>
> csum = drm_edid_block_checksum(raw_edid);
> - if (csum) {
> + if (drm_edid_block_checksum_diff(raw_edid, csum)) {
> if (edid_corrupt)
> *edid_corrupt = true;
>
> @@ -1793,6 +1804,10 @@ static void connector_bad_edid(struct drm_connector
> *connector,
> u8 *edid, int num_blocks)
> {
> int i;
> + u8 num_of_ext = edid[0x7e];
> +
> + /* Calculate real checksum for the last edid extension block data */
> + connector->real_edid_checksum = drm_edid_block_checksum(edid +
> num_of_ext * EDID_LENGTH);
>
> if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
> return;
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index 2113500b4075..b3815371c271 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -1357,6 +1357,12 @@ struct drm_connector {
>* rev1.1 4.2.2.6
>*/
> bool edid_corrupt;
> +
Re: [Intel-gfx] [PATCH 1/2] drm/i915/tracepoints: Don't compile-out low-level tracepoints
Hi! I use GPUVis and now Intel Vtune Profiler. These tools don't work out-of-the-box on all Linux based systems for Intel integrated graphics. It is needed to rebuild at least i915 module. And each time when the kernel is updated it is needed to rebuild i915 module again. > No numbers from (micro-)bechmarks showing how small the impact of doing > this is? I thought John was compiling this data. It will be just a no-op > on the fast path, but a bit more generated code. Have you collected the results? If not, I've done it for you: Benchmark for Metro 2033 Last Light Redux: w/o events: 1st run aver. fps: 36.06 2nd run aver. fps: 35.87 w events: 1st run aver. fps: 36.05 2nd run aver. fps: 35.92 There is no difference. It was run on Intel Core i9-9900K CPU @ 3.60GHz on integrated graphics. > Assuming that will be fine, the only potentially problematic aspect that > comes to mind is the fact meaning of these tracepoints is a bit > different between execlists and guc. But maybe that is thinking to low > level (!) - in fact they are in both cases at points where i915 is >passing/receiving requests to/from hardware so not an issue? In my view, it is not an issue. The real issue now that you cannot collect performance results for Intel GPU on Linux systems without rebuilding the i915 module. You cannot debug performance problems on the system even if you use tools from Intel. Do you have ETA to accept this patch? Thanks, Egor ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH V5] drm: Add support for DP 1.4 Compliance edid corruption test
Unlike DP 1.2 edid corruption test, DP 1.4 requires to calculate
real CRC value of the last edid data block, and write it back.
Current edid CRC calculates routine adds the last CRC byte,
and check if non-zero.
This behavior is not accurate; actually, we need to return
the actual CRC value when corruption is detected.
This commit changes this issue by returning the calculated CRC,
and initiate the required sequence.
Change since v5
- Obtain real CRC value before dumping bad edid
Change since v4
- Fix for CI.CHECKPATCH
Change since v3
- Fix a minor typo.
Change since v2
- Rewrite checksum computation routine to avoid duplicated code.
- Rename to avoid confusion.
Change since v1
- Have separate routine for returning real CRC.
Signed-off-by: Jerry (Fangzhi) Zuo
---
drivers/gpu/drm/drm_dp_helper.c | 35 +
drivers/gpu/drm/drm_edid.c | 23 ++
include/drm/drm_connector.h | 6 ++
include/drm/drm_dp_helper.h | 3 +++
4 files changed, 63 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index f629fc5494a4..18b285fa1a42 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -351,6 +351,41 @@ int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
}
EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
+/**
+ * drm_dp_send_real_edid_checksum() - send back real edid checksum value
+ * @aux: DisplayPort AUX channel
+ * @real_edid_checksum: real edid checksum for the last block
+ *
+ * Returns true on success
+ */
+bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
+u8 real_edid_checksum)
+{
+ u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0;
+
+ drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, _test_req, 1);
+ auto_test_req &= DP_AUTOMATED_TEST_REQUEST;
+
+ drm_dp_dpcd_read(aux, DP_TEST_REQUEST, _edid_read, 1);
+ link_edid_read &= DP_TEST_LINK_EDID_READ;
+
+ if (!auto_test_req || !link_edid_read) {
+ DRM_DEBUG_KMS("Source DUT does not support TEST_EDID_READ\n");
+ return false;
+ }
+
+ drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, _test_req, 1);
+
+ /* send back checksum for the last edid extension block data */
+ drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM, _edid_checksum, 1);
+
+ test_resp |= DP_TEST_EDID_CHECKSUM_WRITE;
+ drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, _resp, 1);
+
+ return true;
+}
+EXPORT_SYMBOL(drm_dp_send_real_edid_checksum);
+
/**
* drm_dp_downstream_max_clock() - extract branch device max
* pixel rate for legacy VGA
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 99769d6c9f84..f064e75fb4c5 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1590,11 +1590,22 @@ static int validate_displayid(u8 *displayid, int
length, int idx);
static int drm_edid_block_checksum(const u8 *raw_edid)
{
int i;
- u8 csum = 0;
- for (i = 0; i < EDID_LENGTH; i++)
+ u8 csum = 0, crc = 0;
+
+ for (i = 0; i < EDID_LENGTH - 1; i++)
csum += raw_edid[i];
- return csum;
+ crc = 0x100 - csum;
+
+ return crc;
+}
+
+static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum)
+{
+ if (raw_edid[EDID_LENGTH - 1] != real_checksum)
+ return true;
+ else
+ return false;
}
static bool drm_edid_is_zero(const u8 *in_edid, int length)
@@ -1652,7 +1663,7 @@ bool drm_edid_block_valid(u8 *raw_edid, int block, bool
print_bad_edid,
}
csum = drm_edid_block_checksum(raw_edid);
- if (csum) {
+ if (drm_edid_block_checksum_diff(raw_edid, csum)) {
if (edid_corrupt)
*edid_corrupt = true;
@@ -1793,6 +1804,10 @@ static void connector_bad_edid(struct drm_connector
*connector,
u8 *edid, int num_blocks)
{
int i;
+ u8 num_of_ext = edid[0x7e];
+
+ /* Calculate real checksum for the last edid extension block data */
+ connector->real_edid_checksum = drm_edid_block_checksum(edid +
num_of_ext * EDID_LENGTH);
if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
return;
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 2113500b4075..b3815371c271 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -1357,6 +1357,12 @@ struct drm_connector {
* rev1.1 4.2.2.6
*/
bool edid_corrupt;
+ /**
+* @real_edid_checksum: real edid checksum for corrupted edid block.
+* Required in Displayport 1.4 compliance testing
+* rev1.1 4.2.2.6
+*/
+ u8 real_edid_checksum;
/** @debugfs_entry: debugfs directory for this connector */
Re: [Intel-gfx] [PATCH 1/2] drm/i915/tracepoints: Don't compile-out low-level tracepoints
Hi!I use GPUVis and now Intel Vtune Profiler. These tools don't work out-of-the-box on all Linux based systems for Intel integrated graphics.It is needed to rebuild at least i915 module. And each time when the kernel is updated it is needed to rebuild i915 module again. > No numbers from (micro-)bechmarks showing how small the impact of doing> this is? I thought John was compiling this data. It will be just a no-op> on the fast path, but a bit more generated code.Have you collected the results? If not, I've done it for you:Benchmark for Metro 2033 Last Light Redux:w/o events:1st run aver. fps: 36.062nd run aver. fps: 35.87w events:1st run aver. fps: 36.052nd run aver. fps: 35.92 There is no difference. It was run on Intel Core i9-9900K CPU @ 3.60GHz on integrated graphics. > Assuming that will be fine, the only potentially problematic aspect that> comes to mind is the fact meaning of these tracepoints is a bit> different between execlists and guc. But maybe that is thinking to low> level (!) - in fact they are in both cases at points where i915 is>passing/receiving requests to/from hardware so not an issue?In my view, it is not an issue. The real issue now that you cannot collect performance results for Intel GPUon Linux systems without rebuilding the i915 module. You cannot debug performance problemson the system even if you use tools from Intel. Do you have ETA to accept this patch? Thanks,Egor___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/tracepoints: Don't compile-out low-level tracepoints
Hi! I use GPUVis and now Intel Vtune Profiler. These tools don't work out-of-the-box on all Linux based systems for Intel integrated graphics. It is needed to rebuild at least i915 module. And each time when the kernel is updated it is needed to rebuild i915 module again. > No numbers from (micro-)bechmarks showing how small the impact of doing > this is? I thought John was compiling this data. It will be just a no-op > on the fast path, but a bit more generated code. Have you collected the results? If not, I've done it for you: Benchmark for Metro 2033 Last Light Redux: w/o events: 1st run aver. fps: 36.06 2nd run aver. fps: 35.87 w events: 1st run aver. fps: 36.05 2nd run aver. fps: 35.92 There is no difference. It was run on Intel Core i9-9900K CPU @ 3.60GHz on integrated graphics. > Assuming that will be fine, the only potentially problematic aspect that > comes to mind is the fact meaning of these tracepoints is a bit > different between execlists and guc. But maybe that is thinking to low > level (!) - in fact they are in both cases at points where i915 is >passing/receiving requests to/from hardware so not an issue? In my view, it is not an issue. The real issue now that you cannot collect performance results for Intel GPU on Linux systems without rebuilding the i915 module. You cannot debug performance problems on the system even if you use tools from Intel. Do you have ETA to accept this patch? Thanks, Egor ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/tracepoints: Don't compile-out low-level tracepoints
Hi! I use GPUVis and now Intel Vtune Profiler. These tools don't work out-of-the-box on all Linux based systems for Intel integrated graphics. It is needed to rebuild at least i915 module. And each time when the kernel is updated it is needed to rebuild i915 module again. > No numbers from (micro-)bechmarks showing how small the impact of doing > this is? I thought John was compiling this data. It will be just a no-op > on the fast path, but a bit more generated code. Have you collected the results? If not, I've done it for you: Benchmark for Metro 2033 Last Light Redux: w/o events: 1st run aver. fps: 36.06 2nd run aver. fps: 35.87 w events: 1st run aver. fps: 36.05 2nd run aver. fps: 35.92 There is no difference. It was run on Intel Core i9-9900K CPU @ 3.60GHz on integrated graphics. > Assuming that will be fine, the only potentially problematic aspect that > comes to mind is the fact meaning of these tracepoints is a bit > different between execlists and guc. But maybe that is thinking to low > level (!) - in fact they are in both cases at points where i915 is >passing/receiving requests to/from hardware so not an issue? In my view, it is not an issue. The real issue now that you cannot collect performance results for Intel GPU on Linux systems without rebuilding the i915 module. You cannot debug performance problems on the system even if you use tools from Intel. Do you have ETA to accept this patch? Thanks, Egor ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/perf: Fix OA context id overlap with idle context id
On Fri, Jan 31, 2020 at 01:00:54PM +0200, Lionel Landwerlin wrote:
On 31/01/2020 01:54, Umesh Nerlige Ramappa wrote:
On Mon, Jan 27, 2020 at 11:16:32AM +0200, Lionel Landwerlin wrote:
[snip]
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1323,7 +1323,12 @@ static int
oa_get_render_ctx_id(struct i915_perf_stream *stream)
case 12: {
stream->specific_ctx_id_mask =
((1U << GEN11_SW_CTX_ID_WIDTH) - 1) <<
(GEN11_SW_CTX_ID_SHIFT - 32);
- stream->specific_ctx_id = stream->specific_ctx_id_mask;
+ /* Pick an unused context id
+ * 0 - (NUM_CONTEXT_TAG - 1) are used by other contexts
+ * GEN12_MAX_CONTEXT_HW_ID (0x7ff) is used by idle context
+ */
+ stream->specific_ctx_id = (GEN12_MAX_CONTEXT_HW_ID
- 1) << (GEN11_SW_CTX_ID_SHIFT - 32);
+ BUILD_BUG_ON((GEN12_MAX_CONTEXT_HW_ID - 1) <
NUM_CONTEXT_TAG);
Arg yeah, we can't use an id that has all bits to 1 because
that matches the idle value in the OA reports :/
This also affects gen8-10 cases (afaik).
For gen8-10, I did not see a specific definition for an idle
context id. The from/to idle context switches are indicated by
dedicated bits in the CSB instead (from spec).
I meant that I remember the periodic OA reports when HW is idle to
have the contex_id=0x.
For these gens we use 0x1f as the context id. Before we return
reports to the user, we are setting context id to 0x for
invalid and irrelevant contexts.
Thanks,
Umesh
Sorry, I've been a bit out of the loop on OA reports lately.
I just noticed that the context valid bit is not checked on gen12 anymore.
The documentation is really horrible, but BSpec 52198 seems to
indicate the bit is still around.
I am looking at the first table describing the report ID in 52198 which
has TGL next to it. I don't see a definition for this bit.
I will try to ask around to see if that's not the case.
Could it be the source of the issue?
You mean - seeing 0x during idle in periodic reports?
Thanks,
Umesh
Thanks for your help :)
-Lionel
I could remember wrong :/
-Lionel
Thanks,
Umesh
Thanks for spotting this!
-Lionel
break;
}
@@ -1331,7 +1336,7 @@ static int oa_get_render_ctx_id(struct
i915_perf_stream *stream)
MISSING_CASE(INTEL_GEN(ce->engine->i915));
}
- ce->tag = stream->specific_ctx_id_mask;
+ ce->tag = stream->specific_ctx_id;
DRM_DEBUG_DRIVER("filtering on ctx_id=0x%x ctx_id_mask=0x%x\n",
stream->specific_ctx_id,
___
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Re: [Intel-gfx] [PATCH 3/3] drm/i915/dp: Add all tiled and port sync conns to modeset
On Fri, Jan 31, 2020 at 10:05:03PM +0200, Ville Syrjälä wrote:
> On Fri, Jan 31, 2020 at 11:46:25AM -0800, Manasi Navare wrote:
> > On Fri, Jan 31, 2020 at 07:53:23PM +0200, Ville Syrjälä wrote:
> > > On Fri, Jan 31, 2020 at 09:15:47AM -0800, Manasi Navare wrote:
> > > > If one of the synced crtcs needs a full modeset, we need
> > > > to make sure all the synced crtcs are forced a full
> > > > modeset.
> > > >
> > > > Suggested-by: Ville Syrjälä
> > > > Cc: Ville Syrjälä
> > > > Signed-off-by: Manasi Navare
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_display.c | 88 +
> > > > drivers/gpu/drm/i915/display/intel_dp.c | 131 ++-
> > > > 2 files changed, 131 insertions(+), 88 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index e638543f5f87..709a737638b6 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -13123,8 +13123,7 @@ intel_modeset_pipe_config(struct
> > > > intel_crtc_state *pipe_config)
> > > > struct drm_i915_private *i915 =
> > > > to_i915(pipe_config->uapi.crtc->dev);
> > > > struct drm_connector *connector;
> > > > struct drm_connector_state *connector_state;
> > > > - int base_bpp, ret;
> > > > - int i, tile_group_id = -1, num_tiled_conns = 0;
> > > > + int base_bpp, ret, i;
> > > > bool retry = true;
> > > >
> > > > pipe_config->cpu_transcoder =
> > > > @@ -14559,76 +14558,6 @@ static bool
> > > > intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
> > > > return false;
> > > > }
> > > >
> > > > -static int
> > > > -intel_modeset_all_tiles(struct intel_atomic_state *state, int
> > > > tile_grp_id)
> > > > -{
> > > > - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > - struct drm_connector *connector;
> > > > - struct drm_connector_list_iter conn_iter;
> > > > - int ret = 0;
> > > > -
> > > > - drm_connector_list_iter_begin(_priv->drm, _iter);
> > > > - drm_for_each_connector_iter(connector, _iter) {
> > > > - struct drm_connector_state *conn_state;
> > > > - struct drm_crtc_state *crtc_state;
> > > > -
> > > > - if (!connector->has_tile ||
> > > > - connector->tile_group->id != tile_grp_id)
> > > > - continue;
> > > > - conn_state =
> > > > drm_atomic_get_connector_state(>base,
> > > > - connector);
> > > > - if (IS_ERR(conn_state)) {
> > > > - ret = PTR_ERR(conn_state);
> > > > - break;
> > > > - }
> > > > -
> > > > - if (!conn_state->crtc)
> > > > - continue;
> > > > -
> > > > - crtc_state = drm_atomic_get_crtc_state(>base,
> > > > -
> > > > conn_state->crtc);
> > > > - if (IS_ERR(crtc_state)) {
> > > > - ret = PTR_ERR(crtc_state);
> > > > - break;
> > > > - }
> > > > - crtc_state->mode_changed = true;
> > > > - ret = drm_atomic_add_affected_connectors(>base,
> > > > -
> > > > conn_state->crtc);
> > > > - if (ret)
> > > > - break;
> > > > - }
> > > > - drm_connector_list_iter_end(_iter);
> > > > -
> > > > - return ret;
> > > > -}
> > > > -
> > > > -static int
> > > > -intel_atomic_check_tiled_conns(struct intel_atomic_state *state)
> > > > -{
> > > > - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > - struct drm_connector *connector;
> > > > - struct drm_connector_state *old_conn_state, *new_conn_state;
> > > > - int i, ret;
> > > > -
> > > > - if (INTEL_GEN(dev_priv) < 11)
> > > > - return 0;
> > > > -
> > > > - /* Is tiled, mark all other tiled CRTCs as needing a modeset */
> > > > - for_each_oldnew_connector_in_state(>base, connector,
> > > > - old_conn_state,
> > > > new_conn_state, i) {
> > > > - if (!connector->has_tile)
> > > > - continue;
> > > > - if (!intel_connector_needs_modeset(state, connector))
> > > > - continue;
> > > > -
> > > > - ret = intel_modeset_all_tiles(state,
> > > > connector->tile_group->id);
> > > > - if (ret)
> > > > - return ret;
> > > > - }
> > > > -
> > > > - return 0;
> > > > -}
> > > > -
> > > > /**
> > > > * intel_atomic_check - validate state object
> > > > * @dev: drm device
> > > > @@
[Intel-gfx] [PATCH 2/4] drm/i915: Initialise basic fence before acquiring seqno
Inside the intel_timeline_get_seqno(), we currently track the retirement of the old cachelines by listening to the new request. This requires that the new request is ready to be used and so requires a minimum bit of initialisation prior to getting the new seqno. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Matthew Auld --- drivers/gpu/drm/i915/i915_request.c | 21 ++--- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 78a5f5d3c070..f56b046a32de 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -595,6 +595,8 @@ static void __i915_request_ctor(void *arg) i915_sw_fence_init(>submit, submit_notify); i915_sw_fence_init(>semaphore, semaphore_notify); + dma_fence_init(>fence, _fence_ops, >lock, 0, 0); + rq->file_priv = NULL; rq->capture_list = NULL; @@ -653,25 +655,30 @@ __i915_request_create(struct intel_context *ce, gfp_t gfp) } } - ret = intel_timeline_get_seqno(tl, rq, ); - if (ret) - goto err_free; - rq->i915 = ce->engine->i915; rq->context = ce; rq->engine = ce->engine; rq->ring = ce->ring; rq->execution_mask = ce->engine->mask; + kref_init(>fence.refcount); + rq->fence.flags = 0; + rq->fence.error = 0; + INIT_LIST_HEAD(>fence.cb_list); + + ret = intel_timeline_get_seqno(tl, rq, ); + if (ret) + goto err_free; + + rq->fence.context = tl->fence_context; + rq->fence.seqno = seqno; + RCU_INIT_POINTER(rq->timeline, tl); RCU_INIT_POINTER(rq->hwsp_cacheline, tl->hwsp_cacheline); rq->hwsp_seqno = tl->hwsp_seqno; rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */ - dma_fence_init(>fence, _fence_ops, >lock, - tl->fence_context, seqno); - /* We bump the ref for the fence chain */ i915_sw_fence_reinit(_request_get(rq)->submit); i915_sw_fence_reinit(_request_get(rq)->semaphore); -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/4] drm/i915/display: Wake the power well during resume
Acquire the power well before writing the setup during resume so that
our mmio are not dropped. E.g. on Braswell we see,
<4> [135.959703] i915 :00:02.0: Unclaimed write to register 0x1e0100
<4> [135.959936] WARNING: CPU: 1 PID: 3085 at
drivers/gpu/drm/i915/intel_uncore.c:1166 __unclaimed_reg_debug+0x69/0x80 [i915]
<4> [135.959944] Modules linked in: vgem snd_hda_codec_hdmi
snd_hda_codec_realtek snd_hda_codec_generic i915 coretemp btusb
crct10dif_pclmul btrtl crc32_pclmul btbcm btintel snd_hda_intel
ghash_clmulni_intel snd_intel_dspcfg bluetooth snd_hda_codec snd_hwdep
ecdh_generic ecc snd_hda_core r8169 realtek snd_pcm lpc_ich prime_numbers
pinctrl_cherryview
<4> [135.960011] CPU: 1 PID: 3085 Comm: kworker/u4:5 Tainted: G U
5.5.0-CI-CI_DRM_7849+ #1
<4> [135.960019] Hardware name: /NUC5CPYB, BIOS
PYBSWCEL.86A.0058.2016.1102.1842 11/02/2016
<4> [135.960033] Workqueue: events_unbound async_run_entry_fn
<4> [135.960189] RIP: 0010:__unclaimed_reg_debug+0x69/0x80 [i915]
<4> [135.960199] Code: 48 8b 78 18 48 8b 5f 50 48 85 db 74 2d e8 0f d1 43 e1 45
89 e8 48 89 e9 48 89 da 48 89 c6 48 c7 c7 58 4c 44 a0 e8 37 bd e3 e0 <0f> 0b 83
2d 7e cd 2b 00 01 5b 5d 41 5c 41 5d c3 48 8b 1f eb ce 66
<4> [135.960207] RSP: 0018:c947bd08 EFLAGS: 00010082
<4> [135.960217] RAX: RBX: 88817a0edb60 RCX:
0003
<4> [135.960225] RDX: 8003 RSI: RDI:
<4> [135.960232] RBP: a0485e86 R08: R09:
0001
<4> [135.960240] R10: d3945727 R11: 9a92dbc6 R12:
<4> [135.960248] R13: 001e0100 R14: 0286 R15:
8234a213
<4> [135.960257] FS: () GS:88817bd0()
knlGS:
<4> [135.960264] CS: 0010 DS: ES: CR0: 80050033
<4> [135.960272] CR2: 7f2f0dab2778 CR3: 00016f78c000 CR4:
001006e0
<4> [135.960279] Call Trace:
<4> [135.960448] fwtable_write32+0x114/0x1d0 [i915]
<4> [135.960633] intel_power_domains_init_hw+0x4ff/0x650 [i915]
<4> [135.960821] intel_power_domains_resume+0x3d/0x70 [i915]
<4> [135.960974] i915_drm_resume_early+0x97/0xd0 [i915]
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1089
Signed-off-by: Chris Wilson
Cc: Imre Deak
---
.../gpu/drm/i915/display/intel_display_power.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 64943179c05e..99463356be03 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5255,6 +5255,15 @@ void intel_power_domains_init_hw(struct drm_i915_private
*i915, bool resume)
/* Must happen before power domain init on VLV/CHV */
intel_update_rawclk(i915);
+ /*
+* Keep all power wells enabled for any dependent HW access during
+* initialization and to make sure we keep BIOS enabled display HW
+* resources powered until display HW readout is complete. We drop
+* this reference in intel_power_domains_enable().
+*/
+ power_domains->wakeref =
+ intel_display_power_get(i915, POWER_DOMAIN_INIT);
+
if (INTEL_GEN(i915) >= 11) {
icl_display_core_init(i915, resume);
} else if (IS_CANNONLAKE(i915)) {
@@ -5281,15 +5290,6 @@ void intel_power_domains_init_hw(struct drm_i915_private
*i915, bool resume)
intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915));
}
- /*
-* Keep all power wells enabled for any dependent HW access during
-* initialization and to make sure we keep BIOS enabled display HW
-* resources powered until display HW readout is complete. We drop
-* this reference in intel_power_domains_enable().
-*/
- power_domains->wakeref =
- intel_display_power_get(i915, POWER_DOMAIN_INIT);
-
/* Disable power support if the user asked so. */
if (!i915_modparams.disable_power_well)
intel_display_power_get(i915, POWER_DOMAIN_INIT);
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/4] drm/i915/selftests: Add a simple rollover for the kernel context
Exercise the seqno wrap paths on the kernel context to provide a small
amount of sanity checking and ensure that they are visible to lockdep.
Signed-off-by: Chris Wilson
Cc: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/selftest_timeline.c | 171
1 file changed, 171 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c
b/drivers/gpu/drm/i915/gt/selftest_timeline.c
index e2d78cc22fb4..ddbe029cbde8 100644
--- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
@@ -6,6 +6,8 @@
#include
+#include "intel_context.h"
+#include "intel_engine_heartbeat.h"
#include "intel_engine_pm.h"
#include "intel_gt.h"
#include "intel_gt_requests.h"
@@ -750,6 +752,173 @@ static int live_hwsp_wrap(void *arg)
return err;
}
+static void engine_heartbeat_disable(struct intel_engine_cs *engine,
+unsigned long *saved)
+{
+ *saved = engine->props.heartbeat_interval_ms;
+ engine->props.heartbeat_interval_ms = 0;
+
+ intel_engine_pm_get(engine);
+ intel_engine_park_heartbeat(engine);
+}
+
+static void engine_heartbeat_enable(struct intel_engine_cs *engine,
+ unsigned long saved)
+{
+ intel_engine_pm_put(engine);
+
+ engine->props.heartbeat_interval_ms = saved;
+}
+
+static int live_hwsp_rollover_kernel(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /*
+* Run the host for long enough, and even the kernel context will
+* see a seqno rollover.
+*/
+
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce = engine->kernel_context;
+ struct intel_timeline *tl = ce->timeline;
+ struct i915_request *rq[3] = {};
+ unsigned long heartbeat;
+ int i;
+
+ engine_heartbeat_disable(engine, );
+ if (intel_gt_wait_for_idle(gt, HZ / 2)) {
+ err = -EIO;
+ goto out;
+ }
+
+ GEM_BUG_ON(i915_active_fence_isset(>last_request));
+ tl->seqno = 0;
+ timeline_rollback(tl);
+ timeline_rollback(tl);
+ WRITE_ONCE(*(u32 *)tl->hwsp_seqno, tl->seqno);
+
+ for (i = 0; i < ARRAY_SIZE(rq); i++) {
+ rq[i] = i915_request_create(ce);
+ if (IS_ERR(rq[i])) {
+ err = PTR_ERR(rq[i]);
+ goto out;
+ }
+
+ pr_debug("%s: create fence.seqnp:%d\n",
+engine->name,
lower_32_bits(rq[i]->fence.seqno));
+ i915_request_get(rq[i]);
+ i915_request_add(rq[i]);
+ }
+
+ /* We expected a wrap! */
+ GEM_BUG_ON(rq[2]->fence.seqno > rq[0]->fence.seqno);
+
+ if (i915_request_wait(rq[2], 0, HZ / 5) < 0) {
+ pr_err("Wait for timeline wrap timed out!\n");
+ err = -EIO;
+ goto out;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(rq); i++) {
+ if (!i915_request_completed(rq[i])) {
+ pr_err("Pre-wrap request not completed!\n");
+ err = -EINVAL;
+ goto out;
+ }
+ }
+
+out:
+ for (i = 0; i < ARRAY_SIZE(rq); i++)
+ i915_request_put(rq[i]);
+ engine_heartbeat_enable(engine, heartbeat);
+ if (err)
+ break;
+ }
+
+ if (igt_flush_test(gt->i915))
+ err = -EIO;
+
+ return err;
+}
+
+static int live_hwsp_rollover_user(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /*
+* Run the host for long enough, and even the kernel context will
+* see a seqno rollover.
+*/
+
+ for_each_engine(engine, gt, id) {
+ struct i915_request *rq[3] = {};
+ struct intel_context *ce;
+ int i;
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ err = intel_context_alloc_state(ce);
+ if (err)
+ goto out;
+
+ timeline_rollback(ce->timeline);
+ timeline_rollback(ce->timeline);
+ WRITE_ONCE(*(u32 *)ce->timeline->hwsp_seqno,
+ ce->timeline->seqno);
+
+ for (i = 0; i < ARRAY_SIZE(rq); i++) {
+ rq[i] = intel_context_create_request(ce);
+
[Intel-gfx] [PATCH 3/4] drm/i915/gt: Warn about the hidden i915_vma_pin in timeline_get_seqno
On seqno rollover, we need to allocate ourselves a new cacheline. This might incur grabbing a new page and pinning it into the GGTT, with some rather unfortunate lockdep implications. To avoid a mutex, and more specifically pinning in the GGTT from inside the kernel context being used to flush the GGTT in emergencies, we will likely need to lift the next-cacheline allocation to a pre-reservation. Signed-off-by: Chris Wilson Cc: Maarten Lankhorst Reviewed-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gt/intel_timeline.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c index 465f87b65901..54e1e55f3c81 100644 --- a/drivers/gpu/drm/i915/gt/intel_timeline.c +++ b/drivers/gpu/drm/i915/gt/intel_timeline.c @@ -406,6 +406,8 @@ __intel_timeline_get_seqno(struct intel_timeline *tl, void *vaddr; int err; + might_lock(>gt->ggtt->vm.mutex); + /* * If there is an outstanding GPU reference to this cacheline, * such as it being sampled by a HW semaphore on another timeline, -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Initialise basic fence before acquiring seqno
Inside the intel_timeline_get_seqno(), we currently track the retirement of the old cachelines by listening to the new request. This requires that the new request is ready to be used and so requires a minimum bit of initialisation prior to getting the new seqno. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Matthew Auld --- drivers/gpu/drm/i915/i915_request.c | 21 ++--- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 78a5f5d3c070..f56b046a32de 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -595,6 +595,8 @@ static void __i915_request_ctor(void *arg) i915_sw_fence_init(>submit, submit_notify); i915_sw_fence_init(>semaphore, semaphore_notify); + dma_fence_init(>fence, _fence_ops, >lock, 0, 0); + rq->file_priv = NULL; rq->capture_list = NULL; @@ -653,25 +655,30 @@ __i915_request_create(struct intel_context *ce, gfp_t gfp) } } - ret = intel_timeline_get_seqno(tl, rq, ); - if (ret) - goto err_free; - rq->i915 = ce->engine->i915; rq->context = ce; rq->engine = ce->engine; rq->ring = ce->ring; rq->execution_mask = ce->engine->mask; + kref_init(>fence.refcount); + rq->fence.flags = 0; + rq->fence.error = 0; + INIT_LIST_HEAD(>fence.cb_list); + + ret = intel_timeline_get_seqno(tl, rq, ); + if (ret) + goto err_free; + + rq->fence.context = tl->fence_context; + rq->fence.seqno = seqno; + RCU_INIT_POINTER(rq->timeline, tl); RCU_INIT_POINTER(rq->hwsp_cacheline, tl->hwsp_cacheline); rq->hwsp_seqno = tl->hwsp_seqno; rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */ - dma_fence_init(>fence, _fence_ops, >lock, - tl->fence_context, seqno); - /* We bump the ref for the fence chain */ i915_sw_fence_reinit(_request_get(rq)->submit); i915_sw_fence_reinit(_request_get(rq)->semaphore); -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/gt: Warn about the hidden i915_vma_pin in timeline_get_seqno
On seqno rollover, we need to allocate ourselves a new cacheline. This might incur grabbing a new page and pinning it into the GGTT, with some rather unfortunate lockdep implications. To avoid a mutex, and more specifically pinning in the GGTT from inside the kernel context being used to flush the GGTT in emergencies, we will likely need to lift the next-cacheline allocation to a pre-reservation. Signed-off-by: Chris Wilson Cc: Maarten Lankhorst Reviewed-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gt/intel_timeline.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c index 465f87b65901..54e1e55f3c81 100644 --- a/drivers/gpu/drm/i915/gt/intel_timeline.c +++ b/drivers/gpu/drm/i915/gt/intel_timeline.c @@ -406,6 +406,8 @@ __intel_timeline_get_seqno(struct intel_timeline *tl, void *vaddr; int err; + might_lock(>gt->ggtt->vm.mutex); + /* * If there is an outstanding GPU reference to this cacheline, * such as it being sampled by a HW semaphore on another timeline, -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Stop using mutex while sending CTB messages
== Series Details == Series: drm/i915/guc: Stop using mutex while sending CTB messages URL : https://patchwork.freedesktop.org/series/72827/ State : success == Summary == CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16359 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16359/index.html Known issues Here are the changes found in Patchwork_16359 that come from known issues: ### IGT changes ### Issues hit * igt@i915_module_load@reload: - fi-skl-6770hq: [PASS][1] -> [DMESG-WARN][2] ([i915#92]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-skl-6770hq/igt@i915_module_l...@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16359/fi-skl-6770hq/igt@i915_module_l...@reload.html * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][3] -> [DMESG-FAIL][4] ([i915#563]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-4770r/igt@i915_selftest@live_blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16359/fi-hsw-4770r/igt@i915_selftest@live_blt.html * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-skl-6770hq: [PASS][5] -> [SKIP][6] ([fdo#109271]) +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16359/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - fi-skl-6770hq: [PASS][7] -> [DMESG-WARN][8] ([i915#106] / [i915#188]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16359/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-n2820: [TIMEOUT][9] ([fdo#112271] / [i915#1084] / [i915#816]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16359/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live_execlists: - fi-icl-y: [DMESG-FAIL][11] ([fdo#108569]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-y/igt@i915_selftest@live_execlists.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16359/fi-icl-y/igt@i915_selftest@live_execlists.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][13] ([fdo#111096] / [i915#323]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16359/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Warnings * igt@i915_pm_rpm@basic-rte: - fi-kbl-guc: [FAIL][15] ([i915#579]) -> [SKIP][16] ([fdo#109271]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-guc/igt@i915_pm_...@basic-rte.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16359/fi-kbl-guc/igt@i915_pm_...@basic-rte.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][17] ([i915#563]) -> [DMESG-FAIL][18] ([i915#770]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-4770/igt@i915_selftest@live_blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16359/fi-hsw-4770/igt@i915_selftest@live_blt.html [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#106]: https://gitlab.freedesktop.org/drm/intel/issues/106 [i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084 [i915#188]: https://gitlab.freedesktop.org/drm/intel/issues/188 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579 [i915#770]: https://gitlab.freedesktop.org/drm/intel/issues/770 [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 Participating hosts (47 -> 41) -- Additional (4): fi-gdg-551 fi-cfl-8109u fi-skl-6600u fi-snb-2600 Missing(10): fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-ivb-3770 fi-blb-e6850 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529
[Intel-gfx] ✓ Fi.CI.BAT: success for disable drm_global_mutex for most drivers (rev4)
== Series Details == Series: disable drm_global_mutex for most drivers (rev4) URL : https://patchwork.freedesktop.org/series/72711/ State : success == Summary == CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16357 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16357/index.html Known issues Here are the changes found in Patchwork_16357 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][1] -> [DMESG-FAIL][2] ([i915#725]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-4770r/igt@i915_selftest@live_blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16357/fi-hsw-4770r/igt@i915_selftest@live_blt.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-j1900: [TIMEOUT][3] ([fdo#112271] / [i915#1084] / [i915#816]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16357/fi-byt-j1900/igt@gem_close_r...@basic-threads.html - fi-byt-n2820: [TIMEOUT][5] ([fdo#112271] / [i915#1084] / [i915#816]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16357/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-cml-u2: [DMESG-WARN][7] ([IGT#4]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-cml-u2/igt@kms_chamel...@common-hpd-after-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16357/fi-cml-u2/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][9] ([fdo#111096] / [i915#323]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16357/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Warnings * igt@i915_pm_rpm@basic-rte: - fi-kbl-guc: [FAIL][11] ([i915#579]) -> [SKIP][12] ([fdo#109271]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-guc/igt@i915_pm_...@basic-rte.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16357/fi-kbl-guc/igt@i915_pm_...@basic-rte.html [IGT#4]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/4 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816 Participating hosts (47 -> 45) -- Additional (4): fi-skl-6700k2 fi-cfl-8109u fi-skl-6600u fi-snb-2600 Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7853 -> Patchwork_16357 CI-20190529: 20190529 CI_DRM_7853: 1df04205c16923e525efe9c26d6e98612d38c9b3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5409: 93aefe6baa3fabf8c0cabe83e185f7b8f8d8753d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16357: 0aa851bfac6dd1e5818bab37e3a722e736d276ca @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0aa851bfac6d drm: Nerf drm_global_mutex BKL for good drivers 850beb19ef64 drm: Push drm_global_mutex locking in drm_open edabfe0698c0 drm/client: Rename _force to _locked 58509b1c6e52 drm/fbdev-helper: don't force restores ec6b1085531d drm: Complain if drivers still use the ->load callback == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16357/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915/dp: Add all tiled and port sync conns to modeset
On Fri, Jan 31, 2020 at 11:46:25AM -0800, Manasi Navare wrote:
> On Fri, Jan 31, 2020 at 07:53:23PM +0200, Ville Syrjälä wrote:
> > On Fri, Jan 31, 2020 at 09:15:47AM -0800, Manasi Navare wrote:
> > > If one of the synced crtcs needs a full modeset, we need
> > > to make sure all the synced crtcs are forced a full
> > > modeset.
> > >
> > > Suggested-by: Ville Syrjälä
> > > Cc: Ville Syrjälä
> > > Signed-off-by: Manasi Navare
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 88 +
> > > drivers/gpu/drm/i915/display/intel_dp.c | 131 ++-
> > > 2 files changed, 131 insertions(+), 88 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index e638543f5f87..709a737638b6 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -13123,8 +13123,7 @@ intel_modeset_pipe_config(struct intel_crtc_state
> > > *pipe_config)
> > > struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
> > > struct drm_connector *connector;
> > > struct drm_connector_state *connector_state;
> > > - int base_bpp, ret;
> > > - int i, tile_group_id = -1, num_tiled_conns = 0;
> > > + int base_bpp, ret, i;
> > > bool retry = true;
> > >
> > > pipe_config->cpu_transcoder =
> > > @@ -14559,76 +14558,6 @@ static bool
> > > intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
> > > return false;
> > > }
> > >
> > > -static int
> > > -intel_modeset_all_tiles(struct intel_atomic_state *state, int
> > > tile_grp_id)
> > > -{
> > > - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > - struct drm_connector *connector;
> > > - struct drm_connector_list_iter conn_iter;
> > > - int ret = 0;
> > > -
> > > - drm_connector_list_iter_begin(_priv->drm, _iter);
> > > - drm_for_each_connector_iter(connector, _iter) {
> > > - struct drm_connector_state *conn_state;
> > > - struct drm_crtc_state *crtc_state;
> > > -
> > > - if (!connector->has_tile ||
> > > - connector->tile_group->id != tile_grp_id)
> > > - continue;
> > > - conn_state = drm_atomic_get_connector_state(>base,
> > > - connector);
> > > - if (IS_ERR(conn_state)) {
> > > - ret = PTR_ERR(conn_state);
> > > - break;
> > > - }
> > > -
> > > - if (!conn_state->crtc)
> > > - continue;
> > > -
> > > - crtc_state = drm_atomic_get_crtc_state(>base,
> > > -conn_state->crtc);
> > > - if (IS_ERR(crtc_state)) {
> > > - ret = PTR_ERR(crtc_state);
> > > - break;
> > > - }
> > > - crtc_state->mode_changed = true;
> > > - ret = drm_atomic_add_affected_connectors(>base,
> > > - conn_state->crtc);
> > > - if (ret)
> > > - break;
> > > - }
> > > - drm_connector_list_iter_end(_iter);
> > > -
> > > - return ret;
> > > -}
> > > -
> > > -static int
> > > -intel_atomic_check_tiled_conns(struct intel_atomic_state *state)
> > > -{
> > > - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > - struct drm_connector *connector;
> > > - struct drm_connector_state *old_conn_state, *new_conn_state;
> > > - int i, ret;
> > > -
> > > - if (INTEL_GEN(dev_priv) < 11)
> > > - return 0;
> > > -
> > > - /* Is tiled, mark all other tiled CRTCs as needing a modeset */
> > > - for_each_oldnew_connector_in_state(>base, connector,
> > > -old_conn_state, new_conn_state, i) {
> > > - if (!connector->has_tile)
> > > - continue;
> > > - if (!intel_connector_needs_modeset(state, connector))
> > > - continue;
> > > -
> > > - ret = intel_modeset_all_tiles(state, connector->tile_group->id);
> > > - if (ret)
> > > - return ret;
> > > - }
> > > -
> > > - return 0;
> > > -}
> > > -
> > > /**
> > > * intel_atomic_check - validate state object
> > > * @dev: drm device
> > > @@ -14656,21 +14585,6 @@ static int intel_atomic_check(struct drm_device
> > > *dev,
> > > if (ret)
> > > goto fail;
> > >
> > > - /**
> > > - * This check adds all the connectors in current state that belong to
> > > - * the same tile group to a full modeset.
> > > - * This function directly sets the mode_changed to true and we also call
> > > - * drm_atomic_add_affected_connectors(). Hence we are not explicitly
> > > - * calling drm_atomic_helper_check_modeset() after this.
> > > - *
> > > - * Fixme: Handle some corner cases where one of the
> > > - * tiled connectors gets disconnected and tile info is lost but since it
> > > - * was previously synced to other conn, we
Re: [Intel-gfx] [PATCH 3/3] drm/i915/dp: Add all tiled and port sync conns to modeset
On Fri, Jan 31, 2020 at 07:53:23PM +0200, Ville Syrjälä wrote:
> On Fri, Jan 31, 2020 at 09:15:47AM -0800, Manasi Navare wrote:
> > If one of the synced crtcs needs a full modeset, we need
> > to make sure all the synced crtcs are forced a full
> > modeset.
> >
> > Suggested-by: Ville Syrjälä
> > Cc: Ville Syrjälä
> > Signed-off-by: Manasi Navare
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 88 +
> > drivers/gpu/drm/i915/display/intel_dp.c | 131 ++-
> > 2 files changed, 131 insertions(+), 88 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index e638543f5f87..709a737638b6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -13123,8 +13123,7 @@ intel_modeset_pipe_config(struct intel_crtc_state
> > *pipe_config)
> > struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
> > struct drm_connector *connector;
> > struct drm_connector_state *connector_state;
> > - int base_bpp, ret;
> > - int i, tile_group_id = -1, num_tiled_conns = 0;
> > + int base_bpp, ret, i;
> > bool retry = true;
> >
> > pipe_config->cpu_transcoder =
> > @@ -14559,76 +14558,6 @@ static bool
> > intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
> > return false;
> > }
> >
> > -static int
> > -intel_modeset_all_tiles(struct intel_atomic_state *state, int tile_grp_id)
> > -{
> > - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > - struct drm_connector *connector;
> > - struct drm_connector_list_iter conn_iter;
> > - int ret = 0;
> > -
> > - drm_connector_list_iter_begin(_priv->drm, _iter);
> > - drm_for_each_connector_iter(connector, _iter) {
> > - struct drm_connector_state *conn_state;
> > - struct drm_crtc_state *crtc_state;
> > -
> > - if (!connector->has_tile ||
> > - connector->tile_group->id != tile_grp_id)
> > - continue;
> > - conn_state = drm_atomic_get_connector_state(>base,
> > - connector);
> > - if (IS_ERR(conn_state)) {
> > - ret = PTR_ERR(conn_state);
> > - break;
> > - }
> > -
> > - if (!conn_state->crtc)
> > - continue;
> > -
> > - crtc_state = drm_atomic_get_crtc_state(>base,
> > - conn_state->crtc);
> > - if (IS_ERR(crtc_state)) {
> > - ret = PTR_ERR(crtc_state);
> > - break;
> > - }
> > - crtc_state->mode_changed = true;
> > - ret = drm_atomic_add_affected_connectors(>base,
> > -conn_state->crtc);
> > - if (ret)
> > - break;
> > - }
> > - drm_connector_list_iter_end(_iter);
> > -
> > - return ret;
> > -}
> > -
> > -static int
> > -intel_atomic_check_tiled_conns(struct intel_atomic_state *state)
> > -{
> > - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > - struct drm_connector *connector;
> > - struct drm_connector_state *old_conn_state, *new_conn_state;
> > - int i, ret;
> > -
> > - if (INTEL_GEN(dev_priv) < 11)
> > - return 0;
> > -
> > - /* Is tiled, mark all other tiled CRTCs as needing a modeset */
> > - for_each_oldnew_connector_in_state(>base, connector,
> > - old_conn_state, new_conn_state, i) {
> > - if (!connector->has_tile)
> > - continue;
> > - if (!intel_connector_needs_modeset(state, connector))
> > - continue;
> > -
> > - ret = intel_modeset_all_tiles(state, connector->tile_group->id);
> > - if (ret)
> > - return ret;
> > - }
> > -
> > - return 0;
> > -}
> > -
> > /**
> > * intel_atomic_check - validate state object
> > * @dev: drm device
> > @@ -14656,21 +14585,6 @@ static int intel_atomic_check(struct drm_device
> > *dev,
> > if (ret)
> > goto fail;
> >
> > - /**
> > -* This check adds all the connectors in current state that belong to
> > -* the same tile group to a full modeset.
> > -* This function directly sets the mode_changed to true and we also call
> > -* drm_atomic_add_affected_connectors(). Hence we are not explicitly
> > -* calling drm_atomic_helper_check_modeset() after this.
> > -*
> > -* Fixme: Handle some corner cases where one of the
> > -* tiled connectors gets disconnected and tile info is lost but since it
> > -* was previously synced to other conn, we need to add that to the
> > modeset.
> > -*/
> > - ret = intel_atomic_check_tiled_conns(state);
> > - if (ret)
> > - goto fail;
> > -
> >
Re: [Intel-gfx] [v2] drm/i915/tgl: Add Wa_1606054188:tgl
On Fri, Jan 31, 2020 at 10:19:51PM -0500, Matt Atwood wrote:
> On Tiger Lake we do not support source keying in the pixel formats P010,
> P012, P016.
>
> v2: Move WA to end of function. Create helper function for format
> check. Less verbose debugging messaging.
>
> Bspec: 52890
> Cc: Matt Roper
> Cc: Manasi Navare
> CC: Ville Syrjälä
Wrong address
> Signed-off-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 22 +
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 2f277d1fc6f1..6e4d73588b48 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -2070,6 +2070,18 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
> return 0;
> }
>
> +static bool intel_format_is_p01x(int format)
^^^
u32
> +{
> + switch(format){
Missing spaces
> + case DRM_FORMAT_P010:
> + case DRM_FORMAT_P012:
> + case DRM_FORMAT_P016:
> + return true;
> + default:
> + return false;
Wrong indentantion
> + }
> +}
> +
> static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> @@ -2143,6 +2155,16 @@ static int skl_plane_check_fb(const struct
> intel_crtc_state *crtc_state,
> return -EINVAL;
> }
>
> + /* Wa_1606054188:tgl
> + *
> + * TODO: Add format RGB64i when implemented.
> + *
> + */
Wrong comment format
> + if(IS_GEN(dev_priv, 12) &&
Missing space
> +plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
> +intel_format_is_p01x(fb->format->format))
> + DRM_DEBUG_KMS("Source color keying not supported with P01x
> formats\n");
Missing error return.
Was also going to suggest you should use drm_dbg_kms() now, but
looks like this file hasn't been converted yet. Well, I guess
there'd be no harm in using drm_dbg_kms() anyway if you want.
As for the w/a itself, not sure it's any more broken than any other
planar format (don't have the hw to test it right now). But I just
tried my wip colorkey test on glk with nv12/p010 and while it
more or less seems to work the chroma upsampling is definitely
making it impossible to test with crcs. I guess we'll get to
testing out eventually to see if it is actually more broken than
that. Certainly wouldn't be the first time the hw has issues with
the >8bpc to 8bpc conversion for the key match. Just a bit
surprising that it would be limited to just the specific combo
of tgl and P01x formats.
> +
> return 0;
> }
>
> --
> 2.21.1
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
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Intel
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[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt (rev3)
== Series Details == Series: series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt (rev3) URL : https://patchwork.freedesktop.org/series/72809/ State : failure == Summary == Applying: drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt .git/rebase-apply/patch:15: space before tab in indent. I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND; warning: 1 line adds whitespace errors. Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gt/intel_ggtt.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/gt/intel_ggtt.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_ggtt.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for disable drm_global_mutex for most drivers (rev4)
== Series Details ==
Series: disable drm_global_mutex for most drivers (rev4)
URL : https://patchwork.freedesktop.org/series/72711/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ec6b1085531d drm: Complain if drivers still use the ->load callback
-:48: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch
author 'Daniel Vetter '
total: 0 errors, 1 warnings, 0 checks, 21 lines checked
58509b1c6e52 drm/fbdev-helper: don't force restores
-:70: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch
author 'Daniel Vetter '
total: 0 errors, 1 warnings, 0 checks, 29 lines checked
edabfe0698c0 drm/client: Rename _force to _locked
-:97: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch
author 'Daniel Vetter '
total: 0 errors, 1 warnings, 0 checks, 60 lines checked
850beb19ef64 drm: Push drm_global_mutex locking in drm_open
-:95: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch
author 'Daniel Vetter '
total: 0 errors, 1 warnings, 0 checks, 54 lines checked
0aa851bfac6d drm: Nerf drm_global_mutex BKL for good drivers
-:19: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 7e13ad896484 ("drm: Avoid
drm_global_mutex for simple inc/dec of dev->open_count")'
#19:
commit 7e13ad896484a0165a68197a2e64091ea28c9602
-:162: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch
author 'Daniel Vetter '
total: 1 errors, 1 warnings, 0 checks, 109 lines checked
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Disable heartbeat around hang tests
== Series Details == Series: drm/i915/selftests: Disable heartbeat around hang tests URL : https://patchwork.freedesktop.org/series/72821/ State : failure == Summary == Applying: drm/i915/selftests: Disable heartbeat around hang tests Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gt/selftest_lrc.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/gt/selftest_lrc.c No changes -- Patch already applied. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/12] drm/i915/gt: Rename lrc.c to execlists_submission.c
On 1/31/20 2:45 AM, Chris Wilson wrote:
We want to separate the utility functions for controlling the logical
ring context from the execlists submission mechanism (which is an
overgrown scheduler).
This is similar to Daniele's work to split up the files, but being
selfish I wanted to base it after my own changes to intel_lrc.c petered
out.
Signed-off-by: Chris Wilson
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_context.c | 1 +
drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
drivers/gpu/drm/i915/gt/intel_engine_pool.c | 1 +
...tel_lrc.c => intel_execlists_submission.c} | 30 ++
...tel_lrc.h => intel_execlists_submission.h} | 31 +++
drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
.../{selftest_lrc.c => selftest_execlists.c} | 0
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 1 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_perf.c | 1 +
13 files changed, 16 insertions(+), 58 deletions(-)
rename drivers/gpu/drm/i915/gt/{intel_lrc.c => intel_execlists_submission.c}
(99%)
rename drivers/gpu/drm/i915/gt/{intel_lrc.h => intel_execlists_submission.h}
(56%)
rename drivers/gpu/drm/i915/gt/{selftest_lrc.c => selftest_execlists.c} (100%)
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7d04db92aae5..f2b5742218a0 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -87,6 +87,7 @@ gt-y += \
gt/intel_engine_pm.o \
gt/intel_engine_pool.o \
gt/intel_engine_user.o \
+ gt/intel_execlists_submission.o \
gt/intel_ggtt.o \
gt/intel_gt.o \
gt/intel_gt_irq.o \
@@ -95,7 +96,6 @@ gt-y += \
gt/intel_gt_requests.o \
gt/intel_gtt.o \
gt/intel_llc.o \
- gt/intel_lrc.o \
gt/intel_mocs.o \
gt/intel_ppgtt.o \
gt/intel_rc6.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 9130706417c0..cbc1cec9988d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -73,6 +73,7 @@
#include "gt/intel_context.h"
#include "gt/intel_engine_heartbeat.h"
#include "gt/intel_engine_user.h"
+#include "gt/intel_execlists_submission.h" /* virtual_engine */
#include "gt/intel_ring.h"
#include "i915_gem_context.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_context_sseu.c
b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
index 57a30956c922..ee4ef2559914 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
@@ -8,7 +8,7 @@
#include "intel_context.h"
#include "intel_engine_pm.h"
#include "intel_gpu_commands.h"
-#include "intel_lrc.h"
+#include "intel_execlists_submission.h"
#include "intel_lrc_reg.h"
#include "intel_ring.h"
#include "intel_sseu.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 2aa3bb883cb3..2e8e178ce966 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -33,6 +33,7 @@
#include "intel_engine_pm.h"
#include "intel_engine_pool.h"
#include "intel_engine_user.h"
+#include "intel_execlists_submission.h"
#include "intel_gt.h"
#include "intel_gt_requests.h"
#include "intel_gt_pm.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pool.c
b/drivers/gpu/drm/i915/gt/intel_engine_pool.c
index 397186818305..56abd7a068d3 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pool.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pool.c
@@ -9,6 +9,7 @@
#include "i915_drv.h"
#include "intel_engine_pm.h"
#include "intel_engine_pool.h"
+#include "intel_execlists_submission.h" /* intel_virtual_engine*() */
static struct intel_engine_cs *to_engine(struct intel_engine_pool *pool)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
similarity index 99%
rename from drivers/gpu/drm/i915/gt/intel_lrc.c
rename to drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index e1ea369bc62d..698276d3c074 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1,31 +1,6 @@
+// SPDX-License-Identifier: MIT
/*
* Copyright © 2014 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Add missing HDMI audio pixel clocks for gen12 (rev2)
== Series Details == Series: drm/i915: Add missing HDMI audio pixel clocks for gen12 (rev2) URL : https://patchwork.freedesktop.org/series/72617/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7835_full -> Patchwork_16310_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16310_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16310_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16310_full: ### IGT changes ### Possible regressions * igt@gem_exec_schedule@pi-shared-iova-blt: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7835/shard-skl6/igt@gem_exec_sched...@pi-shared-iova-blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16310/shard-skl5/igt@gem_exec_sched...@pi-shared-iova-blt.html Known issues Here are the changes found in Patchwork_16310_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@vcs1-mixed-process: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7835/shard-iclb4/igt@gem_ctx_persiste...@vcs1-mixed-process.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16310/shard-iclb8/igt@gem_ctx_persiste...@vcs1-mixed-process.html * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110841]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7835/shard-iclb7/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16310/shard-iclb2/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112080]) +17 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7835/shard-iclb4/igt@gem_exec_paral...@vcs1-fds.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16310/shard-iclb8/igt@gem_exec_paral...@vcs1-fds.html * igt@gem_exec_schedule@independent-bsd2: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +15 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7835/shard-iclb4/igt@gem_exec_sched...@independent-bsd2.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16310/shard-iclb8/igt@gem_exec_sched...@independent-bsd2.html * igt@gem_exec_schedule@pi-common-bsd: - shard-iclb: [PASS][11] -> [SKIP][12] ([i915#677]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7835/shard-iclb8/igt@gem_exec_sched...@pi-common-bsd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16310/shard-iclb1/igt@gem_exec_sched...@pi-common-bsd.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112146]) +7 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7835/shard-iclb7/igt@gem_exec_sched...@preemptive-hang-bsd.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16310/shard-iclb2/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@gem_exec_suspend@basic-s3: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7835/shard-kbl1/igt@gem_exec_susp...@basic-s3.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16310/shard-kbl1/igt@gem_exec_susp...@basic-s3.html * igt@gen7_exec_parse@basic-offset: - shard-hsw: [PASS][17] -> [FAIL][18] ([i915#694]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7835/shard-hsw8/igt@gen7_exec_pa...@basic-offset.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16310/shard-hsw5/igt@gen7_exec_pa...@basic-offset.html * igt@i915_pm_dc@dc6-dpms: - shard-iclb: [PASS][19] -> [FAIL][20] ([i915#454]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7835/shard-iclb1/igt@i915_pm...@dc6-dpms.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16310/shard-iclb3/igt@i915_pm...@dc6-dpms.html * igt@i915_pm_rpm@system-suspend: - shard-skl: [PASS][21] -> [INCOMPLETE][22] ([i915#151] / [i915#69]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7835/shard-skl10/igt@i915_pm_...@system-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16310/shard-skl5/igt@i915_pm_...@system-suspend.html * igt@i915_pm_rps@reset: - shard-tglb: [PASS][23] -> [FAIL][24] ([i915#413])
[Intel-gfx] [v2] drm/i915/tgl: Add Wa_1606054188:tgl
On Tiger Lake we do not support source keying in the pixel formats P010,
P012, P016.
v2: Move WA to end of function. Create helper function for format
check. Less verbose debugging messaging.
Bspec: 52890
Cc: Matt Roper
Cc: Manasi Navare
CC: Ville Syrjälä
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/display/intel_sprite.c | 22 +
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 2f277d1fc6f1..6e4d73588b48 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2070,6 +2070,18 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
return 0;
}
+static bool intel_format_is_p01x(int format)
+{
+ switch(format){
+ case DRM_FORMAT_P010:
+ case DRM_FORMAT_P012:
+ case DRM_FORMAT_P016:
+ return true;
+ default:
+ return false;
+ }
+}
+
static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
@@ -2143,6 +2155,16 @@ static int skl_plane_check_fb(const struct
intel_crtc_state *crtc_state,
return -EINVAL;
}
+ /* Wa_1606054188:tgl
+*
+* TODO: Add format RGB64i when implemented.
+*
+*/
+ if(IS_GEN(dev_priv, 12) &&
+ plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
+ intel_format_is_p01x(fb->format->format))
+ DRM_DEBUG_KMS("Source color keying not supported with P01x
formats\n");
+
return 0;
}
--
2.21.1
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Re: [Intel-gfx] [PATCH 3/3] drm/i915/dp: Add all tiled and port sync conns to modeset
On Fri, Jan 31, 2020 at 09:15:47AM -0800, Manasi Navare wrote:
> If one of the synced crtcs needs a full modeset, we need
> to make sure all the synced crtcs are forced a full
> modeset.
>
> Suggested-by: Ville Syrjälä
> Cc: Ville Syrjälä
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 88 +
> drivers/gpu/drm/i915/display/intel_dp.c | 131 ++-
> 2 files changed, 131 insertions(+), 88 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e638543f5f87..709a737638b6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13123,8 +13123,7 @@ intel_modeset_pipe_config(struct intel_crtc_state
> *pipe_config)
> struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
> struct drm_connector *connector;
> struct drm_connector_state *connector_state;
> - int base_bpp, ret;
> - int i, tile_group_id = -1, num_tiled_conns = 0;
> + int base_bpp, ret, i;
> bool retry = true;
>
> pipe_config->cpu_transcoder =
> @@ -14559,76 +14558,6 @@ static bool
> intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
> return false;
> }
>
> -static int
> -intel_modeset_all_tiles(struct intel_atomic_state *state, int tile_grp_id)
> -{
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - struct drm_connector *connector;
> - struct drm_connector_list_iter conn_iter;
> - int ret = 0;
> -
> - drm_connector_list_iter_begin(_priv->drm, _iter);
> - drm_for_each_connector_iter(connector, _iter) {
> - struct drm_connector_state *conn_state;
> - struct drm_crtc_state *crtc_state;
> -
> - if (!connector->has_tile ||
> - connector->tile_group->id != tile_grp_id)
> - continue;
> - conn_state = drm_atomic_get_connector_state(>base,
> - connector);
> - if (IS_ERR(conn_state)) {
> - ret = PTR_ERR(conn_state);
> - break;
> - }
> -
> - if (!conn_state->crtc)
> - continue;
> -
> - crtc_state = drm_atomic_get_crtc_state(>base,
> -conn_state->crtc);
> - if (IS_ERR(crtc_state)) {
> - ret = PTR_ERR(crtc_state);
> - break;
> - }
> - crtc_state->mode_changed = true;
> - ret = drm_atomic_add_affected_connectors(>base,
> - conn_state->crtc);
> - if (ret)
> - break;
> - }
> - drm_connector_list_iter_end(_iter);
> -
> - return ret;
> -}
> -
> -static int
> -intel_atomic_check_tiled_conns(struct intel_atomic_state *state)
> -{
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - struct drm_connector *connector;
> - struct drm_connector_state *old_conn_state, *new_conn_state;
> - int i, ret;
> -
> - if (INTEL_GEN(dev_priv) < 11)
> - return 0;
> -
> - /* Is tiled, mark all other tiled CRTCs as needing a modeset */
> - for_each_oldnew_connector_in_state(>base, connector,
> -old_conn_state, new_conn_state, i) {
> - if (!connector->has_tile)
> - continue;
> - if (!intel_connector_needs_modeset(state, connector))
> - continue;
> -
> - ret = intel_modeset_all_tiles(state, connector->tile_group->id);
> - if (ret)
> - return ret;
> - }
> -
> - return 0;
> -}
> -
> /**
> * intel_atomic_check - validate state object
> * @dev: drm device
> @@ -14656,21 +14585,6 @@ static int intel_atomic_check(struct drm_device *dev,
> if (ret)
> goto fail;
>
> - /**
> - * This check adds all the connectors in current state that belong to
> - * the same tile group to a full modeset.
> - * This function directly sets the mode_changed to true and we also call
> - * drm_atomic_add_affected_connectors(). Hence we are not explicitly
> - * calling drm_atomic_helper_check_modeset() after this.
> - *
> - * Fixme: Handle some corner cases where one of the
> - * tiled connectors gets disconnected and tile info is lost but since it
> - * was previously synced to other conn, we need to add that to the
> modeset.
> - */
> - ret = intel_atomic_check_tiled_conns(state);
> - if (ret)
> - goto fail;
> -
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> if
Re: [Intel-gfx] [PATCH 2/3] drm/i915/dp: Compute port sync crtc states post compute_config()
On Fri, Jan 31, 2020 at 09:15:46AM -0800, Manasi Navare wrote:
> This patch pushes out the computation of master and slave
> transcoders in crtc states after encoder's compute_config hook.
> This ensures that the assigned master slave crtcs have exact same
> mode and timings which is a requirement for Port sync mode
> to be enabled.
>
> Suggested-by: Ville Syrjälä
> Cc: Ville Syrjälä
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 125 +++
> drivers/gpu/drm/i915/display/intel_display.c | 156 ---
> 2 files changed, 125 insertions(+), 156 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index c96f629cddc3..4ec36eb5ce28 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4440,6 +4440,130 @@ static int intel_ddi_compute_config(struct
> intel_encoder *encoder,
> return 0;
> }
>
> +static bool mode_equal(const struct drm_display_mode *mode1,
> +const struct drm_display_mode *mode2)
> +{
> + return drm_mode_match(mode1, mode2,
> + DRM_MODE_MATCH_TIMINGS |
> + DRM_MODE_MATCH_FLAGS |
> + DRM_MODE_MATCH_3D_FLAGS) &&
> + mode1->clock == mode2->clock; /* we want an exact match */
Trying to remember why we chose .clock rather than .crtc_clock... Ah,
because drm_mode_match() anyway looks at the non-crtc timings. Yeah,
should work fine since we make sure the 3D flags match so the crtc
timings vs non-crtc timings should be consistent for each one.
> +}
> +
> +static bool m_n_equal(const struct intel_link_m_n *m_n_1,
> + const struct intel_link_m_n *m_n_2)
> +{
> + return m_n_1->tu == m_n_2->tu &&
> + m_n_1->gmch_m == m_n_2->gmch_m &&
> + m_n_1->gmch_n == m_n_2->gmch_n &&
> + m_n_1->link_m == m_n_2->link_m &&
> + m_n_1->link_n == m_n_2->link_n;
> +}
> +
> +static bool crtcs_port_sync_compatible(struct intel_crtc_state *crtc_state1,
> +struct intel_crtc_state *crtc_state2)
> +{
> + return crtc_state1->hw.active && crtc_state2->hw.active &&
> + crtc_state1->output_types == crtc_state2->output_types &&
> + crtc_state1->output_format == crtc_state2->output_format &&
> + crtc_state1->lane_count == crtc_state2->lane_count &&
> + crtc_state1->port_clock == crtc_state2->port_clock &&
> + mode_equal(_state1->hw.adjusted_mode,
> +_state2->hw.adjusted_mode) &&
> + m_n_equal(_state1->dp_m_n, _state2->dp_m_n);
> +}
> +
> +static u8
> +intel_ddi_compute_port_sync_crtc_state
The name is misleading. something_port_sync_transcoders() etc. to
better describe what it returns.
>(struct drm_connector *ref_connector,
You don't need the whole connector. The tile group id will suffice.
> +struct intel_crtc_state *ref_crtc_state)
const
> +{
> + struct drm_connector *connector;
> + struct drm_connector_state *conn_state;
> + struct drm_i915_private *dev_priv =
> to_i915(ref_crtc_state->uapi.crtc->dev);
> + struct intel_atomic_state *state =
> + to_intel_atomic_state(ref_crtc_state->uapi.state);
> + struct intel_crtc *ref_crtc = to_intel_crtc(ref_crtc_state->uapi.crtc);
> + u8 transcoders = 0;
> + int i;
> +
> + DRM_DEBUG_KMS("for [CRTC:%d:%s]\n",
> + ref_crtc_state->uapi.crtc->base.id,
> + ref_crtc_state->uapi.crtc->name);
More noise than signal. Pls remove.
> +
> + if (INTEL_GEN(dev_priv) < 11)
> + return 0;
> +
> + if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
> + return 0;
> +
> + for_each_new_connector_in_state(>base, connector, conn_state, i)
> {
> + struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
> + struct intel_crtc_state *crtc_state = NULL;
> +
> + if (!crtc)
> + continue;
> +
> + if (!(connector->has_tile &&
> + connector->tile_group->id ==
> + ref_connector->tile_group->id))
> + continue;
> +
> + crtc_state = intel_atomic_get_new_crtc_state(state,
> + crtc);
> + if (!crtcs_port_sync_compatible(ref_crtc_state,
> + crtc_state)) {
> + DRM_DEBUG_KMS("[CRTC:%d:%s] and [CRTC:%d:%s] not Port
> Sync Compatible\n",
> + ref_crtc->base.base.id,
> + ref_crtc->base.name,
> + crtc->base.base.id, crtc->base.name);
Another noisy debug. The
Re: [Intel-gfx] [PATCH] drm/i915/dsb: Enable lmem for dsb
On 31-01-2020 17:33, Ville Syrjälä wrote:
On Fri, Jan 31, 2020 at 05:12:58PM +0530, Animesh Manna wrote:
If lmem is supported DSB should use local memeory instead
of system memory. Using local memory surely bring performance
improvement as local memory is close to gpu. Also want to avoid
multiple gpu using system memory.
Used LMEM api to create gem object needed for DSB command buffer.
The whole point of the dsb is to avoid doing mmio.a Now you're
replacing the nice dma with mmio again. Granted lmem is probably
wc so maybe not as slow as direct mmio register access, and also
we can do this ahead of time so not as time critical as direct
mmio during the the vblank.
As per sas documentation Lmem (HBM) memory is preferable for command/batch
buffer, planning to do some profiling. Will update the result.
Regards,
Animesh
v1: Initial patch.
Cc: Jani Nikula
Cc: Matthew Auld
Cc: Ramalingam C
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 9dd18144a664..d67b6a764ba0 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -6,6 +6,7 @@
#include "i915_drv.h"
#include "intel_display_types.h"
+#include "gem/i915_gem_lmem.h"
#define DSB_BUF_SIZE(2 * PAGE_SIZE)
@@ -113,7 +114,11 @@ intel_dsb_get(struct intel_crtc *crtc)
wakeref = intel_runtime_pm_get(>runtime_pm);
- obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
+ if (HAS_LMEM(i915))
+ obj = i915_gem_object_create_lmem(i915, DSB_BUF_SIZE, 0);
+ else
+ obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
+
if (IS_ERR(obj)) {
DRM_ERROR("Gem object creation failed\n");
goto out;
--
2.24.0
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[Intel-gfx] [PATCH 1/3] drm/i915: Introduce encoder->compute_config_late()
From: Ville Syrjälä
Add an optional secondary encoder state compute hook. This gets
called after the normak .compute_config() has been called for
all the encoders in the state. Thus in the new hook we can rely
on all derived state populated by .compute_config() to be already
set up. Should be useful for MST and port sync master/slave
transcoder selection.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 39 +++
.../drm/i915/display/intel_display_types.h| 3 ++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index c0e5002ce64c..de4ab51216f6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13416,6 +13416,35 @@ intel_modeset_pipe_config(struct intel_crtc_state
*pipe_config)
return 0;
}
+static int
+intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state)
+{
+ struct intel_atomic_state *state =
+ to_intel_atomic_state(crtc_state->uapi.state);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_connector_state *conn_state;
+ struct drm_connector *connector;
+ int i;
+
+ for_each_new_connector_in_state(>base, connector,
+ conn_state, i) {
+ struct intel_encoder *encoder =
+ to_intel_encoder(conn_state->best_encoder);
+ int ret;
+
+ if (conn_state->crtc != >base ||
+ !encoder->compute_config_late)
+ continue;
+
+ ret = encoder->compute_config_late(encoder, crtc_state,
+ conn_state);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
bool intel_fuzzy_clock_check(int clock1, int clock2)
{
int diff;
@@ -14817,6 +14846,16 @@ static int intel_atomic_check(struct drm_device *dev,
ret = intel_modeset_pipe_config(new_crtc_state);
if (ret)
goto fail;
+ }
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ if (!needs_modeset(new_crtc_state))
+ continue;
+
+ ret = intel_modeset_pipe_config_late(new_crtc_state);
+ if (ret)
+ goto fail;
intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 33ba93863488..51f0108a6e09 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -140,6 +140,9 @@ struct intel_encoder {
int (*compute_config)(struct intel_encoder *,
struct intel_crtc_state *,
struct drm_connector_state *);
+ int (*compute_config_late)(struct intel_encoder *,
+ struct intel_crtc_state *,
+ struct drm_connector_state *);
void (*update_prepare)(struct intel_atomic_state *,
struct intel_encoder *,
struct intel_crtc *);
--
2.19.1
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[Intel-gfx] [PATCH 3/3] drm/i915/dp: Add all tiled and port sync conns to modeset
If one of the synced crtcs needs a full modeset, we need
to make sure all the synced crtcs are forced a full
modeset.
Suggested-by: Ville Syrjälä
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 88 +
drivers/gpu/drm/i915/display/intel_dp.c | 131 ++-
2 files changed, 131 insertions(+), 88 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e638543f5f87..709a737638b6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13123,8 +13123,7 @@ intel_modeset_pipe_config(struct intel_crtc_state
*pipe_config)
struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
struct drm_connector *connector;
struct drm_connector_state *connector_state;
- int base_bpp, ret;
- int i, tile_group_id = -1, num_tiled_conns = 0;
+ int base_bpp, ret, i;
bool retry = true;
pipe_config->cpu_transcoder =
@@ -14559,76 +14558,6 @@ static bool intel_cpu_transcoders_need_modeset(struct
intel_atomic_state *state,
return false;
}
-static int
-intel_modeset_all_tiles(struct intel_atomic_state *state, int tile_grp_id)
-{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct drm_connector *connector;
- struct drm_connector_list_iter conn_iter;
- int ret = 0;
-
- drm_connector_list_iter_begin(_priv->drm, _iter);
- drm_for_each_connector_iter(connector, _iter) {
- struct drm_connector_state *conn_state;
- struct drm_crtc_state *crtc_state;
-
- if (!connector->has_tile ||
- connector->tile_group->id != tile_grp_id)
- continue;
- conn_state = drm_atomic_get_connector_state(>base,
- connector);
- if (IS_ERR(conn_state)) {
- ret = PTR_ERR(conn_state);
- break;
- }
-
- if (!conn_state->crtc)
- continue;
-
- crtc_state = drm_atomic_get_crtc_state(>base,
- conn_state->crtc);
- if (IS_ERR(crtc_state)) {
- ret = PTR_ERR(crtc_state);
- break;
- }
- crtc_state->mode_changed = true;
- ret = drm_atomic_add_affected_connectors(>base,
-conn_state->crtc);
- if (ret)
- break;
- }
- drm_connector_list_iter_end(_iter);
-
- return ret;
-}
-
-static int
-intel_atomic_check_tiled_conns(struct intel_atomic_state *state)
-{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct drm_connector *connector;
- struct drm_connector_state *old_conn_state, *new_conn_state;
- int i, ret;
-
- if (INTEL_GEN(dev_priv) < 11)
- return 0;
-
- /* Is tiled, mark all other tiled CRTCs as needing a modeset */
- for_each_oldnew_connector_in_state(>base, connector,
- old_conn_state, new_conn_state, i) {
- if (!connector->has_tile)
- continue;
- if (!intel_connector_needs_modeset(state, connector))
- continue;
-
- ret = intel_modeset_all_tiles(state, connector->tile_group->id);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
/**
* intel_atomic_check - validate state object
* @dev: drm device
@@ -14656,21 +14585,6 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
- /**
-* This check adds all the connectors in current state that belong to
-* the same tile group to a full modeset.
-* This function directly sets the mode_changed to true and we also call
-* drm_atomic_add_affected_connectors(). Hence we are not explicitly
-* calling drm_atomic_helper_check_modeset() after this.
-*
-* Fixme: Handle some corner cases where one of the
-* tiled connectors gets disconnected and tile info is lost but since it
-* was previously synced to other conn, we need to add that to the
modeset.
-*/
- ret = intel_atomic_check_tiled_conns(state);
- if (ret)
- goto fail;
-
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
if (!needs_modeset(new_crtc_state)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f4dede6253f8..7eb4b3dbbcb3 100644
---
[Intel-gfx] [PATCH 2/3] drm/i915/dp: Compute port sync crtc states post compute_config()
This patch pushes out the computation of master and slave
transcoders in crtc states after encoder's compute_config hook.
This ensures that the assigned master slave crtcs have exact same
mode and timings which is a requirement for Port sync mode
to be enabled.
Suggested-by: Ville Syrjälä
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_ddi.c | 125 +++
drivers/gpu/drm/i915/display/intel_display.c | 156 ---
2 files changed, 125 insertions(+), 156 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index c96f629cddc3..4ec36eb5ce28 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4440,6 +4440,130 @@ static int intel_ddi_compute_config(struct
intel_encoder *encoder,
return 0;
}
+static bool mode_equal(const struct drm_display_mode *mode1,
+ const struct drm_display_mode *mode2)
+{
+ return drm_mode_match(mode1, mode2,
+ DRM_MODE_MATCH_TIMINGS |
+ DRM_MODE_MATCH_FLAGS |
+ DRM_MODE_MATCH_3D_FLAGS) &&
+ mode1->clock == mode2->clock; /* we want an exact match */
+}
+
+static bool m_n_equal(const struct intel_link_m_n *m_n_1,
+ const struct intel_link_m_n *m_n_2)
+{
+ return m_n_1->tu == m_n_2->tu &&
+ m_n_1->gmch_m == m_n_2->gmch_m &&
+ m_n_1->gmch_n == m_n_2->gmch_n &&
+ m_n_1->link_m == m_n_2->link_m &&
+ m_n_1->link_n == m_n_2->link_n;
+}
+
+static bool crtcs_port_sync_compatible(struct intel_crtc_state *crtc_state1,
+ struct intel_crtc_state *crtc_state2)
+{
+ return crtc_state1->hw.active && crtc_state2->hw.active &&
+ crtc_state1->output_types == crtc_state2->output_types &&
+ crtc_state1->output_format == crtc_state2->output_format &&
+ crtc_state1->lane_count == crtc_state2->lane_count &&
+ crtc_state1->port_clock == crtc_state2->port_clock &&
+ mode_equal(_state1->hw.adjusted_mode,
+ _state2->hw.adjusted_mode) &&
+ m_n_equal(_state1->dp_m_n, _state2->dp_m_n);
+}
+
+static u8
+intel_ddi_compute_port_sync_crtc_state(struct drm_connector *ref_connector,
+ struct intel_crtc_state *ref_crtc_state)
+{
+ struct drm_connector *connector;
+ struct drm_connector_state *conn_state;
+ struct drm_i915_private *dev_priv =
to_i915(ref_crtc_state->uapi.crtc->dev);
+ struct intel_atomic_state *state =
+ to_intel_atomic_state(ref_crtc_state->uapi.state);
+ struct intel_crtc *ref_crtc = to_intel_crtc(ref_crtc_state->uapi.crtc);
+ u8 transcoders = 0;
+ int i;
+
+ DRM_DEBUG_KMS("for [CRTC:%d:%s]\n",
+ ref_crtc_state->uapi.crtc->base.id,
+ ref_crtc_state->uapi.crtc->name);
+
+ if (INTEL_GEN(dev_priv) < 11)
+ return 0;
+
+ if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
+ return 0;
+
+ for_each_new_connector_in_state(>base, connector, conn_state, i)
{
+ struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
+ struct intel_crtc_state *crtc_state = NULL;
+
+ if (!crtc)
+ continue;
+
+ if (!(connector->has_tile &&
+ connector->tile_group->id ==
+ ref_connector->tile_group->id))
+ continue;
+
+ crtc_state = intel_atomic_get_new_crtc_state(state,
+crtc);
+ if (!crtcs_port_sync_compatible(ref_crtc_state,
+ crtc_state)) {
+ DRM_DEBUG_KMS("[CRTC:%d:%s] and [CRTC:%d:%s] not Port
Sync Compatible\n",
+ ref_crtc->base.base.id,
+ ref_crtc->base.name,
+ crtc->base.base.id, crtc->base.name);
+ continue;
+ }
+
+ transcoders |= BIT(crtc_state->cpu_transcoder);
+ }
+
+ return transcoders;
+}
+
+static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
+struct intel_crtc_state *crtc_state,
+struct drm_connector_state *conn_state)
+{
+ struct drm_connector *connector = conn_state->connector;
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ u8 port_sync_transcoders = 0;
+
+ DRM_DEBUG_KMS("[ENCODER:%d:%s] [CRTC:%d:%s]",
+ encoder->base.base.id, encoder->base.name,
+
Re: [Intel-gfx] [PATCH] drm/i915/guc: Stop using mutex while sending CTB messages
On Fri, 31 Jan 2020 17:40:12 +0100, Matthew Brost wrote: On Fri, Jan 31, 2020 at 03:33:55PM +, Chris Wilson wrote: Quoting Michal Wajdeczko (2020-01-31 14:58:34) While we are always using CT "send" buffer to send request messages to GuC, we usually don't ask GuC to use CT "receive" buffer to send back response messages, since almost all returned data can fit into reserved bits in status dword inside CT descriptor. However, relying on data modifications inside CT descriptor requires use of mutex to allow only single CT request in flight, until we read back that status dword from the CT descriptor. Q. do we need the same lock for ct_read() and ct_write()? Could ct_read() use a lock-free ringbuffer, and then if I've read it right, you wouldn't have any overlapping spinlock between the interrupt handler and the rest (thus avoiding the interrupt-off). -Chris Agree with Chris, it would nice if ct_read() didn't need a lock. At a minimum I think it needs a different lock than the write path. two options: 1) reuse gt->irq_lock for ct_read() and use ct->lock for ct_write() 2) define lock as part of ct->ctbs[] for dedicated use by ct_read()/write() I guess 2 is clearer ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/guc: Stop using mutex while sending CTB messages
On Fri, 31 Jan 2020 16:33:55 +0100, Chris Wilson wrote: Quoting Michal Wajdeczko (2020-01-31 14:58:34) While we are always using CT "send" buffer to send request messages to GuC, we usually don't ask GuC to use CT "receive" buffer to send back response messages, since almost all returned data can fit into reserved bits in status dword inside CT descriptor. However, relying on data modifications inside CT descriptor requires use of mutex to allow only single CT request in flight, until we read back that status dword from the CT descriptor. Q. do we need the same lock for ct_read() and ct_write()? No. And additionally I missed that ct_read() was already implicitly locked with gt->irq_lock by gen11_gt_irq_handler and with i915->irq_lock by guc_enable_communication() - need to fix that too ;( Could ct_read() use a lock-free ringbuffer, and then if I've read it right, you wouldn't have any overlapping spinlock between the interrupt handler and the rest (thus avoiding the interrupt-off). Not sure if can go lock-free with two callers, will look for gt->irq_lock ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/guc: Stop using mutex while sending CTB messages
On Fri, Jan 31, 2020 at 03:33:55PM +, Chris Wilson wrote: Quoting Michal Wajdeczko (2020-01-31 14:58:34) While we are always using CT "send" buffer to send request messages to GuC, we usually don't ask GuC to use CT "receive" buffer to send back response messages, since almost all returned data can fit into reserved bits in status dword inside CT descriptor. However, relying on data modifications inside CT descriptor requires use of mutex to allow only single CT request in flight, until we read back that status dword from the CT descriptor. Q. do we need the same lock for ct_read() and ct_write()? Could ct_read() use a lock-free ringbuffer, and then if I've read it right, you wouldn't have any overlapping spinlock between the interrupt handler and the rest (thus avoiding the interrupt-off). -Chris Agree with Chris, it would nice if ct_read() didn't need a lock. At a minimum I think it needs a different lock than the write path. Matt ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/gen7: Clear all EU/L3 residual contexts
Reducing audience as this series is of high interest externally. I fully agree with Joonas' suggestion here, and we have been looking at doing just that. But can we iterate as a follow up patch series? Putting in the infra to support igt assembly from source will take a little time (igt assembler doesn't like the source right now, so it looks like it will need updating), and we are under pressure to get this security fix out. Jon > -Original Message- > From: Joonas Lahtinen > Sent: Friday, January 31, 2020 1:52 AM > To: Abodunrin, Akeem G ; Wilson, Chris P > ; Phillips, D Scott ; > Vetter, Daniel ; Stewart, David C > ; dri-de...@lists.freedesktop.org; Balestrieri, > Francesco ; intel-gfx@lists.freedesktop.org; > Nikula, Jani ; Bloomfield, Jon > ; Kuoppala, Mika ; > Aran, Omer ; Pathi, Pragyansri > ; Kumar Valsan, Prathap > ; Dutt, Sudeep ; > Luck, Tony > Subject: Re: [PATCH 2/2] drm/i915/gen7: Clear all EU/L3 residual contexts > > Quoting Akeem G Abodunrin (2020-01-30 18:57:21) > > From: Prathap Kumar Valsan > > > > On gen7 and gen7.5 devices, there could be leftover data residuals in > > EU/L3 from the retiring context. This patch introduces workaround to clear > > that residual contexts, by submitting a batch buffer with dedicated HW > > context to the GPU with ring allocation for each context switching. > > > > This security mitigation change does not trigger any performance > > regression. Performance is on par with current mainline/drm-tip. > > > > Signed-off-by: Mika Kuoppala > > Signed-off-by: Prathap Kumar Valsan > > Signed-off-by: Akeem G Abodunrin > > Cc: Chris Wilson > > Cc: Balestrieri Francesco > > Cc: Bloomfield Jon > > Cc: Dutt Sudeep > > --- > > drivers/gpu/drm/i915/Makefile | 1 + > > drivers/gpu/drm/i915/gt/gen7_renderclear.c| 535 ++ > > drivers/gpu/drm/i915/gt/gen7_renderclear.h| 15 + > > drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 17 +- > > .../gpu/drm/i915/gt/intel_ring_submission.c | 3 +- > > drivers/gpu/drm/i915/i915_utils.h | 5 + > > 6 files changed, 572 insertions(+), 4 deletions(-) > > create mode 100644 drivers/gpu/drm/i915/gt/gen7_renderclear.c > > create mode 100644 drivers/gpu/drm/i915/gt/gen7_renderclear.h > > > > diff --git a/drivers/gpu/drm/i915/Makefile > b/drivers/gpu/drm/i915/Makefile > > index 3c88d7d8c764..f96bae664a03 100644 > > --- a/drivers/gpu/drm/i915/Makefile > > +++ b/drivers/gpu/drm/i915/Makefile > > @@ -78,6 +78,7 @@ gt-y += \ > > gt/debugfs_gt.o \ > > gt/debugfs_gt_pm.o \ > > gt/gen6_ppgtt.o \ > > + gt/gen7_renderclear.o \ > > gt/gen8_ppgtt.o \ > > gt/intel_breadcrumbs.o \ > > gt/intel_context.o \ > > diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c > b/drivers/gpu/drm/i915/gt/gen7_renderclear.c > > new file mode 100644 > > index ..a6f5f1602e33 > > --- /dev/null > > +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c > > @@ -0,0 +1,535 @@ > > +// SPDX-License-Identifier: MIT > > +/* > > + * Copyright © 2019 Intel Corporation > > + */ > > + > > +#include "gen7_renderclear.h" > > +#include "i915_drv.h" > > +#include "i915_utils.h" > > +#include "intel_gpu_commands.h" > > + > > +#define MAX_URB_ENTRIES 64 > > +#define STATE_SIZE (4 * 1024) > > +#define GT3_INLINE_DATA_DELAYS 0x1E00 > > +#define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS)) > > + > > +/* > > + * Media CB Kernel for gen7 devices > > + * TODO: Add comments to kernel, indicating what each array of hex does > or > > + * include header file, which has assembly source and support in igt to be > > + * able to generate kernel in this same format > > + */ > > Having the original source code for the kernels in IGT is the > best way to proceed. The kernels should also be split into > separate files which can be generated from IGT and copied > over as-is for easy verification. > > Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/guc: Introduce guc_is_ready
Quoting Michal Wajdeczko (2020-01-31 15:37:06) > We already have guc_is_running function, but it only reflects > firmware status, while to fully use GuC we need to know if we've > already established communication with it. > > v2: also s/intel_guc_is_running/intel_guc_is_fw_running (Chris) > > Signed-off-by: Michal Wajdeczko > Cc: Daniele Ceraolo Spurio > Cc: Chris Wilson It's a small change, but it does read much better. Reviewed-by: Chris Wilson (I hope the crux of the change is ok :) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/guc: Introduce guc_is_ready
We already have guc_is_running function, but it only reflects
firmware status, while to fully use GuC we need to know if we've
already established communication with it.
v2: also s/intel_guc_is_running/intel_guc_is_fw_running (Chris)
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 7 ++-
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 10 +-
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
5 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 910d49590068..7ca9e5159f05 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -148,11 +148,16 @@ static inline bool intel_guc_is_enabled(struct intel_guc
*guc)
return intel_uc_fw_is_enabled(>fw);
}
-static inline bool intel_guc_is_running(struct intel_guc *guc)
+static inline bool intel_guc_is_fw_running(struct intel_guc *guc)
{
return intel_uc_fw_is_running(>fw);
}
+static inline bool intel_guc_is_ready(struct intel_guc *guc)
+{
+ return intel_guc_is_fw_running(guc) && intel_guc_ct_enabled(>ct);
+}
+
static inline int intel_guc_sanitize(struct intel_guc *guc)
{
intel_uc_fw_sanitize(>fw);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index d84812683364..11742fca0e9e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -279,7 +279,7 @@ void intel_guc_ct_disable(struct intel_guc_ct *ct)
ct->enabled = false;
- if (intel_guc_is_running(guc)) {
+ if (intel_guc_is_fw_running(guc)) {
ct_deregister_buffer(ct, INTEL_GUC_CT_BUFFER_TYPE_SEND);
ct_deregister_buffer(ct, INTEL_GUC_CT_BUFFER_TYPE_RECV);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 64934a876a50..affc4d6f9ead 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -505,7 +505,7 @@ static void __uc_fini_hw(struct intel_uc *uc)
{
struct intel_guc *guc = >guc;
- if (!intel_guc_is_running(guc))
+ if (!intel_guc_is_fw_running(guc))
return;
if (intel_uc_supports_guc_submission(uc))
@@ -527,7 +527,7 @@ void intel_uc_reset_prepare(struct intel_uc *uc)
{
struct intel_guc *guc = >guc;
- if (!intel_guc_is_running(guc))
+ if (!intel_guc_is_ready(guc))
return;
guc_disable_communication(guc);
@@ -539,7 +539,7 @@ void intel_uc_runtime_suspend(struct intel_uc *uc)
struct intel_guc *guc = >guc;
int err;
- if (!intel_guc_is_running(guc))
+ if (!intel_guc_is_ready(guc))
return;
err = intel_guc_suspend(guc);
@@ -554,7 +554,7 @@ void intel_uc_suspend(struct intel_uc *uc)
struct intel_guc *guc = >guc;
intel_wakeref_t wakeref;
- if (!intel_guc_is_running(guc))
+ if (!intel_guc_is_ready(guc))
return;
with_intel_runtime_pm(uc_to_gt(uc)->uncore->rpm, wakeref)
@@ -566,7 +566,7 @@ static int __uc_resume(struct intel_uc *uc, bool
enable_communication)
struct intel_guc *guc = >guc;
int err;
- if (!intel_guc_is_running(guc))
+ if (!intel_guc_is_fw_running(guc))
return 0;
/* Make sure we enable communication if and only if it's disabled */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 2d76138c349f..e329503b68c2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1914,7 +1914,7 @@ static int i915_guc_log_relay_open(struct inode *inode,
struct file *file)
struct intel_guc *guc = >gt.uc.guc;
struct intel_guc_log *log = >log;
- if (!intel_guc_is_running(guc))
+ if (!intel_guc_is_ready(guc))
return -ENODEV;
file->private_data = log;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a8a08c63278e..404699382ac6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2033,7 +2033,7 @@ i915_coherent_map_type(struct drm_i915_private *i915)
static inline bool intel_guc_submission_is_enabled(struct intel_guc *guc)
{
return intel_guc_is_submission_supported(guc) &&
- intel_guc_is_running(guc);
+ intel_guc_is_ready(guc);
}
#endif
--
2.19.2
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Re: [Intel-gfx] [PATCH] drm/i915/guc: Stop using mutex while sending CTB messages
Quoting Michal Wajdeczko (2020-01-31 14:58:34) > While we are always using CT "send" buffer to send request messages > to GuC, we usually don't ask GuC to use CT "receive" buffer to send > back response messages, since almost all returned data can fit into > reserved bits in status dword inside CT descriptor. However, relying > on data modifications inside CT descriptor requires use of mutex to > allow only single CT request in flight, until we read back that status > dword from the CT descriptor. Q. do we need the same lock for ct_read() and ct_write()? Could ct_read() use a lock-free ringbuffer, and then if I've read it right, you wouldn't have any overlapping spinlock between the interrupt handler and the rest (thus avoiding the interrupt-off). -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH v2] drm/i915: Never allow userptr into the new mapping types
Commit 4f2a572eda67 ("drm/i915/userptr: Never allow userptr into the
mappable GGTT") made I915_GEM_MMAP_GTT IOCTLs to fail when attempted
on a userptr object in order to protect from a lockdep splat. Later
on, new mapping types were introduced by commit cc662126b413
("drm/i915: Introduce DRM_I915_GEM_MMAP_OFFSET"). Those new mapping
types suffer from the same lockdep splat issue but they now succeed
when tried on top of a userptr object. Fix it.
v2: Don't play with the -ENODEV driver response (Chris)
Signed-off-by: Janusz Krzysztofik
Cc: Abdiel Janulgue
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 3 +--
drivers/gpu/drm/i915/gem/i915_gem_object.h | 4 ++--
drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 2 +-
5 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 879fff8adc48..2a3b428a103e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -553,8 +553,7 @@ __assign_mmap_offset(struct drm_file *file,
if (!obj)
return -ENOENT;
- if (mmap_type == I915_MMAP_TYPE_GTT &&
- i915_gem_object_never_bind_ggtt(obj)) {
+ if (i915_gem_object_never_mmap(obj)) {
err = -ENODEV;
goto out;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 858f8bf49a04..3fd0d6e9eec8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -185,9 +185,9 @@ i915_gem_object_is_proxy(const struct drm_i915_gem_object
*obj)
}
static inline bool
-i915_gem_object_never_bind_ggtt(const struct drm_i915_gem_object *obj)
+i915_gem_object_never_mmap(const struct drm_i915_gem_object *obj)
{
- return i915_gem_object_type_has(obj, I915_GEM_OBJECT_NO_GGTT);
+ return i915_gem_object_type_has(obj, I915_GEM_OBJECT_NO_MMAP);
}
static inline bool
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 88e268633fdc..bb66d44fc1c4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -34,7 +34,7 @@ struct drm_i915_gem_object_ops {
#define I915_GEM_OBJECT_HAS_IOMEM BIT(1)
#define I915_GEM_OBJECT_IS_SHRINKABLE BIT(2)
#define I915_GEM_OBJECT_IS_PROXY BIT(3)
-#define I915_GEM_OBJECT_NO_GGTTBIT(4)
+#define I915_GEM_OBJECT_NO_MMAPBIT(4)
#define I915_GEM_OBJECT_ASYNC_CANCEL BIT(5)
/* Interface between the GEM object and its backing storage.
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index e5558af111e2..da79cc9e57bf 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -703,7 +703,7 @@ i915_gem_userptr_dmabuf_export(struct drm_i915_gem_object
*obj)
static const struct drm_i915_gem_object_ops i915_gem_userptr_ops = {
.flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
I915_GEM_OBJECT_IS_SHRINKABLE |
-I915_GEM_OBJECT_NO_GGTT |
+I915_GEM_OBJECT_NO_MMAP |
I915_GEM_OBJECT_ASYNC_CANCEL,
.get_pages = i915_gem_userptr_get_pages,
.put_pages = i915_gem_userptr_put_pages,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 9ddcf17230e6..334a578ce85f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -923,7 +923,7 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
struct i915_vma *vma;
int ret;
- if (i915_gem_object_never_bind_ggtt(obj))
+ if (i915_gem_object_never_mmap(obj))
return ERR_PTR(-ENODEV);
if (flags & PIN_MAPPABLE &&
--
2.21.0
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Re: [Intel-gfx] [PATCH v16 6/7] drm/i915: Protect intel_dbuf_slices_update with mutex
On Tue, Jan 28, 2020 at 03:33:11PM -0800, Matt Roper wrote:
> On Fri, Jan 24, 2020 at 10:44:55AM +0200, Stanislav Lisovskiy wrote:
> > Now using power_domain mutex to protect from race condition, which
> > can occur because intel_dbuf_slices_update might be running in
> > parallel to gen9_dc_off_power_well_enable being called from
> > intel_dp_detect for instance, which causes assertion triggered by
> > race condition, as gen9_assert_dbuf_enabled might preempt this
> > when registers were already updated, while dev_priv was not.
>
> I may be overlooking something, but I think your next patch already
> takes care of this by ensuring we only do dbuf updates during modesets.
> We already had POWER_DOMAIN_MODESET in our various DC_OFF_POWER_DOMAINS
> definitions which would ensure that the "DC off" power well is enabled
> (and DC states themselves are disabled) for the entire duration of the
> modeset process.
Hmm. That's assuming we only do the dbuf assert from the dc off
power well hook. Can't remember if that's the case. If that's not
the only place then we probably miss the lock somewhere else too.
>
> If we need this, I'm not sure whether it's a good idea to use
> power_domains->lock rather than a new, dedicated lock. Anything that
> touches power domains in any manner grabs this lock, even though we only
> really care about it for stopping races with the specific "DC off" power
> well.
Separate lock feels a bit overkill to me for something small
like this.
>
> Also, if we bisect to the point right before these last two patches,
> don't we have a problem since there's a point in the git history where
> we potentially face a race?
Yeah should be earlier in the series I guess. If we need it at all,
which as you point out maybe we don't with the state->modeset checks.
Though maybe we want to get rid of that state->modeset dependency.
I *think* we should start using the global state stuff for dbuf
management, but haven't really looked at the details to figure out
how to organize it in the end. So at that point we may not anymore
be holding the dc off reference (although one might argue that we
should always hold that for dbuf programming so the "wait for it
to enable" thing can't be perturbed by dc transitions).
Anyways for now this seems fine by me
Reviewed-by: Ville Syrjälä
>
>
> Matt
>
> >
> > Signed-off-by: Stanislav Lisovskiy
> > ---
> > drivers/gpu/drm/i915/display/intel_display_power.c | 12
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 96b38252578b..99ddc21e004c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -4404,12 +4404,22 @@ void icl_dbuf_slices_update(struct drm_i915_private
> > *dev_priv,
> > {
> > int i;
> > int max_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
> > + struct i915_power_domains *power_domains = _priv->power_domains;
> >
> > WARN(hweight8(req_slices) > max_slices,
> > "Invalid number of dbuf slices requested\n");
> >
> > DRM_DEBUG_KMS("Updating dbuf slices to 0x%x\n", req_slices);
> >
> > + /*
> > +* Might be running this in parallel to gen9_dc_off_power_well_enable
> > +* being called from intel_dp_detect for instance,
> > +* which causes assertion triggered by race condition,
> > +* as gen9_assert_dbuf_enabled might preempt this when registers
> > +* were already updated, while dev_priv was not.
> > +*/
> > + mutex_lock(_domains->lock);
> > +
> > for (i = 0; i < max_slices; i++) {
> > intel_dbuf_slice_set(dev_priv,
> > _DBUF_CTL_S(i),
> > @@ -4417,6 +4427,8 @@ void icl_dbuf_slices_update(struct drm_i915_private
> > *dev_priv,
> > }
> >
> > dev_priv->enabled_dbuf_slices_mask = req_slices;
> > +
> > + mutex_unlock(_domains->lock);
> > }
> >
> > static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
> > --
> > 2.24.1.485.gad05a3d8e5
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
--
Ville Syrjälä
Intel
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsb: Enable lmem for dsb
== Series Details ==
Series: drm/i915/dsb: Enable lmem for dsb
URL : https://patchwork.freedesktop.org/series/72818/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7850 -> Patchwork_16355
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16355/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_16355:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_execlists:
- {fi-tgl-u}: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-tgl-u/igt@i915_selftest@live_execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16355/fi-tgl-u/igt@i915_selftest@live_execlists.html
Known issues
Here are the changes found in Patchwork_16355 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_close_race@basic-threads:
- fi-hsw-peppy: [PASS][3] -> [TIMEOUT][4] ([fdo#112271] / [i915#1084])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-hsw-peppy/igt@gem_close_r...@basic-threads.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16355/fi-hsw-peppy/igt@gem_close_r...@basic-threads.html
* igt@i915_selftest@live_blt:
- fi-hsw-4770r: [PASS][5] -> [DMESG-FAIL][6] ([i915#563])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-hsw-4770r/igt@i915_selftest@live_blt.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16355/fi-hsw-4770r/igt@i915_selftest@live_blt.html
Possible fixes
* igt@gem_close_race@basic-threads:
- fi-byt-n2820: [TIMEOUT][7] ([fdo#112271] / [i915#1084] /
[i915#816]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-byt-n2820/igt@gem_close_r...@basic-threads.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16355/fi-byt-n2820/igt@gem_close_r...@basic-threads.html
* igt@gem_exec_store@basic-all:
- fi-apl-guc: [TIMEOUT][9] ([fdo#112271]) -> [PASS][10] +8 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-apl-guc/igt@gem_exec_st...@basic-all.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16355/fi-apl-guc/igt@gem_exec_st...@basic-all.html
* igt@gem_tiled_fence_blits@basic:
- fi-apl-guc: [SKIP][11] ([fdo#109271]) -> [PASS][12] +47 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-apl-guc/igt@gem_tiled_fence_bl...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16355/fi-apl-guc/igt@gem_tiled_fence_bl...@basic.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#111407]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16355/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
[i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084
[i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563
[i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816
Participating hosts (43 -> 44)
--
Additional (10): fi-bdw-5557u fi-bsw-n3050 fi-byt-j1900 fi-skl-6770hq
fi-whl-u fi-gdg-551 fi-ivb-3770 fi-elk-e7500 fi-kbl-r fi-snb-2600
Missing(9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ilk-650 fi-kbl-7560u fi-tgl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7850 -> Patchwork_16355
CI-20190529: 20190529
CI_DRM_7850: ae66f2257648ce52c51298506977baa32873c9d5 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5407: a9d69f51dadbcbc53527671f87572d05c3370cba @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16355: 1dd958225f8bd0be5aec69f0ff5bc3c942607f26 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
1dd958225f8b drm/i915/dsb: Enable lmem for dsb
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16355/index.html
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Re: [Intel-gfx] [PATCH v16 7/7] drm/i915: Update dbuf slices only with full modeset
On Tue, Jan 28, 2020 at 03:37:06PM -0800, Matt Roper wrote:
> On Fri, Jan 24, 2020 at 10:44:56AM +0200, Stanislav Lisovskiy wrote:
> > During full modeset, global state(i.e dev_priv) is protected
> > by locking the crtcs in state, otherwise global state is not
> > serialized. Also if it is not a full modeset, we anyway
> > don't need to change DBuf slice configuration as Pipe configuration
> > doesn't change.
>
> Looks correct, but don't we need this earlier so that we don't have a
> bad bisection point in the git history (assuming we rely on this rather
> than the extra locking from the previous patch to cover the DC off
> race)?
Could perhaps just squash into the patch that moves these calls here.
Or move just after that patch in the series.
Reviewed-by: Ville Syrjälä
>
>
> Matt
>
> >
> > Signed-off-by: Stanislav Lisovskiy
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 6 --
> > 1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 1c957df5c28c..888a9e94032e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -15373,7 +15373,8 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> > intel_encoders_update_prepare(state);
> >
> > /* Enable all new slices, we might need */
> > - icl_dbuf_slice_pre_update(state);
> > + if (state->modeset)
> > + icl_dbuf_slice_pre_update(state);
> >
> > /* Now enable the clocks, plane, pipe, and connectors that we set up. */
> > dev_priv->display.commit_modeset_enables(state);
> > @@ -15432,7 +15433,8 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> > }
> >
> > /* Disable all slices, we don't need */
> > - icl_dbuf_slice_post_update(state);
> > + if (state->modeset)
> > + icl_dbuf_slice_post_update(state);
> >
> > for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> > new_crtc_state, i) {
> > intel_post_plane_update(state, crtc);
> > --
> > 2.24.1.485.gad05a3d8e5
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
--
Ville Syrjälä
Intel
___
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Re: [Intel-gfx] [RFC PATCH 1/1] drm/i915: Never allow userptr into the new mapping types
On Friday, January 31, 2020 3:32:21 PM CET Chris Wilson wrote:
> Quoting Janusz Krzysztofik (2020-01-31 13:20:37)
> > Commit 4f2a572eda67 ("drm/i915/userptr: Never allow userptr into the
> > mappable GGTT") made I915_GEM_MMAP_GTT IOCTLs to fail when atepmted
> > on a userptr object in order to protect from a lockdep splat. Later
> > on, new mapping types were introduced by commit cc662126b413
> > ("drm/i915: Introduce DRM_I915_GEM_MMAP_OFFSET"). Those new mapping
> > types suffer from the same lockdep splat issue but they now succeed
> > when tried on top of a userptr object. Fix it.
> >
> > While being at it, return -EINVAL which seems to better reflect the
> > reason for the failure than -ENODEV.
>
> No. It is not a user error, it's a failure to implement support for it,
> so we parcel it off as an incompatible device.
How about -ENOTSUP?
Thanks,
Janusz
> -Chris
>
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Re: [Intel-gfx] [PATCH 02/17] drm/i915: Move linetime wms into the crtc state
On Mon, Jan 20, 2020 at 07:47:12PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > The linetime watermarks really have very little in common with the > plane watermarks. It looks to be cleaner to simply track them in > the crtc_state and program them from the normal modeset/fastset > paths. > > The only dark cloud comes from the fact that the register is > still supposedly single buffered. So in theory it might still > need some form of two stage programming. Note that even though > HSW/BDWhave two stage programming we never computed any special > intermediate values for the linetime watermarks, and on SKL+ > we don't even have the two stage stuff plugged in since everything > else is double buffered. So let's assume it's all fine and > continue doing what we've been doing. > > Actually on HSW/BDW the value should not even change without > a full modeset since it doesn't account for pfit downscaling. > Thus only fastboot might be affected. But on SKL+ the pfit > scaling factor is take into consideration so the value may > change during any fastset. > > As a bonus we'll plug this thing into the state > checker/dump now. > > v2: Rebase due to bigjoiner prep > v2: Only compute ips linetime for IPS capable pipes. > Bspec says the register values is ignored for other > pipes, but in fact it can't even be written so the > state checker becomes unhappy if we don't compute > it as zero. > > Cc: Stanislav Lisovskiy > Signed-off-by: Ville Syrjälä Extracted Stan's r-b from the trybot list (whoops) and pushed the lot: https://lists.freedesktop.org/archives/intel-gfx-trybot/2020-January/086561.html Thanks for the reviews. As Imre pointed out there some further docs/function naming improvements should probably be done to make the thing a bit less confusing. I'll look at that as a followup. -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Also wait for the scratch buffer to be bound
Chris Wilson writes:
> Since PIN_GLOBAL is no longer guaranteed to be synchronous, we must no
> forget to include a wait-for-vma prior to execution.
Dunno if we got em all, we soon know.
Cried for helper but lets move first,
Reviewed-by: Mika Kuoppala
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 ++
> drivers/gpu/drm/i915/gt/selftest_lrc.c| 33 +++
> .../gpu/drm/i915/gt/selftest_workarounds.c| 9 +
> 3 files changed, 52 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 5a7db279f702..8d7c3191137c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1612,6 +1612,16 @@ static int engine_wa_list_verify(struct intel_context
> *ce,
> goto err_vma;
> }
>
> + i915_vma_lock(vma);
> + err = i915_request_await_object(rq, vma->obj, true);
> + if (err == 0)
> + err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
> + i915_vma_unlock(vma);
> + if (err) {
> + i915_request_add(rq);
> + goto err_vma;
> + }
> +
> err = wa_list_srm(rq, wal, vma);
> if (err)
> goto err_vma;
> diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> index f5214a374fb7..0efb46665667 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> @@ -734,6 +734,10 @@ static int live_timeslice_preempt(void *arg)
> if (err)
> goto err_map;
>
> + err = i915_vma_sync(vma);
> + if (err)
> + goto err_pin;
> +
> for_each_prime_number_from(count, 1, 16) {
> struct intel_engine_cs *engine;
> enum intel_engine_id id;
> @@ -827,6 +831,10 @@ static int live_timeslice_queue(void *arg)
> if (err)
> goto err_map;
>
> + err = i915_vma_sync(vma);
> + if (err)
> + goto err_unpin;
> +
> for_each_engine(engine, gt, id) {
> struct i915_sched_attr attr = {
> .priority = I915_USER_PRIORITY(I915_PRIORITY_MAX),
> @@ -913,6 +921,7 @@ static int live_timeslice_queue(void *arg)
> break;
> }
>
> +err_unpin:
> i915_vma_unpin(vma);
> err_map:
> i915_gem_object_unpin_map(obj);
> @@ -971,6 +980,10 @@ static int live_busywait_preempt(void *arg)
> if (err)
> goto err_map;
>
> + err = i915_vma_sync(vma);
> + if (err)
> + goto err_vma;
> +
> for_each_engine(engine, gt, id) {
> struct i915_request *lo, *hi;
> struct igt_live_test t;
> @@ -3204,6 +3217,10 @@ static int preserved_virtual_engine(struct intel_gt
> *gt,
> if (IS_ERR(scratch))
> return PTR_ERR(scratch);
>
> + err = i915_vma_sync(scratch);
> + if (err)
> + goto out_scratch;
> +
> ve = intel_execlists_create_virtual(siblings, nsibling);
> if (IS_ERR(ve)) {
> err = PTR_ERR(ve);
> @@ -4030,8 +4047,16 @@ static int __live_lrc_state(struct intel_engine_cs
> *engine,
> *cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32);
> *cs++ = 0;
>
> + i915_vma_lock(scratch);
> + err = i915_request_await_object(rq, scratch->obj, true);
> + if (!err)
> + err = i915_vma_move_to_active(scratch, rq, EXEC_OBJECT_WRITE);
> + i915_vma_unlock(scratch);
> +
> i915_request_get(rq);
> i915_request_add(rq);
> + if (err)
> + goto err_rq;
>
> intel_engine_flush_submission(engine);
> expected[RING_TAIL_IDX] = ce->ring->tail;
> @@ -4166,8 +4191,16 @@ static int __live_gpr_clear(struct intel_engine_cs
> *engine,
> *cs++ = 0;
> }
>
> + i915_vma_lock(scratch);
> + err = i915_request_await_object(rq, scratch->obj, true);
> + if (!err)
> + err = i915_vma_move_to_active(scratch, rq, EXEC_OBJECT_WRITE);
> + i915_vma_unlock(scratch);
> +
> i915_request_get(rq);
> i915_request_add(rq);
> + if (err)
> + goto err_rq;
>
> if (i915_request_wait(rq, 0, HZ / 5) < 0) {
> err = -ETIME;
> diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> index ac1921854cbf..5ed323254ee1 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> @@ -583,6 +583,15 @@ static int check_dirty_whitelist(struct intel_context
> *ce)
> if (err)
> goto err_request;
>
> + i915_vma_lock(scratch);
> + err = i915_request_await_object(rq, scratch->obj, true);
> + if (err == 0)
> + err = i915_vma_move_to_active(scratch, rq,
> +
[Intel-gfx] [PATCH] drm/i915/guc: Stop using mutex while sending CTB messages
While we are always using CT "send" buffer to send request messages
to GuC, we usually don't ask GuC to use CT "receive" buffer to send
back response messages, since almost all returned data can fit into
reserved bits in status dword inside CT descriptor. However, relying
on data modifications inside CT descriptor requires use of mutex to
allow only single CT request in flight, until we read back that status
dword from the CT descriptor.
But some H2G actions (like AUTHENTICATE_HUC, and more to come) are
like one-way requests for which we don't care about immediate status,
since we will use a different way to confirm that given action was
completed (ie. HUC_STATUS reg is used to verify HuC authentication).
If we ask GuC to always send response messages over "receive" buffer
for all requests for which we care about their status, then we can
use CT descriptor option only for our new one-way requests, for which
status can be temporary ignored.
Since we only need to protect CT descriptor during reading/writing
from the command buffer, we can drop mutex and switch to spinlock.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Cc: John Harrison
Cc: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 147 --
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 3 +
3 files changed, 57 insertions(+), 95 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index c4c1523da7a6..d5938c1d44a2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -519,7 +519,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc)
int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
{
u32 action[] = {
- INTEL_GUC_ACTION_AUTHENTICATE_HUC,
+ INTEL_GUC_ACTION_AUTHENTICATE_HUC | GUC_SEND_FLAG_NO_RESPONSE,
rsa_offset
};
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index d84812683364..760e03cc2bad 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -41,6 +41,7 @@ static void ct_incoming_request_worker_func(struct
work_struct *w);
*/
void intel_guc_ct_init_early(struct intel_guc_ct *ct)
{
+ spin_lock_init(>lock);
spin_lock_init(>requests.lock);
INIT_LIST_HEAD(>requests.pending);
INIT_LIST_HEAD(>requests.incoming);
@@ -88,13 +89,6 @@ static void guc_ct_buffer_desc_init(struct
guc_ct_buffer_desc *desc,
desc->owner = CTB_OWNER_HOST;
}
-static void guc_ct_buffer_desc_reset(struct guc_ct_buffer_desc *desc)
-{
- desc->head = 0;
- desc->tail = 0;
- desc->is_in_error = 0;
-}
-
static int guc_action_register_ct_buffer(struct intel_guc *guc,
u32 desc_addr,
u32 type)
@@ -317,6 +311,7 @@ static int ct_write(struct intel_guc_ct *ct,
{
struct intel_guc_ct_buffer *ctb = >ctbs[CTB_SEND];
struct guc_ct_buffer_desc *desc = ctb->desc;
+ u32 action_code = action[0] & GUC_CT_MSG_ACTION_MASK;
u32 head = desc->head;
u32 tail = desc->tail;
u32 size = desc->size;
@@ -325,6 +320,8 @@ static int ct_write(struct intel_guc_ct *ct,
u32 *cmds = ctb->cmds;
unsigned int i;
+ lockdep_assert_held(>lock);
+
if (unlikely(desc->is_in_error))
return -EPIPE;
@@ -359,7 +356,7 @@ static int ct_write(struct intel_guc_ct *ct,
header = (len << GUC_CT_MSG_LEN_SHIFT) |
(GUC_CT_MSG_WRITE_FENCE_TO_DESC) |
(want_response ? GUC_CT_MSG_SEND_STATUS : 0) |
-(action[0] << GUC_CT_MSG_ACTION_SHIFT);
+(action_code << GUC_CT_MSG_ACTION_SHIFT);
CT_DEBUG(ct, "writing %*ph %*ph %*ph\n",
4, , 4, , 4 * (len - 1), [1]);
@@ -387,62 +384,11 @@ static int ct_write(struct intel_guc_ct *ct,
return -EPIPE;
}
-/**
- * wait_for_ctb_desc_update - Wait for the CT buffer descriptor update.
- * @desc: buffer descriptor
- * @fence: response fence
- * @status:placeholder for status
- *
- * Guc will update CT buffer descriptor with new fence and status
- * after processing the command identified by the fence. Wait for
- * specified fence and then read from the descriptor status of the
- * command.
- *
- * Return:
- * * 0 response received (status is valid)
- * * -ETIMEDOUT no response within hardcoded timeout
- * * -EPROTO no response, CT buffer is in error
- */
-static int wait_for_ctb_desc_update(struct guc_ct_buffer_desc *desc,
- u32 fence,
- u32 *status)
-{
- int err;
-
- /*
-* Fast commands should complete in less than 10us, so sample quickly
-* up to that length of
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsb: Enable lmem for dsb
== Series Details == Series: drm/i915/dsb: Enable lmem for dsb URL : https://patchwork.freedesktop.org/series/72818/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1dd958225f8b drm/i915/dsb: Enable lmem for dsb -:6: WARNING:TYPO_SPELLING: 'memeory' may be misspelled - perhaps 'memory'? #6: If lmem is supported DSB should use local memeory instead total: 0 errors, 1 warnings, 0 checks, 19 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH i-g-t 1/1] tests/gem_mmap_offset: Exercise mapping to userptr
On Friday, January 31, 2020 3:37:05 PM CET Chris Wilson wrote:
> Quoting Janusz Krzysztofik (2020-01-31 13:12:34)
> > Creating a mapping to a userptr backed GEM object may cause a currently
> > unavoidable lockdep splat inside the i915 driver. Then, such operation
> > is expected to fail to prevent from that badness to happen.
> >
> > Add a respective subtest for each mapping type.
> >
> > Signed-off-by: Janusz Krzysztofik
> > Cc: Matthew Auld
> > Cc: Chris Wilson
> > ---
> > tests/i915/gem_mmap_offset.c | 55
> > 1 file changed, 55 insertions(+)
> >
> > diff --git a/tests/i915/gem_mmap_offset.c b/tests/i915/gem_mmap_offset.c
> > index 7c4088cdf..a5f28328b 100644
> > --- a/tests/i915/gem_mmap_offset.c
> > +++ b/tests/i915/gem_mmap_offset.c
> > @@ -141,6 +141,36 @@ static void bad_extensions(int i915)
> > gem_close(i915, arg.handle);
> > }
> >
> > +static bool has_userptr(int i915)
> > +{
> > + uint32_t handle = 0;
> > + void *ptr;
> > +
> > + igt_assert_eq(posix_memalign(, 4096, 4096), 0);
> > + if (__gem_userptr(i915, ptr, 4096, 0, 0, ) == 0)
> > + gem_close(i915, handle);
> > + free(ptr);
> > +
> > + return handle;
> > +}
> > +
> > +static void userptr(int i915, uint64_t flags)
> > +{
> > + struct drm_i915_gem_mmap_offset arg = {
> > + .flags = flags,
> > + };
> > + void *ptr;
> > +
> > + igt_assert_eq(posix_memalign(, 4096, 4096), 0);
> > +
> > + gem_userptr(i915, ptr, 4096, 0, 0, );
> > +
> > + igt_assert_eq(mmap_offset_ioctl(i915, ), -EINVAL);
>
> Not quite. The only reason it doesn't work is because the implementation
> ties itself into knots, not that it is meant to not work. :|
Are you suggesting the test should fail if the IOCTL fails? That would be
fair, but how are we going to have that accepted by CI then, and merged?
Skipping also doesn't seem a good option to me.
I can add some more exhaustive examination should the IOCTL succeed, but that
won't help to make CI happy.
>From your long experience, what approach should we take?
Thanks,
Janusz
> -Chris
>
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt (rev2)
== Series Details == Series: series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt (rev2) URL : https://patchwork.freedesktop.org/series/72809/ State : success == Summary == CI Bug Log - changes from CI_DRM_7850 -> Patchwork_16354 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16354/index.html Known issues Here are the changes found in Patchwork_16354 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][1] -> [DMESG-FAIL][2] ([i915#725]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-hsw-4770r/igt@i915_selftest@live_blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16354/fi-hsw-4770r/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-cfl-8700k: [PASS][3] -> [INCOMPLETE][4] ([i915#424]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16354/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-n2820: [TIMEOUT][5] ([fdo#112271] / [i915#1084] / [i915#816]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16354/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@gem_exec_store@basic-all: - fi-apl-guc: [TIMEOUT][7] ([fdo#112271]) -> [PASS][8] +8 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-apl-guc/igt@gem_exec_st...@basic-all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16354/fi-apl-guc/igt@gem_exec_st...@basic-all.html * igt@gem_tiled_fence_blits@basic: - fi-apl-guc: [SKIP][9] ([fdo#109271]) -> [PASS][10] +47 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-apl-guc/igt@gem_tiled_fence_bl...@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16354/fi-apl-guc/igt@gem_tiled_fence_bl...@basic.html * igt@kms_addfb_basic@bad-pitch-32: - fi-tgl-y: [DMESG-WARN][11] ([CI#94] / [i915#402]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-32.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16354/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-32.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][13] ([fdo#111407]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16354/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816 Participating hosts (43 -> 39) -- Additional (7): fi-bsw-n3050 fi-byt-j1900 fi-skl-6770hq fi-snb-2520m fi-whl-u fi-elk-e7500 fi-kbl-r Missing(11): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-glk-dsi fi-byt-squawks fi-bsw-cyan fi-cfl-8109u fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7850 -> Patchwork_16354 CI-20190529: 20190529 CI_DRM_7850: ae66f2257648ce52c51298506977baa32873c9d5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5407: a9d69f51dadbcbc53527671f87572d05c3370cba @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16354: 0221737f059279a78c56ee70b14fe8747947f100 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0221737f0592 drm/i915/selftests: Also wait for the scratch buffer to be bound bb9f5c3f2305 drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16354/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 1/1] drm/i915: Never allow userptr into the new mapping types
On Friday, January 31, 2020 3:32:21 PM CET Chris Wilson wrote:
> Quoting Janusz Krzysztofik (2020-01-31 13:20:37)
> > Commit 4f2a572eda67 ("drm/i915/userptr: Never allow userptr into the
> > mappable GGTT") made I915_GEM_MMAP_GTT IOCTLs to fail when atepmted
> > on a userptr object in order to protect from a lockdep splat. Later
> > on, new mapping types were introduced by commit cc662126b413
> > ("drm/i915: Introduce DRM_I915_GEM_MMAP_OFFSET"). Those new mapping
> > types suffer from the same lockdep splat issue but they now succeed
> > when tried on top of a userptr object. Fix it.
> >
> > While being at it, return -EINVAL which seems to better reflect the
> > reason for the failure than -ENODEV.
>
> No. It is not a user error, it's a failure to implement support for it,
> so we parcel it off as an incompatible device.
OK, if there is no better option I'll revert that to -ENODEV and resubmit.
Thanks,
Janusz
> -Chris
>
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt
Chris Wilson writes:
> In the rare cases where we are using the global GGTT for execution in
> the selftests, we have marked them with PIN_USER knowing that they will
> be bound as PIN_GLOBAL as well. However, we need to catch the extra flag
> in deciding to use the async worker for such binds as well.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index 3b23b431bd56..9e8c2e189aef 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -846,7 +846,8 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
> IS_CHERRYVIEW(i915) /* fails with concurrent use/update */) {
> ggtt->vm.insert_entries = bxt_vtd_ggtt_insert_entries__BKL;
> ggtt->vm.insert_page= bxt_vtd_ggtt_insert_page__BKL;
> - ggtt->vm.bind_async_flags = I915_VMA_GLOBAL_BIND;
> + ggtt->vm.bind_async_flags =
> + I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
> }
>
> ggtt->invalidate = gen8_ggtt_invalidate;
> --
> 2.25.0
>
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Re: [Intel-gfx] [RFC PATCH i-g-t 1/1] tests/gem_mmap_offset: Exercise mapping to userptr
Quoting Janusz Krzysztofik (2020-01-31 13:12:34)
> Creating a mapping to a userptr backed GEM object may cause a currently
> unavoidable lockdep splat inside the i915 driver. Then, such operation
> is expected to fail to prevent from that badness to happen.
>
> Add a respective subtest for each mapping type.
>
> Signed-off-by: Janusz Krzysztofik
> Cc: Matthew Auld
> Cc: Chris Wilson
> ---
> tests/i915/gem_mmap_offset.c | 55
> 1 file changed, 55 insertions(+)
>
> diff --git a/tests/i915/gem_mmap_offset.c b/tests/i915/gem_mmap_offset.c
> index 7c4088cdf..a5f28328b 100644
> --- a/tests/i915/gem_mmap_offset.c
> +++ b/tests/i915/gem_mmap_offset.c
> @@ -141,6 +141,36 @@ static void bad_extensions(int i915)
> gem_close(i915, arg.handle);
> }
>
> +static bool has_userptr(int i915)
> +{
> + uint32_t handle = 0;
> + void *ptr;
> +
> + igt_assert_eq(posix_memalign(, 4096, 4096), 0);
> + if (__gem_userptr(i915, ptr, 4096, 0, 0, ) == 0)
> + gem_close(i915, handle);
> + free(ptr);
> +
> + return handle;
> +}
> +
> +static void userptr(int i915, uint64_t flags)
> +{
> + struct drm_i915_gem_mmap_offset arg = {
> + .flags = flags,
> + };
> + void *ptr;
> +
> + igt_assert_eq(posix_memalign(, 4096, 4096), 0);
> +
> + gem_userptr(i915, ptr, 4096, 0, 0, );
> +
> + igt_assert_eq(mmap_offset_ioctl(i915, ), -EINVAL);
Not quite. The only reason it doesn't work is because the implementation
ties itself into knots, not that it is meant to not work. :|
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/12] drm/i915/gem: Require per-engine reset support for non-persistent contexts
== Series Details == Series: series starting with [01/12] drm/i915/gem: Require per-engine reset support for non-persistent contexts URL : https://patchwork.freedesktop.org/series/72813/ State : success == Summary == CI Bug Log - changes from CI_DRM_7850 -> Patchwork_16353 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16353/index.html Known issues Here are the changes found in Patchwork_16353 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_active: - fi-icl-y: [PASS][1] -> [DMESG-FAIL][2] ([i915#765]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-icl-y/igt@i915_selftest@live_active.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16353/fi-icl-y/igt@i915_selftest@live_active.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: [PASS][3] -> [FAIL][4] ([i915#217]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16353/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html * igt@prime_self_import@basic-llseek-bad: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([CI#94] / [i915#402]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-tgl-y/igt@prime_self_imp...@basic-llseek-bad.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16353/fi-tgl-y/igt@prime_self_imp...@basic-llseek-bad.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-n2820: [TIMEOUT][7] ([fdo#112271] / [i915#1084] / [i915#816]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16353/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@gem_exec_store@basic-all: - fi-apl-guc: [TIMEOUT][9] ([fdo#112271]) -> [PASS][10] +8 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-apl-guc/igt@gem_exec_st...@basic-all.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16353/fi-apl-guc/igt@gem_exec_st...@basic-all.html * igt@gem_exec_suspend@basic-s4-devices: - fi-tgl-y: [FAIL][11] ([CI#94]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16353/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html * igt@gem_tiled_fence_blits@basic: - fi-apl-guc: [SKIP][13] ([fdo#109271]) -> [PASS][14] +47 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-apl-guc/igt@gem_tiled_fence_bl...@basic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16353/fi-apl-guc/igt@gem_tiled_fence_bl...@basic.html * igt@kms_addfb_basic@bad-pitch-32: - fi-tgl-y: [DMESG-WARN][15] ([CI#94] / [i915#402]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-32.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16353/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-32.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][17] ([fdo#111407]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16353/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Warnings * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][19] ([i915#553] / [i915#725]) -> [DMESG-FAIL][20] ([i915#770]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/fi-hsw-4770/igt@i915_selftest@live_blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16353/fi-hsw-4770/igt@i915_selftest@live_blt.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084 [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#765]: https://gitlab.freedesktop.org/drm/intel/issues/765 [i915#770]: https://gitlab.freedesktop.org/drm/intel/issues/770 [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816 Participating hosts (43 -> 45)
Re: [Intel-gfx] [RFC PATCH 1/1] drm/i915: Never allow userptr into the new mapping types
Quoting Janusz Krzysztofik (2020-01-31 13:20:37)
> Commit 4f2a572eda67 ("drm/i915/userptr: Never allow userptr into the
> mappable GGTT") made I915_GEM_MMAP_GTT IOCTLs to fail when atepmted
> on a userptr object in order to protect from a lockdep splat. Later
> on, new mapping types were introduced by commit cc662126b413
> ("drm/i915: Introduce DRM_I915_GEM_MMAP_OFFSET"). Those new mapping
> types suffer from the same lockdep splat issue but they now succeed
> when tried on top of a userptr object. Fix it.
>
> While being at it, return -EINVAL which seems to better reflect the
> reason for the failure than -ENODEV.
No. It is not a user error, it's a failure to implement support for it,
so we parcel it off as an incompatible device.
-Chris
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[Intel-gfx] [PATCH] drm/i915/selftests: Also wait for the scratch buffer to be bound
Since PIN_GLOBAL is no longer guaranteed to be synchronous, we must no
forget to include a wait-for-vma prior to execution.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 ++
drivers/gpu/drm/i915/gt/selftest_lrc.c| 33 +++
.../gpu/drm/i915/gt/selftest_workarounds.c| 9 +
3 files changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 5a7db279f702..8d7c3191137c 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1612,6 +1612,16 @@ static int engine_wa_list_verify(struct intel_context
*ce,
goto err_vma;
}
+ i915_vma_lock(vma);
+ err = i915_request_await_object(rq, vma->obj, true);
+ if (err == 0)
+ err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+ i915_vma_unlock(vma);
+ if (err) {
+ i915_request_add(rq);
+ goto err_vma;
+ }
+
err = wa_list_srm(rq, wal, vma);
if (err)
goto err_vma;
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index f5214a374fb7..0efb46665667 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -734,6 +734,10 @@ static int live_timeslice_preempt(void *arg)
if (err)
goto err_map;
+ err = i915_vma_sync(vma);
+ if (err)
+ goto err_pin;
+
for_each_prime_number_from(count, 1, 16) {
struct intel_engine_cs *engine;
enum intel_engine_id id;
@@ -827,6 +831,10 @@ static int live_timeslice_queue(void *arg)
if (err)
goto err_map;
+ err = i915_vma_sync(vma);
+ if (err)
+ goto err_unpin;
+
for_each_engine(engine, gt, id) {
struct i915_sched_attr attr = {
.priority = I915_USER_PRIORITY(I915_PRIORITY_MAX),
@@ -913,6 +921,7 @@ static int live_timeslice_queue(void *arg)
break;
}
+err_unpin:
i915_vma_unpin(vma);
err_map:
i915_gem_object_unpin_map(obj);
@@ -971,6 +980,10 @@ static int live_busywait_preempt(void *arg)
if (err)
goto err_map;
+ err = i915_vma_sync(vma);
+ if (err)
+ goto err_vma;
+
for_each_engine(engine, gt, id) {
struct i915_request *lo, *hi;
struct igt_live_test t;
@@ -3204,6 +3217,10 @@ static int preserved_virtual_engine(struct intel_gt *gt,
if (IS_ERR(scratch))
return PTR_ERR(scratch);
+ err = i915_vma_sync(scratch);
+ if (err)
+ goto out_scratch;
+
ve = intel_execlists_create_virtual(siblings, nsibling);
if (IS_ERR(ve)) {
err = PTR_ERR(ve);
@@ -4030,8 +4047,16 @@ static int __live_lrc_state(struct intel_engine_cs
*engine,
*cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32);
*cs++ = 0;
+ i915_vma_lock(scratch);
+ err = i915_request_await_object(rq, scratch->obj, true);
+ if (!err)
+ err = i915_vma_move_to_active(scratch, rq, EXEC_OBJECT_WRITE);
+ i915_vma_unlock(scratch);
+
i915_request_get(rq);
i915_request_add(rq);
+ if (err)
+ goto err_rq;
intel_engine_flush_submission(engine);
expected[RING_TAIL_IDX] = ce->ring->tail;
@@ -4166,8 +4191,16 @@ static int __live_gpr_clear(struct intel_engine_cs
*engine,
*cs++ = 0;
}
+ i915_vma_lock(scratch);
+ err = i915_request_await_object(rq, scratch->obj, true);
+ if (!err)
+ err = i915_vma_move_to_active(scratch, rq, EXEC_OBJECT_WRITE);
+ i915_vma_unlock(scratch);
+
i915_request_get(rq);
i915_request_add(rq);
+ if (err)
+ goto err_rq;
if (i915_request_wait(rq, 0, HZ / 5) < 0) {
err = -ETIME;
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index ac1921854cbf..5ed323254ee1 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -583,6 +583,15 @@ static int check_dirty_whitelist(struct intel_context *ce)
if (err)
goto err_request;
+ i915_vma_lock(scratch);
+ err = i915_request_await_object(rq, scratch->obj, true);
+ if (err == 0)
+ err = i915_vma_move_to_active(scratch, rq,
+ EXEC_OBJECT_WRITE);
+ i915_vma_unlock(scratch);
+ if (err)
+ goto err_request;
+
err = engine->emit_bb_start(rq,
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt (rev2)
== Series Details == Series: series starting with [1/2] drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt (rev2) URL : https://patchwork.freedesktop.org/series/72809/ State : warning == Summary == $ dim checkpatch origin/drm-tip bb9f5c3f2305 drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt -:24: ERROR:CODE_INDENT: code indent should use tabs where possible #24: FILE: drivers/gpu/drm/i915/gt/intel_ggtt.c:850: +^I^I ^II915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;$ -:24: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #24: FILE: drivers/gpu/drm/i915/gt/intel_ggtt.c:850: +^I^I ^II915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;$ total: 1 errors, 1 warnings, 0 checks, 9 lines checked 0221737f0592 drm/i915/selftests: Also wait for the scratch buffer to be bound ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/12] drm/i915/gem: Require per-engine reset support for non-persistent contexts
== Series Details == Series: series starting with [01/12] drm/i915/gem: Require per-engine reset support for non-persistent contexts URL : https://patchwork.freedesktop.org/series/72813/ State : warning == Summary == $ dim checkpatch origin/drm-tip d94430028946 drm/i915/gem: Require per-engine reset support for non-persistent contexts 3f22ad1cf14f drm/i915/gt: Also use async bind for PIN_USER into bsw/bxt ggtt -:24: ERROR:CODE_INDENT: code indent should use tabs where possible #24: FILE: drivers/gpu/drm/i915/gt/intel_ggtt.c:850: +^I^I ^II915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;$ -:24: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #24: FILE: drivers/gpu/drm/i915/gt/intel_ggtt.c:850: +^I^I ^II915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;$ total: 1 errors, 1 warnings, 0 checks, 9 lines checked edaa3f3922af drm/i915/selftests: Also wait for the scratch buffer to be bound 1178f728bc7d drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore e88c6333db37 drm/i915/gvt: Use the pinned ce->lrc_reg_state -:44: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #44: FILE: drivers/gpu/drm/i915/gvt/scheduler.c:70: + set_context_pdp_root_pointer((struct execlist_ring_context *)regs, (void *)workload->shadow_mm->ppgtt_mm.shadow_pdps); total: 0 errors, 0 warnings, 1 checks, 88 lines checked f572562b1f0b drm/i915/gt: Pull sseu context updates under gt -:142: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #142: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 212 lines checked bc6a62afb01e drm/i915/gt: Move move context layout registers and offsets to lrc_reg.h 37da77f319f6 drm/i915/gt: Rename lrc.c to execlists_submission.c -:89: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #89: rename from drivers/gpu/drm/i915/gt/intel_lrc.c total: 0 errors, 1 warnings, 0 checks, 175 lines checked fec4d13402ab drm/i915/gt: Split logical ring context manipulation into intel_lrc.c -:47: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #47: new file mode 100644 -:749: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #749: FILE: drivers/gpu/drm/i915/gt/intel_engine_workaround_bb.c:306: + batch = batch_ptr = kmap_atomic(page); -:2668: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'count' - possible side-effects? #2668: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:132: +#define LRI(count, flags) ((flags) << 6 | (count) | BUILD_BUG_ON_ZERO(count >= BIT(6))) -:2670: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects? #2670: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:134: +#define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) -:2671: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #2671: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:135: +#define REG16(x) \ + (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x1)), \ + (((x) >> 2) & 0x7f) -:2671: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects? #2671: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:135: +#define REG16(x) \ + (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x1)), \ + (((x) >> 2) & 0x7f) -:2674: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #2674: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:138: +#define END(x) 0, (x) total: 2 errors, 1 warnings, 4 checks, 3977 lines checked 14152045734c drm/i915: Flush idle barriers when waiting 04486f9552c2 drm/i915: Allow userspace to specify ringsize on construction -:227: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #227: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 305 lines checked 5b086f11a8fe drm/i915/gem: Honour O_NONBLOCK before throttling execbuf submissions ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/guc: Introduce guc_is_ready
Quoting Michal Wajdeczko (2020-01-31 13:26:10) > We already have guc_is_running function, but it only reflects > firmware status, while to fully use GuC we need to know if we've > already established communication with it. "Ready, set, go!" ready has connotations of being before running, whereas for intel_guc_is_ready(), we are already running. Just a quibble, rationale is fine. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Disable heartbeat around hang tests
Quoting Mika Kuoppala (2020-01-31 13:22:38)
> Chris Wilson writes:
>
> > If the heartbeat fires in the middle of the preempt-hang test, it
> > consumes our forced hang disrupting the test.
> >
> > Reported-by: Daniel Vetter
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/gt/selftest_lrc.c | 10 ++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> > b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> > index 5e04ecb61dcc..f5214a374fb7 100644
> > --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> > @@ -2452,15 +2452,19 @@ static int live_preempt_hang(void *arg)
> > I915_USER_PRIORITY(I915_CONTEXT_MIN_USER_PRIORITY);
> >
> > for_each_engine(engine, gt, id) {
> > + unsigned long heartbeat;
> > struct i915_request *rq;
> >
> > if (!intel_engine_has_preemption(engine))
> > continue;
> >
> > + engine_heartbeat_disable(engine, );
> > +
> > rq = spinner_create_request(_lo, ctx_lo, engine,
> > MI_ARB_CHECK);
> > if (IS_ERR(rq)) {
> > err = PTR_ERR(rq);
> > + engine_heartbeat_enable(engine, heartbeat);
>
> Was thinking that you could grab the engine and abuse then the error
> path to enable.
>
> But too hairy.
Yeah, we've done staggered error paths, but both look ugly, So I took
the easy approach. Move the inner loop to its own test function usually
helps though.
-Chris
___
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