From: Maarten Lankhorst
DSC is available on the display emulator, but not set in DPCD.
Override the entries to allow bigjoiner testing.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/drm_dp_helper.c | 4 ++--
include/drm/drm_dp_helper.h | 1 +
2 files changed, 3 insertions(+), 2
Skip iterating over bigjoiner slaves, only the master has the state we
care about.
Add the width of the bigjoiner slave to the reconstructed fb.
Hide the bigjoiner slave to userspace, and double the mode on bigjoiner
master.
And last, disable bigjoiner slave from primary if reconstruction
From: Maarten Lankhorst
When the clock is higher than the dotclock, try with 2 pipes enabled.
If we can enable 2, then we will go into big joiner mode, and steal
the adjacent crtc.
This only links the crtc's in software, no hardware or plane
programming is done yet. Blobs are also copied
Thsi series has all the previous review commenst addressed
and Patches split into smaller patches for cleaner bisect.
Maarten Lankhorst (7):
HAX to make DSC work on the icelake test system
drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
drm/i915/dp: Allow big joiner
From: Maarten Lankhorst
We need to look at hw.fb for the framebuffer, and add the translation
for the slave_plane_state. With these changes we set the correct
rectangle on the bigjoiner slave, and don't set incorrect
src/dst/visibility on the slave plane.
v2:
* Manual rebase (Manasi)
v3:
*
From: Maarten Lankhorst
Dump debugfs and planar links as well, this will make it easier to debug
when things go wrong.
v4:
* Rebase
Changes since v1:
- Report planar slaves as such, now that we have the plane_state switch.
Changes since v2:
- Rebase on top of the new plane format dumping
Enabling is done in a special sequence and so should plane updates
be. Ideally the end user never notices the second pipe is used.
This way ideally everything will be tear free, and updates are
really atomic as userspace expects it.
This uses generic modeset_enables() calls like trans port sync
No functional changes. This patch just moves some mode checks
around to prepare for adding bigjoiner related mode validation
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_dp.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
From: Maarten Lankhorst
With bigjoiner, there will be 2 pipes driving 2 halfs of 1 transcoder,
because of this, we need a pipe_mode for various calculations, including
for example watermarks, plane clipping, etc.
v6:
* renaming in separate function, only pipe_mode here (Ville)
* Add description
From: Maarten Lankhorst
Make sure that when a plane is set in a bigjoiner mode, we will add
their counterpart to the atomic state as well. This will allow us to
make sure all state is available when planes are checked.
Because of the funny interactions with bigjoiner and planar YUV
formats,
No functional changes here. Just pass intel_atomic_state
along with crtc_state to certain atomic_check functions.
This will lay the foundation for adding bigjoiner master/slave
states in atomic check.
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
Make vdsc work when no output is enabled. The big joiner needs VDSC
on the slave, so enable it and set the appropriate bits.
So remove encoder usage from dsc functions.
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
From: Maarten Lankhorst
Small changes to intel_dp_mode_valid(), allow listing modes that
can only be supported in the bigjoiner configuration, which is
not supported yet.
eDP does not support bigjoiner, so do not expose bigjoiner only
modes on the eDP port.
v9:
* Restric Bigjoiner on PORT A
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Use the local HWSP offset
during submission
URL : https://patchwork.freedesktop.org/series/82935/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9179_full -> Patchwork_18760_full
On Wed, Oct. 21, 2020, 5:13 p.m, Souza, Jose wrote:
>On Wed, 2020-10-21 at 22:24 +0800, Lee Shawn C wrote:
>> Driver should refer to commit 'b2fc2252ce41 ("drm/i915/psr:
>> Always wait for idle state when disabling PSR")' to wait for idle
>> state when turn PSR off. But it did not follow
Hi,
With linux-next 20201021, when booting up, I am seeing this:
[0.560896] UBSAN: signed-integer-overflow in
../drivers/gpu/drm/drm_modes.c:765:20
[0.560903] 2376000 * 1000 cannot be represented in type 'int'
[0.560909] CPU: 3 PID: 7 Comm: kworker/u16:0 Not tainted
5.9.0-next
Hi Chris,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip linus/master v5.9 next-20201021]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch
== Series Details ==
Series: drm/i915/guc: skip disabling CTBs before sanitizing the GuC
URL : https://patchwork.freedesktop.org/series/82934/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9178_full -> Patchwork_18759_full
== Series Details ==
Series: drm/i915/display: Unkerneldoc cnl_program_nearest_filter_coefs
URL : https://patchwork.freedesktop.org/series/82933/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9178_full -> Patchwork_18758_full
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Use the local HWSP offset
during submission
URL : https://patchwork.freedesktop.org/series/82935/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9179 -> Patchwork_18760
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Use the local HWSP offset
during submission
URL : https://patchwork.freedesktop.org/series/82935/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Use the local HWSP offset
during submission
URL : https://patchwork.freedesktop.org/series/82935/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c352f2f98f6d drm/i915/gt: Use the local HWSP offset during
We wrap the timeline on construction of the next request, but there may
still be requests in flight that have not yet finalized the breadcrumb.
(The breadcrumb is delayed as we need engine-local offsets, and for the
virtual engine that is not known until execution.) As such, by the time
we write
intel_timeline_read_hwsp() is used to support semaphore waits between
engines, that may themselves be deferred for arbitrary periods -- that
is the read of the target request's HWSP is at an indeterminant point in
the future. To support this, we need to prevent overwriting a HWSP that
is being
On Tue, Oct 20, 2020 at 8:54 PM Almahallawy, Khaled
wrote:
>
> On Wed, 2020-10-21 at 00:29 +, Souza, Jose wrote:
> > On Tue, 2020-10-20 at 16:25 -0700, José Roberto de Souza wrote:
> > > On Tue, 2020-10-20 at 15:41 +0300, Ville Syrjälä wrote:
> > > > On Tue, Oct 20, 2020 at 12:45:55AM -0700,
On Wed, 2020-10-21 at 16:26 +0300, Ville Syrjälä wrote:
> On Tue, Oct 20, 2020 at 11:25:53PM +, Souza, Jose wrote:
> > On Tue, 2020-10-20 at 15:41 +0300, Ville Syrjälä wrote:
> > > On Tue, Oct 20, 2020 at 12:45:55AM -0700, Khaled Almahallawy wrote:
> > > > This patch avoids failing
On Wed, Oct 21, 2020 at 01:20:28AM -0700, Lucas De Marchi wrote:
These are the remaining patches from
https://patchwork.freedesktop.org/series/82594/
Main change here is how we enable hpd interrupt handling since that
changed on recent refactors for other platforms. This commit is
currently not
On Wed, Oct 21, 2020 at 01:43:42PM -0700, Matt Roper wrote:
On Wed, Oct 21, 2020 at 06:31:57AM -0700, Aditya Swarup wrote:
From: Caz Yokoyama
ADL_S re-uses the same stolen memory registers as TGL and ICL.
Bspec: 52055
Bspec: 49589
Bspec: 49636
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Cc:
Quoting Chris Wilson (2020-10-21 18:36:00)
> Quoting Ville Syrjala (2020-10-21 14:14:40)
> > From: Ville Syrjälä
> >
> > There is no GEN6_RPSTAT1 on ILK. Instead of reading that let's
> > try to get the same information from MEMSTAT_ILK. At least it
> > seems to track MEMSWCTL frequency request
On Wed, Oct 21, 2020 at 06:31:57AM -0700, Aditya Swarup wrote:
> From: Caz Yokoyama
>
> ADL_S re-uses the same stolen memory registers as TGL and ICL.
>
> Bspec: 52055
> Bspec: 49589
> Bspec: 49636
>
> Cc: Lucas De Marchi
> Cc: Anusha Srivatsa
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Cc:
== Series Details ==
Series: drm/i915/guc: skip disabling CTBs before sanitizing the GuC
URL : https://patchwork.freedesktop.org/series/82934/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9178 -> Patchwork_18759
Summary
== Series Details ==
Series: drm/i915/display: Unkerneldoc cnl_program_nearest_filter_coefs
URL : https://patchwork.freedesktop.org/series/82933/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9178 -> Patchwork_18758
== Series Details ==
Series: drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
URL : https://patchwork.freedesktop.org/series/82931/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9178 -> Patchwork_18757
On Wed, Oct 21, 2020 at 07:56:49PM +0100, Chris Wilson wrote:
> The block comment for cnl_program_nearest_filter_coefs() has a wonderful
> diagram, but although it is marked up as kerneldoc does not use the
> markup for providing the function definition.
>
>
== Series Details ==
Series: drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
URL : https://patchwork.freedesktop.org/series/82931/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3060c8151734 drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
If we're about to sanitize the GuC, something might have gone wrong
beforehand, so we should avoid trying to talk to it. Even if GuC is
still running fine, the sanitize will reset its internal state and clear
the CTB registration, so there is still no need to explicitly do so.
References:
== Series Details ==
Series: drm/i915: dump power domain info on mismatches for all devices
URL : https://patchwork.freedesktop.org/series/82924/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9176_full -> Patchwork_18755_full
The block comment for cnl_program_nearest_filter_coefs() has a wonderful
diagram, but although it is marked up as kerneldoc does not use the
markup for providing the function definition.
drivers/gpu/drm/i915/display/intel_display.c:6341: warning: Function parameter
or member 'dev_priv' not
From: Maarten Lankhorst
With bigjoiner, there will be 2 pipes driving 2 halfs of 1 transcoder,
because of this, we need a pipe_mode for various calculations, including
for example watermarks, plane clipping, etc.
v6:
* renaming in separate function, only pipe_mode here (Ville)
* Add description
== Series Details ==
Series: drm/i915: wait PSR state back to idle when turn PSR off
URL : https://patchwork.freedesktop.org/series/82920/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9176_full -> Patchwork_18754_full
Chris Wilson writes:
> In order to test how fast the heartbeat can respond, we measure with the
> interval set to its minimum. Before we measure though, we want to be
> sure we start with a fresh pulse, and so wait until any old one is
> complete. During that wait though, we were continually
Quoting Ville Syrjala (2020-10-21 14:14:43)
> From: Ville Syrjälä
>
> Let's unmask the PCU event irq _after_ we've set up the
> hardware and software to deal with the fallout. We can
> also drop the PCU event bit from DEIER except when we
> need it for rps.
>
> And on the disable side we
Quoting Ville Syrjala (2020-10-21 14:14:42)
> From: Ville Syrjälä
>
> Let's make sure the lower level interrupt bits are all lined
> up before we flip on the master interrupt.
That does seem sensible, yes.
From a quick scan, ilk_irq_postinstall does seem the odd one out.
Reviewed-by: Chris
== Series Details ==
Series: series starting with [1/3] drm/atomic-helpers: remove
legacy_cursor_update hacks
URL : https://patchwork.freedesktop.org/series/82926/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9177 -> Patchwork_18756
Quoting Ville Syrjala (2020-10-21 14:14:41)
> From: Ville Syrjälä
>
> A bunch of the ips calculations require 64bit math. In particular
> 'corr' and 'corr2' look like they can overflow on 32bit systems.
> Switch to explicit u64 for those.
>
> Signed-off-by: Ville Syrjälä
> ---
>
Quoting Ville Syrjala (2020-10-21 14:14:40)
> From: Ville Syrjälä
>
> There is no GEN6_RPSTAT1 on ILK. Instead of reading that let's
> try to get the same information from MEMSTAT_ILK. At least it
> seems to track MEMSWCTL frequency request perfectly on my ILK.
> It needs the same invert trick
On 21.10.2020 15:36, Jason Andryuk wrote:
> On Wed, Oct 21, 2020 at 8:53 AM Jan Beulich wrote:
>>
>> On 21.10.2020 14:45, Jason Andryuk wrote:
>>> On Wed, Oct 21, 2020 at 5:58 AM Roger Pau Monné
>>> wrote:
Hm, it's hard to tell what's going on. My limited experience with
IOMMU faults
On 21.10.2020 14:45, Jason Andryuk wrote:
> On Wed, Oct 21, 2020 at 5:58 AM Roger Pau Monné wrote:
>> Hm, it's hard to tell what's going on. My limited experience with
>> IOMMU faults on broken systems there's a small range that initially
>> triggers those, and then the device goes wonky and
On Wed, Oct 21, 2020 at 06:31:59AM -0700, Aditya Swarup wrote:
From: Anusha Srivatsa
ADLS follows ICP/TGP like interrupts. Reuse hpd_icp and introduce
ADLS DDI and HPD masks for setting up hpd interrupts.
Cc: Lucas De Marchi
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt Roper
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/pmu: Handle PCI unbind
URL : https://patchwork.freedesktop.org/series/82918/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9176_full -> Patchwork_18753_full
Quoting Matthew Auld (2020-10-21 11:36:06)
> We are incorrectly limiting the max allocation size as per the mm
> max_order, which is effectively the largest power-of-two that we can fit
> in the region size. However, it's normal to setup the region or
> allocator with a non-power-of-two size(for
== Series Details ==
Series: series starting with [1/3] drm/atomic-helpers: remove
legacy_cursor_update hacks
URL : https://patchwork.freedesktop.org/series/82926/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
84380fbd2ded drm/atomic-helpers: remove legacy_cursor_update hacks
On Wed, 2020-10-21 at 22:24 +0800, Lee Shawn C wrote:
> Driver should refer to commit 'b2fc2252ce41 ("drm/i915/psr:
> Always wait for idle state when disabling PSR")' to wait for
> idle state when turn PSR off. But it did not follow
> previous method. Driver just call intel_psr_exit() in
>
== Series Details ==
Series: Introduce Alderlake-S
URL : https://patchwork.freedesktop.org/series/82917/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9176_full -> Patchwork_18752_full
Summary
---
**FAILURE**
It's the horror and shouldn't be used. Realized we're not clear on
this in a discussion with Rob about what msm is doing to better
support async commits.
v2: Refine existing todo item to include this (Thomas)
Cc: Sean Paul
Cc: Rob Clark
Signed-off-by: Daniel Vetter
Cc: Maarten Lankhorst
Cc:
With the removal of helper support it doesn't do anything anymore.
Also, we already have async plane update code in vc4.
Signed-off-by: Daniel Vetter
Cc: Eric Anholt
Cc: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_kms.c | 6 --
1 file changed, 6 deletions(-)
diff --git
The stuff never really worked, and leads to lots of fun because it
out-of-order frees atomic states. Which upsets KASAN, among other
things.
For async updates we now have a more solid solution with the
->atomic_async_check and ->atomic_async_commit hooks. Support for that
for msm and vc4 landed.
>
> On Tue, 20 Oct 2020, Anshuman Gupta wrote:
> > Fix the size of WIRED_REPEATER_AUTH_STREAM_REQ cmd buffer size.
> > It is based upon the actual number of MST streams and size of
> > wired_cmd_repeater_auth_stream_req_in.
> > Excluding the size of hdcp_cmd_header.
> >
> > Cc: Tomas Winkler
== Series Details ==
Series: drm/i915: dump power domain info on mismatches for all devices
URL : https://patchwork.freedesktop.org/series/82924/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9176 -> Patchwork_18755
== Series Details ==
Series: series starting with [1/5] drm/i915: Restore ILK-M RPS support
URL : https://patchwork.freedesktop.org/series/82916/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9176_full -> Patchwork_18751_full
== Series Details ==
Series: drm/i915: wait PSR state back to idle when turn PSR off
URL : https://patchwork.freedesktop.org/series/82920/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9176 -> Patchwork_18754
Summary
It's an unlikely scenario to have refcount mismatch issues in multiple
devices at once, but a) don't let problems with one device mask the
problems with another, and b) remove the bad example of static data
usage when the data should be per-device.
Signed-off-by: Jani Nikula
---
== Series Details ==
Series: drm/i915: wait PSR state back to idle when turn PSR off
URL : https://patchwork.freedesktop.org/series/82920/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
57f806dd4a6e drm/i915: wait PSR state back to idle when turn PSR off
-:101: CHECK:BRACES:
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/pmu: Handle PCI unbind
URL : https://patchwork.freedesktop.org/series/82918/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9176 -> Patchwork_18753
Summary
On Wed, Oct 21, 2020 at 12:33:05PM +0200, Jan Beulich wrote:
> On 21.10.2020 11:58, Roger Pau Monné wrote:
> > On Fri, Oct 16, 2020 at 12:23:22PM -0400, Jason Andryuk wrote:
> >> The RMRRs are:
> >> (XEN) [VT-D]Host address width 39
> >> (XEN) [VT-D]found ACPI_DMAR_DRHD:
> >> (XEN) [VT-D]
== Series Details ==
Series: Introduce Alderlake-S
URL : https://patchwork.freedesktop.org/series/82917/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9176 -> Patchwork_18752
Summary
---
**SUCCESS**
No
On Wed, 21 Oct 2020, Aditya Swarup wrote:
> Add changes to configure port clock registers for ADL-S. Combo phy port
> clocks are configured by DPCLKA_CFGCR0 and DPCLKA_CFGCR1 registers.
>
> The DDI to internal clock mappings in DPCLKA_CFGCR0 register for ADL-S
> translates to
> DDI A -> DDIA
>
Driver should refer to commit 'b2fc2252ce41 ("drm/i915/psr:
Always wait for idle state when disabling PSR")' to wait for
idle state when turn PSR off. But it did not follow
previous method. Driver just call intel_psr_exit() in
intel_psr_invalidate() and psr_force_hw_tracking_exit().
Then leave the
On Wed, 21 Oct 2020, Aditya Swarup wrote:
> From: Anusha Srivatsa
>
> Add support for Alderpoint(ADP) PCH used with Alderlake-S.
>
> Cc: Matt Roper
> Cc: Lucas De Marchi
> Cc: Caz Yokoyama
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Cc: Imre Deak
> Signed-off-by: Anusha Srivatsa
>
== Series Details ==
Series: Introduce Alderlake-S
URL : https://patchwork.freedesktop.org/series/82917/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
== Series Details ==
Series: Introduce Alderlake-S
URL : https://patchwork.freedesktop.org/series/82917/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
37adab61ebad drm/i915/adl_s: Add ADL-S platform info and PCI ids
-:54: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' -
== Series Details ==
Series: series starting with [1/5] drm/i915: Restore ILK-M RPS support
URL : https://patchwork.freedesktop.org/series/82916/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9176 -> Patchwork_18751
On Fri, Oct 16, 2020 at 12:23:22PM -0400, Jason Andryuk wrote:
> On Thu, Oct 15, 2020 at 11:16 AM Jason Andryuk wrote:
> >
> > On Thu, Oct 15, 2020 at 7:31 AM Roger Pau Monné
> > wrote:
> > >
> > > On Wed, Oct 14, 2020 at 08:37:06PM +0100, Andrew Cooper wrote:
> > > > On 14/10/2020 20:28, Jason
From: Tvrtko Ursulin
Since we keep a driver global mask of online CPUs and base the decision
whether PMU needs to be migrated upon it, we need to make sure the
migration is done for all registered PMUs (so GPUs).
To do this we need to track the current CPU for each PMU and base the
decision on
From: Tvrtko Ursulin
Mark the device as closed and keep references to driver data alive to
allow for safe driver unbind with active PMU clients. Perf core does not
otherwise handle this case so we have to do it manually like this.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
On Wed, Oct 21, 2020 at 8:53 AM Jan Beulich wrote:
>
> On 21.10.2020 14:45, Jason Andryuk wrote:
> > On Wed, Oct 21, 2020 at 5:58 AM Roger Pau Monné
> > wrote:
> >> Hm, it's hard to tell what's going on. My limited experience with
> >> IOMMU faults on broken systems there's a small range that
From: Anusha Srivatsa
- Inherit the gen12 workarounds.
- Add placeholders to setup GT WA.
- Extend permanent driver WA Wa_1409767108 to adl-s and
Wa_14010685332 to adl-s.
- Extend permanent driver WA Wa_1606054188 to adl-s
- Add Wa_14011765242 for adl-s A0 stepping.
Cc: Jani Nikula
Cc: Ville
From: Tejas Upadhyay
Just like RKL, the ADL_S platform also has different memory
characteristics from past platforms. Update the values used
by our memory bandwidth calculations accordingly.
Bspec: 64631
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
From: Matt Roper
ADL-S has instances of the PHY_MISC register on the first three PHYs,
but only expects the "DE to IO Comp Pwr Down" bit (the only bit we touch
on non-EHL platforms) to be programmed for PHY A.
Bspec: 50107
Cc: Lucas De Marchi
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
From: Matt Roper
ADL-S switches up which PHYs are considered a master to other PHYs;
PHY-C is no longer a master, but PHY-D is now.
Bspec: 49291
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Signed-off-by: Aditya Swarup
---
From: "Yokoyama, Caz"
The crwebview indicates on ADL-S that some of our MCHBAR
registers have moved from their traditional 0x50XX offsets to
new locations. The meaning and bit layout of the registers
remain same.
Cc: Lucas De Marchi
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt
From: Anusha Srivatsa
Load DMC on ADL_S v2.01. This is the first offcial
release of DMC for ADL_S.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Aditya Swarup
Signed-off-by: Anusha Srivatsa
Signed-off-by: Aditya Swarup
---
drivers/gpu/drm/i915/display/intel_csr.c
From: Matt Roper
ADL-S, like RKL, uses the same internal device ID for the GuC and HuC as
TGL did, making them all firmware-compatible. Let's re-use TGL's
firmware for ADL-S.
Bspec: 50668
Cc: John Harrison
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Signed-off-by: Aditya Swarup
---
From: José Roberto de Souza
- As RKL and ADL-S only have 5 planes, primary and 4 sprites and
the cursor plane, let's group the handling together under
HAS_D12_PLANE_MINIMIZATION.
- Also use macro to select pipe irq fault error mask.
BSpec: 49251
Cc: Lucas De Marchi
Cc: Jani Nikula
Cc:
Initialize display outputs and add HTI support for ADL-S. ADL-S has 5
display outputs -> 1 eDP, 2 HDMI and 2 DP++ outputs.
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt Roper
Cc: Lucas De Marchi
Signed-off-by: Aditya Swarup
---
drivers/gpu/drm/i915/display/intel_display.c | 8
- ADL-S driver internal mapping uses PORT D, E, F, G for Combo phy B, C, D and
E.
- Add ADLS specific port mappings for vbt port dvo settings.
- Select appropriate AUX CH specific to ADLS based on port mapping.
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt Roper
Cc: Lucas De
Add changes to configure port clock registers for ADL-S. Combo phy port
clocks are configured by DPCLKA_CFGCR0 and DPCLKA_CFGCR1 registers.
The DDI to internal clock mappings in DPCLKA_CFGCR0 register for ADL-S
translates to
DDI A -> DDIA
DDI B -> USBC1
DDI I -> USBC2
For DPCLKA_CFGCR1
DDI J ->
From: Caz Yokoyama
ADL_S re-uses the same stolen memory registers as TGL and ICL.
Bspec: 52055
Bspec: 49589
Bspec: 49636
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Signed-off-by: Caz Yokoyama
Signed-off-by: Aditya Swarup
---
Add changes for configuring DPLL for ADL-S
- Reusing DG1 DPLL 2 & DPLL 3 for ADL-S
- Extend CNL macro to choose DPLL_ENABLE
for ADL-S.
- Select CFGCR0 and CFGCR1 for ADL-S plls.
On BSpec: 53720 PLL arrangement dig for adls:
DPLL2 cfgcr is programmed using _ADLS_DPLL3_CFGCR(0/1)
DPLL3 cfgcr is
ADL-S requires TC pins to set up ddc for Combo PHY B, C, D and E.
Combo PHY A still uses the old ddc pin mapping.
From VBT, ddc pin info suggests the following mapping:
VBTDRIVER
DDI B->ddc_pin=2 should translate to PORT_D->0x9
DDI C->ddc_pin=3 should translate
From: Caz Yokoyama
- Add the initial platform information for Alderlake-S.
- Specify ppgtt_size value
- Add dma_mask_size
- Add ADLS REVIDs
- HW tracking(Selective Update Tracking Enable) has been removed from
ADLS. Disable PSR2 till we enable software/manual tracking.
Bspec: 53597
Bspec:
From: Anusha Srivatsa
Alderlake-S has 5 combo phys, add reg definitions for
combo phys and update the port to phy helper for ADL-S.
Cc: Lucas De Marchi
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Signed-off-by: Aditya Swarup
---
From: Anusha Srivatsa
Add support for Alderpoint(ADP) PCH used with Alderlake-S.
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Caz Yokoyama
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Signed-off-by: Anusha Srivatsa
Signed-off-by: Aditya Swarup
---
drivers/gpu/drm/i915/intel_pch.c | 8
From: Anusha Srivatsa
ADLS follows ICP/TGP like interrupts. Reuse hpd_icp and introduce
ADLS DDI and HPD masks for setting up hpd interrupts.
Cc: Lucas De Marchi
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt Roper
Cc: José Roberto de Souza
Signed-off-by: Anusha Srivatsa
Alder Lake-S (ADL-S) is another gen12 platform and a TGL variant, with
5 combo phy outputs with the following port/phy assignment:
DDI-A (port A) <-> PHY-A
DDI-TC1 (port D) <-> PHY-B
DDI-TC2 (port E) <-> PHY-C
DDI-TC3 (port F) <-> PHY-D
DDI-TC4 (port G)
On Tue, Oct 20, 2020 at 11:25:53PM +, Souza, Jose wrote:
> On Tue, 2020-10-20 at 15:41 +0300, Ville Syrjälä wrote:
> > On Tue, Oct 20, 2020 at 12:45:55AM -0700, Khaled Almahallawy wrote:
> > > This patch avoids failing atomic commits sent by user space by making
> > > sure CRTC/Connector
Quoting Ville Syrjala (2020-10-21 14:14:39)
> From: Ville Syrjälä
>
> Restore RPS for ILK-M. We lost it when an extra HAS_RPS()
> check appeared in intel_rps_enable().
>
> Unfortunaltey this just makes the performance worse on my
> ILK because intel_ips insists on limiting the GPU freq to
> the
On Tue, Oct 20, 2020 at 10:12:27PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2020-10-20 20:43:30)
> > From: Ville Syrjälä
> >
> > Do the fb size readout correctly for the 90/270 degree rotated
> > cases. Not sure if we're missing something else as well.
> >
> > Also no idea whether
From: Ville Syrjälä
Restore RPS for ILK-M. We lost it when an extra HAS_RPS()
check appeared in intel_rps_enable().
Unfortunaltey this just makes the performance worse on my
ILK because intel_ips insists on limiting the GPU freq to
the minimum. If we don't do the RPS init then intel_ips will
From: Ville Syrjälä
Let's make sure the lower level interrupt bits are all lined
up before we flip on the master interrupt.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c
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