Re: [Intel-gfx] [PATCH v5] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9
Hi Rong, Please help to trigger 3D performance test on several Gen9 CI test boxes which different fusing sku with/without “patch v5”, and share the results. Thanks, Best Regards, Cooper ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9
Hi Rong, Please help to trigger 3D performance test on several Gen9 CI test boxes which different fusing sku with/without “patch v5”. Thanks, Best Regards, Cooper > On Mar 6, 2021, at 12:01 AM, Tvrtko Ursulin > wrote: > > >> On 05/03/2021 15:24, Chiou, Cooper wrote: >> After switched to ffs from fls in "patch >> v5"(https://patchwork.freedesktop.org/series/81764/#rev7), now CI result is >> PASS no regression in wa_verify warning. >> @Chen, Rong >> Could you please run >> “phoronix-test-suite.supertuxkart.1024x768.Fullscreen.Ultimate.1.GranParadisoIsland.frames_per_second” >> with this latest patch v5 on test box to see if any performance impact. > > We need testing on more that one box I'm afraid. Need to cover different > fusing configs of Gen9 with and without the patch. I don't have any useful > ideas on how to do it though. :( > > Regards, > > Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for i915/perf: Start hrtimer only if sampling the OA buffer (rev2)
== Series Details == Series: i915/perf: Start hrtimer only if sampling the OA buffer (rev2) URL : https://patchwork.freedesktop.org/series/87524/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9836_full -> Patchwork_19764_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19764_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19764_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19764_full: ### IGT changes ### Possible regressions * igt@kms_flip@flip-vs-suspend@c-edp1: - shard-iclb: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-iclb7/igt@kms_flip@flip-vs-susp...@c-edp1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/shard-iclb1/igt@kms_flip@flip-vs-susp...@c-edp1.html Known issues Here are the changes found in Patchwork_19764_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@display-4x: - shard-iclb: NOTRUN -> [SKIP][3] ([i915#1839]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/shard-iclb3/igt@feature_discov...@display-4x.html * igt@gem_create@create-massive: - shard-kbl: NOTRUN -> [DMESG-WARN][4] ([i915#3002]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/shard-kbl4/igt@gem_cre...@create-massive.html * igt@gem_ctx_persistence@engines-mixed: - shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/shard-snb7/igt@gem_ctx_persiste...@engines-mixed.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: [PASS][6] -> [FAIL][7] ([i915#2842]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-kbl4/igt@gem_exec_fair@basic-none-s...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/shard-kbl7/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2842]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-tglb2/igt@gem_exec_fair@basic-p...@bcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/shard-tglb7/igt@gem_exec_fair@basic-p...@bcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][10] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/shard-glk3/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-snb: NOTRUN -> [FAIL][13] ([i915#2389]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/shard-snb6/igt@gem_exec_reloc@basic-many-act...@rcs0.html * igt@gem_exec_reloc@basic-wide-active@bcs0: - shard-apl: NOTRUN -> [FAIL][14] ([i915#2389]) +3 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/shard-apl8/igt@gem_exec_reloc@basic-wide-act...@bcs0.html * igt@gem_exec_schedule@u-fairslice@rcs0: - shard-tglb: [PASS][15] -> [DMESG-WARN][16] ([i915#2803]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-tglb3/igt@gem_exec_schedule@u-fairsl...@rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/shard-tglb6/igt@gem_exec_schedule@u-fairsl...@rcs0.html * igt@gem_exec_whisper@basic-forked-all: - shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#118] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-glk7/igt@gem_exec_whis...@basic-forked-all.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/shard-glk3/igt@gem_exec_whis...@basic-forked-all.html * igt@gem_huc_copy@huc-copy: - shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#2190]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/shard-kbl4/igt@gem_huc_c...@huc-copy.html * igt@gem_pread@exhaustion: - shard-snb: NOTRUN -> [WARN][20] ([i915#2658]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/shard-snb7/igt@gem_pr...@exhaustion.html *
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/3] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct
== Series Details == Series: series starting with [v2,1/3] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct URL : https://patchwork.freedesktop.org/series/87717/ State : success == Summary == CI Bug Log - changes from CI_DRM_9836_full -> Patchwork_19763_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19763_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@display-4x: - shard-iclb: NOTRUN -> [SKIP][1] ([i915#1839]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/shard-iclb6/igt@feature_discov...@display-4x.html * igt@gem_create@create-massive: - shard-snb: NOTRUN -> [DMESG-WARN][2] ([i915#3002]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/shard-snb5/igt@gem_cre...@create-massive.html - shard-kbl: NOTRUN -> [DMESG-WARN][3] ([i915#3002]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/shard-kbl4/igt@gem_cre...@create-massive.html * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-kbl: [PASS][4] -> [INCOMPLETE][5] ([i915#794]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-kbl7/igt@gem_ctx_isolation@preservation...@rcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/shard-kbl3/igt@gem_ctx_isolation@preservation...@rcs0.html * igt@gem_ctx_persistence@engines-mixed: - shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/shard-snb6/igt@gem_ctx_persiste...@engines-mixed.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-tglb3/igt@gem_exec_fair@basic-f...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/shard-tglb5/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-kbl: [PASS][9] -> [SKIP][10] ([fdo#109271]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-kbl1/igt@gem_exec_fair@basic-p...@vcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/shard-kbl4/igt@gem_exec_fair@basic-p...@vcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/shard-glk2/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_reloc@basic-wide-active@bcs0: - shard-apl: NOTRUN -> [FAIL][13] ([i915#2389]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/shard-apl6/igt@gem_exec_reloc@basic-wide-act...@bcs0.html * igt@gem_exec_schedule@u-fairslice@rcs0: - shard-skl: NOTRUN -> [DMESG-WARN][14] ([i915#1610] / [i915#2803]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/shard-skl7/igt@gem_exec_schedule@u-fairsl...@rcs0.html * igt@gem_exec_schedule@u-fairslice@vecs0: - shard-iclb: [PASS][15] -> [DMESG-WARN][16] ([i915#2803]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-iclb8/igt@gem_exec_schedule@u-fairsl...@vecs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/shard-iclb2/igt@gem_exec_schedule@u-fairsl...@vecs0.html * igt@gem_exec_suspend@basic-s3: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-apl1/igt@gem_exec_susp...@basic-s3.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/shard-apl2/igt@gem_exec_susp...@basic-s3.html * igt@gem_exec_whisper@basic-normal: - shard-glk: [PASS][19] -> [DMESG-WARN][20] ([i915#118] / [i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-glk9/igt@gem_exec_whis...@basic-normal.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/shard-glk1/igt@gem_exec_whis...@basic-normal.html * igt@gem_huc_copy@huc-copy: - shard-kbl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#2190]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/shard-kbl4/igt@gem_huc_c...@huc-copy.html * igt@gem_mmap_gtt@cpuset-big-copy-odd: - shard-iclb: [PASS][22] -> [FAIL][23] ([i915#307]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-iclb3/igt@gem_mmap_...@cpuset-big-copy-odd.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/shard-iclb8/igt@gem_mmap_...@cpuset-big-copy-odd.html * igt@gem_pread@exhaustion:
Re: [Intel-gfx] [RFC PATCH 8/9] drm/gem: Associate GEM objects with drm cgroup
On 2/11/2021 7:34 AM, Daniel Vetter wrote: > On Wed, Feb 10, 2021 at 02:00:57PM -0800, Brian Welty wrote: >> >> On 2/9/2021 2:54 AM, Daniel Vetter wrote: >>> On Tue, Jan 26, 2021 at 01:46:25PM -0800, Brian Welty wrote: This patch adds tracking of which cgroup to make charges against for a given GEM object. We associate the current task's cgroup with GEM objects as they are created. First user of this is for charging DRM cgroup for device memory allocations. The intended behavior is for device drivers to make the cgroup charging calls at the time that backing store is allocated or deallocated for the object. Exported functions are provided for charging memory allocations for a GEM object to DRM cgroup. To aid in debugging, we store how many bytes have been charged inside the GEM object. Add helpers for setting and clearing the object's associated cgroup which will check that charges are not being leaked. For shared objects, this may make the charge against a cgroup that is potentially not the same cgroup as the process using the memory. Based on the memory cgroup's discussion of "memory ownership", this seems acceptable [1]. [1] https://www.kernel.org/doc/Documentation/cgroup-v2.txt, "Memory Ownership" Signed-off-by: Brian Welty >>> >>> Since for now we only have the generic gpu/xpu/bikeshed.memory bucket that >>> counts everything, why don't we also charge in these gem functions? >> >> I'm not sure what you mean exactly. You want to merge/move the charging >> logic >> proposed in patch #5 (drm_cgroup_try_charge in kernel/cgroup/drm.c) into >> drm_gem_object_charge_mem() ? >> >> Or reading below, I think you are okay keeping the logic separated as is, but >> you want much of the code in kernel/cgroup/drm.c moved to drivers/gpu/cgroup >> ? >> Yes, I see that should allow to reduce number of exported functions. > > Both. I mean we'd need to look at the code again when it's shuffled, but > I'd say: > > - cgroup code and the charging for general gpu memory moves to > drivers/gpu/cgroup, so dma-buf heaps can use it too. > > - the charging for gem buffers moves into core gem code, so it happens for > all gpu drivers and all gem buffer allocations. Daniel, I'm not sure we're in sync on what 'charging for general gpu memory' means. Thus far, I have been proposing to charge/uncharge when backing store is allocated/freed. And thus, this would be done in DRM driver (so then also in the dma-buf exporter). I can't see how we'd hoist this part into drm gem code. The memory limit in this series is for VRAM usage/limit not GEM buffers... Unless you are talking about charging for GEM buffer creation? But this is more of a 'soft resource' more along lines of Kenny's earlier GEM buffer limit control. I raised issue with this then, and at the time, Tejun agreed we should keep to 'hard resource' controls, see [1] and [2]. [1] https://lists.freedesktop.org/archives/dri-devel/2019-May/218071.html [2] https://lists.freedesktop.org/archives/dri-devel/2020-April/262141.html > > - this might or might not mean a bunch less exported stuff from the > cgroups files (since you don't need separate steps for linking a gem > object to a cgroup from the actual charging), and probably no exports > anymore for drivers (since they charge nothing). That will change > when we add charging for specific memory pools I guess, but we add that > when we add tha functionality. ... so considering VRAM charging, then yes, we very much need to have exported functions for drivers to do the charging. But these can be exported from drm.ko (or new .ko?) instead of kernel. Is that still preference? Also, if number of exported functions is concern, we can replace some of it with use of function pointers. So then returning to this comment of yours: > - cgroup code and the charging for general gpu memory moves to > drivers/gpu/cgroup, so dma-buf heaps can use it too. If you agree that we are charging just at backing-store level, then I think logic belongs in drivers/gpu/drm/cgroup ?? As charging is done in DRM driver (also dma-buf exporter). In other words, part of drm. If I understand, dma-buf heaps is exporter of system memory and doesn't need to charge against gpu controller?? Will need some help to understand the dma-buf heap use case a bit more. Thanks, -Brian > >>> Also, that would remove the need for all these functions exported to >>> drivers. Plus the cgroups setup could also move fully into drm core code, >>> since all drivers (*) support it >>> That way this would really be a fully >>> generic cgroups controller, and we could land it. >> >> >> Patch #2 proposed to have a few setup functions called during drm device >> registration. >> You are suggesting to have this more tightly integrated? > > Yeah essentially if DRIVER_GEM is set drm core would simply set this all > up. Since with this we'd
[Intel-gfx] ✗ Fi.CI.IGT: failure for i915/query: Correlate engine and cpu timestamps with better accuracy (rev3)
== Series Details == Series: i915/query: Correlate engine and cpu timestamps with better accuracy (rev3) URL : https://patchwork.freedesktop.org/series/87552/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9836_full -> Patchwork_19762_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19762_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19762_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19762_full: ### IGT changes ### Possible regressions * igt@kms_atomic_transition@plane-all-transition-nonblocking-fencing@dp-1-pipe-b: - shard-kbl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-kbl3/igt@kms_atomic_transition@plane-all-transition-nonblocking-fenc...@dp-1-pipe-b.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19762/shard-kbl4/igt@kms_atomic_transition@plane-all-transition-nonblocking-fenc...@dp-1-pipe-b.html Known issues Here are the changes found in Patchwork_19762_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@display-4x: - shard-iclb: NOTRUN -> [SKIP][3] ([i915#1839]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19762/shard-iclb5/igt@feature_discov...@display-4x.html * igt@gem_create@create-massive: - shard-snb: NOTRUN -> [DMESG-WARN][4] ([i915#3002]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19762/shard-snb6/igt@gem_cre...@create-massive.html - shard-kbl: NOTRUN -> [DMESG-WARN][5] ([i915#3002]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19762/shard-kbl6/igt@gem_cre...@create-massive.html * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-kbl: [PASS][6] -> [INCOMPLETE][7] ([i915#794]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-kbl7/igt@gem_ctx_isolation@preservation...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19762/shard-kbl3/igt@gem_ctx_isolation@preservation...@rcs0.html * igt@gem_ctx_persistence@engines-mixed: - shard-snb: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1099]) +5 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19762/shard-snb5/igt@gem_ctx_persiste...@engines-mixed.html * igt@gem_ctx_ringsize@plugged@vecs0: - shard-skl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-skl9/igt@gem_ctx_ringsize@plug...@vecs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19762/shard-skl9/igt@gem_ctx_ringsize@plug...@vecs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-kbl4/igt@gem_exec_fair@basic-none-s...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19762/shard-kbl3/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-tglb2/igt@gem_exec_fair@basic-p...@bcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19762/shard-tglb7/igt@gem_exec_fair@basic-p...@bcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-glk: [PASS][15] -> [FAIL][16] ([i915#2842]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-glk3/igt@gem_exec_fair@basic-p...@vecs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19762/shard-glk9/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-snb: NOTRUN -> [FAIL][17] ([i915#2389]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19762/shard-snb2/igt@gem_exec_reloc@basic-many-act...@rcs0.html * igt@gem_exec_schedule@u-fairslice@rcs0: - shard-tglb: [PASS][18] -> [DMESG-WARN][19] ([i915#2803]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-tglb3/igt@gem_exec_schedule@u-fairsl...@rcs0.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19762/shard-tglb1/igt@gem_exec_schedule@u-fairsl...@rcs0.html * igt@gem_exec_schedule@u-fairslice@vcs0: - shard-skl: NOTRUN -> [DMESG-WARN][20] ([i915#1610] / [i915#2803]) [20]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for Revert "drm/i915: Propagate errors on awaiting already signaled fences"
== Series Details == Series: Revert "drm/i915: Propagate errors on awaiting already signaled fences" URL : https://patchwork.freedesktop.org/series/87704/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9836_full -> Patchwork_19761_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19761_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19761_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19761_full: ### IGT changes ### Possible regressions * igt@gen9_exec_parse@basic-rejected: - shard-skl: NOTRUN -> [FAIL][1] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/shard-skl1/igt@gen9_exec_pa...@basic-rejected.html * igt@gen9_exec_parse@batch-without-end: - shard-apl: [PASS][2] -> [FAIL][3] +3 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-apl1/igt@gen9_exec_pa...@batch-without-end.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/shard-apl1/igt@gen9_exec_pa...@batch-without-end.html * igt@gen9_exec_parse@batch-zero-length: - shard-kbl: [PASS][4] -> [FAIL][5] +6 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-kbl3/igt@gen9_exec_pa...@batch-zero-length.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/shard-kbl2/igt@gen9_exec_pa...@batch-zero-length.html - shard-glk: [PASS][6] -> [INCOMPLETE][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-glk9/igt@gen9_exec_pa...@batch-zero-length.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/shard-glk2/igt@gen9_exec_pa...@batch-zero-length.html * igt@gen9_exec_parse@bb-chained: - shard-glk: [PASS][8] -> [FAIL][9] +7 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-glk2/igt@gen9_exec_pa...@bb-chained.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/shard-glk9/igt@gen9_exec_pa...@bb-chained.html * igt@gen9_exec_parse@bb-start-out: - shard-apl: NOTRUN -> [FAIL][10] +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/shard-apl1/igt@gen9_exec_pa...@bb-start-out.html * igt@gen9_exec_parse@bb-start-param: - shard-skl: [PASS][11] -> [TIMEOUT][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-skl1/igt@gen9_exec_pa...@bb-start-param.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/shard-skl9/igt@gen9_exec_pa...@bb-start-param.html - shard-kbl: [PASS][13] -> [TIMEOUT][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-kbl6/igt@gen9_exec_pa...@bb-start-param.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/shard-kbl7/igt@gen9_exec_pa...@bb-start-param.html - shard-glk: [PASS][15] -> [TIMEOUT][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-glk5/igt@gen9_exec_pa...@bb-start-param.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/shard-glk6/igt@gen9_exec_pa...@bb-start-param.html - shard-apl: [PASS][17] -> [TIMEOUT][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-apl7/igt@gen9_exec_pa...@bb-start-param.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/shard-apl8/igt@gen9_exec_pa...@bb-start-param.html * igt@gen9_exec_parse@valid-registers: - shard-skl: [PASS][19] -> [FAIL][20] +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-skl6/igt@gen9_exec_pa...@valid-registers.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/shard-skl7/igt@gen9_exec_pa...@valid-registers.html * igt@i915_selftest@live@client: - shard-skl: [PASS][21] -> [DMESG-FAIL][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-skl9/igt@i915_selftest@l...@client.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/shard-skl2/igt@i915_selftest@l...@client.html * igt@kms_atomic_transition@plane-all-transition-nonblocking@edp-1-pipe-b: - shard-iclb: [PASS][23] -> [FAIL][24] +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-iclb7/igt@kms_atomic_transition@plane-all-transition-nonblock...@edp-1-pipe-b.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/shard-iclb6/igt@kms_atomic_transition@plane-all-transition-nonblock...@edp-1-pipe-b.html Known issues Here are the changes found in Patchwork_19761_full
[Intel-gfx] ✓ Fi.CI.BAT: success for i915/perf: Start hrtimer only if sampling the OA buffer (rev2)
== Series Details ==
Series: i915/perf: Start hrtimer only if sampling the OA buffer (rev2)
URL : https://patchwork.freedesktop.org/series/87524/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9836 -> Patchwork_19764
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/index.html
Known issues
Here are the changes found in Patchwork_19764 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271]) +23 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_tiled_fence_blits@basic:
- fi-kbl-8809g: [PASS][4] -> [TIMEOUT][5] ([i915#3145])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/fi-kbl-8809g/igt@gem_tiled_fence_bl...@basic.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/fi-kbl-8809g/igt@gem_tiled_fence_bl...@basic.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][6] ([i915#1886] / [i915#2291])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_frontbuffer_tracking@basic:
- fi-kbl-soraka: NOTRUN -> [FAIL][8] ([i915#49])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/fi-kbl-soraka/igt@kms_frontbuffer_track...@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#533])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[INCOMPLETE][10] ([i915#2782]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
Warnings
* igt@gem_tiled_blits@basic:
- fi-kbl-8809g: [TIMEOUT][12] ([i915#3145]) -> [TIMEOUT][13]
([i915#2502] / [i915#3145])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19764/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1222]: https://gitlab.freedesktop.org/drm/intel/issues/1222
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2502]: https://gitlab.freedesktop.org/drm/intel/issues/2502
[i915#2601]: https://gitlab.freedesktop.org/drm/intel/issues/2601
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#3145]: https://gitlab.freedesktop.org/drm/intel/issues/3145
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Participating hosts (43 -> 38)
--
Additional (1): fi-kbl-soraka
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-bsw-cyan fi-icl-y
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9836 -> Patchwork_19764
CI-20190529: 20190529
CI_DRM_9836: 8449e42c5aabce79a2c9f5e75ddd31b9b50e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6024: d8e03fe437f0c328c96717a92ad97719c02ba2cd @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19764: eccbb7788b1cdec359c6e6af94b46803c4a3290d @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
eccbb7788b1c i915/perf: Start hrtimer only if
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/3] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct
== Series Details == Series: series starting with [v2,1/3] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct URL : https://patchwork.freedesktop.org/series/87717/ State : success == Summary == CI Bug Log - changes from CI_DRM_9836 -> Patchwork_19763 Summary --- **WARNING** Minor unknown changes coming with Patchwork_19763 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19763, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19763: ### IGT changes ### Warnings * igt@gem_exec_suspend@basic-s3: - fi-bsw-n3050: [INCOMPLETE][1] ([i915#3159]) -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/fi-bsw-n3050/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/fi-bsw-n3050/igt@gem_exec_susp...@basic-s3.html Known issues Here are the changes found in Patchwork_19763 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271]) +23 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][5] ([i915#1886] / [i915#2291]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_frontbuffer_tracking@basic: - fi-kbl-soraka: NOTRUN -> [FAIL][7] ([i915#49]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/fi-kbl-soraka/igt@kms_frontbuffer_track...@basic.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#533]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@runner@aborted: - fi-byt-j1900: NOTRUN -> [FAIL][9] ([i915#2426] / [i915#2505]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/fi-byt-j1900/igt@run...@aborted.html Possible fixes * igt@gem_tiled_blits@basic: - fi-kbl-8809g: [TIMEOUT][10] ([i915#3145]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19763/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426 [i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505 [i915#3145]: https://gitlab.freedesktop.org/drm/intel/issues/3145 [i915#3159]: https://gitlab.freedesktop.org/drm/intel/issues/3159 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 Participating hosts (43 -> 39) -- Additional (1): fi-kbl-soraka Missing(5): fi-ilk-m540 fi-tgl-dsi fi-hsw-4200u fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_9836 -> Patchwork_19763 CI-20190529: 20190529 CI_DRM_9836: 8449e42c5aabce79a2c9f5e75ddd31b9b50e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6024: d8e03fe437f0c328c96717a92ad97719c02ba2cd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19763: be397574544b1a79a258a7f1615f3597f6d35c08 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == be397574544b drm/i915/display: Introduce new intel_psr_pause/resume function 531d6207a548 drm/i915/display: Remove a redundant function argument from intel_psr_enable_source() a1c366f1d864 drm/i915/display:
[Intel-gfx] [PATCH] i915/perf: Start hrtimer only if sampling the OA buffer
SAMPLE_OA parameter enables sampling of OA buffer and results in a call
to init the OA buffer which initializes the OA unit head/tail pointers.
The OA_EXPONENT parameter controls the periodicity of the OA reports in
the OA buffer and results in starting a hrtimer.
Before gen12, all use cases required the use of the OA buffer and i915
enforced this setting when vetting out the parameters passed. In these
platforms the hrtimer was enabled if OA_EXPONENT was passed. This worked
fine since it was implied that SAMPLE_OA is always passed.
With gen12, this changed. Users can use perf without enabling the OA
buffer as in OAR use cases. While an OAR use case should ideally not
start the hrtimer, we see that passing an OA_EXPONENT parameter will
start the hrtimer even though SAMPLE_OA is not specified. This results
in an uninitialized OA buffer, so the head/tail pointers used to track
the buffer are zero.
This itself does not fail, but if we ran a use-case that SAMPLED the OA
buffer previously, then the OA_TAIL register is still pointing to an old
value. When the timer callback runs, it ends up calculating a
wrong/large number of available reports. Since we do a spinlock_irq_save
and start processing a large number of reports, NMI watchdog fires and
causes a crash.
Start the timer only if SAMPLE_OA is specified.
v2:
- Drop SAMPLE OA check when appending samples (Ashutosh)
- Prevent read if OA buffer is not being sampled
Fixes: 00a7f0d7155c ("drm/i915/tgl: Add perf support on TGL")
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_perf.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index c15bead2dac7..2fd2c13b76ac 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -595,7 +595,6 @@ static int append_oa_sample(struct i915_perf_stream *stream,
{
int report_size = stream->oa_buffer.format_size;
struct drm_i915_perf_record_header header;
- u32 sample_flags = stream->sample_flags;
header.type = DRM_I915_PERF_RECORD_SAMPLE;
header.pad = 0;
@@ -609,10 +608,8 @@ static int append_oa_sample(struct i915_perf_stream
*stream,
return -EFAULT;
buf += sizeof(header);
- if (sample_flags & SAMPLE_OA_REPORT) {
- if (copy_to_user(buf, report, report_size))
- return -EFAULT;
- }
+ if (copy_to_user(buf, report, report_size))
+ return -EFAULT;
(*offset) += header.size;
@@ -2669,7 +2666,7 @@ static void i915_oa_stream_enable(struct i915_perf_stream
*stream)
stream->perf->ops.oa_enable(stream);
- if (stream->periodic)
+ if (stream->sample_flags & SAMPLE_OA_REPORT)
hrtimer_start(>poll_check_timer,
ns_to_ktime(stream->poll_oa_period),
HRTIMER_MODE_REL_PINNED);
@@ -2732,7 +2729,7 @@ static void i915_oa_stream_disable(struct
i915_perf_stream *stream)
{
stream->perf->ops.oa_disable(stream);
- if (stream->periodic)
+ if (stream->sample_flags & SAMPLE_OA_REPORT)
hrtimer_cancel(>poll_check_timer);
}
@@ -3015,7 +3012,7 @@ static ssize_t i915_perf_read(struct file *file,
* disabled stream as an error. In particular it might otherwise lead
* to a deadlock for blocking file descriptors...
*/
- if (!stream->enabled)
+ if (!stream->enabled || !(stream->sample_flags & SAMPLE_OA_REPORT))
return -EIO;
if (!(file->f_flags & O_NONBLOCK)) {
--
2.20.1
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for i915/query: Correlate engine and cpu timestamps with better accuracy (rev3)
== Series Details == Series: i915/query: Correlate engine and cpu timestamps with better accuracy (rev3) URL : https://patchwork.freedesktop.org/series/87552/ State : success == Summary == CI Bug Log - changes from CI_DRM_9836 -> Patchwork_19762 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19762/index.html Known issues Here are the changes found in Patchwork_19762 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +23 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19762/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19762/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_tiled_fence_blits@basic: - fi-kbl-8809g: [PASS][3] -> [TIMEOUT][4] ([i915#3145]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/fi-kbl-8809g/igt@gem_tiled_fence_bl...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19762/fi-kbl-8809g/igt@gem_tiled_fence_bl...@basic.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][5] ([i915#1886] / [i915#2291]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19762/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19762/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_frontbuffer_tracking@basic: - fi-kbl-soraka: NOTRUN -> [FAIL][7] ([i915#49]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19762/fi-kbl-soraka/igt@kms_frontbuffer_track...@basic.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#533]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19762/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html Warnings * igt@i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][9] ([i915#1982] / [i915#3143]) -> [DMESG-WARN][10] ([i915#3143]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/fi-glk-dsi/igt@i915_pm_...@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19762/fi-glk-dsi/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#3143]: https://gitlab.freedesktop.org/drm/intel/issues/3143 [i915#3145]: https://gitlab.freedesktop.org/drm/intel/issues/3145 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 Participating hosts (43 -> 39) -- Additional (1): fi-kbl-soraka Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-icl-y fi-bdw-samus Build changes - * Linux: CI_DRM_9836 -> Patchwork_19762 CI-20190529: 20190529 CI_DRM_9836: 8449e42c5aabce79a2c9f5e75ddd31b9b50e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6024: d8e03fe437f0c328c96717a92ad97719c02ba2cd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19762: 885dfe7b703ec08c3522dbb7253f42af121590dd @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 885dfe7b703e i915/query: Correlate engine and cpu timestamps with better accuracy == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19762/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: More SAGV related fixes/cleanups
== Series Details == Series: drm/i915: More SAGV related fixes/cleanups URL : https://patchwork.freedesktop.org/series/87699/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9836_full -> Patchwork_19760_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19760_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19760_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19760_full: ### IGT changes ### Possible regressions * igt@gem_eio@in-flight-contexts-10ms: - shard-skl: NOTRUN -> [TIMEOUT][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-skl1/igt@gem_...@in-flight-contexts-10ms.html * igt@i915_selftest@live@reset: - shard-skl: [PASS][2] -> [DMESG-FAIL][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-skl9/igt@i915_selftest@l...@reset.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-skl3/igt@i915_selftest@l...@reset.html * igt@kms_atomic_transition@plane-all-transition-nonblocking@edp-1-pipe-b: - shard-iclb: [PASS][4] -> [FAIL][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-iclb7/igt@kms_atomic_transition@plane-all-transition-nonblock...@edp-1-pipe-b.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb5/igt@kms_atomic_transition@plane-all-transition-nonblock...@edp-1-pipe-b.html Known issues Here are the changes found in Patchwork_19760_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@display-4x: - shard-iclb: NOTRUN -> [SKIP][6] ([i915#1839]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-iclb7/igt@feature_discov...@display-4x.html * igt@gem_create@create-massive: - shard-snb: NOTRUN -> [DMESG-WARN][7] ([i915#3002]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-snb5/igt@gem_cre...@create-massive.html * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-kbl: [PASS][8] -> [DMESG-WARN][9] ([i915#180]) +2 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-kbl7/igt@gem_ctx_isolation@preservation...@bcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-kbl1/igt@gem_ctx_isolation@preservation...@bcs0.html * igt@gem_ctx_persistence@engines-mixed: - shard-snb: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#1099]) +4 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-snb7/igt@gem_ctx_persiste...@engines-mixed.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-tglb1/igt@gem_exec_fair@basic-none-sh...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-tglb2/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-kbl4/igt@gem_exec_fair@basic-none-s...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-kbl1/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][15] -> [FAIL][16] ([i915#2842]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-glk1/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_flush@basic-batch-kernel-default-cmd: - shard-snb: NOTRUN -> [SKIP][17] ([fdo#109271]) +294 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-snb7/igt@gem_exec_fl...@basic-batch-kernel-default-cmd.html * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-snb: NOTRUN -> [FAIL][18] ([i915#2389]) +2 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-snb5/igt@gem_exec_reloc@basic-many-act...@rcs0.html * igt@gem_exec_reloc@basic-wide-active@bcs0: - shard-apl: NOTRUN -> [FAIL][19] ([i915#2389]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/shard-apl6/igt@gem_exec_reloc@basic-wide-act...@bcs0.html * igt@gem_exec_schedule@u-fairslice@vecs0: - shard-kbl: NOTRUN -> [DMESG-WARN][20] ([i915#1610] / [i915#2803]) [20]:
[Intel-gfx] [PATCH v2 3/3] drm/i915/display: Introduce new intel_psr_pause/resume function
This introduces the following function that can enable and disable psr
without intel_crtc_state/drm_connector_state when intel_psr is already
enabled with current intel_crtc_state and drm_connector_state information.
- intel_psr_pause(): Pause current PSR. it deactivates current psr state.
- intel_psr_resume(): Resume paused PSR without intel_crtc_state and
drm_connector_state. It activates paused psr state.
v2: Add new _intel_psr_enable_locked() function for removing duplicated
code. (Jose)
Cc: José Roberto de Souza
Cc: Stanislav Lisovskiy
Signed-off-by: Gwan-gyeong Mun
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 117 +++---
drivers/gpu/drm/i915/display/intel_psr.h | 2 +
3 files changed, 100 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 45c6388fa605..e29ffa8e8051 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1455,6 +1455,7 @@ struct intel_psr {
u16 su_x_granularity;
u32 dc3co_exitline;
u32 dc3co_exit_delay;
+ bool paused;
struct delayed_work dc3co_work;
struct drm_dp_vsc_sdp vsc;
};
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index ce7ce82d6f1b..d90c0d769f26 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -957,27 +957,11 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp)
IGNORE_PSR2_HW_TRACKING : 0);
}
-static void intel_psr_enable_locked(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state
*conn_state)
+static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
{
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_encoder *encoder = _port->base;
u32 val;
- drm_WARN_ON(_priv->drm, intel_dp->psr.enabled);
-
- intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
- intel_dp->psr.busy_frontbuffer_bits = 0;
- intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
- intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
- /* DC5/DC6 requires at least 6 idle frames */
- val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
- intel_dp->psr.dc3co_exit_delay = val;
- intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
- intel_dp->psr.psr2_sel_fetch_enabled =
crtc_state->enable_psr2_sel_fetch;
-
/*
* If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
* will still keep the error set even after the reset done in the
@@ -998,13 +982,26 @@ static void intel_psr_enable_locked(struct intel_dp
*intel_dp,
intel_dp->psr.sink_not_reliable = true;
drm_dbg_kms(_priv->drm,
"PSR interruption error set, not enabling PSR\n");
- return;
+ return false;
}
+ return true;
+}
+
+static void _intel_psr_enable_locked(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_encoder *encoder = _port->base;
+ const struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(encoder->base.crtc->state);
+
+ if (!psr_interrupt_error_check(intel_dp))
+ return;
+
drm_dbg_kms(_priv->drm, "Enabling PSR%s\n",
intel_dp->psr.psr2_enabled ? "2" : "1");
- intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
-_dp->psr.vsc);
+
intel_write_dp_vsc_sdp(encoder, crtc_state, _dp->psr.vsc);
intel_psr_enable_sink(intel_dp);
intel_psr_enable_source(intel_dp);
@@ -1013,6 +1010,32 @@ static void intel_psr_enable_locked(struct intel_dp
*intel_dp,
intel_psr_activate(intel_dp);
}
+static void intel_psr_enable_locked(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state
*conn_state)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ u32 val;
+
+ drm_WARN_ON(_priv->drm, intel_dp->psr.enabled);
+
+ intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
+ intel_dp->psr.busy_frontbuffer_bits = 0;
+ intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
+ intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
+ /* DC5/DC6 requires
[Intel-gfx] [PATCH v2 2/3] drm/i915/display: Remove a redundant function argument from intel_psr_enable_source()
It removes intel_crtc_state from function argument of
intel_psr_enable_source() in order to use intel_psr_enable_source()
without intel_crtc_state on other psr internal functions.
And we can get cpu_trancoder from intel_psr, therefore we don't need to
pass intel_crtc_state to this function.
Cc: José Roberto de Souza
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_psr.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 9c25a701943a..ce7ce82d6f1b 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -896,11 +896,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
intel_dp->psr.active = true;
}
-static void intel_psr_enable_source(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
+static void intel_psr_enable_source(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
u32 mask;
/* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
@@ -1008,7 +1007,7 @@ static void intel_psr_enable_locked(struct intel_dp
*intel_dp,
_dp->psr.vsc);
intel_write_dp_vsc_sdp(encoder, crtc_state, _dp->psr.vsc);
intel_psr_enable_sink(intel_dp);
- intel_psr_enable_source(intel_dp, crtc_state);
+ intel_psr_enable_source(intel_dp);
intel_dp->psr.enabled = true;
intel_psr_activate(intel_dp);
--
2.30.1
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/3] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct
It replaces dc3co_enabled with dc3co_exitline on intel_psr struct.
And it saves dc3co_exitline, not dc3co_enabled, so we can use
dc3co_exitline without intel_crtc_state on other psr internal function
like as intel_psr_enable_source().
v2: Do not mutate externally visible state in .compute_config(). (Ville)
Cc: Ville Syrjälä
Cc: José Roberto de Souza
Cc: Anshuman Gupta
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 10 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 1a76e1d9de7a..45c6388fa605 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1453,7 +1453,7 @@ struct intel_psr {
bool sink_not_reliable;
bool irq_aux_error;
u16 su_x_granularity;
- bool dc3co_enabled;
+ u32 dc3co_exitline;
u32 dc3co_exit_delay;
struct delayed_work dc3co_work;
struct drm_dp_vsc_sdp vsc;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index cd434285e3b7..9c25a701943a 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -637,7 +637,7 @@ static void tgl_dc3co_disable_work(struct work_struct *work)
static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp)
{
- if (!intel_dp->psr.dc3co_enabled)
+ if (!intel_dp->psr.dc3co_exitline)
return;
cancel_delayed_work(_dp->psr.dc3co_work);
@@ -938,7 +938,7 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
psr_irq_control(intel_dp);
- if (crtc_state->dc3co_exitline) {
+ if (intel_dp->psr.dc3co_exitline) {
u32 val;
/*
@@ -947,7 +947,7 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
*/
val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder));
val &= ~EXITLINE_MASK;
- val |= crtc_state->dc3co_exitline << EXITLINE_SHIFT;
+ val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT;
val |= EXITLINE_ENABLE;
intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val);
}
@@ -972,11 +972,11 @@ static void intel_psr_enable_locked(struct intel_dp
*intel_dp,
intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
intel_dp->psr.busy_frontbuffer_bits = 0;
intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
- intel_dp->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
/* DC5/DC6 requires at least 6 idle frames */
val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
intel_dp->psr.dc3co_exit_delay = val;
+ intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
intel_dp->psr.psr2_sel_fetch_enabled =
crtc_state->enable_psr2_sel_fetch;
/*
@@ -1761,7 +1761,7 @@ tgl_dc3co_flush(struct intel_dp *intel_dp, unsigned int
frontbuffer_bits,
{
mutex_lock(_dp->psr.lock);
- if (!intel_dp->psr.dc3co_enabled)
+ if (!intel_dp->psr.dc3co_exitline)
goto unlock;
if (!intel_dp->psr.psr2_enabled || !intel_dp->psr.active)
--
2.30.1
___
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Re: [Intel-gfx] [PATCH 3/3] drm/i915/display: Introduce new intel_psr_pause/resume function
On Wed, 2021-03-03 at 10:05 -0800, Souza, Jose wrote:
> patch 1 is a nack for the reasons that Ville explained.
>
> This one could be simplified even more.
>
> intel_psr_enable_locked() should have all the dev_priv->psr.*
> initialization from crtc_state + intel_dp_compute_psr_vsc_sdp().
> Then add a function(_intel_psr_enable_locked() or other better name
> that you can think) with the error checking + intel_write_dp_vsc_sdp()
> +
> intel_psr_enable_sink() + intel_psr_enable_source() +
> intel_psr_activate()...
>
> intel_psr_resume()
> take loock
> checks
> _intel_psr_enable_locked()
> unlock()
>
>
Hi, thanks for checking it.
I'll float a new patch that addresses your comments.
>
> On Wed, 2021-03-03 at 18:42 +0200, Gwan-gyeong Mun wrote:
> > This introduces the following function that can enable and disable
> > psr
> > without intel_crtc_state when intel_psr is already enabled with
> > current
> > intel_crtc_state information.
> >
> > - intel_psr_pause(): Pause current PSR. it deactivates current psr
> > state.
> > - intel_psr_resume(): Resume paused PSR without intel_crtc_state.
> > It activates paused psr state.
> >
> > Cc: José Roberto de Souza
> > Cc: Stanislav Lisovskiy
> > Signed-off-by: Gwan-gyeong Mun
> > ---
> > .../drm/i915/display/intel_display_types.h | 1 +
> > drivers/gpu/drm/i915/display/intel_psr.c | 111 +++-
> > --
> > drivers/gpu/drm/i915/display/intel_psr.h | 2 +
> > 3 files changed, 97 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index f69bd1caebbf..d49b79a0691a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1454,6 +1454,7 @@ struct intel_psr {
> > u16 su_x_granularity;
> > u32 dc3co_exitline;
> > u32 dc3co_exit_delay;
> > + bool paused;
> > struct delayed_work dc3co_work;
> > struct drm_dp_vsc_sdp vsc;
> > };
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index ea8f9598e6a3..533fc21f4352 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -957,26 +957,11 @@ static void intel_psr_enable_source(struct
> > intel_dp *intel_dp)
> > IGNORE_PSR2_HW_TRACKING : 0);
> > }
> >
> >
> > -static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> > - const struct intel_crtc_state
> > *crtc_state,
> > - const struct drm_connector_state
> > *conn_state)
> > +static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
> > {
> > - struct intel_digital_port *dig_port =
> > dp_to_dig_port(intel_dp);
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > - struct intel_encoder *encoder = _port->base;
> > u32 val;
> >
> >
> > - drm_WARN_ON(_priv->drm, intel_dp->psr.enabled);
> > -
> > - intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> > - intel_dp->psr.busy_frontbuffer_bits = 0;
> > - intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)-
> > >pipe;
> > - intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> > - /* DC5/DC6 requires at least 6 idle frames */
> > - val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) *
> > 6);
> > - intel_dp->psr.dc3co_exit_delay = val;
> > - intel_dp->psr.psr2_sel_fetch_enabled = crtc_state-
> > >enable_psr2_sel_fetch;
> > -
> > /*
> > * If a PSR error happened and the driver is reloaded, the
> > EDP_PSR_IIR
> > * will still keep the error set even after the reset done in
> > the
> > @@ -997,9 +982,36 @@ static void intel_psr_enable_locked(struct
> > intel_dp *intel_dp,
> > intel_dp->psr.sink_not_reliable = true;
> > drm_dbg_kms(_priv->drm,
> > "PSR interruption error set, not enabling
> > PSR\n");
> > - return;
> > + return false;
> > }
> >
> >
> > + return true;
> > +}
> > +
> > +static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> > + const struct intel_crtc_state
> > *crtc_state,
> > + const struct drm_connector_state
> > *conn_state)
> > +{
> > + struct intel_digital_port *dig_port =
> > dp_to_dig_port(intel_dp);
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > + struct intel_encoder *encoder = _port->base;
> > + u32 val;
> > +
> > + drm_WARN_ON(_priv->drm, intel_dp->psr.enabled);
> > +
> > + intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> > + intel_dp->psr.busy_frontbuffer_bits = 0;
> > +
Re: [Intel-gfx] [PATCH 1/3] drm/i915/display: Move dc3co_exitline variable to struct intel_psr
On Wed, 2021-03-03 at 18:54 +0200, Ville Syrjälä wrote:
> On Wed, Mar 03, 2021 at 06:41:59PM +0200, Gwan-gyeong Mun wrote:
> > dc3co_exitline is indirectly called by intel_psr_compute_config().
> > And it will not be changed until the next calling of
> > intel_psr_compute_config(). So in order to use dc3co_exitline without
> > intel_crtc_state on other psr internal function, it moves
> > dc3co_exitline
> > variable to struct intel_psr.
> > And it removes a dc3co_enabled variable from struct intel_psr.
> >
> > Cc: José Roberto de Souza
> > Cc: Anshuman Gupta
> > Signed-off-by: Gwan-gyeong Mun
> > ---
> > drivers/gpu/drm/i915/display/intel_display_types.h | 3 +--
> > drivers/gpu/drm/i915/display/intel_psr.c | 11 +--
> > 2 files changed, 6 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 1a76e1d9de7a..f69bd1caebbf 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1002,7 +1002,6 @@ struct intel_crtc_state {
> > bool has_psr;
> > bool has_psr2;
> > bool enable_psr2_sel_fetch;
> > - u32 dc3co_exitline;
> >
> > /*
> > * Frequence the dpll for the port should run at. Differs
> > from the
> > @@ -1453,7 +1452,7 @@ struct intel_psr {
> > bool sink_not_reliable;
> > bool irq_aux_error;
> > u16 su_x_granularity;
> > - bool dc3co_enabled;
> > + u32 dc3co_exitline;
> > u32 dc3co_exit_delay;
> > struct delayed_work dc3co_work;
> > struct drm_dp_vsc_sdp vsc;
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index cd434285e3b7..976826653143 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -637,7 +637,7 @@ static void tgl_dc3co_disable_work(struct
> > work_struct *work)
> >
> > static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp
> > *intel_dp)
> > {
> > - if (!intel_dp->psr.dc3co_enabled)
> > + if (!intel_dp->psr.dc3co_exitline)
> > return;
> >
> > cancel_delayed_work(_dp->psr.dc3co_work);
> > @@ -679,7 +679,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp
> > *intel_dp,
> > if (drm_WARN_ON(_priv->drm, exit_scanlines >
> > crtc_vdisplay))
> > return;
> >
> > - crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;
> > + intel_dp->psr.dc3co_exitline = crtc_vdisplay -
> > exit_scanlines;
>
> Thou shalt not mutate externally visible state in .compute_config().
> You either want to make a copy of it or just compute it on the spot in
> the psr_enable(). The first option is a good choice when you can also
> hook into into the readout+state checker.
>
Hi, thanks for pointing out where I was approached incorrectly.
I'll float new patch that makes copy crtc_state's dc3co_exitline to
intel_psr.dc3co_exitline.
> > }
> >
> > static bool intel_psr2_sel_fetch_config_valid(struct intel_dp
> > *intel_dp,
> > @@ -938,7 +938,7 @@ static void intel_psr_enable_source(struct
> > intel_dp *intel_dp,
> >
> > psr_irq_control(intel_dp);
> >
> > - if (crtc_state->dc3co_exitline) {
> > + if (intel_dp->psr.dc3co_exitline) {
> > u32 val;
> >
> > /*
> > @@ -947,7 +947,7 @@ static void intel_psr_enable_source(struct
> > intel_dp *intel_dp,
> > */
> > val = intel_de_read(dev_priv,
> > EXITLINE(cpu_transcoder));
> > val &= ~EXITLINE_MASK;
> > - val |= crtc_state->dc3co_exitline << EXITLINE_SHIFT;
> > + val |= intel_dp->psr.dc3co_exitline <<
> > EXITLINE_SHIFT;
> > val |= EXITLINE_ENABLE;
> > intel_de_write(dev_priv, EXITLINE(cpu_transcoder),
> > val);
> > }
> > @@ -972,7 +972,6 @@ static void intel_psr_enable_locked(struct
> > intel_dp *intel_dp,
> > intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> > intel_dp->psr.busy_frontbuffer_bits = 0;
> > intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)-
> > >pipe;
> > - intel_dp->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
> > intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> > /* DC5/DC6 requires at least 6 idle frames */
> > val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) *
> > 6);
> > @@ -1761,7 +1760,7 @@ tgl_dc3co_flush(struct intel_dp *intel_dp,
> > unsigned int frontbuffer_bits,
> > {
> > mutex_lock(_dp->psr.lock);
> >
> > - if (!intel_dp->psr.dc3co_enabled)
> > + if (!intel_dp->psr.dc3co_exitline)
> > goto unlock;
> >
> > if (!intel_dp->psr.psr2_enabled || !intel_dp->psr.active)
> > --
> > 2.30.1
> >
> >
[Intel-gfx] [PATCH] i915/query: Correlate engine and cpu timestamps with better accuracy
Perf measurements rely on CPU and engine timestamps to correlate
events of interest across these time domains. Current mechanisms get
these timestamps separately and the calculated delta between these
timestamps lack enough accuracy.
To improve the accuracy of these time measurements to within a few us,
add a query that returns the engine and cpu timestamps captured as
close to each other as possible.
v2: (Tvrtko)
- document clock reference used
- return cpu timestamp always
- capture cpu time just before lower dword of cs timestamp
v3: (Chris)
- use uncore-rpm
- use __query_cs_timestamp helper
v4: (Lionel)
- Kernel perf subsytem allows users to specify the clock id to be used
in perf_event_open. This clock id is used by the perf subsystem to
return the appropriate cpu timestamp in perf events. Similarly, let
the user pass the clockid to this query so that cpu timestamp
corresponds to the clock id requested.
v5: (Tvrtko)
- Use normal ktime accessors instead of fast versions
- Add more uApi documentation
v6: (Lionel)
- Move switch out of spinlock
v7: (Chris)
- cs_timestamp is a misnomer, use cs_cycles instead
- return the cs cycle frequency as well in the query
v8:
- Add platform and engine specific checks
v9: (Lionel)
- Return 2 cpu timestamps in the query - captured before and after the
register read
v10: (Chris)
- Use local_clock() to measure time taken to read lower dword of
register and return it to user.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_query.c | 145 ++
include/uapi/drm/i915_drm.h | 48 ++
2 files changed, 193 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_query.c
b/drivers/gpu/drm/i915/i915_query.c
index fed337ad7b68..25b96927ab92 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -6,6 +6,8 @@
#include
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_user.h"
#include "i915_drv.h"
#include "i915_perf.h"
#include "i915_query.h"
@@ -90,6 +92,148 @@ static int query_topology_info(struct drm_i915_private
*dev_priv,
return total_length;
}
+typedef u64 (*__ktime_func_t)(void);
+static __ktime_func_t __clock_id_to_func(clockid_t clk_id)
+{
+ /*
+* Use logic same as the perf subsystem to allow user to select the
+* reference clock id to be used for timestamps.
+*/
+ switch (clk_id) {
+ case CLOCK_MONOTONIC:
+ return _get_ns;
+ case CLOCK_MONOTONIC_RAW:
+ return _get_raw_ns;
+ case CLOCK_REALTIME:
+ return _get_real_ns;
+ case CLOCK_BOOTTIME:
+ return _get_boottime_ns;
+ case CLOCK_TAI:
+ return _get_clocktai_ns;
+ default:
+ return NULL;
+ }
+}
+
+static inline int
+__read_timestamps(struct intel_uncore *uncore,
+ i915_reg_t lower_reg,
+ i915_reg_t upper_reg,
+ u64 *cs_ts,
+ u64 *cpu_ts,
+ __ktime_func_t cpu_clock)
+{
+ u32 upper, lower, old_upper, loop = 0;
+
+ upper = intel_uncore_read_fw(uncore, upper_reg);
+ do {
+ cpu_ts[1] = local_clock();
+ cpu_ts[0] = cpu_clock();
+ lower = intel_uncore_read_fw(uncore, lower_reg);
+ cpu_ts[1] = local_clock() - cpu_ts[1];
+ old_upper = upper;
+ upper = intel_uncore_read_fw(uncore, upper_reg);
+ } while (upper != old_upper && loop++ < 2);
+
+ *cs_ts = (u64)upper << 32 | lower;
+
+ return 0;
+}
+
+static int
+__query_cs_cycles(struct intel_engine_cs *engine,
+ u64 *cs_ts, u64 *cpu_ts,
+ __ktime_func_t cpu_clock)
+{
+ struct intel_uncore *uncore = engine->uncore;
+ enum forcewake_domains fw_domains;
+ u32 base = engine->mmio_base;
+ intel_wakeref_t wakeref;
+ int ret;
+
+ fw_domains = intel_uncore_forcewake_for_reg(uncore,
+ RING_TIMESTAMP(base),
+ FW_REG_READ);
+
+ with_intel_runtime_pm(uncore->rpm, wakeref) {
+ spin_lock_irq(>lock);
+ intel_uncore_forcewake_get__locked(uncore, fw_domains);
+
+ ret = __read_timestamps(uncore,
+ RING_TIMESTAMP(base),
+ RING_TIMESTAMP_UDW(base),
+ cs_ts,
+ cpu_ts,
+ cpu_clock);
+
+ intel_uncore_forcewake_put__locked(uncore, fw_domains);
+ spin_unlock_irq(>lock);
+ }
+
+ return ret;
+}
+
+static int
+query_cs_cycles(struct drm_i915_private *i915,
+ struct drm_i915_query_item *query_item)
+{
+ struct drm_i915_query_cs_cycles __user *query_ptr;
+
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev7)
== Series Details == Series: drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev7) URL : https://patchwork.freedesktop.org/series/81764/ State : success == Summary == CI Bug Log - changes from CI_DRM_9835_full -> Patchwork_19759_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19759_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@psr2: - shard-iclb: NOTRUN -> [SKIP][1] ([i915#658]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/shard-iclb7/igt@feature_discov...@psr2.html * igt@gem_create@create-massive: - shard-snb: NOTRUN -> [DMESG-WARN][2] ([i915#3002]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/shard-snb5/igt@gem_cre...@create-massive.html - shard-skl: NOTRUN -> [DMESG-WARN][3] ([i915#3002]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/shard-skl9/igt@gem_cre...@create-massive.html - shard-apl: NOTRUN -> [DMESG-WARN][4] ([i915#3002]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/shard-apl8/igt@gem_cre...@create-massive.html * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-kbl: NOTRUN -> [DMESG-WARN][5] ([i915#180]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/shard-kbl2/igt@gem_ctx_isolation@preservation...@vcs0.html * igt@gem_ctx_persistence@clone: - shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +5 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/shard-snb7/igt@gem_ctx_persiste...@clone.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9835/shard-tglb1/igt@gem_exec_fair@basic-f...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/shard-tglb8/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9835/shard-iclb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/shard-iclb4/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][11] ([i915#2842]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-glk: [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9835/shard-glk8/igt@gem_exec_fair@basic-p...@vecs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/shard-glk6/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_params@no-vebox: - shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271]) +118 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/shard-skl4/igt@gem_exec_par...@no-vebox.html * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-apl: [PASS][15] -> [FAIL][16] ([i915#2389]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9835/shard-apl1/igt@gem_exec_reloc@basic-many-act...@rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/shard-apl7/igt@gem_exec_reloc@basic-many-act...@rcs0.html * igt@gem_exec_reloc@basic-parallel: - shard-apl: NOTRUN -> [TIMEOUT][17] ([i915#1729]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/shard-apl2/igt@gem_exec_re...@basic-parallel.html * igt@gem_exec_reloc@basic-wide-active@rcs0: - shard-snb: NOTRUN -> [FAIL][18] ([i915#2389]) +5 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/shard-snb7/igt@gem_exec_reloc@basic-wide-act...@rcs0.html * igt@gem_exec_schedule@u-fairslice@rcs0: - shard-apl: NOTRUN -> [DMESG-WARN][19] ([i915#1610]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/shard-apl7/igt@gem_exec_schedule@u-fairsl...@rcs0.html - shard-skl: [PASS][20] -> [DMESG-WARN][21] ([i915#1610] / [i915#2803]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9835/shard-skl4/igt@gem_exec_schedule@u-fairsl...@rcs0.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/shard-skl7/igt@gem_exec_schedule@u-fairsl...@rcs0.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#2190]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/shard-apl8/igt@gem_huc_c...@huc-copy.html * igt@gem_pread@exhaustion: - shard-apl: NOTRUN -> [WARN][23]
[Intel-gfx] ✓ Fi.CI.BAT: success for Revert "drm/i915: Propagate errors on awaiting already signaled fences"
== Series Details == Series: Revert "drm/i915: Propagate errors on awaiting already signaled fences" URL : https://patchwork.freedesktop.org/series/87704/ State : success == Summary == CI Bug Log - changes from CI_DRM_9836 -> Patchwork_19761 Summary --- **WARNING** Minor unknown changes coming with Patchwork_19761 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19761, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19761: ### IGT changes ### Warnings * igt@gem_linear_blits@basic: - fi-kbl-8809g: [TIMEOUT][1] ([i915#2502]) -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/fi-kbl-8809g/igt@gem_linear_bl...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/fi-kbl-8809g/igt@gem_linear_bl...@basic.html Known issues Here are the changes found in Patchwork_19761 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271]) +23 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_tiled_fence_blits@basic: - fi-kbl-8809g: [PASS][5] -> [TIMEOUT][6] ([i915#3145]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/fi-kbl-8809g/igt@gem_tiled_fence_bl...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/fi-kbl-8809g/igt@gem_tiled_fence_bl...@basic.html * igt@i915_selftest@live@gt_heartbeat: - fi-bxt-dsi: [PASS][7] -> [DMESG-FAIL][8] ([i915#2291] / [i915#541]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][9] ([i915#1886] / [i915#2291]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@late_gt_pm: - fi-bsw-nick:[PASS][10] -> [DMESG-FAIL][11] ([i915#2927]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_frontbuffer_tracking@basic: - fi-kbl-soraka: NOTRUN -> [FAIL][13] ([i915#49]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/fi-kbl-soraka/igt@kms_frontbuffer_track...@basic.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-kbl-soraka: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#533]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@runner@aborted: - fi-bsw-nick:NOTRUN -> [FAIL][15] ([i915#1436]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/fi-bsw-nick/igt@run...@aborted.html Warnings * igt@gem_tiled_blits@basic: - fi-kbl-8809g: [TIMEOUT][16] ([i915#3145]) -> [TIMEOUT][17] ([i915#2502] / [i915#3145]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html * igt@i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][18] ([i915#1982] / [i915#3143]) -> [DMESG-WARN][19] ([i915#3143]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/fi-glk-dsi/igt@i915_pm_...@module-reload.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19761/fi-glk-dsi/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
Re: [Intel-gfx] [PATCH] Revert "drm/i915: Propagate errors on awaiting already signaled fences"
Quoting Jason Ekstrand (2021-03-05 17:05:46) > This reverts commit 9e31c1fe45d555a948ff66f1f0e3fe1f83ca63f7. Ever > since that commit, we've been having issues where a hang in one client > can propagate to another. In particular, a hang in an app can propagate > to the X server which causes the whole desktop to lock up. The fence error handling is required to prevent user's circumventing incomplete work, such as security validation or escaping isolation. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gem: Fix fall-through warnings for Clang
== Series Details == Series: drm/i915/gem: Fix fall-through warnings for Clang URL : https://patchwork.freedesktop.org/series/87690/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9835_full -> Patchwork_19758_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19758_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19758_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19758_full: ### IGT changes ### Possible regressions * igt@kms_atomic_transition@plane-all-transition-nonblocking@dp-1-pipe-b: - shard-kbl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9835/shard-kbl3/igt@kms_atomic_transition@plane-all-transition-nonblock...@dp-1-pipe-b.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19758/shard-kbl2/igt@kms_atomic_transition@plane-all-transition-nonblock...@dp-1-pipe-b.html * igt@perf@non-zero-reason: - shard-tglb: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9835/shard-tglb6/igt@p...@non-zero-reason.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19758/shard-tglb2/igt@p...@non-zero-reason.html Known issues Here are the changes found in Patchwork_19758_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-snb: NOTRUN -> [DMESG-WARN][5] ([i915#3002]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19758/shard-snb2/igt@gem_cre...@create-massive.html - shard-skl: NOTRUN -> [DMESG-WARN][6] ([i915#3002]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19758/shard-skl10/igt@gem_cre...@create-massive.html - shard-apl: NOTRUN -> [DMESG-WARN][7] ([i915#3002]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19758/shard-apl2/igt@gem_cre...@create-massive.html * igt@gem_ctx_persistence@smoketest: - shard-snb: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1099]) +4 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19758/shard-snb6/igt@gem_ctx_persiste...@smoketest.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][9] -> [TIMEOUT][10] ([i915#2369] / [i915#3063]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9835/shard-tglb1/igt@gem_...@unwedge-stress.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19758/shard-tglb5/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-deadline: - shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2846]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9835/shard-kbl4/igt@gem_exec_f...@basic-deadline.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19758/shard-kbl6/igt@gem_exec_f...@basic-deadline.html - shard-skl: NOTRUN -> [FAIL][13] ([i915#2846]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19758/shard-skl2/igt@gem_exec_f...@basic-deadline.html - shard-apl: NOTRUN -> [FAIL][14] ([i915#2846]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19758/shard-apl6/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2842]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9835/shard-tglb1/igt@gem_exec_fair@basic-f...@rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19758/shard-tglb1/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][17] ([i915#2842]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19758/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][18] -> [FAIL][19] ([i915#2842]) +2 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9835/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19758/shard-glk6/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_flush@basic-batch-kernel-default-cmd: - shard-snb: NOTRUN -> [SKIP][20] ([fdo#109271]) +355 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19758/shard-snb6/igt@gem_exec_fl...@basic-batch-kernel-default-cmd.html * igt@gem_exec_params@no-vebox: - shard-skl: NOTRUN -> [SKIP][21] ([fdo#109271]) +126 similar issues [21]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Revert "drm/i915: Propagate errors on awaiting already signaled fences"
== Series Details == Series: Revert "drm/i915: Propagate errors on awaiting already signaled fences" URL : https://patchwork.freedesktop.org/series/87704/ State : warning == Summary == $ dim checkpatch origin/drm-tip d9e330a82c56 Revert "drm/i915: Propagate errors on awaiting already signaled fences" -:44: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: Jason Ekstrand ' != 'Signed-off-by: Jason Ekstrand ' total: 0 errors, 1 warnings, 0 checks, 22 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] Revert "drm/i915: Propagate errors on awaiting already signaled fences"
This reverts commit 9e31c1fe45d555a948ff66f1f0e3fe1f83ca63f7. Ever
since that commit, we've been having issues where a hang in one client
can propagate to another. In particular, a hang in an app can propagate
to the X server which causes the whole desktop to lock up.
Signed-off-by: Jason Ekstrand
Reported-by: Marcin Slusarz
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3080
Fixes: 9e31c1fe45d5 ("drm/i915: Propagate errors on awaiting already signaled
fences")
---
drivers/gpu/drm/i915/i915_request.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index e7b4c4bc41a64..870d6083bb57e 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1232,10 +1232,8 @@ i915_request_await_execution(struct i915_request *rq,
do {
fence = *child++;
- if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >flags)) {
- i915_sw_fence_set_error_once(>submit, fence->error);
+ if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >flags))
continue;
- }
if (fence->context == rq->fence.context)
continue;
@@ -1333,10 +1331,8 @@ i915_request_await_dma_fence(struct i915_request *rq,
struct dma_fence *fence)
do {
fence = *child++;
- if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >flags)) {
- i915_sw_fence_set_error_once(>submit, fence->error);
+ if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >flags))
continue;
- }
/*
* Requests on the same timeline are explicitly ordered, along
--
2.29.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: More SAGV related fixes/cleanups
== Series Details ==
Series: drm/i915: More SAGV related fixes/cleanups
URL : https://patchwork.freedesktop.org/series/87699/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9836 -> Patchwork_19760
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19760:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@active:
- {fi-ehl-1}: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/fi-ehl-1/igt@i915_selftest@l...@active.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/fi-ehl-1/igt@i915_selftest@l...@active.html
Known issues
Here are the changes found in Patchwork_19760 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271]) +23 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html
* igt@gem_exec_gttfill@basic:
- fi-kbl-8809g: [PASS][4] -> [TIMEOUT][5] ([i915#3145]) +1 similar
issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/fi-kbl-8809g/igt@gem_exec_gttf...@basic.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/fi-kbl-8809g/igt@gem_exec_gttf...@basic.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@i915_selftest@live@client:
- fi-glk-dsi: [PASS][7] -> [DMESG-FAIL][8] ([i915#3047])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/fi-glk-dsi/igt@i915_selftest@l...@client.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/fi-glk-dsi/igt@i915_selftest@l...@client.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][9] ([i915#1886] / [i915#2291])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_frontbuffer_tracking@basic:
- fi-kbl-soraka: NOTRUN -> [FAIL][11] ([i915#49])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/fi-kbl-soraka/igt@kms_frontbuffer_track...@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
Possible fixes
* igt@gem_linear_blits@basic:
- fi-kbl-8809g: [TIMEOUT][13] ([i915#2502]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/fi-kbl-8809g/igt@gem_linear_bl...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/fi-kbl-8809g/igt@gem_linear_bl...@basic.html
Warnings
* igt@gem_tiled_blits@basic:
- fi-kbl-8809g: [TIMEOUT][15] ([i915#3145]) -> [TIMEOUT][16]
([i915#2502] / [i915#3145])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9836/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19760/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2089]: https://gitlab.freedesktop.org/drm/intel/issues/2089
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2502]: https://gitlab.freedesktop.org/drm/intel/issues/2502
[i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
[i915#3047]: https://gitlab.freedesktop.org/drm/intel/issues/3047
[i915#3145]: https://gitlab.freedesktop.org/drm/intel/issues/3145
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Participating hosts (43 -> 39)
Re: [Intel-gfx] [patch 2/7] drm/vmgfx: Replace kmap_atomic()
On 03.03.21 14:20, Thomas Gleixner wrote:
> From: Thomas Gleixner
>
> There is no reason to disable pagefaults and preemption as a side effect of
> kmap_atomic_prot().
>
> Use kmap_local_page_prot() instead and document the reasoning for the
> mapping usage with the given pgprot.
>
> Remove the NULL pointer check for the map. These functions return a valid
> address for valid pages and the return was bogus anyway as it would have
> left preemption and pagefaults disabled.
>
> Signed-off-by: Thomas Gleixner
> Cc: VMware Graphics
> Cc: Roland Scheidegger
> Cc: Zack Rusin
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: dri-de...@lists.freedesktop.org
> ---
> drivers/gpu/drm/vmwgfx/vmwgfx_blit.c | 30 --
> 1 file changed, 12 insertions(+), 18 deletions(-)
>
> --- a/drivers/gpu/drm/vmwgfx/vmwgfx_blit.c
> +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_blit.c
> @@ -375,12 +375,12 @@ static int vmw_bo_cpu_blit_line(struct v
> copy_size = min_t(u32, copy_size, PAGE_SIZE - src_page_offset);
>
> if (unmap_src) {
> - kunmap_atomic(d->src_addr);
> + kunmap_local(d->src_addr);
> d->src_addr = NULL;
> }
>
> if (unmap_dst) {
> - kunmap_atomic(d->dst_addr);
> + kunmap_local(d->dst_addr);
> d->dst_addr = NULL;
> }
>
> @@ -388,12 +388,8 @@ static int vmw_bo_cpu_blit_line(struct v
> if (WARN_ON_ONCE(dst_page >= d->dst_num_pages))
> return -EINVAL;
>
> - d->dst_addr =
> - kmap_atomic_prot(d->dst_pages[dst_page],
> - d->dst_prot);
> - if (!d->dst_addr)
> - return -ENOMEM;
> -
> + d->dst_addr =
> kmap_local_page_prot(d->dst_pages[dst_page],
> +d->dst_prot);
> d->mapped_dst = dst_page;
> }
>
> @@ -401,12 +397,8 @@ static int vmw_bo_cpu_blit_line(struct v
> if (WARN_ON_ONCE(src_page >= d->src_num_pages))
> return -EINVAL;
>
> - d->src_addr =
> - kmap_atomic_prot(d->src_pages[src_page],
> - d->src_prot);
> - if (!d->src_addr)
> - return -ENOMEM;
> -
> + d->src_addr =
> kmap_local_page_prot(d->src_pages[src_page],
> +d->src_prot);
> d->mapped_src = src_page;
> }
> diff->do_cpy(diff, d->dst_addr + dst_page_offset,
> @@ -436,8 +428,10 @@ static int vmw_bo_cpu_blit_line(struct v
> *
> * Performs a CPU blit from one buffer object to another avoiding a full
> * bo vmap which may exhaust- or fragment vmalloc space.
> - * On supported architectures (x86), we're using kmap_atomic which avoids
> - * cross-processor TLB- and cache flushes and may, on non-HIGHMEM systems
> + *
> + * On supported architectures (x86), we're using kmap_local_prot() which
> + * avoids cross-processor TLB- and cache flushes. kmap_local_prot() will
> + * either map a highmem page with the proper pgprot on HIGHMEM=y systems or
> * reference already set-up mappings.
> *
> * Neither of the buffer objects may be placed in PCI memory
> @@ -500,9 +494,9 @@ int vmw_bo_cpu_blit(struct ttm_buffer_ob
> }
> out:
> if (d.src_addr)
> - kunmap_atomic(d.src_addr);
> + kunmap_local(d.src_addr);
> if (d.dst_addr)
> - kunmap_atomic(d.dst_addr);
> + kunmap_local(d.dst_addr);
>
> return ret;
> }
>
>
Seems reasonable to me.
Reviewed-by: Roland Scheidegger
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: More SAGV related fixes/cleanups
== Series Details == Series: drm/i915: More SAGV related fixes/cleanups URL : https://patchwork.freedesktop.org/series/87699/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5c14f9d5eac8 drm/i915: Fix enabled_planes bitmask ebc6a3e5fe6d drm/i915: Tighten SAGV constraint for pre-tgl 6316c8608f20 drm/i915: Check SAGV wm min_ddb_alloc rather than plane_res_b dca8ca1685be drm/i915: Calculate min_ddb_alloc for trans_wm 0531f5094e07 drm/i915: Extract skl_check_wm_level() and skl_check_nv12_wm_level() 42e654ae9c91 drm/i915: s/plane_res_b/blocks/ etc. -:385: WARNING:LONG_LINE: line length of 107 exceeds 100 columns #385: FILE: drivers/gpu/drm/i915/intel_pm.c:5955: + enast(old_wm->sagv.trans_wm.ignore_lines), old_wm->sagv.trans_wm.lines, -:396: WARNING:LONG_LINE: line length of 108 exceeds 100 columns #396: FILE: drivers/gpu/drm/i915/intel_pm.c:5966: + enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.lines); total: 0 errors, 2 warnings, 0 checks, 402 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9
On 05/03/2021 15:24, Chiou, Cooper wrote: After switched to ffs from fls in "patch v5"(https://patchwork.freedesktop.org/series/81764/#rev7), now CI result is PASS no regression in wa_verify warning. @Chen, Rong Could you please run “phoronix-test-suite.supertuxkart.1024x768.Fullscreen.Ultimate.1.GranParadisoIsland.frames_per_second” with this latest patch v5 on test box to see if any performance impact. We need testing on more that one box I'm afraid. Need to cover different fusing configs of Gen9 with and without the patch. I don't have any useful ideas on how to do it though. :( Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/4] drm/i915: Silence pipe tracepoint WARNs
On Thu, Mar 04, 2021 at 02:20:22PM -0500, Steven Rostedt wrote:
> On Thu, 4 Mar 2021 19:04:17 +0200
> Ville Syrjala wrote:
>
> > From: Ville Syrjälä
> >
> > I believe this should silence the WARN spew from the
> > pipe disable tracepoint Steve reported. And I tossed in
> > a few other minor improvements as well.
> >
> > Cc: Steven Rostedt
>
> It seemed to have stopped the general protection faults when tracing all
> events on my machine.
>
> Reported-by: Steven Rostedt (VMware)
> Tested-by: Steven Rostedt (VMware)
Series pushed to drm-intel-next. Thanks for reporting the problem.
>
> -- Steve
>
> >
> > Ville Syrjälä (4):
> > drm/i915: Move pipe enable/disable tracepoints to
> > intel_crtc_vblank_{on,off}()
> > drm/i915: Don't try to query the frame counter for disabled pipes
> > drm/i915: Return zero as the scanline counter for disabled pipes
> > drm/i915: Fix DSI TE max_vblank_count handling
> >
> > drivers/gpu/drm/i915/display/intel_crtc.c| 24 +---
> > drivers/gpu/drm/i915/display/intel_display.c | 8 +--
> > drivers/gpu/drm/i915/i915_irq.c | 2 +-
> > 3 files changed, 23 insertions(+), 11 deletions(-)
> >
--
Ville Syrjälä
Intel
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[Intel-gfx] [PATCH 4/6] drm/i915: Calculate min_ddb_alloc for trans_wm
From: Ville Syrjälä
Let's make all the "do we have enough DDB for this WM level?"
checks use min_ddb_alloc. To achieve that we need to populate
this for the transition watermarks as well.
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 36601e0a5073..38a6feced74f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4986,13 +4986,13 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
struct skl_plane_wm *wm =
_state->wm.skl.optimal.planes[plane_id];
- if (wm->trans_wm.plane_res_b >= total[plane_id])
+ if (wm->trans_wm.min_ddb_alloc > total[plane_id])
memset(>trans_wm, 0, sizeof(wm->trans_wm));
if (wm->sagv.wm0.min_ddb_alloc > total[plane_id])
memset(>sagv.wm0, 0, sizeof(wm->sagv.wm0));
- if (wm->sagv.trans_wm.plane_res_b >= total[plane_id])
+ if (wm->sagv.trans_wm.min_ddb_alloc > total[plane_id])
memset(>sagv.trans_wm, 0,
sizeof(wm->sagv.trans_wm));
}
@@ -5404,13 +5404,15 @@ static void skl_compute_transition_wm(struct
drm_i915_private *dev_priv,
} else {
res_blocks = wm0_sel_res_b + trans_offset_b;
}
+ res_blocks++;
/*
* Just assume we can enable the transition watermark. After
* computing the DDB we'll come back and disable it if that
* assumption turns out to be false.
*/
- trans_wm->plane_res_b = res_blocks + 1;
+ trans_wm->plane_res_b = res_blocks;
+ trans_wm->min_ddb_alloc = max_t(u16, wm0->min_ddb_alloc, res_blocks +
1);
trans_wm->plane_en = true;
}
--
2.26.2
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[Intel-gfx] [PATCH 6/6] drm/i915: s/plane_res_b/blocks/ etc.
From: Ville Syrjälä
Rename a bunch of the skl+ watermark struct members to
have sensible names. Avoids me having to think what
plane_res_b/etc. means.
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 24 +--
.../drm/i915/display/intel_display_types.h| 6 +-
drivers/gpu/drm/i915/intel_pm.c | 198 +-
3 files changed, 112 insertions(+), 116 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 076d381d3387..ad6567f04bfa 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9433,12 +9433,12 @@ static void verify_wm_state(struct intel_crtc *crtc,
drm_err(_priv->drm,
"[PLANE:%d:%s] mismatch in WM%d (expected e=%d
b=%u l=%u, got e=%d b=%u l=%u)\n",
plane->base.base.id, plane->base.name, level,
- sw_wm_level->plane_en,
- sw_wm_level->plane_res_b,
- sw_wm_level->plane_res_l,
- hw_wm_level->plane_en,
- hw_wm_level->plane_res_b,
- hw_wm_level->plane_res_l);
+ sw_wm_level->enable,
+ sw_wm_level->blocks,
+ sw_wm_level->lines,
+ hw_wm_level->enable,
+ hw_wm_level->blocks,
+ hw_wm_level->lines);
}
hw_wm_level = >wm.planes[plane->id].trans_wm;
@@ -9448,12 +9448,12 @@ static void verify_wm_state(struct intel_crtc *crtc,
drm_err(_priv->drm,
"[PLANE:%d:%s] mismatch in trans WM (expected
e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
plane->base.base.id, plane->base.name,
- sw_wm_level->plane_en,
- sw_wm_level->plane_res_b,
- sw_wm_level->plane_res_l,
- hw_wm_level->plane_en,
- hw_wm_level->plane_res_b,
- hw_wm_level->plane_res_l);
+ sw_wm_level->enable,
+ sw_wm_level->blocks,
+ sw_wm_level->lines,
+ hw_wm_level->enable,
+ hw_wm_level->blocks,
+ hw_wm_level->lines);
}
/* DDB */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8d9113fa82c7..b6eaa8ee2b66 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -721,9 +721,9 @@ struct intel_pipe_wm {
struct skl_wm_level {
u16 min_ddb_alloc;
- u16 plane_res_b;
- u8 plane_res_l;
- bool plane_en;
+ u16 blocks;
+ u8 lines;
+ bool enable;
bool ignore_lines;
bool can_sagv;
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3e26d8b667a1..559bc3ba9a74 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3893,12 +3893,12 @@ static bool skl_crtc_can_enable_sagv(const struct
intel_crtc_state *crtc_state)
int level;
/* Skip this plane if it's not enabled */
- if (!wm->wm[0].plane_en)
+ if (!wm->wm[0].enable)
continue;
/* Find the highest enabled wm level for this plane */
for (level = ilk_wm_max_level(dev_priv);
-!wm->wm[level].plane_en; --level)
+!wm->wm[level].enable; --level)
{ }
/* Highest common enabled wm level for all planes */
@@ -3917,7 +3917,7 @@ static bool skl_crtc_can_enable_sagv(const struct
intel_crtc_state *crtc_state)
* All enabled planes must have enabled a common wm level that
* can tolerate memory latencies higher than sagv_block_time_us
*/
- if (wm->wm[0].plane_en && !wm->wm[max_level].can_sagv)
+ if (wm->wm[0].enable && !wm->wm[max_level].can_sagv)
return false;
}
@@ -3936,7 +3936,7 @@ static bool tgl_crtc_can_enable_sagv(const struct
intel_crtc_state *crtc_state)
const struct skl_plane_wm *wm =
_state->wm.skl.optimal.planes[plane_id];
- if (wm->wm[0].plane_en && !wm->sagv.wm0.plane_en)
+ if (wm->wm[0].enable && !wm->sagv.wm0.enable)
[Intel-gfx] [PATCH 5/6] drm/i915: Extract skl_check_wm_level() and skl_check_nv12_wm_level()
From: Ville Syrjälä
Make the code more typo proof by extracting small helpers that
do the "do we have enough DDB for the WM level?" checks in
a consistent manner.
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 58 -
1 file changed, 35 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 38a6feced74f..3e26d8b667a1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4782,6 +4782,36 @@ skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
return >trans_wm;
}
+/*
+ * We only disable the watermarks for each plane if
+ * they exceed the ddb allocation of said plane. This
+ * is done so that we don't end up touching cursor
+ * watermarks needlessly when some other plane reduces
+ * our max possible watermark level.
+ *
+ * Bspec has this to say about the PLANE_WM enable bit:
+ * "All the watermarks at this level for all enabled
+ * planes must be enabled before the level will be used."
+ * So this is actually safe to do.
+ */
+static void
+skl_check_wm_level(struct skl_wm_level *wm, u64 total)
+{
+ if (wm->min_ddb_alloc > total)
+ memset(wm, 0, sizeof(*wm));
+}
+
+static void
+skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm,
+ u64 total, u64 uv_total)
+{
+ if (wm->min_ddb_alloc > total ||
+ uv_wm->min_ddb_alloc > uv_total) {
+ memset(wm, 0, sizeof(*wm));
+ memset(uv_wm, 0, sizeof(*uv_wm));
+ }
+}
+
static int
skl_allocate_plane_ddb(struct intel_atomic_state *state,
struct intel_crtc *crtc)
@@ -4949,21 +4979,8 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
struct skl_plane_wm *wm =
_state->wm.skl.optimal.planes[plane_id];
- /*
-* We only disable the watermarks for each plane if
-* they exceed the ddb allocation of said plane. This
-* is done so that we don't end up touching cursor
-* watermarks needlessly when some other plane reduces
-* our max possible watermark level.
-*
-* Bspec has this to say about the PLANE_WM enable bit:
-* "All the watermarks at this level for all enabled
-* planes must be enabled before the level will be
used."
-* So this is actually safe to do.
-*/
- if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
- wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
- memset(>wm[level], 0,
sizeof(wm->wm[level]));
+ skl_check_nv12_wm_level(>wm[level],
>uv_wm[level],
+ total[plane_id],
uv_total[plane_id]);
/*
* Wa_1408961008:icl, ehl
@@ -4986,14 +5003,9 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
struct skl_plane_wm *wm =
_state->wm.skl.optimal.planes[plane_id];
- if (wm->trans_wm.min_ddb_alloc > total[plane_id])
- memset(>trans_wm, 0, sizeof(wm->trans_wm));
-
- if (wm->sagv.wm0.min_ddb_alloc > total[plane_id])
- memset(>sagv.wm0, 0, sizeof(wm->sagv.wm0));
-
- if (wm->sagv.trans_wm.min_ddb_alloc > total[plane_id])
- memset(>sagv.trans_wm, 0,
sizeof(wm->sagv.trans_wm));
+ skl_check_wm_level(>trans_wm, total[plane_id]);
+ skl_check_wm_level(>sagv.wm0, total[plane_id]);
+ skl_check_wm_level(>sagv.trans_wm, total[plane_id]);
}
return 0;
--
2.26.2
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[Intel-gfx] [PATCH 3/6] drm/i915: Check SAGV wm min_ddb_alloc rather than plane_res_b
From: Ville Syrjälä
For non-transition watermarks we are supposed to check min_ddb_alloc
rather than plane_res_b when determining if we have enough DDB space
for it. A bit too much copy pasta made me check the wrong thing.
Cc: Stanislav Lisovskiy
Fixes: df4a50a35e2c ("drm/i915: Zero out SAGV wm when we don't have enough DDB
for it")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b6e34d1701a0..36601e0a5073 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4989,7 +4989,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
if (wm->trans_wm.plane_res_b >= total[plane_id])
memset(>trans_wm, 0, sizeof(wm->trans_wm));
- if (wm->sagv.wm0.plane_res_b >= total[plane_id])
+ if (wm->sagv.wm0.min_ddb_alloc > total[plane_id])
memset(>sagv.wm0, 0, sizeof(wm->sagv.wm0));
if (wm->sagv.trans_wm.plane_res_b >= total[plane_id])
--
2.26.2
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[Intel-gfx] [PATCH 2/6] drm/i915: Tighten SAGV constraint for pre-tgl
From: Ville Syrjälä
Say we have two planes enabled with watermarks configured
as follows:
plane A: wm0=enabled/can_sagv=false, wm1=enabled/can_sagv=true
plane B: wm0=enabled/can_sagv=true, wm1=disabled
This is possible since the latency we use to calculate
can_sagv may not be the same for both planes due to
skl_needs_memory_bw_wa().
In this case skl_crtc_can_enable_sagv() will see that
both planes have enabled at least one watermark level
with can_sagv==true, and thus proceeds to allow SAGV.
However, since plane B does not have wm1 enabled
plane A can't actually use it either. Thus we are
now running with SAGV enabled, but plane A can't
actually tolerate the extra latency it imposes.
To remedy this only allow SAGV on if the highest common
enabled watermark level for all active planes can tolerate
the extra SAGV latency.
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 854ffecd98d9..b6e34d1701a0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3876,6 +3876,7 @@ static bool skl_crtc_can_enable_sagv(const struct
intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum plane_id plane_id;
+ int max_level = INT_MAX;
if (!intel_has_sagv(dev_priv))
return false;
@@ -3900,12 +3901,23 @@ static bool skl_crtc_can_enable_sagv(const struct
intel_crtc_state *crtc_state)
!wm->wm[level].plane_en; --level)
{ }
+ /* Highest common enabled wm level for all planes */
+ max_level = min(level, max_level);
+ }
+
+ /* No enabled planes? */
+ if (max_level == INT_MAX)
+ return true;
+
+ for_each_plane_id_on_crtc(crtc, plane_id) {
+ const struct skl_plane_wm *wm =
+ _state->wm.skl.optimal.planes[plane_id];
+
/*
-* If any of the planes on this pipe don't enable wm levels that
-* incur memory latencies higher than sagv_block_time_us we
-* can't enable SAGV.
+* All enabled planes must have enabled a common wm level that
+* can tolerate memory latencies higher than sagv_block_time_us
*/
- if (!wm->wm[level].can_sagv)
+ if (wm->wm[0].plane_en && !wm->wm[max_level].can_sagv)
return false;
}
--
2.26.2
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[Intel-gfx] [PATCH 1/6] drm/i915: Fix enabled_planes bitmask
From: Ville Syrjälä
The enabled_planes bitmask was supposed to track logically enabled
planes (ie. fb!=NULL and crtc!=NULL), but instead we end up putting
even disabled planes into the bitmask since
intel_plane_atomic_check_with_state() only takes the early exit
if the plane was disabled and stays disabled. I think I misread
the early said codepath to exit whenever the plane is logically
disabled, which is not true.
So let's fix this up properly and set the bit only when the plane
actually is logically enabled.
Cc: Manasi Navare
Fixes: ee42ec19ca2e ("drm/i915: Track logically enabled planes for hw state")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 4683f98f7e54..c3f2962aa1eb 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -317,12 +317,13 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
return 0;
- new_crtc_state->enabled_planes |= BIT(plane->id);
-
ret = plane->check_plane(new_crtc_state, new_plane_state);
if (ret)
return ret;
+ if (fb)
+ new_crtc_state->enabled_planes |= BIT(plane->id);
+
/* FIXME pre-g4x don't work like this */
if (new_plane_state->uapi.visible)
new_crtc_state->active_planes |= BIT(plane->id);
--
2.26.2
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[Intel-gfx] [PATCH 0/6] drm/i915: More SAGV related fixes/cleanups
From: Ville Syrjälä The SAGV watermark handling is still a bit of mess. Let's try to clean it up a bit more, and in the process fix up a couple of minor mishaps. Ville Syrjälä (6): drm/i915: Fix enabled_planes bitmask drm/i915: Tighten SAGV constraint for pre-tgl drm/i915: Check SAGV wm min_ddb_alloc rather than plane_res_b drm/i915: Calculate min_ddb_alloc for trans_wm drm/i915: Extract skl_check_wm_level() and skl_check_nv12_wm_level() drm/i915: s/plane_res_b/blocks/ etc. .../gpu/drm/i915/display/intel_atomic_plane.c | 5 +- drivers/gpu/drm/i915/display/intel_display.c | 24 +- .../drm/i915/display/intel_display_types.h| 6 +- drivers/gpu/drm/i915/intel_pm.c | 272 ++ 4 files changed, 165 insertions(+), 142 deletions(-) -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9
After switched to ffs from fls in "patch v5"(https://patchwork.freedesktop.org/series/81764/#rev7), now CI result is PASS no regression in wa_verify warning. @Chen, Rong Could you please run “phoronix-test-suite.supertuxkart.1024x768.Fullscreen.Ultimate.1.GranParadisoIsland.frames_per_second” with this latest patch v5 on test box to see if any performance impact. Thanks, Best Regards, Cooper > Quoting Tvrtko Ursulin (2021-03-05 09:23:02) > > I am not sure if PC8 and DMC could also be involved from what Cooper > > was saying in a different thread. Maybe another CI run without the > > DMC, both ffs and fls. Another for limiting cstates. > > Disabling the dmc leaves the display code in an inconsistent state so we don't > complete a BAT run; but since the warnings are thrown during boot we can > say that disabling the dmc does clear up the workaround issues on > ehl/jsl: > > https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7612/fi-ehl-2/boot0.txt > https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7612/fi-jsl-1/boot0.txt > -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9
Quoting Chris Wilson (2021-03-05 12:20:45) > Quoting Tvrtko Ursulin (2021-03-05 09:23:02) > > I am not sure if PC8 and DMC could also be involved from what Cooper was > > saying in a different thread. Maybe another CI run without the DMC, both > > ffs and fls. Another for limiting cstates. > > Disabling the dmc leaves the display code in an inconsistent state so we > don't complete a BAT run; but since the warnings are thrown during boot > we can say that disabling the dmc does clear up the workaround issues on > ehl/jsl: > > https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7612/fi-ehl-2/boot0.txt > https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7612/fi-jsl-1/boot0.txt Fwiw, disabling the dmc and using fls for gen9 is not enough to avoid the warnings though: https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7614/fi-cfl-8109u/igt@i915_selftest@live@memory_region.html So far only ffs works for gen9 mcr. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev7)
== Series Details == Series: drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev7) URL : https://patchwork.freedesktop.org/series/81764/ State : success == Summary == CI Bug Log - changes from CI_DRM_9835 -> Patchwork_19759 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/index.html Known issues Here are the changes found in Patchwork_19759 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +26 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html * igt@core_hotunplug@unbind-rebind: - fi-bdw-5557u: NOTRUN -> [WARN][2] ([i915#2283]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html * igt@gem_exec_gttfill@basic: - fi-kbl-8809g: [PASS][3] -> [TIMEOUT][4] ([i915#3145]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9835/fi-kbl-8809g/igt@gem_exec_gttf...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/fi-kbl-8809g/igt@gem_exec_gttf...@basic.html * igt@kms_chamelium@dp-crc-fast: - fi-bdw-5557u: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html Possible fixes * igt@gem_linear_blits@basic: - fi-kbl-8809g: [TIMEOUT][6] ([i915#2502]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9835/fi-kbl-8809g/igt@gem_linear_bl...@basic.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/fi-kbl-8809g/igt@gem_linear_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - fi-kbl-8809g: [TIMEOUT][8] ([i915#3145]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9835/fi-kbl-8809g/igt@gem_tiled_fence_bl...@basic.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/fi-kbl-8809g/igt@gem_tiled_fence_bl...@basic.html * igt@i915_selftest@live@client: - fi-bsw-nick:[DMESG-FAIL][10] -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9835/fi-bsw-nick/igt@i915_selftest@l...@client.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/fi-bsw-nick/igt@i915_selftest@l...@client.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283 [i915#2502]: https://gitlab.freedesktop.org/drm/intel/issues/2502 [i915#3145]: https://gitlab.freedesktop.org/drm/intel/issues/3145 Participating hosts (44 -> 40) -- Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9835 -> Patchwork_19759 CI-20190529: 20190529 CI_DRM_9835: 2757a24fdc1f5f5bbef4371b2a1aa8cf739f818a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6024: d8e03fe437f0c328c96717a92ad97719c02ba2cd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19759: 300cf9636d21fd419ed23b4039579a2d7928704f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 300cf9636d21 drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19759/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Fix fall-through warnings for Clang
== Series Details == Series: drm/i915/gem: Fix fall-through warnings for Clang URL : https://patchwork.freedesktop.org/series/87690/ State : success == Summary == CI Bug Log - changes from CI_DRM_9835 -> Patchwork_19758 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19758/index.html Known issues Here are the changes found in Patchwork_19758 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +26 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19758/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html * igt@core_hotunplug@unbind-rebind: - fi-bdw-5557u: NOTRUN -> [WARN][2] ([i915#2283]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19758/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html * igt@gem_exec_gttfill@basic: - fi-kbl-8809g: [PASS][3] -> [TIMEOUT][4] ([i915#3145]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9835/fi-kbl-8809g/igt@gem_exec_gttf...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19758/fi-kbl-8809g/igt@gem_exec_gttf...@basic.html * igt@kms_chamelium@dp-crc-fast: - fi-bdw-5557u: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19758/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html Possible fixes * igt@i915_selftest@live@client: - fi-bsw-nick:[DMESG-FAIL][6] -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9835/fi-bsw-nick/igt@i915_selftest@l...@client.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19758/fi-bsw-nick/igt@i915_selftest@l...@client.html Warnings * igt@i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][8] ([i915#3143]) -> [DMESG-WARN][9] ([i915#1982] / [i915#3143]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9835/fi-glk-dsi/igt@i915_pm_...@module-reload.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19758/fi-glk-dsi/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283 [i915#3143]: https://gitlab.freedesktop.org/drm/intel/issues/3143 [i915#3145]: https://gitlab.freedesktop.org/drm/intel/issues/3145 Participating hosts (44 -> 38) -- Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-bsw-cyan fi-icl-y fi-bdw-samus Build changes - * Linux: CI_DRM_9835 -> Patchwork_19758 CI-20190529: 20190529 CI_DRM_9835: 2757a24fdc1f5f5bbef4371b2a1aa8cf739f818a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6024: d8e03fe437f0c328c96717a92ad97719c02ba2cd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19758: 8dc258c3615cd2356d3f057fc375754a147b7a75 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8dc258c3615c drm/i915/gem: Fix fall-through warnings for Clang == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19758/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9
WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Gen9 to
resolve VP8 hardware encoding system hang up on GT1 sku for
ChromiumOS projects
Slice specific MMIO read inaccurate so MGSR needs to be programmed
appropriately to get correct reads from these slicet-related MMIOs.
It dictates that before any MMIO read into Slice/Subslice specific
registers, MCR packet control register(0xFDC) needs to be programmed
to point to any enabled slice/subslice pair, especially GT1 fused sku
since this issue can be reproduced on VP8 hardware encoding via ffmpeg
on ChromiumOS devices.
When exit PC7, MGSR will reset so that we have to skip fused subslice ID.
Reference: HSD#1508045018,1405586840, BSID#0575
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Cc: William Tseng
Cc: Lee Shawn C
Signed-off-by: Cooper Chiou
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3b4a7da60f0b..eb2a587b06b8 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -878,9 +878,46 @@ hsw_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME);
}
+static void
+gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+ const struct sseu_dev_info *sseu = >gt.info.sseu;
+ unsigned int slice, subslice;
+ u32 mcr, mcr_mask;
+
+ GEM_BUG_ON(INTEL_GEN(i915) < 9);
+
+ /*
+* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml
+* Before any MMIO read into slice/subslice specific registers, MCR
+* packet control register needs to be programmed to point to any
+* enabled s/ss pair. Otherwise, incorrect values will be returned.
+* This means each subsequent MMIO read will be forwarded to an
+* specific s/ss combination, but this is OK since these registers
+* are consistent across s/ss in almost all cases. In the rare
+* occasions, such as INSTDONE, where this value is dependent
+* on s/ss combo, the read should be done with read_subslice_reg.
+*/
+ slice = ffs(sseu->slice_mask) - 1;
+ GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
+ subslice = ffs(intel_sseu_get_subslices(sseu, slice));
+ GEM_BUG_ON(!subslice);
+ subslice--;
+
+ mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+ mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
+
+ drm_dbg(>drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice,
mcr);
+
+ wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
+}
+
static void
gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
{
+ /* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml,gen9 */
+ gen9_wa_init_mcr(i915, wal);
+
/* WaDisableKillLogic:bxt,skl,kbl */
if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915))
wa_write_or(wal,
--
2.17.1
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[Intel-gfx] [PATCH RESEND][next] drm/i915/gem: Fix fall-through warnings for Clang
In preparation to enable -Wimplicit-fallthrough for Clang, fix a warning
by explicitly adding a return statement instead of letting the code fall
through to the next case.
Link: https://github.com/KSPP/linux/issues/115
Signed-off-by: Gustavo A. R. Silva
---
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index c2dba1cd9532..2a14a5c94a8a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -60,6 +60,7 @@ static void try_to_writeback(struct drm_i915_gem_object *obj,
switch (obj->mm.madv) {
case I915_MADV_DONTNEED:
i915_gem_object_truncate(obj);
+ return;
case __I915_MADV_PURGED:
return;
}
--
2.27.0
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Re: [Intel-gfx] [PATCH v3] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9
Quoting Tvrtko Ursulin (2021-03-05 09:23:02) > I am not sure if PC8 and DMC could also be involved from what Cooper was > saying in a different thread. Maybe another CI run without the DMC, both > ffs and fls. Another for limiting cstates. Disabling the dmc leaves the display code in an inconsistent state so we don't complete a BAT run; but since the warnings are thrown during boot we can say that disabling the dmc does clear up the workaround issues on ehl/jsl: https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7612/fi-ehl-2/boot0.txt https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7612/fi-jsl-1/boot0.txt -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 6/7] drm/i915: rename DISP_STEPPING->DISPLAY_STEP and GT_STEPPING->GT_STEP
Quoting Jani Nikula (2021-02-24 08:46:55)
> On Tue, 23 Feb 2021, Lucas De Marchi wrote:
> > On Tue, Feb 23, 2021 at 05:35:11PM +0200, Jani Nikula wrote:
> >>Matter of taste. STEP matches the enums.
> >>
> >>Signed-off-by: Jani Nikula
> >>---
> >> drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
> >> drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
> >> drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
> >> drivers/gpu/drm/i915/gt/intel_workarounds.c| 10 +-
> >> drivers/gpu/drm/i915/i915_drv.h| 10 +-
> >> drivers/gpu/drm/i915/intel_device_info.c | 2 +-
> >> drivers/gpu/drm/i915/intel_pm.c| 2 +-
> >> 7 files changed, 16 insertions(+), 16 deletions(-)
> >>
> >>diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> >>b/drivers/gpu/drm/i915/display/intel_display_power.c
> >>index f00c1750febd..1f7b2700947a 100644
> >>--- a/drivers/gpu/drm/i915/display/intel_display_power.c
> >>+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> >>@@ -5349,7 +5349,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private
> >>*dev_priv)
> >>
> >> if (IS_ALDERLAKE_S(dev_priv) ||
> >> IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> >>- IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
> >>+ IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >> /* Wa_1409767108:tgl,dg1,adl-s */
> >> table = wa_1409767108_buddy_page_masks;
> >> else
> >>diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> >>b/drivers/gpu/drm/i915/display/intel_psr.c
> >>index 7c6e561f86c1..da5084b54eb6 100644
> >>--- a/drivers/gpu/drm/i915/display/intel_psr.c
> >>+++ b/drivers/gpu/drm/i915/display/intel_psr.c
> >>@@ -548,7 +548,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> >>
> >> if (intel_dp->psr.psr2_sel_fetch_enabled) {
> >> /* WA 1408330847 */
> >>- if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
> >>+ if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
> >
> > I always hated the DISP vs DISPLAY. It should be in the commit message.
> >
> > But if you are doing the s/STEPPING/STEP/, shouldn't the filename also use
> > step and all the functions/structs?
>
> To be honest, the rename came as an afterthought, after Aditya (I think)
> added the STEP_X enums.
>
> For me step everywhere sounds good, I wonder what the native speakers
> think.
IS_DISPLAY_STEPPING(STEP_X) is more flamboyant than
IS_DISPLAY_STEP(STEP_X), but we often make the concession for brevity
and in this case the consistency between macro and enum beats the
inconsistency in English. So STEP reads as a perfectly acceptable synonym
for STEPPING.
-Chris
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Re: [Intel-gfx] [PATCH v3] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9
On 05/03/2021 00:53, Chris Wilson wrote:
Quoting Chris Wilson (2021-03-04 11:56:16)
Quoting Chris Wilson (2021-03-04 09:19:24)
Quoting Tvrtko Ursulin (2021-03-04 09:12:26)
On 02/03/2021 06:27, Cooper Chiou wrote:
WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Gen9 to
resolve VP8 hardware encoding system hang up on GT1 sku for
ChromiumOS projects
Slice specific MMIO read inaccurate so MGSR needs to be programmed
appropriately to get correct reads from these slicet-related MMIOs.
It dictates that before any MMIO read into Slice/Subslice specific
registers, MCR packet control register(0xFDC) needs to be programmed
to point to any enabled slice/subslice pair, especially GT1 fused sku
since this issue can be reproduced on VP8 hardware encoding via ffmpeg
on ChromiumOS devices.
When exit PC7, MGSR will reset so that we have to skip fused subslice ID.
Reference: HSD#1508045018,1405586840, BSID#0575
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Cc: William Tseng
Cc: Lee Shawn C
Signed-off-by: Cooper Chiou
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 38 +
1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3b4a7da60f0b..4ad598a727a6 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -878,9 +878,47 @@ hsw_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME);
}
+static void
+gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+ const struct sseu_dev_info *sseu = >gt.info.sseu;
+ unsigned int slice, subslice;
+ u32 mcr, mcr_mask;
+
+ GEM_BUG_ON(INTEL_GEN(i915) < 9);
+
+ /*
+ * WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml
+ * Before any MMIO read into slice/subslice specific registers, MCR
+ * packet control register needs to be programmed to point to any
+ * enabled s/ss pair. Otherwise, incorrect values will be returned.
+ * This means each subsequent MMIO read will be forwarded to an
+ * specific s/ss combination, but this is OK since these registers
+ * are consistent across s/ss in almost all cases. In the rare
+ * occasions, such as INSTDONE, where this value is dependent
+ * on s/ss combo, the read should be done with read_subslice_reg.
+ */
+ slice = fls(sseu->slice_mask) - 1;
+ GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
+ subslice = fls(intel_sseu_get_subslices(sseu, slice));
+ GEM_BUG_ON(!subslice);
+ subslice--;
+
+ mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+ mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
+
+ drm_dbg(>drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice,
mcr);
+
+ wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
+}
Have you considered reusing existing wa_init_mcr? Just needs the
top-level assert changed and otherwise it looks it would do the right
thing for Gen9. Advantage being a smaller patch and less code to carry.
That was the first patch, and fails for the same reason. The problem
would appear to be in the mcr_mask for gt3.
For the record, it appears to be an issue with fls vs ffs. Switching to
ffs also removes the warnings for workaround failures on ehl/jsl.
Of course the icl in farm2 started spewing warnigns, but the other icl
in farm1 were happy.
It figures yes, now I remember it was the shards which had a mix of ICL
GT1/2 with different fusing which were exhibiting odd behaviour.
I have old patches around which a) try to program each WA in unicast
mode (for all present ss), b) do verification for each present ss. Idea
being to see if there are any patterns as to what writes land and which
get lost. I don't think the results were conclusive back then but maybe
I can try again.
I am not sure if PC8 and DMC could also be involved from what Cooper was
saying in a different thread. Maybe another CI run without the DMC, both
ffs and fls. Another for limiting cstates.
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH 0/4] drm/i915: Silence pipe tracepoint WARNs
On Thu, 04 Mar 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> I believe this should silence the WARN spew from the
> pipe disable tracepoint Steve reported. And I tossed in
> a few other minor improvements as well.
On some of the patches I'll just have to take your word for what it says
in the commit messages, but the patches do what they say. On the series,
Reviewed-by: Jani Nikula
>
> Cc: Steven Rostedt
>
> Ville Syrjälä (4):
> drm/i915: Move pipe enable/disable tracepoints to
> intel_crtc_vblank_{on,off}()
> drm/i915: Don't try to query the frame counter for disabled pipes
> drm/i915: Return zero as the scanline counter for disabled pipes
> drm/i915: Fix DSI TE max_vblank_count handling
>
> drivers/gpu/drm/i915/display/intel_crtc.c| 24 +---
> drivers/gpu/drm/i915/display/intel_display.c | 8 +--
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> 3 files changed, 23 insertions(+), 11 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center
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