[Intel-gfx] [PATCH v4 16/17] drm/i915/pxp: black pixels on pxp disabled
From: Anshuman Gupta
When protected sufaces has flipped and pxp session is disabled,
display black pixels by using plane color CTM correction.
v2:
- Display black pixels in async flip too.
v3:
- Removed the black pixels logic for async flip. [Ville]
- Used plane state to force black pixels. [Ville]
v4 (Daniele): update pxp_is_borked check.
Cc: Ville Syrjälä
Cc: Gaurav Kumar
Cc: Shankar Uma
Signed-off-by: Anshuman Gupta
Signed-off-by: Daniele Ceraolo Spurio
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 13 +-
.../drm/i915/display/intel_display_types.h| 3 ++
.../drm/i915/display/skl_universal_plane.c| 36 ++-
drivers/gpu/drm/i915/i915_reg.h | 46 +++
4 files changed, 95 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 88b3272c0b00..44d7a5072090 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -392,6 +392,11 @@ static int bo_has_valid_encryption(const struct
drm_i915_gem_object *obj)
intel_pxp_is_active(>gt.pxp);
}
+static bool pxp_is_borked(const struct drm_i915_gem_object *obj)
+{
+ return i915_gem_object_is_protected(obj) &&
!bo_has_valid_encryption(obj);
+}
+
int intel_plane_atomic_check(struct intel_atomic_state *state,
struct intel_plane *plane)
{
@@ -424,10 +429,14 @@ int intel_plane_atomic_check(struct intel_atomic_state
*state,
crtc);
fb = new_plane_state->hw.fb;
- if (fb)
+ if (fb) {
new_plane_state->decrypt =
bo_has_valid_encryption(intel_fb_obj(fb));
- else
+ new_plane_state->force_black = pxp_is_borked(intel_fb_obj(fb));
+
+ } else {
new_plane_state->decrypt = old_plane_state->decrypt;
+ new_plane_state->force_black = old_plane_state->force_black;
+ }
new_plane_state->uapi.visible = false;
if (!new_crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6b5dab9e1c40..88c0b882b844 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -624,6 +624,9 @@ struct intel_plane_state {
/* Plane pxp decryption state */
bool decrypt;
+ /* Plane state to display black pixels when pxp is borked */
+ bool force_black;
+
/* plane control register */
u32 ctl;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 2c8e88e8ad83..d4eb43b96ffd 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -975,6 +975,33 @@ static u32 skl_surf_address(const struct intel_plane_state
*plane_state,
}
}
+static void intel_load_plane_csc_black(struct intel_plane *intel_plane)
+{
+ struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
+ enum pipe pipe = intel_plane->pipe;
+ enum plane_id plane = intel_plane->id;
+ u16 postoff = 0;
+
+ drm_dbg_kms(_priv->drm, "plane color CTM to black %s:%d\n",
+ intel_plane->base.name, plane);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 0), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 1), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 2), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 3), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 4), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 5), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 0), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 1), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 2), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 0), postoff);
+ intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 1), postoff);
+ intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 2), postoff);
+}
+
static void
skl_program_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -1088,14 +1115,21 @@ skl_program_plane(struct intel_plane *plane,
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
+ plane_color_ctl = intel_de_read_fw(dev_priv, PLANE_COLOR_CTL(pipe,
plane_id));
/*
* FIXME: pxp session invalidation can hit any time even at time of
commit
* or after the commit, display content will be garbage.
*/
- if (plane_state->decrypt)
+ if
[Intel-gfx] [PATCH v4 15/17] drm/i915/pxp: Add plane decryption support
From: Anshuman Gupta
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PXP session is enabled.
2. Buffer object is protected.
v2:
- Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
v3:
- intel_pxp_gem_object_status() API changes.
v4: use intel_pxp_is_active (Daniele)
v5: rebase and use the new protected object status checker (Daniele)
v6: used plane state for plane_decryption to handle async flip
as suggested by Ville.
v7: check pxp session while plane decrypt state computation. [Ville]
removed pointless code. [Ville]
v8 (Daniele): update PXP check
Cc: Bommu Krishnaiah
Cc: Huang Sean Z
Cc: Gaurav Kumar
Cc: Ville Syrjälä
Signed-off-by: Anshuman Gupta
Signed-off-by: Daniele Ceraolo Spurio
---
.../gpu/drm/i915/display/intel_atomic_plane.c| 16
drivers/gpu/drm/i915/display/intel_display.c | 4
.../gpu/drm/i915/display/intel_display_types.h | 3 +++
.../gpu/drm/i915/display/skl_universal_plane.c | 15 ---
drivers/gpu/drm/i915/i915_reg.h | 1 +
5 files changed, 36 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 36f52a1d7552..88b3272c0b00 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -41,6 +41,7 @@
#include "intel_display_types.h"
#include "intel_pm.h"
#include "intel_sprite.h"
+#include "pxp/intel_pxp.h"
static void intel_plane_state_reset(struct intel_plane_state *plane_state,
struct intel_plane *plane)
@@ -383,6 +384,14 @@ intel_crtc_get_plane(struct intel_crtc *crtc, enum
plane_id plane_id)
return NULL;
}
+static int bo_has_valid_encryption(const struct drm_i915_gem_object *obj)
+{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+
+ return i915_gem_object_has_valid_protection(obj) &&
+ intel_pxp_is_active(>gt.pxp);
+}
+
int intel_plane_atomic_check(struct intel_atomic_state *state,
struct intel_plane *plane)
{
@@ -397,6 +406,7 @@ int intel_plane_atomic_check(struct intel_atomic_state
*state,
intel_atomic_get_old_crtc_state(state, crtc);
struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
+ const struct drm_framebuffer *fb;
if (new_crtc_state && new_crtc_state->bigjoiner_slave) {
struct intel_plane *master_plane =
@@ -413,6 +423,12 @@ int intel_plane_atomic_check(struct intel_atomic_state
*state,
new_master_plane_state,
crtc);
+ fb = new_plane_state->hw.fb;
+ if (fb)
+ new_plane_state->decrypt =
bo_has_valid_encryption(intel_fb_obj(fb));
+ else
+ new_plane_state->decrypt = old_plane_state->decrypt;
+
new_plane_state->uapi.visible = false;
if (!new_crtc_state)
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 0bb2e582c87f..f7f5374114ad 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9767,6 +9767,10 @@ static int intel_atomic_check_async(struct
intel_atomic_state *state)
drm_dbg_kms(>drm, "Color range cannot be changed
in async flip\n");
return -EINVAL;
}
+
+ /* plane decryption is allow to change only in synchronous
flips */
+ if (old_plane_state->decrypt != new_plane_state->decrypt)
+ return -EINVAL;
}
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index ce05475ad560..6b5dab9e1c40 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -621,6 +621,9 @@ struct intel_plane_state {
struct intel_fb_view view;
+ /* Plane pxp decryption state */
+ bool decrypt;
+
/* plane control register */
u32 ctl;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 59e032f3687a..2c8e88e8ad83 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -18,6 +18,7 @@
#include "intel_sprite.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
+#include "pxp/intel_pxp.h"
static const u32 skl_plane_formats[] = {
DRM_FORMAT_C8,
@@ -997,7 +998,7 @@ skl_program_plane(struct intel_plane *plane,
u8 alpha = plane_state->hw.alpha >> 8;
u32
[Intel-gfx] [PATCH v4 14/17] drm/i915/pxp: User interface for Protected buffer
From: Bommu Krishnaiah
This api allow user mode to create Protected buffers. Only contexts
marked as protected are allowed to operate on protected buffers.
We only allow setting the flags at creation time.
All protected objects that have backing storage will be considered
invalid when the session is destroyed and they won't be usable anymore.
Given that the PXP HW supports multiple modes (but we currently only
care about one), a flag variable has been reserved in the structure
used in the create_ext ioctl for possible future updates.
This is a rework of the original code by Bommu Krishnaiah. I've kept
authorship unchanged since significant chunks have not been modified.
v2: split context changes, fix defines and improve documentation (Chris),
add object invalidation logic
v3: fix spinlock definition and usage, only validate objects when
they're first added to a context lut, only remove them once (Chris),
make protected context flag not mandatory in protected object execbuf
to avoid abuse (Lionel)
v4: rebase to new gem_create_ext
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Daniele Ceraolo Spurio
Cc: Telukuntla Sreedhar
Cc: Kondapally Kalyan
Cc: Gupta Anshuman
Cc: Huang Sean Z
Cc: Chris Wilson
Cc: Lionel Landwerlin
Cc: Jason Ekstrand
Cc: Daniel Vetter
---
drivers/gpu/drm/i915/gem/i915_gem_create.c| 26
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 15 +++
drivers/gpu/drm/i915/gem/i915_gem_object.c| 6 +++
drivers/gpu/drm/i915/gem/i915_gem_object.h| 12 ++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 13 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 41 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 13 ++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 5 +++
include/uapi/drm/i915_drm.h | 33 ++-
9 files changed, 163 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index 548ddf39d853..c14be3882c35 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -6,6 +6,7 @@
#include "gem/i915_gem_ioctls.h"
#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_region.h"
+#include "pxp/intel_pxp.h"
#include "i915_drv.h"
#include "i915_trace.h"
@@ -99,7 +100,11 @@ i915_gem_setup(struct drm_i915_gem_object *obj, u64 size)
GEM_BUG_ON(size != obj->base.size);
+ if (obj->user_flags & I915_GEM_OBJECT_PROTECTED)
+ intel_pxp_object_add(obj);
+
trace_i915_gem_object_create(obj);
+
return 0;
}
@@ -344,8 +349,29 @@ static int ext_set_placements(struct i915_user_extension
__user *base,
return set_placements(, data);
}
+static int ext_set_protected(struct i915_user_extension __user *base, void
*data)
+{
+ struct drm_i915_gem_create_ext_protected_content ext;
+ struct create_ext *ext_data = data;
+
+ if (copy_from_user(, base, sizeof(ext)))
+ return -EFAULT;
+
+ if (ext.flags)
+ return -EINVAL;
+
+ if (!intel_pxp_is_enabled(_data->i915->gt.pxp))
+ return -ENODEV;
+
+ ext_data->vanilla_object->user_flags |= I915_GEM_OBJECT_PROTECTED;
+
+ return 0;
+}
+
+
static const i915_user_extension_fn create_extensions[] = {
[I915_GEM_CREATE_EXT_MEMORY_REGIONS] = ext_set_placements,
+ [I915_GEM_CREATE_EXT_PROTECTED_CONTENT] = ext_set_protected,
};
/**
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index c08e28847064..5dd813d04a9f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -839,6 +839,21 @@ static struct i915_vma *eb_lookup_vma(struct
i915_execbuffer *eb, u32 handle)
if (unlikely(!obj))
return ERR_PTR(-ENOENT);
+ /*
+* If the user has opted-in for protected-object tracking, make
+* sure the object encryption can be used.
+* We only need to do this when the object is first used with
+* this context, because the context itself will be banned when
+* the protected objects become invalid.
+*/
+ if (i915_gem_context_uses_protected_content(eb->gem_context) &&
+ i915_gem_object_is_protected(obj)) {
+ if (!intel_pxp_is_active(>gt->pxp))
+ return ERR_PTR(-ENODEV);
+ if (!i915_gem_object_has_valid_protection(obj))
+ return ERR_PTR(-ENOEXEC);
+ }
+
vma = i915_vma_instance(obj, vm, NULL);
if (IS_ERR(vma)) {
i915_gem_object_put(obj);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
[Intel-gfx] [PATCH v4 17/17] drm/i915/pxp: enable PXP for integrated Gen12
Note that discrete cards can support PXP as well, but we haven't tested
on those yet so keeping it disabled for now.
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 97c98f4fb265..23f249797ad8 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -884,6 +884,7 @@ static const struct intel_device_info jsl_info = {
}, \
TGL_CURSOR_OFFSETS, \
.has_global_mocs = 1, \
+ .has_pxp = 1, \
.display.has_dsb = 1
static const struct intel_device_info tgl_info = {
@@ -911,6 +912,7 @@ static const struct intel_device_info rkl_info = {
.memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \
.has_master_unit_irq = 1, \
.has_llc = 0, \
+ .has_pxp = 0, \
.has_snoop = 1, \
.is_dgfx = 1
--
2.29.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 12/17] drm/i915/pxp: start the arb session on demand
Now that we can handle destruction and re-creation of the arb session,
we can postpone the start of the session to the first submission that
requires it, to avoid keeping it running with no user.
Signed-off-by: Daniele Ceraolo Spurio
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 8 ++--
drivers/gpu/drm/i915/pxp/intel_pxp.c | 37 ---
drivers/gpu/drm/i915/pxp/intel_pxp.h | 4 +-
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 2 +-
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 6 +--
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 10 +
drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 3 ++
7 files changed, 39 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index a11e9d5767bf..c08e28847064 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2948,9 +2948,11 @@ eb_select_engine(struct i915_execbuffer *eb)
intel_gt_pm_get(ce->engine->gt);
if (i915_gem_context_uses_protected_content(eb->gem_context)) {
- err = intel_pxp_wait_for_arb_start(>engine->gt->pxp);
- if (err)
- goto err;
+ if (!intel_pxp_is_active(>engine->gt->pxp)) {
+ err = intel_pxp_start(>engine->gt->pxp);
+ if (err)
+ goto err;
+ }
if (i915_gem_context_invalidated(eb->gem_context)) {
err = -EACCES;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index f713d3423cea..2291c68fd3a0 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -77,6 +77,7 @@ void intel_pxp_init(struct intel_pxp *pxp)
init_completion(>termination);
complete_all(>termination);
+ mutex_init(>arb_mutex);
INIT_WORK(>session_work, intel_pxp_session_work);
ret = create_vcs_context(pxp);
@@ -113,7 +114,7 @@ void intel_pxp_mark_termination_in_progress(struct
intel_pxp *pxp)
reinit_completion(>termination);
}
-static void intel_pxp_queue_termination(struct intel_pxp *pxp)
+static void pxp_queue_termination(struct intel_pxp *pxp)
{
struct intel_gt *gt = pxp_to_gt(pxp);
@@ -132,31 +133,41 @@ static void intel_pxp_queue_termination(struct intel_pxp
*pxp)
* the arb session is restarted from the irq work when we receive the
* termination completion interrupt
*/
-int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp)
+int intel_pxp_start(struct intel_pxp *pxp)
{
+ int ret = 0;
+
if (!intel_pxp_is_enabled(pxp))
- return 0;
+ return -ENODEV;
+
+ mutex_lock(>arb_mutex);
+
+ if (pxp->arb_is_valid)
+ goto unlock;
+
+ pxp_queue_termination(pxp);
if (!wait_for_completion_timeout(>termination,
-msecs_to_jiffies(100)))
- return -ETIMEDOUT;
+ msecs_to_jiffies(100))) {
+ ret = -ETIMEDOUT;
+ goto unlock;
+ }
+
+ /* make sure the compiler doesn't optimize the double access */
+ barrier();
if (!pxp->arb_is_valid)
- return -EIO;
+ ret = -EIO;
- return 0;
+unlock:
+ mutex_unlock(>arb_mutex);
+ return ret;
}
void intel_pxp_init_hw(struct intel_pxp *pxp)
{
kcr_pxp_enable(pxp_to_gt(pxp));
intel_pxp_irq_enable(pxp);
-
- /*
-* the session could've been attacked while we weren't loaded, so
-* handle it as if it was and re-create it.
-*/
- intel_pxp_queue_termination(pxp);
}
void intel_pxp_fini_hw(struct intel_pxp *pxp)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 91c1a2056309..1f9871e64096 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -32,7 +32,7 @@ void intel_pxp_init_hw(struct intel_pxp *pxp);
void intel_pxp_fini_hw(struct intel_pxp *pxp);
void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp);
-int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp);
+int intel_pxp_start(struct intel_pxp *pxp);
void intel_pxp_invalidate(struct intel_pxp *pxp);
#else
static inline void intel_pxp_init(struct intel_pxp *pxp)
@@ -43,7 +43,7 @@ static inline void intel_pxp_fini(struct intel_pxp *pxp)
{
}
-static inline int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp)
+static inline int intel_pxp_start(struct intel_pxp *pxp)
{
return 0;
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
index 196449243515..a230d0034e50 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
@@ -31,7 +31,7 @@ void
[Intel-gfx] [PATCH v4 13/17] drm/i915/pxp: Enable PXP power management
From: "Huang, Sean Z"
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
session state might still be marked as alive after resume. Therefore,
we should consider the session as dead on suspend and invalidate all the
objects. The session will be automatically restarted on the first
protected submission on resume.
v2: runtime suspend also invalidates the keys
v3: fix return codes, simplify rpm ops (Chris), use the new worker func
v4: invalidate the objects on suspend, don't re-create the arb sesson on
resume (delayed to first submission).
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gt_pm.c| 15 +++-
drivers/gpu/drm/i915/i915_drv.c | 2 +
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 11 --
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 40
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 23 +++
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 38 ++-
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 9 +
8 files changed, 124 insertions(+), 15 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 29331bbb3e98..9cce0bf9a50f 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -278,6 +278,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_cmd.o \
pxp/intel_pxp_irq.o \
+ pxp/intel_pxp_pm.o \
pxp/intel_pxp_session.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index aef3084e8b16..91151a02f7a2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -19,6 +19,7 @@
#include "intel_rc6.h"
#include "intel_rps.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_pm.h"
static void user_forcewake(struct intel_gt *gt, bool suspend)
{
@@ -265,6 +266,8 @@ int intel_gt_resume(struct intel_gt *gt)
intel_uc_resume(>uc);
+ intel_pxp_resume(>pxp);
+
user_forcewake(gt, false);
out_fw:
@@ -299,6 +302,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
user_forcewake(gt, true);
wait_for_suspend(gt);
+ intel_pxp_suspend(>pxp);
intel_uc_suspend(>uc);
}
@@ -349,6 +353,7 @@ void intel_gt_suspend_late(struct intel_gt *gt)
void intel_gt_runtime_suspend(struct intel_gt *gt)
{
+ intel_pxp_suspend(>pxp);
intel_uc_runtime_suspend(>uc);
GT_TRACE(gt, "\n");
@@ -356,11 +361,19 @@ void intel_gt_runtime_suspend(struct intel_gt *gt)
int intel_gt_runtime_resume(struct intel_gt *gt)
{
+ int ret;
+
GT_TRACE(gt, "\n");
intel_gt_init_swizzling(gt);
intel_ggtt_restore_fences(gt->ggtt);
- return intel_uc_runtime_resume(>uc);
+ ret = intel_uc_runtime_resume(>uc);
+ if (ret)
+ return ret;
+
+ intel_pxp_resume(>pxp);
+
+ return 0;
}
static ktime_t __intel_gt_get_awake_time(const struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2f06bb7b3ed2..6543e5577709 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -68,6 +68,8 @@
#include "gt/intel_gt_pm.h"
#include "gt/intel_rc6.h"
+#include "pxp/intel_pxp_pm.h"
+
#include "i915_debugfs.h"
#include "i915_drv.h"
#include "i915_ioc32.h"
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
index a230d0034e50..9e5847c653f2 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
@@ -9,6 +9,7 @@
#include "gt/intel_gt_irq.h"
#include "i915_irq.h"
#include "i915_reg.h"
+#include "intel_runtime_pm.h"
/**
* intel_pxp_irq_handler - Handles PXP interrupts.
@@ -62,11 +63,13 @@ void intel_pxp_irq_enable(struct intel_pxp *pxp)
struct intel_gt *gt = pxp_to_gt(pxp);
spin_lock_irq(>irq_lock);
- if (!pxp->irq_enabled) {
+
+ if (!pxp->irq_enabled)
WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_KCR));
- __pxp_set_interrupts(gt, GEN12_PXP_INTERRUPTS);
- pxp->irq_enabled = true;
- }
+
+ __pxp_set_interrupts(gt, GEN12_PXP_INTERRUPTS);
+ pxp->irq_enabled = true;
+
spin_unlock_irq(>irq_lock);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
new file mode 100644
index ..400b3a9944c8
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
[Intel-gfx] [PATCH v4 11/17] drm/i915/pxp: interface for marking contexts as using protected content
Extra tracking and checks around protected objects, coming in a follow-up
patch, will be enabled only for contexts that opt in. Contexts can only be
marked as using protected content at creation time and they must be both
bannable and not recoverable.
When a PXP teardown occurs, all gem contexts marked this way that
have been used at least once will be marked as invalid and all new
submissions using them will be rejected. All intel contexts within the
invalidated gem contexts will be marked banned.
A new flag has been added to the RESET_STATS ioctl to report the
invalidation to userspace.
v2: split to its own patch and improve doc (Chris), invalidate contexts
on teardown
v3: improve doc, use -EACCES for execbuf fail (Chris), make protected
context flag not mandatory in protected object execbuf to avoid
abuse (Lionel)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Lionel Landwerlin
Cc: Jason Ekstrand
Cc: Daniel Vetter
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 59 ++-
drivers/gpu/drm/i915/gem/i915_gem_context.h | 18 ++
.../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 18 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 48 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 3 +
include/uapi/drm/i915_drm.h | 26
8 files changed, 172 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 188dee13e017..11b67f1f6e96 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -76,6 +76,8 @@
#include "gt/intel_gpu_commands.h"
#include "gt/intel_ring.h"
+#include "pxp/intel_pxp.h"
+
#include "i915_gem_context.h"
#include "i915_globals.h"
#include "i915_trace.h"
@@ -1971,6 +1973,40 @@ static int set_priority(struct i915_gem_context *ctx,
return 0;
}
+static int set_protected(struct i915_gem_context *ctx,
+const struct drm_i915_gem_context_param *args)
+{
+ int ret = 0;
+
+ if (!intel_pxp_is_enabled(>i915->gt.pxp))
+ ret = -ENODEV;
+ else if (ctx->file_priv) /* can't change this after creation! */
+ ret = -EEXIST;
+ else if (args->size)
+ ret = -EINVAL;
+ else if (!args->value)
+ clear_bit(UCONTEXT_PROTECTED, >user_flags);
+ else if (i915_gem_context_is_recoverable(ctx) ||
+!i915_gem_context_is_bannable(ctx))
+ ret = -EPERM;
+ else
+ set_bit(UCONTEXT_PROTECTED, >user_flags);
+
+ return ret;
+}
+
+static int get_protected(struct i915_gem_context *ctx,
+struct drm_i915_gem_context_param *args)
+{
+ if (!intel_pxp_is_enabled(>i915->gt.pxp))
+ return -ENODEV;
+
+ args->size = 0;
+ args->value = i915_gem_context_uses_protected_content(ctx);
+
+ return 0;
+}
+
static int ctx_setparam(struct drm_i915_file_private *fpriv,
struct i915_gem_context *ctx,
struct drm_i915_gem_context_param *args)
@@ -2003,6 +2039,8 @@ static int ctx_setparam(struct drm_i915_file_private
*fpriv,
ret = -EPERM;
else if (args->value)
i915_gem_context_set_bannable(ctx);
+ else if (i915_gem_context_uses_protected_content(ctx))
+ ret = -EPERM; /* can't clear this for protected
contexts */
else
i915_gem_context_clear_bannable(ctx);
break;
@@ -2010,10 +2048,12 @@ static int ctx_setparam(struct drm_i915_file_private
*fpriv,
case I915_CONTEXT_PARAM_RECOVERABLE:
if (args->size)
ret = -EINVAL;
- else if (args->value)
- i915_gem_context_set_recoverable(ctx);
- else
+ else if (!args->value)
i915_gem_context_clear_recoverable(ctx);
+ else if (i915_gem_context_uses_protected_content(ctx))
+ ret = -EPERM; /* can't set this for protected contexts
*/
+ else
+ i915_gem_context_set_recoverable(ctx);
break;
case I915_CONTEXT_PARAM_PRIORITY:
@@ -2040,6 +2080,10 @@ static int ctx_setparam(struct drm_i915_file_private
*fpriv,
ret = set_ringsize(ctx, args);
break;
+ case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ ret = set_protected(ctx, args);
+ break;
+
case I915_CONTEXT_PARAM_BAN_PERIOD:
default:
ret = -EINVAL;
@@ -2493,6 +2537,10 @@ int i915_gem_context_getparam_ioctl(struct drm_device
*dev, void *data,
ret = get_ringsize(ctx,
[Intel-gfx] [PATCH v4 05/17] drm/i915/pxp: allocate a vcs context for pxp usage
The context is required to send the session termination commands to the
VCS, which will be implemented in a follow-up patch. We can also use the
presence of the context as a check of pxp initialization completion.
v2: use perma-pinned context (Chris)
v3: rename pinned_context functions (Chris)
v4: split export of pinned_context functions to a separate patch (Rodrigo)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 4 ++
drivers/gpu/drm/i915/gt/intel_engine.h | 2 +
drivers/gpu/drm/i915/gt/intel_gt.c | 5 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 62 ++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 35
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 15 ++
7 files changed, 126 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 6947495bf34b..efd950122e40 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -273,6 +273,10 @@ i915-y += \
i915-y += i915_perf.o
+# Protected execution platform (PXP) support
+i915-$(CONFIG_DRM_I915_PXP) += \
+ pxp/intel_pxp.o
+
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
i915-$(CONFIG_DRM_I915_SELFTEST) += \
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index a64d28aba257..903e498beb0b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -187,6 +187,8 @@ intel_write_status_page(struct intel_engine_cs *engine, int
reg, u32 value)
#define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT * sizeof(u32))
#define I915_GEM_HWS_SEQNO 0x40
#define I915_GEM_HWS_SEQNO_ADDR(I915_GEM_HWS_SEQNO *
sizeof(u32))
+#define I915_GEM_HWS_PXP 0x60
+#define I915_GEM_HWS_PXP_ADDR (I915_GEM_HWS_PXP * sizeof(u32))
#define I915_GEM_HWS_SCRATCH 0x80
#define I915_HWS_CSB_BUF0_INDEX0x10
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 8d77dcbad059..68f42fabc151 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -20,6 +20,7 @@
#include "intel_uncore.h"
#include "intel_pm.h"
#include "shmem_utils.h"
+#include "pxp/intel_pxp.h"
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
{
@@ -627,6 +628,8 @@ int intel_gt_init(struct intel_gt *gt)
if (err)
goto err_gt;
+ intel_pxp_init(>pxp);
+
goto out_fw;
err_gt:
__intel_gt_disable(gt);
@@ -661,6 +664,8 @@ void intel_gt_driver_unregister(struct intel_gt *gt)
intel_rps_driver_unregister(>rps);
+ intel_pxp_fini(>pxp);
+
/*
* Upon unregistering the device to prevent any new users, cancel
* all in-flight requests so that we can quickly unbind the active
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 0caf6ca0a784..53f44fd4a974 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -25,6 +25,7 @@
#include "intel_rc6_types.h"
#include "intel_rps_types.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_types.h"
struct drm_i915_private;
struct i915_ggtt;
@@ -148,6 +149,8 @@ struct intel_gt {
/* Slice/subslice/EU info */
struct sseu_dev_info sseu;
} info;
+
+ struct intel_pxp pxp;
};
enum intel_gt_scratch_field {
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
new file mode 100644
index ..3255c6da34e8
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+#include "intel_pxp.h"
+#include "gt/intel_context.h"
+#include "i915_drv.h"
+
+static int create_vcs_context(struct intel_pxp *pxp)
+{
+ static struct lock_class_key pxp_lock;
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ struct intel_engine_cs *engine;
+ struct intel_context *ce;
+
+ /*
+* Find the first VCS engine present. We're guaranteed there is one
+* if we're in this function due to the check in has_pxp
+*/
+ for (engine = gt->engine_class[VIDEO_DECODE_CLASS][0]; !engine;
engine++);
+ GEM_BUG_ON(!engine || engine->class != VIDEO_DECODE_CLASS);
+
+ ce = intel_engine_create_pinned_context(engine, NULL, SZ_4K,
+ I915_GEM_HWS_PXP_ADDR,
+ _lock, "pxp_context");
+ if
[Intel-gfx] [PATCH v4 04/17] drm/i915/gt: Export the pinned context constructor and destructor
From: Chris Wilson
Allow internal clients to create a pinned context.
v2 (Daniele): export destructor as well, allow optional usage of custom
vm for maximum flexibility.
Signed-off-by: Chris Wilson
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_engine.h| 10
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 29 +++
2 files changed, 29 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index 47ee8578e511..a64d28aba257 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -18,7 +18,9 @@
#include "intel_workarounds.h"
struct drm_printer;
+struct intel_context;
struct intel_gt;
+struct lock_class_key;
/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
* but keeps the logic simple. Indeed, the whole purpose of this macro is just
@@ -255,6 +257,14 @@ struct i915_request *
intel_engine_find_active_request(struct intel_engine_cs *engine);
u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
+struct intel_context *
+intel_engine_create_pinned_context(struct intel_engine_cs *engine,
+ struct i915_address_space *vm,
+ unsigned int ring_size,
+ unsigned int hwsp,
+ struct lock_class_key *key,
+ const char *name);
+void intel_engine_destroy_pinned_context(struct intel_context *ce);
void intel_engine_init_active(struct intel_engine_cs *engine,
unsigned int subclass);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index eba2da9679a5..8cbf11497e8e 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -801,11 +801,13 @@ intel_engine_init_active(struct intel_engine_cs *engine,
unsigned int subclass)
#endif
}
-static struct intel_context *
-create_pinned_context(struct intel_engine_cs *engine,
- unsigned int hwsp,
- struct lock_class_key *key,
- const char *name)
+struct intel_context *
+intel_engine_create_pinned_context(struct intel_engine_cs *engine,
+ struct i915_address_space *vm,
+ unsigned int ring_size,
+ unsigned int hwsp,
+ struct lock_class_key *key,
+ const char *name)
{
struct intel_context *ce;
int err;
@@ -816,6 +818,12 @@ create_pinned_context(struct intel_engine_cs *engine,
__set_bit(CONTEXT_BARRIER_BIT, >flags);
ce->timeline = page_pack_bits(NULL, hwsp);
+ ce->ring = __intel_context_ring_size(ring_size);
+
+ if (vm) {
+ i915_vm_put(ce->vm);
+ ce->vm = i915_vm_get(vm);
+ }
err = intel_context_pin(ce); /* perma-pin so it is always available */
if (err) {
@@ -834,7 +842,7 @@ create_pinned_context(struct intel_engine_cs *engine,
return ce;
}
-static void destroy_pinned_context(struct intel_context *ce)
+void intel_engine_destroy_pinned_context(struct intel_context *ce)
{
struct intel_engine_cs *engine = ce->engine;
struct i915_vma *hwsp = engine->status_page.vma;
@@ -854,8 +862,9 @@ create_kernel_context(struct intel_engine_cs *engine)
{
static struct lock_class_key kernel;
- return create_pinned_context(engine, I915_GEM_HWS_SEQNO_ADDR,
-, "kernel_context");
+ return intel_engine_create_pinned_context(engine, NULL, SZ_4K,
+ I915_GEM_HWS_SEQNO_ADDR,
+ , "kernel_context");
}
/**
@@ -898,7 +907,7 @@ static int engine_init_common(struct intel_engine_cs
*engine)
return 0;
err_context:
- destroy_pinned_context(ce);
+ intel_engine_destroy_pinned_context(ce);
return ret;
}
@@ -956,7 +965,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs
*engine)
fput(engine->default_state);
if (engine->kernel_context)
- destroy_pinned_context(engine->kernel_context);
+ intel_engine_destroy_pinned_context(engine->kernel_context);
GEM_BUG_ON(!llist_empty(>barrier_tasks));
cleanup_status_page(engine);
--
2.29.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 08/17] drm/i915/pxp: Create the arbitrary session after boot
From: "Huang, Sean Z"
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session will need to be re-created after
teardown or power event because hardware encryption key won't be
valid after such cases.
The session ID is exposed as part of the uapi so it can be used as part
of userspace commands.
v2: use gt->uncore->rpm (Chris)
v3: s/arb_is_in_play/arb_is_valid (Chris), move set-up to the new
init_hw function
v4: move interface defs to separate header, set arb_is valid to false
on fini (Rodrigo)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 5 ++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 5 ++
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 74 +++
drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 15
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 68 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 3 +
.../drm/i915/pxp/intel_pxp_tee_interface.h| 37 ++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 9 +++
include/uapi/drm/i915_drm.h | 3 +
10 files changed, 220 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0dfff52fea24..739510549545 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -276,6 +276,7 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
+ pxp/intel_pxp_session.o \
pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index ab19d2a23ec2..4e30e5e98522 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -3,6 +3,7 @@
* Copyright(c) 2020 Intel Corporation.
*/
#include "intel_pxp.h"
+#include "intel_pxp_session.h"
#include "intel_pxp_tee.h"
#include "gt/intel_context.h"
#include "i915_drv.h"
@@ -86,6 +87,8 @@ void intel_pxp_fini(struct intel_pxp *pxp)
if (!intel_pxp_is_enabled(pxp))
return;
+ pxp->arb_is_valid = false;
+
intel_pxp_tee_component_fini(pxp);
destroy_vcs_context(pxp);
@@ -94,6 +97,8 @@ void intel_pxp_fini(struct intel_pxp *pxp)
void intel_pxp_init_hw(struct intel_pxp *pxp)
{
kcr_pxp_enable(pxp_to_gt(pxp));
+
+ intel_pxp_create_arb_session(pxp);
}
void intel_pxp_fini_hw(struct intel_pxp *pxp)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 5427c3b28aa9..8eeb65af78b1 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -19,6 +19,11 @@ static inline bool intel_pxp_is_enabled(const struct
intel_pxp *pxp)
return pxp->ce;
}
+static inline bool intel_pxp_is_active(const struct intel_pxp *pxp)
+{
+ return pxp->arb_is_valid;
+}
+
#ifdef CONFIG_DRM_I915_PXP
void intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_fini(struct intel_pxp *pxp);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
new file mode 100644
index ..3331868f354c
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "drm/i915_drm.h"
+#include "i915_drv.h"
+
+#include "intel_pxp.h"
+#include "intel_pxp_session.h"
+#include "intel_pxp_tee.h"
+#include "intel_pxp_types.h"
+
+#define ARB_SESSION I915_PROTECTED_CONTENT_DEFAULT_SESSION /* shorter define */
+
+#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */
+
+static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ intel_wakeref_t wakeref;
+ u32 sip = 0;
+
+ with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+ sip = intel_uncore_read(gt->uncore, GEN12_KCR_SIP);
+
+ return sip & BIT(id);
+}
+
+static int pxp_wait_for_session_state(struct intel_pxp *pxp, u32 id, bool
in_play)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ intel_wakeref_t wakeref;
+ u32 mask = BIT(id);
+ int ret;
+
+ with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+ ret = intel_wait_for_register(gt->uncore,
+
[Intel-gfx] [PATCH v4 01/17] drm/i915/pxp: Define PXP component interface
This will be used for communication between the i915 driver and the mei
one. Defining it in a stand-alone patch to avoid circualr dependedencies
between the patches modifying the 2 drivers.
Split out from an original patch from Huang, Sean Z
v2: rename the component struct (Rodrigo)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
---
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 45
2 files changed, 46 insertions(+)
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index 55c3b123581b..c1e2a43d2d1e 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -29,6 +29,7 @@
enum i915_component_type {
I915_COMPONENT_AUDIO = 1,
I915_COMPONENT_HDCP,
+ I915_COMPONENT_PXP
};
/* MAX_PORT is the number of port
diff --git a/include/drm/i915_pxp_tee_interface.h
b/include/drm/i915_pxp_tee_interface.h
new file mode 100644
index ..09b8389152af
--- /dev/null
+++ b/include/drm/i915_pxp_tee_interface.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Authors:
+ * Vitaly Lubart
+ */
+
+#ifndef _I915_PXP_TEE_INTERFACE_H_
+#define _I915_PXP_TEE_INTERFACE_H_
+
+#include
+#include
+
+/**
+ * struct i915_pxp_component_ops - ops for PXP services.
+ * @owner: Module providing the ops
+ * @send: sends data to PXP
+ * @receive: receives data from PXP
+ */
+struct i915_pxp_component_ops {
+ /**
+* @owner: owner of the module provding the ops
+*/
+ struct module *owner;
+
+ int (*send)(struct device *dev, const void *message, size_t size);
+ int (*recv)(struct device *dev, void *buffer, size_t size);
+};
+
+/**
+ * struct i915_pxp_component - Used for communication between i915 and TEE
+ * drivers for the PXP services
+ * @tee_dev: device that provide the PXP service from TEE Bus.
+ * @pxp_ops: Ops implemented by TEE driver, used by i915 driver.
+ */
+struct i915_pxp_component {
+ struct device *tee_dev;
+ const struct i915_pxp_component_ops *ops;
+
+ /* To protect the above members. */
+ struct mutex mutex;
+};
+
+#endif /* _I915_TEE_PXP_INTERFACE_H_ */
--
2.29.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 09/17] drm/i915/pxp: Implement arb session teardown
From: "Huang, Sean Z"
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. Additionally, we want to emit a
teardown operation to make sure we're clean on boot and resume
v2: emit in the ring, use high prio request (Chris)
v3: better defines, stalling flush, cleaned up and renamed submission
funcs (Chris)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 22 ++-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 7 +-
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 140 +++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 15 ++
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 29
drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 1 +
7 files changed, 211 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 739510549545..0fba97014512 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -276,6 +276,7 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
+ pxp/intel_pxp_cmd.o \
pxp/intel_pxp_session.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 2694dbb9967e..2eda14ea0162 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -28,10 +28,13 @@
#define INSTR_26_TO_24_MASK0x700
#define INSTR_26_TO_24_SHIFT 24
+#define __INSTR(client) ((client) << INSTR_CLIENT_SHIFT)
+
/*
* Memory interface instructions used by the kernel
*/
-#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
+#define MI_INSTR(opcode, flags) \
+ (__INSTR(INSTR_MI_CLIENT) | (opcode) << 23 | (flags))
/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
#define MI_GLOBAL_GTT(1<<22)
@@ -57,6 +60,7 @@
#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
#define MI_SUSPEND_FLUSH_EN (1<<0)
#define MI_SET_APPID MI_INSTR(0x0e, 0)
+#define MI_SET_APPID_SESSION_ID(x) ((x) << 0)
#define MI_OVERLAY_FLIPMI_INSTR(0x11, 0)
#define MI_OVERLAY_CONTINUE (0x0<<21)
#define MI_OVERLAY_ON(0x1<<21)
@@ -144,6 +148,7 @@
#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
#define MI_SRM_LRM_GLOBAL_GTT(1<<22)
#define MI_FLUSH_DWMI_INSTR(0x26, 1) /* for GEN6 */
+#define MI_FLUSH_DW_PROTECTED_MEM_EN (1<<22)
#define MI_FLUSH_DW_STORE_INDEX (1<<21)
#define MI_INVALIDATE_TLB(1<<18)
#define MI_FLUSH_DW_OP_STOREDW (1<<14)
@@ -270,6 +275,19 @@
#define MI_MATH_REG_ZF 0x32
#define MI_MATH_REG_CF 0x33
+/*
+ * Media instructions used by the kernel
+ */
+#define MEDIA_INSTR(pipe, op, sub_op, flags) \
+ (__INSTR(INSTR_RC_CLIENT) | (pipe) << INSTR_SUBCLIENT_SHIFT | \
+ (op) << INSTR_26_TO_24_SHIFT | (sub_op) << 16 | (flags))
+
+#define MFX_WAIT MEDIA_INSTR(1, 0, 0, 0)
+#define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAGREG_BIT(8)
+#define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAGREG_BIT(9)
+
+#define CRYPTO_KEY_EXCHANGEMEDIA_INSTR(2, 6, 9, 0)
+
/*
* Commands used only by the command parser
*/
@@ -326,8 +344,6 @@
#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
-#define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
-
#define COLOR_BLT ((0x2<<29)|(0x40<<22))
#define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 4e30e5e98522..e48debb5ca22 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -96,9 +96,14 @@ void intel_pxp_fini(struct intel_pxp *pxp)
void intel_pxp_init_hw(struct intel_pxp *pxp)
{
+ int ret;
+
kcr_pxp_enable(pxp_to_gt(pxp));
- intel_pxp_create_arb_session(pxp);
+ /* always emit a full termination to clean the state */
+ ret = intel_pxp_terminate_arb_session_and_global(pxp);
+ if (!ret)
+ intel_pxp_create_arb_session(pxp);
}
void intel_pxp_fini_hw(struct intel_pxp *pxp)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
new file mode 100644
index ..c577f1fbee55
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
[Intel-gfx] [PATCH v4 10/17] drm/i915/pxp: Implement PXP irq handler
From: "Huang, Sean Z"
The HW will generate a teardown interrupt when session termination is
required, which requires i915 to submit a terminating batch. Once the HW
is done with the termination it will generate another interrupt, at
which point it is safe to re-create the session.
Since the termination and re-creation flow is something we want to
trigger from the driver as well, use a common work function that can be
called both from the irq handler and from the driver set-up flows, which
has the addded benefit of allowing us to skip any extra locks because
the work itself serializes the operations.
v2: use struct completion instead of bool (Chris)
v3: drop locks, clean up functions and improve comments (Chris),
move to common work function.
v4: improve comments, simplify wait logic (Rodrigo)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 7 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 66 +++--
drivers/gpu/drm/i915/pxp/intel_pxp.h | 8 ++
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 97
drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 32 +++
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 54 ++-
drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 5 +-
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 8 +-
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 18
11 files changed, 281 insertions(+), 16 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0fba97014512..29331bbb3e98 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -277,6 +277,7 @@ i915-y += i915_perf.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_cmd.o \
+ pxp/intel_pxp_irq.o \
pxp/intel_pxp_session.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 9fc6c912a4e5..7c4ec8880b1a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -13,6 +13,7 @@
#include "intel_lrc_reg.h"
#include "intel_uncore.h"
#include "intel_rps.h"
+#include "pxp/intel_pxp_irq.h"
static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
@@ -106,6 +107,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8
instance,
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(>rps, iir);
+ if (instance == OTHER_KCR_INSTANCE)
+ return intel_pxp_irq_handler(>pxp, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
@@ -232,6 +236,9 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0);
+
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, 0);
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~0);
}
void gen11_gt_irq_postinstall(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4dbe79009c0e..297671d78076 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8023,6 +8023,7 @@ enum {
/* irq instances for OTHER_CLASS */
#define OTHER_GUC_INSTANCE 0
#define OTHER_GTPM_INSTANCE1
+#define OTHER_KCR_INSTANCE 4
#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index e48debb5ca22..6b0e7170c29b 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -2,7 +2,9 @@
/*
* Copyright(c) 2020 Intel Corporation.
*/
+#include
#include "intel_pxp.h"
+#include "intel_pxp_irq.h"
#include "intel_pxp_session.h"
#include "intel_pxp_tee.h"
#include "gt/intel_context.h"
@@ -66,6 +68,16 @@ void intel_pxp_init(struct intel_pxp *pxp)
if (!HAS_PXP(gt->i915))
return;
+ /*
+* we'll use the completion to check if there is a termination pending,
+* so we start it as completed and we reinit it when a termination
+* is triggered.
+*/
+ init_completion(>termination);
+ complete_all(>termination);
+
+ INIT_WORK(>session_work, intel_pxp_session_work);
+
ret = create_vcs_context(pxp);
if (ret)
return;
@@ -94,19 +106,61 @@ void intel_pxp_fini(struct intel_pxp *pxp)
destroy_vcs_context(pxp);
}
-void intel_pxp_init_hw(struct intel_pxp
[Intel-gfx] [PATCH v4 06/17] drm/i915/pxp: Implement funcs to create the TEE channel
From: "Huang, Sean Z"
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(default) session.
v2: fix locking, don't pollute dev_priv (Chris)
v3: wait for mei PXP component to be bound.
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Reviewed-by: Rodrigo Vivi #v2
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 13
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 87 ++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 3 +
5 files changed, 119 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index efd950122e40..0dfff52fea24 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -275,7 +275,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
- pxp/intel_pxp.o
+ pxp/intel_pxp.o \
+ pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 3255c6da34e8..5df2a09c9e4b 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -3,6 +3,7 @@
* Copyright(c) 2020 Intel Corporation.
*/
#include "intel_pxp.h"
+#include "intel_pxp_tee.h"
#include "gt/intel_context.h"
#include "i915_drv.h"
@@ -50,7 +51,16 @@ void intel_pxp_init(struct intel_pxp *pxp)
if (ret)
return;
+ ret = intel_pxp_tee_component_init(pxp);
+ if (ret)
+ goto out_context;
+
drm_info(>i915->drm, "Protected Xe Path (PXP) protected content
support initialized\n");
+
+ return;
+
+out_context:
+ destroy_vcs_context(pxp);
}
void intel_pxp_fini(struct intel_pxp *pxp)
@@ -58,5 +68,8 @@ void intel_pxp_fini(struct intel_pxp *pxp)
if (!intel_pxp_is_enabled(pxp))
return;
+ intel_pxp_tee_component_fini(pxp);
+
destroy_vcs_context(pxp);
+
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
new file mode 100644
index ..4ed234d8584f
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include
+#include "drm/i915_pxp_tee_interface.h"
+#include "drm/i915_component.h"
+#include "i915_drv.h"
+#include "intel_pxp.h"
+#include "intel_pxp_tee.h"
+
+static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev)
+{
+ return _to_i915(i915_kdev)->gt.pxp;
+}
+
+/**
+ * i915_pxp_tee_component_bind - bind function to pass the function pointers
to pxp_tee
+ * @i915_kdev: pointer to i915 kernel device
+ * @tee_kdev: pointer to tee kernel device
+ * @data: pointer to pxp_tee_master containing the function pointers
+ *
+ * This bind function is called during the system boot or resume from system
sleep.
+ *
+ * Return: return 0 if successful.
+ */
+static int i915_pxp_tee_component_bind(struct device *i915_kdev,
+ struct device *tee_kdev, void *data)
+{
+ struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
+
+ pxp->pxp_component = data;
+ pxp->pxp_component->tee_dev = tee_kdev;
+
+ return 0;
+}
+
+static void i915_pxp_tee_component_unbind(struct device *i915_kdev,
+ struct device *tee_kdev, void *data)
+{
+ struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
+
+ pxp->pxp_component = NULL;
+}
+
+static const struct component_ops i915_pxp_tee_component_ops = {
+ .bind = i915_pxp_tee_component_bind,
+ .unbind = i915_pxp_tee_component_unbind,
+};
+
+int intel_pxp_tee_component_init(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ struct drm_i915_private *i915 = gt->i915;
+
+ ret = component_add_typed(i915->drm.dev, _pxp_tee_component_ops,
+ I915_COMPONENT_PXP);
+ if (ret < 0) {
+ drm_err(>drm, "Failed to add PXP component (%d)\n", ret);
+ return ret;
+ }
+
+ /*
+* Adding the component does not guarantee that it will bind properly,
+* so make sure to wait until it does.
+*/
+ ret = wait_for(pxp->pxp_component, 50);
+ if (ret) {
+ drm_err(>drm, "Failed to bind PXP component (%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+void intel_pxp_tee_component_fini(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+
[Intel-gfx] [PATCH v4 07/17] drm/i915/pxp: set KCR reg init
The setting is required by hardware to allow us doing further protection
operation such as sending commands to GPU or TEE. The register needs to
be re-programmed on resume, so for simplicitly we bundle the programming
with the component binding, which is automatically called on resume.
Further HW set-up operations will be added in the same location in
follow-up patches, so get ready for them by using a couple of
init/fini_hw wrappers instead of calling the KCR funcs directly.
v3: move programming to component binding function, rework commit msg
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 27
drivers/gpu/drm/i915/pxp/intel_pxp.h | 3 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 5 +
3 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 5df2a09c9e4b..ab19d2a23ec2 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -7,6 +7,24 @@
#include "gt/intel_context.h"
#include "i915_drv.h"
+/* KCR register definitions */
+#define KCR_INIT _MMIO(0x320f0)
+
+/* Setting KCR Init bit is required after system boot */
+#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14)
+
+static void kcr_pxp_enable(struct intel_gt *gt)
+{
+ intel_uncore_write(gt->uncore, KCR_INIT,
+
_MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES));
+}
+
+static void kcr_pxp_disable(struct intel_gt *gt)
+{
+ intel_uncore_write(gt->uncore, KCR_INIT,
+
_MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES));
+}
+
static int create_vcs_context(struct intel_pxp *pxp)
{
static struct lock_class_key pxp_lock;
@@ -71,5 +89,14 @@ void intel_pxp_fini(struct intel_pxp *pxp)
intel_pxp_tee_component_fini(pxp);
destroy_vcs_context(pxp);
+}
+
+void intel_pxp_init_hw(struct intel_pxp *pxp)
+{
+ kcr_pxp_enable(pxp_to_gt(pxp));
+}
+void intel_pxp_fini_hw(struct intel_pxp *pxp)
+{
+ kcr_pxp_disable(pxp_to_gt(pxp));
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index e87550fb9821..5427c3b28aa9 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -22,6 +22,9 @@ static inline bool intel_pxp_is_enabled(const struct
intel_pxp *pxp)
#ifdef CONFIG_DRM_I915_PXP
void intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_fini(struct intel_pxp *pxp);
+
+void intel_pxp_init_hw(struct intel_pxp *pxp);
+void intel_pxp_fini_hw(struct intel_pxp *pxp);
#else
static inline void intel_pxp_init(struct intel_pxp *pxp)
{
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index 4ed234d8584f..dc0dcd040bf8 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -33,6 +33,9 @@ static int i915_pxp_tee_component_bind(struct device
*i915_kdev,
pxp->pxp_component = data;
pxp->pxp_component->tee_dev = tee_kdev;
+ /* the component is required to fully start the PXP HW */
+ intel_pxp_init_hw(pxp);
+
return 0;
}
@@ -41,6 +44,8 @@ static void i915_pxp_tee_component_unbind(struct device
*i915_kdev,
{
struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
+ intel_pxp_fini_hw(pxp);
+
pxp->pxp_component = NULL;
}
--
2.29.2
___
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[Intel-gfx] [PATCH v4 02/17] mei: pxp: export pavp client to me client bus
From: Vitaly Lubart
Export PAVP client to work with i915 driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig | 13 ++
drivers/misc/mei/pxp/Makefile | 7 +
drivers/misc/mei/pxp/mei_pxp.c | 233 +
drivers/misc/mei/pxp/mei_pxp.h | 18 +++
6 files changed, 274 insertions(+)
create mode 100644 drivers/misc/mei/pxp/Kconfig
create mode 100644 drivers/misc/mei/pxp/Makefile
create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index f5fd5b786607..0e0bcd0da852 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -47,3 +47,5 @@ config INTEL_MEI_TXE
Intel Bay Trail
source "drivers/misc/mei/hdcp/Kconfig"
+source "drivers/misc/mei/pxp/Kconfig"
+
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index f1c76f7ee804..d8e5165917f2 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -26,3 +26,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o
CFLAGS_mei-trace.o = -I$(src)
obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
+obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig
new file mode 100644
index ..4029b96afc04
--- /dev/null
+++ b/drivers/misc/mei/pxp/Kconfig
@@ -0,0 +1,13 @@
+
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+config INTEL_MEI_PXP
+ tristate "Intel PXP services of ME Interface"
+ select INTEL_MEI_ME
+ depends on DRM_I915
+ help
+ MEI Support for PXP Services on Intel platforms.
+
+ Enables the ME FW services required for PXP support through
+ I915 display driver of Intel.
diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile
new file mode 100644
index ..0329950d5794
--- /dev/null
+++ b/drivers/misc/mei/pxp/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+# Makefile - PXP client driver for Intel MEI Bus Driver.
+
+obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
new file mode 100644
index ..cacfbedb640a
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+/**
+ * DOC: MEI_PXP Client Driver
+ *
+ * The mei_pxp driver acts as a translation layer between PXP
+ * protocol implementer (I915) and ME FW by translating PXP
+ * negotiation messages to ME FW command payloads and vice versa.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mei_pxp.h"
+
+/**
+ * mei_pxp_send_message() - Sends a PXP message to ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @message: a message buffer to send
+ * @size: size of the message
+ * Return: 0 on Success, <0 on Failure
+ */
+static int
+mei_pxp_send_message(struct device *dev, const void *message, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !message)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ /* temporary drop const qualifier till the API is fixed */
+ byte = mei_cldev_send(cldev, (u8 *)message, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ return 0;
+}
+
+/**
+ * mei_pxp_receive_message() - Receives a PXP message from ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @buffer: a message buffer to contain the received message
+ * @size: size of the buffer
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static int
+mei_pxp_receive_message(struct device *dev, void *buffer, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !buffer)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ byte = mei_cldev_recv(cldev, buffer, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ return byte;
+}
+
+static const struct i915_pxp_component_ops mei_pxp_ops = {
+ .owner = THIS_MODULE,
+ .send = mei_pxp_send_message,
+ .recv = mei_pxp_receive_message,
+};
+
+static int mei_component_master_bind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_component *comp_master = mei_cldev_get_drvdata(cldev);
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+
[Intel-gfx] [PATCH v4 03/17] drm/i915/pxp: define PXP device flag and kconfig
Ahead of the PXP implementation, define the relevant define flag and
kconfig option.
v2: flip kconfig default to N. Some machines have IFWIs that do not
support PXP, so we need it to be an opt-in until we add support to query
the caps from the mei device.
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi #v1
---
drivers/gpu/drm/i915/Kconfig | 11 +++
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 93f4d059fc89..3303579b41bb 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -131,6 +131,17 @@ config DRM_I915_GVT_KVMGT
Choose this option if you want to enable KVMGT support for
Intel GVT-g.
+config DRM_I915_PXP
+ bool "Enable Intel PXP support for Intel Gen12+ platform"
+ depends on DRM_I915
+ depends on INTEL_MEI && INTEL_MEI_PXP
+ default n
+ help
+ PXP (Protected Xe Path) is an i915 component, available on GEN12+
+ GPUs, that helps to establish the hardware protected session and
+ manage the status of the alive software session, as well as its life
+ cycle.
+
menu "drm/i915 Debugging"
depends on DRM_I915
depends on EXPERT
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9cb02618ba15..ee7280cad3bb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1701,6 +1701,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_VRR(i915) (INTEL_GEN(i915) >= 12)
+#define HAS_PXP(dev_priv) (IS_ENABLED(CONFIG_DRM_I915_PXP) && \
+ INTEL_INFO(dev_priv)->has_pxp) && \
+ VDBOX_MASK(_priv->gt)
+
/* Only valid when HAS_DISPLAY() is true */
#define INTEL_DISPLAY_ENABLED(dev_priv) \
(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)),
!(dev_priv)->params.disable_display)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 1390fad5ec06..2252f03558ff 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -129,6 +129,7 @@ enum intel_ppgtt_type {
func(has_logical_ring_elsq); \
func(has_master_unit_irq); \
func(has_pooled_eu); \
+ func(has_pxp); \
func(has_rc6); \
func(has_rc6p); \
func(has_rps); \
--
2.29.2
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[Intel-gfx] [PATCH v4 00/17] drm/i915: Introduce Intel PXP
PXP (Protected Xe Path) is an i915 component, available on GEN12+, that helps to establish the hardware protected session and manage the status of the alive software session, as well as its life cycle. Several minor changes and fixes, but the main changes in v4 are: - Rebased to new create_ext ioctl implementation - Default kconfig option is now N. - The default session is now only started when protected objects are submitted via execbuf. Tested with: https://patchwork.freedesktop.org/series/87570/ Cc: Gaurav Kumar Cc: Chris Wilson Cc: Rodrigo Vivi Cc: Joonas Lahtinen Cc: Juston Li Cc: Alan Previn Cc: Lionel Landwerlin Cc: Jason Ekstrand Cc: Daniel Vetter Anshuman Gupta (2): drm/i915/pxp: Add plane decryption support drm/i915/pxp: black pixels on pxp disabled Bommu Krishnaiah (1): drm/i915/pxp: User interface for Protected buffer Chris Wilson (1): drm/i915/gt: Export the pinned context constructor and destructor Daniele Ceraolo Spurio (7): drm/i915/pxp: Define PXP component interface drm/i915/pxp: define PXP device flag and kconfig drm/i915/pxp: allocate a vcs context for pxp usage drm/i915/pxp: set KCR reg init drm/i915/pxp: interface for marking contexts as using protected content drm/i915/pxp: start the arb session on demand drm/i915/pxp: enable PXP for integrated Gen12 Huang, Sean Z (5): drm/i915/pxp: Implement funcs to create the TEE channel drm/i915/pxp: Create the arbitrary session after boot drm/i915/pxp: Implement arb session teardown drm/i915/pxp: Implement PXP irq handler drm/i915/pxp: Enable PXP power management Vitaly Lubart (1): mei: pxp: export pavp client to me client bus drivers/gpu/drm/i915/Kconfig | 11 + drivers/gpu/drm/i915/Makefile | 9 + .../gpu/drm/i915/display/intel_atomic_plane.c | 25 ++ drivers/gpu/drm/i915/display/intel_display.c | 4 + .../drm/i915/display/intel_display_types.h| 6 + .../drm/i915/display/skl_universal_plane.c| 49 +++- drivers/gpu/drm/i915/gem/i915_gem_context.c | 59 +++- drivers/gpu/drm/i915/gem/i915_gem_context.h | 18 ++ .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 + drivers/gpu/drm/i915/gem/i915_gem_create.c| 26 ++ .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 35 +++ drivers/gpu/drm/i915/gem/i915_gem_object.c| 6 + drivers/gpu/drm/i915/gem/i915_gem_object.h| 12 + .../gpu/drm/i915/gem/i915_gem_object_types.h | 13 + drivers/gpu/drm/i915/gt/intel_engine.h| 12 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 29 +- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 22 +- drivers/gpu/drm/i915/gt/intel_gt.c| 5 + drivers/gpu/drm/i915/gt/intel_gt_irq.c| 7 + drivers/gpu/drm/i915/gt/intel_gt_pm.c | 15 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 + drivers/gpu/drm/i915/i915_drv.c | 2 + drivers/gpu/drm/i915/i915_drv.h | 4 + drivers/gpu/drm/i915/i915_pci.c | 2 + drivers/gpu/drm/i915/i915_reg.h | 48 drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/pxp/intel_pxp.c | 266 ++ drivers/gpu/drm/i915/pxp/intel_pxp.h | 65 + drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 140 + drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 15 + drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 100 +++ drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 32 +++ drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 40 +++ drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 23 ++ drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 172 +++ drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 15 + drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 161 +++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 17 ++ .../drm/i915/pxp/intel_pxp_tee_interface.h| 37 +++ drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 53 drivers/misc/mei/Kconfig | 2 + drivers/misc/mei/Makefile | 1 + drivers/misc/mei/pxp/Kconfig | 13 + drivers/misc/mei/pxp/Makefile | 7 + drivers/misc/mei/pxp/mei_pxp.c| 233 +++ drivers/misc/mei/pxp/mei_pxp.h| 18 ++ include/drm/i915_component.h | 1 + include/drm/i915_pxp_tee_interface.h | 45 +++ include/uapi/drm/i915_drm.h | 62 +++- 49 files changed, 1922 insertions(+), 21 deletions(-) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.h create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c create mode 100644
[Intel-gfx] ✗ Fi.CI.IGT: failure for dma-buf: Add an API for exporting sync files (v10)
== Series Details == Series: dma-buf: Add an API for exporting sync files (v10) URL : https://patchwork.freedesktop.org/series/90491/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10128_full -> Patchwork_20183_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_20183_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20183_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_20183_full: ### IGT changes ### Possible regressions * igt@kms_big_fb@yf-tiled-32bpp-rotate-180: - shard-iclb: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10128/shard-iclb3/igt@kms_big...@yf-tiled-32bpp-rotate-180.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20183/shard-iclb6/igt@kms_big...@yf-tiled-32bpp-rotate-180.html * igt@kms_ccs@pipe-c-bad-rotation-90: - shard-tglb: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10128/shard-tglb1/igt@kms_...@pipe-c-bad-rotation-90.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20183/shard-tglb6/igt@kms_...@pipe-c-bad-rotation-90.html New tests - New tests have been introduced between CI_DRM_10128_full and Patchwork_20183_full: ### New IGT tests (9) ### * igt@dmabuf_sync_file@export-basic: - Statuses : 5 pass(s) - Exec time: [0.0, 0.01] s * igt@dmabuf_sync_file@export-before-signal: - Statuses : 7 pass(s) - Exec time: [0.00, 0.03] s * igt@dmabuf_sync_file@export-multiwait: - Statuses : 6 pass(s) - Exec time: [0.00, 0.01] s * igt@dmabuf_sync_file@export-wait-after-attach: - Statuses : 5 pass(s) - Exec time: [0.00, 0.01] s * igt@dmabuf_sync_file@import-basic: - Statuses : 7 pass(s) - Exec time: [0.00, 0.04] s * igt@dmabuf_sync_file@import-existing-exclusive: - Statuses : 5 pass(s) - Exec time: [0.00, 0.02] s * igt@dmabuf_sync_file@import-existing-shared-1: - Statuses : 5 pass(s) - Exec time: [0.00, 0.03] s * igt@dmabuf_sync_file@import-existing-shared-32: - Statuses : 6 pass(s) - Exec time: [0.01, 0.10] s * igt@dmabuf_sync_file@import-existing-shared-5: - Statuses : 4 pass(s) - Exec time: [0.00, 0.01] s Known issues Here are the changes found in Patchwork_20183_full that come from known issues: ### IGT changes ### Issues hit * igt@api_intel_bb@full-batch: - shard-glk: NOTRUN -> [DMESG-WARN][5] ([i915#118] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20183/shard-glk5/igt@api_intel...@full-batch.html * igt@core_hotunplug@unbind-rebind: - shard-kbl: [PASS][6] -> [DMESG-WARN][7] ([i915#2283]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10128/shard-kbl2/igt@core_hotunp...@unbind-rebind.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20183/shard-kbl1/igt@core_hotunp...@unbind-rebind.html * igt@gem_ctx_persistence@legacy-engines-mixed: - shard-snb: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1099]) +8 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20183/shard-snb7/igt@gem_ctx_persiste...@legacy-engines-mixed.html * igt@gem_ctx_ringsize@idle@bcs0: - shard-skl: NOTRUN -> [INCOMPLETE][9] ([i915#3316]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20183/shard-skl10/igt@gem_ctx_ringsize@i...@bcs0.html * igt@gem_ctx_sseu@invalid-args: - shard-tglb: NOTRUN -> [SKIP][10] ([i915#280]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20183/shard-tglb1/igt@gem_ctx_s...@invalid-args.html * igt@gem_exec_fair@basic-deadline: - shard-apl: NOTRUN -> [FAIL][11] ([i915#2846]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20183/shard-apl2/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-tglb: NOTRUN -> [FAIL][12] ([i915#2842]) +6 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20183/shard-tglb1/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-kbl: NOTRUN -> [FAIL][13] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20183/shard-kbl7/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-iclb: NOTRUN -> [FAIL][14] ([i915#2842]) +4 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20183/shard-iclb6/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: -
Re: [Intel-gfx] [RFC PATCH 16/97] drm/i915/guc: Start protecting access to CTB descriptors
On Thu, May 06, 2021 at 12:13:30PM -0700, Matthew Brost wrote:
> From: Michal Wajdeczko
>
> We want to stop using guc.send_mutex while sending CTB messages
> so we have to start protecting access to CTB send descriptor.
>
> For completeness protect also CTB send descriptor.
>
> Add spinlock to struct intel_guc_ct_buffer and start using it.
>
> Signed-off-by: Michal Wajdeczko
> Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 14 --
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 2 ++
> 2 files changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index a4b2e7fe318b..bee0958d8bae 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -89,6 +89,8 @@ static void ct_incoming_request_worker_func(struct
> work_struct *w);
> */
> void intel_guc_ct_init_early(struct intel_guc_ct *ct)
> {
> + spin_lock_init(>ctbs.send.lock);
> + spin_lock_init(>ctbs.recv.lock);
> spin_lock_init(>requests.lock);
> INIT_LIST_HEAD(>requests.pending);
> INIT_LIST_HEAD(>requests.incoming);
> @@ -479,17 +481,22 @@ static int ct_send(struct intel_guc_ct *ct,
> GEM_BUG_ON(len & ~GUC_CT_MSG_LEN_MASK);
> GEM_BUG_ON(!response_buf && response_buf_size);
>
> + spin_lock_irqsave(>ctbs.send.lock, flags);
> +
> fence = ct_get_next_fence(ct);
> request.fence = fence;
> request.status = 0;
> request.response_len = response_buf_size;
> request.response_buf = response_buf;
>
> - spin_lock_irqsave(>requests.lock, flags);
> + spin_lock(>requests.lock);
> list_add_tail(, >requests.pending);
> - spin_unlock_irqrestore(>requests.lock, flags);
> + spin_unlock(>requests.lock);
>
> err = ct_write(ct, action, len, fence);
> +
> + spin_unlock_irqrestore(>ctbs.send.lock, flags);
> +
> if (unlikely(err))
> goto unlink;
>
> @@ -825,6 +832,7 @@ static int ct_handle_request(struct intel_guc_ct *ct,
> const u32 *msg)
> void intel_guc_ct_event_handler(struct intel_guc_ct *ct)
> {
> u32 msg[GUC_CT_MSG_LEN_MASK + 1]; /* one extra dw for the header */
> + unsigned long flags;
> int err = 0;
>
> if (unlikely(!ct->enabled)) {
> @@ -833,7 +841,9 @@ void intel_guc_ct_event_handler(struct intel_guc_ct *ct)
> }
>
> do {
> + spin_lock_irqsave(>ctbs.recv.lock, flags);
> err = ct_read(ct, msg);
> + spin_unlock_irqrestore(>ctbs.recv.lock, flags);
> if (err)
> break;
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> index fc9486779e87..bc52dc479a14 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> @@ -27,11 +27,13 @@ struct intel_guc;
> * record (command transport buffer descriptor) and the actual buffer which
> * holds the commands.
> *
> + * @lock: protects access to the commands buffer and buffer descriptor
> * @desc: pointer to the buffer descriptor
> * @cmds: pointer to the commands buffer
> * @size: size of the commands buffer
> */
> struct intel_guc_ct_buffer {
> + spinlock_t lock;
> struct guc_ct_buffer_desc *desc;
> u32 *cmds;
> u32 size;
> --
> 2.28.0
>
___
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Re: [Intel-gfx] [RFC PATCH 16/97] drm/i915/guc: Start protecting access to CTB descriptors
On Thu, May 06, 2021 at 12:13:30PM -0700, Matthew Brost wrote:
> From: Michal Wajdeczko
>
> We want to stop using guc.send_mutex while sending CTB messages
> so we have to start protecting access to CTB send descriptor.
>
> For completeness protect also CTB send descriptor.
Michal I think you have a typo here, receive descriptor, right? Again
this is going to get squashed in the firmware update patch but thought
I'd mention this.
With that:
Reviewed-by: Matthew Brost
>
> Add spinlock to struct intel_guc_ct_buffer and start using it.
>
> Signed-off-by: Michal Wajdeczko
> Signed-off-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 14 --
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 2 ++
> 2 files changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index a4b2e7fe318b..bee0958d8bae 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -89,6 +89,8 @@ static void ct_incoming_request_worker_func(struct
> work_struct *w);
> */
> void intel_guc_ct_init_early(struct intel_guc_ct *ct)
> {
> + spin_lock_init(>ctbs.send.lock);
> + spin_lock_init(>ctbs.recv.lock);
> spin_lock_init(>requests.lock);
> INIT_LIST_HEAD(>requests.pending);
> INIT_LIST_HEAD(>requests.incoming);
> @@ -479,17 +481,22 @@ static int ct_send(struct intel_guc_ct *ct,
> GEM_BUG_ON(len & ~GUC_CT_MSG_LEN_MASK);
> GEM_BUG_ON(!response_buf && response_buf_size);
>
> + spin_lock_irqsave(>ctbs.send.lock, flags);
> +
> fence = ct_get_next_fence(ct);
> request.fence = fence;
> request.status = 0;
> request.response_len = response_buf_size;
> request.response_buf = response_buf;
>
> - spin_lock_irqsave(>requests.lock, flags);
> + spin_lock(>requests.lock);
> list_add_tail(, >requests.pending);
> - spin_unlock_irqrestore(>requests.lock, flags);
> + spin_unlock(>requests.lock);
>
> err = ct_write(ct, action, len, fence);
> +
> + spin_unlock_irqrestore(>ctbs.send.lock, flags);
> +
> if (unlikely(err))
> goto unlink;
>
> @@ -825,6 +832,7 @@ static int ct_handle_request(struct intel_guc_ct *ct,
> const u32 *msg)
> void intel_guc_ct_event_handler(struct intel_guc_ct *ct)
> {
> u32 msg[GUC_CT_MSG_LEN_MASK + 1]; /* one extra dw for the header */
> + unsigned long flags;
> int err = 0;
>
> if (unlikely(!ct->enabled)) {
> @@ -833,7 +841,9 @@ void intel_guc_ct_event_handler(struct intel_guc_ct *ct)
> }
>
> do {
> + spin_lock_irqsave(>ctbs.recv.lock, flags);
> err = ct_read(ct, msg);
> + spin_unlock_irqrestore(>ctbs.recv.lock, flags);
> if (err)
> break;
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> index fc9486779e87..bc52dc479a14 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> @@ -27,11 +27,13 @@ struct intel_guc;
> * record (command transport buffer descriptor) and the actual buffer which
> * holds the commands.
> *
> + * @lock: protects access to the commands buffer and buffer descriptor
> * @desc: pointer to the buffer descriptor
> * @cmds: pointer to the commands buffer
> * @size: size of the commands buffer
> */
> struct intel_guc_ct_buffer {
> + spinlock_t lock;
> struct guc_ct_buffer_desc *desc;
> u32 *cmds;
> u32 size;
> --
> 2.28.0
>
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Re: [Intel-gfx] [RFC PATCH 13/97] drm/i915/guc: Replace CTB array with explicit members
On Thu, May 06, 2021 at 12:13:27PM -0700, Matthew Brost wrote:
> From: Michal Wajdeczko
>
> Upcoming GuC firmware will always require just two CTBs and we
> also plan to configure them with different sizes, so definining
> them as array is no longer suitable.
>
> Signed-off-by: Michal Wajdeczko
> Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 46 ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 7 +++-
> 2 files changed, 30 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index fbd6bd20f588..c54a29176862 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -168,10 +168,10 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
> struct intel_guc *guc = ct_to_guc(ct);
> struct guc_ct_buffer_desc *desc;
> u32 blob_size;
> + u32 cmds_size;
> void *blob;
> u32 *cmds;
> int err;
> - int i;
>
> GEM_BUG_ON(ct->vma);
>
> @@ -207,15 +207,23 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
>
> CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma),
> blob_size);
>
> - /* store pointers to desc and cmds */
> - for (i = 0; i < ARRAY_SIZE(ct->ctbs); i++) {
> - GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
> + /* store pointers to desc and cmds for send ctb */
> + desc = blob;
> + cmds = blob + PAGE_SIZE / 2;
> + cmds_size = PAGE_SIZE / 4;
> + CT_DEBUG(ct, "%s desc %#lx cmds %#lx size %u\n", "send",
> + ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size);
>
> - desc = blob + PAGE_SIZE / 4 * i;
> - cmds = blob + PAGE_SIZE / 4 * i + PAGE_SIZE / 2;
> + guc_ct_buffer_init(>ctbs.send, desc, cmds, cmds_size);
>
> - guc_ct_buffer_init(>ctbs[i], desc, cmds, PAGE_SIZE / 4);
> - }
> + /* store pointers to desc and cmds for recv ctb */
> + desc = blob + PAGE_SIZE / 4;
> + cmds = blob + PAGE_SIZE / 4 + PAGE_SIZE / 2;
> + cmds_size = PAGE_SIZE / 4;
> + CT_DEBUG(ct, "%s desc %#lx cmds %#lx size %u\n", "recv",
> + ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size);
> +
> + guc_ct_buffer_init(>ctbs.recv, desc, cmds, cmds_size);
>
> return 0;
> }
> @@ -246,7 +254,6 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
> u32 base, cmds;
> void *blob;
> int err;
> - int i;
>
> GEM_BUG_ON(ct->enabled);
>
> @@ -257,28 +264,25 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
>
> /* blob should start with send descriptor */
> blob = __px_vaddr(ct->vma->obj);
> - GEM_BUG_ON(blob != ct->ctbs[CTB_SEND].desc);
> + GEM_BUG_ON(blob != ct->ctbs.send.desc);
>
> /* (re)initialize descriptors */
> - for (i = 0; i < ARRAY_SIZE(ct->ctbs); i++) {
> - GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
> + cmds = base + ptrdiff(ct->ctbs.send.cmds, blob);
> + guc_ct_buffer_reset(>ctbs.send, cmds);
>
> - cmds = base + ptrdiff(ct->ctbs[i].cmds, blob);
> - CT_DEBUG(ct, "%d: cmds addr=%#x\n", i, cmds);
> -
> - guc_ct_buffer_reset(>ctbs[i], cmds);
> - }
> + cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob);
> + guc_ct_buffer_reset(>ctbs.recv, cmds);
>
> /*
>* Register both CT buffers starting with RECV buffer.
>* Descriptors are in first half of the blob.
>*/
> - err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs[CTB_RECV].desc,
> blob),
> + err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs.recv.desc, blob),
>INTEL_GUC_CT_BUFFER_TYPE_RECV);
> if (unlikely(err))
> goto err_out;
>
> - err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs[CTB_SEND].desc,
> blob),
> + err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs.send.desc, blob),
>INTEL_GUC_CT_BUFFER_TYPE_SEND);
> if (unlikely(err))
> goto err_deregister;
> @@ -341,7 +345,7 @@ static int ct_write(struct intel_guc_ct *ct,
> u32 len /* in dwords */,
> u32 fence)
> {
> - struct intel_guc_ct_buffer *ctb = >ctbs[CTB_SEND];
> + struct intel_guc_ct_buffer *ctb = >ctbs.send;
> struct guc_ct_buffer_desc *desc = ctb->desc;
> u32 head = desc->head;
> u32 tail = desc->tail;
> @@ -557,7 +561,7 @@ static inline bool ct_header_is_response(u32 header)
>
> static int ct_read(struct intel_guc_ct *ct, u32 *data)
> {
> - struct intel_guc_ct_buffer *ctb = >ctbs[CTB_RECV];
> + struct intel_guc_ct_buffer *ctb = >ctbs.recv;
> struct guc_ct_buffer_desc *desc = ctb->desc;
> u32 head = desc->head;
> u32 tail = desc->tail;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
>
Re: [Intel-gfx] [PATCH v7 04/15] swiotlb: Add restricted DMA pool initialization
On Mon, May 24, 2021 at 11:49 PM Konrad Rzeszutek Wilk wrote: > > On Tue, May 18, 2021 at 02:48:35PM +0800, Claire Chang wrote: > > I didn't move this to a separate file because I feel it might be > > confusing for swiotlb_alloc/free (and need more functions to be > > non-static). > > Maybe instead of moving to a separate file, we can try to come up with > > a better naming? > > I think you are referring to: > > rmem_swiotlb_setup > > ? Yes, and the following swiotlb_alloc/free. > > Which is ARM specific and inside the generic code? > > > > Christopher wants to unify it in all the code so there is one single > source, but the "you seperate arch code out from generic" saying > makes me want to move it out. > > I agree that if you move it out from generic to arch-specific we have to > expose more of the swiotlb functions, which will undo's Christopher > cleanup code. > > How about this - lets leave it as is now, and when there are more > use-cases we can revisit it and then if need to move the code? > Ok! Sounds good! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v7 05/15] swiotlb: Add a new get_io_tlb_mem getter
On Mon, May 24, 2021 at 11:51 PM Konrad Rzeszutek Wilk wrote: > > On Tue, May 18, 2021 at 02:51:52PM +0800, Claire Chang wrote: > > Still keep this function because directly using dev->dma_io_tlb_mem > > will cause issues for memory allocation for existing devices. The pool > > can't support atomic coherent allocation so we need to distinguish the > > per device pool and the default pool in swiotlb_alloc. > > This above should really be rolled in the commit. You can prefix it by > "The reason it was done this way was because directly using .." > Will add it. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v7 01/15] swiotlb: Refactor swiotlb init functions
On Mon, May 24, 2021 at 11:53 PM Konrad Rzeszutek Wilk wrote: > > > > do the set_memory_decrypted()+memset(). Is this okay or should > > > swiotlb_init_io_tlb_mem() add an additional argument to do this > > > conditionally? > > > > I'm actually not sure if this it okay. If not, will add an additional > > argument for it. > > Any observations discovered? (Want to make sure my memory-cache has the > correct semantics for set_memory_decrypted in mind). It works fine on my arm64 device. > > > > > -- > > > Florian ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 14/97] drm/i915/guc: Update sizes of CTB buffers
On Thu, May 06, 2021 at 12:13:28PM -0700, Matthew Brost wrote:
> From: Michal Wajdeczko
>
> Future GuC will require CTB buffers sizes to be multiple of 4K.
> Make these changes now as this shouldn't impact us too much.
>
> Signed-off-by: Michal Wajdeczko
> Signed-off-by: Matthew Brost
> Cc: John Harrison
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 60 ---
> 1 file changed, 32 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index c54a29176862..c87a0a8bef26 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -38,6 +38,32 @@ static inline struct drm_device *ct_to_drm(struct
> intel_guc_ct *ct)
> #define CT_PROBE_ERROR(_ct, _fmt, ...) \
> i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__);
>
> +/**
> + * DOC: CTB Blob
> + *
> + * We allocate single blob to hold both CTB descriptors and buffers:
> + *
> + * ++---+--+
> + * | offset | contents | size |
> + * ++===+==+
> + * | 0x | H2G `CTB Descriptor`_ (send) | |
> + * ++---+ 4K |
> + * | 0x0800 | G2H `CTB Descriptor`_ (recv) | |
> + * ++---+--+
> + * | 0x1000 | H2G `CT Buffer`_ (send) | n*4K |
> + * || | |
> + * ++---+--+
> + * | 0x1000 | G2H `CT Buffer`_ (recv) | m*4K |
> + * | + n*4K | | |
> + * ++---+--+
> + *
> + * Size of each `CT Buffer`_ must be multiple of 4K.
> + * As we don't expect too many messages, for now use minimum sizes.
> + */
> +#define CTB_DESC_SIZEALIGN(sizeof(struct
> guc_ct_buffer_desc), SZ_2K)
> +#define CTB_H2G_BUFFER_SIZE (SZ_4K)
> +#define CTB_G2H_BUFFER_SIZE (SZ_4K)
> +
> struct ct_request {
> struct list_head link;
> u32 fence;
> @@ -175,29 +201,7 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
>
> GEM_BUG_ON(ct->vma);
>
> - /* We allocate 1 page to hold both descriptors and both buffers.
> - * ___.
> - * |desc (SEND)| :
> - * |___| PAGE/4
> - * :___:
> - * |desc (RECV)| :
> - * |___| PAGE/4
> - * :___:
> - * |cmds (SEND)|
> - * | PAGE/4
> - * |___|
> - * |cmds (RECV)|
> - * | PAGE/4
> - * |___|
> - *
> - * Each message can use a maximum of 32 dwords and we don't expect to
> - * have more than 1 in flight at any time, so we have enough space.
> - * Some logic further ahead will rely on the fact that there is only 1
> - * page and that it is always mapped, so if the size is changed the
> - * other code will need updating as well.
> - */
> -
> - blob_size = PAGE_SIZE;
> + blob_size = 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE +
> CTB_G2H_BUFFER_SIZE;
> err = intel_guc_allocate_and_map_vma(guc, blob_size, >vma, );
> if (unlikely(err)) {
> CT_PROBE_ERROR(ct, "Failed to allocate %u for CTB data (%pe)\n",
> @@ -209,17 +213,17 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
>
> /* store pointers to desc and cmds for send ctb */
> desc = blob;
> - cmds = blob + PAGE_SIZE / 2;
> - cmds_size = PAGE_SIZE / 4;
> + cmds = blob + 2 * CTB_DESC_SIZE;
2 is a magic number here. Think it would be more clear with
CTB_NUMBER_DESC define here.
Michal what do you think? We can fix this in the next post of this with
your blessing.
With that nit:
Reviewed-by: Matthew Brost
> + cmds_size = CTB_H2G_BUFFER_SIZE;
> CT_DEBUG(ct, "%s desc %#lx cmds %#lx size %u\n", "send",
>ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size);
>
> guc_ct_buffer_init(>ctbs.send, desc, cmds, cmds_size);
>
> /* store pointers to desc and cmds for recv ctb */
> - desc = blob + PAGE_SIZE / 4;
> - cmds = blob + PAGE_SIZE / 4 + PAGE_SIZE / 2;
> - cmds_size = PAGE_SIZE / 4;
> + desc = blob + CTB_DESC_SIZE;
> + cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE;
> + cmds_size =
Re: [Intel-gfx] [RFC PATCH 12/97] drm/i915/guc: Don't repeat CTB layout calculations
On Thu, May 06, 2021 at 12:13:26PM -0700, Matthew Brost wrote:
> From: Michal Wajdeczko
>
> We can retrieve offsets to cmds buffers and descriptor from
> actual pointers that we already keep locally.
>
> Signed-off-by: Michal Wajdeczko
> Signed-off-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 16 ++--
> 1 file changed, 10 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index dbece569fbe4..fbd6bd20f588 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -244,6 +244,7 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
> {
> struct intel_guc *guc = ct_to_guc(ct);
> u32 base, cmds;
> + void *blob;
> int err;
> int i;
>
> @@ -251,15 +252,18 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
>
> /* vma should be already allocated and map'ed */
> GEM_BUG_ON(!ct->vma);
> + GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj));
This doesn't really have anything to do with this patch, but again this
patch will be squashed into a large patch updating the GuC firmware, so
I think this is fine.
With that:
Reviewed-by: Matthew Brost
> base = intel_guc_ggtt_offset(guc, ct->vma);
>
> - /* (re)initialize descriptors
> - * cmds buffers are in the second half of the blob page
> - */
> + /* blob should start with send descriptor */
> + blob = __px_vaddr(ct->vma->obj);
> + GEM_BUG_ON(blob != ct->ctbs[CTB_SEND].desc);
> +
> + /* (re)initialize descriptors */
> for (i = 0; i < ARRAY_SIZE(ct->ctbs); i++) {
> GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
>
> - cmds = base + PAGE_SIZE / 4 * i + PAGE_SIZE / 2;
> + cmds = base + ptrdiff(ct->ctbs[i].cmds, blob);
> CT_DEBUG(ct, "%d: cmds addr=%#x\n", i, cmds);
>
> guc_ct_buffer_reset(>ctbs[i], cmds);
> @@ -269,12 +273,12 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
>* Register both CT buffers starting with RECV buffer.
>* Descriptors are in first half of the blob.
>*/
> - err = ct_register_buffer(ct, base + PAGE_SIZE / 4 * CTB_RECV,
> + err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs[CTB_RECV].desc,
> blob),
>INTEL_GUC_CT_BUFFER_TYPE_RECV);
> if (unlikely(err))
> goto err_out;
>
> - err = ct_register_buffer(ct, base + PAGE_SIZE / 4 * CTB_SEND,
> + err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs[CTB_SEND].desc,
> blob),
>INTEL_GUC_CT_BUFFER_TYPE_SEND);
> if (unlikely(err))
> goto err_deregister;
> --
> 2.28.0
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 11/97] drm/i915/guc: Only rely on own CTB size
On Thu, May 06, 2021 at 12:13:25PM -0700, Matthew Brost wrote:
> From: Michal Wajdeczko
>
> In upcoming GuC firmware, CTB size will be removed from the CTB
> descriptor so we must keep it locally for any calculations.
>
> While around, improve some debug messages and helpers.
>
desc->size is still used in the patch and really shouldn't be per this
comment but a patch later in the series drops it. Seeing as this patch
and that patch are going to squashed into a single patch upgrading the
GuC firmware I think that is ok.
With that:
Reviewed-by: Matthew Brost
> Signed-off-by: Michal Wajdeczko
> Signed-off-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 55 +--
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 2 +
> 2 files changed, 43 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index 4cc8c0b71699..dbece569fbe4 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -90,6 +90,24 @@ static void guc_ct_buffer_desc_init(struct
> guc_ct_buffer_desc *desc,
> desc->owner = CTB_OWNER_HOST;
> }
>
> +static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb, u32
> cmds_addr)
> +{
> + guc_ct_buffer_desc_init(ctb->desc, cmds_addr, ctb->size);
> +}
> +
> +static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb,
> +struct guc_ct_buffer_desc *desc,
> +u32 *cmds, u32 size)
> +{
> + GEM_BUG_ON(size % 4);
> +
> + ctb->desc = desc;
> + ctb->cmds = cmds;
> + ctb->size = size;
> +
> + guc_ct_buffer_reset(ctb, 0);
> +}
> +
> static int guc_action_register_ct_buffer(struct intel_guc *guc,
>u32 desc_addr,
>u32 type)
> @@ -148,7 +166,10 @@ static int ct_deregister_buffer(struct intel_guc_ct *ct,
> u32 type)
> int intel_guc_ct_init(struct intel_guc_ct *ct)
> {
> struct intel_guc *guc = ct_to_guc(ct);
> + struct guc_ct_buffer_desc *desc;
> + u32 blob_size;
> void *blob;
> + u32 *cmds;
> int err;
> int i;
>
> @@ -176,19 +197,24 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
>* other code will need updating as well.
>*/
>
> - err = intel_guc_allocate_and_map_vma(guc, PAGE_SIZE, >vma, );
> + blob_size = PAGE_SIZE;
> + err = intel_guc_allocate_and_map_vma(guc, blob_size, >vma, );
> if (unlikely(err)) {
> - CT_ERROR(ct, "Failed to allocate CT channel (err=%d)\n", err);
> + CT_PROBE_ERROR(ct, "Failed to allocate %u for CTB data (%pe)\n",
> +blob_size, ERR_PTR(err));
> return err;
> }
>
> - CT_DEBUG(ct, "vma base=%#x\n", intel_guc_ggtt_offset(guc, ct->vma));
> + CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma),
> blob_size);
>
> /* store pointers to desc and cmds */
> for (i = 0; i < ARRAY_SIZE(ct->ctbs); i++) {
> GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
> - ct->ctbs[i].desc = blob + PAGE_SIZE/4 * i;
> - ct->ctbs[i].cmds = blob + PAGE_SIZE/4 * i + PAGE_SIZE/2;
> +
> + desc = blob + PAGE_SIZE / 4 * i;
> + cmds = blob + PAGE_SIZE / 4 * i + PAGE_SIZE / 2;
> +
> + guc_ct_buffer_init(>ctbs[i], desc, cmds, PAGE_SIZE / 4);
> }
>
> return 0;
> @@ -217,7 +243,7 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct)
> int intel_guc_ct_enable(struct intel_guc_ct *ct)
> {
> struct intel_guc *guc = ct_to_guc(ct);
> - u32 base, cmds, size;
> + u32 base, cmds;
> int err;
> int i;
>
> @@ -232,10 +258,11 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
>*/
> for (i = 0; i < ARRAY_SIZE(ct->ctbs); i++) {
> GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
> +
> cmds = base + PAGE_SIZE / 4 * i + PAGE_SIZE / 2;
> - size = PAGE_SIZE / 4;
> - CT_DEBUG(ct, "%d: addr=%#x size=%u\n", i, cmds, size);
> - guc_ct_buffer_desc_init(ct->ctbs[i].desc, cmds, size);
> + CT_DEBUG(ct, "%d: cmds addr=%#x\n", i, cmds);
> +
> + guc_ct_buffer_reset(>ctbs[i], cmds);
> }
>
> /*
> @@ -259,7 +286,7 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
> err_deregister:
> ct_deregister_buffer(ct, INTEL_GUC_CT_BUFFER_TYPE_RECV);
> err_out:
> - CT_PROBE_ERROR(ct, "Failed to open channel (err=%d)\n", err);
> + CT_PROBE_ERROR(ct, "Failed to enable CTB (%pe)\n", ERR_PTR(err));
> return err;
> }
>
> @@ -314,7 +341,7 @@ static int ct_write(struct intel_guc_ct *ct,
> struct guc_ct_buffer_desc *desc = ctb->desc;
> u32 head = desc->head;
> u32 tail = desc->tail;
> - u32 size = desc->size;
> + u32 size = ctb->size;
> u32 used;
>
Re: [Intel-gfx] [RFC PATCH 09/97] drm/i915/guc: Stop using fence/status from CTB descriptor
On Thu, May 06, 2021 at 12:13:23PM -0700, Matthew Brost wrote:
> From: Michal Wajdeczko
>
> Stop using fence/status from CTB descriptor as future GuC ABI will
> no longer support replies over CTB descriptor.
>
> Signed-off-by: Michal Wajdeczko
> Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
> ---
> .../gt/uc/abi/guc_communication_ctb_abi.h | 4 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 72 ++-
> 2 files changed, 6 insertions(+), 70 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
> b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
> index ebd8c3e0e4bb..d38935f47ecf 100644
> --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
> +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
> @@ -71,8 +71,8 @@ struct guc_ct_buffer_desc {
> u32 head; /* offset updated by GuC*/
> u32 tail; /* offset updated by owner */
> u32 is_in_error;/* error indicator */
> - u32 fence; /* fence updated by GuC */
> - u32 status; /* status updated by GuC */
> + u32 reserved1;
> + u32 reserved2;
> u32 owner; /* id of the channel owner */
> u32 owner_sub_id; /* owner-defined field for extra tracking */
> u32 reserved[5];
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index 25618649048f..4cc8c0b71699 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -90,13 +90,6 @@ static void guc_ct_buffer_desc_init(struct
> guc_ct_buffer_desc *desc,
> desc->owner = CTB_OWNER_HOST;
> }
>
> -static void guc_ct_buffer_desc_reset(struct guc_ct_buffer_desc *desc)
> -{
> - desc->head = 0;
> - desc->tail = 0;
> - desc->is_in_error = 0;
> -}
> -
> static int guc_action_register_ct_buffer(struct intel_guc *guc,
>u32 desc_addr,
>u32 type)
> @@ -315,8 +308,7 @@ static u32 ct_get_next_fence(struct intel_guc_ct *ct)
> static int ct_write(struct intel_guc_ct *ct,
> const u32 *action,
> u32 len /* in dwords */,
> - u32 fence,
> - bool want_response)
> + u32 fence)
> {
> struct intel_guc_ct_buffer *ctb = >ctbs[CTB_SEND];
> struct guc_ct_buffer_desc *desc = ctb->desc;
> @@ -360,8 +352,7 @@ static int ct_write(struct intel_guc_ct *ct,
>* DW2+: action data
>*/
> header = (len << GUC_CT_MSG_LEN_SHIFT) |
> - (GUC_CT_MSG_WRITE_FENCE_TO_DESC) |
> - (want_response ? GUC_CT_MSG_SEND_STATUS : 0) |
> + GUC_CT_MSG_SEND_STATUS |
>(action[0] << GUC_CT_MSG_ACTION_SHIFT);
>
> CT_DEBUG(ct, "writing %*ph %*ph %*ph\n",
> @@ -390,56 +381,6 @@ static int ct_write(struct intel_guc_ct *ct,
> return -EPIPE;
> }
>
> -/**
> - * wait_for_ctb_desc_update - Wait for the CT buffer descriptor update.
> - * @desc:buffer descriptor
> - * @fence: response fence
> - * @status: placeholder for status
> - *
> - * Guc will update CT buffer descriptor with new fence and status
> - * after processing the command identified by the fence. Wait for
> - * specified fence and then read from the descriptor status of the
> - * command.
> - *
> - * Return:
> - * * 0 response received (status is valid)
> - * * -ETIMEDOUT no response within hardcoded timeout
> - * * -EPROTO no response, CT buffer is in error
> - */
> -static int wait_for_ctb_desc_update(struct guc_ct_buffer_desc *desc,
> - u32 fence,
> - u32 *status)
> -{
> - int err;
> -
> - /*
> - * Fast commands should complete in less than 10us, so sample quickly
> - * up to that length of time, then switch to a slower sleep-wait loop.
> - * No GuC command should ever take longer than 10ms.
> - */
> -#define done (READ_ONCE(desc->fence) == fence)
> - err = wait_for_us(done, 10);
> - if (err)
> - err = wait_for(done, 10);
> -#undef done
> -
> - if (unlikely(err)) {
> - DRM_ERROR("CT: fence %u failed; reported fence=%u\n",
> - fence, desc->fence);
> -
> - if (WARN_ON(desc->is_in_error)) {
> - /* Something went wrong with the messaging, try to reset
> - * the buffer and hope for the best
> - */
> - guc_ct_buffer_desc_reset(desc);
> - err = -EPROTO;
> - }
> - }
> -
> - *status = desc->status;
> - return err;
> -}
> -
> /**
> * wait_for_ct_request_update - Wait for CT request state update.
> * @req: pointer to pending request
> @@ -483,8 +424,6 @@ static int ct_send(struct intel_guc_ct *ct,
>
[Intel-gfx] ✓ Fi.CI.IGT: success for More DMC cleanup (rev4)
== Series Details == Series: More DMC cleanup (rev4) URL : https://patchwork.freedesktop.org/series/90379/ State : success == Summary == CI Bug Log - changes from CI_DRM_10127_full -> Patchwork_20181_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_20181_full that come from known issues: ### CI changes ### Possible fixes * boot: - shard-skl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [FAIL][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) ([i915#3174]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl8/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl8/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl8/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl8/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl7/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl7/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl7/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl7/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl6/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl6/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl6/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl6/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl4/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl4/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl4/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl3/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl3/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl10/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl10/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl10/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl10/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl1/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl1/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl1/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl1/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/shard-skl4/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/shard-skl4/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/shard-skl3/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/shard-skl3/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/shard-skl10/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/shard-skl10/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/shard-skl10/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/shard-skl10/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/shard-skl1/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/shard-skl1/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/shard-skl1/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/shard-skl1/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/shard-skl8/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/shard-skl8/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/shard-skl8/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/shard-skl8/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/shard-skl7/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/shard-skl7/boot.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/shard-skl7/boot.html [45]:
Re: [Intel-gfx] [RFC PATCH 23/97] drm/i915/guc: Support per context scheduling policies
On Thu, May 06, 2021 at 12:13:37PM -0700, Matthew Brost wrote:
> From: John Harrison
>
> GuC firmware v53.0.0 introduced per context scheduling policies. This
> includes changes to some of the ADS structures which are required to
> load the firmware even if not using GuC submission.
>
> Signed-off-by: John Harrison
> Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 26 +++--
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 31 +
> 2 files changed, 11 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index 17526717368c..648e1767b17a 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -58,30 +58,12 @@ static u32 guc_ads_blob_size(struct intel_guc *guc)
> guc_ads_private_data_size(guc);
> }
>
> -static void guc_policy_init(struct guc_policy *policy)
> -{
> - policy->execution_quantum = POLICY_DEFAULT_EXECUTION_QUANTUM_US;
> - policy->preemption_time = POLICY_DEFAULT_PREEMPTION_TIME_US;
> - policy->fault_time = POLICY_DEFAULT_FAULT_TIME_US;
> - policy->policy_flags = 0;
> -}
> -
> static void guc_policies_init(struct guc_policies *policies)
> {
> - struct guc_policy *policy;
> - u32 p, i;
> -
> - policies->dpc_promote_time = POLICY_DEFAULT_DPC_PROMOTE_TIME_US;
> - policies->max_num_work_items = POLICY_MAX_NUM_WI;
> -
> - for (p = 0; p < GUC_CLIENT_PRIORITY_NUM; p++) {
> - for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++) {
> - policy = >policy[p][i];
> -
> - guc_policy_init(policy);
> - }
> - }
> -
> + policies->dpc_promote_time = GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US;
> + policies->max_num_work_items = GLOBAL_POLICY_MAX_NUM_WI;
> + /* Disable automatic resets as not yet supported. */
> + policies->global_flags = GLOBAL_POLICY_DISABLE_ENGINE_RESET;
> policies->is_valid = 1;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> index d445f6b77db4..95db4a7d3f4d 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> @@ -221,32 +221,14 @@ struct guc_stage_desc {
>
> /* Scheduling policy settings */
>
> -/* Reset engine upon preempt failure */
> -#define POLICY_RESET_ENGINE (1<<0)
> -/* Preempt to idle on quantum expiry */
> -#define POLICY_PREEMPT_TO_IDLE (1<<1)
> -
> -#define POLICY_MAX_NUM_WI 15
> -#define POLICY_DEFAULT_DPC_PROMOTE_TIME_US 50
> -#define POLICY_DEFAULT_EXECUTION_QUANTUM_US 100
> -#define POLICY_DEFAULT_PREEMPTION_TIME_US 50
> -#define POLICY_DEFAULT_FAULT_TIME_US 25
> -
> -struct guc_policy {
> - /* Time for one workload to execute. (in micro seconds) */
> - u32 execution_quantum;
> - /* Time to wait for a preemption request to completed before issuing a
> - * reset. (in micro seconds). */
> - u32 preemption_time;
> - /* How much time to allow to run after the first fault is observed.
> - * Then preempt afterwards. (in micro seconds) */
> - u32 fault_time;
> - u32 policy_flags;
> - u32 reserved[8];
> -} __packed;
> +#define GLOBAL_POLICY_MAX_NUM_WI 15
> +
> +/* Don't reset an engine upon preemption failure */
> +#define GLOBAL_POLICY_DISABLE_ENGINE_RESET BIT(0)
> +
> +#define GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US 50
>
> struct guc_policies {
> - struct guc_policy
> policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINE_CLASSES];
> u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];
> /* In micro seconds. How much time to allow before DPC processing is
>* called back via interrupt (to prevent DPC queue drain starving).
> @@ -260,6 +242,7 @@ struct guc_policies {
>* idle. */
> u32 max_num_work_items;
>
> + u32 global_flags;
> u32 reserved[4];
> } __packed;
>
> --
> 2.28.0
>
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Re: [Intel-gfx] [RFC PATCH 28/97] drm/i915/guc: Kill guc_clients.ct_pool
On Thu, May 06, 2021 at 12:13:42PM -0700, Matthew Brost wrote:
> From: Michal Wajdeczko
>
> CTB pool is now maintained internally by the GuC as part of its
> "private data". No need to allocate separate buffer and pass it
> to GuC as yet another ADS.
>
> GuC: 57.0.0
> Signed-off-by: Michal Wajdeczko
> Signed-off-by: Matthew Brost
> Cc: Janusz Krzysztofik
> Cc: Matthew Brost
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 12
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 12 +---
> 2 files changed, 1 insertion(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index 648e1767b17a..775f00d706fa 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -25,8 +25,6 @@
> * +---+
> * | guc_clients_info |
> * +---+
> - * | guc_ct_pool_entry[size] |
> - * +---+
> * | padding |
> * +---+ <== 4K aligned
> * | private data |
> @@ -39,7 +37,6 @@ struct __guc_ads_blob {
> struct guc_policies policies;
> struct guc_gt_system_info system_info;
> struct guc_clients_info clients_info;
> - struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE];
> } __packed;
>
> static u32 guc_ads_private_data_size(struct intel_guc *guc)
> @@ -67,11 +64,6 @@ static void guc_policies_init(struct guc_policies
> *policies)
> policies->is_valid = 1;
> }
>
> -static void guc_ct_pool_entries_init(struct guc_ct_pool_entry *pool, u32 num)
> -{
> - memset(pool, 0, num * sizeof(*pool));
> -}
> -
> static void guc_mapping_table_init(struct intel_gt *gt,
> struct guc_gt_system_info *system_info)
> {
> @@ -157,11 +149,7 @@ static void __guc_ads_init(struct intel_guc *guc)
> base = intel_guc_ggtt_offset(guc, guc->ads_vma);
>
> /* Clients info */
> - guc_ct_pool_entries_init(blob->ct_pool, ARRAY_SIZE(blob->ct_pool));
> -
> blob->clients_info.clients_num = 1;
> - blob->clients_info.ct_pool_addr = base + ptr_offset(blob, ct_pool);
> - blob->clients_info.ct_pool_count = ARRAY_SIZE(blob->ct_pool);
>
> /* ADS */
> blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> index 95db4a7d3f4d..301b173a26bc 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> @@ -269,19 +269,9 @@ struct guc_gt_system_info {
> } __packed;
>
> /* Clients info */
> -struct guc_ct_pool_entry {
> - struct guc_ct_buffer_desc desc;
> - u32 reserved[7];
> -} __packed;
> -
> -#define GUC_CT_POOL_SIZE 2
> -
> struct guc_clients_info {
> u32 clients_num;
> - u32 reserved0[13];
> - u32 ct_pool_addr;
> - u32 ct_pool_count;
> - u32 reserved[4];
> + u32 reserved[19];
> } __packed;
>
> /* GuC Additional Data Struct */
> --
> 2.28.0
>
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Re: [Intel-gfx] [RFC PATCH 10/97] drm/i915: Promote ptrdiff() to i915_utils.h
On Thu, May 06, 2021 at 12:13:24PM -0700, Matthew Brost wrote:
> From: Michal Wajdeczko
>
> Generic helpers should be placed in i915_utils.h.
>
> Signed-off-by: Michal Wajdeczko
> Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/i915_utils.h | 5 +
> drivers/gpu/drm/i915/i915_vma.h | 5 -
> 2 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_utils.h
> b/drivers/gpu/drm/i915/i915_utils.h
> index f02f52ab5070..5259edacde38 100644
> --- a/drivers/gpu/drm/i915/i915_utils.h
> +++ b/drivers/gpu/drm/i915/i915_utils.h
> @@ -201,6 +201,11 @@ __check_struct_size(size_t base, size_t arr, size_t
> count, size_t *size)
> __T;\
> })
>
> +static __always_inline ptrdiff_t ptrdiff(const void *a, const void *b)
> +{
> + return a - b;
> +}
> +
> /*
> * container_of_user: Extract the superclass from a pointer to a member.
> *
> diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
> index 8df784a026d2..a29a158990c6 100644
> --- a/drivers/gpu/drm/i915/i915_vma.h
> +++ b/drivers/gpu/drm/i915/i915_vma.h
> @@ -146,11 +146,6 @@ static inline void i915_vma_put(struct i915_vma *vma)
> i915_gem_object_put(vma->obj);
> }
>
> -static __always_inline ptrdiff_t ptrdiff(const void *a, const void *b)
> -{
> - return a - b;
> -}
> -
> static inline long
> i915_vma_compare(struct i915_vma *vma,
>struct i915_address_space *vm,
> --
> 2.28.0
>
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Re: [Intel-gfx] [RFC PATCH 07/97] drm/i915/guc: Remove sample_forcewake h2g action
On Thu, May 06, 2021 at 12:13:21PM -0700, Matthew Brost wrote:
> From: Rodrigo Vivi
>
> This action is no-op in the GuC side for a few versions already
> and it is getting entirely removed soon, in an upcoming version.
>
> Time to remove before we face communication issues.
>
> Cc: Vinay Belgaumkar
> Signed-off-by: Rodrigo Vivi
> Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 16
> drivers/gpu/drm/i915/gt/uc/intel_guc.h | 1 -
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 4
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4
> 4 files changed, 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index adae04c47aab..ab2c8fe8cdfa 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -469,22 +469,6 @@ int intel_guc_to_host_process_recv_msg(struct intel_guc
> *guc,
> return 0;
> }
>
> -int intel_guc_sample_forcewake(struct intel_guc *guc)
> -{
> - struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
> - u32 action[2];
> -
> - action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
> - /* WaRsDisableCoarsePowerGating:skl,cnl */
> - if (!HAS_RC6(dev_priv) || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
> - action[1] = 0;
> - else
> - /* bit 0 and 1 are for Render and Media domain separately */
> - action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
> -
> - return intel_guc_send(guc, action, ARRAY_SIZE(action));
> -}
> -
> /**
> * intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
> * @guc: intel_guc structure
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index bc2ba7d0626c..c20f3839de12 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -128,7 +128,6 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
> *action, u32 len,
> u32 *response_buf, u32 response_buf_size);
> int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
> const u32 *payload, u32 len);
> -int intel_guc_sample_forcewake(struct intel_guc *guc);
> int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
> int intel_guc_suspend(struct intel_guc *guc);
> int intel_guc_resume(struct intel_guc *guc);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> index 79c560d9c0b6..0f9afcde1d0b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> @@ -302,9 +302,6 @@ struct guc_ct_buffer_desc {
> #define GUC_CT_MSG_ACTION_SHIFT 16
> #define GUC_CT_MSG_ACTION_MASK 0x
>
> -#define GUC_FORCEWAKE_RENDER (1 << 0)
> -#define GUC_FORCEWAKE_MEDIA (1 << 1)
> -
> #define GUC_POWER_UNSPECIFIED0
> #define GUC_POWER_D0 1
> #define GUC_POWER_D1 2
> @@ -558,7 +555,6 @@ enum intel_guc_action {
> INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
> INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
> INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
> - INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x3005,
> INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
> INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
> INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index 892c1315ce49..ab0789d66e06 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -502,10 +502,6 @@ static int __uc_init_hw(struct intel_uc *uc)
>
> intel_huc_auth(huc);
>
> - ret = intel_guc_sample_forcewake(guc);
> - if (ret)
> - goto err_log_capture;
> -
> if (intel_uc_uses_guc_submission(uc))
> intel_guc_submission_enable(guc);
>
> --
> 2.28.0
>
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Re: [Intel-gfx] [RFC PATCH 06/97] drm/i915/guc: enable only the user interrupt when using GuC submission
On Thu, May 06, 2021 at 12:13:20PM -0700, Matthew Brost wrote:
> From: Daniele Ceraolo Spurio
>
> In GuC submission mode the CS is owned by the GuC FW, so all CS status
> interrupts are handled by it. We only need the user interrupt as that
> signals request completion.
>
> Since we're now starting the engines directly in GuC submission mode
> when selected, we can stop switching back and forth between the
> execlists and the GuC programming and select directly the correct
> interrupt mask.
>
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
> Cc: John Harrison
> Cc: Michal Wajdeczko
> ---
> drivers/gpu/drm/i915/gt/intel_gt_irq.c| 18 ++-
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 31 ---
> 2 files changed, 11 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index d29126c458ba..f88c10366e58 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -194,14 +194,18 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
>
> void gen11_gt_irq_postinstall(struct intel_gt *gt)
> {
> - const u32 irqs =
> - GT_CS_MASTER_ERROR_INTERRUPT |
> - GT_RENDER_USER_INTERRUPT |
> - GT_CONTEXT_SWITCH_INTERRUPT |
> - GT_WAIT_SEMAPHORE_INTERRUPT;
> struct intel_uncore *uncore = gt->uncore;
> - const u32 dmask = irqs << 16 | irqs;
> - const u32 smask = irqs << 16;
> + u32 irqs = GT_RENDER_USER_INTERRUPT;
> + u32 dmask;
> + u32 smask;
> +
> + if (!intel_uc_wants_guc_submission(>uc))
> + irqs |= GT_CS_MASTER_ERROR_INTERRUPT |
> + GT_CONTEXT_SWITCH_INTERRUPT |
> + GT_WAIT_SEMAPHORE_INTERRUPT;
> +
> + dmask = irqs << 16 | irqs;
> + smask = irqs << 16;
>
> BUILD_BUG_ON(irqs & 0x);
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 335719f17490..38cda5d599a6 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -432,32 +432,6 @@ void intel_guc_submission_fini(struct intel_guc *guc)
> }
> }
>
> -static void guc_interrupts_capture(struct intel_gt *gt)
> -{
> - struct intel_uncore *uncore = gt->uncore;
> - u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT;
> - u32 dmask = irqs << 16 | irqs;
> -
> - GEM_BUG_ON(INTEL_GEN(gt->i915) < 11);
> -
> - /* Don't handle the ctx switch interrupt in GuC submission mode */
> - intel_uncore_rmw(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask, 0);
> - intel_uncore_rmw(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask, 0);
> -}
> -
> -static void guc_interrupts_release(struct intel_gt *gt)
> -{
> - struct intel_uncore *uncore = gt->uncore;
> - u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT;
> - u32 dmask = irqs << 16 | irqs;
> -
> - GEM_BUG_ON(INTEL_GEN(gt->i915) < 11);
> -
> - /* Handle ctx switch interrupts again */
> - intel_uncore_rmw(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0, dmask);
> - intel_uncore_rmw(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0, dmask);
> -}
> -
> static int guc_context_alloc(struct intel_context *ce)
> {
> return lrc_alloc(ce, ce->engine);
> @@ -722,9 +696,6 @@ int intel_guc_submission_setup(struct intel_engine_cs
> *engine)
> void intel_guc_submission_enable(struct intel_guc *guc)
> {
> guc_stage_desc_init(guc);
> -
> - /* Take over from manual control of ELSP (execlists) */
> - guc_interrupts_capture(guc_to_gt(guc));
> }
>
> void intel_guc_submission_disable(struct intel_guc *guc)
> @@ -735,8 +706,6 @@ void intel_guc_submission_disable(struct intel_guc *guc)
>
> /* Note: By the time we're here, GuC may have already been reset */
>
> - guc_interrupts_release(gt);
> -
> guc_stage_desc_fini(guc);
> }
>
> --
> 2.28.0
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/adlp: Require DPT FB CCS color planes to be 2MB aligned
== Series Details == Series: series starting with [1/3] drm/i915/adlp: Require DPT FB CCS color planes to be 2MB aligned URL : https://patchwork.freedesktop.org/series/90484/ State : success == Summary == CI Bug Log - changes from CI_DRM_10127_full -> Patchwork_20180_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_20180_full that come from known issues: ### CI changes ### Possible fixes * boot: - shard-skl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [FAIL][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) ([i915#3174]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl1/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl1/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl8/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl8/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl8/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl8/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl7/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl7/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl7/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl7/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl6/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl6/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl6/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl6/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl4/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl4/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl4/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl3/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl3/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl10/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl10/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl10/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl10/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl1/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl1/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/shard-skl8/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/shard-skl8/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/shard-skl7/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/shard-skl7/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/shard-skl7/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/shard-skl7/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/shard-skl6/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/shard-skl6/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/shard-skl6/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/shard-skl6/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/shard-skl4/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/shard-skl4/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/shard-skl4/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/shard-skl3/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/shard-skl3/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/shard-skl3/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/shard-skl10/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/shard-skl10/boot.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/shard-skl10/boot.html [45]:
Re: [Intel-gfx] [RFC PATCH 08/97] drm/i915/guc: Keep strict GuC ABI definitions
Quoting Matthew Brost (2021-05-06 21:13:22) > From: Michal Wajdeczko > > Our fwif.h file is now mix of strict firmware ABI definitions and > set of our helpers. In anticipation of upcoming changes to the GuC > interface try to keep them separate in smaller maintainable files. > > Signed-off-by: Michal Wajdeczko > Signed-off-by: Matthew Brost > Cc: Michał Winiarski Reviewed-by: Michał Winiarski -Michał > --- > .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 51 + > .../gt/uc/abi/guc_communication_ctb_abi.h | 106 + > .../gt/uc/abi/guc_communication_mmio_abi.h| 52 + > .../gpu/drm/i915/gt/uc/abi/guc_errors_abi.h | 14 ++ > .../gpu/drm/i915/gt/uc/abi/guc_messages_abi.h | 21 ++ > drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 203 +- > 6 files changed, 250 insertions(+), 197 deletions(-) > create mode 100644 drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h > create mode 100644 drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h > create mode 100644 > drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h > create mode 100644 drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h > create mode 100644 drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for GPD Win Max display fixes
== Series Details == Series: GPD Win Max display fixes URL : https://patchwork.freedesktop.org/series/90483/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10127_full -> Patchwork_20179_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_20179_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20179_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_20179_full: ### IGT changes ### Possible regressions * igt@i915_pm_rpm@system-suspend-modeset: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-iclb5/igt@i915_pm_...@system-suspend-modeset.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/shard-iclb4/igt@i915_pm_...@system-suspend-modeset.html Known issues Here are the changes found in Patchwork_20179_full that come from known issues: ### CI changes ### Possible fixes * boot: - shard-skl: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [FAIL][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27]) ([i915#3174]) -> ([PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl8/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl8/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl8/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl8/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl7/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl7/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl7/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl7/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl6/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl6/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl6/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl6/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl4/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl4/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl4/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl3/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl3/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl10/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl10/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl10/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl10/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl1/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl1/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl1/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/shard-skl1/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/shard-skl8/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/shard-skl8/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/shard-skl8/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/shard-skl7/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/shard-skl7/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/shard-skl7/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/shard-skl6/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/shard-skl6/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/shard-skl4/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/shard-skl4/boot.html [38]:
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/display/adl_p: Drop earlier return in tc_has_modular_fia()
== Series Details ==
Series: series starting with [1/5] drm/i915/display/adl_p: Drop earlier return
in tc_has_modular_fia()
URL : https://patchwork.freedesktop.org/series/90495/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10128 -> Patchwork_20184
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20184/index.html
Known issues
Here are the changes found in Patchwork_20184 that come from known issues:
### IGT changes ###
Warnings
* igt@i915_selftest@live@execlists:
- fi-icl-u2: [DMESG-FAIL][1] ([i915#3462]) -> [INCOMPLETE][2]
([i915#2782] / [i915#3462])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10128/fi-icl-u2/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20184/fi-icl-u2/igt@i915_selftest@l...@execlists.html
* igt@runner@aborted:
- fi-skl-6600u: [FAIL][3] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][4] ([i915#1436] / [i915#3363])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10128/fi-skl-6600u/igt@run...@aborted.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20184/fi-skl-6600u/igt@run...@aborted.html
- fi-icl-u2: [FAIL][5] ([i915#2426] / [i915#2782] / [i915#3363])
-> [FAIL][6] ([i915#2782] / [i915#3363])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10128/fi-icl-u2/igt@run...@aborted.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20184/fi-icl-u2/igt@run...@aborted.html
- fi-glk-dsi: [FAIL][7] ([i915#2426] / [i915#3363] /
[k.org#202321]) -> [FAIL][8] ([i915#3363] / [k.org#202321])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10128/fi-glk-dsi/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20184/fi-glk-dsi/igt@run...@aborted.html
- fi-kbl-r: [FAIL][9] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][10] ([i915#1436] / [i915#3363])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10128/fi-kbl-r/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20184/fi-kbl-r/igt@run...@aborted.html
- fi-cml-u2: [FAIL][11] ([i915#3363] / [i915#3462]) -> [FAIL][12]
([i915#2082] / [i915#2426] / [i915#3363] / [i915#3462])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10128/fi-cml-u2/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20184/fi-cml-u2/igt@run...@aborted.html
- fi-cfl-guc: [FAIL][13] ([i915#2426] / [i915#3363]) -> [FAIL][14]
([i915#3363])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10128/fi-cfl-guc/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20184/fi-cfl-guc/igt@run...@aborted.html
- fi-kbl-7567u: [FAIL][15] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][16] ([i915#1436] / [i915#3363])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10128/fi-kbl-7567u/igt@run...@aborted.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20184/fi-kbl-7567u/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1222]: https://gitlab.freedesktop.org/drm/intel/issues/1222
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2082]: https://gitlab.freedesktop.org/drm/intel/issues/2082
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#3004]: https://gitlab.freedesktop.org/drm/intel/issues/3004
[i915#3005]: https://gitlab.freedesktop.org/drm/intel/issues/3005
[i915#3011]: https://gitlab.freedesktop.org/drm/intel/issues/3011
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3013]: https://gitlab.freedesktop.org/drm/intel/issues/3013
[i915#3014]: https://gitlab.freedesktop.org/drm/intel/issues/3014
[i915#3015]: https://gitlab.freedesktop.org/drm/intel/issues/3015
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
[i915#533]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915/display/adl_p: Drop earlier return in tc_has_modular_fia()
== Series Details == Series: series starting with [1/5] drm/i915/display/adl_p: Drop earlier return in tc_has_modular_fia() URL : https://patchwork.freedesktop.org/series/90495/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1887:21:expected struct i915_vma *[assigned] vma +drivers/gpu/drm/i915/display/intel_display.c:1887:21:got void [noderef] __iomem *[assigned] iomem +drivers/gpu/drm/i915/display/intel_display.c:1887:21: warning: incorrect type in assignment (different address spaces) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for dma-buf: Add an API for exporting sync files (v10)
== Series Details ==
Series: dma-buf: Add an API for exporting sync files (v10)
URL : https://patchwork.freedesktop.org/series/90491/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10128 -> Patchwork_20183
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20183/index.html
Known issues
Here are the changes found in Patchwork_20183 that come from known issues:
### IGT changes ###
Warnings
* igt@i915_selftest@live@execlists:
- fi-icl-u2: [DMESG-FAIL][1] ([i915#3462]) -> [INCOMPLETE][2]
([i915#2782] / [i915#3462])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10128/fi-icl-u2/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20183/fi-icl-u2/igt@i915_selftest@l...@execlists.html
* igt@runner@aborted:
- fi-skl-6600u: [FAIL][3] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][4] ([i915#1436] / [i915#3363])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10128/fi-skl-6600u/igt@run...@aborted.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20183/fi-skl-6600u/igt@run...@aborted.html
- fi-icl-u2: [FAIL][5] ([i915#2426] / [i915#2782] / [i915#3363])
-> [FAIL][6] ([i915#2782] / [i915#3363])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10128/fi-icl-u2/igt@run...@aborted.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20183/fi-icl-u2/igt@run...@aborted.html
- fi-kbl-r: [FAIL][7] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][8] ([i915#1436] / [i915#3363])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10128/fi-kbl-r/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20183/fi-kbl-r/igt@run...@aborted.html
- fi-cfl-guc: [FAIL][9] ([i915#2426] / [i915#3363]) -> [FAIL][10]
([i915#3363])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10128/fi-cfl-guc/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20183/fi-cfl-guc/igt@run...@aborted.html
- fi-kbl-7567u: [FAIL][11] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][12] ([i915#1436] / [i915#3363])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10128/fi-kbl-7567u/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20183/fi-kbl-7567u/igt@run...@aborted.html
- fi-skl-6700k2: [FAIL][13] ([i915#1436] / [i915#3363]) -> [FAIL][14]
([i915#1436] / [i915#2426] / [i915#3363])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10128/fi-skl-6700k2/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20183/fi-skl-6700k2/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1222]: https://gitlab.freedesktop.org/drm/intel/issues/1222
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#3004]: https://gitlab.freedesktop.org/drm/intel/issues/3004
[i915#3005]: https://gitlab.freedesktop.org/drm/intel/issues/3005
[i915#3011]: https://gitlab.freedesktop.org/drm/intel/issues/3011
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3013]: https://gitlab.freedesktop.org/drm/intel/issues/3013
[i915#3014]: https://gitlab.freedesktop.org/drm/intel/issues/3014
[i915#3015]: https://gitlab.freedesktop.org/drm/intel/issues/3015
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Participating hosts (34 -> 34)
--
Additional (2): fi-ehl-2 fi-hsw-gt1
Missing(2): fi-bsw-cyan fi-bdw-samus
Build changes
-
* IGT: IGT_6092 -> IGTPW_5846
* Linux: CI_DRM_10128 -> Patchwork_20183
CI-20190529: 20190529
CI_DRM_10128: a65996afe32761b9eef973bf230a566f38ac3340 @
git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5846:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for dma-buf: Add an API for exporting sync files (v10)
== Series Details == Series: dma-buf: Add an API for exporting sync files (v10) URL : https://patchwork.freedesktop.org/series/90491/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for dma-buf: Add an API for exporting sync files (v10)
== Series Details == Series: dma-buf: Add an API for exporting sync files (v10) URL : https://patchwork.freedesktop.org/series/90491/ State : warning == Summary == $ dim checkpatch origin/drm-tip 24b0f0b1996a dma-buf: add dma_fence_array_for_each (v2) -:73: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'fence' - possible side-effects? #73: FILE: include/linux/dma-fence-array.h:86: +#define dma_fence_array_for_each(fence, index, head) \ + for (index = 0, fence = dma_fence_array_first(head); fence; \ +++(index), fence = dma_fence_array_next(head, index)) -:73: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects? #73: FILE: include/linux/dma-fence-array.h:86: +#define dma_fence_array_for_each(fence, index, head) \ + for (index = 0, fence = dma_fence_array_first(head); fence; \ +++(index), fence = dma_fence_array_next(head, index)) -:73: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'head' - possible side-effects? #73: FILE: include/linux/dma-fence-array.h:86: +#define dma_fence_array_for_each(fence, index, head) \ + for (index = 0, fence = dma_fence_array_first(head); fence; \ +++(index), fence = dma_fence_array_next(head, index)) -:88: ERROR:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author '"Christian König" ' total: 1 errors, 0 warnings, 3 checks, 57 lines checked 0087839c7fb5 dma-buf: Rename dma_resv helpers from _rcu to _unlocked -:24: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #24: FILE: drivers/dma-buf/dma-buf.c:1151: + ret = dma_resv_wait_timeout_unlocked(resv, write, true, MAX_SCHEDULE_TIMEOUT); -:50: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int *' to bare use of 'unsigned *' #50: FILE: drivers/dma-buf/dma-resv.c:434: +unsigned *pshared_count, -:124: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #124: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:207: + r = dma_resv_get_fences_unlocked(new_abo->tbo.base.resv, >excl, >shared_count, -:150: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #150: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c:475: + ret = dma_resv_wait_timeout_unlocked(robj->tbo.base.resv, true, true, timeout); -:172: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #172: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c:160: + dma_resv_wait_timeout_unlocked(resv, true, false, MAX_SCHEDULE_TIMEOUT); -:185: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #185: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:79: + r = dma_resv_wait_timeout_unlocked(bo->tbo.base.resv, true, false, MAX_SCHEDULE_TIMEOUT); -:198: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #198: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:760: + r = dma_resv_wait_timeout_unlocked(bo->tbo.base.resv, false, false, MAX_SCHEDULE_TIMEOUT); -:211: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #211: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c:1130: + r = dma_resv_wait_timeout_unlocked(bo->tbo.base.resv, true, false, -:224: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #224: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:2026: + r = dma_resv_get_fences_unlocked(resv, , _count, ); -:231: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #231: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:2032: + dma_resv_wait_timeout_unlocked(resv, true, false, MAX_SCHEDULE_TIMEOUT); -:249: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #249: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:2824: + timeout = dma_resv_wait_timeout_unlocked(vm->root.base.bo->tbo.base.resv, true, true, timeout); -:262: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #262: FILE: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:8404: + r = dma_resv_wait_timeout_unlocked(abo->tbo.base.resv, true, false, -:275: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #275: FILE: drivers/gpu/drm/drm_gem.c:774: + ret = dma_resv_wait_timeout_unlocked(obj->resv, wait_all, true, timeout); -:290: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open
Re: [Intel-gfx] [PATCH 5/5] drm/i915/display/adl_p: Disable PSR2
On 5/24/21 2:48 PM, José Roberto de Souza wrote:
We are missing the implementation of some workarounds to enabled PSR2
in Alderlake P, so to avoid any CI report of issues around PSR2
disabling it until all PSR2 workarounds are implemented.
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_psr.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index c57210862206..46bd77669ead 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -765,6 +765,16 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
return false;
}
+ /*
+* We are missing the implementation of some workarounds to enabled PSR2
+* also Windows team found issues in this stepping that are causing
+* issues in most PSR2 panels.
+*/
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ drm_dbg_kms(_priv->drm, "PSR2 is missing the implementation of
workarounds\n");
+ return false;
+ }
+
if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) {
drm_dbg_kms(_priv->drm,
"PSR2 not supported in transcoder %s\n",
Reviewed-by: Clint Taylor
-Clint
___
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Re: [Intel-gfx] [PATCH 4/5] drm/i915/display/adl_p: Allow DC3CO in pipe and port B
On 5/24/21 2:48 PM, José Roberto de Souza wrote:
DC3CO is allowed in all the combinations between pipe and port A and B
on alderlake-P.
BSpec: 49196
Cc: Anshuman Gupta
Cc: Gwan-gyeong Mun
Cc: Matt Atwood
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_psr.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 216626444c76..c57210862206 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -646,12 +646,26 @@ static void tgl_disallow_dc3co_on_psr2_exit(struct
intel_dp *intel_dp)
tgl_psr2_disable_dc3co(intel_dp);
}
+static bool
+dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ enum port port = dig_port->base.port;
+
+ if (IS_ALDERLAKE_P(dev_priv))
+ return pipe <= PIPE_B && port <= PORT_B;
+ else
+ return pipe == PIPE_A && port == PORT_A;
+}
+
static void
tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state)
{
const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay;
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 exit_scanlines;
@@ -672,9 +686,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
if (!(dev_priv->dmc.allowed_dc_mask & DC_STATE_EN_DC3CO))
return;
- /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
- if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A ||
- dig_port->base.port != PORT_A)
+ if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
return;
/*
Reviewed-by: Clint Taylor
-Clint
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Re: [Intel-gfx] [PATCH 3/5] drm/i915: WA for zero memory channel
On 5/24/21 2:48 PM, José Roberto de Souza wrote:
Commit c457d9cf256e ("drm/i915: Make sure we have enough memory
bandwidth on ICL") assumes that we always have a non-zero
dram_info->channels and uses it as a divisor.
We need num memory channels to be at least 1 for sane bw limits
checking, even when PCode returns 0 or there is a error reading it, so
lets force it to 1 in this case.
Cc: Stanislav Lisovskiy
Cc: Rodrigo Vivi
Cc: Ville Syrjälä
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 3a1ba52266a7..bfb398f0432e 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -162,7 +162,7 @@ static int icl_get_bw_info(struct drm_i915_private
*dev_priv, const struct intel
{
struct intel_qgv_info qi = {};
bool is_y_tile = true; /* assume y tile may be used */
- int num_channels = dev_priv->dram_info.num_channels;
+ int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels);
int deinterleave;
int ipqdepth, ipqdepthpch;
int dclk_max;
Reviewed-by: Clint Taylor
-Clint
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Re: [Intel-gfx] [PATCH 2/5] drm/i915/adl_p: Handle TC cold
On 5/24/21 2:48 PM, José Roberto de Souza wrote:
On ADL-P TC cold is exited and blocked when legacy aux is powered,
that is exacly the same of what ICL need for static TC ports.
TODO: When a TBT hub or monitor is connected it will cause TBT and
legacy aux to be powered at the same time, hopefully this will not
cause any issues but if it do, some rework will be needed.
v2:
- skip icl_tc_port_assert_ref_held() warn on, adl-p uses aux to
block TC cold
v3:
- Drop icl_tc_port_assert_ref_held() earlier return for adl_p, not
needed anymore
- Set timeout_expected when enabling aux power well as port could be
disconnected when tc_cold_block() is called
BSpec: 55480
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6 ++
drivers/gpu/drm/i915/display/intel_tc.c| 14 ++
drivers/gpu/drm/i915/display/intel_tc.h| 2 ++
3 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 991ceea06a07..2f7d1664c473 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -619,11 +619,9 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private
*dev_priv,
* or need to enable AUX on a legacy TypeC port as part of the TC-cold
* exit sequence.
*/
- timeout_expected = is_tbt;
- if (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port) {
+ timeout_expected = is_tbt || intel_tc_cold_requires_aux_pw(dig_port);
+ if (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port)
icl_tc_cold_exit(dev_priv);
- timeout_expected = true;
- }
hsw_wait_for_power_well_enable(dev_priv, power_well, timeout_expected);
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index db85e0e2031e..c23c210a55f5 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -26,9 +26,7 @@ static const char *tc_port_mode_name(enum tc_port_mode mode)
static enum intel_display_power_domain
tc_cold_get_power_domain(struct intel_digital_port *dig_port)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
-
- if (DISPLAY_VER(i915) == 11)
+ if (intel_tc_cold_requires_aux_pw(dig_port))
return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
else
return POWER_DOMAIN_TC_COLD_OFF;
@@ -564,7 +562,7 @@ static void intel_tc_port_reset_mode(struct
intel_digital_port *dig_port,
enum tc_port_mode old_tc_mode = dig_port->tc_mode;
intel_display_power_flush_work(i915);
- if (DISPLAY_VER(i915) != 11 || !dig_port->tc_legacy_port) {
+ if (!intel_tc_cold_requires_aux_pw(dig_port)) {
enum intel_display_power_domain aux_domain;
bool aux_powered;
@@ -781,3 +779,11 @@ void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
dig_port->tc_link_refcount = 0;
tc_port_load_fia_params(i915, dig_port);
}
+
+bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+
+ return (DISPLAY_VER(i915) == 11 && dig_port->tc_legacy_port) ||
+ IS_ALDERLAKE_P(i915);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_tc.h
b/drivers/gpu/drm/i915/display/intel_tc.h
index b619e4736f85..0eacbd76ec15 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.h
+++ b/drivers/gpu/drm/i915/display/intel_tc.h
@@ -29,4 +29,6 @@ bool intel_tc_port_ref_held(struct intel_digital_port
*dig_port);
void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy);
+bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port);
+
#endif /* __INTEL_TC_H__ */
Reviewed-by: Clint Taylor
-Clint
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Re: [Intel-gfx] [PATCH 1/5] drm/i915/display/adl_p: Drop earlier return in tc_has_modular_fia()
On 5/24/21 2:48 PM, José Roberto de Souza wrote: MODULAR_FIA_MASK is set in adl_p so we can drop this ealier return and read registers. Also to avoid warnings from icl_tc_port_assert_ref_held() when calling tc_cold_block() in this functions it is necessary to held the lock. Cc: Imre Deak Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_tc.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 5f03215a03e4..db85e0e2031e 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -734,13 +734,11 @@ tc_has_modular_fia(struct drm_i915_private *i915, struct intel_digital_port *dig if (!INTEL_INFO(i915)->display.has_modular_fia) return false; - /* TODO: check if in real HW MODULAR_FIA_MASK is set, if so remove this block */ - if (IS_ALDERLAKE_P(i915)) - return true; - + mutex_lock(_port->tc_lock); wakeref = tc_cold_block(dig_port); val = intel_uncore_read(>uncore, PORT_TX_DFLEXDPSP(FIA1)); tc_cold_unblock(dig_port, wakeref); + mutex_unlock(_port->tc_lock); drm_WARN_ON(>drm, val == 0x); Reviewed-by: Clint Taylor -Clint ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/7] drm/i915/dmc: Introduce DMC_FW_MAIN
On Mon, 2021-05-24 at 12:30 -0700, Anusha Srivatsa wrote:
> This is a prep patch for Pipe DMC plugging.
>
> Add dmc_info struct in intel_dmc to have all common fields
> shared between all DMC's in the package.
> Add DMC_FW_MAIN(dmc_id 0) to refer to the blob.
>
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 44 +++-
> drivers/gpu/drm/i915/display/intel_dmc.h | 20 ---
> 2 files changed, 35 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index f9a0f194f9cf..16bfbca6c1ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -239,7 +239,7 @@ struct stepping_info {
>
> bool intel_dmc_has_payload(struct drm_i915_private *i915)
> {
> - return i915->dmc.dmc_payload;
> + return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
> }
>
> static const struct stepping_info skl_stepping_info[] = {
> @@ -316,7 +316,8 @@ static void gen9_set_dc_state_debugmask(struct
> drm_i915_private *dev_priv)
> */
> void intel_dmc_load_program(struct drm_i915_private *dev_priv)
> {
> - u32 *payload = dev_priv->dmc.dmc_payload;
> + struct intel_dmc *dmc = _priv->dmc;
> + struct dmc_fw_info *dmc_info = >dmc_info[DMC_FW_MAIN];
> u32 i, fw_size;
>
> if (!HAS_DMC(dev_priv)) {
> @@ -325,26 +326,26 @@ void intel_dmc_load_program(struct drm_i915_private
> *dev_priv)
> return;
> }
>
> - if (!intel_dmc_has_payload(dev_priv)) {
> + if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) {
> drm_err(_priv->drm,
> "Tried to program CSR with empty payload\n");
> return;
> }
>
> - fw_size = dev_priv->dmc.dmc_fw_size;
> + fw_size = dmc_info->dmc_fw_size;
> assert_rpm_wakelock_held(_priv->runtime_pm);
>
> preempt_disable();
>
> for (i = 0; i < fw_size; i++)
> intel_uncore_write_fw(_priv->uncore, DMC_PROGRAM(i),
> - payload[i]);
> + dmc_info->payload[i]);
>
> preempt_enable();
>
> - for (i = 0; i < dev_priv->dmc.mmio_count; i++) {
> - intel_de_write(dev_priv, dev_priv->dmc.mmioaddr[i],
> -dev_priv->dmc.mmiodata[i]);
> + for (i = 0; i < dmc_info->mmio_count; i++) {
> + intel_de_write(dev_priv, dmc_info->mmioaddr[i],
> +dmc_info->mmiodata[i]);
> }
>
> dev_priv->dmc.dc_state = 0;
> @@ -401,13 +402,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> size_t rem_size)
> {
> struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
> + struct dmc_fw_info *dmc_info = >dmc_info[DMC_FW_MAIN];
> unsigned int header_len_bytes, dmc_header_size, payload_size, i;
> const u32 *mmioaddr, *mmiodata;
> u32 mmio_count, mmio_count_max;
> u8 *payload;
>
> - BUILD_BUG_ON(ARRAY_SIZE(dmc->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
> - ARRAY_SIZE(dmc->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
> + BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
> + ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
>
> /*
>* Check if we can access common fields, we will checkc again below
> @@ -463,16 +465,10 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> }
>
> for (i = 0; i < mmio_count; i++) {
> - if (mmioaddr[i] < DMC_MMIO_START_RANGE ||
> - mmioaddr[i] > DMC_MMIO_END_RANGE) {
> - drm_err(>drm, "DMC firmware has wrong mmio
> address 0x%x\n",
> - mmioaddr[i]);
> - return 0;
> - }
Why the checks above were dropped?
> - dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
> - dmc->mmiodata[i] = mmiodata[i];
> + dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
> + dmc_info->mmiodata[i] = mmiodata[i];
> }
> - dmc->mmio_count = mmio_count;
> + dmc_info->mmio_count = mmio_count;
>
> rem_size -= header_len_bytes;
>
> @@ -485,16 +481,16 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> drm_err(>drm, "DMC FW too big (%u bytes)\n",
> payload_size);
> return 0;
> }
> - dmc->dmc_fw_size = dmc_header->fw_size;
> + dmc_info->dmc_fw_size = dmc_header->fw_size;
Did not read the next patches but the if possible would be better to rename
dmc_info to dmc_main_info or dmc_pipe_info when possible.
>
> - dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
> - if (!dmc->dmc_payload) {
> + dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);
> + if (!dmc_info->payload) {
> drm_err(>drm, "Memory allocation failed for dmc
>
Re: [Intel-gfx] [PATCH 3/7] drm/i915/dmc: Move struct intel_dmc to intel_dmc.h
On Mon, 2021-05-24 at 12:30 -0700, Anusha Srivatsa wrote:
> Move struct intel_dmc from i915_drv.h to intel_dmc.h.
Reviewed-by: José Roberto de Souza
>
> v2: Add includes along with moving the struct.
>
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/display/intel_dmc.h | 21 +
> drivers/gpu/drm/i915/i915_drv.h | 18 +-
> 2 files changed, 22 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h
> b/drivers/gpu/drm/i915/display/intel_dmc.h
> index 64816f4a71b6..4c22f567b61b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> @@ -6,12 +6,33 @@
> #ifndef __INTEL_DMC_H__
> #define __INTEL_DMC_H__
>
> +#include "i915_reg.h"
> +#include "intel_wakeref.h"
> +#include
> +
> struct drm_i915_private;
>
> #define DMC_VERSION(major, minor)((major) << 16 | (minor))
> #define DMC_VERSION_MAJOR(version) ((version) >> 16)
> #define DMC_VERSION_MINOR(version) ((version) & 0x)
>
> +struct intel_dmc {
> + struct work_struct work;
> + const char *fw_path;
> + u32 required_version;
> + u32 max_fw_size; /* bytes */
> + u32 *dmc_payload;
> + u32 dmc_fw_size; /* dwords */
> + u32 version;
> + u32 mmio_count;
> + i915_reg_t mmioaddr[20];
> + u32 mmiodata[20];
> + u32 dc_state;
> + u32 target_dc_state;
> + u32 allowed_dc_mask;
> + intel_wakeref_t wakeref;
> +};
> +
> void intel_dmc_ucode_init(struct drm_i915_private *i915);
> void intel_dmc_load_program(struct drm_i915_private *i915);
> void intel_dmc_ucode_fini(struct drm_i915_private *i915);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 9cb02618ba15..b5962768a1f1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -67,6 +67,7 @@
> #include "display/intel_bios.h"
> #include "display/intel_display.h"
> #include "display/intel_display_power.h"
> +#include "display/intel_dmc.h"
> #include "display/intel_dpll_mgr.h"
> #include "display/intel_dsb.h"
> #include "display/intel_frontbuffer.h"
> @@ -328,23 +329,6 @@ struct drm_i915_display_funcs {
> void (*read_luts)(struct intel_crtc_state *crtc_state);
> };
>
> -struct intel_dmc {
> - struct work_struct work;
> - const char *fw_path;
> - u32 required_version;
> - u32 max_fw_size; /* bytes */
> - u32 *dmc_payload;
> - u32 dmc_fw_size; /* dwords */
> - u32 version;
> - u32 mmio_count;
> - i915_reg_t mmioaddr[20];
> - u32 mmiodata[20];
> - u32 dc_state;
> - u32 target_dc_state;
> - u32 allowed_dc_mask;
> - intel_wakeref_t wakeref;
> -};
> -
> enum i915_cache_level {
> I915_CACHE_NONE = 0,
> I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
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[Intel-gfx] [PATCH 1/5] drm/i915/display/adl_p: Drop earlier return in tc_has_modular_fia()
MODULAR_FIA_MASK is set in adl_p so we can drop this ealier return and read registers. Also to avoid warnings from icl_tc_port_assert_ref_held() when calling tc_cold_block() in this functions it is necessary to held the lock. Cc: Imre Deak Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_tc.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 5f03215a03e4..db85e0e2031e 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -734,13 +734,11 @@ tc_has_modular_fia(struct drm_i915_private *i915, struct intel_digital_port *dig if (!INTEL_INFO(i915)->display.has_modular_fia) return false; - /* TODO: check if in real HW MODULAR_FIA_MASK is set, if so remove this block */ - if (IS_ALDERLAKE_P(i915)) - return true; - + mutex_lock(_port->tc_lock); wakeref = tc_cold_block(dig_port); val = intel_uncore_read(>uncore, PORT_TX_DFLEXDPSP(FIA1)); tc_cold_unblock(dig_port, wakeref); + mutex_unlock(_port->tc_lock); drm_WARN_ON(>drm, val == 0x); -- 2.31.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/5] drm/i915/display/adl_p: Allow DC3CO in pipe and port B
DC3CO is allowed in all the combinations between pipe and port A and B
on alderlake-P.
BSpec: 49196
Cc: Anshuman Gupta
Cc: Gwan-gyeong Mun
Cc: Matt Atwood
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_psr.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 216626444c76..c57210862206 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -646,12 +646,26 @@ static void tgl_disallow_dc3co_on_psr2_exit(struct
intel_dp *intel_dp)
tgl_psr2_disable_dc3co(intel_dp);
}
+static bool
+dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ enum port port = dig_port->base.port;
+
+ if (IS_ALDERLAKE_P(dev_priv))
+ return pipe <= PIPE_B && port <= PORT_B;
+ else
+ return pipe == PIPE_A && port == PORT_A;
+}
+
static void
tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state)
{
const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay;
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 exit_scanlines;
@@ -672,9 +686,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
if (!(dev_priv->dmc.allowed_dc_mask & DC_STATE_EN_DC3CO))
return;
- /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
- if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A ||
- dig_port->base.port != PORT_A)
+ if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
return;
/*
--
2.31.1
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[Intel-gfx] [PATCH 5/5] drm/i915/display/adl_p: Disable PSR2
We are missing the implementation of some workarounds to enabled PSR2
in Alderlake P, so to avoid any CI report of issues around PSR2
disabling it until all PSR2 workarounds are implemented.
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_psr.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index c57210862206..46bd77669ead 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -765,6 +765,16 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
return false;
}
+ /*
+* We are missing the implementation of some workarounds to enabled PSR2
+* also Windows team found issues in this stepping that are causing
+* issues in most PSR2 panels.
+*/
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ drm_dbg_kms(_priv->drm, "PSR2 is missing the implementation
of workarounds\n");
+ return false;
+ }
+
if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) {
drm_dbg_kms(_priv->drm,
"PSR2 not supported in transcoder %s\n",
--
2.31.1
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[Intel-gfx] [PATCH 3/5] drm/i915: WA for zero memory channel
Commit c457d9cf256e ("drm/i915: Make sure we have enough memory
bandwidth on ICL") assumes that we always have a non-zero
dram_info->channels and uses it as a divisor.
We need num memory channels to be at least 1 for sane bw limits
checking, even when PCode returns 0 or there is a error reading it, so
lets force it to 1 in this case.
Cc: Stanislav Lisovskiy
Cc: Rodrigo Vivi
Cc: Ville Syrjälä
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 3a1ba52266a7..bfb398f0432e 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -162,7 +162,7 @@ static int icl_get_bw_info(struct drm_i915_private
*dev_priv, const struct intel
{
struct intel_qgv_info qi = {};
bool is_y_tile = true; /* assume y tile may be used */
- int num_channels = dev_priv->dram_info.num_channels;
+ int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels);
int deinterleave;
int ipqdepth, ipqdepthpch;
int dclk_max;
--
2.31.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/5] drm/i915/adl_p: Handle TC cold
On ADL-P TC cold is exited and blocked when legacy aux is powered,
that is exacly the same of what ICL need for static TC ports.
TODO: When a TBT hub or monitor is connected it will cause TBT and
legacy aux to be powered at the same time, hopefully this will not
cause any issues but if it do, some rework will be needed.
v2:
- skip icl_tc_port_assert_ref_held() warn on, adl-p uses aux to
block TC cold
v3:
- Drop icl_tc_port_assert_ref_held() earlier return for adl_p, not
needed anymore
- Set timeout_expected when enabling aux power well as port could be
disconnected when tc_cold_block() is called
BSpec: 55480
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6 ++
drivers/gpu/drm/i915/display/intel_tc.c| 14 ++
drivers/gpu/drm/i915/display/intel_tc.h| 2 ++
3 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 991ceea06a07..2f7d1664c473 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -619,11 +619,9 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private
*dev_priv,
* or need to enable AUX on a legacy TypeC port as part of the TC-cold
* exit sequence.
*/
- timeout_expected = is_tbt;
- if (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port) {
+ timeout_expected = is_tbt || intel_tc_cold_requires_aux_pw(dig_port);
+ if (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port)
icl_tc_cold_exit(dev_priv);
- timeout_expected = true;
- }
hsw_wait_for_power_well_enable(dev_priv, power_well, timeout_expected);
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index db85e0e2031e..c23c210a55f5 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -26,9 +26,7 @@ static const char *tc_port_mode_name(enum tc_port_mode mode)
static enum intel_display_power_domain
tc_cold_get_power_domain(struct intel_digital_port *dig_port)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
-
- if (DISPLAY_VER(i915) == 11)
+ if (intel_tc_cold_requires_aux_pw(dig_port))
return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
else
return POWER_DOMAIN_TC_COLD_OFF;
@@ -564,7 +562,7 @@ static void intel_tc_port_reset_mode(struct
intel_digital_port *dig_port,
enum tc_port_mode old_tc_mode = dig_port->tc_mode;
intel_display_power_flush_work(i915);
- if (DISPLAY_VER(i915) != 11 || !dig_port->tc_legacy_port) {
+ if (!intel_tc_cold_requires_aux_pw(dig_port)) {
enum intel_display_power_domain aux_domain;
bool aux_powered;
@@ -781,3 +779,11 @@ void intel_tc_port_init(struct intel_digital_port
*dig_port, bool is_legacy)
dig_port->tc_link_refcount = 0;
tc_port_load_fia_params(i915, dig_port);
}
+
+bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+
+ return (DISPLAY_VER(i915) == 11 && dig_port->tc_legacy_port) ||
+ IS_ALDERLAKE_P(i915);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_tc.h
b/drivers/gpu/drm/i915/display/intel_tc.h
index b619e4736f85..0eacbd76ec15 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.h
+++ b/drivers/gpu/drm/i915/display/intel_tc.h
@@ -29,4 +29,6 @@ bool intel_tc_port_ref_held(struct intel_digital_port
*dig_port);
void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy);
+bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port);
+
#endif /* __INTEL_TC_H__ */
--
2.31.1
___
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[Intel-gfx] [PATCH 6/6] RFC: dma-buf: Add an API for importing sync files (v6)
This patch is analogous to the previous sync file export patch in that
it allows you to import a sync_file into a dma-buf. Unlike the previous
patch, however, this does add genuinely new functionality to dma-buf.
Without this, the only way to attach a sync_file to a dma-buf is to
submit a batch to your driver of choice which waits on the sync_file and
claims to write to the dma-buf. Even if said batch is a no-op, a submit
is typically way more overhead than just attaching a fence. A submit
may also imply extra synchronization with other work because it happens
on a hardware queue.
In the Vulkan world, this is useful for dealing with the out-fence from
vkQueuePresent. Current Linux window-systems (X11, Wayland, etc.) all
rely on dma-buf implicit sync. Since Vulkan is an explicit sync API, we
get a set of fences (VkSemaphores) in vkQueuePresent and have to stash
those as an exclusive (write) fence on the dma-buf. We handle it in
Mesa today with the above mentioned dummy submit trick. This ioctl
would allow us to set it directly without the dummy submit.
This may also open up possibilities for GPU drivers to move away from
implicit sync for their kernel driver uAPI and instead provide sync
files and rely on dma-buf import/export for communicating with other
implicit sync clients.
We make the explicit choice here to only allow setting RW fences which
translates to an exclusive fence on the dma_resv. There's no use for
read-only fences for communicating with other implicit sync userspace
and any such attempts are likely to be racy at best. When we got to
insert the RW fence, the actual fence we set as the new exclusive fence
is a combination of the sync_file provided by the user and all the other
fences on the dma_resv. This ensures that the newly added exclusive
fence will never signal before the old one would have and ensures that
we don't break any dma_resv contracts. We require userspace to specify
RW in the flags for symmetry with the export ioctl and in case we ever
want to support read fences in the future.
There is one downside here that's worth documenting: If two clients
writing to the same dma-buf using this API race with each other, their
actions on the dma-buf may happen in parallel or in an undefined order.
Both with and without this API, the pattern is the same: Collect all
the fences on dma-buf, submit work which depends on said fences, and
then set a new exclusive (write) fence on the dma-buf which depends on
said work. The difference is that, when it's all handled by the GPU
driver's submit ioctl, the three operations happen atomically under the
dma_resv lock. If two userspace submits race, one will happen before
the other. You aren't guaranteed which but you are guaranteed that
they're strictly ordered. If userspace manages the fences itself, then
these three operations happen separately and the two render operations
may happen genuinely in parallel or get interleaved. However, this is a
case of userspace racing with itself. As long as we ensure userspace
can't back the kernel into a corner, it should be fine.
v2 (Jason Ekstrand):
- Use a wrapper dma_fence_array of all fences including the new one
when importing an exclusive fence.
v3 (Jason Ekstrand):
- Lock around setting shared fences as well as exclusive
- Mark SIGNAL_SYNC_FILE as a read-write ioctl.
- Initialize ret to 0 in dma_buf_wait_sync_file
v4 (Jason Ekstrand):
- Use the new dma_resv_get_singleton helper
v5 (Jason Ekstrand):
- Rename the IOCTLs to import/export rather than wait/signal
- Drop the WRITE flag and always get/set the exclusive fence
v5 (Jason Ekstrand):
- Split import and export into separate patches
- New commit message
Signed-off-by: Jason Ekstrand
---
drivers/dma-buf/dma-buf.c| 34 ++
include/uapi/linux/dma-buf.h | 1 +
2 files changed, 35 insertions(+)
diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
index f23d939e0e833..0a50c19dcf015 100644
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@ -419,6 +419,38 @@ static long dma_buf_export_sync_file(struct dma_buf
*dmabuf,
put_unused_fd(fd);
return ret;
}
+
+static long dma_buf_import_sync_file(struct dma_buf *dmabuf,
+const void __user *user_data)
+{
+ struct dma_buf_sync_file arg;
+ struct dma_fence *fence, *singleton = NULL;
+ int ret = 0;
+
+ if (copy_from_user(, user_data, sizeof(arg)))
+ return -EFAULT;
+
+ if (arg.flags != DMA_BUF_SYNC_RW)
+ return -EINVAL;
+
+ fence = sync_file_get_fence(arg.fd);
+ if (!fence)
+ return -EINVAL;
+
+ dma_resv_lock(dmabuf->resv, NULL);
+
+ singleton = dma_resv_get_singleton_unlocked(dmabuf->resv, fence);
+ if (IS_ERR(singleton))
+ ret = PTR_ERR(singleton);
+ else if (singleton)
+ dma_resv_add_excl_fence(dmabuf->resv, singleton);
+
[Intel-gfx] [PATCH 2/6] dma-buf: Rename dma_resv helpers from _rcu to _unlocked
None of these helpers actually leak any RCU details to the caller. They
all assume you have a genuine reference, take the RCU read lock, and
retry if needed. Naming them with an _rcu is likely to cause callers
more panic than needed.
Signed-off-by: Jason Ekstrand
Suggested-by: Daniel Vetter
---
drivers/dma-buf/dma-buf.c | 2 +-
drivers/dma-buf/dma-resv.c| 28 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 4 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c| 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 8 +++---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu/drm/drm_gem.c | 6 ++--
drivers/gpu/drm/drm_gem_atomic_helper.c | 2 +-
drivers/gpu/drm/etnaviv/etnaviv_gem.c | 4 +--
drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 4 +--
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/dma_resv_utils.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_busy.c | 2 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_object.h| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_wait.c | 10 +++
drivers/gpu/drm/i915/i915_request.c | 4 +--
drivers/gpu/drm/i915/i915_sw_fence.c | 4 +--
drivers/gpu/drm/msm/msm_gem.c | 2 +-
drivers/gpu/drm/nouveau/dispnv50/wndw.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_gem.c | 2 +-
drivers/gpu/drm/panfrost/panfrost_drv.c | 2 +-
drivers/gpu/drm/panfrost/panfrost_job.c | 2 +-
drivers/gpu/drm/radeon/radeon_gem.c | 6 ++--
drivers/gpu/drm/radeon/radeon_mn.c| 2 +-
drivers/gpu/drm/ttm/ttm_bo.c | 12
drivers/gpu/drm/vgem/vgem_fence.c | 2 +-
drivers/gpu/drm/virtio/virtgpu_ioctl.c| 4 +--
drivers/gpu/drm/vmwgfx/vmwgfx_bo.c| 2 +-
include/linux/dma-resv.h | 18 ++--
36 files changed, 79 insertions(+), 79 deletions(-)
diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
index f264b70c383eb..d4529aa9d1a5a 100644
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@ -1147,7 +1147,7 @@ static int __dma_buf_begin_cpu_access(struct dma_buf
*dmabuf,
long ret;
/* Wait on any implicit rendering fences */
- ret = dma_resv_wait_timeout_rcu(resv, write, true,
+ ret = dma_resv_wait_timeout_unlocked(resv, write, true,
MAX_SCHEDULE_TIMEOUT);
if (ret < 0)
return ret;
diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c
index 6ddbeb5dfbf65..d6f1ed4cd4d55 100644
--- a/drivers/dma-buf/dma-resv.c
+++ b/drivers/dma-buf/dma-resv.c
@@ -417,7 +417,7 @@ int dma_resv_copy_fences(struct dma_resv *dst, struct
dma_resv *src)
EXPORT_SYMBOL(dma_resv_copy_fences);
/**
- * dma_resv_get_fences_rcu - Get an object's shared and exclusive
+ * dma_resv_get_fences_unlocked - Get an object's shared and exclusive
* fences without update side lock held
* @obj: the reservation object
* @pfence_excl: the returned exclusive fence (or NULL)
@@ -429,10 +429,10 @@ EXPORT_SYMBOL(dma_resv_copy_fences);
* exclusive fence is not specified the fence is put into the array of the
* shared fences as well. Returns either zero or -ENOMEM.
*/
-int dma_resv_get_fences_rcu(struct dma_resv *obj,
- struct dma_fence **pfence_excl,
- unsigned *pshared_count,
- struct dma_fence ***pshared)
+int dma_resv_get_fences_unlocked(struct dma_resv *obj,
+struct dma_fence **pfence_excl,
+unsigned *pshared_count,
+struct dma_fence ***pshared)
{
struct dma_fence **shared = NULL;
struct dma_fence *fence_excl;
@@ -515,10 +515,10 @@ int dma_resv_get_fences_rcu(struct dma_resv *obj,
*pshared = shared;
return ret;
}
-EXPORT_SYMBOL_GPL(dma_resv_get_fences_rcu);
+EXPORT_SYMBOL_GPL(dma_resv_get_fences_unlocked);
/**
- * dma_resv_wait_timeout_rcu - Wait on reservation's objects
+ * dma_resv_wait_timeout_unlocked - Wait on reservation's objects
* shared and/or exclusive fences.
* @obj: the reservation object
* @wait_all: if true, wait on all fences, else wait on just exclusive fence
@@ -529,9 +529,9 @@ EXPORT_SYMBOL_GPL(dma_resv_get_fences_rcu);
* Returns -ERESTARTSYS if interrupted, 0 if the wait timed out, or
* greater than zer on success.
*/
-long dma_resv_wait_timeout_rcu(struct
[Intel-gfx] [PATCH 1/6] dma-buf: add dma_fence_array_for_each (v2)
From: Christian König
Add a helper to iterate over all fences in a dma_fence_array object.
v2 (Jason Ekstrand)
- Return NULL from dma_fence_array_first if head == NULL. This matches
the iterator behavior of dma_fence_chain_for_each in that it iterates
zero times if head == NULL.
- Return NULL from dma_fence_array_next if index > array->num_fences.
Signed-off-by: Jason Ekstrand
Reviewed-by: Jason Ekstrand
Reviewed-by: Christian König
---
drivers/dma-buf/dma-fence-array.c | 27 +++
include/linux/dma-fence-array.h | 17 +
2 files changed, 44 insertions(+)
diff --git a/drivers/dma-buf/dma-fence-array.c
b/drivers/dma-buf/dma-fence-array.c
index d3fbd950be944..2ac1afc697d0f 100644
--- a/drivers/dma-buf/dma-fence-array.c
+++ b/drivers/dma-buf/dma-fence-array.c
@@ -201,3 +201,30 @@ bool dma_fence_match_context(struct dma_fence *fence, u64
context)
return true;
}
EXPORT_SYMBOL(dma_fence_match_context);
+
+struct dma_fence *dma_fence_array_first(struct dma_fence *head)
+{
+ struct dma_fence_array *array;
+
+ if (!head)
+ return NULL;
+
+ array = to_dma_fence_array(head);
+ if (!array)
+ return head;
+
+ return array->fences[0];
+}
+EXPORT_SYMBOL(dma_fence_array_first);
+
+struct dma_fence *dma_fence_array_next(struct dma_fence *head,
+ unsigned int index)
+{
+ struct dma_fence_array *array = to_dma_fence_array(head);
+
+ if (!array || index >= array->num_fences)
+ return NULL;
+
+ return array->fences[index];
+}
+EXPORT_SYMBOL(dma_fence_array_next);
diff --git a/include/linux/dma-fence-array.h b/include/linux/dma-fence-array.h
index 303dd712220fd..588ac8089dd61 100644
--- a/include/linux/dma-fence-array.h
+++ b/include/linux/dma-fence-array.h
@@ -74,6 +74,19 @@ to_dma_fence_array(struct dma_fence *fence)
return container_of(fence, struct dma_fence_array, base);
}
+/**
+ * dma_fence_array_for_each - iterate over all fences in array
+ * @fence: current fence
+ * @index: index into the array
+ * @head: potential dma_fence_array object
+ *
+ * Test if @array is a dma_fence_array object and if yes iterate over all
fences
+ * in the array. If not just iterate over the fence in @array itself.
+ */
+#define dma_fence_array_for_each(fence, index, head) \
+ for (index = 0, fence = dma_fence_array_first(head); fence; \
+++(index), fence = dma_fence_array_next(head, index))
+
struct dma_fence_array *dma_fence_array_create(int num_fences,
struct dma_fence **fences,
u64 context, unsigned seqno,
@@ -81,4 +94,8 @@ struct dma_fence_array *dma_fence_array_create(int num_fences,
bool dma_fence_match_context(struct dma_fence *fence, u64 context);
+struct dma_fence *dma_fence_array_first(struct dma_fence *head);
+struct dma_fence *dma_fence_array_next(struct dma_fence *head,
+ unsigned int index);
+
#endif /* __LINUX_DMA_FENCE_ARRAY_H */
--
2.31.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/6] dma-buf: add dma_resv_get_singleton_unlocked (v4)
Add a helper function to get a single fence representing
all fences in a dma_resv object.
This fence is either the only one in the object or all not
signaled fences of the object in a flatted out dma_fence_array.
v2 (Jason Ekstrand):
- Take reference of fences both for creating the dma_fence_array and in
the case where we return one fence.
- Handle the case where dma_resv_get_list() returns NULL
v3 (Jason Ekstrand):
- Add an _rcu suffix because it is read-only
- Rewrite to use dma_resv_get_fences_rcu so it's RCU-safe
- Add an EXPORT_SYMBOL_GPL declaration
- Re-author the patch to Jason since very little is left of Christian
König's original patch
- Remove the extra fence argument
v4 (Jason Ekstrand):
- Restore the extra fence argument
v5 (Daniel Vetter):
- Rename from _rcu to _unlocked since it doesn't leak RCU details to
the caller
- Fix docs
- Use ERR_PTR for error handling rather than an output dma_fence**
v5 (Jason Ekstrand):
- Drop the extra fence param and leave that to a separate patch
Signed-off-by: Jason Ekstrand
Reviewed-by: Daniel Vetter
---
drivers/dma-buf/dma-resv.c | 93 ++
include/linux/dma-resv.h | 2 +
2 files changed, 95 insertions(+)
diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c
index d6f1ed4cd4d55..312a3a59dac6a 100644
--- a/drivers/dma-buf/dma-resv.c
+++ b/drivers/dma-buf/dma-resv.c
@@ -33,6 +33,8 @@
*/
#include
+#include
+#include
#include
#include
#include
@@ -49,6 +51,11 @@
* write-side updates.
*/
+/* deep dive into the fence containers */
+#define dma_fence_deep_dive_for_each(fence, chain, index, head)\
+ dma_fence_chain_for_each(chain, head) \
+ dma_fence_array_for_each(fence, index, chain)
+
DEFINE_WD_CLASS(reservation_ww_class);
EXPORT_SYMBOL(reservation_ww_class);
@@ -517,6 +524,92 @@ int dma_resv_get_fences_unlocked(struct dma_resv *obj,
}
EXPORT_SYMBOL_GPL(dma_resv_get_fences_unlocked);
+/**
+ * dma_resv_get_singleton_unlocked - get a single fence for the dma_resv object
+ * @obj: the reservation object
+ * @result: resulting dma_fence
+ *
+ * Get a single fence representing all unsignaled fences in the dma_resv object
+ * plus the given extra fence. If we got only one fence return a new
+ * reference to that, otherwise return a dma_fence_array object.
+ *
+ * RETURNS
+ * Returns -NOMEM if allocations fail, zero otherwise.
+ */
+struct dma_fence *dma_resv_get_singleton_unlocked(struct dma_resv *obj)
+{
+ struct dma_fence *result, **resv_fences, *fence, *chain, **fences;
+ struct dma_fence_array *array;
+ unsigned int num_resv_fences, num_fences;
+ unsigned int err, i, j;
+
+ err = dma_resv_get_fences_unlocked(obj, NULL, _resv_fences,
_fences);
+ if (err)
+ return ERR_PTR(err);
+
+ if (num_resv_fences == 0)
+ return NULL;
+
+ num_fences = 0;
+ result = NULL;
+
+ for (i = 0; i < num_resv_fences; ++i) {
+ dma_fence_deep_dive_for_each(fence, chain, j, resv_fences[i]) {
+ if (dma_fence_is_signaled(fence))
+ continue;
+
+ result = fence;
+ ++num_fences;
+ }
+ }
+
+ if (num_fences <= 1) {
+ result = dma_fence_get(result);
+ goto put_resv_fences;
+ }
+
+ fences = kmalloc_array(num_fences, sizeof(struct dma_fence*),
+ GFP_KERNEL);
+ if (!fences) {
+ result = ERR_PTR(-ENOMEM);
+ goto put_resv_fences;
+ }
+
+ num_fences = 0;
+ for (i = 0; i < num_resv_fences; ++i) {
+ dma_fence_deep_dive_for_each(fence, chain, j, resv_fences[i]) {
+ if (!dma_fence_is_signaled(fence))
+ fences[num_fences++] = dma_fence_get(fence);
+ }
+ }
+
+ if (num_fences <= 1) {
+ result = num_fences ? fences[0] : NULL;
+ kfree(fences);
+ goto put_resv_fences;
+ }
+
+ array = dma_fence_array_create(num_fences, fences,
+ dma_fence_context_alloc(1),
+ 1, false);
+ if (array) {
+ result = >base;
+ } else {
+ result = ERR_PTR(-ENOMEM);
+ while (num_fences--)
+ dma_fence_put(fences[num_fences]);
+ kfree(fences);
+ }
+
+put_resv_fences:
+ while (num_resv_fences--)
+ dma_fence_put(resv_fences[num_resv_fences]);
+ kfree(resv_fences);
+
+ return result;
+}
+EXPORT_SYMBOL_GPL(dma_resv_get_singleton_unlocked);
+
/**
* dma_resv_wait_timeout_unlocked - Wait on reservation's objects
* shared and/or exclusive fences.
diff --git a/include/linux/dma-resv.h b/include/linux/dma-resv.h
[Intel-gfx] [PATCH 4/6] dma-buf: Add an API for exporting sync files (v9)
Modern userspace APIs like Vulkan are built on an explicit
synchronization model. This doesn't always play nicely with the
implicit synchronization used in the kernel and assumed by X11 and
Wayland. The client -> compositor half of the synchronization isn't too
bad, at least on intel, because we can control whether or not i915
synchronizes on the buffer and whether or not it's considered written.
The harder part is the compositor -> client synchronization when we get
the buffer back from the compositor. We're required to be able to
provide the client with a VkSemaphore and VkFence representing the point
in time where the window system (compositor and/or display) finished
using the buffer. With current APIs, it's very hard to do this in such
a way that we don't get confused by the Vulkan driver's access of the
buffer. In particular, once we tell the kernel that we're rendering to
the buffer again, any CPU waits on the buffer or GPU dependencies will
wait on some of the client rendering and not just the compositor.
This new IOCTL solves this problem by allowing us to get a snapshot of
the implicit synchronization state of a given dma-buf in the form of a
sync file. It's effectively the same as a poll() or I915_GEM_WAIT only,
instead of CPU waiting directly, it encapsulates the wait operation, at
the current moment in time, in a sync_file so we can check/wait on it
later. As long as the Vulkan driver does the sync_file export from the
dma-buf before we re-introduce it for rendering, it will only contain
fences from the compositor or display. This allows to accurately turn
it into a VkFence or VkSemaphore without any over- synchronization.
v2 (Jason Ekstrand):
- Use a wrapper dma_fence_array of all fences including the new one
when importing an exclusive fence.
v3 (Jason Ekstrand):
- Lock around setting shared fences as well as exclusive
- Mark SIGNAL_SYNC_FILE as a read-write ioctl.
- Initialize ret to 0 in dma_buf_wait_sync_file
v4 (Jason Ekstrand):
- Use the new dma_resv_get_singleton helper
v5 (Jason Ekstrand):
- Rename the IOCTLs to import/export rather than wait/signal
- Drop the WRITE flag and always get/set the exclusive fence
v6 (Jason Ekstrand):
- Drop the sync_file import as it was all-around sketchy and not nearly
as useful as import.
- Re-introduce READ/WRITE flag support for export
- Rework the commit message
v7 (Jason Ekstrand):
- Require at least one sync flag
- Fix a refcounting bug: dma_resv_get_excl() doesn't take a reference
- Use _rcu helpers since we're accessing the dma_resv read-only
v8 (Jason Ekstrand):
- Return -ENOMEM if the sync_file_create fails
- Predicate support on IS_ENABLED(CONFIG_SYNC_FILE)
v9 (Jason Ekstrand):
- Add documentation for the new ioctl
v10 (Jason Ekstrand):
- Go back to dma_buf_sync_file as the ioctl struct name
Signed-off-by: Jason Ekstrand
Acked-by: Simon Ser
Acked-by: Christian König
---
drivers/dma-buf/dma-buf.c| 64
include/uapi/linux/dma-buf.h | 24 ++
2 files changed, 88 insertions(+)
diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
index d4529aa9d1a5a..86efe71c0db96 100644
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -362,6 +363,64 @@ static long dma_buf_set_name(struct dma_buf *dmabuf, const
char __user *buf)
return ret;
}
+#if IS_ENABLED(CONFIG_SYNC_FILE)
+static long dma_buf_export_sync_file(struct dma_buf *dmabuf,
+void __user *user_data)
+{
+ struct dma_buf_sync_file arg;
+ struct dma_fence *fence = NULL;
+ struct sync_file *sync_file;
+ int fd, ret;
+
+ if (copy_from_user(, user_data, sizeof(arg)))
+ return -EFAULT;
+
+ if (arg.flags & ~DMA_BUF_SYNC_RW)
+ return -EINVAL;
+
+ if ((arg.flags & DMA_BUF_SYNC_RW) == 0)
+ return -EINVAL;
+
+ fd = get_unused_fd_flags(O_CLOEXEC);
+ if (fd < 0)
+ return fd;
+
+ if (arg.flags & DMA_BUF_SYNC_WRITE) {
+ fence = dma_resv_get_singleton_unlocked(dmabuf->resv);
+ if (IS_ERR(fence)) {
+ ret = PTR_ERR(fence);
+ goto err_put_fd;
+ }
+ } else if (arg.flags & DMA_BUF_SYNC_READ) {
+ fence = dma_resv_get_excl_unlocked(dmabuf->resv);
+ }
+
+ if (!fence)
+ fence = dma_fence_get_stub();
+
+ sync_file = sync_file_create(fence);
+
+ dma_fence_put(fence);
+
+ if (!sync_file) {
+ ret = -ENOMEM;
+ goto err_put_fd;
+ }
+
+ fd_install(fd, sync_file->file);
+
+ arg.fd = fd;
+ if (copy_to_user(user_data, , sizeof(arg)))
+ return -EFAULT;
+
+ return 0;
+
+err_put_fd:
+ put_unused_fd(fd);
+ return ret;
+}
+#endif
[Intel-gfx] [PATCH 5/6] RFC: dma-buf: Add an extra fence to dma_resv_get_singleton_unlocked
For dma-buf sync_file import, we want to get all the fences on a
dma_resv plus one more. We could wrap the fence we get back in an array
fence or we could make dma_resv_get_singleton_unlocked take "one more"
to make this case easier.
Signed-off-by: Jason Ekstrand
---
drivers/dma-buf/dma-buf.c | 2 +-
drivers/dma-buf/dma-resv.c | 23 +--
include/linux/dma-resv.h | 3 ++-
3 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
index 86efe71c0db96..f23d939e0e833 100644
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@ -386,7 +386,7 @@ static long dma_buf_export_sync_file(struct dma_buf *dmabuf,
return fd;
if (arg.flags & DMA_BUF_SYNC_WRITE) {
- fence = dma_resv_get_singleton_unlocked(dmabuf->resv);
+ fence = dma_resv_get_singleton_unlocked(dmabuf->resv, NULL);
if (IS_ERR(fence)) {
ret = PTR_ERR(fence);
goto err_put_fd;
diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c
index 312a3a59dac6a..3c0ef8d0f599b 100644
--- a/drivers/dma-buf/dma-resv.c
+++ b/drivers/dma-buf/dma-resv.c
@@ -527,6 +527,7 @@ EXPORT_SYMBOL_GPL(dma_resv_get_fences_unlocked);
/**
* dma_resv_get_singleton_unlocked - get a single fence for the dma_resv object
* @obj: the reservation object
+ * @extra: extra fence to add to the resulting array
* @result: resulting dma_fence
*
* Get a single fence representing all unsignaled fences in the dma_resv object
@@ -536,7 +537,8 @@ EXPORT_SYMBOL_GPL(dma_resv_get_fences_unlocked);
* RETURNS
* Returns -NOMEM if allocations fail, zero otherwise.
*/
-struct dma_fence *dma_resv_get_singleton_unlocked(struct dma_resv *obj)
+struct dma_fence *dma_resv_get_singleton_unlocked(struct dma_resv *obj,
+ struct dma_fence *extra)
{
struct dma_fence *result, **resv_fences, *fence, *chain, **fences;
struct dma_fence_array *array;
@@ -547,7 +549,7 @@ struct dma_fence *dma_resv_get_singleton_unlocked(struct
dma_resv *obj)
if (err)
return ERR_PTR(err);
- if (num_resv_fences == 0)
+ if (num_resv_fences == 0 && !extra)
return NULL;
num_fences = 0;
@@ -563,6 +565,16 @@ struct dma_fence *dma_resv_get_singleton_unlocked(struct
dma_resv *obj)
}
}
+ if (extra) {
+ dma_fence_deep_dive_for_each(fence, chain, j, extra) {
+ if (dma_fence_is_signaled(fence))
+ continue;
+
+ result = fence;
+ ++num_fences;
+ }
+ }
+
if (num_fences <= 1) {
result = dma_fence_get(result);
goto put_resv_fences;
@@ -583,6 +595,13 @@ struct dma_fence *dma_resv_get_singleton_unlocked(struct
dma_resv *obj)
}
}
+ if (extra) {
+ dma_fence_deep_dive_for_each(fence, chain, j, extra) {
+ if (dma_fence_is_signaled(fence))
+ fences[num_fences++] = dma_fence_get(fence);
+ }
+ }
+
if (num_fences <= 1) {
result = num_fences ? fences[0] : NULL;
kfree(fences);
diff --git a/include/linux/dma-resv.h b/include/linux/dma-resv.h
index c529ccee94bc5..156d989e95ab4 100644
--- a/include/linux/dma-resv.h
+++ b/include/linux/dma-resv.h
@@ -285,7 +285,8 @@ int dma_resv_get_fences_unlocked(struct dma_resv *obj,
int dma_resv_copy_fences(struct dma_resv *dst, struct dma_resv *src);
-struct dma_fence *dma_resv_get_singleton_unlocked(struct dma_resv *obj);
+struct dma_fence *dma_resv_get_singleton_unlocked(struct dma_resv *obj,
+ struct dma_fence *extra);
long dma_resv_wait_timeout_unlocked(struct dma_resv *obj, bool wait_all, bool
intr,
unsigned long timeout);
--
2.31.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/6] dma-buf: Add an API for exporting sync files (v10)
Modern userspace APIs like Vulkan are built on an explicit synchronization model. This doesn't always play nicely with the implicit synchronization used in the kernel and assumed by X11 and Wayland. The client -> compositor half of the synchronization isn't too bad, at least on intel, because we can control whether or not i915 synchronizes on the buffer and whether or not it's considered written. The harder part is the compositor -> client synchronization when we get the buffer back from the compositor. We're required to be able to provide the client with a VkSemaphore and VkFence representing the point in time where the window system (compositor and/or display) finished using the buffer. With current APIs, it's very hard to do this in such a way that we don't get confused by the Vulkan driver's access of the buffer. In particular, once we tell the kernel that we're rendering to the buffer again, any CPU waits on the buffer or GPU dependencies will wait on some of the client rendering and not just the compositor. This new IOCTL solves this problem by allowing us to get a snapshot of the implicit synchronization state of a given dma-buf in the form of a sync file. It's effectively the same as a poll() or I915_GEM_WAIT only, instead of CPU waiting directly, it encapsulates the wait operation, at the current moment in time, in a sync_file so we can check/wait on it later. As long as the Vulkan driver does the sync_file export from the dma-buf before we re-introduce it for rendering, it will only contain fences from the compositor or display. This allows to accurately turn it into a VkFence or VkSemaphore without any over- synchronization. This patch series actually contains two new ioctls. There is the export one mentioned above as well as an RFC for an import ioctl which provides the other half. The intention is to land the export ioctl since it seems like there's no real disagreement on that one. The import ioctl, however, has a lot of debate around it so it's intended to be RFC-only for now. Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4037 IGT tests: https://patchwork.freedesktop.org/series/90490/ v10 (Jason Ekstrand, Daniel Vetter): - Add reviews/acks - Add a patch to rename _rcu to _unlocked - Split things better so import is clearly RFC status Cc: Christian König Cc: Michel Dänzer Cc: Dave Airlie Cc: Bas Nieuwenhuizen Cc: Daniel Stone Cc: mesa-...@lists.freedesktop.org Cc: wayland-de...@lists.freedesktop.org Test-with: 20210524205225.872316-1-ja...@jlekstrand.net Christian König (1): dma-buf: add dma_fence_array_for_each (v2) Jason Ekstrand (5): dma-buf: Rename dma_resv helpers from _rcu to _unlocked dma-buf: add dma_resv_get_singleton_unlocked (v4) dma-buf: Add an API for exporting sync files (v9) RFC: dma-buf: Add an extra fence to dma_resv_get_singleton_unlocked RFC: dma-buf: Add an API for importing sync files (v6) drivers/dma-buf/dma-buf.c | 100 - drivers/dma-buf/dma-fence-array.c | 27 drivers/dma-buf/dma-resv.c| 140 -- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c| 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 8 +- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/drm_gem.c | 6 +- drivers/gpu/drm/drm_gem_atomic_helper.c | 2 +- drivers/gpu/drm/etnaviv/etnaviv_gem.c | 4 +- drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 4 +- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/dma_resv_utils.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_busy.c | 2 +- .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 +- drivers/gpu/drm/i915/gem/i915_gem_object.h| 2 +- drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_wait.c | 10 +- drivers/gpu/drm/i915/i915_request.c | 4 +- drivers/gpu/drm/i915/i915_sw_fence.c | 4 +- drivers/gpu/drm/msm/msm_gem.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/wndw.c | 2 +- drivers/gpu/drm/nouveau/nouveau_gem.c | 2 +- drivers/gpu/drm/panfrost/panfrost_drv.c | 2 +- drivers/gpu/drm/panfrost/panfrost_job.c | 2 +- drivers/gpu/drm/radeon/radeon_gem.c | 6 +- drivers/gpu/drm/radeon/radeon_mn.c| 2 +- drivers/gpu/drm/ttm/ttm_bo.c | 12 +- drivers/gpu/drm/vgem/vgem_fence.c | 2 +- drivers/gpu/drm/virtio/virtgpu_ioctl.c| 4 +- drivers/gpu/drm/vmwgfx/vmwgfx_bo.c| 2 +-
[Intel-gfx] ✗ Fi.CI.BAT: failure for Pipe DMC Support (rev2)
== Series Details ==
Series: Pipe DMC Support (rev2)
URL : https://patchwork.freedesktop.org/series/90445/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10127 -> Patchwork_20182
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20182 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20182, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_20182:
### IGT changes ###
Possible regressions
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-skl-6700k2: [PASS][1] -> [DMESG-WARN][2] +3 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-skl-6600u: [PASS][3] -> [DMESG-WARN][4] +2 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-skl-6600u/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-skl-6600u/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {fi-tgl-dsi}: [FAIL][5] ([i915#1436] / [i915#2932] / [i915#2966])
-> [FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-tgl-dsi/igt@run...@aborted.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-tgl-dsi/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_20182 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-gfx:
- fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#109315]) +17
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-hsw-4770/igt@amdgpu/amd_ba...@cs-gfx.html
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][8] ([fdo#109271]) +17 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@core_hotunplug@unbind-rebind:
- fi-hsw-4770:NOTRUN -> [WARN][9] ([i915#2283])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-hsw-4770/igt@core_hotunp...@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-hsw-4770:NOTRUN -> [SKIP][10] ([fdo#109271]) +4 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-hsw-4770/igt@gem_huc_c...@huc-copy.html
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#3012])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6600u: [PASS][12] -> [SKIP][13] ([fdo#109271]) +2 similar
issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-skl-6600u/igt@i915_pm_...@module-reload.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-skl-6600u/igt@i915_pm_...@module-reload.html
- fi-skl-6700k2: [PASS][14] -> [SKIP][15] ([fdo#109271]) +2 similar
issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-skl-6700k2/igt@i915_pm_...@module-reload.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-skl-6700k2/igt@i915_pm_...@module-reload.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +8
similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-hsw-4770:NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#533])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_mmap_gtt:
- fi-hsw-4770:NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#1072]) +3
similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html
Possible fixes
* igt@gem_exec_suspend@basic-s0:
- fi-hsw-4770:[INCOMPLETE][19] -> [PASS][20]
[19]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Pipe DMC Support (rev2)
== Series Details == Series: Pipe DMC Support (rev2) URL : https://patchwork.freedesktop.org/series/90445/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1887:21:expected struct i915_vma *[assigned] vma +drivers/gpu/drm/i915/display/intel_display.c:1887:21:got void [noderef] __iomem *[assigned] iomem +drivers/gpu/drm/i915/display/intel_display.c:1887:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1329:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/intel_ring_submission.c:1203:24: warning: Using plain integer as NULL pointer +drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Pipe DMC Support (rev2)
== Series Details ==
Series: Pipe DMC Support (rev2)
URL : https://patchwork.freedesktop.org/series/90445/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e45725e49bdd drm/i915/dmc: s/DRM_ERROR/drm_err
-:80: WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
#80: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:487:
if (!dmc->dmc_payload) {
+ drm_err(>drm, "Memory allocation failed for dmc
payload\n");
total: 0 errors, 1 warnings, 0 checks, 140 lines checked
7cd57a2ac1a8 drm/i915/dmc: Add intel_dmc_has_payload() helper
bf455925 drm/i915/dmc: Move struct intel_dmc to intel_dmc.h
75f070edde6f drm/i915/dmc: Introduce DMC_FW_MAIN
11185b96af31 drm/i915/xelpd: Pipe A DMC plugging
-:39: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#39: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:587:
+ intel_de_read(dev_priv,
DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
-:54: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#54: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:965:
+
DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
-:147: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#147: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:387:
+ drm_notice(>drm, "Invalid firmware id:
%d\n", fw_info[i].dmc_id);
total: 0 errors, 3 warnings, 0 checks, 263 lines checked
f7ecd81b636d drm/i915/adl_p: Pipe B DMC Support
09bd925cfaf4 drm/i915/adl_p: Load DMC
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for More DMC cleanup (rev4)
== Series Details == Series: More DMC cleanup (rev4) URL : https://patchwork.freedesktop.org/series/90379/ State : success == Summary == CI Bug Log - changes from CI_DRM_10127 -> Patchwork_20181 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/index.html Known issues Here are the changes found in Patchwork_20181 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/fi-hsw-4770/igt@amdgpu/amd_ba...@cs-gfx.html * igt@core_hotunplug@unbind-rebind: - fi-hsw-4770:NOTRUN -> [WARN][2] ([i915#2283]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/fi-hsw-4770/igt@core_hotunp...@unbind-rebind.html * igt@gem_huc_copy@huc-copy: - fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/fi-hsw-4770/igt@gem_huc_c...@huc-copy.html * igt@i915_pm_backlight@basic-brightness: - fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#3012]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: [PASS][6] -> [DMESG-WARN][7] ([i915#2203] / [i915#2868]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#533]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@primary_mmap_gtt: - fi-hsw-4770:NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1072]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html Possible fixes * igt@gem_exec_suspend@basic-s0: - fi-hsw-4770:[INCOMPLETE][10] -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-hsw-4770/igt@gem_exec_susp...@basic-s0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/fi-hsw-4770/igt@gem_exec_susp...@basic-s0.html Warnings * igt@i915_selftest@live@execlists: - fi-bsw-nick:[DMESG-FAIL][12] ([i915#3462]) -> [INCOMPLETE][13] ([i915#2782] / [i915#2940] / [i915#3462]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@runner@aborted: - fi-skl-6600u: [FAIL][14] ([i915#1436] / [i915#3363]) -> [FAIL][15] ([i915#1436] / [i915#2426] / [i915#3363]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-skl-6600u/igt@run...@aborted.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/fi-skl-6600u/igt@run...@aborted.html - fi-glk-dsi: [FAIL][16] ([i915#3363] / [k.org#202321]) -> [FAIL][17] ([i915#2426] / [i915#3363] / [k.org#202321]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-glk-dsi/igt@run...@aborted.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/fi-glk-dsi/igt@run...@aborted.html - fi-cml-u2: [FAIL][18] ([i915#2082] / [i915#2426] / [i915#3363] / [i915#3462]) -> [FAIL][19] ([i915#3363] / [i915#3462]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-cml-u2/igt@run...@aborted.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/fi-cml-u2/igt@run...@aborted.html - fi-cfl-guc: [FAIL][20] ([i915#2426] / [i915#3363]) -> [FAIL][21] ([i915#3363]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-cfl-guc/igt@run...@aborted.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20181/fi-cfl-guc/igt@run...@aborted.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1436]:
Re: [Intel-gfx] [PATCH 3/3] drm: Add orientation quirk for GPD Win Max
Hi,
On 5/24/21 6:47 PM, Anisse Astier wrote:
> Panel is 800x1280, but mounted on a laptop form factor, sideways.
>
> Signed-off-by: Anisse Astier
Thanks, patch looks good to me:
Reviewed-by: Hans de Goede
Regards,
Hans
> ---
> drivers/gpu/drm/drm_panel_orientation_quirks.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c
> b/drivers/gpu/drm/drm_panel_orientation_quirks.c
> index f6bdec7fa925..3c3f4ed89173 100644
> --- a/drivers/gpu/drm/drm_panel_orientation_quirks.c
> +++ b/drivers/gpu/drm/drm_panel_orientation_quirks.c
> @@ -148,6 +148,12 @@ static const struct dmi_system_id orientation_data[] = {
> DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "MicroPC"),
> },
> .driver_data = (void *)_rightside_up,
> + }, {/* GPD Win Max */
> + .matches = {
> + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "GPD"),
> + DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "G1619-01"),
> + },
> + .driver_data = (void *)_rightside_up,
> }, {/*
>* GPD Pocket, note that the the DMI data is less generic then
>* it seems, devices with a board-vendor of "AMI Corporation"
>
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for More DMC cleanup (rev4)
== Series Details ==
Series: More DMC cleanup (rev4)
URL : https://patchwork.freedesktop.org/series/90379/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a62325931c20 drm/i915/dmc: s/DRM_ERROR/drm_err
-:80: WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
#80: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:487:
if (!dmc->dmc_payload) {
+ drm_err(>drm, "Memory allocation failed for dmc
payload\n");
total: 0 errors, 1 warnings, 0 checks, 140 lines checked
c2cbbb1b7bff drm/i915/dmc: Add intel_dmc_has_payload() helper
e0e29d94cf74 drm/i915/dmc: Move struct intel_dmc to intel_dmc.h
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[Intel-gfx] [PATCH 7/7] drm/i915/adl_p: Load DMC
Load DMC v2.06 on ADLP. The release notes mention that
this version enables few power savings features.
Cc: Lucas De Marchi
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 3b3bb15e6a24..e1a7426cb7b6 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -45,6 +45,10 @@
#define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
+#define ADLP_DMC_PATH "i915/adlp_dmc_ver2_10.bin"
+#define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 10)
+MODULE_FIRMWARE(ADLP_DMC_PATH);
+
#define ADLS_DMC_PATH DMC_PATH(adls, 2, 01)
#define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1)
MODULE_FIRMWARE(ADLS_DMC_PATH);
@@ -722,7 +726,11 @@ void intel_dmc_ucode_init(struct drm_i915_private
*dev_priv)
*/
intel_dmc_runtime_pm_get(dev_priv);
- if (IS_ALDERLAKE_S(dev_priv)) {
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ dmc->fw_path = ADLP_DMC_PATH;
+ dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
+ } else if (IS_ALDERLAKE_S(dev_priv)) {
dmc->fw_path = ADLS_DMC_PATH;
dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
--
2.25.0
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[Intel-gfx] [PATCH 6/7] drm/i915/adl_p: Pipe B DMC Support
ADLP requires us to load both Pipe A and Pipe B.
Plug Pipe B loading support.
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 ++
drivers/gpu/drm/i915/display/intel_dmc.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 2a1c39a0e56e..db38891a9ef0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -546,6 +546,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "path: %s\n", dmc->fw_path);
seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >=
12));
seq_printf(m, "Pipe A fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
+ seq_printf(m, "Pipe B fw support: %s\n",
yesno(IS_ALDERLAKE_P(dev_priv)));
+ seq_printf(m, "Pipe B fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEB].payload));
if (!intel_dmc_has_payload(dev_priv))
goto out;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h
b/drivers/gpu/drm/i915/display/intel_dmc.h
index 007a284b0ef0..c3c00ff03869 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -19,6 +19,7 @@ struct drm_i915_private;
enum {
DMC_FW_MAIN = 0,
DMC_FW_PIPEA,
+ DMC_FW_PIPEB,
DMC_FW_MAX
};
--
2.25.0
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[Intel-gfx] [PATCH 5/7] drm/i915/xelpd: Pipe A DMC plugging
This patch adds Pipe A plumbing to the already
existing parsing and loading functions which is
taken care of in the prep patches. Adding MAX_DMC_FW
to keep track for both Main and Pipe A DMC while loading
the respective blobs.
Also adding present field in dmc_info.
s/find_dmc_fw_offset/csr_set_dmc_fw_offset. While at it add
fw_info_matches_stepping() helper. CSR_PROGRAM() should now
take the starting address of the particular blob (Main or Pipe)
and not hardcode it.
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
.../drm/i915/display/intel_display_debugfs.c | 4 +-
.../drm/i915/display/intel_display_power.c| 5 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 121 ++
drivers/gpu/drm/i915/display/intel_dmc.h | 2 +
drivers/gpu/drm/i915/i915_reg.h | 2 +-
5 files changed, 79 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 88bb05d5c483..2a1c39a0e56e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -544,6 +544,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "fw loaded: %s\n",
yesno(intel_dmc_has_payload(dev_priv)));
seq_printf(m, "path: %s\n", dmc->fw_path);
+ seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >=
12));
+ seq_printf(m, "Pipe A fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
if (!intel_dmc_has_payload(dev_priv))
goto out;
@@ -582,7 +584,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
out:
seq_printf(m, "program base: 0x%08x\n",
- intel_de_read(dev_priv, DMC_PROGRAM(0)));
+ intel_de_read(dev_priv,
DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
seq_printf(m, "ssp base: 0x%08x\n",
intel_de_read(dev_priv, DMC_SSP_BASE));
seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, DMC_HTP_SKL));
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index b546672c9b00..dce7f1d1540f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -961,8 +961,9 @@ static void bxt_disable_dc9(struct drm_i915_private
*dev_priv)
static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
{
drm_WARN_ONCE(_priv->drm,
- !intel_de_read(dev_priv, DMC_PROGRAM(0)),
- "DMC program storage start is NULL\n");
+ !intel_de_read(dev_priv,
+
DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
+"DMC program storage start is NULL\n");
drm_WARN_ONCE(_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
"DMC SSP Base Not fine\n");
drm_WARN_ONCE(_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 16bfbca6c1ed..3b3bb15e6a24 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -317,8 +317,7 @@ static void gen9_set_dc_state_debugmask(struct
drm_i915_private *dev_priv)
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
struct intel_dmc *dmc = _priv->dmc;
- struct dmc_fw_info *dmc_info = >dmc_info[DMC_FW_MAIN];
- u32 i, fw_size;
+ u32 id, i;
if (!HAS_DMC(dev_priv)) {
drm_err(_priv->drm,
@@ -332,20 +331,25 @@ void intel_dmc_load_program(struct drm_i915_private
*dev_priv)
return;
}
- fw_size = dmc_info->dmc_fw_size;
assert_rpm_wakelock_held(_priv->runtime_pm);
preempt_disable();
- for (i = 0; i < fw_size; i++)
- intel_uncore_write_fw(_priv->uncore, DMC_PROGRAM(i),
- dmc_info->payload[i]);
+ for (id = 0; id < DMC_FW_MAX; id++) {
+ for (i = 0; i < dmc->dmc_info[id].dmc_fw_size; i++) {
+ intel_uncore_write_fw(_priv->uncore,
+
DMC_PROGRAM(dmc->dmc_info[id].start_mmioaddr, i),
+ dmc->dmc_info[id].payload[i]);
+ }
+ }
preempt_enable();
- for (i = 0; i < dmc_info->mmio_count; i++) {
- intel_de_write(dev_priv, dmc_info->mmioaddr[i],
- dmc_info->mmiodata[i]);
+ for (id = 0; id < DMC_FW_MAX; id++) {
+ for (i = 0; i < dmc->dmc_info[id].mmio_count; i++) {
+ intel_de_write(dev_priv, dmc->dmc_info[id].mmioaddr[i],
+
[Intel-gfx] [PATCH 3/7] drm/i915/dmc: Move struct intel_dmc to intel_dmc.h
Move struct intel_dmc from i915_drv.h to intel_dmc.h.
v2: Add includes along with moving the struct.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.h | 21 +
drivers/gpu/drm/i915/i915_drv.h | 18 +-
2 files changed, 22 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h
b/drivers/gpu/drm/i915/display/intel_dmc.h
index 64816f4a71b6..4c22f567b61b 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -6,12 +6,33 @@
#ifndef __INTEL_DMC_H__
#define __INTEL_DMC_H__
+#include "i915_reg.h"
+#include "intel_wakeref.h"
+#include
+
struct drm_i915_private;
#define DMC_VERSION(major, minor) ((major) << 16 | (minor))
#define DMC_VERSION_MAJOR(version) ((version) >> 16)
#define DMC_VERSION_MINOR(version) ((version) & 0x)
+struct intel_dmc {
+ struct work_struct work;
+ const char *fw_path;
+ u32 required_version;
+ u32 max_fw_size; /* bytes */
+ u32 *dmc_payload;
+ u32 dmc_fw_size; /* dwords */
+ u32 version;
+ u32 mmio_count;
+ i915_reg_t mmioaddr[20];
+ u32 mmiodata[20];
+ u32 dc_state;
+ u32 target_dc_state;
+ u32 allowed_dc_mask;
+ intel_wakeref_t wakeref;
+};
+
void intel_dmc_ucode_init(struct drm_i915_private *i915);
void intel_dmc_load_program(struct drm_i915_private *i915);
void intel_dmc_ucode_fini(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9cb02618ba15..b5962768a1f1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -67,6 +67,7 @@
#include "display/intel_bios.h"
#include "display/intel_display.h"
#include "display/intel_display_power.h"
+#include "display/intel_dmc.h"
#include "display/intel_dpll_mgr.h"
#include "display/intel_dsb.h"
#include "display/intel_frontbuffer.h"
@@ -328,23 +329,6 @@ struct drm_i915_display_funcs {
void (*read_luts)(struct intel_crtc_state *crtc_state);
};
-struct intel_dmc {
- struct work_struct work;
- const char *fw_path;
- u32 required_version;
- u32 max_fw_size; /* bytes */
- u32 *dmc_payload;
- u32 dmc_fw_size; /* dwords */
- u32 version;
- u32 mmio_count;
- i915_reg_t mmioaddr[20];
- u32 mmiodata[20];
- u32 dc_state;
- u32 target_dc_state;
- u32 allowed_dc_mask;
- intel_wakeref_t wakeref;
-};
-
enum i915_cache_level {
I915_CACHE_NONE = 0,
I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/7] drm/i915/dmc: Add intel_dmc_has_payload() helper
We check for dmc_payload being there at various points in the driver.
Replace it with the helper.
v2: rebased.
v3: Move intel_dmc to intel_dmc.h in another patch (Lucas)
v4: Remove headers not needed from intel_dmc.h
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
.../gpu/drm/i915/display/intel_display_debugfs.c | 4 ++--
.../gpu/drm/i915/display/intel_display_power.c | 16
drivers/gpu/drm/i915/display/intel_dmc.c | 13 +
drivers/gpu/drm/i915/display/intel_dmc.h | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c| 2 +-
5 files changed, 21 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 94e5cbd86e77..88bb05d5c483 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -542,10 +542,10 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
wakeref = intel_runtime_pm_get(_priv->runtime_pm);
- seq_printf(m, "fw loaded: %s\n", yesno(dmc->dmc_payload));
+ seq_printf(m, "fw loaded: %s\n",
yesno(intel_dmc_has_payload(dev_priv)));
seq_printf(m, "path: %s\n", dmc->fw_path);
- if (!dmc->dmc_payload)
+ if (!intel_dmc_has_payload(dev_priv))
goto out;
seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version),
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 991ceea06a07..b546672c9b00 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1220,7 +1220,7 @@ static void gen9_dc_off_power_well_enable(struct
drm_i915_private *dev_priv,
static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- if (!dev_priv->dmc.dmc_payload)
+ if (!intel_dmc_has_payload(dev_priv))
return;
switch (dev_priv->dmc.target_dc_state) {
@@ -5579,7 +5579,7 @@ static void skl_display_core_init(struct drm_i915_private
*dev_priv,
gen9_dbuf_enable(dev_priv);
- if (resume && dev_priv->dmc.dmc_payload)
+ if (resume && intel_dmc_has_payload(dev_priv))
intel_dmc_load_program(dev_priv);
}
@@ -5646,7 +5646,7 @@ static void bxt_display_core_init(struct drm_i915_private
*dev_priv, bool resume
gen9_dbuf_enable(dev_priv);
- if (resume && dev_priv->dmc.dmc_payload)
+ if (resume && intel_dmc_has_payload(dev_priv))
intel_dmc_load_program(dev_priv);
}
@@ -5712,7 +5712,7 @@ static void cnl_display_core_init(struct drm_i915_private
*dev_priv, bool resume
/* 6. Enable DBUF */
gen9_dbuf_enable(dev_priv);
- if (resume && dev_priv->dmc.dmc_payload)
+ if (resume && intel_dmc_has_payload(dev_priv))
intel_dmc_load_program(dev_priv);
}
@@ -5869,7 +5869,7 @@ static void icl_display_core_init(struct drm_i915_private
*dev_priv,
if (DISPLAY_VER(dev_priv) >= 12)
tgl_bw_buddy_init(dev_priv);
- if (resume && dev_priv->dmc.dmc_payload)
+ if (resume && intel_dmc_has_payload(dev_priv))
intel_dmc_load_program(dev_priv);
/* Wa_14011508470 */
@@ -6230,7 +6230,7 @@ void intel_power_domains_suspend(struct drm_i915_private
*i915,
*/
if (!(i915->dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&
suspend_mode == I915_DRM_SUSPEND_IDLE &&
- i915->dmc.dmc_payload) {
+ intel_dmc_has_payload(i915)) {
intel_display_power_flush_work(i915);
intel_power_domains_verify_state(i915);
return;
@@ -6420,7 +6420,7 @@ void intel_display_power_resume(struct drm_i915_private
*i915)
if (DISPLAY_VER(i915) >= 11) {
bxt_disable_dc9(i915);
icl_display_core_init(i915, true);
- if (i915->dmc.dmc_payload) {
+ if (intel_dmc_has_payload(i915)) {
if (i915->dmc.allowed_dc_mask &
DC_STATE_EN_UPTO_DC6)
skl_enable_dc6(i915);
@@ -6431,7 +6431,7 @@ void intel_display_power_resume(struct drm_i915_private
*i915)
} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
bxt_disable_dc9(i915);
bxt_display_core_init(i915, true);
- if (i915->dmc.dmc_payload &&
+ if (intel_dmc_has_payload(i915) &&
(i915->dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
gen9_enable_dc5(i915);
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index
[Intel-gfx] [PATCH 4/7] drm/i915/dmc: Introduce DMC_FW_MAIN
This is a prep patch for Pipe DMC plugging.
Add dmc_info struct in intel_dmc to have all common fields
shared between all DMC's in the package.
Add DMC_FW_MAIN(dmc_id 0) to refer to the blob.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 44 +++-
drivers/gpu/drm/i915/display/intel_dmc.h | 20 ---
2 files changed, 35 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index f9a0f194f9cf..16bfbca6c1ed 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -239,7 +239,7 @@ struct stepping_info {
bool intel_dmc_has_payload(struct drm_i915_private *i915)
{
- return i915->dmc.dmc_payload;
+ return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
}
static const struct stepping_info skl_stepping_info[] = {
@@ -316,7 +316,8 @@ static void gen9_set_dc_state_debugmask(struct
drm_i915_private *dev_priv)
*/
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
- u32 *payload = dev_priv->dmc.dmc_payload;
+ struct intel_dmc *dmc = _priv->dmc;
+ struct dmc_fw_info *dmc_info = >dmc_info[DMC_FW_MAIN];
u32 i, fw_size;
if (!HAS_DMC(dev_priv)) {
@@ -325,26 +326,26 @@ void intel_dmc_load_program(struct drm_i915_private
*dev_priv)
return;
}
- if (!intel_dmc_has_payload(dev_priv)) {
+ if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) {
drm_err(_priv->drm,
"Tried to program CSR with empty payload\n");
return;
}
- fw_size = dev_priv->dmc.dmc_fw_size;
+ fw_size = dmc_info->dmc_fw_size;
assert_rpm_wakelock_held(_priv->runtime_pm);
preempt_disable();
for (i = 0; i < fw_size; i++)
intel_uncore_write_fw(_priv->uncore, DMC_PROGRAM(i),
- payload[i]);
+ dmc_info->payload[i]);
preempt_enable();
- for (i = 0; i < dev_priv->dmc.mmio_count; i++) {
- intel_de_write(dev_priv, dev_priv->dmc.mmioaddr[i],
- dev_priv->dmc.mmiodata[i]);
+ for (i = 0; i < dmc_info->mmio_count; i++) {
+ intel_de_write(dev_priv, dmc_info->mmioaddr[i],
+ dmc_info->mmiodata[i]);
}
dev_priv->dmc.dc_state = 0;
@@ -401,13 +402,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
size_t rem_size)
{
struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ struct dmc_fw_info *dmc_info = >dmc_info[DMC_FW_MAIN];
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
const u32 *mmioaddr, *mmiodata;
u32 mmio_count, mmio_count_max;
u8 *payload;
- BUILD_BUG_ON(ARRAY_SIZE(dmc->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
-ARRAY_SIZE(dmc->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
+ BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
+ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
/*
* Check if we can access common fields, we will checkc again below
@@ -463,16 +465,10 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
}
for (i = 0; i < mmio_count; i++) {
- if (mmioaddr[i] < DMC_MMIO_START_RANGE ||
- mmioaddr[i] > DMC_MMIO_END_RANGE) {
- drm_err(>drm, "DMC firmware has wrong mmio
address 0x%x\n",
- mmioaddr[i]);
- return 0;
- }
- dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
- dmc->mmiodata[i] = mmiodata[i];
+ dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
+ dmc_info->mmiodata[i] = mmiodata[i];
}
- dmc->mmio_count = mmio_count;
+ dmc_info->mmio_count = mmio_count;
rem_size -= header_len_bytes;
@@ -485,16 +481,16 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
drm_err(>drm, "DMC FW too big (%u bytes)\n",
payload_size);
return 0;
}
- dmc->dmc_fw_size = dmc_header->fw_size;
+ dmc_info->dmc_fw_size = dmc_header->fw_size;
- dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
- if (!dmc->dmc_payload) {
+ dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);
+ if (!dmc_info->payload) {
drm_err(>drm, "Memory allocation failed for dmc
payload\n");
return 0;
}
payload = (u8 *)(dmc_header) + header_len_bytes;
- memcpy(dmc->dmc_payload, payload, payload_size);
+ memcpy(dmc_info->payload, payload, payload_size);
return header_len_bytes + payload_size;
@@ -829,5 +825,5 @@ void intel_dmc_ucode_fini(struct
[Intel-gfx] [PATCH 1/7] drm/i915/dmc: s/DRM_ERROR/drm_err
Use new format of debug messages across intel_csr.
While at it, change some function definitions which now
need dev_priv for drm_err and drm_info etc.
v2: use container_of() (Jani)
v3: Indentation fixes. (Jani)
Cc: Jani Nikula
Suggested-by: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 48 +---
1 file changed, 26 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 560574dd929a..5887453ff302 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -395,6 +395,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
const struct intel_dmc_header_base *dmc_header,
size_t rem_size)
{
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
const u32 *mmioaddr, *mmiodata;
u32 mmio_count, mmio_count_max;
@@ -439,28 +440,28 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
header_len_bytes = dmc_header->header_len;
dmc_header_size = sizeof(*v1);
} else {
- DRM_ERROR("Unknown DMC fw header version: %u\n",
- dmc_header->header_ver);
+ drm_err(>drm, "Unknown DMC fw header version: %u\n",
+ dmc_header->header_ver);
return 0;
}
if (header_len_bytes != dmc_header_size) {
- DRM_ERROR("DMC firmware has wrong dmc header length "
- "(%u bytes)\n", header_len_bytes);
+ drm_err(>drm, "DMC firmware has wrong dmc header length "
+ "(%u bytes)\n", header_len_bytes);
return 0;
}
/* Cache the dmc header info. */
if (mmio_count > mmio_count_max) {
- DRM_ERROR("DMC firmware has wrong mmio count %u\n", mmio_count);
+ drm_err(>drm, "DMC firmware has wrong mmio count %u\n",
mmio_count);
return 0;
}
for (i = 0; i < mmio_count; i++) {
if (mmioaddr[i] < DMC_MMIO_START_RANGE ||
mmioaddr[i] > DMC_MMIO_END_RANGE) {
- DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
- mmioaddr[i]);
+ drm_err(>drm, "DMC firmware has wrong mmio
address 0x%x\n",
+ mmioaddr[i]);
return 0;
}
dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
@@ -476,14 +477,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
goto error_truncated;
if (payload_size > dmc->max_fw_size) {
- DRM_ERROR("DMC FW too big (%u bytes)\n", payload_size);
+ drm_err(>drm, "DMC FW too big (%u bytes)\n",
payload_size);
return 0;
}
dmc->dmc_fw_size = dmc_header->fw_size;
dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
if (!dmc->dmc_payload) {
- DRM_ERROR("Memory allocation failed for dmc payload\n");
+ drm_err(>drm, "Memory allocation failed for dmc
payload\n");
return 0;
}
@@ -493,7 +494,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
return header_len_bytes + payload_size;
error_truncated:
- DRM_ERROR("Truncated DMC firmware, refusing.\n");
+ drm_err(>drm, "Truncated DMC firmware, refusing.\n");
return 0;
}
@@ -503,6 +504,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
const struct stepping_info *si,
size_t rem_size)
{
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
u32 package_size = sizeof(struct intel_package_header);
u32 num_entries, max_entries, dmc_offset;
const struct intel_fw_info *fw_info;
@@ -515,8 +517,8 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
} else if (package_header->header_ver == 2) {
max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES;
} else {
- DRM_ERROR("DMC firmware has unknown header version %u\n",
- package_header->header_ver);
+ drm_err(>drm, "DMC firmware has unknown header version
%u\n",
+ package_header->header_ver);
return 0;
}
@@ -529,8 +531,8 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
goto error_truncated;
if (package_header->header_len * 4 != package_size) {
- DRM_ERROR("DMC firmware has wrong package header length "
- "(%u bytes)\n", package_size);
+ drm_err(>drm, "DMC firmware has wrong package header
length "
+
[Intel-gfx] [PATCH 0/7] Pipe DMC Support
Adding the actual Pipe DMC bits. This series is rebased on top of the new "More DMC cleanup" series: https://patchwork.freedesktop.org/series/90379/ Anusha Srivatsa (7): drm/i915/dmc: s/DRM_ERROR/drm_err drm/i915/dmc: Add intel_dmc_has_payload() helper drm/i915/dmc: Move struct intel_dmc to intel_dmc.h drm/i915/dmc: Introduce DMC_FW_MAIN drm/i915/xelpd: Pipe A DMC plugging drm/i915/adl_p: Pipe B DMC Support drm/i915/adl_p: Load DMC .../drm/i915/display/intel_display_debugfs.c | 10 +- .../drm/i915/display/intel_display_power.c| 21 +- drivers/gpu/drm/i915/display/intel_dmc.c | 212 ++ drivers/gpu/drm/i915/display/intel_dmc.h | 35 +++ drivers/gpu/drm/i915/i915_drv.h | 18 +- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 7 files changed, 178 insertions(+), 122 deletions(-) -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/3] drm/i915/dmc: s/DRM_ERROR/drm_err
Use new format of debug messages across intel_csr.
While at it, change some function definitions which now
need dev_priv for drm_err and drm_info etc.
v2: use container_of() (Jani)
v3: Indentation fixes. (Jani)
Cc: Jani Nikula
Suggested-by: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 48 +---
1 file changed, 26 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 560574dd929a..5887453ff302 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -395,6 +395,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
const struct intel_dmc_header_base *dmc_header,
size_t rem_size)
{
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
const u32 *mmioaddr, *mmiodata;
u32 mmio_count, mmio_count_max;
@@ -439,28 +440,28 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
header_len_bytes = dmc_header->header_len;
dmc_header_size = sizeof(*v1);
} else {
- DRM_ERROR("Unknown DMC fw header version: %u\n",
- dmc_header->header_ver);
+ drm_err(>drm, "Unknown DMC fw header version: %u\n",
+ dmc_header->header_ver);
return 0;
}
if (header_len_bytes != dmc_header_size) {
- DRM_ERROR("DMC firmware has wrong dmc header length "
- "(%u bytes)\n", header_len_bytes);
+ drm_err(>drm, "DMC firmware has wrong dmc header length "
+ "(%u bytes)\n", header_len_bytes);
return 0;
}
/* Cache the dmc header info. */
if (mmio_count > mmio_count_max) {
- DRM_ERROR("DMC firmware has wrong mmio count %u\n", mmio_count);
+ drm_err(>drm, "DMC firmware has wrong mmio count %u\n",
mmio_count);
return 0;
}
for (i = 0; i < mmio_count; i++) {
if (mmioaddr[i] < DMC_MMIO_START_RANGE ||
mmioaddr[i] > DMC_MMIO_END_RANGE) {
- DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
- mmioaddr[i]);
+ drm_err(>drm, "DMC firmware has wrong mmio
address 0x%x\n",
+ mmioaddr[i]);
return 0;
}
dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
@@ -476,14 +477,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
goto error_truncated;
if (payload_size > dmc->max_fw_size) {
- DRM_ERROR("DMC FW too big (%u bytes)\n", payload_size);
+ drm_err(>drm, "DMC FW too big (%u bytes)\n",
payload_size);
return 0;
}
dmc->dmc_fw_size = dmc_header->fw_size;
dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
if (!dmc->dmc_payload) {
- DRM_ERROR("Memory allocation failed for dmc payload\n");
+ drm_err(>drm, "Memory allocation failed for dmc
payload\n");
return 0;
}
@@ -493,7 +494,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
return header_len_bytes + payload_size;
error_truncated:
- DRM_ERROR("Truncated DMC firmware, refusing.\n");
+ drm_err(>drm, "Truncated DMC firmware, refusing.\n");
return 0;
}
@@ -503,6 +504,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
const struct stepping_info *si,
size_t rem_size)
{
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
u32 package_size = sizeof(struct intel_package_header);
u32 num_entries, max_entries, dmc_offset;
const struct intel_fw_info *fw_info;
@@ -515,8 +517,8 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
} else if (package_header->header_ver == 2) {
max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES;
} else {
- DRM_ERROR("DMC firmware has unknown header version %u\n",
- package_header->header_ver);
+ drm_err(>drm, "DMC firmware has unknown header version
%u\n",
+ package_header->header_ver);
return 0;
}
@@ -529,8 +531,8 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
goto error_truncated;
if (package_header->header_len * 4 != package_size) {
- DRM_ERROR("DMC firmware has wrong package header length "
- "(%u bytes)\n", package_size);
+ drm_err(>drm, "DMC firmware has wrong package header
length "
+
[Intel-gfx] [CI 2/3] drm/i915/dmc: Add intel_dmc_has_payload() helper
We check for dmc_payload being there at various points in the driver.
Replace it with the helper.
v2: rebased.
v3: Move intel_dmc to intel_dmc.h in another patch (Lucas)
v4: Remove headers not needed from intel_dmc.h
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
.../gpu/drm/i915/display/intel_display_debugfs.c | 4 ++--
.../gpu/drm/i915/display/intel_display_power.c | 16
drivers/gpu/drm/i915/display/intel_dmc.c | 13 +
drivers/gpu/drm/i915/display/intel_dmc.h | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c| 2 +-
5 files changed, 21 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 94e5cbd86e77..88bb05d5c483 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -542,10 +542,10 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
wakeref = intel_runtime_pm_get(_priv->runtime_pm);
- seq_printf(m, "fw loaded: %s\n", yesno(dmc->dmc_payload));
+ seq_printf(m, "fw loaded: %s\n",
yesno(intel_dmc_has_payload(dev_priv)));
seq_printf(m, "path: %s\n", dmc->fw_path);
- if (!dmc->dmc_payload)
+ if (!intel_dmc_has_payload(dev_priv))
goto out;
seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version),
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 991ceea06a07..b546672c9b00 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1220,7 +1220,7 @@ static void gen9_dc_off_power_well_enable(struct
drm_i915_private *dev_priv,
static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- if (!dev_priv->dmc.dmc_payload)
+ if (!intel_dmc_has_payload(dev_priv))
return;
switch (dev_priv->dmc.target_dc_state) {
@@ -5579,7 +5579,7 @@ static void skl_display_core_init(struct drm_i915_private
*dev_priv,
gen9_dbuf_enable(dev_priv);
- if (resume && dev_priv->dmc.dmc_payload)
+ if (resume && intel_dmc_has_payload(dev_priv))
intel_dmc_load_program(dev_priv);
}
@@ -5646,7 +5646,7 @@ static void bxt_display_core_init(struct drm_i915_private
*dev_priv, bool resume
gen9_dbuf_enable(dev_priv);
- if (resume && dev_priv->dmc.dmc_payload)
+ if (resume && intel_dmc_has_payload(dev_priv))
intel_dmc_load_program(dev_priv);
}
@@ -5712,7 +5712,7 @@ static void cnl_display_core_init(struct drm_i915_private
*dev_priv, bool resume
/* 6. Enable DBUF */
gen9_dbuf_enable(dev_priv);
- if (resume && dev_priv->dmc.dmc_payload)
+ if (resume && intel_dmc_has_payload(dev_priv))
intel_dmc_load_program(dev_priv);
}
@@ -5869,7 +5869,7 @@ static void icl_display_core_init(struct drm_i915_private
*dev_priv,
if (DISPLAY_VER(dev_priv) >= 12)
tgl_bw_buddy_init(dev_priv);
- if (resume && dev_priv->dmc.dmc_payload)
+ if (resume && intel_dmc_has_payload(dev_priv))
intel_dmc_load_program(dev_priv);
/* Wa_14011508470 */
@@ -6230,7 +6230,7 @@ void intel_power_domains_suspend(struct drm_i915_private
*i915,
*/
if (!(i915->dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&
suspend_mode == I915_DRM_SUSPEND_IDLE &&
- i915->dmc.dmc_payload) {
+ intel_dmc_has_payload(i915)) {
intel_display_power_flush_work(i915);
intel_power_domains_verify_state(i915);
return;
@@ -6420,7 +6420,7 @@ void intel_display_power_resume(struct drm_i915_private
*i915)
if (DISPLAY_VER(i915) >= 11) {
bxt_disable_dc9(i915);
icl_display_core_init(i915, true);
- if (i915->dmc.dmc_payload) {
+ if (intel_dmc_has_payload(i915)) {
if (i915->dmc.allowed_dc_mask &
DC_STATE_EN_UPTO_DC6)
skl_enable_dc6(i915);
@@ -6431,7 +6431,7 @@ void intel_display_power_resume(struct drm_i915_private
*i915)
} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
bxt_disable_dc9(i915);
bxt_display_core_init(i915, true);
- if (i915->dmc.dmc_payload &&
+ if (intel_dmc_has_payload(i915) &&
(i915->dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
gen9_enable_dc5(i915);
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index
[Intel-gfx] [CI 3/3] drm/i915/dmc: Move struct intel_dmc to intel_dmc.h
Move struct intel_dmc from i915_drv.h to intel_dmc.h.
v2: Add includes along with moving the struct.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.h | 21 +
drivers/gpu/drm/i915/i915_drv.h | 18 +-
2 files changed, 22 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h
b/drivers/gpu/drm/i915/display/intel_dmc.h
index 64816f4a71b6..4c22f567b61b 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -6,12 +6,33 @@
#ifndef __INTEL_DMC_H__
#define __INTEL_DMC_H__
+#include "i915_reg.h"
+#include "intel_wakeref.h"
+#include
+
struct drm_i915_private;
#define DMC_VERSION(major, minor) ((major) << 16 | (minor))
#define DMC_VERSION_MAJOR(version) ((version) >> 16)
#define DMC_VERSION_MINOR(version) ((version) & 0x)
+struct intel_dmc {
+ struct work_struct work;
+ const char *fw_path;
+ u32 required_version;
+ u32 max_fw_size; /* bytes */
+ u32 *dmc_payload;
+ u32 dmc_fw_size; /* dwords */
+ u32 version;
+ u32 mmio_count;
+ i915_reg_t mmioaddr[20];
+ u32 mmiodata[20];
+ u32 dc_state;
+ u32 target_dc_state;
+ u32 allowed_dc_mask;
+ intel_wakeref_t wakeref;
+};
+
void intel_dmc_ucode_init(struct drm_i915_private *i915);
void intel_dmc_load_program(struct drm_i915_private *i915);
void intel_dmc_ucode_fini(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9cb02618ba15..b5962768a1f1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -67,6 +67,7 @@
#include "display/intel_bios.h"
#include "display/intel_display.h"
#include "display/intel_display_power.h"
+#include "display/intel_dmc.h"
#include "display/intel_dpll_mgr.h"
#include "display/intel_dsb.h"
#include "display/intel_frontbuffer.h"
@@ -328,23 +329,6 @@ struct drm_i915_display_funcs {
void (*read_luts)(struct intel_crtc_state *crtc_state);
};
-struct intel_dmc {
- struct work_struct work;
- const char *fw_path;
- u32 required_version;
- u32 max_fw_size; /* bytes */
- u32 *dmc_payload;
- u32 dmc_fw_size; /* dwords */
- u32 version;
- u32 mmio_count;
- i915_reg_t mmioaddr[20];
- u32 mmiodata[20];
- u32 dc_state;
- u32 target_dc_state;
- u32 allowed_dc_mask;
- intel_wakeref_t wakeref;
-};
-
enum i915_cache_level {
I915_CACHE_NONE = 0,
I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 0/3] More DMC cleanup
Last of prep patches before Pipe DMC patches can land. v2: Add struct intel_dmc to intel_dmc.h in a separate patch v3: Minor code shuffling and indentation fixes Anusha Srivatsa (3): drm/i915/dmc: s/DRM_ERROR/drm_err drm/i915/dmc: Add intel_dmc_has_payload() helper drm/i915/dmc: Move struct intel_dmc to intel_dmc.h .../drm/i915/display/intel_display_debugfs.c | 4 +- .../drm/i915/display/intel_display_power.c| 16 ++--- drivers/gpu/drm/i915/display/intel_dmc.c | 61 +++ drivers/gpu/drm/i915/display/intel_dmc.h | 22 +++ drivers/gpu/drm/i915/i915_drv.h | 18 +- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- 6 files changed, 69 insertions(+), 54 deletions(-) -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/adlp: Require DPT FB CCS color planes to be 2MB aligned
== Series Details == Series: series starting with [1/3] drm/i915/adlp: Require DPT FB CCS color planes to be 2MB aligned URL : https://patchwork.freedesktop.org/series/90484/ State : success == Summary == CI Bug Log - changes from CI_DRM_10127 -> Patchwork_20180 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/index.html Known issues Here are the changes found in Patchwork_20180 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/fi-hsw-4770/igt@amdgpu/amd_ba...@cs-gfx.html * igt@amdgpu/amd_cs_nop@sync-fork-compute0: - fi-snb-2600:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html * igt@core_hotunplug@unbind-rebind: - fi-hsw-4770:NOTRUN -> [WARN][3] ([i915#2283]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/fi-hsw-4770/igt@core_hotunp...@unbind-rebind.html * igt@gem_huc_copy@huc-copy: - fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271]) +4 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/fi-hsw-4770/igt@gem_huc_c...@huc-copy.html * igt@i915_pm_backlight@basic-brightness: - fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#3012]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#533]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@primary_mmap_gtt: - fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1072]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html Possible fixes * igt@gem_exec_suspend@basic-s0: - fi-hsw-4770:[INCOMPLETE][9] -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-hsw-4770/igt@gem_exec_susp...@basic-s0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/fi-hsw-4770/igt@gem_exec_susp...@basic-s0.html * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[INCOMPLETE][11] ([i915#2782]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html Warnings * igt@i915_selftest@live@execlists: - fi-cfl-8109u: [INCOMPLETE][13] ([i915#3462]) -> [DMESG-FAIL][14] ([i915#3462]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html - fi-bsw-nick:[DMESG-FAIL][15] ([i915#3462]) -> [INCOMPLETE][16] ([i915#2782] / [i915#2940] / [i915#3462]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/fi-bsw-nick/igt@i915_selftest@l...@execlists.html - fi-icl-u2: [INCOMPLETE][17] ([i915#2782] / [i915#3462]) -> [DMESG-FAIL][18] ([i915#3462]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-icl-u2/igt@i915_selftest@l...@execlists.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/fi-icl-u2/igt@i915_selftest@l...@execlists.html * igt@runner@aborted: - fi-skl-6600u: [FAIL][19] ([i915#1436] / [i915#3363]) -> [FAIL][20] ([i915#1436] / [i915#2426] / [i915#3363]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-skl-6600u/igt@run...@aborted.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/fi-skl-6600u/igt@run...@aborted.html - fi-cfl-8109u: [FAIL][21] ([i915#3363]) -> [FAIL][22] ([i915#2426] / [i915#3363]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-cfl-8109u/igt@run...@aborted.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20180/fi-cfl-8109u/igt@run...@aborted.html - fi-icl-u2:
Re: [Intel-gfx] [RFC PATCH 39/97] drm/i915/guc: Increase size of CTB buffers
On Mon, May 24, 2021 at 03:43:11PM +0200, Michal Wajdeczko wrote: > > > On 06.05.2021 21:13, Matthew Brost wrote: > > With the introduction of non-blocking CTBs more than one CTB can be in > > flight at a time. Increasing the size of the CTBs should reduce how > > often software hits the case where no space is available in the CTB > > buffer. > > > > Cc: John Harrison > > Signed-off-by: Matthew Brost > > --- > > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 11 --- > > 1 file changed, 8 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > > b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > > index 77dfbc94dcc3..d6895d29ed2d 100644 > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > > @@ -63,11 +63,16 @@ static inline struct drm_device *ct_to_drm(struct > > intel_guc_ct *ct) > > * ++---+--+ > > * > > * Size of each `CT Buffer`_ must be multiple of 4K. > > - * As we don't expect too many messages, for now use minimum sizes. > > + * We don't expect too many messages in flight at any time, unless we are > > + * using the GuC submission. In that case each request requires a minimum > > + * 16 bytes which gives us a maximum 256 queue'd requests. Hopefully this > > nit: all our CTB calculations are in dwords now, not bytes > I can change the wording to DW sizes. > > + * enough space to avoid backpressure on the driver. We increase the size > > + * of the receive buffer (relative to the send) to ensure a G2H response > > + * CTB has a landing spot. > > hmm, but we are not checking G2H CTB yet > will start doing it around patch 54/97 > so maybe this other patch should be introduced earlier ? > Yes, that patch is going to be pulled down to an earlier spot in the series. > > */ > > #define CTB_DESC_SIZE ALIGN(sizeof(struct > > guc_ct_buffer_desc), SZ_2K) > > #define CTB_H2G_BUFFER_SIZE(SZ_4K) > > -#define CTB_G2H_BUFFER_SIZE(SZ_4K) > > +#define CTB_G2H_BUFFER_SIZE(4 * CTB_H2G_BUFFER_SIZE) > > in theory, we (host) should be faster than GuC, so G2H CTB shall be > almost always empty, if this is not a case, maybe we should start > monitoring what is happening and report some warnings if G2H is half full ? > Certainly some IGTs put some more pressure on the G2H channel than the H2G channel at least I think. This is something we can tune over time after this lands upstream. IMO a message at this point is overkill. Matt > > > > #define MAX_US_STALL_CTB 100 > > > > @@ -753,7 +758,7 @@ static int ct_read(struct intel_guc_ct *ct, struct > > ct_incoming_msg **msg) > > /* beware of buffer wrap case */ > > if (unlikely(available < 0)) > > available += size; > > - CT_DEBUG(ct, "available %d (%u:%u)\n", available, head, tail); > > + CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size); > > GEM_BUG_ON(available < 0); > > > > header = cmds[head]; > > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 08/12] drm/ttm: Use drm_memcpy_from_wc_dbm for TTM bo moves
On Mon, 2021-05-24 at 19:16 +0100, Matthew Auld wrote:
> On Fri, 21 May 2021 at 16:33, Thomas Hellström
> wrote:
> >
> > Use fast wc memcpy for reading out of wc memory for TTM bo moves.
> >
> > Cc: Dave Airlie
> > Cc: Christian König
> > Cc: Daniel Vetter
> > Signed-off-by: Thomas Hellström
> > ---
> > drivers/gpu/drm/ttm/ttm_bo_util.c | 9 -
> > 1 file changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
> > b/drivers/gpu/drm/ttm/ttm_bo_util.c
> > index 912cbe8e60a2..4a7d3d672f9a 100644
> > --- a/drivers/gpu/drm/ttm/ttm_bo_util.c
> > +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
> > @@ -31,6 +31,7 @@
> >
> > #include
> > #include
> > +#include
> > #include
> > #include
> > #include
> > @@ -91,6 +92,7 @@ void ttm_move_memcpy(struct ttm_buffer_object
> > *bo,
> > const struct ttm_kmap_iter_ops *src_ops = src_iter->ops;
> > struct ttm_tt *ttm = bo->ttm;
> > struct dma_buf_map src_map, dst_map;
> > + bool wc_memcpy;
> > pgoff_t i;
> >
> > /* Single TTM move. NOP */
> > @@ -114,11 +116,16 @@ void ttm_move_memcpy(struct ttm_buffer_object
> > *bo,
> > return;
> > }
> >
> > + wc_memcpy = ((!src_ops->maps_tt || ttm->caching !=
> > ttm_cached) &&
>
> Why do we only consider the caching value for the maps_tt case? Or am
> I misreading this?
Hmm, you're right we should probably check also the iomem caching or
ignore the tt caching. Sometimes these special memcpys tend to be less
cpu cache thrashing and should be used wherever possible, but I guess
we should start out with only using it when source is WC.
>
> > + drm_has_memcpy_from_wc());
> > +
> > for (i = 0; i < dst_mem->num_pages; ++i) {
> > dst_ops->map_local(dst_iter, _map, i);
> > src_ops->map_local(src_iter, _map, i);
> >
> > - if (!src_map.is_iomem && !dst_map.is_iomem) {
> > + if (wc_memcpy) {
> > + drm_memcpy_from_wc_dbm(_map, _map,
> > PAGE_SIZE);
>
> Do we need to check the return value here? memcpy_from_wc expects
> certain address alignment, or is that always guaranteed here? Maybe
> throw a warning just for paranoia?
It should always be PAGE_SIZE aligned. But I guess it doesn't hurt to
do
if (wc_memcpy && drm_memcpy_from_wc_dbm())
;
>
> > + } else if (!src_map.is_iomem && !dst_map.is_iomem)
> > {
> > memcpy(dst_map.vaddr, src_map.vaddr,
> > PAGE_SIZE);
> > } else if (!src_map.is_iomem) {
> > dma_buf_map_memcpy_to(_map,
> > src_map.vaddr,
> > --
> > 2.31.1
> >
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/adlp: Require DPT FB CCS color planes to be 2MB aligned
== Series Details == Series: series starting with [1/3] drm/i915/adlp: Require DPT FB CCS color planes to be 2MB aligned URL : https://patchwork.freedesktop.org/series/90484/ State : warning == Summary == $ dim checkpatch origin/drm-tip 67ae62f3578a drm/i915/adlp: Require DPT FB CCS color planes to be 2MB aligned ab61802fef7d drm/i915/adlp: Fix GEM VM asserts for DPT VMs -:27: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'vm' - possible side-effects? #27: FILE: drivers/gpu/drm/i915/gt/intel_gtt.h:362: +#define i915_is_ggtt_or_dpt(vm) (i915_is_ggtt(vm) || i915_is_dpt(vm)) total: 0 errors, 0 warnings, 1 checks, 31 lines checked 5e4ab79a1296 drm/i915/debugfs: Print remap info for DPT VMAs as well -:28: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 15) #28: FILE: drivers/gpu/drm/i915/i915_debugfs.c:129: + if (i915_vma_is_ggtt(vma)) + return "ggtt"; -:29: WARNING:TABSTOP: Statements should start on a tabstop #29: FILE: drivers/gpu/drm/i915/i915_debugfs.c:130: + return "ggtt"; total: 0 errors, 2 warnings, 0 checks, 42 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 37/97] drm/i915/guc: Add stall timer to non blocking CTB send function
On Mon, May 24, 2021 at 02:58:12PM +0200, Michal Wajdeczko wrote:
>
>
> On 06.05.2021 21:13, Matthew Brost wrote:
> > Implement a stall timer which fails H2G CTBs once a period of time
> > with no forward progress is reached to prevent deadlock.
> >
> > Also update to ct_write to return -EDEADLK rather than -EPIPE on a
> > corrupted descriptor.
>
> broken descriptor is really separate issue compared to no progress from
> GuC side, I would really like to keep old error code
>
I know you do as you have brought it up several times. Again to the rest
of the stack these two things mean the exact same thing.
> note that broken CTB descriptor is unrecoverable error, while on other
> hand, in theory, we could recover from temporary non-moving CTB
>
Yea but we don't, in both cases we disable submission which in turn
triggers a full GPU reset.
> >
> > Signed-off-by: John Harrison
> > Signed-off-by: Daniele Ceraolo Spurio
> > Signed-off-by: Matthew Brost
> > ---
> > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 48 +--
> > 1 file changed, 45 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > index af7314d45a78..4eab319d61be 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > @@ -69,6 +69,8 @@ static inline struct drm_device *ct_to_drm(struct
> > intel_guc_ct *ct)
> > #define CTB_H2G_BUFFER_SIZE(SZ_4K)
> > #define CTB_G2H_BUFFER_SIZE(SZ_4K)
> >
> > +#define MAX_US_STALL_CTB 100
>
> nit: maybe we should make it a CONFIG value ?
>
Sure.
> > +
> > struct ct_request {
> > struct list_head link;
> > u32 fence;
> > @@ -315,6 +317,7 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
> >
> > ct->requests.last_fence = 1;
> > ct->enabled = true;
> > + ct->stall_time = KTIME_MAX;
> >
> > return 0;
> >
> > @@ -378,7 +381,7 @@ static int ct_write(struct intel_guc_ct *ct,
> > unsigned int i;
> >
> > if (unlikely(ctb->broken))
> > - return -EPIPE;
> > + return -EDEADLK;
> >
> > if (unlikely(desc->status))
> > goto corrupted;
> > @@ -449,7 +452,7 @@ static int ct_write(struct intel_guc_ct *ct,
> > CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
> > desc->head, desc->tail, desc->status);
> > ctb->broken = true;
> > - return -EPIPE;
> > + return -EDEADLK;
> > }
> >
> > /**
> > @@ -494,6 +497,17 @@ static int wait_for_ct_request_update(struct
> > ct_request *req, u32 *status)
> > return err;
> > }
> >
> > +static inline bool ct_deadlocked(struct intel_guc_ct *ct)
> > +{
> > + bool ret = ktime_us_delta(ktime_get(), ct->stall_time) >
> > + MAX_US_STALL_CTB;
> > +
> > + if (unlikely(ret))
> > + CT_ERROR(ct, "CT deadlocked\n");
> > +
> > + return ret;
> > +}
> > +
> > static inline bool ctb_has_room(struct intel_guc_ct_buffer *ctb, u32
> > len_dw)
> > {
> > struct guc_ct_buffer_desc *desc = ctb->desc;
> > @@ -505,6 +519,26 @@ static inline bool ctb_has_room(struct
> > intel_guc_ct_buffer *ctb, u32 len_dw)
> > return space >= len_dw;
> > }
> >
> > +static int has_room_nb(struct intel_guc_ct *ct, u32 len_dw)
> > +{
> > + struct intel_guc_ct_buffer *ctb = >ctbs.send;
> > +
> > + lockdep_assert_held(>ctbs.send.lock);
> > +
> > + if (unlikely(!ctb_has_room(ctb, len_dw))) {
> > + if (ct->stall_time == KTIME_MAX)
> > + ct->stall_time = ktime_get();
> > +
> > + if (unlikely(ct_deadlocked(ct)))
> > + return -EDEADLK;
> > + else
> > + return -EBUSY;
> > + }
> > +
> > + ct->stall_time = KTIME_MAX;
> > + return 0;
> > +}
> > +
> > static int ct_send_nb(struct intel_guc_ct *ct,
> > const u32 *action,
> > u32 len,
> > @@ -517,7 +551,7 @@ static int ct_send_nb(struct intel_guc_ct *ct,
> >
> > spin_lock_irqsave(>lock, spin_flags);
> >
> > - ret = ctb_has_room(ctb, len + 1);
> > + ret = has_room_nb(ct, len + 1);
> > if (unlikely(ret))
> > goto out;
> >
> > @@ -561,11 +595,19 @@ static int ct_send(struct intel_guc_ct *ct,
> > retry:
> > spin_lock_irqsave(>ctbs.send.lock, flags);
> > if (unlikely(!ctb_has_room(ctb, len + 1))) {
> > + if (ct->stall_time == KTIME_MAX)
> > + ct->stall_time = ktime_get();
> > spin_unlock_irqrestore(>ctbs.send.lock, flags);
> > +
> > + if (unlikely(ct_deadlocked(ct)))
> > + return -EDEADLK;
> > +
>
> likely, instead of duplicating code, you can reuse has_room_nb here
>
In this patch yes, in the following patch no as this check changes
between non-blockig and blocking once we introduce G2H credits. I'd
rather just leave it as is than churning on the patches.
Matt
> > cond_resched();
> >
[Intel-gfx] ✓ Fi.CI.BAT: success for GPD Win Max display fixes
== Series Details == Series: GPD Win Max display fixes URL : https://patchwork.freedesktop.org/series/90483/ State : success == Summary == CI Bug Log - changes from CI_DRM_10127 -> Patchwork_20179 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/index.html Known issues Here are the changes found in Patchwork_20179 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/fi-hsw-4770/igt@amdgpu/amd_ba...@cs-gfx.html * igt@amdgpu/amd_cs_nop@sync-fork-compute0: - fi-snb-2600:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html * igt@core_hotunplug@unbind-rebind: - fi-hsw-4770:NOTRUN -> [WARN][3] ([i915#2283]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/fi-hsw-4770/igt@core_hotunp...@unbind-rebind.html * igt@gem_huc_copy@huc-copy: - fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271]) +4 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/fi-hsw-4770/igt@gem_huc_c...@huc-copy.html * igt@i915_pm_backlight@basic-brightness: - fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#3012]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#533]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@primary_mmap_gtt: - fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1072]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html Possible fixes * igt@gem_exec_suspend@basic-s0: - fi-hsw-4770:[INCOMPLETE][9] -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-hsw-4770/igt@gem_exec_susp...@basic-s0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/fi-hsw-4770/igt@gem_exec_susp...@basic-s0.html * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[INCOMPLETE][11] ([i915#2782]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html Warnings * igt@i915_selftest@live@execlists: - fi-bsw-nick:[DMESG-FAIL][13] ([i915#3462]) -> [INCOMPLETE][14] ([i915#2782] / [i915#2940] / [i915#3462]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/fi-bsw-nick/igt@i915_selftest@l...@execlists.html - fi-icl-u2: [INCOMPLETE][15] ([i915#2782] / [i915#3462]) -> [DMESG-FAIL][16] ([i915#3462]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-icl-u2/igt@i915_selftest@l...@execlists.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/fi-icl-u2/igt@i915_selftest@l...@execlists.html * igt@runner@aborted: - fi-cfl-8700k: [FAIL][17] ([i915#3363]) -> [FAIL][18] ([i915#2426] / [i915#3363]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-cfl-8700k/igt@run...@aborted.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/fi-cfl-8700k/igt@run...@aborted.html - fi-icl-u2: [FAIL][19] ([i915#2782] / [i915#3363]) -> [FAIL][20] ([i915#2426] / [i915#2782] / [i915#3363]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-icl-u2/igt@run...@aborted.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/fi-icl-u2/igt@run...@aborted.html - fi-cml-u2: [FAIL][21] ([i915#2082] / [i915#2426] / [i915#3363] / [i915#3462]) -> [FAIL][22] ([i915#3363] / [i915#3462]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-cml-u2/igt@run...@aborted.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20179/fi-cml-u2/igt@run...@aborted.html - fi-kbl-7567u: [FAIL][23] ([i915#1436] / [i915#3363]) -> [FAIL][24]
Re: [Intel-gfx] [PATCH v3 08/12] drm/ttm: Use drm_memcpy_from_wc_dbm for TTM bo moves
On Fri, 21 May 2021 at 16:33, Thomas Hellström
wrote:
>
> Use fast wc memcpy for reading out of wc memory for TTM bo moves.
>
> Cc: Dave Airlie
> Cc: Christian König
> Cc: Daniel Vetter
> Signed-off-by: Thomas Hellström
> ---
> drivers/gpu/drm/ttm/ttm_bo_util.c | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
> b/drivers/gpu/drm/ttm/ttm_bo_util.c
> index 912cbe8e60a2..4a7d3d672f9a 100644
> --- a/drivers/gpu/drm/ttm/ttm_bo_util.c
> +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
> @@ -31,6 +31,7 @@
>
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -91,6 +92,7 @@ void ttm_move_memcpy(struct ttm_buffer_object *bo,
> const struct ttm_kmap_iter_ops *src_ops = src_iter->ops;
> struct ttm_tt *ttm = bo->ttm;
> struct dma_buf_map src_map, dst_map;
> + bool wc_memcpy;
> pgoff_t i;
>
> /* Single TTM move. NOP */
> @@ -114,11 +116,16 @@ void ttm_move_memcpy(struct ttm_buffer_object *bo,
> return;
> }
>
> + wc_memcpy = ((!src_ops->maps_tt || ttm->caching != ttm_cached) &&
Why do we only consider the caching value for the maps_tt case? Or am
I misreading this?
> +drm_has_memcpy_from_wc());
> +
> for (i = 0; i < dst_mem->num_pages; ++i) {
> dst_ops->map_local(dst_iter, _map, i);
> src_ops->map_local(src_iter, _map, i);
>
> - if (!src_map.is_iomem && !dst_map.is_iomem) {
> + if (wc_memcpy) {
> + drm_memcpy_from_wc_dbm(_map, _map, PAGE_SIZE);
Do we need to check the return value here? memcpy_from_wc expects
certain address alignment, or is that always guaranteed here? Maybe
throw a warning just for paranoia?
> + } else if (!src_map.is_iomem && !dst_map.is_iomem) {
> memcpy(dst_map.vaddr, src_map.vaddr, PAGE_SIZE);
> } else if (!src_map.is_iomem) {
> dma_buf_map_memcpy_to(_map, src_map.vaddr,
> --
> 2.31.1
>
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for GPD Win Max display fixes
== Series Details == Series: GPD Win Max display fixes URL : https://patchwork.freedesktop.org/series/90483/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1887:21:expected struct i915_vma *[assigned] vma +drivers/gpu/drm/i915/display/intel_display.c:1887:21:got void [noderef] __iomem *[assigned] iomem +drivers/gpu/drm/i915/display/intel_display.c:1887:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1329:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/intel_ring_submission.c:1203:24: warning: Using plain integer as NULL pointer +drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
Re: [Intel-gfx] [PATCH v3 07/12] drm, drm/i915: Move the memcpy_from_wc functionality to core drm
On Mon, 2021-05-24 at 17:45 +0100, Matthew Auld wrote: > On Fri, 21 May 2021 at 16:33, Thomas Hellström > wrote: > > > > Memcpy from wc will be used as well by TTM memcpy. > > Move it to core drm, and make the interface do the right thing > > even on !X86. > > > > Cc: Christian König > > Cc: Daniel Vetter > > Cc: Dave Airlie > > Signed-off-by: Thomas Hellström > > --- > > > > > + > > +#ifdef CONFIG_X86 > > +bool drm_memcpy_from_wc(void *dst, const void *src, unsigned long > > len); > > +bool drm_memcpy_from_wc_dbm(struct dma_buf_map *dst, > > + const struct dma_buf_map *src, > > + unsigned long len); > > +void drm_unaligned_memcpy_from_wc(void *dst, const void *src, > > unsigned long len); > > + > > +/* The movntdqa instructions used for memcpy-from-wc require 16- > > byte alignment, > > + * as well as SSE4.1 support. drm_memcpy_from_wc() will report if > > it cannot > > + * perform the operation. To check beforehand, pass in the > > parameters to > > + * drm_can_memcpy_from_wc() - since we only care about the low 4 > > bits, > > + * you only need to pass in the minor offsets, page-aligned > > pointers are > > + * always valid. > > + * > > + * For just checking for SSE4.1, in the foreknowledge that the > > future use > > + * will be correctly aligned, just use drm_has_memcpy_from_wc(). > > + */ > > +#define drm_can_memcpy_from_wc(dst, src, len) \ > > + drm_memcpy_from_wc((void *)((unsigned long)(dst) | > > (unsigned long)(src) | (len)), NULL, 0) > > + > > +#define drm_has_memcpy_from_wc() \ > > + drm_memcpy_from_wc(NULL, NULL, 0) > > + > > +void drm_memcpy_init_early(void); > > + > > +#else > > + > > +#define drm_memcpy_from_wc(_dst, _src, _len) (false) > > +#define drm_memcpy_from_wc_dbm(_dst, _src, _len) (false) > > +#define drm_can_memcpy_from_wc(_dst, _src, _len) (false) > > +#define drm_has_memcpy_from_wc() (false) > > Does the compiler not complain for these on !x86, if called without > checking the result of the statement? Maybe just make these function > stubs? > > Otherwise, > Reviewed-by: Matthew Auld Hmm, you're right. I'll fix. Thanks for reviewing! /Thomas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915/debugfs: Print remap info for DPT VMAs as well
On Mon, 2021-05-24 at 20:27 +0300, Imre Deak wrote:
> Similarly to GGTT VMAs, DPT VMAs can be also a remapped or rotated view
> of the mapped object, so make sure we debug print the details for these
> views as well besides the normal view.
>
> While at it also fix the debug print for the VMA type of DPT VMAs.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 17 ++---
> drivers/gpu/drm/i915/i915_vma.h | 5 +
> 2 files changed, 19 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 8dd3746911021..6d5c6ea02fab5 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -124,6 +124,17 @@ stringify_page_sizes(unsigned int page_sizes, char *buf,
> size_t len)
> }
> }
>
> +static const char *stringify_vma_type(const struct i915_vma *vma)
> +{
> + if (i915_vma_is_ggtt(vma))
> +return "ggtt";
> +
> + if (i915_vma_is_dpt(vma))
> + return "dpt";
> +
> + return "ppgtt";
> +}
> +
> void
> i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object
> *obj)
> {
> @@ -156,11 +167,11 @@ i915_debugfs_describe_obj(struct seq_file *m, struct
> drm_i915_gem_object *obj)
> if (i915_vma_is_pinned(vma))
> pin_count++;
>
> - seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s",
> -i915_vma_is_ggtt(vma) ? "g" : "pp",
> + seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s",
> +stringify_vma_type(vma),
> vma->node.start, vma->node.size,
> stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
> - if (i915_vma_is_ggtt(vma)) {
> + if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) {
> switch (vma->ggtt_view.type) {
> case I915_GGTT_VIEW_NORMAL:
> seq_puts(m, ", normal");
> diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
> index 2a108e66cd495..dc6926d896266 100644
> --- a/drivers/gpu/drm/i915/i915_vma.h
> +++ b/drivers/gpu/drm/i915/i915_vma.h
> @@ -68,6 +68,11 @@ static inline bool i915_vma_is_ggtt(const struct i915_vma
> *vma)
> return test_bit(I915_VMA_GGTT_BIT, __i915_vma_flags(vma));
> }
>
> +static inline bool i915_vma_is_dpt(const struct i915_vma *vma)
> +{
> + return i915_is_dpt(vma->vm);
> +}
> +
> static inline bool i915_vma_has_ggtt_write(const struct i915_vma *vma)
> {
> return test_bit(I915_VMA_GGTT_WRITE_BIT, __i915_vma_flags(vma));
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Re: [Intel-gfx] [PATCH 2/3] drm/i915/adlp: Fix GEM VM asserts for DPT VMs
On Mon, 2021-05-24 at 20:27 +0300, Imre Deak wrote:
> An object mapped via DPT can have remapped and rotated VMA instances
> besides the normal VMA instance, similarly to GGTT VMA instances.
> Adjust the corresponding VMA lookup asserts.
>
> While at it also check if a DPT VM is passed incorrectly to
> i915_vm_to_ppgtt().
>
Reviewed-by: José Roberto de Souza
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/gt/intel_gtt.h | 3 ++-
> drivers/gpu/drm/i915/i915_vma.c | 2 +-
> drivers/gpu/drm/i915/i915_vma.h | 2 +-
> 3 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
> b/drivers/gpu/drm/i915/gt/intel_gtt.h
> index ca00b45827b74..50a98ce39f74b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
> @@ -359,6 +359,7 @@ struct i915_ppgtt {
>
> #define i915_is_ggtt(vm) ((vm)->is_ggtt)
> #define i915_is_dpt(vm) ((vm)->is_dpt)
> +#define i915_is_ggtt_or_dpt(vm) (i915_is_ggtt(vm) || i915_is_dpt(vm))
>
> int __must_check
> i915_vm_lock_objects(struct i915_address_space *vm, struct i915_gem_ww_ctx
> *ww);
> @@ -393,7 +394,7 @@ static inline struct i915_ppgtt *
> i915_vm_to_ppgtt(struct i915_address_space *vm)
> {
> BUILD_BUG_ON(offsetof(struct i915_ppgtt, vm));
> - GEM_BUG_ON(i915_is_ggtt(vm));
> + GEM_BUG_ON(i915_is_ggtt_or_dpt(vm));
> return container_of(vm, struct i915_ppgtt, vm);
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
> index a6cd0fa628477..b319fd3f91cc3 100644
> --- a/drivers/gpu/drm/i915/i915_vma.c
> +++ b/drivers/gpu/drm/i915/i915_vma.c
> @@ -274,7 +274,7 @@ i915_vma_instance(struct drm_i915_gem_object *obj,
> {
> struct i915_vma *vma;
>
> - GEM_BUG_ON(view && !i915_is_ggtt(vm));
> + GEM_BUG_ON(view && !i915_is_ggtt_or_dpt(vm));
> GEM_BUG_ON(!atomic_read(>open));
>
> spin_lock(>vma.lock);
> diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
> index 8df784a026d21..2a108e66cd495 100644
> --- a/drivers/gpu/drm/i915/i915_vma.h
> +++ b/drivers/gpu/drm/i915/i915_vma.h
> @@ -158,7 +158,7 @@ i915_vma_compare(struct i915_vma *vma,
> {
> ptrdiff_t cmp;
>
> - GEM_BUG_ON(view && !i915_is_ggtt(vm));
> + GEM_BUG_ON(view && !i915_is_ggtt_or_dpt(vm));
>
> cmp = ptrdiff(vma->vm, vm);
> if (cmp)
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[Intel-gfx] [PATCH 3/3] drm/i915/debugfs: Print remap info for DPT VMAs as well
Similarly to GGTT VMAs, DPT VMAs can be also a remapped or rotated view
of the mapped object, so make sure we debug print the details for these
views as well besides the normal view.
While at it also fix the debug print for the VMA type of DPT VMAs.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_debugfs.c | 17 ++---
drivers/gpu/drm/i915/i915_vma.h | 5 +
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 8dd3746911021..6d5c6ea02fab5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -124,6 +124,17 @@ stringify_page_sizes(unsigned int page_sizes, char *buf,
size_t len)
}
}
+static const char *stringify_vma_type(const struct i915_vma *vma)
+{
+ if (i915_vma_is_ggtt(vma))
+ return "ggtt";
+
+ if (i915_vma_is_dpt(vma))
+ return "dpt";
+
+ return "ppgtt";
+}
+
void
i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
{
@@ -156,11 +167,11 @@ i915_debugfs_describe_obj(struct seq_file *m, struct
drm_i915_gem_object *obj)
if (i915_vma_is_pinned(vma))
pin_count++;
- seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s",
- i915_vma_is_ggtt(vma) ? "g" : "pp",
+ seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s",
+ stringify_vma_type(vma),
vma->node.start, vma->node.size,
stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
- if (i915_vma_is_ggtt(vma)) {
+ if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) {
switch (vma->ggtt_view.type) {
case I915_GGTT_VIEW_NORMAL:
seq_puts(m, ", normal");
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 2a108e66cd495..dc6926d896266 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -68,6 +68,11 @@ static inline bool i915_vma_is_ggtt(const struct i915_vma
*vma)
return test_bit(I915_VMA_GGTT_BIT, __i915_vma_flags(vma));
}
+static inline bool i915_vma_is_dpt(const struct i915_vma *vma)
+{
+ return i915_is_dpt(vma->vm);
+}
+
static inline bool i915_vma_has_ggtt_write(const struct i915_vma *vma)
{
return test_bit(I915_VMA_GGTT_WRITE_BIT, __i915_vma_flags(vma));
--
2.27.0
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[Intel-gfx] [PATCH 1/3] drm/i915/adlp: Require DPT FB CCS color planes to be 2MB aligned
All DPT FB color plane surface base addresses must be 2MB aligned. On ADL_P this means that the offsets in CCS FB object must be also 2MB aligned. Adjusting unaligned offsets for these FBs during commit time (compensating with the x/y offsets) doesn't work, since the big alignment would most probably lead to an x/y offset mismatch error between the main and CCS planes. We can overcome this limitation by remapping CCS FBs, so that each color plane is at an aligned offset, leaving x/y for each plane unadjusted during commit and so not causing an x/y mismatch error. However remapping for CCS FBs will be done as a follow-up, so for now require that user space allocates the FB obj with properly aligned planes. v2: s/SZ_2M/512*4k/ for clarity. (Ville) Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fb.c | 13 +++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index a005c68889e7c..c60a81a81c09c 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -355,8 +355,17 @@ static int intel_fb_offset_to_xy(int *x, int *y, unsigned int height; u32 alignment; - if (DISPLAY_VER(i915) >= 12 && - is_semiplanar_uv_plane(fb, color_plane)) + /* +* All DPT color planes must be 512*4k aligned (the amount mapped by a +* single DPT page). For ADL_P CCS FBs this only works by requiring +* the allocated offsets to be 2MB aligned. Once supoort to remap +* such FBs is added we can remove this requirement, as then all the +* planes can be remapped to an aligned offset. +*/ + if (IS_ALDERLAKE_P(i915) && is_ccs_modifier(fb->modifier)) + alignment = 512 * 4096; + else if (DISPLAY_VER(i915) >= 12 && +is_semiplanar_uv_plane(fb, color_plane)) alignment = intel_tile_row_size(fb, color_plane); else if (fb->modifier != DRM_FORMAT_MOD_LINEAR) alignment = intel_tile_size(i915); -- 2.27.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] drm/i915/adlp: Fix GEM VM asserts for DPT VMs
An object mapped via DPT can have remapped and rotated VMA instances
besides the normal VMA instance, similarly to GGTT VMA instances.
Adjust the corresponding VMA lookup asserts.
While at it also check if a DPT VM is passed incorrectly to
i915_vm_to_ppgtt().
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/gt/intel_gtt.h | 3 ++-
drivers/gpu/drm/i915/i915_vma.c | 2 +-
drivers/gpu/drm/i915/i915_vma.h | 2 +-
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index ca00b45827b74..50a98ce39f74b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -359,6 +359,7 @@ struct i915_ppgtt {
#define i915_is_ggtt(vm) ((vm)->is_ggtt)
#define i915_is_dpt(vm) ((vm)->is_dpt)
+#define i915_is_ggtt_or_dpt(vm) (i915_is_ggtt(vm) || i915_is_dpt(vm))
int __must_check
i915_vm_lock_objects(struct i915_address_space *vm, struct i915_gem_ww_ctx
*ww);
@@ -393,7 +394,7 @@ static inline struct i915_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
BUILD_BUG_ON(offsetof(struct i915_ppgtt, vm));
- GEM_BUG_ON(i915_is_ggtt(vm));
+ GEM_BUG_ON(i915_is_ggtt_or_dpt(vm));
return container_of(vm, struct i915_ppgtt, vm);
}
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index a6cd0fa628477..b319fd3f91cc3 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -274,7 +274,7 @@ i915_vma_instance(struct drm_i915_gem_object *obj,
{
struct i915_vma *vma;
- GEM_BUG_ON(view && !i915_is_ggtt(vm));
+ GEM_BUG_ON(view && !i915_is_ggtt_or_dpt(vm));
GEM_BUG_ON(!atomic_read(>open));
spin_lock(>vma.lock);
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 8df784a026d21..2a108e66cd495 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -158,7 +158,7 @@ i915_vma_compare(struct i915_vma *vma,
{
ptrdiff_t cmp;
- GEM_BUG_ON(view && !i915_is_ggtt(vm));
+ GEM_BUG_ON(view && !i915_is_ggtt_or_dpt(vm));
cmp = ptrdiff(vma->vm, vm);
if (cmp)
--
2.27.0
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[Intel-gfx] [PATCH 2/3] drm/i915/dp: use opregion mailbox #5 EDID for eDP, if available
From: Jani Nikula
If a panel's EDID is broken, there may be an override EDID set in the
ACPI OpRegion mailbox #5. Use it if available.
Fixes the GPD Win Max display.
Cc: Uma Shankar
Signed-off-by: Jani Nikula
Signed-off-by: Anisse Astier
[Anisse changes: function name]
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 5c983044..43fb485c0e02 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5191,6 +5191,9 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
goto out_vdd_off;
}
+ /* Set up override EDID, if any, from ACPI OpRegion */
+ intel_opregion_edid_probe(intel_connector);
+
mutex_lock(>mode_config.mutex);
edid = drm_get_edid(connector, _dp->aux.ddc);
if (edid) {
--
2.31.1
___
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[Intel-gfx] [PATCH 0/3] GPD Win Max display fixes
This patch series is for making the GPD Win Max display usable with Linux. The GPD Win Max is a small laptop, and its eDP panel does not send an EDID over DPCD; the EDID is instead available in the intel opregion, in mailbox #5 [1] The first two patches are based on Jani's patch series [2] adding support for the opregion, with minimal changes. I've change authorship for the first, but we can revert it. The third patch is just to fix the orientation of the panel. For some reason it does not work at boot when an external display is plugged, but I doubt this is specific to this hardware. [1]: https://gitlab.freedesktop.org/drm/intel/-/issues/3454 [2]: https://patchwork.kernel.org/project/intel-gfx/patch/20200828061941.17051-1-jani.nik...@intel.com/ Anisse Astier (2): drm/i915/opregion: add support for mailbox #5 EDID drm: Add orientation quirk for GPD Win Max Jani Nikula (1): drm/i915/dp: use opregion mailbox #5 EDID for eDP, if available .../gpu/drm/drm_panel_orientation_quirks.c| 6 ++ drivers/gpu/drm/i915/display/intel_dp.c | 3 + drivers/gpu/drm/i915/display/intel_opregion.c | 69 ++- drivers/gpu/drm/i915/display/intel_opregion.h | 8 +++ 4 files changed, 85 insertions(+), 1 deletion(-) -- 2.31.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] drm: Add orientation quirk for GPD Win Max
Panel is 800x1280, but mounted on a laptop form factor, sideways.
Signed-off-by: Anisse Astier
---
drivers/gpu/drm/drm_panel_orientation_quirks.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c
b/drivers/gpu/drm/drm_panel_orientation_quirks.c
index f6bdec7fa925..3c3f4ed89173 100644
--- a/drivers/gpu/drm/drm_panel_orientation_quirks.c
+++ b/drivers/gpu/drm/drm_panel_orientation_quirks.c
@@ -148,6 +148,12 @@ static const struct dmi_system_id orientation_data[] = {
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "MicroPC"),
},
.driver_data = (void *)_rightside_up,
+ }, {/* GPD Win Max */
+ .matches = {
+ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "GPD"),
+ DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "G1619-01"),
+ },
+ .driver_data = (void *)_rightside_up,
}, {/*
* GPD Pocket, note that the the DMI data is less generic then
* it seems, devices with a board-vendor of "AMI Corporation"
--
2.31.1
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[Intel-gfx] [PATCH 1/3] drm/i915/opregion: add support for mailbox #5 EDID
The ACPI OpRegion Mailbox #5 ASLE extension may contain an EDID to be
used for the embedded display. Add support for using it via by adding
the EDID to the list of available modes on the connector.
Based on original patch by: Jani Nikula
Changes:
- EDID is copied and validated with drm_edid_is_valid
- Mode is now added via drm_add_edid_modes instead of using override
mechanism
Cc: Jani Nikula
Cc: Uma Shankar
Cc: Ville Syrjälä
Signed-off-by: Anisse Astier
---
drivers/gpu/drm/i915/display/intel_opregion.c | 69 ++-
drivers/gpu/drm/i915/display/intel_opregion.h | 8 +++
2 files changed, 76 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c
b/drivers/gpu/drm/i915/display/intel_opregion.c
index dfd724e506b5..ef8d38f041eb 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -196,6 +196,8 @@ struct opregion_asle_ext {
#define ASLE_IUER_WINDOWS_BTN (1 << 1)
#define ASLE_IUER_POWER_BTN(1 << 0)
+#define ASLE_PHED_EDID_VALID_MASK 0x3
+
/* Software System Control Interrupt (SWSCI) */
#define SWSCI_SCIC_INDICATOR (1 << 0)
#define SWSCI_SCIC_MAIN_FUNCTION_SHIFT 1
@@ -909,8 +911,10 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
opregion->asle->ardy = ASLE_ARDY_NOT_READY;
}
- if (mboxes & MBOX_ASLE_EXT)
+ if (mboxes & MBOX_ASLE_EXT) {
drm_dbg(_priv->drm, "ASLE extension supported\n");
+ opregion->asle_ext = base + OPREGION_ASLE_EXT_OFFSET;
+ }
if (intel_load_vbt_firmware(dev_priv) == 0)
goto out;
@@ -1037,6 +1041,68 @@ intel_opregion_get_panel_type(struct drm_i915_private
*dev_priv)
return ret - 1;
}
+/**
+ * intel_opregion_edid_probe - Add EDID from ACPI OpRegion mailbox #5
+ * @intel_connector: eDP connector
+ *
+ * This reads the ACPI Opregion mailbox #5 to extract the EDID that is passed
+ * to it.
+ *
+ * Will take a lock on the DRM mode_config to add the EDID; make sure it isn't
+ * called with lock taken.
+ *
+ */
+void intel_opregion_edid_probe(struct intel_connector *intel_connector)
+{
+ struct drm_connector *connector = _connector->base;
+ struct drm_i915_private *i915 = to_i915(connector->dev);
+ struct intel_opregion *opregion = >opregion;
+ const void *in_edid;
+ const struct edid *edid;
+ struct edid *new_edid;
+ int len, ret, num;
+
+ if (!opregion->asle_ext || connector->override_edid)
+ return;
+
+ in_edid = opregion->asle_ext->bddc;
+
+ /* Validity corresponds to number of 128-byte blocks */
+ len = (opregion->asle_ext->phed & ASLE_PHED_EDID_VALID_MASK) * 128;
+ if (!len || !memchr_inv(in_edid, 0, len))
+ return;
+
+ edid = in_edid;
+
+ if (len < EDID_LENGTH * (1 + edid->extensions)) {
+ drm_dbg_kms(>drm, "Invalid EDID in ACPI OpRegion (Mailbox
#5)\n");
+ return;
+ }
+ new_edid = drm_edid_duplicate(edid);
+ if (!new_edid) {
+ drm_err(>drm, "Cannot duplicate EDID\n");
+ return;
+ }
+ if (!drm_edid_is_valid(new_edid)) {
+ kfree(new_edid);
+ drm_dbg_kms(>drm, "Cannot validate EDID in ACPI OpRegion
(Mailbox #5)\n");
+ return;
+ }
+
+ ret = drm_connector_update_edid_property(connector, new_edid);
+ if (ret) {
+ kfree(new_edid);
+ return;
+ }
+
+ mutex_lock(>dev->mode_config.mutex);
+ num = drm_add_edid_modes(connector, new_edid);
+ mutex_unlock(>dev->mode_config.mutex);
+
+ drm_dbg_kms(>drm, "Using OpRegion EDID for [CONNECTOR:%d:%s],
added %d mode(s)\n",
+ connector->base.id, connector->name, num);
+}
+
void intel_opregion_register(struct drm_i915_private *i915)
{
struct intel_opregion *opregion = >opregion;
@@ -1127,6 +1193,7 @@ void intel_opregion_unregister(struct drm_i915_private
*i915)
opregion->acpi = NULL;
opregion->swsci = NULL;
opregion->asle = NULL;
+ opregion->asle_ext = NULL;
opregion->vbt = NULL;
opregion->lid_state = NULL;
}
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h
b/drivers/gpu/drm/i915/display/intel_opregion.h
index 4aa68ffbd30e..c1ecfcbb6f55 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.h
+++ b/drivers/gpu/drm/i915/display/intel_opregion.h
@@ -29,12 +29,14 @@
#include
struct drm_i915_private;
+struct intel_connector;
struct intel_encoder;
struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;
+struct opregion_asle_ext;
struct intel_opregion {
struct opregion_header *header;
@@ -43,6 +45,7 @@ struct intel_opregion {
u32 swsci_gbda_sub_functions;
u32 swsci_sbcb_sub_functions;
struct opregion_asle
Re: [Intel-gfx] [PATCH v3 07/12] drm, drm/i915: Move the memcpy_from_wc functionality to core drm
On Fri, 21 May 2021 at 16:33, Thomas Hellström
wrote:
>
> Memcpy from wc will be used as well by TTM memcpy.
> Move it to core drm, and make the interface do the right thing
> even on !X86.
>
> Cc: Christian König
> Cc: Daniel Vetter
> Cc: Dave Airlie
> Signed-off-by: Thomas Hellström
> ---
> +
> +#ifdef CONFIG_X86
> +bool drm_memcpy_from_wc(void *dst, const void *src, unsigned long len);
> +bool drm_memcpy_from_wc_dbm(struct dma_buf_map *dst,
> + const struct dma_buf_map *src,
> + unsigned long len);
> +void drm_unaligned_memcpy_from_wc(void *dst, const void *src, unsigned long
> len);
> +
> +/* The movntdqa instructions used for memcpy-from-wc require 16-byte
> alignment,
> + * as well as SSE4.1 support. drm_memcpy_from_wc() will report if it cannot
> + * perform the operation. To check beforehand, pass in the parameters to
> + * drm_can_memcpy_from_wc() - since we only care about the low 4 bits,
> + * you only need to pass in the minor offsets, page-aligned pointers are
> + * always valid.
> + *
> + * For just checking for SSE4.1, in the foreknowledge that the future use
> + * will be correctly aligned, just use drm_has_memcpy_from_wc().
> + */
> +#define drm_can_memcpy_from_wc(dst, src, len) \
> + drm_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned
> long)(src) | (len)), NULL, 0)
> +
> +#define drm_has_memcpy_from_wc() \
> + drm_memcpy_from_wc(NULL, NULL, 0)
> +
> +void drm_memcpy_init_early(void);
> +
> +#else
> +
> +#define drm_memcpy_from_wc(_dst, _src, _len) (false)
> +#define drm_memcpy_from_wc_dbm(_dst, _src, _len) (false)
> +#define drm_can_memcpy_from_wc(_dst, _src, _len) (false)
> +#define drm_has_memcpy_from_wc() (false)
Does the compiler not complain for these on !x86, if called without
checking the result of the statement? Maybe just make these function
stubs?
Otherwise,
Reviewed-by: Matthew Auld
> +#define drm_unaligned_memcpy_from_wc(_dst, _src, _len) WARN_ON(1)
> +#define drm_memcpy_init_early() do {} while (0)
> +#endif /* CONFIG_X86 */
> +#endif /* __DRM_MEMCPY_H__ */
> --
> 2.31.1
>
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Re: [Intel-gfx] [PATCH v7 01/15] swiotlb: Refactor swiotlb init functions
> > do the set_memory_decrypted()+memset(). Is this okay or should > > swiotlb_init_io_tlb_mem() add an additional argument to do this > > conditionally? > > I'm actually not sure if this it okay. If not, will add an additional > argument for it. Any observations discovered? (Want to make sure my memory-cache has the correct semantics for set_memory_decrypted in mind). > > > -- > > Florian ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
