== Series Details ==
Series: drm/i915/hdcp: HDCP2.2 MST dock fixes (rev8)
URL : https://patchwork.freedesktop.org/series/93570/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10537_full -> Patchwork_20921_full
Summary
> -Original Message-
> From: Intel-gfx On Behalf Of Talla
> Raviteja Goud
> Sent: Friday, September 3, 2021 11:51 PM
> To: intel-gfx@lists.freedesktop.org; Surendrakumar Upadhyay, TejaskumarX
> ; Meena, Mahesh
> ; Pandey, Hariom
> Cc: Talla, RavitejaX Goud ; De Marchi, Lucas
>
>
Hi Jaswanth ,
Could you please raise a issue for below failure and re-report the results.
https://patchwork.freedesktop.org/series/93570/
Thanks,
Anshuman Gupta.
> -Original Message-
> From: Gupta, Anshuman
> Sent: Tuesday, September 7, 2021 9:52 AM
> To: Li, Juston ; Vudum,
== Series Details ==
Series: drm/i915/adlp: Add support for remapping CCS FBs (rev3)
URL : https://patchwork.freedesktop.org/series/94108/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10553_full -> Patchwork_20971_full
Hi Lakshmi ,
Below test failure are not related to Display and HDCP.
spec@!opengl 3.0@required-renderbuffer-attachment-formats (NEW):
pig-glk-j5005: NOTRUN -> INCOMPLETE +2 similar issues
Could you please raise issue and re-report the results.
Thanks,
Anshuman Gupta.
From: Intel-gfx
> -Original Message-
> From: Latvala, Petri
> Sent: Monday, September 6, 2021 4:56 PM
> To: Tvrtko Ursulin
> Cc: jim.cro...@gmail.com; Intel Graphics Development g...@lists.freedesktop.org>; Bhatt, Jigar ; Gupta,
> Anshuman
> Subject: Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for use
== Series Details ==
Series: drm/i915/adlp: Add support for remapping CCS FBs (rev3)
URL : https://patchwork.freedesktop.org/series/94108/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10553 -> Patchwork_20971
Summary
The tile size for all surface types is 4 kbyte (or 2 kbyte on old
platforms), with the exception of the TGL/ADL CCS surface where the tile
size is 64 bytes. To be able to remap CCS FBs the CCS surface tile needs
to be defined as 4 kbyte as well (the granularity of GTT pages in a
remapped view).
Resending [1] to test with the fixed IGT changes at [2]. Sending only a
cover letter doesn't seem to trigger a new patchwork test run, so try
again also sending the first patch.
[1] https://patchwork.freedesktop.org/series/94108/
[2] https://patchwork.freedesktop.org/series/94107/
Test-with:
Resending [1] to test with the fixed IGT changes at [2].
[1] https://patchwork.freedesktop.org/series/94108/
[2] https://patchwork.freedesktop.org/series/94107/
Test-with: 20210907015807.3932309-1-imre.d...@intel.com
Cc: Juha-Pekka Heikkila
Cc: Nanley G Chery
Imre Deak (6):
drm/i915: Use
== Series Details ==
Series: drm/i915: move display funcs into a display struct. (v2)
URL : https://patchwork.freedesktop.org/series/94396/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10553 -> Patchwork_20970
Summary
From: Dave Airlie
This is the first step in an idea to refactor the display code
into a bit more of a corner.
v2: move display to being a pointer.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_audio.c| 24 +--
drivers/gpu/drm/i915/display/intel_cdclk.c| 148
This is my alternate first patch for the sequence I proposed earlier.
Of course while I'm looking at funcs I realise a lot of them are kinda
pointless and could be refactored (tangents on tangents).
Dave.
== Series Details ==
Series: Add Support for Plane Color Lut and CSC features (rev2)
URL : https://patchwork.freedesktop.org/series/90825/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10553_full -> Patchwork_20969_full
== Series Details ==
Series: Add Support for Plane Color Lut and CSC features (rev2)
URL : https://patchwork.freedesktop.org/series/90825/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10553 -> Patchwork_20969
Summary
== Series Details ==
Series: Add Support for Plane Color Lut and CSC features (rev2)
URL : https://patchwork.freedesktop.org/series/90825/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
== Series Details ==
Series: Add Support for Plane Color Lut and CSC features (rev2)
URL : https://patchwork.freedesktop.org/series/90825/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0bd5f1aa34e1 drm: RFC for Plane Color Hardware Pipeline
-:18: WARNING:FILE_PATH_CHANGES:
== Series Details ==
Series: drm/i915/adlp: Add support for remapping CCS FBs (rev2)
URL : https://patchwork.freedesktop.org/series/94108/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10553_full -> Patchwork_20968_full
Extract the LUT and program plane gamma registers.
Enabled multi segmented lut as well.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 89 ++
drivers/gpu/drm/i915/i915_reg.h| 9 ++-
2 files changed, 94 insertions(+), 4 deletions(-)
Enable plane gamma feature in check callbacks. Decide
based on the user input.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
Add macros to define Plane Gamma registers
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 73 +
1 file changed, 73 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ceee500e64d7..fc4f8b430518
Add Plane Gamma Lut as a blob property.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic_state_helper.c | 3 +++
drivers/gpu/drm/drm_atomic_uapi.c | 10 ++
drivers/gpu/drm/drm_color_mgmt.c | 18 ++
include/drm/drm_plane.h | 14
Define the structure with XE_LPD gamma lut ranges. HDR and SDR planes
have different capabilities, implemented respective structure for
the HDR planes. Degamma and GAMMA has same Lut caps for SDR planes,
extended the same.
Initialize the mode range caps as well.
Signed-off-by: Uma Shankar
Add Plane Gamma Mode as a blob property. This is an enum property
with values as blob_id's and exposes the various gamma modes
supported and the lut ranges. Getting the blob id in userspace,
user can get the mode supported and also the range of gamma mode
supported with number of lut coefficients.
Implement plane CSC for ICL+
Signed-off-by: Uma Shankar
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 5 +-
drivers/gpu/drm/i915/display/intel_color.c| 82 +++
.../drm/i915/display/skl_universal_plane.c| 4 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
Define Register macros for plane CSC.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 43 +
1 file changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0c36a330734f..20c1b8ddded8 100644
Add a DRM helper to attach ctm property.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_color_mgmt.c | 10 ++
include/drm/drm_plane.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index
Add a blob property for plane CSC usage.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic_state_helper.c | 3 +++
drivers/gpu/drm/drm_atomic_uapi.c | 10 ++
drivers/gpu/drm/drm_color_mgmt.c | 11 +++
include/drm/drm_plane.h | 15
Load plane color luts as part of atomic plane updates.
This will be done only if the plane color luts are changed.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 3 +++
drivers/gpu/drm/i915/display/intel_atomic_plane.h | 1 +
Initialize plane color features for XE_LPD.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_atomic_plane.h | 1 +
drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
Extended glk_plane_color_ctl to have plane color checks. This helps
enabling the degamma or gamma block based on user inputs.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 5 +
1 file changed, 5 insertions(+)
diff --git
Extract the LUT and program plane degamma registers.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 116 +
drivers/gpu/drm/i915/i915_reg.h| 2 +
2 files changed, 118 insertions(+)
diff --git
Enable and initialize plane color features.
Also initialize the color features of HDR planes.
Signed-off-by: Uma Shankar
Signed-off-by: Bhanuprakash Modem
---
drivers/gpu/drm/i915/display/intel_color.c | 22 +-
drivers/gpu/drm/i915/display/intel_color.h | 2 ++
Add the Color capabilities of SDR planes.
Signed-off-by: Uma Shankar
Signed-off-by: Bhanuprakash Modem
---
drivers/gpu/drm/i915/display/intel_color.c | 67 --
1 file changed, 63 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
Add macros to define Plane Degamma registers
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 52 +
1 file changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 313432ed6196..919982c878ac
This is a RFC proposal for plane color hardware blocks.
It exposes the property interface to userspace and calls
out the details or interfaces created and the intended
purpose.
Credits: Ville Syrjälä
Signed-off-by: Uma Shankar
---
Documentation/gpu/rfc/drm_color_pipeline.rst | 167
Add Plane Degamma Mode as an enum property. Create a helper
function for all plane color management features.
This is an enum property with values as blob_id's and exposes
the various gamma modes supported and the lut ranges. Getting
the blob id in userspace, user can get the mode supported and
Add Plane Degamma Lut as a blob property. User will calculate
the lut values, create the blob and send it to driver using
this property. Lut calculation will be based on the gamma mode
chosen out of the gamma mode exposed.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic_state_helper.c
Define the structure with XE_LPD degamma lut ranges. HDR and SDR
planes have different capabilities, implemented respective
structure for the HDR planes.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 52 ++
1 file changed, 52 insertions(+)
diff
Existing LUT precision structure is having only 16 bit
precision. This is not enough for upcoming enhanced hardwares
and advance usecases like HDR processing. Hence added a new
structure with 32 bit precision values.
This also defines a new structure to define color lut ranges,
along with related
This is how a typical display color hardware pipeline looks like:
+---+
|RAM|
| +--++-++-+ |
| | FB 1 || FB 2 || FB N| |
| +--++-++-+
== Series Details ==
Series: drm/i915/adlp: Add support for remapping CCS FBs (rev2)
URL : https://patchwork.freedesktop.org/series/94108/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10553 -> Patchwork_20968
Summary
On Mon, 6 Sept 2021 at 18:18, Jani Nikula wrote:
>
> On Mon, 06 Sep 2021, Dave Airlie wrote:
> > From: Dave Airlie
> >
> > This is the first step in an idea to refactor the display code
> > into a bit more of a corner.
>
> So, do we want to make i915->display a pointer?
>
> If we do, and we're
== Series Details ==
Series: drm/i915: Suspend / resume backup- and restore of LMEM. (rev2)
URL : https://patchwork.freedesktop.org/series/94278/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10553_full -> Patchwork_20967_full
On Alderlake-P for all CCS modifiers the main surface pitch must be
either 8 Y-tile width or the multiple of 16 Y-tile widths. The CCS
surface pitch must be rounded up to power-of-two.
Adjust the modifier descriptions accordingly.
Cc: Nanley G Chery
Cc: Juha-Pekka Heikkila
Cc:
Add support for remapping CCS FBs on ADL-P to remove the restriction
of the power-of-two sized stride and the 2MB surface offset alignment
for these FBs.
We can only remap the tiles on the main surface, not the tiles on the
CCS surface, so userspace has to generate the CCS surface aligning to
the
Atm the DPT object can accommodate only one VMA, so the VMA offset will
be always 0. Add an assert for this.
Cc: Juha-Pekka Heikkila
Signed-off-by: Imre Deak
Reviewed-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 5 +
1 file changed, 5 insertions(+)
Follow the usual new->old order in intel_fb_stride_alignment() platform
check ladder.
Cc: Juha-Pekka Heikkila
Signed-off-by: Imre Deak
Reviewed-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_fb.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff
At the moment CCS FB strides must be power-of-two sized, but a follow-up
change will add support remapping these FBs, allowing the FB passed in
by userspace to have a non-POT sized stride. For these remapped FBs we
can only remap the main surface, not the CCS surface. This means that
userspace has
The tile size for all surface types is 4 kbyte (or 2 kbyte on old
platforms), with the exception of the TGL/ADL CCS surface where the tile
size is 64 bytes. To be able to remap CCS FBs the CCS surface tile needs
to be defined as 4 kbyte as well (the granularity of GTT pages in a
remapped view).
This is v2 of [1] fixing the initialization of plane_alignment in patch
5 and issues reported by checkpatch, sparse. Also the last patch in this
series adds a description to drm_fourcc.h about the main and CCS surface
stride requirements for all CCS modifiers on ADL-P.
The corresponding IGT
> I'll try to extract the "executive summary" from this, you tell me if I
> got it right.
>
> So using or not using dynamic debug for DRM debug ends up being about
> shifting the cost between kernel binary size (data section grows by each
> pr_debug call site) and runtime conditionals?
Yes.
>
On Mon, Sep 6, 2021 at 6:26 AM Tvrtko Ursulin <
tvrtko.ursu...@linux.intel.com> wrote:
>
>
> On 03/09/2021 20:22, jim.cro...@gmail.com wrote:
> > On Fri, Sep 3, 2021 at 5:07 AM Tvrtko Ursulin
> > wrote:
> >>
> >>
> >> On 31/08/2021 21:21, Jim Cromie wrote:
> >>> The gvt component of this driver
== Series Details ==
Series: drm/i915: Suspend / resume backup- and restore of LMEM. (rev2)
URL : https://patchwork.freedesktop.org/series/94278/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10553 -> Patchwork_20967
== Series Details ==
Series: drm/i915: Suspend / resume backup- and restore of LMEM. (rev2)
URL : https://patchwork.freedesktop.org/series/94278/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
aaef4ee507ef drm/i915/ttm: Implement a function to copy the contents of two
TTM-base
Pinned contexts, like the migrate contexts need reset after resume
since their context image may have been lost. Also the GuC needs to
register pinned contexts.
Add a list to struct intel_engine_cs where we add all pinned contexts on
creation, and traverse that list at resume time to reset the
We really only need memcpy restore for objects that affect the
operability of the migrate context. That is, primarily the page-table
objects of the migrate VM.
Add an object flag, I915_BO_ALLOC_PM_EARLY for objects that need early
restores using memcpy and a way to assign LMEM page-table object
Pinned context images are now reset during resume. Don't back them up,
and assuming that rings can be assumed empty at suspend, don't back them
up either.
Introduce a new object flag, I915_BO_ALLOC_PM_VOLATILE meaning that an
object is allowed to lose its content on suspend.
Signed-off-by:
An upcoming common pattern is to traverse the region object list and
perform certain actions on all objects in a region. It's a little tricky
to get the list locking right, in particular since a gem object may
change region unless it's pinned or the object lock is held.
Define a function that
Just evict unpinned objects to system. For pinned LMEM objects,
make a backup system object and blit the contents to that.
Backup is performed in three steps,
1: Opportunistically evict evictable objects using the gpu blitter.
2: After gt idle, evict evictable objects using the gpu blitter. This
When backing up or restoring contents of pinned objects at suspend /
resume time we need to allocate a new object as the backup. Add a function
to facilitate copies between the two. Some data needs to be copied before
the migration context is ready for operation, so make sure we can
disable
Implement backup and restore of LMEM during suspend / resume.
What complicates things a bit is handling of pinned LMEM memory during
suspend and the fact that we might be dealing with unmappable LMEM in
the future, which makes us want to restrict the number of pinned objects that
need memcpy
Looks good to me.
Reviewed-by: Gwan-gyeong Mun
On 8/25/21 3:58 AM, José Roberto de Souza wrote:
After commit "drm/i915/display/skl+: Drop frontbuffer rendering
support" frontbuffer rendering is not supported for display 9 and
newer and as PSR is only supported by default in display 9 and newer
On 06/09/2021 14:48, Matthew Auld wrote:
On 06/09/2021 13:53, Tvrtko Ursulin wrote:
On 06/09/2021 13:30, Matthew Auld wrote:
On 06/09/2021 13:19, Tvrtko Ursulin wrote:
On 06/09/2021 10:17, Matthew Auld wrote:
Since the object might still be active here, the shrink_all will
simply
ignore
On 06/09/2021 13:53, Tvrtko Ursulin wrote:
On 06/09/2021 13:30, Matthew Auld wrote:
On 06/09/2021 13:19, Tvrtko Ursulin wrote:
On 06/09/2021 10:17, Matthew Auld wrote:
Since the object might still be active here, the shrink_all will simply
ignore it, which blows up in the test, since the
On 06/09/2021 13:30, Matthew Auld wrote:
On 06/09/2021 13:19, Tvrtko Ursulin wrote:
On 06/09/2021 10:17, Matthew Auld wrote:
Since the object might still be active here, the shrink_all will simply
ignore it, which blows up in the test, since the pages will still be
there. Currently THP is
On 06/09/2021 13:19, Tvrtko Ursulin wrote:
On 06/09/2021 10:17, Matthew Auld wrote:
Since the object might still be active here, the shrink_all will simply
ignore it, which blows up in the test, since the pages will still be
there. Currently THP is disabled which should result in the test
On 03/09/2021 20:22, jim.cro...@gmail.com wrote:
On Fri, Sep 3, 2021 at 5:07 AM Tvrtko Ursulin
wrote:
On 31/08/2021 21:21, Jim Cromie wrote:
The gvt component of this driver has ~120 pr_debugs, in 9 categories
quite similar to those in DRM. Following the interface model of
drm.debug, add
On 06/09/2021 10:17, Matthew Auld wrote:
Since the object might still be active here, the shrink_all will simply
ignore it, which blows up in the test, since the pages will still be
there. Currently THP is disabled which should result in the test being
skipped, but if we ever re-enable THP we
== Series Details ==
Series: drm/i915/selftests: fixup igt_shrink_thp (rev2)
URL : https://patchwork.freedesktop.org/series/93128/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10552_full -> Patchwork_20966_full
Summary
On Mon, Sep 06, 2021 at 11:04:13AM +0100, Tvrtko Ursulin wrote:
>
> On 03/09/2021 14:01, Petri Latvala wrote:
> > On Fri, Sep 03, 2021 at 12:29:51PM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 03/09/2021 01:31, jim.cro...@gmail.com wrote:
> > > >
> > > >
> > > > On Tue, Aug 31, 2021 at 5:38 PM
== Series Details ==
Series: drm: Add privacy-screen class and connector properties (rev4)
URL : https://patchwork.freedesktop.org/series/79259/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10552_full -> Patchwork_20965_full
On 03/09/2021 22:57, jim.cro...@gmail.com wrote:
On Fri, Sep 3, 2021 at 5:15 AM Tvrtko Ursulin
wrote:
On 31/08/2021 21:21, Jim Cromie wrote:
drm's debug system writes 10 distinct categories of messages to syslog
using a small API[1]: drm_dbg*(10 names), DRM_DEV_DEBUG*(3 names),
== Series Details ==
Series: drm/i915/selftests: fixup igt_shrink_thp (rev2)
URL : https://patchwork.freedesktop.org/series/93128/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10552 -> Patchwork_20966
Summary
---
On 03/09/2021 14:01, Petri Latvala wrote:
On Fri, Sep 03, 2021 at 12:29:51PM +0100, Tvrtko Ursulin wrote:
On 03/09/2021 01:31, jim.cro...@gmail.com wrote:
On Tue, Aug 31, 2021 at 5:38 PM Patchwork
mailto:patchw...@emeril.freedesktop.org>> wrote:
__
*Patch Details*
Looks good to me.
Reviewed-by: Gwan-gyeong Mun
On 9/4/21 3:26 AM, Souza, Jose wrote:
On Fri, 2021-09-03 at 22:09 +, Souza, Jose wrote:
On Thu, 2021-09-02 at 21:42 +0300, Gwan-gyeong Mun wrote:
On 8/25/21 3:58 AM, José Roberto de Souza wrote:
By now all the userspace applications should
== Series Details ==
Series: drm/i915/adl_s: Remove require_force_probe protection
URL : https://patchwork.freedesktop.org/series/94338/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10550_full -> Patchwork_20955_full
== Series Details ==
Series: drm/i915/selftests: fixup igt_shrink_thp (rev2)
URL : https://patchwork.freedesktop.org/series/93128/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c703d855f95d drm/i915/selftests: fixup igt_shrink_thp
-:52: CHECK:LINE_SPACING: Please don't use
Looks good to me.
Reviewed-by: Gwan-gyeong Mun
On 9/4/21 1:10 AM, José Roberto de Souza wrote:
Both functions are pretty much equal, with minor changes that can be
handled by a single parameter.
v3:
- not scheduling work from invalidate operations
Cc: Gwan-gyeong Mun
Signed-off-by: José
Since the object might still be active here, the shrink_all will simply
ignore it, which blows up in the test, since the pages will still be
there. Currently THP is disabled which should result in the test being
skipped, but if we ever re-enable THP we might start seeing the failure.
Fix this by
== Series Details ==
Series: drm: Add privacy-screen class and connector properties (rev4)
URL : https://patchwork.freedesktop.org/series/79259/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10552 -> Patchwork_20965
Looks good to me.
Reviewed-by: Gwan-gyeong Mun
On 9/4/21 1:10 AM, José Roberto de Souza wrote:
It started as a code style fix for the lines above 100 col but it
turned out to simplifications to intel_drrs_set_state().
Now it receives the desired refresh rate type, high or low.
v3:
- Fixed the
On Fri, Sep 03, 2021 at 09:05:00AM +0100, Tvrtko Ursulin wrote:
>
> On 02/09/2021 15:20, Daniel Vetter wrote:
> > The important part isn't so much that this does an rcu lookup - that's
> > more an implementation detail, which will also be removed.
> >
> > The thing that makes this different from
== Series Details ==
Series: drm: Add privacy-screen class and connector properties (rev4)
URL : https://patchwork.freedesktop.org/series/79259/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
== Series Details ==
Series: drm: Add privacy-screen class and connector properties (rev4)
URL : https://patchwork.freedesktop.org/series/79259/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bc1b50a446f7 drm/connector: Add support for privacy-screen properties (v4)
-:30:
== Series Details ==
Series: drm/i915: Mark GPU wedging on driver unregister unrecoverable (rev2)
URL : https://patchwork.freedesktop.org/series/94247/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10550_full -> Patchwork_20953_full
== Series Details ==
Series: drm/i915/adl_s: Remove require_force_probe protection
URL : https://patchwork.freedesktop.org/series/94338/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10550 -> Patchwork_20955
Summary
On Mon, 06 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> This is the first step in an idea to refactor the display code
> into a bit more of a corner.
So, do we want to make i915->display a pointer?
If we do, and we're about to touch every place accessing the display
struct, we might
Hi,
On Mon, 6 Sep 2021, Kai-Heng Feng wrote:
> Commit 989634fb49ad ("drm/i915/audio: set HDA link parameters in
> driver") makes HDMI audio on Lenovo P350 disappear.
>
> So in addition to TGL, extend the logic to RKL to use BIOS provided
> value to fix the regression.
thanks Kai-Heng! We were
Add support for eDP panels with a built-in privacy screen using the
new drm_privacy_screen class.
One thing which stands out here is the addition of these 2 lines to
intel_atomic_commit_tail:
for_each_new_connector_in_state(>base, connector, ...
Register a privacy-screen device on laptops with a privacy-screen,
this exports the PrivacyGuard features to user-space using a
standardized vendor-agnostic sysfs interface. Note the sysfs interface
is read-only.
Registering a privacy-screen device with the new privacy-screen class
code will also
Get the privacy-screen / lcdshadow ACPI handles once and cache them,
instead of retrieving them every time we need them.
Reviewed-by: Emil Velikov
Signed-off-by: Hans de Goede
---
drivers/platform/x86/thinkpad_acpi.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
Factor the extended hotkey handling out of hotkey_notify_hotkey() and
into a new hotkey_notify_extended_hotkey() helper.
This is a preparation patch for adding support the privacy-screen hotkey
toggle (which needs some special handling, it should NOT send an evdev
key-event to userspace...).
Add 2 drm_connector privacy-screen helper functions:
1. drm_connector_attach_privacy_screen_provider(), this function creates
and attaches the standard privacy-screen properties and registers a
generic notifier for generating sysfs-connector-status-events on external
changes to the privacy-screen
Add support for privacy-screen consumers to register a notifier to
be notified of external (e.g. done by the hw itself on a hotkey press)
state changes.
Reviewed-by: Emil Velikov
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/drm_privacy_screen.c | 67 +++
Add X86 specific arch init code, which fills the privacy-screen lookup
table by checking for various vendor specific ACPI interfaces for
controlling the privacy-screen.
This initial version only checks for the Lenovo Thinkpad specific ACPI
methods for privacy-screen control.
Reviewed-by: Emil
On some new laptops the LCD panel has a builtin electronic privacy-screen.
We want to export this functionality as a property on the drm connector
object. But often this functionality is not exposed on the GPU but on some
other (ACPI) device.
This commit adds a privacy-screen class allowing the
From: Rajat Jain
Add support for generic electronic privacy screen properties, that
can be added by systems that have an integrated EPS.
Changes in v2 (Hans de Goede)
- Create 2 properties, "privacy-screen sw-state" and
"privacy-screen hw-state", to deal with devices where the OS might be
Hi all,
Here is the privacy-screen related code which I last posted in April 2021
To the best of my knowledge there is consensus about / everyone is in
agreement with the new userspace API (2 connector properties) this
patch-set add (patch 1 of the series).
This is unchanged (except for a rebase
On Mon, Sep 6, 2021 at 12:49 AM Stephen Rothwell wrote:
> Hi all,
>
> On Thu, 2 Sep 2021 07:50:38 +1000 Stephen Rothwell
> wrote:
> >
> > On Fri, 20 Aug 2021 15:23:34 +0900 Masahiro Yamada
> > wrote:
> > >
> > > On Fri, Aug 20, 2021 at 11:33 AM Stephen Rothwell
> > > wrote:
> > > >
> > >
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