[Intel-gfx] [PATCH v4] drm/i915/gt: move remaining debugfs interfaces into gt
From: Andi Shyti
The following interfaces:
i915_wedged
i915_forcewake_user
are dependent on gt values. Put them inside gt/ and drop the
"i915_" prefix name. This would be the new structure:
dri/0/gt
|
+-- forcewake_user
|
\-- reset
For backwards compatibility with existing igt (and the slight
semantic difference between operating on the i915 abi entry
points and the deep gt info):
dri/0
|
+-- i915_wedged
|
\-- i915_forcewake_user
remain at the top level.
Signed-off-by: Andi Shyti
Cc: Tvrtko Ursulin
Cc: Chris Wilson
---
Changelog:
--
v3 -> v4: https://patchwork.freedesktop.org/patch/458225/
* remove the unnecessary interrupt_info_show() information. They
were already removed here by Chris:
cf977e18610e6 ("drm/i915/gem: Spring clean debugfs")
v2 -> v3: https://patchwork.freedesktop.org/patch/458108/
* keep the original interfaces as they were (thanks Chris) but
implement the functionality inside the gt. The upper level
files will call the gt functions (thanks Lucas).
v1 -> v2: https://patchwork.freedesktop.org/patch/456652/
* keep the original interfaces intact (thanks Chris).
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c| 42 ++
drivers/gpu/drm/i915/gt/intel_gt_debugfs.h| 4 ++
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 41 ++
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h | 4 ++
drivers/gpu/drm/i915/i915_debugfs.c | 43 +++
5 files changed, 98 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
index 1fe19ccd27942..f712670993b68 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
@@ -13,6 +13,46 @@
#include "pxp/intel_pxp_debugfs.h"
#include "uc/intel_uc_debugfs.h"
+int reset_show(void *data, u64 *val)
+{
+ struct intel_gt *gt = data;
+ int ret = intel_gt_terminally_wedged(gt);
+
+ switch (ret) {
+ case -EIO:
+ *val = 1;
+ return 0;
+ case 0:
+ *val = 0;
+ return 0;
+ default:
+ return ret;
+ }
+}
+
+int reset_store(void *data, u64 val)
+{
+ struct intel_gt *gt = data;
+
+ /* Flush any previous reset before applying for a new one */
+ wait_event(gt->reset.queue,
+ !test_bit(I915_RESET_BACKOFF, >reset.flags));
+
+ intel_gt_handle_error(gt, val, I915_ERROR_CAPTURE,
+ "Manually reset engine mask to %llx", val);
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(reset_fops, reset_show, reset_store, "%llu\n");
+
+static void gt_debugfs_register(struct intel_gt *gt, struct dentry *root)
+{
+ static const struct intel_gt_debugfs_file files[] = {
+ { "reset", _fops, NULL },
+ };
+
+ intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
+}
+
void intel_gt_debugfs_register(struct intel_gt *gt)
{
struct dentry *root;
@@ -24,6 +64,8 @@ void intel_gt_debugfs_register(struct intel_gt *gt)
if (IS_ERR(root))
return;
+ gt_debugfs_register(gt, root);
+
intel_gt_engines_debugfs_register(gt, root);
intel_gt_pm_debugfs_register(gt, root);
intel_sseu_debugfs_register(gt, root);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
index 8b6fca09897ce..6bc4f044c23f3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
@@ -35,4 +35,8 @@ void intel_gt_debugfs_register_files(struct dentry *root,
const struct intel_gt_debugfs_file *files,
unsigned long count, void *data);
+/* functions that need to be accessed by the upper level non-gt interfaces */
+int reset_show(void *data, u64 *val);
+int reset_store(void *data, u64 val);
+
#endif /* INTEL_GT_DEBUGFS_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 5f84ad6026423..712c91d588eb3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -19,6 +19,46 @@
#include "intel_sideband.h"
#include "intel_uncore.h"
+int __forcewake_user_open(struct intel_gt *gt)
+{
+ atomic_inc(>user_wakeref);
+ intel_gt_pm_get(gt);
+ if (GRAPHICS_VER(gt->i915) >= 6)
+ intel_uncore_forcewake_user_get(gt->uncore);
+
+ return 0;
+}
+
+int __forcewake_user_release(struct intel_gt *gt)
+{
+ if (GRAPHICS_VER(gt->i915) >= 6)
+ intel_uncore_forcewake_user_put(gt->uncore);
+ intel_gt_pm_put(gt);
+ atomic_dec(>user_wakeref);
+
+ return 0;
+}
+
+static int forcewake_user_open(struct inode *inode, struct file *file)
+{
+ struct intel_gt *gt = inode->i_private;
+
+ return
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: move remaining debugfs interfaces into gt (rev11)
== Series Details == Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev11) URL : https://patchwork.freedesktop.org/series/75333/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10700_full -> Patchwork_21301_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21301_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21301_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21301_full: ### IGT changes ### Possible regressions * igt@gem_userptr_blits@huge-split: - shard-snb: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-snb6/igt@gem_userptr_bl...@huge-split.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21301/shard-snb7/igt@gem_userptr_bl...@huge-split.html * igt@i915_pm_dc@dc9-dpms: - shard-tglb: NOTRUN -> [SKIP][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21301/shard-tglb5/igt@i915_pm...@dc9-dpms.html * igt@i915_suspend@debugfs-reader: - shard-kbl: [PASS][4] -> [INCOMPLETE][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-kbl6/igt@i915_susp...@debugfs-reader.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21301/shard-kbl3/igt@i915_susp...@debugfs-reader.html Known issues Here are the changes found in Patchwork_21301_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21301/shard-snb2/igt@gem_ctx_persiste...@legacy-engines-queued.html * igt@gem_eio@in-flight-contexts-10ms: - shard-iclb: [PASS][7] -> [TIMEOUT][8] ([i915#3070]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-iclb5/igt@gem_...@in-flight-contexts-10ms.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21301/shard-iclb8/igt@gem_...@in-flight-contexts-10ms.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][9] -> [TIMEOUT][10] ([i915#2369] / [i915#3063] / [i915#3648]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-tglb2/igt@gem_...@unwedge-stress.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21301/shard-tglb6/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-deadline: - shard-apl: NOTRUN -> [FAIL][11] ([i915#2846]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21301/shard-apl7/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-kbl: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-kbl3/igt@gem_exec_fair@basic-none-...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21301/shard-kbl6/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][14] -> [FAIL][15] ([i915#2842]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21301/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-iclb: NOTRUN -> [FAIL][16] ([i915#2842]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21301/shard-iclb1/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: NOTRUN -> [FAIL][17] ([i915#2842]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21301/shard-glk8/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_schedule@u-submit-early-slice@vecs0: - shard-skl: [PASS][18] -> [INCOMPLETE][19] ([i915#3797]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-skl1/igt@gem_exec_schedule@u-submit-early-sl...@vecs0.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21301/shard-skl6/igt@gem_exec_schedule@u-submit-early-sl...@vecs0.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#2190]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21301/shard-apl6/igt@gem_huc_c...@huc-copy.html * igt@gem_pwrite@basic-exhaustion: - shard-snb: NOTRUN -> [WARN][21] ([i915#2658]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21301/shard-snb5/igt@gem_pwr...@basic-exhaustion.html -
[Intel-gfx] ✗ Fi.CI.IGT: failure for i915: Initial multi-tile support
== Series Details == Series: i915: Initial multi-tile support URL : https://patchwork.freedesktop.org/series/95631/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10700_full -> Patchwork_21298_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21298_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21298_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21298_full: ### IGT changes ### Possible regressions * igt@i915_pm_dc@dc9-dpms: - shard-tglb: NOTRUN -> [SKIP][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/shard-tglb8/igt@i915_pm...@dc9-dpms.html - shard-iclb: NOTRUN -> [SKIP][2] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/shard-iclb3/igt@i915_pm...@dc9-dpms.html Known issues Here are the changes found in Patchwork_21298_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/shard-snb6/igt@gem_ctx_persiste...@legacy-engines-queued.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#2369] / [i915#3063] / [i915#3648]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-tglb2/igt@gem_...@unwedge-stress.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/shard-tglb6/igt@gem_...@unwedge-stress.html - shard-iclb: [PASS][6] -> [TIMEOUT][7] ([i915#2369] / [i915#2481] / [i915#3070]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-iclb6/igt@gem_...@unwedge-stress.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/shard-iclb1/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-deadline: - shard-apl: NOTRUN -> [FAIL][8] ([i915#2846]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/shard-apl7/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-iclb: NOTRUN -> [FAIL][9] ([i915#2842]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/shard-iclb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-glk: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-glk4/igt@gem_exec_fair@basic-p...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/shard-glk5/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#2190]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/shard-apl2/igt@gem_huc_c...@huc-copy.html * igt@gem_pwrite@basic-exhaustion: - shard-snb: NOTRUN -> [WARN][13] ([i915#2658]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/shard-snb6/igt@gem_pwr...@basic-exhaustion.html - shard-glk: NOTRUN -> [WARN][14] ([i915#2658]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/shard-glk6/igt@gem_pwr...@basic-exhaustion.html * igt@gem_pxp@reject-modify-context-protection-off-2: - shard-tglb: NOTRUN -> [SKIP][15] ([i915#4270]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/shard-tglb8/igt@gem_...@reject-modify-context-protection-off-2.html - shard-iclb: NOTRUN -> [SKIP][16] ([i915#4270]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/shard-iclb3/igt@gem_...@reject-modify-context-protection-off-2.html * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled: - shard-glk: NOTRUN -> [SKIP][17] ([fdo#109271]) +36 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/shard-glk6/igt@gem_render_c...@yf-tiled-mc-ccs-to-vebox-y-tiled.html * igt@gen9_exec_parse@batch-invalid-length: - shard-iclb: NOTRUN -> [SKIP][18] ([i915#2856]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/shard-iclb3/igt@gen9_exec_pa...@batch-invalid-length.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [PASS][19] -> [FAIL][20] ([i915#454]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-iclb2/igt@i915_pm...@dc6-psr.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/shard-iclb8/igt@i915_pm...@dc6-psr.html * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp: - shard-apl: NOTRUN ->
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers (rev8)
== Series Details == Series: drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers (rev8) URL : https://patchwork.freedesktop.org/series/95127/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10700_full -> Patchwork_21296_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21296_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21296_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21296_full: ### IGT changes ### Possible regressions * igt@i915_pm_dc@dc9-dpms: - shard-tglb: NOTRUN -> [SKIP][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/shard-tglb6/igt@i915_pm...@dc9-dpms.html - shard-iclb: NOTRUN -> [SKIP][2] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/shard-iclb3/igt@i915_pm...@dc9-dpms.html * igt@i915_suspend@debugfs-reader: - shard-kbl: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-kbl6/igt@i915_susp...@debugfs-reader.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/shard-kbl3/igt@i915_susp...@debugfs-reader.html Known issues Here are the changes found in Patchwork_21296_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-apl: NOTRUN -> [DMESG-WARN][5] ([i915#180]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/shard-apl1/igt@gem_ctx_isolation@preservation...@rcs0.html * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/shard-snb5/igt@gem_ctx_persiste...@legacy-engines-queued.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][7] -> [TIMEOUT][8] ([i915#2369] / [i915#3063] / [i915#3648]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-tglb2/igt@gem_...@unwedge-stress.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/shard-tglb5/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-deadline: - shard-apl: NOTRUN -> [FAIL][9] ([i915#2846]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/shard-apl6/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-kbl: [PASS][10] -> [SKIP][11] ([fdo#109271]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-kbl4/igt@gem_exec_fair@basic-none-sh...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/shard-kbl6/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: NOTRUN -> [FAIL][12] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/shard-kbl4/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-kbl7/igt@gem_exec_fair@basic-n...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/shard-kbl1/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-iclb: NOTRUN -> [FAIL][15] ([i915#2842]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/shard-iclb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: NOTRUN -> [FAIL][16] ([i915#2842]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2190]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/shard-apl1/igt@gem_huc_c...@huc-copy.html * igt@gem_pwrite@basic-exhaustion: - shard-glk: NOTRUN -> [WARN][18] ([i915#2658]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/shard-glk7/igt@gem_pwr...@basic-exhaustion.html * igt@gem_pxp@reject-modify-context-protection-off-2: - shard-iclb: NOTRUN -> [SKIP][19] ([i915#4270]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/shard-iclb3/igt@gem_...@reject-modify-context-protection-off-2.html * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled: - shard-glk: NOTRUN -> [SKIP][20] ([fdo#109271]) +36 similar
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: move remaining debugfs interfaces into gt (rev11)
== Series Details ==
Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev11)
URL : https://patchwork.freedesktop.org/series/75333/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21301
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21301/index.html
Known issues
Here are the changes found in Patchwork_21301 that come from known issues:
### IGT changes ###
Possible fixes
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a:
- {fi-tgl-dsi}: [DMESG-WARN][1] ([i915#1982]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-tgl-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-a.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21301/fi-tgl-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
Participating hosts (40 -> 36)
--
Missing(4): fi-bsw-cyan fi-ilk-m540 fi-hsw-4200u fi-kbl-r
Build changes
-
* Linux: CI_DRM_10700 -> Patchwork_21301
CI-20190529: 20190529
CI_DRM_10700: 6ecdd5e29c83cd8fc191f8cce5c283eefb53c97e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6240: b232a092b9e1b10a8be13601acaa440903b226bc @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21301: 5c3271ef5a87996a244d7a515d6653350053ba01 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5c3271ef5a87 drm/i915/gt: move remaining debugfs interfaces into gt
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21301/index.html
Re: [Intel-gfx] [PATCH v3] drm/dp: Add Additional DP2 Headers
On 2021-10-08 04:36, Tvrtko Ursulin wrote: > > Hi, > > Is it my checkout only or this causes a lot of build warnings for everyone? > > ./include/drm/drm_dp_helper.h:1120: warning: > "DP_TEST_264BIT_CUSTOM_PATTERN_7_0" redefined > 1120 | #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230 > | > In file included from > ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_types.h:35, > from > ./drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:30, > from > ./drivers/gpu/drm/amd/amdgpu/../include/dm_pp_interface.h:26, > from drivers/gpu/drm/amd/amdgpu/amdgpu.h:66, > from drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:40: > ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:871: note: this is > the location of the previous definition > > Etc.. > Fixed by https://patchwork.freedesktop.org/patch/456190/?series=95166=2 but looks like it's not in drm-misc-next. Siqueira, do you have bandwidth to pull that patch into drm-misc-next? Harry > Regards, > > Tvrtko > > > On 30/09/2021 22:21, Rodrigo Siqueira wrote: >> Applied to drm-misc-next. >> >> Thanks >> >> On 09/28, Harry Wentland wrote: >>> On 2021-09-27 15:23, Fangzhi Zuo wrote: Include FEC, DSC, Link Training related headers. Change since v2 - Align with the spec for DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT Signed-off-by: Fangzhi Zuo >>> >>> Reviewed-by: Harry Wentland >>> >>> Harry >>> --- This patch is based on top of the other DP2.0 work in "drm/dp: add LTTPR DP 2.0 DPCD addresses" --- include/drm/drm_dp_helper.h | 20 1 file changed, 20 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1d5b3dbb6e56..a1df35aa6e68 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -453,6 +453,7 @@ struct drm_panel; # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2) # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3) +#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */ /* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */ #define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC /* 0x9E - 0x92 */ @@ -537,6 +538,9 @@ struct drm_panel; #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1 #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2 +/* DFP Capability Extension */ +#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + /* Link Configuration */ #define DP_LINK_BW_SET 0x100 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ @@ -688,6 +692,7 @@ struct drm_panel; #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ # define DP_DECOMPRESSION_EN (1 << 0) +#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */ #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ # define DP_PSR_ENABLE BIT(0) @@ -743,6 +748,7 @@ struct drm_panel; # define DP_RECEIVE_PORT_0_STATUS (1 << 0) # define DP_RECEIVE_PORT_1_STATUS (1 << 1) # define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */ +# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */ #define DP_ADJUST_REQUEST_LANE0_1 0x206 #define DP_ADJUST_REQUEST_LANE2_3 0x207 @@ -865,6 +871,8 @@ struct drm_panel; # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 # define DP_PHY_TEST_PATTERN_CP2520 0x5 +#define DP_PHY_SQUARE_PATTERN 0x249 + #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251 @@ -1109,6 +1117,18 @@ struct drm_panel; #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */ # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f +#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230 +#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250 + +/* DSC Extended Capability Branch Total DSC Resources */ +#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */ +# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) +# define DP_DSC_DECODER_COUNT_SHIFT 5 +#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */ +# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 + /* Protocol Converter Extension */ /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */ #define DP_CEC_TUNNELING_CAPABILITY 0x3000 >>> >>
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/icl: Fix read of memory frequency
== Series Details == Series: drm/i915/icl: Fix read of memory frequency URL : https://patchwork.freedesktop.org/series/95627/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10700_full -> Patchwork_21295_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21295_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21295_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21295_full: ### IGT changes ### Possible regressions * igt@i915_pm_dc@dc9-dpms: - shard-tglb: NOTRUN -> [SKIP][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21295/shard-tglb5/igt@i915_pm...@dc9-dpms.html Known issues Here are the changes found in Patchwork_21295_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][2] -> [TIMEOUT][3] ([i915#2369] / [i915#3063] / [i915#3648]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-tglb2/igt@gem_...@unwedge-stress.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21295/shard-tglb8/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-kbl: [PASS][4] -> [FAIL][5] ([i915#2842]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-kbl3/igt@gem_exec_fair@basic-none-...@rcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21295/shard-kbl2/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][6] -> [FAIL][7] ([i915#2842]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21295/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-iclb: NOTRUN -> [FAIL][8] ([i915#2842]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21295/shard-iclb7/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: NOTRUN -> [FAIL][9] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21295/shard-glk8/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#2190]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21295/shard-apl3/igt@gem_huc_c...@huc-copy.html * igt@gem_pwrite@basic-exhaustion: - shard-snb: NOTRUN -> [WARN][11] ([i915#2658]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21295/shard-snb5/igt@gem_pwr...@basic-exhaustion.html - shard-glk: NOTRUN -> [WARN][12] ([i915#2658]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21295/shard-glk8/igt@gem_pwr...@basic-exhaustion.html * igt@gem_pxp@reject-modify-context-protection-off-2: - shard-tglb: NOTRUN -> [SKIP][13] ([i915#4270]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21295/shard-tglb5/igt@gem_...@reject-modify-context-protection-off-2.html - shard-iclb: NOTRUN -> [SKIP][14] ([i915#4270]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21295/shard-iclb7/igt@gem_...@reject-modify-context-protection-off-2.html * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled: - shard-glk: NOTRUN -> [SKIP][15] ([fdo#109271]) +36 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21295/shard-glk8/igt@gem_render_c...@yf-tiled-mc-ccs-to-vebox-y-tiled.html * igt@gen9_exec_parse@batch-invalid-length: - shard-iclb: NOTRUN -> [SKIP][16] ([i915#2856]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21295/shard-iclb7/igt@gen9_exec_pa...@batch-invalid-length.html * igt@kms_big_fb@x-tiled-32bpp-rotate-180: - shard-glk: NOTRUN -> [DMESG-WARN][17] ([i915#118]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21295/shard-glk8/igt@kms_big...@x-tiled-32bpp-rotate-180.html * igt@kms_big_fb@x-tiled-64bpp-rotate-270: - shard-iclb: NOTRUN -> [SKIP][18] ([fdo#110725] / [fdo#111614]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21295/shard-iclb7/igt@kms_big...@x-tiled-64bpp-rotate-270.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip: - shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3777]) [19]:
Re: [Intel-gfx] [PATCH v3] drm/i915/gt: move remaining debugfs interfaces into gt
Hi Ville,
> > + if (IS_CHERRYVIEW(i915)) {
> > + seq_printf(m, "Master Interrupt Control:\t%08x\n",
> > + intel_uncore_read(uncore, GEN8_MASTER_IRQ));
> > +
> > + for (i = 0; i < 4; i++) {
> > + seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
> > + i, intel_uncore_read(uncore,
> > + GEN8_GT_IMR(i)));
> > + seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
> > + i, intel_uncore_read(uncore,
> > + GEN8_GT_IIR(i)));
> > + seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
> > + i, intel_uncore_read(uncore,
> > + GEN8_GT_IER(i)));
> > + }
> > +
>
> Why does chv get its own block? Looks identical to the bdw block.
[...]
> > + } else if (!HAS_PCH_SPLIT(i915)) {
>
> HAS_PCH_SPLIT in gt code looks a bit out of place.
>
> > + seq_printf(m, "Interrupt enable:%08x\n",
> > + intel_uncore_read(uncore, GEN2_IER));
> > + seq_printf(m, "Interrupt identity: %08x\n",
> > + intel_uncore_read(uncore, GEN2_IIR));
> > + seq_printf(m, "Interrupt mask: %08x\n",
> > + intel_uncore_read(uncore, GEN2_IMR));
>
> Technically on gen2 these are 16 bits, on gen3+ 32 bits. I don't
> quite remember now what happens when you read them as 32bit on gen2.
> Might be the msbs just come out all zeroes.
>
> > + } else {
> > + seq_printf(m, "Graphics Interrupt enable: %08x\n",
> > + intel_uncore_read(uncore, GTIER));
> > + seq_printf(m, "Graphics Interrupt identity: %08x\n",
> > + intel_uncore_read(uncore, GTIIR));
> > + seq_printf(m, "Graphics Interrupt mask: %08x\n",
> > + intel_uncore_read(uncore, GTIMR));
>
> Probably this should be before the previous block to keep things in
> order. Also missing GEN6_PM stuff for snb+, and the master interrupt
> stuff for ilk+.
[...]
thanks for your input. Actually I'm not even sure this part of
the patch is required anymore. It was originally a copy paste of
the parts of the 'i915_interrupt_info' functions in the
'i915_gem_interrupt' debugfs file.
This file was removed here by Chris:
cf977e18610e6 ("drm/i915/gem: Spring clean debugfs")
I have reproposed it in this patch seeking for comments because I
wanted to understand after all this time it might be needed or
not. If not I was going to remove it in my last version.
I haven't received any comments and therefore I am going to
remove it in v4.
Thank you,
Andi
[Intel-gfx] ✗ Fi.CI.BAT: failure for i915: Initial multi-tile support (rev2)
== Series Details ==
Series: i915: Initial multi-tile support (rev2)
URL : https://patchwork.freedesktop.org/series/95631/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21300
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_21300 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21300, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21300/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_21300:
### IGT changes ###
Possible regressions
* igt@runner@aborted:
- fi-snb-2600:NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21300/fi-snb-2600/igt@run...@aborted.html
- fi-ilk-650: NOTRUN -> [FAIL][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21300/fi-ilk-650/igt@run...@aborted.html
- fi-snb-2520m: NOTRUN -> [FAIL][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21300/fi-snb-2520m/igt@run...@aborted.html
- fi-bwr-2160:NOTRUN -> [FAIL][4]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21300/fi-bwr-2160/igt@run...@aborted.html
- fi-ivb-3770:NOTRUN -> [FAIL][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21300/fi-ivb-3770/igt@run...@aborted.html
- fi-elk-e7500: NOTRUN -> [FAIL][6]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21300/fi-elk-e7500/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_21300 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s0:
- fi-tgl-1115g4: [PASS][7] -> [FAIL][8] ([i915#1888])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21300/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-u2: NOTRUN -> [SKIP][9] ([i915#2190])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21300/fi-tgl-u2/igt@gem_huc_c...@huc-copy.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-tgl-u2: NOTRUN -> [SKIP][10] ([fdo#109284] / [fdo#111827]) +8
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21300/fi-tgl-u2/igt@kms_chamel...@dp-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-u2: NOTRUN -> [SKIP][11] ([i915#4103]) +1 similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21300/fi-tgl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-modeset@c-dp1:
- fi-cfl-8109u: [PASS][12] -> [FAIL][13] ([i915#4165])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-mode...@c-dp1.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21300/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-mode...@c-dp1.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-u2: NOTRUN -> [SKIP][14] ([fdo#109285])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21300/fi-tgl-u2/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][15] -> [DMESG-WARN][16] ([i915#4269])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21300/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
- fi-cfl-8109u: [PASS][17] -> [FAIL][18] ([i915#2546])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21300/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-u2: NOTRUN -> [SKIP][19] ([i915#3301])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21300/fi-tgl-u2/igt@prime_v...@basic-userptr.html
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][20] ([i915#2403])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21300/fi-pnv-d510/igt@run...@aborted.html
- fi-hsw-4770:NOTRUN -> [FAIL][21] ([i915#192] / [i915#193] /
[i915#194])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21300/fi-hsw-4770/igt@run...@aborted.html
Possible fixes
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a:
- {fi-tgl-dsi}: [DMESG-WARN][22] ([i915#1982]) ->
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Initial multi-tile support (rev2)
== Series Details ==
Series: i915: Initial multi-tile support (rev2)
URL : https://patchwork.freedesktop.org/series/95631/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2226b987792c drm/i915: rework some irq functions to take intel_gt as argument
-:17: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-authored-by:
#17:
Co-authored-by: Tvrtko Ursulin
total: 0 errors, 1 warnings, 0 checks, 75 lines checked
e0ff68ad5d2c drm/i915: split general MMIO setup from per-GT uncore init
bda304cedcf1 drm/i915: Restructure probe to handle multi-tile platforms
35a19ffd0117 drm/i915: Store backpointer to GT in uncore
ca609d95d12f drm/i915: Prepare for multiple gts
-:179: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#179: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:91:
+#define for_each_gt(i915__, id__, gt__) \
+ for ((id__) = 0; \
+(id__) < I915_MAX_TILES; \
+(id__)++) \
+ for_each_if (((gt__) = (i915__)->gts[(id__)]))
-:179: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id__' - possible
side-effects?
#179: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:91:
+#define for_each_gt(i915__, id__, gt__) \
+ for ((id__) = 0; \
+(id__) < I915_MAX_TILES; \
+(id__)++) \
+ for_each_if (((gt__) = (i915__)->gts[(id__)]))
-:183: WARNING:SPACING: space prohibited between function name and open
parenthesis '('
#183: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:95:
+ for_each_if (((gt__) = (i915__)->gts[(id__)]))
total: 1 errors, 1 warnings, 1 checks, 192 lines checked
e9cb525007df drm/i915: Initial support for per-tile uncore
2f61fef5cee6 drm/i915/xehp: Determine which tile raised an interrupt
d0ba3e4e7b13 drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware
6a3bf9cfb5b1 drm/i915/guc: Update CT debug macro for multi-tile
9d78e0b7d2fa drm/i915: Release per-gt resources allocated
7702b40e06c2 drm/i915/xehpsdv: Initialize multi-tiles
-:255: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#255: FILE: drivers/gpu/drm/i915/i915_pci.c:1012:
+#define XE_HP_SDV_ENGINES \
+ BIT(BCS0) | \
+ BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) | \
+ BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) | \
+ BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7)
total: 1 errors, 0 warnings, 0 checks, 284 lines checked
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Failsafe migration blits
== Series Details == Series: drm/i915: Failsafe migration blits URL : https://patchwork.freedesktop.org/series/95617/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10700_full -> Patchwork_21293_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21293_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21293_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21293_full: ### IGT changes ### Possible regressions * igt@gem_workarounds@reset: - shard-snb: NOTRUN -> [TIMEOUT][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21293/shard-snb2/igt@gem_workarou...@reset.html * igt@i915_pm_dc@dc9-dpms: - shard-tglb: NOTRUN -> [SKIP][2] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21293/shard-tglb3/igt@i915_pm...@dc9-dpms.html Known issues Here are the changes found in Patchwork_21293_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-apl: NOTRUN -> [DMESG-WARN][3] ([i915#180]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21293/shard-apl6/igt@gem_ctx_isolation@preservation...@rcs0.html * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-kbl: [PASS][4] -> [DMESG-WARN][5] ([i915#180]) +2 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-kbl6/igt@gem_ctx_isolation@preservation...@vcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21293/shard-kbl6/igt@gem_ctx_isolation@preservation...@vcs0.html * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21293/shard-snb7/igt@gem_ctx_persiste...@legacy-engines-queued.html * igt@gem_exec_fair@basic-deadline: - shard-apl: NOTRUN -> [FAIL][7] ([i915#2846]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21293/shard-apl3/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: NOTRUN -> [FAIL][8] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21293/shard-kbl1/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-apl: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-apl2/igt@gem_exec_fair@basic-n...@vcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21293/shard-apl3/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-kbl7/igt@gem_exec_fair@basic-n...@vecs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21293/shard-kbl7/igt@gem_exec_fair@basic-n...@vecs0.html - shard-apl: [PASS][13] -> [FAIL][14] ([i915#2842] / [i915#3468]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-apl2/igt@gem_exec_fair@basic-n...@vecs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21293/shard-apl3/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][15] -> [FAIL][16] ([i915#2842]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21293/shard-glk5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-iclb: NOTRUN -> [FAIL][17] ([i915#2842]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21293/shard-iclb8/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_flush@basic-uc-rw-default: - shard-skl: [PASS][18] -> [DMESG-WARN][19] ([i915#1982]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-skl2/igt@gem_exec_fl...@basic-uc-rw-default.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21293/shard-skl2/igt@gem_exec_fl...@basic-uc-rw-default.html * igt@gem_exec_whisper@basic-queues-priority: - shard-iclb: [PASS][20] -> [INCOMPLETE][21] ([i915#1895]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-iclb6/igt@gem_exec_whis...@basic-queues-priority.html [21]:
Re: [Intel-gfx] [PATCH v2] drm/i915/gt: move remaining debugfs interfaces into gt
On Fri, Oct 8, 2021 at 3:14 AM Andi Shyti wrote:
>
> Hi Lucas,
>
> > > I am reproposing this patch exactly as it was proposed initially
> > > where the original interfaces are kept where they have been
> > > originally placed. It might generate some duplicated code but,
> > > well, it's debugfs and I don't see any issue. In the future we
> > > can transform the upper interfaces to act upon all the GTs and
> > > provide information from all the GTs. This is, for example, how
> > > the sysfs interfaces will act.
> >
> > NACK. We've made this mistake in the past for other debugfs files.
> > We don't want to do it again just to maintain 2 separate places for
> > one year and then finally realize we want to merge them.
>
> In my opinion it's all about what mistake you like the most
> because until we will have multi-gt support in upstream all the
> patches come with the "promise" of a follow-up and maintenance
> cost.
no. If you put the implementation in a single place, later you only have the
decision on what to do with the per-device entrypoint:
- should we remove it once igt is converted?
- should we make it iterate all gts?
- should we make it mean root tile?
Then you take the action that is needed and decide it per interface.
Here you are leaving behind a lot of code that we will need to maintain
until there is support for such a thing.
It already happened once: we needed to maintain that duplicated code
for over a year with multiple patches changing them (or failing to do so).
>
> > > The reason I removed them in V1 is because igt as only user is
> > > not a strong reason to keep duplicated code, but as Chris
> > > suggested offline:
> > >
> > > "It's debugfs, igt is the primary consumer. CI has to be bridged over
> > > changes to the interfaces it is using in any case, as you want
> > > comparable results before/after the patches land.
> >
> > That doesn't mean you have to copy and paste it. It may mean you
> > do the implementation in one of them and the other calls that
> > implementation.
> > See how I did the deduplication in commit d0c560316d6f ("drm/i915:
> > deduplicate frequency dump on debugfs")
>
> In this case, from a user perspective, which gt is the interface
> affecting? is it affecting all the system? or gt 0, 1...? Does
> the user know? The maintenance cost is that later you will need
> to use for_each_gt and make all those interfaces multitile, and
> this would be your "promise".
multi-gt is irrelevant here. This patch without any "promise" should do
what the commit message says: *move*. The only reason to keep
the old entrypoint around is because it's missing the igt conversion. If
you are going to support a per-device entrypoint and do for_each_gt(),
or do a symlink to the root tile, or whatever, it isn't very relevant
to this patch.
Right now we have just a single directory, gt.
Lucas De Marchi
Re: [Intel-gfx] [PATCH 07/11] drm/i915/xehp: Determine which tile raised an interrupt
On Fri, Oct 08, 2021 at 02:56:31PM -0700, Matt Roper wrote:
> From: Paulo Zanoni
>
> The first step of interrupt handling is to read a tile0 register that
> tells us in which tile the interrupt happened; we can then we read the
> usual interrupt registers from the appropriate tile.
>
> Note that this is just the first step of handling interrupts properly on
> multi-tile platforms. Subsequent patches will convert other parts of
> the interrupt handling flow.
>
> Cc: Stuart Summers
> Signed-off-by: Paulo Zanoni
> Signed-off-by: Tvrtko Ursulin
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_irq.c | 31 ---
> 1 file changed, 16 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 038a9ec563c1..9f99ad56cde6 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2772,37 +2772,38 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> {
> struct drm_i915_private * const i915 = arg;
> struct intel_gt *gt = >gt;
> - void __iomem * const regs = gt->uncore->regs;
> + void __iomem * const t0_regs = gt->uncore->regs;
> u32 master_tile_ctl, master_ctl;
> - u32 gu_misc_iir;
> + u32 gu_misc_iir = 0;
> + unsigned int i;
>
> if (!intel_irqs_enabled(i915))
> return IRQ_NONE;
>
> - master_tile_ctl = dg1_master_intr_disable(regs);
> + master_tile_ctl = dg1_master_intr_disable(t0_regs);
> if (!master_tile_ctl) {
> - dg1_master_intr_enable(regs);
> + dg1_master_intr_enable(t0_regs);
> return IRQ_NONE;
> }
>
> - /* FIXME: we only support tile 0 for now. */
> - if (master_tile_ctl & DG1_MSTR_TILE(0)) {
> + for_each_gt(i915, i, gt) {
> + void __iomem *const regs = gt->uncore->regs;
> +
> + if ((master_tile_ctl & DG1_MSTR_TILE(i)) == 0)
> + continue;
> +
> master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
> raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl);
> - } else {
> - DRM_ERROR("Tile not supported: 0x%08x\n", master_tile_ctl);
> - dg1_master_intr_enable(regs);
> - return IRQ_NONE;
> - }
>
> - gen11_gt_irq_handler(gt, master_ctl);
> + gen11_gt_irq_handler(gt, master_ctl);
> +
> + gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
Hmm, I missed it before sending the series, but this doesn't look right.
We ack every tile's gu_misc_irq separately, but...
> + }
>
> if (master_ctl & GEN11_DISPLAY_IRQ)
> gen11_display_irq_handler(i915);
>
> - gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
> -
> - dg1_master_intr_enable(regs);
> + dg1_master_intr_enable(t0_regs);
>
> gen11_gu_misc_irq_handler(gt, gu_misc_iir);
...only handle the value from the final tile? Looks like this was
intended to move inside the loop as well.
Matt
>
> --
> 2.33.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
[Intel-gfx] ✗ Fi.CI.BAT: failure for dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion (rev3)
== Series Details ==
Series: dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after
conversion (rev3)
URL : https://patchwork.freedesktop.org/series/95605/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21299
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_21299 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21299, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21299/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_21299:
### IGT changes ###
Possible regressions
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21299/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
Known issues
Here are the changes found in Patchwork_21299 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21299/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [PASS][3] -> [FAIL][4] ([i915#1888])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21299/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-u2: NOTRUN -> [SKIP][5] ([i915#2190])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21299/fi-tgl-u2/igt@gem_huc_c...@huc-copy.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][6] -> [FAIL][7] ([i915#1372])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21299/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-tgl-u2: NOTRUN -> [SKIP][8] ([fdo#109284] / [fdo#111827]) +8
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21299/fi-tgl-u2/igt@kms_chamel...@dp-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-u2: NOTRUN -> [SKIP][9] ([i915#4103]) +1 similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21299/fi-tgl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-u2: NOTRUN -> [SKIP][10] ([fdo#109285])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21299/fi-tgl-u2/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][11] -> [DMESG-WARN][12] ([i915#4269])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21299/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-u2: NOTRUN -> [SKIP][13] ([i915#3301])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21299/fi-tgl-u2/igt@prime_v...@basic-userptr.html
* igt@runner@aborted:
- fi-tgl-u2: NOTRUN -> [FAIL][14] ([i915#1602] / [i915#2722])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21299/fi-tgl-u2/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[INCOMPLETE][15] ([i915#3921]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21299/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a:
- {fi-tgl-dsi}: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-tgl-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-a.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21299/fi-tgl-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]:
[Intel-gfx] [PATCH v2 11/11] drm/i915/xehpsdv: Initialize multi-tiles
From: Tvrtko Ursulin
Check how many extra GT tiles are available on the system and setup
register access for all of them. We can detect how may GT tiles are
available by reading a register on the root tile. The same register
returns the tile ID on all tiles.
v2:
- Include some additional refactor that didn't get squashed in properly
on v1.
Bspec: 33407
Original-author: Abdiel Janulgue
Signed-off-by: Tvrtko Ursulin
Cc: Matthew Auld
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Paulo Zanoni
Cc: Andi Shyti
Signed-off-by: Paulo Zanoni
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 83 +--
drivers/gpu/drm/i915/gt/intel_gt.h| 4 +-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
drivers/gpu/drm/i915/i915_drv.h | 7 +-
drivers/gpu/drm/i915/i915_pci.c | 40 +--
drivers/gpu/drm/i915/i915_reg.h | 4 ++
drivers/gpu/drm/i915/intel_device_info.h | 15
8 files changed, 145 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 2ae57e4656a3..1d9fcf9572ca 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -525,7 +525,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt
*gt)
u16 vdbox_mask;
u16 vebox_mask;
- info->engine_mask = INTEL_INFO(i915)->platform_engine_mask;
+ GEM_BUG_ON(!info->engine_mask);
if (GRAPHICS_VER(i915) < 11)
return info->engine_mask;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 6528d21e68eb..0879e30ace7c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -912,14 +912,17 @@ u32 intel_gt_read_register_fw(struct intel_gt *gt,
i915_reg_t reg)
return intel_uncore_read_fw(gt->uncore, reg);
}
-static int
-tile_setup(struct intel_gt *gt, unsigned int id, phys_addr_t phys_addr)
+int intel_tile_setup(struct intel_gt *gt, unsigned int id, phys_addr_t
phys_addr)
{
struct drm_i915_private *i915 = gt->i915;
struct intel_uncore *uncore;
struct intel_uncore_mmio_debug *mmio_debug;
int ret;
+ /* For Modern GENs size of GTTMMADR is 16MB (for each tile) */
+ if (GEM_WARN_ON(pci_resource_len(to_pci_dev(i915->drm.dev), 0) < (id +
1) * SZ_16M))
+ return -EINVAL;
+
if (id) {
uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
if (!uncore)
@@ -943,6 +946,16 @@ tile_setup(struct intel_gt *gt, unsigned int id,
phys_addr_t phys_addr)
if (ret)
return ret;
+ /* Which tile am I? default to zero on single tile systems */
+ if (HAS_REMOTE_TILES(i915)) {
+ u32 instance =
+ __raw_uncore_read32(gt->uncore, XEHPSDV_MTCFG_ADDR) &
+ TILE_NUMBER;
+
+ if (GEM_WARN_ON(instance != id))
+ return -ENXIO;
+ }
+
gt->phys_addr = phys_addr;
return 0;
@@ -958,25 +971,87 @@ static void tile_cleanup(struct intel_gt *gt)
}
}
+static unsigned int tile_count(struct drm_i915_private *i915)
+{
+ u32 mtcfg;
+
+ /*
+* We use raw MMIO reads at this point since the
+* MMIO vfuncs are not setup yet
+*/
+ mtcfg = __raw_uncore_read32(>uncore, XEHPSDV_MTCFG_ADDR);
+ return REG_FIELD_GET(TILE_COUNT, mtcfg) + 1;
+}
+
int intel_probe_gts(struct drm_i915_private *i915)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ const struct intel_gt_definition *gtdef;
+ struct intel_gt *gt;
phys_addr_t phys_addr;
unsigned int mmio_bar;
+ unsigned int i, tiles;
int ret;
mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
phys_addr = pci_resource_start(pdev, mmio_bar);
/* We always have at least one primary GT on any device */
- ret = tile_setup(>gt, 0, phys_addr);
+ gt = >gt;
+ gt->name = "Primary GT";
+ gt->info.engine_mask = INTEL_INFO(i915)->platform_engine_mask;
+
+ drm_dbg(>drm, "Setting up %s %u\n", gt->name, gt->info.id);
+ ret = intel_tile_setup(gt, 0, phys_addr);
if (ret)
return ret;
i915->gts[0] = >gt;
- /* TODO: add more tiles */
+ tiles = tile_count(i915);
+ drm_dbg(>drm, "Tile count: %u\n", tiles);
+
+ for (gtdef = INTEL_INFO(i915)->extra_gts, i = 1;
+gtdef && i < tiles;
+gtdef++, i++) {
+ if (GEM_WARN_ON(i >= I915_MAX_GTS)) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ gt = kzalloc(sizeof(*gt), GFP_KERNEL);
+ if (!gt) {
+ ret =
Re: [Intel-gfx] [PATCH 1/1] RFC : drm/i915: Adding new sysfs frequency attributes
On 10/8/2021 4:03 PM, Andi Shyti wrote: Hi Sujaritha, On Fri, Oct 08, 2021 at 01:44:54PM -0700, Sujaritha Sundaresan wrote: This patch adds the following new sysfs frequency attributes; - punit_req_freq_mhz - throttle_reason_status - throttle_reason_pl1 - throttle_reason_pl2 - throttle_reason_pl4 - throttle_reason_thermal - throttle_reason_prochot - throttle_reason_ratl - throttle_reason_vr_thermalert - throttle_reason_vr_tdc Signed-off-by: Sujaritha Sundaresan Cc: Dale B Stimson --- drivers/gpu/drm/i915/gt/intel_rps.c | 83 + drivers/gpu/drm/i915/gt/intel_rps.h | 10 +++ drivers/gpu/drm/i915/i915_reg.h | 11 +++ drivers/gpu/drm/i915/i915_sysfs.c | 135 if we add these here we're stuck forever! Can this hold a few days? The rest of the patch looks OK to me. Andi Hi Andi, Thanks for the quick review. I intended to wait for your patch, hence sent it out as an RFC patch :) So yes I should be able to hold it for a few days. Suja
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion (rev3)
== Series Details == Series: dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion (rev3) URL : https://patchwork.freedesktop.org/series/95605/ State : warning == Summary == $ dim checkpatch origin/drm-tip f35815098fd4 dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion -:16: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #16: <7> [187.536343] i915 :00:02.0: [drm:i915_gem_context_create_ioctl [i915]] HW context 1 created total: 0 errors, 1 warnings, 0 checks, 57 lines checked
Re: [Intel-gfx] [PATCH 1/1] RFC : drm/i915: Adding new sysfs frequency attributes
Hi Sujaritha, On Fri, Oct 08, 2021 at 01:44:54PM -0700, Sujaritha Sundaresan wrote: > This patch adds the following new sysfs frequency attributes; > - punit_req_freq_mhz > - throttle_reason_status > - throttle_reason_pl1 > - throttle_reason_pl2 > - throttle_reason_pl4 > - throttle_reason_thermal > - throttle_reason_prochot > - throttle_reason_ratl > - throttle_reason_vr_thermalert > - throttle_reason_vr_tdc > > Signed-off-by: Sujaritha Sundaresan > Cc: Dale B Stimson > --- > drivers/gpu/drm/i915/gt/intel_rps.c | 83 + > drivers/gpu/drm/i915/gt/intel_rps.h | 10 +++ > drivers/gpu/drm/i915/i915_reg.h | 11 +++ > drivers/gpu/drm/i915/i915_sysfs.c | 135 if we add these here we're stuck forever! Can this hold a few days? The rest of the patch looks OK to me. Andi
[Intel-gfx] ✓ Fi.CI.BAT: success for i915: Initial multi-tile support
== Series Details ==
Series: i915: Initial multi-tile support
URL : https://patchwork.freedesktop.org/series/95631/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21298
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/index.html
Known issues
Here are the changes found in Patchwork_21298 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@memory-alloc:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/fi-kbl-soraka/igt@amdgpu/amd_ba...@memory-alloc.html
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-u2: NOTRUN -> [SKIP][3] ([i915#2190])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/fi-tgl-u2/igt@gem_huc_c...@huc-copy.html
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][4] -> [INCOMPLETE][5] ([i915#2940])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-tgl-u2: NOTRUN -> [SKIP][6] ([fdo#109284] / [fdo#111827]) +8
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/fi-tgl-u2/igt@kms_chamel...@dp-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-u2: NOTRUN -> [SKIP][7] ([i915#4103]) +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/fi-tgl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-modeset@c-dp1:
- fi-cfl-8109u: [PASS][8] -> [FAIL][9] ([i915#4165])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-mode...@c-dp1.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-mode...@c-dp1.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-u2: NOTRUN -> [SKIP][10] ([fdo#109285])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/fi-tgl-u2/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u: [PASS][11] -> [FAIL][12] ([i915#2546])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-u2: NOTRUN -> [SKIP][13] ([i915#3301])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/fi-tgl-u2/igt@prime_v...@basic-userptr.html
* igt@runner@aborted:
- fi-bsw-nick:NOTRUN -> [FAIL][14] ([fdo#109271] / [i915#1436] /
[i915#3428])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/fi-bsw-nick/igt@run...@aborted.html
- fi-bdw-5557u: NOTRUN -> [FAIL][15] ([i915#1602] / [i915#2029])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/fi-bdw-5557u/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[INCOMPLETE][16] ([i915#3921]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a:
- {fi-tgl-dsi}: [DMESG-WARN][18] ([i915#1982]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-tgl-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-a.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21298/fi-tgl-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1982]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Initial multi-tile support
== Series Details ==
Series: i915: Initial multi-tile support
URL : https://patchwork.freedesktop.org/series/95631/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
21a66c454734 drm/i915: rework some irq functions to take intel_gt as argument
-:17: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-authored-by:
#17:
Co-authored-by: Tvrtko Ursulin
total: 0 errors, 1 warnings, 0 checks, 75 lines checked
7c75c8977d8b drm/i915: split general MMIO setup from per-GT uncore init
447d1a2a3ab0 drm/i915: Restructure probe to handle multi-tile platforms
d21c03706792 drm/i915: Store backpointer to GT in uncore
b22d545fdf95 drm/i915: Prepare for multiple gts
-:179: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#179: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:91:
+#define for_each_gt(i915__, id__, gt__) \
+ for ((id__) = 0; \
+(id__) < I915_MAX_TILES; \
+(id__)++) \
+ for_each_if (((gt__) = (i915__)->gts[(id__)]))
-:179: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id__' - possible
side-effects?
#179: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:91:
+#define for_each_gt(i915__, id__, gt__) \
+ for ((id__) = 0; \
+(id__) < I915_MAX_TILES; \
+(id__)++) \
+ for_each_if (((gt__) = (i915__)->gts[(id__)]))
-:183: WARNING:SPACING: space prohibited between function name and open
parenthesis '('
#183: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:95:
+ for_each_if (((gt__) = (i915__)->gts[(id__)]))
total: 1 errors, 1 warnings, 1 checks, 192 lines checked
b38b62d5cc6c drm/i915: Initial support for per-tile uncore
1b3ebba48401 drm/i915/xehp: Determine which tile raised an interrupt
72823afccad4 drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware
c0b1bf330072 drm/i915/guc: Update CT debug macro for multi-tile
1d9f14f403bd drm/i915: Release per-gt resources allocated
a0d4d7f898b5 drm/i915/xehpsdv: Initialize multi-tiles
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers (rev8)
== Series Details ==
Series: drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers
(rev8)
URL : https://patchwork.freedesktop.org/series/95127/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21296
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/index.html
Known issues
Here are the changes found in Patchwork_21296 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-gfx:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +5 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-u2: NOTRUN -> [SKIP][2] ([i915#2190])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/fi-tgl-u2/igt@gem_huc_c...@huc-copy.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-tgl-u2: NOTRUN -> [SKIP][3] ([fdo#109284] / [fdo#111827]) +8
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/fi-tgl-u2/igt@kms_chamel...@dp-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-u2: NOTRUN -> [SKIP][4] ([i915#4103]) +1 similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/fi-tgl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-u2: NOTRUN -> [SKIP][5] ([fdo#109285])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/fi-tgl-u2/igt@kms_force_connector_ba...@force-load-detect.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-u2: NOTRUN -> [SKIP][6] ([i915#3301])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/fi-tgl-u2/igt@prime_v...@basic-userptr.html
Possible fixes
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a:
- {fi-tgl-dsi}: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-tgl-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-a.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/fi-tgl-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
Participating hosts (40 -> 38)
--
Additional (1): fi-tgl-u2
Missing(3): fi-ilk-m540 fi-bsw-cyan fi-hsw-4200u
Build changes
-
* Linux: CI_DRM_10700 -> Patchwork_21296
CI-20190529: 20190529
CI_DRM_10700: 6ecdd5e29c83cd8fc191f8cce5c283eefb53c97e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6240: b232a092b9e1b10a8be13601acaa440903b226bc @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21296: fc1343912712b0b43bbc3a2440411d66f1761f32 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
fc1343912712 drm/i915: Clarify probing order in
intel_dp_aux_init_backlight_funcs()
ebba463275b1 drm/dp, drm/i915: Add support for VESA backlights using PWM for
brightness control
8bd79fe6f494 drm/dp: Disable unsupported features in
DP_EDP_BACKLIGHT_MODE_SET_REGISTER
aeb9e2e08ffa drm/nouveau/kms/nv50-: Explicitly check DPCD backlights for aux
enable/brightness
88ca1a838e62 drm/i915: Add support for panels with VESA backlights with PWM
enable/disable
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/index.html
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/1] RFC : drm/i915: Adding new sysfs frequency attributes
== Series Details ==
Series: series starting with [1/1] RFC : drm/i915: Adding new sysfs frequency
attributes
URL : https://patchwork.freedesktop.org/series/95629/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/i915_sysfs.o
drivers/gpu/drm/i915/i915_sysfs.c:559:32: error: ‘freq_attrs’ defined but not
used [-Werror=unused-variable]
static const struct attribute *freq_attrs[] = {
^~
cc1: all warnings being treated as errors
scripts/Makefile.build:277: recipe for target
'drivers/gpu/drm/i915/i915_sysfs.o' failed
make[4]: *** [drivers/gpu/drm/i915/i915_sysfs.o] Error 1
scripts/Makefile.build:540: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:540: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:540: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1868: recipe for target 'drivers' failed
make: *** [drivers] Error 2
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: move remaining debugfs interfaces into gt (rev10)
== Series Details == Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev10) URL : https://patchwork.freedesktop.org/series/75333/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10700_full -> Patchwork_21292_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21292_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21292_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21292_full: ### IGT changes ### Possible regressions * igt@i915_pm_dc@dc9-dpms: - shard-tglb: NOTRUN -> [SKIP][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-tglb2/igt@i915_pm...@dc9-dpms.html Known issues Here are the changes found in Patchwork_21292_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@engines-queued: - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-snb2/igt@gem_ctx_persiste...@engines-queued.html * igt@gem_ctx_persistence@many-contexts: - shard-tglb: [PASS][3] -> [FAIL][4] ([i915#2410]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-tglb6/igt@gem_ctx_persiste...@many-contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-tglb6/igt@gem_ctx_persiste...@many-contexts.html * igt@gem_eio@in-flight-contexts-immediate: - shard-tglb: [PASS][5] -> [TIMEOUT][6] ([i915#3063]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-tglb8/igt@gem_...@in-flight-contexts-immediate.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-tglb8/igt@gem_...@in-flight-contexts-immediate.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][7] -> [TIMEOUT][8] ([i915#2369] / [i915#3063] / [i915#3648]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-tglb2/igt@gem_...@unwedge-stress.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-tglb3/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-deadline: - shard-apl: NOTRUN -> [FAIL][9] ([i915#2846]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-apl3/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-tglb1/igt@gem_exec_fair@basic-none-sh...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-tglb1/igt@gem_exec_fair@basic-none-sh...@rcs0.html - shard-apl: [PASS][12] -> [SKIP][13] ([fdo#109271]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-apl8/igt@gem_exec_fair@basic-none-sh...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-apl2/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-apl: [PASS][14] -> [FAIL][15] ([i915#2842] / [i915#3468]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-apl2/igt@gem_exec_fair@basic-n...@vecs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-apl8/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-iclb: NOTRUN -> [FAIL][16] ([i915#2842]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-iclb7/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2190]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-apl2/igt@gem_huc_c...@huc-copy.html * igt@gem_pwrite@basic-exhaustion: - shard-snb: NOTRUN -> [WARN][18] ([i915#2658]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-snb5/igt@gem_pwr...@basic-exhaustion.html - shard-glk: NOTRUN -> [WARN][19] ([i915#2658]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-glk6/igt@gem_pwr...@basic-exhaustion.html * igt@gem_pxp@reject-modify-context-protection-off-2: - shard-iclb: NOTRUN -> [SKIP][20] ([i915#4270]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-iclb7/igt@gem_...@reject-modify-context-protection-off-2.html * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled: - shard-glk: NOTRUN -> [SKIP][21] ([fdo#109271]) +36 similar issues [21]:
[Intel-gfx] [PATCH 08/11] drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware
From: Paulo Zanoni
Loop through all the tiles when initializing and resetting interrupts.
Signed-off-by: Paulo Zanoni
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_irq.c | 28 ++--
1 file changed, 18 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9f99ad56cde6..e788e283d4a8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3190,14 +3190,19 @@ static void dg1_irq_reset(struct drm_i915_private
*dev_priv)
{
struct intel_gt *gt = _priv->gt;
struct intel_uncore *uncore = gt->uncore;
+ unsigned int i;
dg1_master_intr_disable(dev_priv->uncore.regs);
- gen11_gt_irq_reset(gt);
- gen11_display_irq_reset(dev_priv);
+ for_each_gt(dev_priv, i, gt) {
+ gen11_gt_irq_reset(gt);
- GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
- GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+ uncore = gt->uncore;
+ GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
+ GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+ }
+
+ gen11_display_irq_reset(dev_priv);
}
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
@@ -3890,13 +3895,16 @@ static void gen11_irq_postinstall(struct
drm_i915_private *dev_priv)
static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
{
- struct intel_gt *gt = _priv->gt;
- struct intel_uncore *uncore = gt->uncore;
+ struct intel_gt *gt;
u32 gu_misc_masked = GEN11_GU_MISC_GSE;
+ unsigned int i;
- gen11_gt_irq_postinstall(gt);
+ for_each_gt(dev_priv, i, gt) {
+ gen11_gt_irq_postinstall(gt);
- GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
+ GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_, ~gu_misc_masked,
+ gu_misc_masked);
+ }
if (HAS_DISPLAY(dev_priv)) {
icp_irq_postinstall(dev_priv);
@@ -3905,8 +3913,8 @@ static void dg1_irq_postinstall(struct drm_i915_private
*dev_priv)
GEN11_DISPLAY_IRQ_ENABLE);
}
- dg1_master_intr_enable(uncore->regs);
- intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
+ dg1_master_intr_enable(dev_priv->gt.uncore->regs);
+ intel_uncore_posting_read(dev_priv->gt.uncore, DG1_MSTR_TILE_INTR);
}
static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
--
2.33.0
[Intel-gfx] [PATCH 11/11] drm/i915/xehpsdv: Initialize multi-tiles
From: Tvrtko Ursulin
Check how many extra GT tiles are available on the system and setup
register access for all of them. We can detect how may GT tiles are
available by reading a register on the root tile. The same register
returns the tile ID on all tiles.
Bspec: 33407
Original-author: Abdiel Janulgue
Signed-off-by: Tvrtko Ursulin
Cc: Matthew Auld
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Paulo Zanoni
Signed-off-by: Paulo Zanoni
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/intel_gt.c | 66 +++-
drivers/gpu/drm/i915/i915_drv.h | 3 ++
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 4 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
5 files changed, 74 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 6528d21e68eb..d7efaef9ade7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -943,6 +943,17 @@ tile_setup(struct intel_gt *gt, unsigned int id,
phys_addr_t phys_addr)
if (ret)
return ret;
+ /* Which tile am I? default to zero on single tile systems */
+ if (HAS_REMOTE_TILES(i915)) {
+ u32 instance =
+ __raw_uncore_read32(gt->uncore, XEHPSDV_MTCFG_ADDR) &
+ TILE_NUMBER;
+
+ if (GEM_WARN_ON(instance != id))
+ return -ENXIO;
+ }
+
+ gt->info.id = id;
gt->phys_addr = phys_addr;
return 0;
@@ -958,11 +969,25 @@ static void tile_cleanup(struct intel_gt *gt)
}
}
+static unsigned int tile_count(struct drm_i915_private *i915)
+{
+ u32 mtcfg;
+
+ /*
+* We use raw MMIO reads at this point since the
+* MMIO vfuncs are not setup yet
+*/
+ mtcfg = __raw_uncore_read32(>uncore, XEHPSDV_MTCFG_ADDR);
+ return REG_FIELD_GET(TILE_COUNT, mtcfg) + 1;
+}
+
int intel_probe_gts(struct drm_i915_private *i915)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ struct intel_gt *gt;
phys_addr_t phys_addr;
unsigned int mmio_bar;
+ unsigned int i, tiles;
int ret;
mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
@@ -975,8 +1000,47 @@ int intel_probe_gts(struct drm_i915_private *i915)
i915->gts[0] = >gt;
- /* TODO: add more tiles */
+ if (!HAS_REMOTE_TILES(i915))
+ return 0;
+
+ /* Setup other tiles */
+ tiles = tile_count(i915);
+ drm_dbg(>drm, "Tile count: %u\n", tiles);
+
+ if (GEM_WARN_ON(tiles > I915_MAX_TILES))
+ return -EINVAL;
+
+ /* For multi-tile platforms, size of GTTMMADR is 16MB per tile */
+ if (GEM_WARN_ON(pci_resource_len(pdev, 0) / tiles != SZ_16M))
+ return -EINVAL;
+
+ for (i = 1; i < tiles; i++) {
+ gt = kzalloc(sizeof(*gt), GFP_KERNEL);
+ if (!gt) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ ret = tile_setup(gt, i, phys_addr + SZ_16M * i);
+ if (ret)
+ goto err;
+
+ i915->gts[i] = gt;
+ }
+
+ i915->remote_tiles = tiles - 1;
+
return 0;
+
+err:
+ drm_err(>drm, "Failed to initialize tile %u! (%d)\n", i, ret);
+
+ for_each_gt(i915, i, gt) {
+ tile_cleanup(gt);
+ i915->gts[i] = NULL;
+ }
+
+ return ret;
}
int intel_gt_tiles_init(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3a26a21ffb3a..342c42e5aa96 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -865,6 +865,8 @@ struct drm_i915_private {
*/
resource_size_t stolen_usable_size; /* Total size minus reserved
ranges */
+ unsigned int remote_tiles;
+
struct intel_uncore uncore;
struct intel_uncore_mmio_debug mmio_debug;
@@ -1724,6 +1726,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
+#define HAS_REMOTE_TILES(dev_priv) (INTEL_INFO(dev_priv)->has_remote_tiles)
#define HAS_GT_UC(dev_priv)(INTEL_INFO(dev_priv)->has_gt_uc)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 169837de395d..95870c2e366e 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1015,6 +1015,7 @@ static const struct intel_device_info xehpsdv_info = {
DGFX_FEATURES,
PLATFORM(INTEL_XEHPSDV),
.display = { },
+ .has_remote_tiles = 1,
.pipe_mask = 0,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
diff --git
[Intel-gfx] [PATCH 03/11] drm/i915: Restructure probe to handle multi-tile platforms
On a multi-tile platform, each tile has its own registers + GGTT space,
and BAR 0 is extended to cover all of them. Upcoming patches will start
exposing the tiles as multiple GTs within a single PCI device. In
preparation for supporting such setups, restructure the driver's probe
code a bit.
Only the primary/root tile is initialized for now; the other tiles will
be detected and plugged in by future patches once the necessary
infrastructure is in place to handle them.
Original-author: Abdiel Janulgue
Cc: Daniele Ceraolo Spurio
Cc: Matthew Auld
Cc: Joonas Lahtinen
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 45
drivers/gpu/drm/i915/gt/intel_gt.h | 3 ++
drivers/gpu/drm/i915/gt/intel_gt_pm.c| 9 -
drivers/gpu/drm/i915/gt/intel_gt_types.h | 5 +++
drivers/gpu/drm/i915/i915_drv.c | 20 +--
drivers/gpu/drm/i915/intel_uncore.c | 12 +++
drivers/gpu/drm/i915/intel_uncore.h | 3 +-
7 files changed, 76 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 1cb1948ac959..f4bea1f1de77 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -900,6 +900,51 @@ u32 intel_gt_read_register_fw(struct intel_gt *gt,
i915_reg_t reg)
return intel_uncore_read_fw(gt->uncore, reg);
}
+static int
+tile_setup(struct intel_gt *gt, unsigned int id, phys_addr_t phys_addr)
+{
+ int ret;
+
+ intel_uncore_init_early(gt->uncore, gt->i915);
+
+ ret = intel_uncore_setup_mmio(gt->uncore, phys_addr);
+ if (ret)
+ return ret;
+
+ gt->phys_addr = phys_addr;
+
+ return 0;
+}
+
+static void tile_cleanup(struct intel_gt *gt)
+{
+ intel_uncore_cleanup_mmio(gt->uncore);
+}
+
+int intel_probe_gts(struct drm_i915_private *i915)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ phys_addr_t phys_addr;
+ unsigned int mmio_bar;
+ int ret;
+
+ mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
+ phys_addr = pci_resource_start(pdev, mmio_bar);
+
+ /* We always have at least one primary GT on any device */
+ ret = tile_setup(>gt, 0, phys_addr);
+ if (ret)
+ return ret;
+
+ /* TODO: add more tiles */
+ return 0;
+}
+
+void intel_gts_release(struct drm_i915_private *i915)
+{
+ tile_cleanup(>gt);
+}
+
void intel_gt_info_print(const struct intel_gt_info *info,
struct drm_printer *p)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 74e771871a9b..f4f35a70cbe4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -85,6 +85,9 @@ static inline bool intel_gt_needs_read_steering(struct
intel_gt *gt,
u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg);
+int intel_probe_gts(struct drm_i915_private *i915);
+void intel_gts_release(struct drm_i915_private *i915);
+
void intel_gt_info_print(const struct intel_gt_info *info,
struct drm_printer *p);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 524eaf678790..76f498edb0d5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -126,7 +126,14 @@ static const struct intel_wakeref_ops wf_ops = {
void intel_gt_pm_init_early(struct intel_gt *gt)
{
- intel_wakeref_init(>wakeref, gt->uncore->rpm, _ops);
+ /*
+* We access the runtime_pm structure via gt->i915 here rather than
+* gt->uncore as we do elsewhere in the file because gt->uncore is not
+* yet initialized for all tiles at this point in the driver startup.
+* runtime_pm is per-device rather than per-tile, so this is still the
+* correct structure.
+*/
+ intel_wakeref_init(>wakeref, >i915->runtime_pm, _ops);
seqcount_mutex_init(>stats.lock, >wakeref.mutex);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 14216cc471b1..66143316d92e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -180,6 +180,11 @@ struct intel_gt {
const struct intel_mmio_range *steering_table[NUM_STEERING_TYPES];
+ /*
+* Base of per-tile GTTMMADR where we can derive the MMIO and the GGTT.
+*/
+ phys_addr_t phys_addr;
+
struct intel_gt_info {
intel_engine_mask_t engine_mask;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7f96d26c012a..51234fd1349b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -312,8 +312,8 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
[Intel-gfx] [PATCH 06/11] drm/i915: Initial support for per-tile uncore
From: Daniele Ceraolo Spurio
Initialization and suspend/resume is replicated per-tile.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++-
drivers/gpu/drm/i915/i915_drv.c | 61 ++---
3 files changed, 51 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 736725411f51..6528d21e68eb 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1008,6 +1008,7 @@ void intel_gts_release(struct drm_i915_private *i915)
void intel_gt_info_print(const struct intel_gt_info *info,
struct drm_printer *p)
{
+ drm_printf(p, "GT %u info:\n", info->id);
drm_printf(p, "available engines: %x\n", info->engine_mask);
intel_sseu_dump(>sseu, p);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index fdbd46ff59e0..34fefdfb6661 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -60,12 +60,15 @@ static int i915_capabilities(struct seq_file *m, void *data)
{
struct drm_i915_private *i915 = node_to_i915(m->private);
struct drm_printer p = drm_seq_file_printer(m);
+ struct intel_gt *gt;
+ unsigned int id;
seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915));
intel_device_info_print_static(INTEL_INFO(i915), );
intel_device_info_print_runtime(RUNTIME_INFO(i915), );
- intel_gt_info_print(>gt.info, );
+ for_each_gt(i915, id, gt)
+ intel_gt_info_print(>info, );
intel_driver_caps_print(>caps, );
kernel_param_lock(THIS_MODULE);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 44ccf0078ac4..36b6e6f2cebf 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -406,6 +406,8 @@ static void i915_driver_late_release(struct
drm_i915_private *dev_priv)
*/
static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
{
+ struct intel_gt *gt;
+ unsigned int i, j;
int ret;
if (i915_inject_probe_failure(dev_priv))
@@ -415,26 +417,35 @@ static int i915_driver_mmio_probe(struct drm_i915_private
*dev_priv)
if (ret < 0)
return ret;
- ret = intel_uncore_init_mmio(_priv->uncore);
- if (ret)
- return ret;
+ for_each_gt(dev_priv, i, gt) {
+ ret = intel_uncore_init_mmio(gt->uncore);
+ if (ret)
+ goto err_uncore;
+ }
/* Try to make sure MCHBAR is enabled before poking at it */
intel_setup_mchbar(dev_priv);
intel_device_info_runtime_init(dev_priv);
- ret = intel_gt_init_mmio(_priv->gt);
- if (ret)
- goto err_uncore;
+ for_each_gt(dev_priv, j, gt) {
+ ret = intel_gt_init_mmio(gt);
+ if (ret)
+ goto err_mchbar;
+ }
/* As early as possible, scrub existing GPU state before clobbering */
sanitize_gpu(dev_priv);
return 0;
-err_uncore:
+err_mchbar:
intel_teardown_mchbar(dev_priv);
- intel_uncore_fini_mmio(_priv->uncore);
+err_uncore:
+ for_each_gt(dev_priv, j, gt) {
+ if (j >= i)
+ break;
+ intel_uncore_fini_mmio(gt->uncore);
+ }
pci_dev_put(dev_priv->bridge_dev);
return ret;
@@ -446,8 +457,12 @@ static int i915_driver_mmio_probe(struct drm_i915_private
*dev_priv)
*/
static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
{
+ struct intel_gt *gt;
+ unsigned int i;
+
intel_teardown_mchbar(dev_priv);
- intel_uncore_fini_mmio(_priv->uncore);
+ for_each_gt(dev_priv, i, gt)
+ intel_uncore_fini_mmio(gt->uncore);
pci_dev_put(dev_priv->bridge_dev);
}
@@ -734,6 +749,8 @@ static void i915_welcome_messages(struct drm_i915_private
*dev_priv)
{
if (drm_debug_enabled(DRM_UT_DRIVER)) {
struct drm_printer p = drm_debug_printer("i915 device info:");
+ struct intel_gt *gt;
+ unsigned int id;
drm_printf(, "pciid=0x%04x rev=0x%02x platform=%s
(subplatform=0x%x) gen=%i\n",
INTEL_DEVID(dev_priv),
@@ -745,7 +762,8 @@ static void i915_welcome_messages(struct drm_i915_private
*dev_priv)
intel_device_info_print_static(INTEL_INFO(dev_priv), );
intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), );
- intel_gt_info_print(_priv->gt.info, );
+ for_each_gt(dev_priv, id, gt)
+ intel_gt_info_print(>info, );
}
if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
@@ -1167,13 +1185,16 @@
[Intel-gfx] [PATCH 07/11] drm/i915/xehp: Determine which tile raised an interrupt
From: Paulo Zanoni
The first step of interrupt handling is to read a tile0 register that
tells us in which tile the interrupt happened; we can then we read the
usual interrupt registers from the appropriate tile.
Note that this is just the first step of handling interrupts properly on
multi-tile platforms. Subsequent patches will convert other parts of
the interrupt handling flow.
Cc: Stuart Summers
Signed-off-by: Paulo Zanoni
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_irq.c | 31 ---
1 file changed, 16 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 038a9ec563c1..9f99ad56cde6 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2772,37 +2772,38 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
{
struct drm_i915_private * const i915 = arg;
struct intel_gt *gt = >gt;
- void __iomem * const regs = gt->uncore->regs;
+ void __iomem * const t0_regs = gt->uncore->regs;
u32 master_tile_ctl, master_ctl;
- u32 gu_misc_iir;
+ u32 gu_misc_iir = 0;
+ unsigned int i;
if (!intel_irqs_enabled(i915))
return IRQ_NONE;
- master_tile_ctl = dg1_master_intr_disable(regs);
+ master_tile_ctl = dg1_master_intr_disable(t0_regs);
if (!master_tile_ctl) {
- dg1_master_intr_enable(regs);
+ dg1_master_intr_enable(t0_regs);
return IRQ_NONE;
}
- /* FIXME: we only support tile 0 for now. */
- if (master_tile_ctl & DG1_MSTR_TILE(0)) {
+ for_each_gt(i915, i, gt) {
+ void __iomem *const regs = gt->uncore->regs;
+
+ if ((master_tile_ctl & DG1_MSTR_TILE(i)) == 0)
+ continue;
+
master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl);
- } else {
- DRM_ERROR("Tile not supported: 0x%08x\n", master_tile_ctl);
- dg1_master_intr_enable(regs);
- return IRQ_NONE;
- }
- gen11_gt_irq_handler(gt, master_ctl);
+ gen11_gt_irq_handler(gt, master_ctl);
+
+ gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
+ }
if (master_ctl & GEN11_DISPLAY_IRQ)
gen11_display_irq_handler(i915);
- gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
-
- dg1_master_intr_enable(regs);
+ dg1_master_intr_enable(t0_regs);
gen11_gu_misc_irq_handler(gt, gu_misc_iir);
--
2.33.0
[Intel-gfx] [PATCH 10/11] drm/i915: Release per-gt resources allocated
From: Venkata Sandeep Dhanalakota
Iterate for_each_gt during release to support multi-tile
devices.
Cc: Tvrtko Ursulin
Signed-off-by: Venkata Sandeep Dhanalakota
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_drv.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 36b6e6f2cebf..da574f422084 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -381,10 +381,14 @@ static int i915_driver_early_probe(struct
drm_i915_private *dev_priv)
*/
static void i915_driver_late_release(struct drm_i915_private *dev_priv)
{
+ struct intel_gt *gt;
+ unsigned int id;
+
intel_irq_fini(dev_priv);
intel_power_domains_cleanup(dev_priv);
i915_gem_cleanup_early(dev_priv);
- intel_gt_driver_late_release(_priv->gt);
+ for_each_gt(dev_priv, id, gt)
+ intel_gt_driver_late_release(gt);
intel_region_ttm_device_fini(dev_priv);
vlv_suspend_cleanup(dev_priv);
i915_workqueues_cleanup(dev_priv);
--
2.33.0
[Intel-gfx] [PATCH 01/11] drm/i915: rework some irq functions to take intel_gt as argument
From: Paulo Zanoni
We'll be adding multi-tile support soon; on multi-tile platforms
interrupts are per-tile and every tile has the full set of
interrupt registers.
In this commit we start passing intel_gt instead of dev_priv for the
functions that are related to Xe_HP irq handling. Right now we're still
passing tile 0 everywhere, but in later patches we'll start actually
passing the correct tile.
Signed-off-by: Paulo Zanoni
Co-authored-by: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_irq.c | 26 +++---
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 77680bca46ee..038a9ec563c1 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2772,7 +2772,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
{
struct drm_i915_private * const i915 = arg;
struct intel_gt *gt = >gt;
- void __iomem * const regs = i915->uncore.regs;
+ void __iomem * const regs = gt->uncore->regs;
u32 master_tile_ctl, master_ctl;
u32 gu_misc_iir;
@@ -3173,11 +3173,12 @@ static void gen11_display_irq_reset(struct
drm_i915_private *dev_priv)
static void gen11_irq_reset(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = _priv->uncore;
+ struct intel_gt *gt = _priv->gt;
+ struct intel_uncore *uncore = gt->uncore;
gen11_master_intr_disable(dev_priv->uncore.regs);
- gen11_gt_irq_reset(_priv->gt);
+ gen11_gt_irq_reset(gt);
gen11_display_irq_reset(dev_priv);
GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
@@ -3186,11 +3187,12 @@ static void gen11_irq_reset(struct drm_i915_private
*dev_priv)
static void dg1_irq_reset(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = _priv->uncore;
+ struct intel_gt *gt = _priv->gt;
+ struct intel_uncore *uncore = gt->uncore;
dg1_master_intr_disable(dev_priv->uncore.regs);
- gen11_gt_irq_reset(_priv->gt);
+ gen11_gt_irq_reset(gt);
gen11_display_irq_reset(dev_priv);
GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
@@ -3869,13 +3871,14 @@ static void gen11_de_irq_postinstall(struct
drm_i915_private *dev_priv)
static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = _priv->uncore;
+ struct intel_gt *gt = _priv->gt;
+ struct intel_uncore *uncore = gt->uncore;
u32 gu_misc_masked = GEN11_GU_MISC_GSE;
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
icp_irq_postinstall(dev_priv);
- gen11_gt_irq_postinstall(_priv->gt);
+ gen11_gt_irq_postinstall(gt);
gen11_de_irq_postinstall(dev_priv);
GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
@@ -3886,10 +3889,11 @@ static void gen11_irq_postinstall(struct
drm_i915_private *dev_priv)
static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = _priv->uncore;
+ struct intel_gt *gt = _priv->gt;
+ struct intel_uncore *uncore = gt->uncore;
u32 gu_misc_masked = GEN11_GU_MISC_GSE;
- gen11_gt_irq_postinstall(_priv->gt);
+ gen11_gt_irq_postinstall(gt);
GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
@@ -3900,8 +3904,8 @@ static void dg1_irq_postinstall(struct drm_i915_private
*dev_priv)
GEN11_DISPLAY_IRQ_ENABLE);
}
- dg1_master_intr_enable(dev_priv->uncore.regs);
- intel_uncore_posting_read(_priv->uncore, DG1_MSTR_TILE_INTR);
+ dg1_master_intr_enable(uncore->regs);
+ intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
}
static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
--
2.33.0
[Intel-gfx] [PATCH 04/11] drm/i915: Store backpointer to GT in uncore
From: Michał Winiarski
We now support a per-gt uncore, yet we're not able to infer which GT
we're operating upon. Let's store a backpointer for now.
Signed-off-by: Michał Winiarski
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 9 +
drivers/gpu/drm/i915/intel_uncore.h | 3 ++-
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 +--
drivers/gpu/drm/i915/selftests/mock_uncore.c | 2 +-
5 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index f4bea1f1de77..863039d56cba 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -905,7 +905,7 @@ tile_setup(struct intel_gt *gt, unsigned int id,
phys_addr_t phys_addr)
{
int ret;
- intel_uncore_init_early(gt->uncore, gt->i915);
+ intel_uncore_init_early(gt->uncore, gt);
ret = intel_uncore_setup_mmio(gt->uncore, phys_addr);
if (ret)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 8a0a0676d67a..2c449836f537 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2057,12 +2057,13 @@ void intel_uncore_cleanup_mmio(struct intel_uncore
*uncore)
}
void intel_uncore_init_early(struct intel_uncore *uncore,
-struct drm_i915_private *i915)
+struct intel_gt *gt)
{
spin_lock_init(>lock);
- uncore->i915 = i915;
- uncore->rpm = >runtime_pm;
- uncore->debug = >mmio_debug;
+ uncore->i915 = gt->i915;
+ uncore->gt = gt;
+ uncore->rpm = >i915->runtime_pm;
+ uncore->debug = >i915->mmio_debug;
}
static void uncore_raw_init(struct intel_uncore *uncore)
diff --git a/drivers/gpu/drm/i915/intel_uncore.h
b/drivers/gpu/drm/i915/intel_uncore.h
index 83a455aa8374..2989032b580b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -130,6 +130,7 @@ struct intel_uncore {
void __iomem *regs;
struct drm_i915_private *i915;
+ struct intel_gt *gt;
struct intel_runtime_pm *rpm;
spinlock_t lock; /** lock is also taken in irq contexts. */
@@ -218,7 +219,7 @@ u32 intel_uncore_read_with_mcr_steering(struct intel_uncore
*uncore,
void
intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug);
void intel_uncore_init_early(struct intel_uncore *uncore,
-struct drm_i915_private *i915);
+struct intel_gt *gt);
int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t
phys_addr);
int intel_uncore_init_mmio(struct intel_uncore *uncore);
void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 4f8180146888..bd21bb7d104e 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -175,10 +175,9 @@ struct drm_i915_private *mock_gem_device(void)
mkwrite_device_info(i915)->memory_regions = REGION_SMEM;
intel_memory_regions_hw_probe(i915);
- mock_uncore_init(>uncore, i915);
-
i915_gem_init__mm(i915);
intel_gt_init_early(>gt, i915);
+ mock_uncore_init(>uncore, i915);
atomic_inc(>gt.wakeref.count); /* disable; no hw support */
i915->gt.awake = -ENODEV;
diff --git a/drivers/gpu/drm/i915/selftests/mock_uncore.c
b/drivers/gpu/drm/i915/selftests/mock_uncore.c
index ca57e4008701..b3790ef137e4 100644
--- a/drivers/gpu/drm/i915/selftests/mock_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/mock_uncore.c
@@ -42,7 +42,7 @@ __nop_read(64)
void mock_uncore_init(struct intel_uncore *uncore,
struct drm_i915_private *i915)
{
- intel_uncore_init_early(uncore, i915);
+ intel_uncore_init_early(uncore, >gt);
ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, nop);
ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, nop);
--
2.33.0
[Intel-gfx] [PATCH 05/11] drm/i915: Prepare for multiple gts
From: Tvrtko Ursulin
Add some basic plumbing to support more than one dynamically allocated
struct intel_gt. Up to four gts are supported in i915->gts[], with slot
zero shadowing the existing i915->gt to enable source compatibility with
legacy driver paths. A for_each_gt macro is added to iterate over the
GTs and will be used by upcoming patches that convert various parts of
the driver to be multi-gt aware.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 74 --
drivers/gpu/drm/i915/gt/intel_gt.h | 8 ++-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +
drivers/gpu/drm/i915/i915_drv.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h| 6 ++
drivers/gpu/drm/i915/intel_memory_region.h | 3 +
6 files changed, 86 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 863039d56cba..736725411f51 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -23,10 +23,13 @@
#include "shmem_utils.h"
#include "pxp/intel_pxp.h"
-void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
+static void
+__intel_gt_init_early(struct intel_gt *gt,
+ struct intel_uncore *uncore,
+ struct drm_i915_private *i915)
{
gt->i915 = i915;
- gt->uncore = >uncore;
+ gt->uncore = uncore;
spin_lock_init(>irq_lock);
@@ -46,13 +49,18 @@ void intel_gt_init_early(struct intel_gt *gt, struct
drm_i915_private *i915)
intel_rps_init_early(>rps);
}
-int intel_gt_probe_lmem(struct intel_gt *gt)
+static int intel_gt_probe_lmem(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
+ unsigned int instance = gt->info.id;
struct intel_memory_region *mem;
int id;
int err;
+ id = INTEL_REGION_LMEM + instance;
+ if (drm_WARN_ON(>drm, id >= INTEL_REGION_STOLEN_SMEM))
+ return -ENODEV;
+
mem = intel_gt_setup_lmem(gt);
if (mem == ERR_PTR(-ENODEV))
mem = intel_gt_setup_fake_lmem(gt);
@@ -67,9 +75,8 @@ int intel_gt_probe_lmem(struct intel_gt *gt)
return err;
}
- id = INTEL_REGION_LMEM;
-
mem->id = id;
+ mem->instance = instance;
intel_memory_region_set_name(mem, "local%u", mem->instance);
@@ -80,6 +87,11 @@ int intel_gt_probe_lmem(struct intel_gt *gt)
return 0;
}
+void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
+{
+ __intel_gt_init_early(gt, >uncore, i915);
+}
+
void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt)
{
gt->ggtt = ggtt;
@@ -903,9 +915,29 @@ u32 intel_gt_read_register_fw(struct intel_gt *gt,
i915_reg_t reg)
static int
tile_setup(struct intel_gt *gt, unsigned int id, phys_addr_t phys_addr)
{
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore;
+ struct intel_uncore_mmio_debug *mmio_debug;
int ret;
- intel_uncore_init_early(gt->uncore, gt);
+ if (id) {
+ uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
+ if (!uncore)
+ return -ENOMEM;
+
+ mmio_debug = kzalloc(sizeof(*mmio_debug), GFP_KERNEL);
+ if (!mmio_debug) {
+ kfree(uncore);
+ return -ENOMEM;
+ }
+
+ __intel_gt_init_early(gt, uncore, i915);
+ } else {
+ uncore = >uncore;
+ mmio_debug = >mmio_debug;
+ }
+
+ intel_uncore_init_early(uncore, gt);
ret = intel_uncore_setup_mmio(gt->uncore, phys_addr);
if (ret)
@@ -919,6 +951,11 @@ tile_setup(struct intel_gt *gt, unsigned int id,
phys_addr_t phys_addr)
static void tile_cleanup(struct intel_gt *gt)
{
intel_uncore_cleanup_mmio(gt->uncore);
+
+ if (gt->info.id) {
+ kfree(gt->uncore);
+ kfree(gt);
+ }
}
int intel_probe_gts(struct drm_i915_private *i915)
@@ -936,13 +973,36 @@ int intel_probe_gts(struct drm_i915_private *i915)
if (ret)
return ret;
+ i915->gts[0] = >gt;
+
/* TODO: add more tiles */
return 0;
}
+int intel_gt_tiles_init(struct drm_i915_private *i915)
+{
+ struct intel_gt *gt;
+ unsigned int id;
+ int ret;
+
+ for_each_gt(i915, id, gt) {
+ ret = intel_gt_probe_lmem(gt);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
void intel_gts_release(struct drm_i915_private *i915)
{
- tile_cleanup(>gt);
+ struct intel_gt *gt;
+ unsigned int id;
+
+ for_each_gt(i915, id, gt) {
+ tile_cleanup(gt);
+ i915->gts[id] = NULL;
+ }
}
void intel_gt_info_print(const struct intel_gt_info
[Intel-gfx] [PATCH 02/11] drm/i915: split general MMIO setup from per-GT uncore init
From: Daniele Ceraolo Spurio
In coming patches we'll be doing the actual tile initialization between
these two uncore init phases.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_drv.c | 9 -
drivers/gpu/drm/i915/intel_uncore.c | 17 +++--
drivers/gpu/drm/i915/intel_uncore.h | 2 ++
3 files changed, 13 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c65c3742887a..7f96d26c012a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -415,10 +415,14 @@ static int i915_driver_mmio_probe(struct drm_i915_private
*dev_priv)
if (ret < 0)
return ret;
- ret = intel_uncore_init_mmio(_priv->uncore);
+ ret = intel_uncore_setup_mmio(_priv->uncore);
if (ret < 0)
goto err_bridge;
+ ret = intel_uncore_init_mmio(_priv->uncore);
+ if (ret)
+ goto err_mmio;
+
/* Try to make sure MCHBAR is enabled before poking at it */
intel_setup_mchbar(dev_priv);
intel_device_info_runtime_init(dev_priv);
@@ -435,6 +439,8 @@ static int i915_driver_mmio_probe(struct drm_i915_private
*dev_priv)
err_uncore:
intel_teardown_mchbar(dev_priv);
intel_uncore_fini_mmio(_priv->uncore);
+err_mmio:
+ intel_uncore_cleanup_mmio(_priv->uncore);
err_bridge:
pci_dev_put(dev_priv->bridge_dev);
@@ -449,6 +455,7 @@ static void i915_driver_mmio_release(struct
drm_i915_private *dev_priv)
{
intel_teardown_mchbar(dev_priv);
intel_uncore_fini_mmio(_priv->uncore);
+ intel_uncore_cleanup_mmio(_priv->uncore);
pci_dev_put(dev_priv->bridge_dev);
}
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index e072054adac5..a308e86c9d9f 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2020,7 +2020,7 @@ static int i915_pmic_bus_access_notifier(struct
notifier_block *nb,
return NOTIFY_OK;
}
-static int uncore_mmio_setup(struct intel_uncore *uncore)
+int intel_uncore_setup_mmio(struct intel_uncore *uncore)
{
struct drm_i915_private *i915 = uncore->i915;
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
@@ -2053,7 +2053,7 @@ static int uncore_mmio_setup(struct intel_uncore *uncore)
return 0;
}
-static void uncore_mmio_cleanup(struct intel_uncore *uncore)
+void intel_uncore_cleanup_mmio(struct intel_uncore *uncore)
{
struct pci_dev *pdev = to_pci_dev(uncore->i915->drm.dev);
@@ -2146,10 +2146,6 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore)
struct drm_i915_private *i915 = uncore->i915;
int ret;
- ret = uncore_mmio_setup(uncore);
- if (ret)
- return ret;
-
/*
* The boot firmware initializes local memory and assesses its health.
* If memory training fails, the punit will have been instructed to
@@ -2170,7 +2166,7 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore)
} else {
ret = uncore_forcewake_init(uncore);
if (ret)
- goto out_mmio_cleanup;
+ return ret;
}
/* make sure fw funcs are set if and only if we have fw*/
@@ -2192,11 +2188,6 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore)
drm_dbg(>drm, "unclaimed mmio detected on uncore init,
clearing\n");
return 0;
-
-out_mmio_cleanup:
- uncore_mmio_cleanup(uncore);
-
- return ret;
}
/*
@@ -2261,8 +2252,6 @@ void intel_uncore_fini_mmio(struct intel_uncore *uncore)
intel_uncore_fw_domains_fini(uncore);
iosf_mbi_punit_release();
}
-
- uncore_mmio_cleanup(uncore);
}
static const struct reg_whitelist {
diff --git a/drivers/gpu/drm/i915/intel_uncore.h
b/drivers/gpu/drm/i915/intel_uncore.h
index 3248e4e2c540..d1d17b04e29f 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -218,11 +218,13 @@ void
intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug);
void intel_uncore_init_early(struct intel_uncore *uncore,
struct drm_i915_private *i915);
+int intel_uncore_setup_mmio(struct intel_uncore *uncore);
int intel_uncore_init_mmio(struct intel_uncore *uncore);
void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
struct intel_gt *gt);
bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
+void intel_uncore_cleanup_mmio(struct intel_uncore *uncore);
void intel_uncore_fini_mmio(struct intel_uncore *uncore);
void intel_uncore_suspend(struct intel_uncore *uncore);
void intel_uncore_resume_early(struct intel_uncore *uncore);
--
2.33.0
[Intel-gfx] [PATCH 00/11] i915: Initial multi-tile support
Some of our upcoming platforms, including the Xe_HP SDV, support a "multi-tile" design. A multi-tile platform is effectively a platform with multiple GT instances and local memory regions, all behind a single PCI device. From an i915 perspective, this translates to multiple intel_gt structures per drm_i915_private. This series provides the initial refactoring to support multiple independent GTs per card, but further work (especially related to local memory) will be required to fully enable a multi-tile platform. Note that the presence of multiple GTs is largely transparent to userspace. A multi-tile platform will advertise a larger list of engines to userspace, but the concept of "tile" is not something userspace has to worry about directly. There will be some uapi implications later due to the devices having multiple local memory regions, but that aspect of multi-tile is not covered by this patch series and will show up in future work. Daniele Ceraolo Spurio (2): drm/i915: split general MMIO setup from per-GT uncore init drm/i915: Initial support for per-tile uncore Matt Roper (1): drm/i915: Restructure probe to handle multi-tile platforms Michal Wajdeczko (1): drm/i915/guc: Update CT debug macro for multi-tile Michał Winiarski (1): drm/i915: Store backpointer to GT in uncore Paulo Zanoni (3): drm/i915: rework some irq functions to take intel_gt as argument drm/i915/xehp: Determine which tile raised an interrupt drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware Tvrtko Ursulin (2): drm/i915: Prepare for multiple gts drm/i915/xehpsdv: Initialize multi-tiles Venkata Sandeep Dhanalakota (1): drm/i915: Release per-gt resources allocated drivers/gpu/drm/i915/gt/intel_gt.c| 180 +- drivers/gpu/drm/i915/gt/intel_gt.h| 11 +- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 9 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 + drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 +- drivers/gpu/drm/i915/i915_debugfs.c | 5 +- drivers/gpu/drm/i915/i915_drv.c | 80 ++-- drivers/gpu/drm/i915/i915_drv.h | 9 + drivers/gpu/drm/i915/i915_irq.c | 71 --- drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 4 + drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_memory_region.h| 3 + drivers/gpu/drm/i915/intel_uncore.c | 36 ++-- drivers/gpu/drm/i915/intel_uncore.h | 6 +- .../gpu/drm/i915/selftests/mock_gem_device.c | 3 +- drivers/gpu/drm/i915/selftests/mock_uncore.c | 2 +- 17 files changed, 345 insertions(+), 89 deletions(-) -- 2.33.0
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers (rev8)
== Series Details == Series: drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers (rev8) URL : https://patchwork.freedesktop.org/series/95127/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Fix read of memory frequency
== Series Details ==
Series: drm/i915/icl: Fix read of memory frequency
URL : https://patchwork.freedesktop.org/series/95627/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21295
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21295/index.html
Known issues
Here are the changes found in Patchwork_21295 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_flip@basic-flip-vs-modeset@c-dp1:
- fi-cfl-8109u: [PASS][1] -> [FAIL][2] ([i915#4165]) +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-mode...@c-dp1.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21295/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-mode...@c-dp1.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#4269])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21295/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [PASS][5] -> [DMESG-WARN][6] ([i915#295]) +18 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21295/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
Possible fixes
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a:
- {fi-tgl-dsi}: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-tgl-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-a.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21295/fi-tgl-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#4165]: https://gitlab.freedesktop.org/drm/intel/issues/4165
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
Participating hosts (40 -> 37)
--
Missing(3): fi-ilk-m540 fi-bsw-cyan fi-hsw-4200u
Build changes
-
* Linux: CI_DRM_10700 -> Patchwork_21295
CI-20190529: 20190529
CI_DRM_10700: 6ecdd5e29c83cd8fc191f8cce5c283eefb53c97e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6240: b232a092b9e1b10a8be13601acaa440903b226bc @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21295: fe3148c5e2cea9b6f99d1e034361122eedad8c45 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
fe3148c5e2ce drm/i915/icl: Fix read of memory frequency
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21295/index.html
Re: [Intel-gfx] [PATCH] drm/i915/icl: Fix read of memory frequency
On Fri, 2021-10-08 at 13:58 -0700, José Roberto de Souza wrote:
> All display 9 and display 10 platforms has only 4 bits for the memory
> frequency but display 11 platforms it changes to 8 bits.
>
> Display 9 platforms has another register in bits 7:4 that prevents us
> to have a single mask.
> Also adding new mask with the current name in CRWebViewer, not
> sure why current mask is named like this.
>
> Fixes: f8112cb9574b ("drm/i915/gen11+: Only load DRAM information from pcode")
Ops hash should be: 5d0c938ec9cc
Will fix in the next version or when applying.
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_dram.c | 7 +--
> 2 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a897f4abea0c3..041f7dc9e0d94 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11148,6 +11148,7 @@ enum skl_power_gate {
> #define SKL_MEMORY_FREQ_MULTIPLIER_HZ2
> #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU_MMIO(MCHBAR_MIRROR_BASE_SNB +
> 0x5E04)
> #define SKL_REQ_DATA_MASK (0xF << 0)
> +#define ICL_FREQ_MASK (0xFF << 0)
> #define DG1_GEAR_TYPE REG_BIT(16)
>
> #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN
> _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
> diff --git a/drivers/gpu/drm/i915/intel_dram.c
> b/drivers/gpu/drm/i915/intel_dram.c
> index 30a0cab5eff46..558589b1202d6 100644
> --- a/drivers/gpu/drm/i915/intel_dram.c
> +++ b/drivers/gpu/drm/i915/intel_dram.c
> @@ -257,8 +257,11 @@ skl_get_dram_info(struct drm_i915_private *i915)
>
> val = intel_uncore_read(>uncore,
> SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
> - mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
> - SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
> + if (DISPLAY_VER(i915) == 11)
> + val &= ICL_FREQ_MASK;
> + else
> + val &= SKL_REQ_DATA_MASK;
> + mem_freq_khz = DIV_ROUND_UP(val * SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
>
> if (dram_info->num_channels * mem_freq_khz == 0) {
> drm_info(>drm,
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm: cleanup: Use DRM_MODESET_LOCK_ALL_* helpers
On 21/10/07 11:58PM, Patchwork wrote: > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_21282_full: > > ### IGT changes ### > > Possible regressions > > * igt@kms_invalid_mode@clock-too-high: > - shard-tglb: NOTRUN -> [SKIP][1] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21282/shard-tglb8/igt@kms_invalid_m...@clock-too-high.html > Can someone more familiar with the tests have a look at this? Could it be related to my changes? Thanks.
Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: cleanup: Use DRM_MODESET_LOCK_ALL_* helpers
On 21/10/07 08:58PM, Patchwork wrote: > > 7bf784bb287c drm: cleanup: remove acquire_ctx from drm_mode_config > -:8: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate > one > > -:27: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s) > > total: 1 errors, 1 warnings, 0 checks, 16 lines checked > > Thanks, I somehow forgot to run checkpatch.pl on the latest commit. Fixing.
Re: [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm: cleanup: Use DRM_MODESET_LOCK_ALL_* helpers
On 21/10/07 09:01PM, Patchwork wrote: > == Series Details == > > Series: drm: cleanup: Use DRM_MODESET_LOCK_ALL_* helpers > URL : https://patchwork.freedesktop.org/series/95578/ > State : warning > > == Summary == > > $ dim sparse --fast origin/drm-tip > Sparse version: v0.6.2 > Fast mode used, each commit won't be checked separately. > -drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:28: > -drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:28: > -drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:28: > -drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:28: > -drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:28: > -drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:28: > -drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:28: > -drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:28: > + from drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:28: > + from drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:28: > + from drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:28: > + from drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:28: > + from drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:28: > + from drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:28: > + from drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:28: > + from drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:28: > - from > drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:28: > - from > drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:28: > - from > drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:28: > - from > drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:28: > + from > drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:30: > + from > drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:30: > + from > drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:30: > + from > drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:30: > > The output of this bot seems to be corrupted. Or am I missing something? I ran sparse against "amdgpu_display.c" before and after my changes and the outputs seem to be identical.
[Intel-gfx] [PATCH 1/1] RFC : drm/i915: Adding new sysfs frequency attributes
This patch adds the following new sysfs frequency attributes;
- punit_req_freq_mhz
- throttle_reason_status
- throttle_reason_pl1
- throttle_reason_pl2
- throttle_reason_pl4
- throttle_reason_thermal
- throttle_reason_prochot
- throttle_reason_ratl
- throttle_reason_vr_thermalert
- throttle_reason_vr_tdc
Signed-off-by: Sujaritha Sundaresan
Cc: Dale B Stimson
---
drivers/gpu/drm/i915/gt/intel_rps.c | 83 +
drivers/gpu/drm/i915/gt/intel_rps.h | 10 +++
drivers/gpu/drm/i915/i915_reg.h | 11 +++
drivers/gpu/drm/i915/i915_sysfs.c | 135
4 files changed, 239 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 172de6c9f949..c03d99f2608c 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2153,6 +2153,89 @@ u32 intel_rps_read_state_cap(struct intel_rps *rps)
return intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
}
+static u32 __rps_read_mmio(struct intel_gt *gt, i915_reg_t reg32)
+{
+ intel_wakeref_t wakeref;
+ u32 val;
+
+ with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+ val = intel_uncore_read(gt->uncore, reg32);
+
+ return val;
+}
+
+u32 intel_rps_read_throttle_reason_status(struct intel_rps *rps)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ u32 status = __rps_read_mmio(gt, GT0_PERF_LIMIT_REASONS) &
GT0_PERF_LIMIT_REASONS_MASK;
+
+ return status;
+}
+
+u32 intel_rps_read_throttle_reason_pl1(struct intel_rps *rps)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ u32 pl1 = __rps_read_mmio(gt, GT0_PERF_LIMIT_REASONS) &
POWER_LIMIT_1_MASK;
+
+ return pl1;
+}
+
+u32 intel_rps_read_throttle_reason_pl2(struct intel_rps *rps)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ u32 pl2 = __rps_read_mmio(gt, GT0_PERF_LIMIT_REASONS) &
POWER_LIMIT_2_MASK;
+
+ return pl2;
+}
+
+u32 intel_rps_read_throttle_reason_pl4(struct intel_rps *rps)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ u32 pl4 = __rps_read_mmio(gt, GT0_PERF_LIMIT_REASONS) &
POWER_LIMIT_4_MASK;
+
+ return pl4;
+}
+
+u32 intel_rps_read_throttle_reason_thermal(struct intel_rps *rps)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ u32 thermal = __rps_read_mmio(gt, GT0_PERF_LIMIT_REASONS) &
THERMAL_LIMIT_MASK;
+
+ return thermal;
+}
+
+u32 intel_rps_read_throttle_reason_prochot(struct intel_rps *rps)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ u32 prochot = __rps_read_mmio(gt, GT0_PERF_LIMIT_REASONS) &
PROCHOT_MASK;
+
+ return prochot;
+}
+
+u32 intel_rps_read_throttle_reason_ratl(struct intel_rps *rps)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ u32 ratl = __rps_read_mmio(gt, GT0_PERF_LIMIT_REASONS) & RATL_MASK;
+
+ return ratl;
+}
+
+u32 intel_rps_read_throttle_reason_vr_thermalert(struct intel_rps *rps)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ u32 thermalert = __rps_read_mmio(gt, GT0_PERF_LIMIT_REASONS) &
VR_THERMALERT_MASK;
+
+ return thermalert;
+}
+
+u32 intel_rps_read_throttle_reason_vr_tdc(struct intel_rps *rps)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ u32 tdc = __rps_read_mmio(gt, GT0_PERF_LIMIT_REASONS) & VR_TDC_MASK;
+
+ return tdc;
+}
+
/* External interface for intel_ips.ko */
static struct drm_i915_private __rcu *ips_mchdev;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h
b/drivers/gpu/drm/i915/gt/intel_rps.h
index 11960d64ca82..d6ac97f1facd 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -42,6 +42,16 @@ u32 intel_rps_get_rpn_frequency(struct intel_rps *rps);
u32 intel_rps_read_punit_req(struct intel_rps *rps);
u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps);
u32 intel_rps_read_state_cap(struct intel_rps *rps);
+u32 intel_rps_read_throttle_reason(struct intel_rps *rps);
+u32 intel_rps_read_throttle_reason_status(struct intel_rps *rps);
+u32 intel_rps_read_throttle_reason_pl1(struct intel_rps *rps);
+u32 intel_rps_read_throttle_reason_pl2(struct intel_rps *rps);
+u32 intel_rps_read_throttle_reason_pl4(struct intel_rps *rps);
+u32 intel_rps_read_throttle_reason_thermal(struct intel_rps *rps);
+u32 intel_rps_read_throttle_reason_prochot(struct intel_rps *rps);
+u32 intel_rps_read_throttle_reason_ratl(struct intel_rps *rps);
+u32 intel_rps_read_throttle_reason_vr_thermalert(struct intel_rps *rps);
+u32 intel_rps_read_throttle_reason_vr_tdc(struct intel_rps *rps);
void gen5_rps_irq_handler(struct intel_rps *rps);
void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a897f4abea0c..9ac322269d49 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4152,6 +4152,17 @@ static inline bool
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: Fix read of memory frequency
== Series Details ==
Series: drm/i915/icl: Fix read of memory frequency
URL : https://patchwork.freedesktop.org/series/95627/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fe3148c5e2ce drm/i915/icl: Fix read of memory frequency
-:17: WARNING:UNKNOWN_COMMIT_ID: Unknown commit id 'f8112cb9574b', maybe
rebased or not pulled?
#17:
Fixes: f8112cb9574b ("drm/i915/gen11+: Only load DRAM information from pcode")
total: 0 errors, 1 warnings, 0 checks, 20 lines checked
Re: [Intel-gfx] [PATCH v3 20/20] drm: cleanup: remove acquire_ctx from drm_mode_config
On 21/10/07 09:37PM, Fernando Ramos wrote: > --- > include/drm/drm_mode_config.h | 10 -- > 1 file changed, 10 deletions(-) > > diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h > index 48b7de80daf5..b214b07157f2 100644 > This patch was missing the commit description and signed-off-by line. I'll fix that for the next revision (v4) together with the rest of issues that might come up.
[Intel-gfx] [PATCH] drm/i915/icl: Fix read of memory frequency
All display 9 and display 10 platforms has only 4 bits for the memory
frequency but display 11 platforms it changes to 8 bits.
Display 9 platforms has another register in bits 7:4 that prevents us
to have a single mask.
Also adding new mask with the current name in CRWebViewer, not
sure why current mask is named like this.
Fixes: f8112cb9574b ("drm/i915/gen11+: Only load DRAM information from pcode")
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_dram.c | 7 +--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a897f4abea0c3..041f7dc9e0d94 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11148,6 +11148,7 @@ enum skl_power_gate {
#define SKL_MEMORY_FREQ_MULTIPLIER_HZ 2
#define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB +
0x5E04)
#define SKL_REQ_DATA_MASK (0xF << 0)
+#define ICL_FREQ_MASK (0xFF << 0)
#define DG1_GEAR_TYPE REG_BIT(16)
#define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB
+ 0x5000)
diff --git a/drivers/gpu/drm/i915/intel_dram.c
b/drivers/gpu/drm/i915/intel_dram.c
index 30a0cab5eff46..558589b1202d6 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -257,8 +257,11 @@ skl_get_dram_info(struct drm_i915_private *i915)
val = intel_uncore_read(>uncore,
SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
- mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
- SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
+ if (DISPLAY_VER(i915) == 11)
+ val &= ICL_FREQ_MASK;
+ else
+ val &= SKL_REQ_DATA_MASK;
+ mem_freq_khz = DIV_ROUND_UP(val * SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
if (dram_info->num_channels * mem_freq_khz == 0) {
drm_info(>drm,
--
2.33.0
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/5] dri: cleanup debugfs error handling
== Series Details == Series: series starting with [1/5] dri: cleanup debugfs error handling URL : https://patchwork.freedesktop.org/series/95602/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10699_full -> Patchwork_21290_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21290_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21290_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21290_full: ### IGT changes ### Possible regressions * igt@i915_pm_dc@dc9-dpms: - shard-tglb: NOTRUN -> [SKIP][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21290/shard-tglb2/igt@i915_pm...@dc9-dpms.html * igt@i915_suspend@debugfs-reader: - shard-kbl: [PASS][2] -> [INCOMPLETE][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10699/shard-kbl2/igt@i915_susp...@debugfs-reader.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21290/shard-kbl3/igt@i915_susp...@debugfs-reader.html Known issues Here are the changes found in Patchwork_21290_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-apl: NOTRUN -> [DMESG-WARN][4] ([i915#3002]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21290/shard-apl1/igt@gem_cre...@create-massive.html * igt@gem_ctx_persistence@legacy-engines-mixed-process: - shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +5 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21290/shard-snb5/igt@gem_ctx_persiste...@legacy-engines-mixed-process.html * igt@gem_eio@unwedge-stress: - shard-snb: NOTRUN -> [FAIL][6] ([i915#3354]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21290/shard-snb5/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-none@rcs0: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10699/shard-glk5/igt@gem_exec_fair@basic-n...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21290/shard-glk8/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10699/shard-kbl4/igt@gem_exec_fair@basic-n...@vcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21290/shard-kbl7/igt@gem_exec_fair@basic-n...@vcs0.html - shard-apl: NOTRUN -> [FAIL][11] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21290/shard-apl1/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10699/shard-tglb3/igt@gem_exec_fair@basic-p...@bcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21290/shard-tglb1/igt@gem_exec_fair@basic-p...@bcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2849]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10699/shard-iclb7/igt@gem_exec_fair@basic-throt...@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21290/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_whisper@basic-queues-priority: - shard-glk: [PASS][16] -> [DMESG-WARN][17] ([i915#118]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10699/shard-glk6/igt@gem_exec_whis...@basic-queues-priority.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21290/shard-glk9/igt@gem_exec_whis...@basic-queues-priority.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#2190]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21290/shard-apl7/igt@gem_huc_c...@huc-copy.html * igt@gem_pread@exhaustion: - shard-apl: NOTRUN -> [WARN][19] ([i915#2658]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21290/shard-apl2/igt@gem_pr...@exhaustion.html * igt@gem_pwrite@basic-exhaustion: - shard-kbl: NOTRUN -> [WARN][20] ([i915#2658]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21290/shard-kbl4/igt@gem_pwr...@basic-exhaustion.html * igt@gem_userptr_blits@dmabuf-sync: - shard-apl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#3323]) [21]:
Re: [Intel-gfx] [PATCH 07/26] drm/i915/guc: Introduce context parent-child relationship
On Thu, Oct 07, 2021 at 12:35:08PM -0700, John Harrison wrote:
> On 10/4/2021 15:06, Matthew Brost wrote:
> > Introduce context parent-child relationship. Once this relationship is
> > created all pinning / unpinning operations are directed to the parent
> > context. The parent context is responsible for pinning all of its'
> No need for an apostrophe.
>
Fixed.
> > children and itself.
> >
> > This is a precursor to the full GuC multi-lrc implementation but aligns
> > to how GuC mutli-lrc interface is defined - a single H2G is used
> > register / deregister all of the contexts simultaneously.
> >
> > Subsequent patches in the series will implement the pinning / unpinning
> > operations for parent / child contexts.
> >
> > v2:
> > (Daniel Vetter)
> >- Add kernel doc, add wrapper to access parent to ensure safety
> > v3:
> > (John Harrison)
> >- Fix comment explaing GEM_BUG_ON in to_parent()
> >- Make variable names generic (non-GuC specific)
> >
> > Signed-off-by: Matthew Brost
> > ---
> > drivers/gpu/drm/i915/gt/intel_context.c | 29 +
> > drivers/gpu/drm/i915/gt/intel_context.h | 41 +++
> > drivers/gpu/drm/i915/gt/intel_context_types.h | 21 ++
> > 3 files changed, 91 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
> > b/drivers/gpu/drm/i915/gt/intel_context.c
> > index f601323b939f..c5bb7ccfb3f8 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> > @@ -403,6 +403,8 @@ intel_context_init(struct intel_context *ce, struct
> > intel_engine_cs *engine)
> > INIT_LIST_HEAD(>destroyed_link);
> > + INIT_LIST_HEAD(>parallel.child_list);
> > +
> > /*
> > * Initialize fence to be complete as this is expected to be complete
> > * unless there is a pending schedule disable outstanding.
> > @@ -417,10 +419,17 @@ intel_context_init(struct intel_context *ce, struct
> > intel_engine_cs *engine)
> > void intel_context_fini(struct intel_context *ce)
> > {
> > + struct intel_context *child, *next;
> > +
> > if (ce->timeline)
> > intel_timeline_put(ce->timeline);
> > i915_vm_put(ce->vm);
> > + /* Need to put the creation ref for the children */
> > + if (intel_context_is_parent(ce))
> > + for_each_child_safe(ce, child, next)
> > + intel_context_put(child);
> > +
> > mutex_destroy(>pin_mutex);
> > i915_active_fini(>active);
> > i915_sw_fence_fini(>guc_state.blocked);
> > @@ -537,6 +546,26 @@ struct i915_request
> > *intel_context_find_active_request(struct intel_context *ce)
> > return active;
> > }
> > +void intel_context_bind_parent_child(struct intel_context *parent,
> > +struct intel_context *child)
> > +{
> > + /*
> > +* Callers responsibility to validate that this function is used
> > +* correctly but we use GEM_BUG_ON here ensure that they do.
> > +*/
> > + GEM_BUG_ON(!intel_engine_uses_guc(parent->engine));
> > + GEM_BUG_ON(intel_context_is_pinned(parent));
> > + GEM_BUG_ON(intel_context_is_child(parent));
> > + GEM_BUG_ON(intel_context_is_pinned(child));
> > + GEM_BUG_ON(intel_context_is_child(child));
> > + GEM_BUG_ON(intel_context_is_parent(child));
> > +
> > + parent->parallel.number_children++;
> > + list_add_tail(>parallel.child_link,
> > + >parallel.child_list);
> > + child->parallel.parent = parent;
> > +}
> > +
> > #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> > #include "selftest_context.c"
> > #endif
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
> > b/drivers/gpu/drm/i915/gt/intel_context.h
> > index c41098950746..b63c10a144af 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_context.h
> > @@ -44,6 +44,47 @@ void intel_context_free(struct intel_context *ce);
> > int intel_context_reconfigure_sseu(struct intel_context *ce,
> >const struct intel_sseu sseu);
> > +static inline bool intel_context_is_child(struct intel_context *ce)
> > +{
> > + return !!ce->parallel.parent;
> > +}
> > +
> > +static inline bool intel_context_is_parent(struct intel_context *ce)
> > +{
> > + return !!ce->parallel.number_children;
> > +}
> > +
> > +static inline bool intel_context_is_pinned(struct intel_context *ce);
> > +
> > +static inline struct intel_context *
> > +intel_context_to_parent(struct intel_context *ce)
> > +{
> > + if (intel_context_is_child(ce)) {
> > + /*
> > +* The parent holds ref count to the child so it is always safe
> > +* for the parent to access the child, but the child has a
> > +* pointer to the parent without a ref. To ensure this is safe
> > +* the child should only access the parent pointer while the
> > +* parent is pinned.
> > +*/
> > +
Re: [Intel-gfx] [PATCH 02/26] drm/i915/guc: Take GT PM ref when deregistering context
On Wed, Oct 06, 2021 at 08:37:03PM -0700, John Harrison wrote:
> On 10/4/2021 15:06, Matthew Brost wrote:
> > Taking a PM reference to prevent intel_gt_wait_for_idle from short
> > circuiting while a deregister context H2G is in flight. To do this must
> > issue the deregister H2G from a worker as context can be destroyed from
> > an atomic context and taking GT PM ref blows up. Previously we took a
> > runtime PM from this atomic context which worked but will stop working
> > once runtime pm autosuspend in enabled.
> >
> > So this patch is two fold, stop intel_gt_wait_for_idle from short
> > circuting and fix runtime pm autosuspend.
> >
> > v2:
> > (John Harrison)
> >- Split structure changes out in different patch
> > (Tvrtko)
> >- Don't drop lock in deregister_destroyed_contexts
> >
> > Signed-off-by: Matthew Brost
> > ---
> > drivers/gpu/drm/i915/gt/intel_context.c | 2 +
> > drivers/gpu/drm/i915/gt/intel_context_types.h | 7 +
> > drivers/gpu/drm/i915/gt/intel_engine_pm.h | 5 +
> > drivers/gpu/drm/i915/gt/intel_gt_pm.h | 4 +
> > drivers/gpu/drm/i915/gt/uc/intel_guc.h| 11 ++
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 146 +++---
> > 6 files changed, 121 insertions(+), 54 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
> > b/drivers/gpu/drm/i915/gt/intel_context.c
> > index e9a0cad5c34d..1076066f41e0 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> > @@ -399,6 +399,8 @@ intel_context_init(struct intel_context *ce, struct
> > intel_engine_cs *engine)
> > ce->guc_id.id = GUC_INVALID_LRC_ID;
> > INIT_LIST_HEAD(>guc_id.link);
> > + INIT_LIST_HEAD(>destroyed_link);
> > +
> > /*
> > * Initialize fence to be complete as this is expected to be complete
> > * unless there is a pending schedule disable outstanding.
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > b/drivers/gpu/drm/i915/gt/intel_context_types.h
> > index e7e3984aab78..4613d027cbc3 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
> > @@ -213,6 +213,13 @@ struct intel_context {
> > struct list_head link;
> > } guc_id;
> > + /**
> > +* @destroyed_link: link in guc->submission_state.destroyed_contexts, in
> > +* list when context is pending to be destroyed (deregistered with the
> > +* GuC), protected by guc->submission_state.lock
> > +*/
> > + struct list_head destroyed_link;
> > +
> > #ifdef CONFIG_DRM_I915_SELFTEST
> > /**
> > * @drop_schedule_enable: Force drop of schedule enable G2H for selftest
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.h
> > b/drivers/gpu/drm/i915/gt/intel_engine_pm.h
> > index 8520c595f5e1..6fdeae668e6e 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.h
> > @@ -16,6 +16,11 @@ intel_engine_pm_is_awake(const struct intel_engine_cs
> > *engine)
> > return intel_wakeref_is_active(>wakeref);
> > }
> > +static inline void __intel_engine_pm_get(struct intel_engine_cs *engine)
> > +{
> > + __intel_wakeref_get(>wakeref);
> > +}
> > +
> > static inline void intel_engine_pm_get(struct intel_engine_cs *engine)
> > {
> > intel_wakeref_get(>wakeref);
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
> > b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
> > index d0588d8aaa44..05de6c1af25b 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
> > @@ -41,6 +41,10 @@ static inline void intel_gt_pm_put_async(struct intel_gt
> > *gt)
> > intel_wakeref_put_async(>wakeref);
> > }
> > +#define with_intel_gt_pm(gt, tmp) \
> > + for (tmp = 1, intel_gt_pm_get(gt); tmp; \
> > +intel_gt_pm_put(gt), tmp = 0)
> > +
> > static inline int intel_gt_pm_wait_for_idle(struct intel_gt *gt)
> > {
> > return intel_wakeref_wait_for_idle(>wakeref);
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > index 65b5e8eeef96..25a598e2b6e8 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > @@ -84,6 +84,17 @@ struct intel_guc {
> > * refs
> > */
> > struct list_head guc_id_list;
> > + /**
> > +* @destroyed_contexts: list of contexts waiting to be destroyed
> > +* (deregistered with the GuC)
> > +*/
> > + struct list_head destroyed_contexts;
> > + /**
> > +* @destroyed_worker: worker to deregister contexts, need as we
> > +* need to take a GT PM reference and can't from destroy
> > +* function as it might be in an atomic context (no sleeping)
> > +*/
> > + struct work_struct destroyed_worker;
> > } submission_state;
>
Re: [Intel-gfx] [PATCH v2 1/7] drm/sysfs: introduce drm_sysfs_connector_hotplug_event
Ping
[Intel-gfx] ✗ Fi.CI.BAT: failure for dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion (rev2)
== Series Details ==
Series: dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after
conversion (rev2)
URL : https://patchwork.freedesktop.org/series/95605/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21294
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_21294 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21294, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21294/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_21294:
### IGT changes ###
Possible regressions
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21294/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
Known issues
Here are the changes found in Patchwork_21294 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-gfx:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271]) +15 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21294/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-u2: NOTRUN -> [SKIP][3] ([i915#2190])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21294/fi-tgl-u2/igt@gem_huc_c...@huc-copy.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-cfl-guc: [PASS][4] -> [DMESG-FAIL][5] ([i915#541])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-cfl-guc/igt@i915_selftest@live@gt_heartbeat.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21294/fi-cfl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-tgl-u2: NOTRUN -> [SKIP][6] ([fdo#109284] / [fdo#111827]) +8
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21294/fi-tgl-u2/igt@kms_chamel...@dp-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-u2: NOTRUN -> [SKIP][7] ([i915#4103]) +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21294/fi-tgl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-u2: NOTRUN -> [SKIP][8] ([fdo#109285])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21294/fi-tgl-u2/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#4269])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21294/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-u2: NOTRUN -> [SKIP][11] ([i915#3301])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21294/fi-tgl-u2/igt@prime_v...@basic-userptr.html
* igt@runner@aborted:
- fi-tgl-u2: NOTRUN -> [FAIL][12] ([i915#1602] / [i915#2722])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21294/fi-tgl-u2/igt@run...@aborted.html
Possible fixes
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a:
- {fi-tgl-dsi}: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-tgl-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-a.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21294/fi-tgl-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts
Re: [Intel-gfx] [PATCH 14/26] drm/i915/guc: Implement multi-lrc reset
On Fri, Oct 08, 2021 at 10:39:35AM -0700, John Harrison wrote:
> On 10/4/2021 15:06, Matthew Brost wrote:
> > Update context and full GPU reset to work with multi-lrc. The idea is
> > parent context tracks all the active requests inflight for itself and
> > its' children. The parent context owns the reset replaying / canceling
> Still its' should be its.
>
Yea. Will fix.
> > requests as needed.
> >
> > v2:
> > (John Harrison)
> >- Simply loop in find active request
> >- Add comments to find ative request / reset loop
> >
> > Signed-off-by: Matthew Brost
> > ---
> > drivers/gpu/drm/i915/gt/intel_context.c | 15 +++-
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 69 ++-
> > 2 files changed, 63 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
> > b/drivers/gpu/drm/i915/gt/intel_context.c
> > index c5bb7ccfb3f8..3b340eb59ada 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> > @@ -528,20 +528,29 @@ struct i915_request
> > *intel_context_create_request(struct intel_context *ce)
> > struct i915_request *intel_context_find_active_request(struct
> > intel_context *ce)
> > {
> > + struct intel_context *parent = intel_context_to_parent(ce);
> > struct i915_request *rq, *active = NULL;
> > unsigned long flags;
> > GEM_BUG_ON(!intel_engine_uses_guc(ce->engine));
> > - spin_lock_irqsave(>guc_state.lock, flags);
> > - list_for_each_entry_reverse(rq, >guc_state.requests,
> > + /*
> > +* We search the parent list to find an active request on the submitted
> > +* context. The parent list contains the requests for all the contexts
> > +* in the relationship so we have to do a compare of each request's
> > +* context must be done.
> "have to do ... must be done" - no need for both.
>
Right, will fix.
> > +*/
> > + spin_lock_irqsave(>guc_state.lock, flags);
> > + list_for_each_entry_reverse(rq, >guc_state.requests,
> > sched.link) {
> > + if (rq->context != ce)
> > + continue;
> > if (i915_request_completed(rq))
> > break;
> > active = rq;
> > }
> > - spin_unlock_irqrestore(>guc_state.lock, flags);
> > + spin_unlock_irqrestore(>guc_state.lock, flags);
> > return active;
> > }
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index 6be7adf89e4f..d661a69ef4f7 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -681,6 +681,11 @@ static inline int rq_prio(const struct i915_request
> > *rq)
> > return rq->sched.attr.priority;
> > }
> > +static inline bool is_multi_lrc(struct intel_context *ce)
> > +{
> > + return intel_context_is_parallel(ce);
> > +}
> > +
> > static bool is_multi_lrc_rq(struct i915_request *rq)
> > {
> > return intel_context_is_parallel(rq->context);
> > @@ -1214,10 +1219,15 @@ __unwind_incomplete_requests(struct intel_context
> > *ce)
> > static void __guc_reset_context(struct intel_context *ce, bool stalled)
> > {
> > + bool local_stalled;
> > struct i915_request *rq;
> > unsigned long flags;
> > u32 head;
> > + int i, number_children = ce->parallel.number_children;
> > bool skip = false;
> > + struct intel_context *parent = ce;
> > +
> > + GEM_BUG_ON(intel_context_is_child(ce));
> > intel_context_get(ce);
> > @@ -1243,25 +1253,38 @@ static void __guc_reset_context(struct
> > intel_context *ce, bool stalled)
> > if (unlikely(skip))
> > goto out_put;
> > - rq = intel_context_find_active_request(ce);
> > - if (!rq) {
> > - head = ce->ring->tail;
> > - stalled = false;
> > - goto out_replay;
> > - }
> > + /*
> > +* For each context in the relationship find the hanging request
> > +* resetting each context / request as needed
> > +*/
> > + for (i = 0; i < number_children + 1; ++i) {
> > + if (!intel_context_is_pinned(ce))
> > + goto next_context;
> > +
> > + local_stalled = false;
> > + rq = intel_context_find_active_request(ce);
> > + if (!rq) {
> > + head = ce->ring->tail;
> > + goto out_replay;
> > + }
> > - if (!i915_request_started(rq))
> > - stalled = false;
> > + GEM_BUG_ON(i915_active_is_idle(>active));
> > + head = intel_ring_wrap(ce->ring, rq->head);
> > - GEM_BUG_ON(i915_active_is_idle(>active));
> > - head = intel_ring_wrap(ce->ring, rq->head);
> > - __i915_request_reset(rq, stalled);
> > + if (i915_request_started(rq))
> I didn't see an answer as to why the started test and the wrap call need to
> be reversed?
>
Sorry, they don't have to be. Can flip this back
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Fixup header includes (rev2)
Re-reported. -Original Message- From: De Marchi, Lucas Sent: Friday, October 8, 2021 8:10 AM To: intel-gfx@lists.freedesktop.org Cc: Vudum, Lakshminarayana Subject: Re: ✗ Fi.CI.BAT: failure for Fixup header includes (rev2) On Fri, Oct 08, 2021 at 06:44:35AM +, Patchwork wrote: >== Series Details == > >Series: Fixup header includes (rev2) >URL : https://patchwork.freedesktop.org/series/95587/ >State : failure > >== Summary == > >CI Bug Log - changes from CI_DRM_10697 -> Patchwork_21289 > > >Summary >--- > > **FAILURE** > > Serious unknown changes coming with Patchwork_21289 absolutely need > to be verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_21289, please notify your bug team to allow > them to document this new failure mode, which will reduce false positives in > CI. > > External URL: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21289/index.html > >Possible new issues >--- > > Here are the unknown changes that may have been introduced in > Patchwork_21289: > >### IGT changes ### > > Possible regressions > > * igt@gem_exec_suspend@basic-s0: >- fi-kbl-soraka: [PASS][1] -> [INCOMPLETE][2] > [1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/fi-kbl-soraka/igt@gem_exec_susp...@basic-s0.html > [2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21289/fi-kbl-soraka > /igt@gem_exec_susp...@basic-s0.html unrelated to header moves. Like issues https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10685/fi-kbl-soraka/igt@gem_exec_susp...@basic-s0.html https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10658/fi-kbl-soraka/igt@gem_exec_susp...@basic-s0.html Lucas De Marchi
Re: [Intel-gfx] [PATCH 16/26] drm/i915: Fix bug in user proto-context creation that leaked contexts
On 10/4/2021 15:06, Matthew Brost wrote:
Set number of engines before attempting to create contexts so the
function free_engines can clean up properly. Also check return of
alloc_engines for NULL.
v2:
(Tvrtko)
- Send as stand alone patch
(John Harrison)
- Check for alloc_engines returning NULL
v3:
(Checkpatch / Tvrtko)
- Remove braces around single line if statement
Cc: Jason Ekstrand
Fixes: d4433c7600f7 ("drm/i915/gem: Use the proto-context to handle create
parameters (v5)")
Reviewed-by: Tvrtko Ursulin
Signed-off-by: Matthew Brost
Cc:
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 8208fd5b72c3..8c7ea6e56262 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -898,6 +898,10 @@ static struct i915_gem_engines *user_engines(struct
i915_gem_context *ctx,
unsigned int n;
e = alloc_engines(num_engines);
+ if (!e)
+ return ERR_PTR(-ENOMEM);
+ e->num_engines = num_engines;
+
for (n = 0; n < num_engines; n++) {
struct intel_context *ce;
int ret;
@@ -931,7 +935,6 @@ static struct i915_gem_engines *user_engines(struct
i915_gem_context *ctx,
goto free_engines;
}
}
- e->num_engines = num_engines;
return e;
Re: [Intel-gfx] [PATCH 15/26] drm/i915/guc: Update debugfs for GuC multi-lrc
On 10/4/2021 15:06, Matthew Brost wrote:
Display the workqueue status in debugfs for GuC contexts that are in
parent-child relationship.
v2:
(John Harrison)
- Output number children in debugfs
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 53 ++-
1 file changed, 39 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index d661a69ef4f7..f69e984683aa 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -3704,6 +3704,26 @@ static inline void guc_log_context_priority(struct
drm_printer *p,
drm_printf(p, "\n");
}
+
+static inline void guc_log_context(struct drm_printer *p,
+ struct intel_context *ce)
+{
+ drm_printf(p, "GuC lrc descriptor %u:\n", ce->guc_id.id);
+ drm_printf(p, "\tHW Context Desc: 0x%08x\n", ce->lrc.lrca);
+ drm_printf(p, "\t\tLRC Head: Internal %u, Memory %u\n",
+ ce->ring->head,
+ ce->lrc_reg_state[CTX_RING_HEAD]);
+ drm_printf(p, "\t\tLRC Tail: Internal %u, Memory %u\n",
+ ce->ring->tail,
+ ce->lrc_reg_state[CTX_RING_TAIL]);
+ drm_printf(p, "\t\tContext Pin Count: %u\n",
+ atomic_read(>pin_count));
+ drm_printf(p, "\t\tGuC ID Ref Count: %u\n",
+ atomic_read(>guc_id.ref));
+ drm_printf(p, "\t\tSchedule State: 0x%x\n\n",
+ ce->guc_state.sched_state);
+}
+
void intel_guc_submission_print_context_info(struct intel_guc *guc,
struct drm_printer *p)
{
@@ -3713,22 +3733,27 @@ void intel_guc_submission_print_context_info(struct
intel_guc *guc,
xa_lock_irqsave(>context_lookup, flags);
xa_for_each(>context_lookup, index, ce) {
- drm_printf(p, "GuC lrc descriptor %u:\n", ce->guc_id.id);
- drm_printf(p, "\tHW Context Desc: 0x%08x\n", ce->lrc.lrca);
- drm_printf(p, "\t\tLRC Head: Internal %u, Memory %u\n",
- ce->ring->head,
- ce->lrc_reg_state[CTX_RING_HEAD]);
- drm_printf(p, "\t\tLRC Tail: Internal %u, Memory %u\n",
- ce->ring->tail,
- ce->lrc_reg_state[CTX_RING_TAIL]);
- drm_printf(p, "\t\tContext Pin Count: %u\n",
- atomic_read(>pin_count));
- drm_printf(p, "\t\tGuC ID Ref Count: %u\n",
- atomic_read(>guc_id.ref));
- drm_printf(p, "\t\tSchedule State: 0x%x\n\n",
- ce->guc_state.sched_state);
+ GEM_BUG_ON(intel_context_is_child(ce));
+ guc_log_context(p, ce);
guc_log_context_priority(p, ce);
+
+ if (intel_context_is_parent(ce)) {
+ struct guc_process_desc *desc = __get_process_desc(ce);
+ struct intel_context *child;
+
+ drm_printf(p, "\t\tNumber children: %u\n",
+ ce->parallel.number_children);
+ drm_printf(p, "\t\tWQI Head: %u\n",
+ READ_ONCE(desc->head));
+ drm_printf(p, "\t\tWQI Tail: %u\n",
+ READ_ONCE(desc->tail));
+ drm_printf(p, "\t\tWQI Status: %u\n\n",
+ READ_ONCE(desc->wq_status));
+
+ for_each_child(ce, child)
+ guc_log_context(p, child);
+ }
}
xa_unlock_irqrestore(>context_lookup, flags);
}
Re: [Intel-gfx] [PATCH 14/26] drm/i915/guc: Implement multi-lrc reset
On 10/4/2021 15:06, Matthew Brost wrote:
Update context and full GPU reset to work with multi-lrc. The idea is
parent context tracks all the active requests inflight for itself and
its' children. The parent context owns the reset replaying / canceling
Still its' should be its.
requests as needed.
v2:
(John Harrison)
- Simply loop in find active request
- Add comments to find ative request / reset loop
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context.c | 15 +++-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 69 ++-
2 files changed, 63 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index c5bb7ccfb3f8..3b340eb59ada 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -528,20 +528,29 @@ struct i915_request *intel_context_create_request(struct
intel_context *ce)
struct i915_request *intel_context_find_active_request(struct intel_context *ce)
{
+ struct intel_context *parent = intel_context_to_parent(ce);
struct i915_request *rq, *active = NULL;
unsigned long flags;
GEM_BUG_ON(!intel_engine_uses_guc(ce->engine));
- spin_lock_irqsave(>guc_state.lock, flags);
- list_for_each_entry_reverse(rq, >guc_state.requests,
+ /*
+* We search the parent list to find an active request on the submitted
+* context. The parent list contains the requests for all the contexts
+* in the relationship so we have to do a compare of each request's
+* context must be done.
"have to do ... must be done" - no need for both.
+*/
+ spin_lock_irqsave(>guc_state.lock, flags);
+ list_for_each_entry_reverse(rq, >guc_state.requests,
sched.link) {
+ if (rq->context != ce)
+ continue;
if (i915_request_completed(rq))
break;
active = rq;
}
- spin_unlock_irqrestore(>guc_state.lock, flags);
+ spin_unlock_irqrestore(>guc_state.lock, flags);
return active;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 6be7adf89e4f..d661a69ef4f7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -681,6 +681,11 @@ static inline int rq_prio(const struct i915_request *rq)
return rq->sched.attr.priority;
}
+static inline bool is_multi_lrc(struct intel_context *ce)
+{
+ return intel_context_is_parallel(ce);
+}
+
static bool is_multi_lrc_rq(struct i915_request *rq)
{
return intel_context_is_parallel(rq->context);
@@ -1214,10 +1219,15 @@ __unwind_incomplete_requests(struct intel_context *ce)
static void __guc_reset_context(struct intel_context *ce, bool stalled)
{
+ bool local_stalled;
struct i915_request *rq;
unsigned long flags;
u32 head;
+ int i, number_children = ce->parallel.number_children;
bool skip = false;
+ struct intel_context *parent = ce;
+
+ GEM_BUG_ON(intel_context_is_child(ce));
intel_context_get(ce);
@@ -1243,25 +1253,38 @@ static void __guc_reset_context(struct intel_context *ce, bool stalled)
if (unlikely(skip))
goto out_put;
- rq = intel_context_find_active_request(ce);
- if (!rq) {
- head = ce->ring->tail;
- stalled = false;
- goto out_replay;
- }
+ /*
+* For each context in the relationship find the hanging request
+* resetting each context / request as needed
+*/
+ for (i = 0; i < number_children + 1; ++i) {
+ if (!intel_context_is_pinned(ce))
+ goto next_context;
+
+ local_stalled = false;
+ rq = intel_context_find_active_request(ce);
+ if (!rq) {
+ head = ce->ring->tail;
+ goto out_replay;
+ }
- if (!i915_request_started(rq))
- stalled = false;
+ GEM_BUG_ON(i915_active_is_idle(>active));
+ head = intel_ring_wrap(ce->ring, rq->head);
- GEM_BUG_ON(i915_active_is_idle(>active));
- head = intel_ring_wrap(ce->ring, rq->head);
- __i915_request_reset(rq, stalled);
+ if (i915_request_started(rq))
I didn't see an answer as to why the started test and the wrap call need
to be reversed?
John.
+ local_stalled = true;
+ __i915_request_reset(rq, local_stalled && stalled);
out_replay:
- guc_reset_state(ce, head, stalled);
- __unwind_incomplete_requests(ce);
+ guc_reset_state(ce, head, local_stalled && stalled);
+next_context:
+ if (i != number_children)
+
Re: [Intel-gfx] [PATCH 08/26] drm/i915/guc: Add multi-lrc context registration
On Fri, Oct 08, 2021 at 10:20:16AM -0700, John Harrison wrote:
> On 10/7/2021 12:50, John Harrison wrote:
> > On 10/4/2021 15:06, Matthew Brost wrote:
> > > Add multi-lrc context registration H2G. In addition a workqueue and
> > > process descriptor are setup during multi-lrc context registration as
> > > these data structures are needed for multi-lrc submission.
> > >
> > > v2:
> > > (John Harrison)
> > > - Move GuC specific fields into sub-struct
> > > - Clean up WQ defines
> > > - Add comment explaining math to derive WQ / PD address
> > >
> > > Signed-off-by: Matthew Brost
> > > ---
> > > drivers/gpu/drm/i915/gt/intel_context_types.h | 12 ++
> > > drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +
> > > .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 1 +
> > > drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 2 -
> > > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 114 +-
> > > 5 files changed, 131 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > > b/drivers/gpu/drm/i915/gt/intel_context_types.h
> > > index 76dfca57cb45..48decb5ee954 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
> > > @@ -239,6 +239,18 @@ struct intel_context {
> > > struct intel_context *parent;
> > > /** @number_children: number of children if parent */
> > > u8 number_children;
> > > + /** @guc: GuC specific members for parallel submission */
> > > + struct {
> > > + /** @wqi_head: head pointer in work queue */
> > > + u16 wqi_head;
> > > + /** @wqi_tail: tail pointer in work queue */
> > > + u16 wqi_tail;
> PS: As per comments on previous rev, something somewhere needs to explicitly
> state what WQI means. One suggestion was to do that here, ideally with maybe
> a brief description of what the queue is, how it is used, etc. Although
> probably it would be better kept in a GuC specific file. E.g. added to
> guc_fwif.h in patch #12.
>
I think this should just be in the main GuC kernel doc. I can include an
update to the kernel DoC in a patch at the end of the next rev of the
series. That patch doesn't necessarily have to included in the initial
merge of parallel submission if it takes a bit more time to review.
Matt
> John.
>
> > > + /**
> > > + * @parent_page: page in context state (ce->state) used
> > > + * by parent for work queue, process descriptor
> > > + */
> > > + u8 parent_page;
> > > + } guc;
> > > } parallel;
> > > #ifdef CONFIG_DRM_I915_SELFTEST
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > index 3ef9eaf8c50e..57339d5c1fc8 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > @@ -942,6 +942,11 @@ __lrc_alloc_state(struct intel_context *ce,
> > > struct intel_engine_cs *engine)
> > > context_size += PAGE_SIZE;
> > > }
> > > + if (intel_context_is_parent(ce) &&
> > > intel_engine_uses_guc(engine)) {
> > > + ce->parallel.guc.parent_page = context_size / PAGE_SIZE;
> > > + context_size += PAGE_SIZE;
> > > + }
> > > +
> > > obj = i915_gem_object_create_lmem(engine->i915, context_size,
> > > I915_BO_ALLOC_PM_VOLATILE);
> > > if (IS_ERR(obj))
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> > > b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> > > index 8ff58aff..ba10bd374cee 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> > > +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> > > @@ -142,6 +142,7 @@ enum intel_guc_action {
> > > INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
> > > INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
> > > INTEL_GUC_ACTION_DEREGISTER_CONTEXT_DONE = 0x4600,
> > > + INTEL_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
> > > INTEL_GUC_ACTION_RESET_CLIENT = 0x5507,
> > > INTEL_GUC_ACTION_LIMIT
> > > };
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> > > b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> > > index fa4be13c8854..0eeb2a9feeed 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> > > @@ -52,8 +52,6 @@
> > > #define GUC_DOORBELL_INVALID 256
> > > -#define GUC_WQ_SIZE (PAGE_SIZE * 2)
> > > -
> > > /* Work queue item header definitions */
> > > #define WQ_STATUS_ACTIVE 1
> > > #define WQ_STATUS_SUSPENDED 2
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > index 451d9ae861a6..ab6d7fc1b0b1 100644
> > > ---
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion (rev2)
== Series Details == Series: dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion (rev2) URL : https://patchwork.freedesktop.org/series/95605/ State : warning == Summary == $ dim checkpatch origin/drm-tip dcabbee4ce57 dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion -:16: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #16: <7> [187.536343] i915 :00:02.0: [drm:i915_gem_context_create_ioctl [i915]] HW context 1 created total: 0 errors, 1 warnings, 0 checks, 57 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Failsafe migration blits
== Series Details ==
Series: drm/i915: Failsafe migration blits
URL : https://patchwork.freedesktop.org/series/95617/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21293
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21293/index.html
Known issues
Here are the changes found in Patchwork_21293 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-tgl-u2: NOTRUN -> [SKIP][1] ([i915#2190])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21293/fi-tgl-u2/igt@gem_huc_c...@huc-copy.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-tgl-u2: NOTRUN -> [SKIP][2] ([fdo#109284] / [fdo#111827]) +8
similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21293/fi-tgl-u2/igt@kms_chamel...@dp-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-u2: NOTRUN -> [SKIP][3] ([i915#4103]) +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21293/fi-tgl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-u2: NOTRUN -> [SKIP][4] ([fdo#109285])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21293/fi-tgl-u2/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#4269])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21293/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-u2: NOTRUN -> [SKIP][7] ([i915#3301])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21293/fi-tgl-u2/igt@prime_v...@basic-userptr.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][8] ([i915#1602] / [i915#2029])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21293/fi-bdw-5557u/igt@run...@aborted.html
Possible fixes
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a:
- {fi-tgl-dsi}: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-tgl-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-a.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21293/fi-tgl-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
Participating hosts (40 -> 38)
--
Additional (1): fi-tgl-u2
Missing(3): fi-ilk-m540 fi-bsw-cyan fi-hsw-4200u
Build changes
-
* Linux: CI_DRM_10700 -> Patchwork_21293
CI-20190529: 20190529
CI_DRM_10700: 6ecdd5e29c83cd8fc191f8cce5c283eefb53c97e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6240: b232a092b9e1b10a8be13601acaa440903b226bc @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21293: c5653fd415d13fb18f1941ee25d8d17bd84fa232 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c5653fd415d1 drm/i915: Use irq work for coalescing-only dma-fence-work
d38939721ed8 drm/i915/ttm: Attach the migration fence to a region timeline on
eviction
dfed5050f265 drm/i915: Add a struct dma_fence_work timeline
67524b4cd58a drm/i915/ttm: Failsafe migration blits
7b60ee40dcf3 drm/i915: Introduce refcounted sg-tables
1d852143d213 drm/i915: Update dma_fence_work
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21293/index.html
Re: [Intel-gfx] [PATCH 12/26] drm/i915/guc: Implement multi-lrc submission
On 10/4/2021 15:06, Matthew Brost wrote:
Implement multi-lrc submission via a single workqueue entry and single
H2G. The workqueue entry contains an updated tail value for each
request, of all the contexts in the multi-lrc submission, and updates
these values simultaneously. As such, the tasklet and bypass path have
been updated to coalesce requests into a single submission.
v2:
(John Harrison)
- s/wqe/wqi
- Use FIELD_PREP macros
- Add GEM_BUG_ONs ensures length fits within field
- Add comment / white space to intel_guc_write_barrier
(Kernel test robot)
- Make need_tasklet a static function
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 26 ++
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 8 +
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 24 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 23 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 319 --
drivers/gpu/drm/i915/i915_request.h | 8 +
6 files changed, 335 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 8f8182bf7c11..7191e8439290 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -756,3 +756,29 @@ void intel_guc_load_status(struct intel_guc *guc, struct
drm_printer *p)
}
}
}
+
+void intel_guc_write_barrier(struct intel_guc *guc)
+{
+ struct intel_gt *gt = guc_to_gt(guc);
+
+ if (i915_gem_object_is_lmem(guc->ct.vma->obj)) {
+ /*
+* Ensure intel_uncore_write_fw can be used rather than
+* intel_uncore_write.
+*/
+ GEM_BUG_ON(guc->send_regs.fw_domains);
+
+ /*
+* This register is used by the i915 and GuC for MMIO based
+* communication. Once we are in this code CTBs are the only
+* method the i915 uses to communicate with the GuC so it is
+* safe to write to this register (a value of 0 is NOP for MMIO
+* communication). If we ever start mixing CTBs and MMIOs a new
+* register will have to be chosen.
+*/
Hmm, missed it before but this comment is very CTB centric and the
barrier function is now being used for parallel submission work queues.
Seems like an extra comment should be added to cover that case. Just
something simple about WQ usage is also guaranteed to be post CTB switch
over.
+ intel_uncore_write_fw(gt->uncore, GEN11_SOFT_SCRATCH(0), 0);
+ } else {
+ /* wmb() sufficient for a barrier if in smem */
+ wmb();
+ }
+}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index a9f4ec972bfb..147f39cc0f2f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -46,6 +46,12 @@ struct intel_guc {
* submitted until the stalled request is processed.
*/
struct i915_request *stalled_request;
+ enum {
+ STALL_NONE,
+ STALL_REGISTER_CONTEXT,
+ STALL_MOVE_LRC_TAIL,
+ STALL_ADD_REQUEST,
+ } submission_stall_reason;
/* intel_guc_recv interrupt related state */
/** @irq_lock: protects GuC irq state */
@@ -361,4 +367,6 @@ void intel_guc_submission_cancel_requests(struct intel_guc
*guc);
void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p);
+void intel_guc_write_barrier(struct intel_guc *guc);
+
#endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 20c710a74498..10d1878d2826 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -377,28 +377,6 @@ static u32 ct_get_next_fence(struct intel_guc_ct *ct)
return ++ct->requests.last_fence;
}
-static void write_barrier(struct intel_guc_ct *ct)
-{
- struct intel_guc *guc = ct_to_guc(ct);
- struct intel_gt *gt = guc_to_gt(guc);
-
- if (i915_gem_object_is_lmem(guc->ct.vma->obj)) {
- GEM_BUG_ON(guc->send_regs.fw_domains);
- /*
-* This register is used by the i915 and GuC for MMIO based
-* communication. Once we are in this code CTBs are the only
-* method the i915 uses to communicate with the GuC so it is
-* safe to write to this register (a value of 0 is NOP for MMIO
-* communication). If we ever start mixing CTBs and MMIOs a new
-* register will have to be chosen.
-*/
- intel_uncore_write_fw(gt->uncore, GEN11_SOFT_SCRATCH(0), 0);
- } else {
- /* wmb() sufficient for a barrier if in smem */
- wmb();
- }
-}
-
static int ct_write(struct
Re: [Intel-gfx] [PATCH 08/26] drm/i915/guc: Add multi-lrc context registration
On 10/7/2021 12:50, John Harrison wrote:
On 10/4/2021 15:06, Matthew Brost wrote:
Add multi-lrc context registration H2G. In addition a workqueue and
process descriptor are setup during multi-lrc context registration as
these data structures are needed for multi-lrc submission.
v2:
(John Harrison)
- Move GuC specific fields into sub-struct
- Clean up WQ defines
- Add comment explaining math to derive WQ / PD address
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 12 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 2 -
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 114 +-
5 files changed, 131 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 76dfca57cb45..48decb5ee954 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -239,6 +239,18 @@ struct intel_context {
struct intel_context *parent;
/** @number_children: number of children if parent */
u8 number_children;
+ /** @guc: GuC specific members for parallel submission */
+ struct {
+ /** @wqi_head: head pointer in work queue */
+ u16 wqi_head;
+ /** @wqi_tail: tail pointer in work queue */
+ u16 wqi_tail;
PS: As per comments on previous rev, something somewhere needs to
explicitly state what WQI means. One suggestion was to do that here,
ideally with maybe a brief description of what the queue is, how it is
used, etc. Although probably it would be better kept in a GuC specific
file. E.g. added to guc_fwif.h in patch #12.
John.
+ /**
+ * @parent_page: page in context state (ce->state) used
+ * by parent for work queue, process descriptor
+ */
+ u8 parent_page;
+ } guc;
} parallel;
#ifdef CONFIG_DRM_I915_SELFTEST
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 3ef9eaf8c50e..57339d5c1fc8 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -942,6 +942,11 @@ __lrc_alloc_state(struct intel_context *ce,
struct intel_engine_cs *engine)
context_size += PAGE_SIZE;
}
+ if (intel_context_is_parent(ce) &&
intel_engine_uses_guc(engine)) {
+ ce->parallel.guc.parent_page = context_size / PAGE_SIZE;
+ context_size += PAGE_SIZE;
+ }
+
obj = i915_gem_object_create_lmem(engine->i915, context_size,
I915_BO_ALLOC_PM_VOLATILE);
if (IS_ERR(obj))
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index 8ff58aff..ba10bd374cee 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -142,6 +142,7 @@ enum intel_guc_action {
INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
INTEL_GUC_ACTION_DEREGISTER_CONTEXT_DONE = 0x4600,
+ INTEL_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
INTEL_GUC_ACTION_RESET_CLIENT = 0x5507,
INTEL_GUC_ACTION_LIMIT
};
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index fa4be13c8854..0eeb2a9feeed 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -52,8 +52,6 @@
#define GUC_DOORBELL_INVALID 256
-#define GUC_WQ_SIZE (PAGE_SIZE * 2)
-
/* Work queue item header definitions */
#define WQ_STATUS_ACTIVE 1
#define WQ_STATUS_SUSPENDED 2
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 451d9ae861a6..ab6d7fc1b0b1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -344,6 +344,45 @@ static inline struct i915_priolist
*to_priolist(struct rb_node *rb)
return rb_entry(rb, struct i915_priolist, node);
}
+/*
+ * When using multi-lrc submission an extra page in the context
state is
+ * reserved for the process descriptor and work queue.
+ *
+ * The layout of this page is below:
+ * 0 guc_process_desc
+ * ... unused
+ * PAGE_SIZE / 2 work queue start
+ * ... work queue
+ * PAGE_SIZE - 1 work queue end
+ */
+#define WQ_SIZE (PAGE_SIZE / 2)
+#define WQ_OFFSET (PAGE_SIZE - WQ_SIZE)
I thought you were going with '#define PARENT_SCRATCH SIZE PAGE_SIZE'
and then using that everywhere else? Unless there is a fundamental
reason why the above must
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Failsafe migration blits
== Series Details == Series: drm/i915: Failsafe migration blits URL : https://patchwork.freedesktop.org/series/95617/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
[Intel-gfx] ✓ Fi.CI.BAT: success for Fixup header includes (rev2)
== Series Details ==
Series: Fixup header includes (rev2)
URL : https://patchwork.freedesktop.org/series/95587/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10697 -> Patchwork_21289
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21289/index.html
Known issues
Here are the changes found in Patchwork_21289 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +27 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21289/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html
* igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u: NOTRUN -> [WARN][2] ([i915#3718])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21289/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html
* igt@debugfs_test@read_all_entries:
- fi-kbl-soraka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982] /
[i915#262])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21289/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-soraka: [PASS][5] -> [INCOMPLETE][6] ([i915#4221])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/fi-kbl-soraka/igt@gem_exec_susp...@basic-s0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21289/fi-kbl-soraka/igt@gem_exec_susp...@basic-s0.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][7] -> [FAIL][8] ([i915#1372])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21289/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
- fi-bdw-5557u: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21289/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [FAIL][10] ([i915#1888]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21289/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[i915#3718]: https://gitlab.freedesktop.org/drm/intel/issues/3718
[i915#4221]: https://gitlab.freedesktop.org/drm/intel/issues/4221
Participating hosts (43 -> 37)
--
Missing(6): fi-ilk-m540 bat-dg1-6 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
bat-jsl-1
Build changes
-
* Linux: CI_DRM_10697 -> Patchwork_21289
CI-20190529: 20190529
CI_DRM_10697: f03304d71481e701bfdb0d6344741100542fec77 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6237: 910b5caac6625d2bf0b6c1dde502451431bd0159 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21289: cd370a5dc2b1ca43a90268136fb5ceeef88c43fb @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cd370a5dc2b1 drm/i915/display: remove unused intel-mid.h include
6148913a9d12 drm/i915/gt: add asm/cacheflush.h for use of clflush()
e15f66ea24df drm/i915/gt: include tsc.h where used
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21289/index.html
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: move remaining debugfs interfaces into gt (rev10)
== Series Details ==
Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev10)
URL : https://patchwork.freedesktop.org/series/75333/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21292
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/index.html
Known issues
Here are the changes found in Patchwork_21292 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [PASS][2] -> [FAIL][3] ([i915#1888])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-skl-6600u: [PASS][4] -> [FAIL][5] ([i915#3239])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-cfl-guc: [PASS][6] -> [DMESG-FAIL][7] ([i915#541])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-cfl-guc/igt@i915_selftest@live@gt_heartbeat.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/fi-cfl-guc/igt@i915_selftest@live@gt_heartbeat.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[INCOMPLETE][8] ([i915#3921]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a:
- {fi-tgl-dsi}: [DMESG-WARN][10] ([i915#1982]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-tgl-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-a.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/fi-tgl-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#3239]: https://gitlab.freedesktop.org/drm/intel/issues/3239
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts (40 -> 37)
--
Missing(3): fi-ilk-m540 fi-bsw-cyan fi-hsw-4200u
Build changes
-
* Linux: CI_DRM_10700 -> Patchwork_21292
CI-20190529: 20190529
CI_DRM_10700: 6ecdd5e29c83cd8fc191f8cce5c283eefb53c97e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6240: b232a092b9e1b10a8be13601acaa440903b226bc @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21292: 99b302f7d8af14c5640e6d9c73cabddd273b @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
99b302f7 drm/i915/gt: move remaining debugfs interfaces into gt
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/index.html
Re: [Intel-gfx] [PATCH v3] drm/i915/gt: move remaining debugfs interfaces into gt
On Fri, Oct 08, 2021 at 01:27:33PM +0200, Andi Shyti wrote:
> +
> + if (IS_CHERRYVIEW(i915)) {
> + seq_printf(m, "Master Interrupt Control:\t%08x\n",
> +intel_uncore_read(uncore, GEN8_MASTER_IRQ));
> +
> + for (i = 0; i < 4; i++) {
> + seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
> +i, intel_uncore_read(uncore,
> + GEN8_GT_IMR(i)));
> + seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
> +i, intel_uncore_read(uncore,
> + GEN8_GT_IIR(i)));
> + seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
> +i, intel_uncore_read(uncore,
> + GEN8_GT_IER(i)));
> + }
> +
Why does chv get its own block? Looks identical to the bdw block.
> + } else if (GRAPHICS_VER(i915) >= 11) {
> + seq_printf(m, "Master Interrupt Control: %08x\n",
> +intel_uncore_read(uncore, GEN11_GFX_MSTR_IRQ));
> +
> + seq_printf(m, "Render/Copy Intr Enable: %08x\n",
> +intel_uncore_read(uncore,
> + GEN11_RENDER_COPY_INTR_ENABLE));
> + seq_printf(m, "VCS/VECS Intr Enable: %08x\n",
> +intel_uncore_read(uncore,
> + GEN11_VCS_VECS_INTR_ENABLE));
> + seq_printf(m, "GUC/SG Intr Enable:\t %08x\n",
> +intel_uncore_read(uncore,
> + GEN11_GUC_SG_INTR_ENABLE));
> + seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
> +intel_uncore_read(uncore,
> + GEN11_GPM_WGBOXPERF_INTR_ENABLE));
> + seq_printf(m, "Crypto Intr Enable:\t %08x\n",
> +intel_uncore_read(uncore,
> + GEN11_CRYPTO_RSVD_INTR_ENABLE));
> + seq_printf(m, "GUnit/CSME Intr Enable:\t %08x\n",
> +intel_uncore_read(uncore,
> + GEN11_GUNIT_CSME_INTR_ENABLE));
> +
> + } else if (GRAPHICS_VER(i915) >= 8) {
> + seq_printf(m, "Master Interrupt Control:\t%08x\n",
> +intel_uncore_read(uncore, GEN8_MASTER_IRQ));
> +
> + for (i = 0; i < 4; i++) {
> + seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
> +i, intel_uncore_read(uncore,
> + GEN8_GT_IMR(i)));
> + seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
> +i, intel_uncore_read(uncore,
> + GEN8_GT_IIR(i)));
> + seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
> +i, intel_uncore_read(uncore,
> + GEN8_GT_IER(i)));
> + }
> +
> + } else if (IS_VALLEYVIEW(i915)) {
> + seq_printf(m, "Master IER:\t%08x\n",
> +intel_uncore_read(uncore, VLV_MASTER_IER));
> +
> + seq_printf(m, "Render IER:\t%08x\n",
> +intel_uncore_read(uncore, GTIER));
> + seq_printf(m, "Render IIR:\t%08x\n",
> +intel_uncore_read(uncore, GTIIR));
> + seq_printf(m, "Render IMR:\t%08x\n",
> +intel_uncore_read(uncore, GTIMR));
> +
> + seq_printf(m, "PM IER:\t\t%08x\n",
> +intel_uncore_read(uncore, GEN6_PMIER));
> + seq_printf(m, "PM IIR:\t\t%08x\n",
> +intel_uncore_read(uncore, GEN6_PMIIR));
> + seq_printf(m, "PM IMR:\t\t%08x\n",
> +intel_uncore_read(uncore, GEN6_PMIMR));
> +
> + } else if (!HAS_PCH_SPLIT(i915)) {
HAS_PCH_SPLIT in gt code looks a bit out of place.
> + seq_printf(m, "Interrupt enable:%08x\n",
> +intel_uncore_read(uncore, GEN2_IER));
> + seq_printf(m, "Interrupt identity: %08x\n",
> +intel_uncore_read(uncore, GEN2_IIR));
> + seq_printf(m, "Interrupt mask: %08x\n",
> +intel_uncore_read(uncore, GEN2_IMR));
Technically on gen2 these are 16 bits, on gen3+ 32 bits. I don't
quite remember now what happens when you read them as 32bit on gen2.
Might be the msbs just come out all zeroes.
> + } else {
> + seq_printf(m, "Graphics Interrupt enable: %08x\n",
> +intel_uncore_read(uncore, GTIER));
> + seq_printf(m, "Graphics Interrupt identity:
Re: [Intel-gfx] [PATCH 10/26] drm/i915/guc: Assign contexts in parent-child relationship consecutive guc_ids
On 10/7/2021 18:21, Matthew Brost wrote:
On Thu, Oct 07, 2021 at 03:03:04PM -0700, John Harrison wrote:
On 10/4/2021 15:06, Matthew Brost wrote:
Assign contexts in parent-child relationship consecutive guc_ids. This
is accomplished by partitioning guc_id space between ones that need to
be consecutive (1/16 available guc_ids) and ones that do not (15/16 of
available guc_ids). The consecutive search is implemented via the bitmap
API.
This is a precursor to the full GuC multi-lrc implementation but aligns
to how GuC mutli-lrc interface is defined - guc_ids must be consecutive
when using the GuC multi-lrc interface.
v2:
(Daniel Vetter)
- Explicitly state why we assign consecutive guc_ids
v3:
(John Harrison)
- Bring back in spin lock
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 6 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 104 ++
2 files changed, 86 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 25a598e2b6e8..a9f4ec972bfb 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -76,9 +76,13 @@ struct intel_guc {
*/
spinlock_t lock;
/**
-* @guc_ids: used to allocate new guc_ids
+* @guc_ids: used to allocate new guc_ids, single-lrc
*/
struct ida guc_ids;
+ /**
+* @guc_ids_bitmap: used to allocate new guc_ids, multi-lrc
+*/
+ unsigned long *guc_ids_bitmap;
/**
* @guc_id_list: list of intel_context with valid guc_ids but no
* refs
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 1f2809187513..79e7732e83b2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -128,6 +128,16 @@ guc_create_virtual(struct intel_engine_cs **siblings,
unsigned int count);
#define GUC_REQUEST_SIZE 64 /* bytes */
+/*
+ * We reserve 1/16 of the guc_ids for multi-lrc as these need to be contiguous
+ * per the GuC submission interface. A different allocation algorithm is used
+ * (bitmap vs. ida) between multi-lrc and single-lrc hence the reason to
+ * partition the guc_id space. We believe the number of multi-lrc contexts in
+ * use should be low and 1/16 should be sufficient. Minimum of 32 guc_ids for
+ * multi-lrc.
+ */
+#define NUMBER_MULTI_LRC_GUC_ID(GUC_MAX_LRC_DESCRIPTORS / 16)
+
/*
* Below is a set of functions which control the GuC scheduling state which
* require a lock.
@@ -1206,6 +1216,11 @@ int intel_guc_submission_init(struct intel_guc *guc)
INIT_WORK(>submission_state.destroyed_worker,
destroyed_worker_func);
+ guc->submission_state.guc_ids_bitmap =
+ bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID, GFP_KERNEL);
+ if (!guc->submission_state.guc_ids_bitmap)
+ return -ENOMEM;
+
return 0;
}
@@ -1217,6 +1232,7 @@ void intel_guc_submission_fini(struct intel_guc *guc)
guc_lrc_desc_pool_destroy(guc);
guc_flush_destroyed_contexts(guc);
i915_sched_engine_put(guc->sched_engine);
+ bitmap_free(guc->submission_state.guc_ids_bitmap);
}
static inline void queue_request(struct i915_sched_engine *sched_engine,
@@ -1268,18 +1284,43 @@ static void guc_submit_request(struct i915_request *rq)
spin_unlock_irqrestore(_engine->lock, flags);
}
-static int new_guc_id(struct intel_guc *guc)
+static int new_guc_id(struct intel_guc *guc, struct intel_context *ce)
{
- return ida_simple_get(>submission_state.guc_ids, 0,
- GUC_MAX_LRC_DESCRIPTORS, GFP_KERNEL |
- __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
+ int ret;
+
+ GEM_BUG_ON(intel_context_is_child(ce));
+
+ if (intel_context_is_parent(ce))
+ ret =
bitmap_find_free_region(guc->submission_state.guc_ids_bitmap,
+ NUMBER_MULTI_LRC_GUC_ID,
+
order_base_2(ce->parallel.number_children
+ + 1));
+ else
+ ret = ida_simple_get(>submission_state.guc_ids,
+NUMBER_MULTI_LRC_GUC_ID,
+GUC_MAX_LRC_DESCRIPTORS,
+GFP_KERNEL | __GFP_RETRY_MAYFAIL |
+__GFP_NOWARN);
+ if (unlikely(ret < 0))
+ return ret;
+
+ ce->guc_id.id = ret;
+ return 0;
}
static void __release_guc_id(struct intel_guc *guc, struct intel_context *ce)
{
+ GEM_BUG_ON(intel_context_is_child(ce));
+
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: move remaining debugfs interfaces into gt (rev10)
== Series Details == Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev10) URL : https://patchwork.freedesktop.org/series/75333/ State : warning == Summary == $ dim checkpatch origin/drm-tip 99b302f7 drm/i915/gt: move remaining debugfs interfaces into gt -:138: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #138: new file mode 100644 -:271: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #271: FILE: drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c:129: + intel_uncore_read(uncore, + GEN12_VCS4_VCS5_INTR_MASK)); -:275: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #275: FILE: drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c:133: + intel_uncore_read(uncore, + GEN12_VCS6_VCS7_INTR_MASK)); -:284: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #284: FILE: drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c:142: + intel_uncore_read(uncore, + GEN12_VECS2_VECS3_INTR_MASK)); total: 0 errors, 1 warnings, 3 checks, 412 lines checked
Re: [Intel-gfx] [PATCH] dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion
Am 08.10.21 um 12:49 schrieb Tvrtko Ursulin:
On 08/10/2021 11:21, Christian König wrote:
Am 08.10.21 um 11:50 schrieb Tvrtko Ursulin:
From: Tvrtko Ursulin
Cache the count of shared fences in the iterator to avoid dereferencing
the dma_resv_object outside the RCU protection. Otherwise iterator
and its
users can observe an incosistent state which makes it impossible to use
safely.
Ah, of course! I've been staring at the code the whole morning and
couldn't see it.
Going to write a testcase to cover that.
Such as:
<6> [187.517041] [IGT] gem_sync: executing
<7> [187.536343] i915 :00:02.0:
[drm:i915_gem_context_create_ioctl [i915]] HW context 1 created
<7> [187.536793] i915 :00:02.0:
[drm:i915_gem_context_create_ioctl [i915]] HW context 1 created
<6> [187.551235] [IGT] gem_sync: starting subtest basic-many-each
<1> [188.935462] BUG: kernel NULL pointer dereference, address:
0010
<1> [188.935485] #PF: supervisor write access in kernel mode
<1> [188.935495] #PF: error_code(0x0002) - not-present page
<6> [188.935504] PGD 0 P4D 0
<4> [188.935512] Oops: 0002 [#1] PREEMPT SMP NOPTI
<4> [188.935521] CPU: 2 PID: 1467 Comm: gem_sync Not tainted
5.15.0-rc4-CI-Patchwork_21264+ #1
<4> [188.935535] Hardware name: /NUC6CAYB, BIOS
AYAPLCEL.86A.0049.2018.0508.1356 05/08/2018
<4> [188.935546] RIP: 0010:dma_resv_get_fences+0x116/0x2d0
<4> [188.935560] Code: 10 85 c0 7f c9 be 03 00 00 00 e8 15 8b df ff
eb bd e8 8e c6 ff ff eb b6 41 8b 04 24 49 8b 55 00 48 89 e7 8d 48 01
41 89 0c 24 <4c> 89 34 c2 e8 41 f2 ff ff 49 89 c6 48 85 c0 75 8c 48
8b 44 24 10
<4> [188.935583] RSP: 0018:c900011dbcc8 EFLAGS: 00010202
<4> [188.935593] RAX: RBX: RCX:
0001
<4> [188.935603] RDX: 0010 RSI: 822e343c RDI:
c900011dbcc8
<4> [188.935613] RBP: c900011dbd48 R08: 88812d255bb8 R09:
fffe
<4> [188.935623] R10: 0001 R11: R12:
c900011dbd44
<4> [188.935633] R13: c900011dbd50 R14: 888113d29cc0 R15:
<4> [188.935643] FS: 7f68d17e9700()
GS:88827790() knlGS:
<4> [188.935655] CS: 0010 DS: ES: CR0: 80050033
<4> [188.935665] CR2: 0010 CR3: 00012d0a4000 CR4:
003506e0
<4> [188.935676] Call Trace:
<4> [188.935685] i915_gem_object_wait+0x1ff/0x410 [i915]
<4> [188.935988] i915_gem_wait_ioctl+0xf2/0x2a0 [i915]
<4> [188.936272] ? i915_gem_object_wait+0x410/0x410 [i915]
<4> [188.936533] drm_ioctl_kernel+0xae/0x140
<4> [188.936546] drm_ioctl+0x201/0x3d0
<4> [188.936555] ? i915_gem_object_wait+0x410/0x410 [i915]
<4> [188.936820] ? __fget_files+0xc2/0x1c0
<4> [188.936830] ? __fget_files+0xda/0x1c0
<4> [188.936839] __x64_sys_ioctl+0x6d/0xa0
<4> [188.936848] do_syscall_64+0x3a/0xb0
<4> [188.936859] entry_SYSCALL_64_after_hwframe+0x44/0xae
If the shared object has changed during the RCU unlocked period
callers will correctly handle the restart on the next iteration.
Signed-off-by: Tvrtko Ursulin
Fixes: 96601e8a4755 ("dma-buf: use new iterator in
dma_resv_copy_fences")
Fixes: d3c80698c9f5 ("dma-buf: use new iterator in
dma_resv_get_fences v3")
Closes:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Fintel%2F-%2Fissues%2F4274data=04%7C01%7Cchristian.koenig%40amd.com%7Cc22feea06a3f4285cdac08d98a495984%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637692870805160909%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000sdata=6oPR30sWnJe04I4GlhhvJWX3QvwKFIOMW1uOIyWZFOE%3Dreserved=0
Cc: Christian König
Cc: Daniel Vetter
Cc: Sumit Semwal
Cc: linux-me...@vger.kernel.org
Cc: dri-de...@lists.freedesktop.org
Cc: linaro-mm-...@lists.linaro.org
Maybe we should remove cursor->fences altogether, but either way the
patch is Reviewed-by: Christian König
Please push to drm-misc-next ASAP.
Not sure I can or if my push permissions are limited to Intel
branches. I can try once CI gives a green light.
If it doesn't work just ping me and I will push it.
Thanks,
Christian.
Regards,
Tvrtko
Thanks,
Christian.
---
drivers/dma-buf/dma-resv.c | 18 ++
include/linux/dma-resv.h | 5 -
2 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c
index a480af9581bd..7b6d881c8904 100644
--- a/drivers/dma-buf/dma-resv.c
+++ b/drivers/dma-buf/dma-resv.c
@@ -333,10 +333,14 @@ static void
dma_resv_iter_restart_unlocked(struct dma_resv_iter *cursor)
{
cursor->seq = read_seqcount_begin(>obj->seq);
cursor->index = -1;
- if (cursor->all_fences)
+ cursor->shared_count = 0;
+ if (cursor->all_fences) {
cursor->fences = dma_resv_shared_list(cursor->obj);
- else
+ if (cursor->fences)
+ cursor->shared_count = cursor->fences->shared_count;
+ } else {
Re: [Intel-gfx] [PATCH v2] drm/i915/gt: move remaining debugfs interfaces into gt
Hi,
please ignore! I run the command from the history and forgot that
I had to update the patch file. :)
V3 of this patch is coming soon.
Andi
On Fri, Oct 08, 2021 at 01:22:48PM +0200, Andi Shyti wrote:
> From: Andi Shyti
>
> The following interfaces:
>
> i915_wedged
> i915_forcewake_user
> i915_gem_interrupt
>
> are dependent on gt values. Put them inside gt/ and drop the
> "i915_" prefix name. This would be the new structure:
>
> dri/0/gt
> |
> +-- forcewake_user
> |
> +-- interrupt_info
> |
> \-- reset
>
> For backwards compatibility with existing igt (and the slight
> semantic difference between operating on the i915 abi entry
> points and the deep gt info):
>
> dri/0
> |
> +-- i915_wedged
> |
> \-- i915_forcewake_user
>
> remain at the top level.
>
> Signed-off-by: Andi Shyti
> Cc: Tvrtko Ursulin
> Cc: Chris Wilson
> ---
> Hi,
>
> I am reproposing this patch exactly as it was proposed initially
> where the original interfaces are kept where they have been
> originally placed. It might generate some duplicated code but,
> well, it's debugfs and I don't see any issue. In the future we
> can transform the upper interfaces to act upon all the GTs and
> provide information from all the GTs. This is, for example, how
> the sysfs interfaces will act.
>
> The reason I removed them in V1 is because igt as only user is
> not a strong reason to keep duplicated code, but as Chris
> suggested offline:
>
> "It's debugfs, igt is the primary consumer. CI has to be bridged over
> changes to the interfaces it is using in any case, as you want
> comparable results before/after the patches land.
>
> For i915_forcewake_user, it's not just igt testing, but part of the
> tools/ packaged up by distro. That makes it a very strong candidate to be
> moved out of debugfs into sysfs/gt."
>
> I, therefore, repropose this patch with the idea of improving the
> behavior of the upper level interfaces as described above.
>
> Thanks,
> Andi
>
> Changelog:
> --
> v1 -> v2:
> * keep the original interfaces intact (thanks Chris).
>
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/gt/intel_gt_debugfs.c| 47 -
> .../gpu/drm/i915/gt/intel_gt_irq_debugfs.c| 178 ++
> .../gpu/drm/i915/gt/intel_gt_irq_debugfs.h| 15 ++
> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 31 +++
> 5 files changed, 271 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c
> create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index cdc244bbbfc1..e92984954ba8 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -98,6 +98,7 @@ gt-y += \
> gt/intel_gt_debugfs.o \
> gt/intel_gt_engines_debugfs.o \
> gt/intel_gt_irq.o \
> + gt/intel_gt_irq_debugfs.o \
> gt/intel_gt_pm.o \
> gt/intel_gt_pm_debugfs.o \
> gt/intel_gt_pm_irq.o \
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> index 1fe19ccd2794..d3075c138585 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> @@ -8,11 +8,54 @@
> #include "i915_drv.h"
> #include "intel_gt_debugfs.h"
> #include "intel_gt_engines_debugfs.h"
> +#include "intel_gt_irq_debugfs.h"
> +#include "intel_gt_pm.h"
> #include "intel_gt_pm_debugfs.h"
> +#include "intel_gt_requests.h"
> #include "intel_sseu_debugfs.h"
> #include "pxp/intel_pxp_debugfs.h"
> #include "uc/intel_uc_debugfs.h"
>
> +static int reset_show(void *data, u64 *val)
> +{
> + struct intel_gt *gt = data;
> + int ret = intel_gt_terminally_wedged(gt);
> +
> + switch (ret) {
> + case -EIO:
> + *val = 1;
> + return 0;
> + case 0:
> + *val = 0;
> + return 0;
> + default:
> + return ret;
> + }
> +}
> +
> +static int reset_store(void *data, u64 val)
> +{
> + struct intel_gt *gt = data;
> +
> + /* Flush any previous reset before applying for a new one */
> + wait_event(gt->reset.queue,
> +!test_bit(I915_RESET_BACKOFF, >reset.flags));
> +
> + intel_gt_handle_error(gt, val, I915_ERROR_CAPTURE,
> + "Manually reset engine mask to %llx", val);
> + return 0;
> +}
> +DEFINE_SIMPLE_ATTRIBUTE(reset_fops, reset_show, reset_store, "%llu\n");
> +
> +static void gt_debugfs_register(struct intel_gt *gt, struct dentry *root)
> +{
> + static const struct intel_gt_debugfs_file files[] = {
> + { "reset", _fops, NULL },
> + };
> +
> + intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
> +}
> +
> void intel_gt_debugfs_register(struct intel_gt *gt)
> {
> struct dentry *root;
> @@ -24,10 +67,12 @@ void intel_gt_debugfs_register(struct intel_gt *gt)
>
[Intel-gfx] [PATCH v3] drm/i915/gt: move remaining debugfs interfaces into gt
From: Andi Shyti
The following interfaces:
i915_wedged
i915_forcewake_user
i915_gem_interrupt
are dependent on gt values. Put them inside gt/ and drop the
"i915_" prefix name. This would be the new structure:
dri/0/gt
|
+-- forcewake_user
|
+-- interrupt_info
|
\-- reset
For backwards compatibility with existing igt (and the slight
semantic difference between operating on the i915 abi entry
points and the deep gt info):
dri/0
|
+-- i915_wedged
|
\-- i915_forcewake_user
remain at the top level.
Signed-off-by: Andi Shyti
Cc: Tvrtko Ursulin
Cc: Chris Wilson
---
Hi Lucas and Chris,
this third version tries to remove duplicated code, but roughly
the amount of code removed is equal to the amount of code added.
In my opinion it doesn't improve much the code. Amongst the three
versions I still prefer the v2.
Changelog:
--
v2 -> v3: https://patchwork.freedesktop.org/patch/458108/
* keep the original interfaces as they were (thanks Chris) but
implement the functionality inside the gt. The upper level
files will call the gt functions (thanks Lucas).
v1 -> v2: https://patchwork.freedesktop.org/patch/456652/
* keep the original interfaces intact (thanks Chris).
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c| 47 -
drivers/gpu/drm/i915/gt/intel_gt_debugfs.h| 4 +
.../gpu/drm/i915/gt/intel_gt_irq_debugfs.c| 178 ++
.../gpu/drm/i915/gt/intel_gt_irq_debugfs.h| 15 ++
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 41
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h | 4 +
drivers/gpu/drm/i915/i915_debugfs.c | 43 +
8 files changed, 296 insertions(+), 37 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index cdc244bbbfc1..e92984954ba8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -98,6 +98,7 @@ gt-y += \
gt/intel_gt_debugfs.o \
gt/intel_gt_engines_debugfs.o \
gt/intel_gt_irq.o \
+ gt/intel_gt_irq_debugfs.o \
gt/intel_gt_pm.o \
gt/intel_gt_pm_debugfs.o \
gt/intel_gt_pm_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
index 1fe19ccd2794..0d651c33110d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
@@ -8,11 +8,54 @@
#include "i915_drv.h"
#include "intel_gt_debugfs.h"
#include "intel_gt_engines_debugfs.h"
+#include "intel_gt_irq_debugfs.h"
+#include "intel_gt_pm.h"
#include "intel_gt_pm_debugfs.h"
+#include "intel_gt_requests.h"
#include "intel_sseu_debugfs.h"
#include "pxp/intel_pxp_debugfs.h"
#include "uc/intel_uc_debugfs.h"
+int reset_show(void *data, u64 *val)
+{
+ struct intel_gt *gt = data;
+ int ret = intel_gt_terminally_wedged(gt);
+
+ switch (ret) {
+ case -EIO:
+ *val = 1;
+ return 0;
+ case 0:
+ *val = 0;
+ return 0;
+ default:
+ return ret;
+ }
+}
+
+int reset_store(void *data, u64 val)
+{
+ struct intel_gt *gt = data;
+
+ /* Flush any previous reset before applying for a new one */
+ wait_event(gt->reset.queue,
+ !test_bit(I915_RESET_BACKOFF, >reset.flags));
+
+ intel_gt_handle_error(gt, val, I915_ERROR_CAPTURE,
+ "Manually reset engine mask to %llx", val);
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(reset_fops, reset_show, reset_store, "%llu\n");
+
+static void gt_debugfs_register(struct intel_gt *gt, struct dentry *root)
+{
+ static const struct intel_gt_debugfs_file files[] = {
+ { "reset", _fops, NULL },
+ };
+
+ intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
+}
+
void intel_gt_debugfs_register(struct intel_gt *gt)
{
struct dentry *root;
@@ -24,10 +67,12 @@ void intel_gt_debugfs_register(struct intel_gt *gt)
if (IS_ERR(root))
return;
+ gt_debugfs_register(gt, root);
+
intel_gt_engines_debugfs_register(gt, root);
intel_gt_pm_debugfs_register(gt, root);
+ intel_gt_irq_debugfs_register(gt, root);
intel_sseu_debugfs_register(gt, root);
-
intel_uc_debugfs_register(>uc, root);
intel_pxp_debugfs_register(>pxp, root);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
index 8b6fca09897c..6bc4f044c23f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
@@ -35,4 +35,8 @@ void intel_gt_debugfs_register_files(struct dentry *root,
const struct intel_gt_debugfs_file *files,
[Intel-gfx] [PATCH v2] drm/i915/gt: move remaining debugfs interfaces into gt
From: Andi Shyti
The following interfaces:
i915_wedged
i915_forcewake_user
i915_gem_interrupt
are dependent on gt values. Put them inside gt/ and drop the
"i915_" prefix name. This would be the new structure:
dri/0/gt
|
+-- forcewake_user
|
+-- interrupt_info
|
\-- reset
For backwards compatibility with existing igt (and the slight
semantic difference between operating on the i915 abi entry
points and the deep gt info):
dri/0
|
+-- i915_wedged
|
\-- i915_forcewake_user
remain at the top level.
Signed-off-by: Andi Shyti
Cc: Tvrtko Ursulin
Cc: Chris Wilson
---
Hi,
I am reproposing this patch exactly as it was proposed initially
where the original interfaces are kept where they have been
originally placed. It might generate some duplicated code but,
well, it's debugfs and I don't see any issue. In the future we
can transform the upper interfaces to act upon all the GTs and
provide information from all the GTs. This is, for example, how
the sysfs interfaces will act.
The reason I removed them in V1 is because igt as only user is
not a strong reason to keep duplicated code, but as Chris
suggested offline:
"It's debugfs, igt is the primary consumer. CI has to be bridged over
changes to the interfaces it is using in any case, as you want
comparable results before/after the patches land.
For i915_forcewake_user, it's not just igt testing, but part of the
tools/ packaged up by distro. That makes it a very strong candidate to be
moved out of debugfs into sysfs/gt."
I, therefore, repropose this patch with the idea of improving the
behavior of the upper level interfaces as described above.
Thanks,
Andi
Changelog:
--
v1 -> v2:
* keep the original interfaces intact (thanks Chris).
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c| 47 -
.../gpu/drm/i915/gt/intel_gt_irq_debugfs.c| 178 ++
.../gpu/drm/i915/gt/intel_gt_irq_debugfs.h| 15 ++
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 31 +++
5 files changed, 271 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index cdc244bbbfc1..e92984954ba8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -98,6 +98,7 @@ gt-y += \
gt/intel_gt_debugfs.o \
gt/intel_gt_engines_debugfs.o \
gt/intel_gt_irq.o \
+ gt/intel_gt_irq_debugfs.o \
gt/intel_gt_pm.o \
gt/intel_gt_pm_debugfs.o \
gt/intel_gt_pm_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
index 1fe19ccd2794..d3075c138585 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
@@ -8,11 +8,54 @@
#include "i915_drv.h"
#include "intel_gt_debugfs.h"
#include "intel_gt_engines_debugfs.h"
+#include "intel_gt_irq_debugfs.h"
+#include "intel_gt_pm.h"
#include "intel_gt_pm_debugfs.h"
+#include "intel_gt_requests.h"
#include "intel_sseu_debugfs.h"
#include "pxp/intel_pxp_debugfs.h"
#include "uc/intel_uc_debugfs.h"
+static int reset_show(void *data, u64 *val)
+{
+ struct intel_gt *gt = data;
+ int ret = intel_gt_terminally_wedged(gt);
+
+ switch (ret) {
+ case -EIO:
+ *val = 1;
+ return 0;
+ case 0:
+ *val = 0;
+ return 0;
+ default:
+ return ret;
+ }
+}
+
+static int reset_store(void *data, u64 val)
+{
+ struct intel_gt *gt = data;
+
+ /* Flush any previous reset before applying for a new one */
+ wait_event(gt->reset.queue,
+ !test_bit(I915_RESET_BACKOFF, >reset.flags));
+
+ intel_gt_handle_error(gt, val, I915_ERROR_CAPTURE,
+ "Manually reset engine mask to %llx", val);
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(reset_fops, reset_show, reset_store, "%llu\n");
+
+static void gt_debugfs_register(struct intel_gt *gt, struct dentry *root)
+{
+ static const struct intel_gt_debugfs_file files[] = {
+ { "reset", _fops, NULL },
+ };
+
+ intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
+}
+
void intel_gt_debugfs_register(struct intel_gt *gt)
{
struct dentry *root;
@@ -24,10 +67,12 @@ void intel_gt_debugfs_register(struct intel_gt *gt)
if (IS_ERR(root))
return;
+ gt_debugfs_register(gt, root);
+
intel_gt_engines_debugfs_register(gt, root);
intel_gt_pm_debugfs_register(gt, root);
+ intel_gt_irq_debugfs_register(gt, root);
intel_sseu_debugfs_register(gt, root);
-
intel_uc_debugfs_register(>uc, root);
intel_pxp_debugfs_register(>pxp, root);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c
[Intel-gfx] ✗ Fi.CI.BAT: failure for dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion
== Series Details == Series: dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion URL : https://patchwork.freedesktop.org/series/95605/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10699 -> Patchwork_21291 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21291 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21291, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21291/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21291: ### IGT changes ### Possible regressions * igt@core_hotunplug@unbind-rebind: - fi-tgl-u2: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21291/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html Known issues Here are the changes found in Patchwork_21291 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-tgl-1115g4: NOTRUN -> [SKIP][2] ([fdo#109315]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21291/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][3] ([fdo#109271]) +23 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21291/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html * igt@amdgpu/amd_cs_nop@nop-gfx0: - fi-tgl-1115g4: NOTRUN -> [SKIP][4] ([fdo#109315] / [i915#2575]) +16 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21291/fi-tgl-1115g4/igt@amdgpu/amd_cs_...@nop-gfx0.html * igt@amdgpu/amd_cs_nop@sync-compute0: - fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271]) +6 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21291/fi-kbl-soraka/igt@amdgpu/amd_cs_...@sync-compute0.html * igt@gem_huc_copy@huc-copy: - fi-tgl-u2: NOTRUN -> [SKIP][6] ([i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21291/fi-tgl-u2/igt@gem_huc_c...@huc-copy.html - fi-tgl-1115g4: NOTRUN -> [SKIP][7] ([i915#2190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21291/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html * igt@i915_pm_backlight@basic-brightness: - fi-tgl-1115g4: NOTRUN -> [SKIP][8] ([i915#1155]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21291/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-tgl-1115g4: NOTRUN -> [SKIP][9] ([fdo#111827]) +8 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21291/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@dp-hpd-fast: - fi-tgl-u2: NOTRUN -> [SKIP][10] ([fdo#109284] / [fdo#111827]) +8 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21291/fi-tgl-u2/igt@kms_chamel...@dp-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-u2: NOTRUN -> [SKIP][11] ([i915#4103]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21291/fi-tgl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html - fi-tgl-1115g4: NOTRUN -> [SKIP][12] ([i915#4103]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21291/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_flip@basic-plain-flip@c-dp1: - fi-cfl-8109u: [PASS][13] -> [FAIL][14] ([i915#4165]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10699/fi-cfl-8109u/igt@kms_flip@basic-plain-f...@c-dp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21291/fi-cfl-8109u/igt@kms_flip@basic-plain-f...@c-dp1.html * igt@kms_force_connector_basic@force-load-detect: - fi-tgl-1115g4: NOTRUN -> [SKIP][15] ([fdo#109285]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21291/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html - fi-tgl-u2: NOTRUN -> [SKIP][16] ([fdo#109285]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21291/fi-tgl-u2/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b: - fi-cfl-8109u: [PASS][17] -> [DMESG-WARN][18] ([i915#295]) +14 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10699/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html [18]:
Re: [Intel-gfx] [PATCH 3/5] drm/radeon: check dri root before debugfs init
[AMD Official Use Only]
I sent all the patches to dr-devel. I think there is an issue with our email
server. Thunderbird is asking for a password every few minutes.
https://patchwork.freedesktop.org/series/95603/
Nirmoy
[sending this from my browser]
From: Koenig, Christian
Sent: Friday, October 8, 2021 12:23 PM
To: Das, Nirmoy ; dri-de...@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org ; Deucher,
Alexander ; Pan, Xinhui
Subject: Re: [PATCH 3/5] drm/radeon: check dri root before debugfs init
Am 08.10.21 um 11:17 schrieb Nirmoy Das:
> Return early if dri minor root dentry is NULL.
>
> CC: Alex Deucher
> CC: "Christian König"
> CC: "Pan, Xinhui"
>
> Signed-off-by: Nirmoy Das
Acked-by: Christian König
Where are the other patches from the series?
Thanks,
Christian.
> ---
> drivers/gpu/drm/radeon/r100.c | 9 +
> drivers/gpu/drm/radeon/r300.c | 3 +++
> drivers/gpu/drm/radeon/r420.c | 3 +++
> drivers/gpu/drm/radeon/r600.c | 3 +++
> drivers/gpu/drm/radeon/radeon_dp_mst.c | 3 +++
> drivers/gpu/drm/radeon/radeon_fence.c | 3 +++
> drivers/gpu/drm/radeon/radeon_gem.c| 3 +++
> drivers/gpu/drm/radeon/radeon_ib.c | 3 +++
> drivers/gpu/drm/radeon/radeon_pm.c | 5 -
> drivers/gpu/drm/radeon/radeon_ring.c | 3 +++
> drivers/gpu/drm/radeon/radeon_ttm.c| 3 +++
> drivers/gpu/drm/radeon/rs400.c | 3 +++
> drivers/gpu/drm/radeon/rv515.c | 3 +++
> 13 files changed, 46 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
> index 2dd85ba1faa2..ae6c95b34013 100644
> --- a/drivers/gpu/drm/radeon/r100.c
> +++ b/drivers/gpu/drm/radeon/r100.c
> @@ -3059,6 +3059,9 @@ void r100_debugfs_rbbm_init(struct radeon_device *rdev)
> #if defined(CONFIG_DEBUG_FS)
>struct dentry *root = rdev->ddev->primary->debugfs_root;
>
> + if (!root)
> + return;
> +
>debugfs_create_file("r100_rbbm_info", 0444, root, rdev,
>_debugfs_rbbm_info_fops);
> #endif
> @@ -3069,6 +3072,9 @@ void r100_debugfs_cp_init(struct radeon_device *rdev)
> #if defined(CONFIG_DEBUG_FS)
>struct dentry *root = rdev->ddev->primary->debugfs_root;
>
> + if (!root)
> + return;
> +
>debugfs_create_file("r100_cp_ring_info", 0444, root, rdev,
>_debugfs_cp_ring_info_fops);
>debugfs_create_file("r100_cp_csq_fifo", 0444, root, rdev,
> @@ -3081,6 +3087,9 @@ void r100_debugfs_mc_info_init(struct radeon_device
> *rdev)
> #if defined(CONFIG_DEBUG_FS)
>struct dentry *root = rdev->ddev->primary->debugfs_root;
>
> + if (!root)
> + return;
> +
>debugfs_create_file("r100_mc_info", 0444, root, rdev,
>_debugfs_mc_info_fops);
> #endif
> diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
> index 621ff174dff3..b22969e2394f 100644
> --- a/drivers/gpu/drm/radeon/r300.c
> +++ b/drivers/gpu/drm/radeon/r300.c
> @@ -618,6 +618,9 @@ static void rv370_debugfs_pcie_gart_info_init(struct
> radeon_device *rdev)
> #if defined(CONFIG_DEBUG_FS)
>struct dentry *root = rdev->ddev->primary->debugfs_root;
>
> + if (!root)
> + return;
> +
>debugfs_create_file("rv370_pcie_gart_info", 0444, root, rdev,
>_debugfs_pcie_gart_info_fops);
> #endif
> diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
> index 7e6320e8c6a0..cdb4ac3e346b 100644
> --- a/drivers/gpu/drm/radeon/r420.c
> +++ b/drivers/gpu/drm/radeon/r420.c
> @@ -494,6 +494,9 @@ void r420_debugfs_pipes_info_init(struct radeon_device
> *rdev)
> #if defined(CONFIG_DEBUG_FS)
>struct dentry *root = rdev->ddev->primary->debugfs_root;
>
> + if (!root)
> + return;
> +
>debugfs_create_file("r420_pipes_info", 0444, root, rdev,
>_debugfs_pipes_info_fops);
> #endif
> diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
> index ca3fcae2adb5..d8f525cf0c3b 100644
> --- a/drivers/gpu/drm/radeon/r600.c
> +++ b/drivers/gpu/drm/radeon/r600.c
> @@ -4360,6 +4360,9 @@ static void r600_debugfs_mc_info_init(struct
> radeon_device *rdev)
> #if defined(CONFIG_DEBUG_FS)
>struct dentry *root = rdev->ddev->primary->debugfs_root;
>
> + if (!root)
> + return;
> +
>debugfs_create_file("r600_mc_info", 0444, root, rdev,
>_debugfs_mc_info_fops);
>
> diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c
> b/drivers/gpu/drm/radeon/radeon_dp_mst.c
> index ec867fa880a4..cf06da89bb7c 100644
> --- a/drivers/gpu/drm/radeon/radeon_dp_mst.c
> +++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c
> @@ -771,6 +771,9 @@ void radeon_mst_debugfs_init(struct radeon_device *rdev)
> #if defined(CONFIG_DEBUG_FS)
>struct dentry *root =
Re: [Intel-gfx] [PATCH 3/5] drm/radeon: check dri root before debugfs init
Am 08.10.21 um 11:17 schrieb Nirmoy Das:
Return early if dri minor root dentry is NULL.
CC: Alex Deucher
CC: "Christian König"
CC: "Pan, Xinhui"
Signed-off-by: Nirmoy Das
Acked-by: Christian König
Where are the other patches from the series?
Thanks,
Christian.
---
drivers/gpu/drm/radeon/r100.c | 9 +
drivers/gpu/drm/radeon/r300.c | 3 +++
drivers/gpu/drm/radeon/r420.c | 3 +++
drivers/gpu/drm/radeon/r600.c | 3 +++
drivers/gpu/drm/radeon/radeon_dp_mst.c | 3 +++
drivers/gpu/drm/radeon/radeon_fence.c | 3 +++
drivers/gpu/drm/radeon/radeon_gem.c| 3 +++
drivers/gpu/drm/radeon/radeon_ib.c | 3 +++
drivers/gpu/drm/radeon/radeon_pm.c | 5 -
drivers/gpu/drm/radeon/radeon_ring.c | 3 +++
drivers/gpu/drm/radeon/radeon_ttm.c| 3 +++
drivers/gpu/drm/radeon/rs400.c | 3 +++
drivers/gpu/drm/radeon/rv515.c | 3 +++
13 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 2dd85ba1faa2..ae6c95b34013 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -3059,6 +3059,9 @@ void r100_debugfs_rbbm_init(struct radeon_device *rdev)
#if defined(CONFIG_DEBUG_FS)
struct dentry *root = rdev->ddev->primary->debugfs_root;
+ if (!root)
+ return;
+
debugfs_create_file("r100_rbbm_info", 0444, root, rdev,
_debugfs_rbbm_info_fops);
#endif
@@ -3069,6 +3072,9 @@ void r100_debugfs_cp_init(struct radeon_device *rdev)
#if defined(CONFIG_DEBUG_FS)
struct dentry *root = rdev->ddev->primary->debugfs_root;
+ if (!root)
+ return;
+
debugfs_create_file("r100_cp_ring_info", 0444, root, rdev,
_debugfs_cp_ring_info_fops);
debugfs_create_file("r100_cp_csq_fifo", 0444, root, rdev,
@@ -3081,6 +3087,9 @@ void r100_debugfs_mc_info_init(struct radeon_device
*rdev)
#if defined(CONFIG_DEBUG_FS)
struct dentry *root = rdev->ddev->primary->debugfs_root;
+ if (!root)
+ return;
+
debugfs_create_file("r100_mc_info", 0444, root, rdev,
_debugfs_mc_info_fops);
#endif
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 621ff174dff3..b22969e2394f 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -618,6 +618,9 @@ static void rv370_debugfs_pcie_gart_info_init(struct
radeon_device *rdev)
#if defined(CONFIG_DEBUG_FS)
struct dentry *root = rdev->ddev->primary->debugfs_root;
+ if (!root)
+ return;
+
debugfs_create_file("rv370_pcie_gart_info", 0444, root, rdev,
_debugfs_pcie_gart_info_fops);
#endif
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 7e6320e8c6a0..cdb4ac3e346b 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -494,6 +494,9 @@ void r420_debugfs_pipes_info_init(struct radeon_device
*rdev)
#if defined(CONFIG_DEBUG_FS)
struct dentry *root = rdev->ddev->primary->debugfs_root;
+ if (!root)
+ return;
+
debugfs_create_file("r420_pipes_info", 0444, root, rdev,
_debugfs_pipes_info_fops);
#endif
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index ca3fcae2adb5..d8f525cf0c3b 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -4360,6 +4360,9 @@ static void r600_debugfs_mc_info_init(struct
radeon_device *rdev)
#if defined(CONFIG_DEBUG_FS)
struct dentry *root = rdev->ddev->primary->debugfs_root;
+ if (!root)
+ return;
+
debugfs_create_file("r600_mc_info", 0444, root, rdev,
_debugfs_mc_info_fops);
diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c
b/drivers/gpu/drm/radeon/radeon_dp_mst.c
index ec867fa880a4..cf06da89bb7c 100644
--- a/drivers/gpu/drm/radeon/radeon_dp_mst.c
+++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c
@@ -771,6 +771,9 @@ void radeon_mst_debugfs_init(struct radeon_device *rdev)
#if defined(CONFIG_DEBUG_FS)
struct dentry *root = rdev->ddev->primary->debugfs_root;
+ if (!root)
+ return;
+
debugfs_create_file("radeon_mst_info", 0444, root, rdev,
_debugfs_mst_info_fops);
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c
b/drivers/gpu/drm/radeon/radeon_fence.c
index 73e3117420bf..11f30349de46 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -1006,6 +1006,9 @@ void radeon_debugfs_fence_init(struct radeon_device *rdev)
#if defined(CONFIG_DEBUG_FS)
struct dentry *root = rdev->ddev->primary->debugfs_root;
+ if (!root)
+ return;
+
debugfs_create_file("radeon_gpu_reset", 0444, root, rdev,
Re: [Intel-gfx] [PATCH] dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion
Am 08.10.21 um 11:50 schrieb Tvrtko Ursulin:
From: Tvrtko Ursulin
Cache the count of shared fences in the iterator to avoid dereferencing
the dma_resv_object outside the RCU protection. Otherwise iterator and its
users can observe an incosistent state which makes it impossible to use
safely.
Ah, of course! I've been staring at the code the whole morning and
couldn't see it.
Going to write a testcase to cover that.
Such as:
<6> [187.517041] [IGT] gem_sync: executing
<7> [187.536343] i915 :00:02.0: [drm:i915_gem_context_create_ioctl [i915]]
HW context 1 created
<7> [187.536793] i915 :00:02.0: [drm:i915_gem_context_create_ioctl [i915]]
HW context 1 created
<6> [187.551235] [IGT] gem_sync: starting subtest basic-many-each
<1> [188.935462] BUG: kernel NULL pointer dereference, address: 0010
<1> [188.935485] #PF: supervisor write access in kernel mode
<1> [188.935495] #PF: error_code(0x0002) - not-present page
<6> [188.935504] PGD 0 P4D 0
<4> [188.935512] Oops: 0002 [#1] PREEMPT SMP NOPTI
<4> [188.935521] CPU: 2 PID: 1467 Comm: gem_sync Not tainted
5.15.0-rc4-CI-Patchwork_21264+ #1
<4> [188.935535] Hardware name: /NUC6CAYB, BIOS
AYAPLCEL.86A.0049.2018.0508.1356 05/08/2018
<4> [188.935546] RIP: 0010:dma_resv_get_fences+0x116/0x2d0
<4> [188.935560] Code: 10 85 c0 7f c9 be 03 00 00 00 e8 15 8b df ff eb bd e8 8e c6 ff
ff eb b6 41 8b 04 24 49 8b 55 00 48 89 e7 8d 48 01 41 89 0c 24 <4c> 89 34 c2 e8 41 f2
ff ff 49 89 c6 48 85 c0 75 8c 48 8b 44 24 10
<4> [188.935583] RSP: 0018:c900011dbcc8 EFLAGS: 00010202
<4> [188.935593] RAX: RBX: RCX:
0001
<4> [188.935603] RDX: 0010 RSI: 822e343c RDI:
c900011dbcc8
<4> [188.935613] RBP: c900011dbd48 R08: 88812d255bb8 R09:
fffe
<4> [188.935623] R10: 0001 R11: R12:
c900011dbd44
<4> [188.935633] R13: c900011dbd50 R14: 888113d29cc0 R15:
<4> [188.935643] FS: 7f68d17e9700() GS:88827790()
knlGS:
<4> [188.935655] CS: 0010 DS: ES: CR0: 80050033
<4> [188.935665] CR2: 0010 CR3: 00012d0a4000 CR4:
003506e0
<4> [188.935676] Call Trace:
<4> [188.935685] i915_gem_object_wait+0x1ff/0x410 [i915]
<4> [188.935988] i915_gem_wait_ioctl+0xf2/0x2a0 [i915]
<4> [188.936272] ? i915_gem_object_wait+0x410/0x410 [i915]
<4> [188.936533] drm_ioctl_kernel+0xae/0x140
<4> [188.936546] drm_ioctl+0x201/0x3d0
<4> [188.936555] ? i915_gem_object_wait+0x410/0x410 [i915]
<4> [188.936820] ? __fget_files+0xc2/0x1c0
<4> [188.936830] ? __fget_files+0xda/0x1c0
<4> [188.936839] __x64_sys_ioctl+0x6d/0xa0
<4> [188.936848] do_syscall_64+0x3a/0xb0
<4> [188.936859] entry_SYSCALL_64_after_hwframe+0x44/0xae
If the shared object has changed during the RCU unlocked period
callers will correctly handle the restart on the next iteration.
Signed-off-by: Tvrtko Ursulin
Fixes: 96601e8a4755 ("dma-buf: use new iterator in dma_resv_copy_fences")
Fixes: d3c80698c9f5 ("dma-buf: use new iterator in dma_resv_get_fences v3")
Closes:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Fintel%2F-%2Fissues%2F4274data=04%7C01%7Cchristian.koenig%40amd.com%7C0a73b5d07f5f44cdc5a808d98a4109f9%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637692834972816537%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C2000sdata=jhcO2Q8bGhLTW7b4%2BNn4TE3UCwBbAcQVuceJEwDK0fg%3Dreserved=0
Cc: Christian König
Cc: Daniel Vetter
Cc: Sumit Semwal
Cc: linux-me...@vger.kernel.org
Cc: dri-de...@lists.freedesktop.org
Cc: linaro-mm-...@lists.linaro.org
Maybe we should remove cursor->fences altogether, but either way the
patch is Reviewed-by: Christian König
Please push to drm-misc-next ASAP.
Thanks,
Christian.
---
drivers/dma-buf/dma-resv.c | 18 ++
include/linux/dma-resv.h | 5 -
2 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c
index a480af9581bd..7b6d881c8904 100644
--- a/drivers/dma-buf/dma-resv.c
+++ b/drivers/dma-buf/dma-resv.c
@@ -333,10 +333,14 @@ static void dma_resv_iter_restart_unlocked(struct
dma_resv_iter *cursor)
{
cursor->seq = read_seqcount_begin(>obj->seq);
cursor->index = -1;
- if (cursor->all_fences)
+ cursor->shared_count = 0;
+ if (cursor->all_fences) {
cursor->fences = dma_resv_shared_list(cursor->obj);
- else
+ if (cursor->fences)
+ cursor->shared_count = cursor->fences->shared_count;
+ } else {
cursor->fences = NULL;
+ }
cursor->is_restarted = true;
}
@@ -363,7 +367,7 @@ static void dma_resv_iter_walk_unlocked(struct dma_resv_iter *cursor)
continue;
} else if (!cursor->fences ||
-
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] dri: cleanup debugfs error handling
== Series Details == Series: series starting with [1/5] dri: cleanup debugfs error handling URL : https://patchwork.freedesktop.org/series/95602/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/drm_drv.c:421:6: warning: context imbalance in 'drm_dev_enter' - different lock contexts for basic block +./include/linux/seqlock.h:840:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:840:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:866:16: warning: trying to copy expression type 31 +./include/linux/srcu.h:188:9: warning: context imbalance in 'drm_dev_exit' - unexpected unlock
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] dri: cleanup debugfs error handling
== Series Details == Series: series starting with [1/5] dri: cleanup debugfs error handling URL : https://patchwork.freedesktop.org/series/95602/ State : warning == Summary == $ dim checkpatch origin/drm-tip 59b65376d0a0 dri: cleanup debugfs error handling -:40: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #40: FILE: drivers/gpu/drm/drm_debugfs.c:210: +void drm_debugfs_init(struct drm_minor *minor, int minor_id, struct dentry *root) -:56: CHECK:LINE_SPACING: Please don't use multiple blank lines #56: FILE: drivers/gpu/drm/drm_debugfs.c:227: + + -:148: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #148: FILE: drivers/gpu/drm/drm_internal.h:195: +static inline void drm_debugfs_init(struct drm_minor *minor, int minor_id, struct dentry *root) total: 0 errors, 0 warnings, 3 checks, 112 lines checked 0ba632f15232 drm/i915: check dri root before debugfs init 348cf9dba853 drm/radeon: check dri root before debugfs init 55b24b7a29aa drm/armada: check dri/crtc root before debugfs init 6f112fc8a5fd drm/tegra: check root dentry before debugfs init
[Intel-gfx] [PATCH 6/6] drm/i915: Use irq work for coalescing-only dma-fence-work
We are using a timeline-attached struct dma_fence_work to coalesce
dma-fences on eviction. In this mode we will not have a work callback
attached.
Similar to how the dma-fence-chain and dma-fence-array containers do this,
use irq work to signal to reduce latency.
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/i915/i915_sw_fence_work.c | 36 ++-
drivers/gpu/drm/i915/i915_sw_fence_work.h | 2 ++
2 files changed, 31 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_sw_fence_work.c
b/drivers/gpu/drm/i915/i915_sw_fence_work.c
index 87cdb3158042..4573f537ada4 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence_work.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence_work.c
@@ -32,16 +32,17 @@ void dma_fence_work_timeline_attach(struct
dma_fence_work_timeline *tl,
{
struct dma_fence *await;
+ might_sleep();
if (tl->ops->get)
tl->ops->get(tl);
- spin_lock(>lock);
+ spin_lock_irq(>lock);
await = tl->last_fence;
tl->last_fence = dma_fence_get(>dma);
f->dma.seqno = tl->seqno++;
f->dma.context = tl->context;
f->tl = tl;
- spin_unlock(>lock);
+ spin_unlock_irq(>lock);
if (await) {
__i915_sw_fence_await_dma_fence(>chain, await, tl_cb);
@@ -53,13 +54,14 @@ static void dma_fence_work_timeline_detach(struct
dma_fence_work *f)
{
struct dma_fence_work_timeline *tl = f->tl;
bool put = false;
+ unsigned long irq_flags;
- spin_lock(>lock);
+ spin_lock_irqsave(>lock, irq_flags);
if (tl->last_fence == >dma) {
put = true;
tl->last_fence = NULL;
}
- spin_unlock(>lock);
+ spin_unlock_irqrestore(>lock, irq_flags);
if (tl->ops->put)
tl->ops->put(tl);
if (put)
@@ -68,8 +70,6 @@ static void dma_fence_work_timeline_detach(struct
dma_fence_work *f)
static void dma_fence_work_complete(struct dma_fence_work *f)
{
- dma_fence_signal(>dma);
-
if (f->ops->release)
f->ops->release(f);
@@ -79,13 +79,32 @@ static void dma_fence_work_complete(struct dma_fence_work
*f)
dma_fence_put(>dma);
}
+static void dma_fence_work_irq_work(struct irq_work *irq_work)
+{
+ struct dma_fence_work *f = container_of(irq_work, typeof(*f), irq_work);
+
+ dma_fence_signal(>dma);
+ if (f->ops->release)
+ /* Note we take the signaled path in dma_fence_work_work() */
+ queue_work(system_unbound_wq, >work);
+ else
+ dma_fence_work_complete(f);
+}
+
static void dma_fence_work_work(struct work_struct *work)
{
struct dma_fence_work *f = container_of(work, typeof(*f), work);
+ if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >dma.flags)) {
+ dma_fence_work_complete(f);
+ return;
+ }
+
if (f->ops->work)
f->ops->work(f);
+ dma_fence_signal(>dma);
+
dma_fence_work_complete(f);
}
@@ -102,8 +121,10 @@ fence_notify(struct i915_sw_fence *fence, enum
i915_sw_fence_notify state)
dma_fence_get(>dma);
if (test_bit(DMA_FENCE_WORK_IMM, >dma.flags))
dma_fence_work_work(>work);
- else
+ else if (f->ops->work)
queue_work(system_unbound_wq, >work);
+ else
+ irq_work_queue(>irq_work);
break;
case FENCE_FREE:
@@ -155,6 +176,7 @@ void dma_fence_work_init(struct dma_fence_work *f,
dma_fence_init(>dma, _ops, >lock, 0, 0);
i915_sw_fence_init(>chain, fence_notify);
INIT_WORK(>work, dma_fence_work_work);
+ init_irq_work(>irq_work, dma_fence_work_irq_work);
}
int dma_fence_work_chain(struct dma_fence_work *f, struct dma_fence *signal)
diff --git a/drivers/gpu/drm/i915/i915_sw_fence_work.h
b/drivers/gpu/drm/i915/i915_sw_fence_work.h
index 6f41ee360133..c412bb4cb288 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence_work.h
+++ b/drivers/gpu/drm/i915/i915_sw_fence_work.h
@@ -8,6 +8,7 @@
#define I915_SW_FENCE_WORK_H
#include
+#include
#include
#include
@@ -77,6 +78,7 @@ struct dma_fence_work {
struct i915_sw_dma_fence_cb cb;
struct work_struct work;
+ struct irq_work irq_work;
struct dma_fence_work_timeline *tl;
--
2.31.1
[Intel-gfx] [PATCH 3/6] drm/i915/ttm: Failsafe migration blits
If the initial fill blit or copy blit of an object fails, the old
content of the data might be exposed and read as soon as either CPU- or
GPU PTEs are set up to point at the pages.
Intercept the blit fence with an async dma_fence_work that checks the
blit fence for errors and if there are errors performs an async cpu blit
instead. If there is a failure to allocate the async dma_fence_work,
allocate it on the stack and sync wait for the blit to complete.
Add selftests that simulate gpu blit failures and failure to allocate
the async dma_fence_work.
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 268 ++
drivers/gpu/drm/i915/gem/i915_gem_ttm.h | 4 +
.../drm/i915/gem/selftests/i915_gem_migrate.c | 24 +-
3 files changed, 240 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 4b4d7457bef9..79d4d50aa4e5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -7,6 +7,7 @@
#include
#include "i915_drv.h"
+#include "i915_sw_fence_work.h"
#include "intel_memory_region.h"
#include "intel_region_ttm.h"
@@ -25,6 +26,18 @@
#define I915_TTM_PRIO_NO_PAGES 1
#define I915_TTM_PRIO_HAS_PAGES 2
+I915_SELFTEST_DECLARE(static bool fail_gpu_migration;)
+I915_SELFTEST_DECLARE(static bool fail_work_allocation;)
+
+#ifdef CONFIG_DRM_I915_SELFTEST
+void i915_ttm_migrate_set_failure_modes(bool gpu_migration,
+ bool work_allocation)
+{
+ fail_gpu_migration = gpu_migration;
+ fail_work_allocation = work_allocation;
+}
+#endif
+
/*
* Size of struct ttm_place vector in on-stack struct ttm_placement allocs
*/
@@ -466,11 +479,11 @@ i915_ttm_resource_get_st(struct drm_i915_gem_object *obj,
return intel_region_ttm_resource_to_rsgt(obj->mm.region, res);
}
-static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
- bool clear,
- struct ttm_resource *dst_mem,
- struct ttm_tt *dst_ttm,
- struct sg_table *dst_st)
+static struct dma_fence *i915_ttm_accel_move(struct ttm_buffer_object *bo,
+bool clear,
+struct ttm_resource *dst_mem,
+struct ttm_tt *dst_ttm,
+struct sg_table *dst_st)
{
struct drm_i915_private *i915 = container_of(bo->bdev, typeof(*i915),
bdev);
@@ -481,30 +494,29 @@ static int i915_ttm_accel_move(struct ttm_buffer_object
*bo,
int ret;
if (!i915->gt.migrate.context || intel_gt_is_wedged(>gt))
- return -EINVAL;
+ return ERR_PTR(-EINVAL);
+
+ /* With fail_gpu_migration, we always perform a GPU clear. */
+ if (I915_SELFTEST_ONLY(fail_gpu_migration))
+ clear = true;
dst_level = i915_ttm_cache_level(i915, dst_mem, dst_ttm);
if (clear) {
- if (bo->type == ttm_bo_type_kernel)
- return -EINVAL;
+ if (bo->type == ttm_bo_type_kernel &&
+ !I915_SELFTEST_ONLY(fail_gpu_migration))
+ return ERR_PTR(-EINVAL);
intel_engine_pm_get(i915->gt.migrate.context->engine);
ret = intel_context_migrate_clear(i915->gt.migrate.context,
NULL,
dst_st->sgl, dst_level,
gpu_binds_iomem(dst_mem),
0, );
-
- if (!ret && rq) {
- i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT);
- i915_request_put(rq);
- }
- intel_engine_pm_put(i915->gt.migrate.context->engine);
} else {
struct i915_refct_sgt *src_rsgt =
i915_ttm_resource_get_st(obj, bo->resource);
if (IS_ERR(src_rsgt))
- return PTR_ERR(src_rsgt);
+ return ERR_CAST(src_rsgt);
src_level = i915_ttm_cache_level(i915, bo->resource, src_ttm);
intel_engine_pm_get(i915->gt.migrate.context->engine);
@@ -515,55 +527,201 @@ static int i915_ttm_accel_move(struct ttm_buffer_object
*bo,
dst_st->sgl, dst_level,
gpu_binds_iomem(dst_mem),
);
+
i915_refct_sgt_put(src_rsgt);
- if (!ret && rq) {
- i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT);
- i915_request_put(rq);
- }
-
[Intel-gfx] [PATCH 5/6] drm/i915/ttm: Attach the migration fence to a region timeline on eviction
On eviction, TTM requires that migration fences from the same region are
ordered using dma_fence_is_later(). For request-based fences we therefore
need to use the same context for the migration, but now that we use a
dma_fence_work for error recovery, and, in addition, might need to coalesce
the migration fence with async unbind fences, Create a coalesce fence for
this.
Chain the coalesce fence on the migration fence and attach it to a region
timeline.
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c| 84 ++
drivers/gpu/drm/i915/intel_memory_region.c | 43 +++
drivers/gpu/drm/i915/intel_memory_region.h | 7 ++
3 files changed, 119 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 79d4d50aa4e5..625ce52e8662 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -672,9 +672,10 @@ static void __i915_ttm_move_fallback(struct
ttm_buffer_object *bo, bool clear,
}
}
-static int __i915_ttm_move(struct ttm_buffer_object *bo, bool clear,
- struct ttm_resource *dst_mem, struct ttm_tt *dst_ttm,
- struct i915_refct_sgt *dst_rsgt, bool allow_accel)
+static struct dma_fence *
+__i915_ttm_move(struct ttm_buffer_object *bo, bool clear,
+ struct ttm_resource *dst_mem, struct ttm_tt *dst_ttm,
+ struct i915_refct_sgt *dst_rsgt, bool allow_accel)
{
struct i915_ttm_memcpy_work *copy_work;
struct dma_fence *fence;
@@ -689,7 +690,7 @@ static int __i915_ttm_move(struct ttm_buffer_object *bo,
bool clear,
/* Don't fail with -ENOMEM. Move sync instead. */
__i915_ttm_move_fallback(bo, clear, dst_mem, dst_ttm, dst_rsgt,
allow_accel);
- return 0;
+ return NULL;
}
dma_fence_work_init(_work->base, _ttm_memcpy_ops);
@@ -714,14 +715,45 @@ static int __i915_ttm_move(struct ttm_buffer_object *bo,
bool clear,
fence = dma_fence_get(_work->base.dma);
dma_fence_work_commit_imm(_work->base);
- /*
-* We're synchronizing here for now. For async moves, return the
-* fence.
-*/
- dma_fence_wait(fence, false);
- dma_fence_put(fence);
+ return fence;
+}
- return ret;
+/**
+ * struct i915_coalesce_fence - A dma-fence used to coalesce multiple fences
+ * similar to struct dm_fence_array, and at the same time being timeline-
+ * attached.
+ * @base: struct dma_fence_work base.
+ * @cb: Callback for timeline attachment.
+ */
+struct i915_coalesce_fence {
+ struct dma_fence_work base;
+ struct i915_sw_dma_fence_cb cb;
+};
+
+/* No .work or .release callback. Just coalescing. */
+static const struct dma_fence_work_ops i915_coalesce_fence_ops = {
+ .name = "Coalesce fence",
+};
+
+static struct dma_fence *
+i915_ttm_coalesce_fence(struct dma_fence *fence, struct intel_memory_region
*mr)
+{
+ struct i915_coalesce_fence *coalesce =
+ kmalloc(sizeof(*coalesce), GFP_KERNEL);
+
+ if (!coalesce) {
+ dma_fence_wait(fence, false);
+ dma_fence_put(fence);
+ return NULL;
+ }
+
+ dma_fence_work_init(>base, _coalesce_fence_ops);
+ dma_fence_work_chain(>base, fence);
+ dma_fence_work_timeline_attach(>tl, >base, >cb);
+ dma_fence_get(>base.dma);
+ dma_fence_work_commit_imm(>base);
+ dma_fence_put(fence);
+ return >base.dma;
}
static int i915_ttm_move(struct ttm_buffer_object *bo, bool evict,
@@ -734,6 +766,7 @@ static int i915_ttm_move(struct ttm_buffer_object *bo, bool
evict,
ttm_manager_type(bo->bdev, dst_mem->mem_type);
struct ttm_tt *ttm = bo->ttm;
struct i915_refct_sgt *dst_rsgt;
+ struct dma_fence *fence = NULL;
bool clear;
int ret;
@@ -765,7 +798,23 @@ static int i915_ttm_move(struct ttm_buffer_object *bo,
bool evict,
clear = !cpu_maps_iomem(bo->resource) && (!ttm ||
!ttm_tt_is_populated(ttm));
if (!(clear && ttm && !(ttm->page_flags & TTM_TT_FLAG_ZERO_ALLOC)))
- __i915_ttm_move(bo, clear, dst_mem, bo->ttm, dst_rsgt, true);
+ fence = __i915_ttm_move(bo, clear, dst_mem, bo->ttm, dst_rsgt,
true);
+ if (fence && evict) {
+ struct intel_memory_region *mr =
+ i915_ttm_region(bo->bdev, bo->resource->mem_type);
+
+ /*
+* Attach to the region timeline and for future async unbind,
+* which requires a timeline. Also future async unbind fences
+* can be attached here.
+*/
+ fence = i915_ttm_coalesce_fence(fence, mr);
+ }
+
+ if (fence) {
+ dma_fence_wait(fence, false);
+
[Intel-gfx] [PATCH 4/6] drm/i915: Add a struct dma_fence_work timeline
The TTM managers and, possibly, the gtt address space managers will
need to be able to order fences for async operation.
Using dma_fence_is_later() for this will require that the fences we hand
them are from a single fence context and ordered.
Introduce a struct dma_fence_work_timeline, and a function to attach
struct dma_fence_work to such a timeline in a way that all previous
fences attached to the timeline will be signaled when the latest
attached struct dma_fence_work signals.
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/i915/i915_sw_fence_work.c | 89 ++-
drivers/gpu/drm/i915/i915_sw_fence_work.h | 58 +++
2 files changed, 145 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_sw_fence_work.c
b/drivers/gpu/drm/i915/i915_sw_fence_work.c
index 5b55cddafc9b..87cdb3158042 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence_work.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence_work.c
@@ -5,6 +5,66 @@
*/
#include "i915_sw_fence_work.h"
+#include "i915_utils.h"
+
+/**
+ * dma_fence_work_timeline_attach - Attach a struct dma_fence_work to a
+ * timeline.
+ * @tl: The timeline to attach to.
+ * @f: The struct dma_fence_work.
+ * @tl_cb: The i915_sw_dma_fence_cb needed to attach to the
+ * timeline. This is typically embedded into the structure that also
+ * embeds the struct dma_fence_work.
+ *
+ * This function takes a timeline reference and associates it with the
+ * struct dma_fence_work. That reference is given up when the fence
+ * signals. Furthermore it assigns a fence context and a seqno to the
+ * dma-fence, and then chains upon the previous fence of the timeline
+ * if any, to make sure that the fence signals after that fence. The
+ * @tl_cb callback structure is needed for that chaining. Finally
+ * the registered last fence of the timeline is replaced by this fence, and
+ * the timeline takes a reference on the fence, which is released when
+ * the fence signals.
+ */
+void dma_fence_work_timeline_attach(struct dma_fence_work_timeline *tl,
+ struct dma_fence_work *f,
+ struct i915_sw_dma_fence_cb *tl_cb)
+{
+ struct dma_fence *await;
+
+ if (tl->ops->get)
+ tl->ops->get(tl);
+
+ spin_lock(>lock);
+ await = tl->last_fence;
+ tl->last_fence = dma_fence_get(>dma);
+ f->dma.seqno = tl->seqno++;
+ f->dma.context = tl->context;
+ f->tl = tl;
+ spin_unlock(>lock);
+
+ if (await) {
+ __i915_sw_fence_await_dma_fence(>chain, await, tl_cb);
+ dma_fence_put(await);
+ }
+}
+
+static void dma_fence_work_timeline_detach(struct dma_fence_work *f)
+{
+ struct dma_fence_work_timeline *tl = f->tl;
+ bool put = false;
+
+ spin_lock(>lock);
+ if (tl->last_fence == >dma) {
+ put = true;
+ tl->last_fence = NULL;
+ }
+ spin_unlock(>lock);
+ if (tl->ops->put)
+ tl->ops->put(tl);
+ if (put)
+ dma_fence_put(>dma);
+}
static void dma_fence_work_complete(struct dma_fence_work *f)
{
@@ -13,6 +73,9 @@ static void dma_fence_work_complete(struct dma_fence_work *f)
if (f->ops->release)
f->ops->release(f);
+ if (f->tl)
+ dma_fence_work_timeline_detach(f);
+
dma_fence_put(>dma);
}
@@ -53,14 +116,17 @@ fence_notify(struct i915_sw_fence *fence, enum
i915_sw_fence_notify state)
static const char *get_driver_name(struct dma_fence *fence)
{
- return "dma-fence";
+ struct dma_fence_work *f = container_of(fence, typeof(*f), dma);
+
+ return (f->tl && f->tl->ops->name) ? f->tl->ops->name : "dma-fence";
}
static const char *get_timeline_name(struct dma_fence *fence)
{
struct dma_fence_work *f = container_of(fence, typeof(*f), dma);
- return f->ops->name ?: "work";
+ return (f->tl && f->tl->name) ? f->tl->name :
+ f->ops->name ?: "work";
}
static void fence_release(struct dma_fence *fence)
@@ -84,6 +150,7 @@ void dma_fence_work_init(struct dma_fence_work *f,
{
f->ops = ops;
f->error = 0;
+ f->tl = NULL;
spin_lock_init(>lock);
dma_fence_init(>dma, _ops, >lock, 0, 0);
i915_sw_fence_init(>chain, fence_notify);
@@ -97,3 +164,21 @@ int dma_fence_work_chain(struct dma_fence_work *f, struct
dma_fence *signal)
return __i915_sw_fence_await_dma_fence(>chain, signal, >cb);
}
+
+/**
+ * dma_fence_work_timeline_init - Initialize a dma_fence_work timeline
+ * @tl: The timeline to initialize,
+ * @name: The name of the timeline,
+ * @ops: The timeline operations.
+ */
+void dma_fence_work_timeline_init(struct dma_fence_work_timeline *tl,
+ const char *name,
+ const struct dma_fence_work_timeline_ops *ops)
+{
+ tl->name = name;
+ spin_lock_init(>lock);
+
[Intel-gfx] [PATCH 2/6] drm/i915: Introduce refcounted sg-tables
As we start to introduce asynchronous failsafe object migration,
where we update the object state and then submit asynchronous
commands we need to record what memory resources are actually used
by various part of the command stream. Initially for three purposes:
1) Error capture.
2) Asynchronous migration error recovery.
3) Asynchronous vma bind.
At the time where these happens, the object state may have been updated
to be several migrations ahead and object sg-tables discarded.
In order to make it possible to keep sg-tables with memory resource
information for these operations, introduce refcounted sg-tables that
aren't freed until the last user is done with them.
The alternative would be to reference information sitting on the
corresponding ttm_resources which typically have the same lifetime as
these refcountes sg_tables, but that leads to other awkward constructs:
Due to the design direction chosen for ttm resource managers that would
lead to diamond-style inheritance, the LMEM resources may sometimes be
prematurely freed, and finally the subclassed struct ttm_resource would
have to bleed into the asynchronous vma bind code.
Signed-off-by: Thomas Hellström
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 159 +++---
drivers/gpu/drm/i915/i915_scatterlist.c | 62 +--
drivers/gpu/drm/i915/i915_scatterlist.h | 76 -
drivers/gpu/drm/i915/intel_region_ttm.c | 15 +-
drivers/gpu/drm/i915/intel_region_ttm.h | 5 +-
drivers/gpu/drm/i915/selftests/mock_region.c | 12 +-
7 files changed, 238 insertions(+), 94 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 7c3da4e3e737..d600cf7ceb35 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -485,6 +485,7 @@ struct drm_i915_gem_object {
*/
struct list_head region_link;
+ struct i915_refct_sgt *rsgt;
struct sg_table *pages;
void *mapping;
@@ -538,7 +539,7 @@ struct drm_i915_gem_object {
} mm;
struct {
- struct sg_table *cached_io_st;
+ struct i915_refct_sgt *cached_io_rsgt;
struct i915_gem_object_page_iter get_io_page;
struct drm_i915_gem_object *backup;
bool created:1;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 74a1ffd0d7dd..4b4d7457bef9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -34,7 +34,7 @@
* struct i915_ttm_tt - TTM page vector with additional private information
* @ttm: The base TTM page vector.
* @dev: The struct device used for dma mapping and unmapping.
- * @cached_st: The cached scatter-gather table.
+ * @cached_rsgt: The cached scatter-gather table.
*
* Note that DMA may be going on right up to the point where the page-
* vector is unpopulated in delayed destroy. Hence keep the
@@ -45,7 +45,7 @@
struct i915_ttm_tt {
struct ttm_tt ttm;
struct device *dev;
- struct sg_table *cached_st;
+ struct i915_refct_sgt cached_rsgt;
};
static const struct ttm_place sys_placement_flags = {
@@ -179,6 +179,21 @@ i915_ttm_placement_from_obj(const struct
drm_i915_gem_object *obj,
placement->busy_placement = busy;
}
+static void i915_ttm_tt_release(struct kref *ref)
+{
+ struct i915_ttm_tt *i915_tt =
+ container_of(ref, typeof(*i915_tt), cached_rsgt.kref);
+ struct sg_table *st = _tt->cached_rsgt.table;
+
+ GEM_WARN_ON(st->sgl);
+
+ kfree(i915_tt);
+}
+
+static const struct i915_refct_sgt_ops tt_rsgt_ops = {
+ .release = i915_ttm_tt_release
+};
+
static struct ttm_tt *i915_ttm_tt_create(struct ttm_buffer_object *bo,
uint32_t page_flags)
{
@@ -203,6 +218,8 @@ static struct ttm_tt *i915_ttm_tt_create(struct
ttm_buffer_object *bo,
return NULL;
}
+ i915_refct_sgt_init_ops(_tt->cached_rsgt, bo->base.size,
+ _rsgt_ops);
i915_tt->dev = obj->base.dev->dev;
return _tt->ttm;
@@ -211,13 +228,13 @@ static struct ttm_tt *i915_ttm_tt_create(struct
ttm_buffer_object *bo,
static void i915_ttm_tt_unpopulate(struct ttm_device *bdev, struct ttm_tt *ttm)
{
struct i915_ttm_tt *i915_tt = container_of(ttm, typeof(*i915_tt), ttm);
+ struct sg_table *st = _tt->cached_rsgt.table;
+
+ GEM_WARN_ON(kref_read(_tt->cached_rsgt.kref) != 1);
- if (i915_tt->cached_st) {
- dma_unmap_sgtable(i915_tt->dev, i915_tt->cached_st,
- DMA_BIDIRECTIONAL, 0);
- sg_free_table(i915_tt->cached_st);
- kfree(i915_tt->cached_st);
-
[Intel-gfx] [PATCH 1/6] drm/i915: Update dma_fence_work
Move the release callback to after fence signaling to align with
what's done for upcoming VM_BIND user-fence signaling.
Finally call the work callback regardless of whether we have a fence
error or not and update the existing callbacks accordingly. We will
need this to intercept the error for failsafe migration.
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 5 +++
drivers/gpu/drm/i915/i915_sw_fence_work.c | 36 ++---
drivers/gpu/drm/i915/i915_sw_fence_work.h | 1 +
drivers/gpu/drm/i915/i915_vma.c | 12 +--
4 files changed, 33 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
index f0435c6feb68..2143ebaf5b6f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
@@ -28,6 +28,11 @@ static void clflush_work(struct dma_fence_work *base)
{
struct clflush *clflush = container_of(base, typeof(*clflush), base);
+ if (base->error) {
+ dma_fence_set_error(>dma, base->error);
+ return;
+ }
+
__do_clflush(clflush->obj);
}
diff --git a/drivers/gpu/drm/i915/i915_sw_fence_work.c
b/drivers/gpu/drm/i915/i915_sw_fence_work.c
index 5b33ef23d54c..5b55cddafc9b 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence_work.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence_work.c
@@ -6,21 +6,24 @@
#include "i915_sw_fence_work.h"
-static void fence_complete(struct dma_fence_work *f)
+static void dma_fence_work_complete(struct dma_fence_work *f)
{
+ dma_fence_signal(>dma);
+
if (f->ops->release)
f->ops->release(f);
- dma_fence_signal(>dma);
+
+ dma_fence_put(>dma);
}
-static void fence_work(struct work_struct *work)
+static void dma_fence_work_work(struct work_struct *work)
{
struct dma_fence_work *f = container_of(work, typeof(*f), work);
- f->ops->work(f);
+ if (f->ops->work)
+ f->ops->work(f);
- fence_complete(f);
- dma_fence_put(>dma);
+ dma_fence_work_complete(f);
}
static int __i915_sw_fence_call
@@ -31,17 +34,13 @@ fence_notify(struct i915_sw_fence *fence, enum
i915_sw_fence_notify state)
switch (state) {
case FENCE_COMPLETE:
if (fence->error)
- dma_fence_set_error(>dma, fence->error);
-
- if (!f->dma.error) {
- dma_fence_get(>dma);
- if (test_bit(DMA_FENCE_WORK_IMM, >dma.flags))
- fence_work(>work);
- else
- queue_work(system_unbound_wq, >work);
- } else {
- fence_complete(f);
- }
+ cmpxchg(>error, 0, fence->error);
+
+ dma_fence_get(>dma);
+ if (test_bit(DMA_FENCE_WORK_IMM, >dma.flags))
+ dma_fence_work_work(>work);
+ else
+ queue_work(system_unbound_wq, >work);
break;
case FENCE_FREE:
@@ -84,10 +83,11 @@ void dma_fence_work_init(struct dma_fence_work *f,
const struct dma_fence_work_ops *ops)
{
f->ops = ops;
+ f->error = 0;
spin_lock_init(>lock);
dma_fence_init(>dma, _ops, >lock, 0, 0);
i915_sw_fence_init(>chain, fence_notify);
- INIT_WORK(>work, fence_work);
+ INIT_WORK(>work, dma_fence_work_work);
}
int dma_fence_work_chain(struct dma_fence_work *f, struct dma_fence *signal)
diff --git a/drivers/gpu/drm/i915/i915_sw_fence_work.h
b/drivers/gpu/drm/i915/i915_sw_fence_work.h
index d56806918d13..caa59fb5252b 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence_work.h
+++ b/drivers/gpu/drm/i915/i915_sw_fence_work.h
@@ -24,6 +24,7 @@ struct dma_fence_work_ops {
struct dma_fence_work {
struct dma_fence dma;
spinlock_t lock;
+ int error;
struct i915_sw_fence chain;
struct i915_sw_dma_fence_cb cb;
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 4b7fc4647e46..5123ac28ad9a 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -301,6 +301,11 @@ static void __vma_bind(struct dma_fence_work *work)
struct i915_vma_work *vw = container_of(work, typeof(*vw), base);
struct i915_vma *vma = vw->vma;
+ if (work->error) {
+ dma_fence_set_error(>dma, work->error);
+ return;
+ }
+
vma->ops->bind_vma(vw->vm, >stash,
vma, vw->cache_level, vw->flags);
}
@@ -333,7 +338,7 @@ struct i915_vma_work *i915_vma_work(void)
return NULL;
dma_fence_work_init(>base, _ops);
- vw->base.dma.error = -EAGAIN; /* disable the worker by default */
+ vw->base.error = -EAGAIN; /* disable the worker by default */
[Intel-gfx] [PATCH 0/6] drm/i915: Failsafe migration blits
This patch series introduces failsafe migration blits. The reason for this seemingly strange concept is that if the initial clearing or readback of LMEM fails for some reason, and we then set up either GPU- or CPU ptes to the allocated LMEM, we can expose old contents from other clients. So after each migration blit we attach a struct dma-fence-work that checks the error value and if it's an error, perform a memcpy blit, instead. This comes with some needed infrastructure updates: Patch 1, updates dma_fence_work to do the work even if there is an error. The work callback needs to check for error and take action accordingly. Patch 2, Introduces refcounted sg-tables. The sg-tables are needed async for the memcpy. Patch 3, Introduces the failsafe migration blits and selftests. Patch 4, Adds the possibility to attach the struct dma_fence_work to a timeline. Patch 5, Attached the migration fence to a timeline since TTM requires that for upcoming async eviction. Patch 6 Adds an optimization for coalescing-only struct dma_fence_work. Worth to consider during review: Patch 4-6 are probably better done in the context of struct dma_fence_array. Both since we perhaps shouldn't add irq work to yet another fence data structure and also because the i915 command submission can individualize struct dma_fence_arrays. Also the memcpy solution here isn't a final one as it only works if the aperture covers all of lmem. We probably need to work on a solution where we intercept move_fence errors and refuse GPU- and CPU mappings. Thomas Hellström (6): drm/i915: Update dma_fence_work drm/i915: Introduce refcounted sg-tables drm/i915/ttm: Failsafe migration blits drm/i915: Add a struct dma_fence_work timeline drm/i915/ttm: Attach the migration fence to a region timeline on eviction drm/i915: Use irq work for coalescing-only dma-fence-work drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 5 + .../gpu/drm/i915/gem/i915_gem_object_types.h | 3 +- drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 467 ++ drivers/gpu/drm/i915/gem/i915_gem_ttm.h | 4 + .../drm/i915/gem/selftests/i915_gem_migrate.c | 24 +- drivers/gpu/drm/i915/i915_scatterlist.c | 62 ++- drivers/gpu/drm/i915/i915_scatterlist.h | 76 ++- drivers/gpu/drm/i915/i915_sw_fence_work.c | 145 +- drivers/gpu/drm/i915/i915_sw_fence_work.h | 61 +++ drivers/gpu/drm/i915/i915_vma.c | 12 +- drivers/gpu/drm/i915/intel_memory_region.c| 43 ++ drivers/gpu/drm/i915/intel_memory_region.h| 7 + drivers/gpu/drm/i915/intel_region_ttm.c | 15 +- drivers/gpu/drm/i915/intel_region_ttm.h | 5 +- drivers/gpu/drm/i915/selftests/mock_region.c | 12 +- 15 files changed, 776 insertions(+), 165 deletions(-) -- 2.31.1
[Intel-gfx] [PATCH 2/5] drm/i915: check dri root before debugfs init
Return early if dri minor root dentry is NULL.
CC: Zhenyu Wang
CC: Zhi Wang
CC: Jani Nikula
CC: Joonas Lahtinen
CC: Rodrigo Vivi
CC: David Airlie
CC: Daniel Vetter
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gvt/debugfs.c | 3 +++
drivers/gpu/drm/i915/i915_debugfs.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/gvt/debugfs.c
b/drivers/gpu/drm/i915/gvt/debugfs.c
index 9f1c209d9251..2d47acaa03ee 100644
--- a/drivers/gpu/drm/i915/gvt/debugfs.c
+++ b/drivers/gpu/drm/i915/gvt/debugfs.c
@@ -187,6 +187,9 @@ void intel_gvt_debugfs_init(struct intel_gvt *gvt)
{
struct drm_minor *minor = gvt->gt->i915->drm.primary;
+ if (!minor->debugfs_root)
+ return;
+
gvt->debugfs_root = debugfs_create_dir("gvt", minor->debugfs_root);
debugfs_create_ulong("num_tracked_mmio", 0444, gvt->debugfs_root,
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 44969f5dde50..d572b686edeb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1012,6 +1012,9 @@ void i915_debugfs_register(struct drm_i915_private
*dev_priv)
struct drm_minor *minor = dev_priv->drm.primary;
int i;
+ if (!minor->debugfs_root)
+ return;
+
i915_debugfs_params(dev_priv);
debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root,
--
2.32.0
[Intel-gfx] [PATCH 1/5] dri: cleanup debugfs error handling
Debugfs API returns encoded error instead of NULL.
This patch cleanups drm debugfs error handling to
properly set dri and its minor's root dentry to NULL.
Also do not error out if dri/minor debugfs directory
creation fails as a debugfs error is not a fatal error.
CC: Maarten Lankhorst
CC: Maxime Ripard
CC: Thomas Zimmermann
CC: David Airlie
CC: Daniel Vetter
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/drm_debugfs.c | 25 +++--
drivers/gpu/drm/drm_drv.c | 16 ++--
drivers/gpu/drm/drm_internal.h | 7 +++
3 files changed, 36 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c
index b0a826489488..af275a0c09b4 100644
--- a/drivers/gpu/drm/drm_debugfs.c
+++ b/drivers/gpu/drm/drm_debugfs.c
@@ -180,6 +180,9 @@ void drm_debugfs_create_files(const struct drm_info_list
*files, int count,
struct drm_info_node *tmp;
int i;
+ if (!minor->debugfs_root)
+ return;
+
for (i = 0; i < count; i++) {
u32 features = files[i].driver_features;
@@ -203,7 +206,7 @@ void drm_debugfs_create_files(const struct drm_info_list
*files, int count,
}
EXPORT_SYMBOL(drm_debugfs_create_files);
-int drm_debugfs_init(struct drm_minor *minor, int minor_id,
+void drm_debugfs_init(struct drm_minor *minor, int minor_id,
struct dentry *root)
{
struct drm_device *dev = minor->dev;
@@ -212,8 +215,16 @@ int drm_debugfs_init(struct drm_minor *minor, int minor_id,
INIT_LIST_HEAD(>debugfs_list);
mutex_init(>debugfs_lock);
sprintf(name, "%d", minor_id);
+
+ if (!root)
+ goto error;
+
minor->debugfs_root = debugfs_create_dir(name, root);
+ if (IS_ERR(minor->debugfs_root))
+ goto error;
+
+
drm_debugfs_create_files(drm_debugfs_list, DRM_DEBUGFS_ENTRIES,
minor->debugfs_root, minor);
@@ -230,7 +241,11 @@ int drm_debugfs_init(struct drm_minor *minor, int minor_id,
if (dev->driver->debugfs_init)
dev->driver->debugfs_init(minor);
- return 0;
+ return;
+
+error:
+ minor->debugfs_root = NULL;
+ return;
}
@@ -241,6 +256,9 @@ int drm_debugfs_remove_files(const struct drm_info_list
*files, int count,
struct drm_info_node *tmp;
int i;
+ if (!minor->debugfs_root)
+ return 0;
+
mutex_lock(>debugfs_lock);
for (i = 0; i < count; i++) {
list_for_each_safe(pos, q, >debugfs_list) {
@@ -261,6 +279,9 @@ static void drm_debugfs_remove_all_files(struct drm_minor
*minor)
{
struct drm_info_node *node, *tmp;
+ if (!minor->debugfs_root)
+ return;
+
mutex_lock(>debugfs_lock);
list_for_each_entry_safe(node, tmp, >debugfs_list, list) {
debugfs_remove(node->dent);
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 7a5097467ba5..fa57ec2d49bf 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -160,11 +160,7 @@ static int drm_minor_register(struct drm_device *dev,
unsigned int type)
if (!minor)
return 0;
- ret = drm_debugfs_init(minor, minor->index, drm_debugfs_root);
- if (ret) {
- DRM_ERROR("DRM: Failed to initialize /sys/kernel/debug/dri.\n");
- goto err_debugfs;
- }
+ drm_debugfs_init(minor, minor->index, drm_debugfs_root);
ret = device_add(minor->kdev);
if (ret)
@@ -1050,7 +1046,15 @@ static int __init drm_core_init(void)
goto error;
}
- drm_debugfs_root = debugfs_create_dir("dri", NULL);
+ if (!debugfs_initialized()) {
+ drm_debugfs_root = NULL;
+ } else {
+ drm_debugfs_root = debugfs_create_dir("dri", NULL);
+ if (IS_ERR(drm_debugfs_root)) {
+ DRM_WARN("DRM: Failed to initialize
/sys/kernel/debug/dri.\n");
+ drm_debugfs_root = NULL;
+ }
+ }
ret = register_chrdev(DRM_MAJOR, "drm", _stub_fops);
if (ret < 0)
diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h
index 17f3548c8ed2..e27a40166178 100644
--- a/drivers/gpu/drm/drm_internal.h
+++ b/drivers/gpu/drm/drm_internal.h
@@ -182,8 +182,8 @@ int drm_gem_dumb_destroy(struct drm_file *file, struct
drm_device *dev,
/* drm_debugfs.c drm_debugfs_crc.c */
#if defined(CONFIG_DEBUG_FS)
-int drm_debugfs_init(struct drm_minor *minor, int minor_id,
-struct dentry *root);
+void drm_debugfs_init(struct drm_minor *minor, int minor_id,
+ struct dentry *root);
void drm_debugfs_cleanup(struct drm_minor *minor);
void drm_debugfs_connector_add(struct drm_connector *connector);
void drm_debugfs_connector_remove(struct drm_connector *connector);
@@ -191,10 +191,9 @@ void
[Intel-gfx] [PATCH 3/5] drm/radeon: check dri root before debugfs init
Return early if dri minor root dentry is NULL.
CC: Alex Deucher
CC: "Christian König"
CC: "Pan, Xinhui"
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/radeon/r100.c | 9 +
drivers/gpu/drm/radeon/r300.c | 3 +++
drivers/gpu/drm/radeon/r420.c | 3 +++
drivers/gpu/drm/radeon/r600.c | 3 +++
drivers/gpu/drm/radeon/radeon_dp_mst.c | 3 +++
drivers/gpu/drm/radeon/radeon_fence.c | 3 +++
drivers/gpu/drm/radeon/radeon_gem.c| 3 +++
drivers/gpu/drm/radeon/radeon_ib.c | 3 +++
drivers/gpu/drm/radeon/radeon_pm.c | 5 -
drivers/gpu/drm/radeon/radeon_ring.c | 3 +++
drivers/gpu/drm/radeon/radeon_ttm.c| 3 +++
drivers/gpu/drm/radeon/rs400.c | 3 +++
drivers/gpu/drm/radeon/rv515.c | 3 +++
13 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 2dd85ba1faa2..ae6c95b34013 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -3059,6 +3059,9 @@ void r100_debugfs_rbbm_init(struct radeon_device *rdev)
#if defined(CONFIG_DEBUG_FS)
struct dentry *root = rdev->ddev->primary->debugfs_root;
+ if (!root)
+ return;
+
debugfs_create_file("r100_rbbm_info", 0444, root, rdev,
_debugfs_rbbm_info_fops);
#endif
@@ -3069,6 +3072,9 @@ void r100_debugfs_cp_init(struct radeon_device *rdev)
#if defined(CONFIG_DEBUG_FS)
struct dentry *root = rdev->ddev->primary->debugfs_root;
+ if (!root)
+ return;
+
debugfs_create_file("r100_cp_ring_info", 0444, root, rdev,
_debugfs_cp_ring_info_fops);
debugfs_create_file("r100_cp_csq_fifo", 0444, root, rdev,
@@ -3081,6 +3087,9 @@ void r100_debugfs_mc_info_init(struct radeon_device
*rdev)
#if defined(CONFIG_DEBUG_FS)
struct dentry *root = rdev->ddev->primary->debugfs_root;
+ if (!root)
+ return;
+
debugfs_create_file("r100_mc_info", 0444, root, rdev,
_debugfs_mc_info_fops);
#endif
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 621ff174dff3..b22969e2394f 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -618,6 +618,9 @@ static void rv370_debugfs_pcie_gart_info_init(struct
radeon_device *rdev)
#if defined(CONFIG_DEBUG_FS)
struct dentry *root = rdev->ddev->primary->debugfs_root;
+ if (!root)
+ return;
+
debugfs_create_file("rv370_pcie_gart_info", 0444, root, rdev,
_debugfs_pcie_gart_info_fops);
#endif
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 7e6320e8c6a0..cdb4ac3e346b 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -494,6 +494,9 @@ void r420_debugfs_pipes_info_init(struct radeon_device
*rdev)
#if defined(CONFIG_DEBUG_FS)
struct dentry *root = rdev->ddev->primary->debugfs_root;
+ if (!root)
+ return;
+
debugfs_create_file("r420_pipes_info", 0444, root, rdev,
_debugfs_pipes_info_fops);
#endif
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index ca3fcae2adb5..d8f525cf0c3b 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -4360,6 +4360,9 @@ static void r600_debugfs_mc_info_init(struct
radeon_device *rdev)
#if defined(CONFIG_DEBUG_FS)
struct dentry *root = rdev->ddev->primary->debugfs_root;
+ if (!root)
+ return;
+
debugfs_create_file("r600_mc_info", 0444, root, rdev,
_debugfs_mc_info_fops);
diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c
b/drivers/gpu/drm/radeon/radeon_dp_mst.c
index ec867fa880a4..cf06da89bb7c 100644
--- a/drivers/gpu/drm/radeon/radeon_dp_mst.c
+++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c
@@ -771,6 +771,9 @@ void radeon_mst_debugfs_init(struct radeon_device *rdev)
#if defined(CONFIG_DEBUG_FS)
struct dentry *root = rdev->ddev->primary->debugfs_root;
+ if (!root)
+ return;
+
debugfs_create_file("radeon_mst_info", 0444, root, rdev,
_debugfs_mst_info_fops);
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c
b/drivers/gpu/drm/radeon/radeon_fence.c
index 73e3117420bf..11f30349de46 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -1006,6 +1006,9 @@ void radeon_debugfs_fence_init(struct radeon_device *rdev)
#if defined(CONFIG_DEBUG_FS)
struct dentry *root = rdev->ddev->primary->debugfs_root;
+ if (!root)
+ return;
+
debugfs_create_file("radeon_gpu_reset", 0444, root, rdev,
_debugfs_gpu_reset_fops);
debugfs_create_file("radeon_fence_info", 0444, root, rdev,
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c
[Intel-gfx] [PATCH 4/5] drm/armada: check dri/crtc root before debugfs init
Return early if dri minor root dentry is NULL.
CC: Russell King
CC: David Airlie
CC: Daniel Vetter
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/armada/armada_debugfs.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/armada/armada_debugfs.c
b/drivers/gpu/drm/armada/armada_debugfs.c
index 29f4b52e3c8d..b40003fe4a89 100644
--- a/drivers/gpu/drm/armada/armada_debugfs.c
+++ b/drivers/gpu/drm/armada/armada_debugfs.c
@@ -93,6 +93,9 @@ static const struct file_operations
armada_debugfs_crtc_reg_fops = {
void armada_drm_crtc_debugfs_init(struct armada_crtc *dcrtc)
{
+ if (!dcrtc->crtc.debugfs_entry)
+ return;
+
debugfs_create_file("armada-regs", 0600, dcrtc->crtc.debugfs_entry,
dcrtc, _debugfs_crtc_reg_fops);
}
@@ -104,6 +107,9 @@ static struct drm_info_list armada_debugfs_list[] = {
int armada_drm_debugfs_init(struct drm_minor *minor)
{
+ if (!minor->debugfs_root)
+ return;
+
drm_debugfs_create_files(armada_debugfs_list, ARMADA_DEBUGFS_ENTRIES,
minor->debugfs_root, minor);
--
2.32.0
[Intel-gfx] [PATCH 5/5] drm/tegra: check root dentry before debugfs init
Return early if crtc or connector's debugfs root dentries are NULL.
CC: Thierry Reding
CC: David Airlie
CC: Daniel Vetter
CC: Jonathan Hunter
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/tegra/dc.c | 5 +
drivers/gpu/drm/tegra/dsi.c | 4
drivers/gpu/drm/tegra/hdmi.c | 5 +
drivers/gpu/drm/tegra/sor.c | 4
4 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index 16c7aabb94d3..87eeda68d231 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -1623,6 +1623,11 @@ static int tegra_dc_late_register(struct drm_crtc *crtc)
struct dentry *root;
struct tegra_dc *dc = to_tegra_dc(crtc);
+ if (!crtc->debugfs_entry) {
+ dc->debugfs_files = NULL;
+ return 0;
+ }
+
#ifdef CONFIG_DEBUG_FS
root = crtc->debugfs_entry;
#else
diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
index f46d377f0c30..f0263165e261 100644
--- a/drivers/gpu/drm/tegra/dsi.c
+++ b/drivers/gpu/drm/tegra/dsi.c
@@ -236,6 +236,10 @@ static int tegra_dsi_late_register(struct drm_connector
*connector)
struct dentry *root = connector->debugfs_entry;
struct tegra_dsi *dsi = to_dsi(output);
+ if (!root) {
+ dsi->debugfs_files = NULL;
+ return 0;
+ }
dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
GFP_KERNEL);
if (!dsi->debugfs_files)
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
index e5d2a4026028..400319db0afc 100644
--- a/drivers/gpu/drm/tegra/hdmi.c
+++ b/drivers/gpu/drm/tegra/hdmi.c
@@ -1065,6 +1065,11 @@ static int tegra_hdmi_late_register(struct drm_connector
*connector)
struct dentry *root = connector->debugfs_entry;
struct tegra_hdmi *hdmi = to_hdmi(output);
+ if (!root) {
+ hdmi->debugfs_files = NULL;
+ return 0;
+ }
+
hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
GFP_KERNEL);
if (!hdmi->debugfs_files)
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index 0ea320c1092b..a8a3b0a587d9 100644
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -1687,6 +1687,10 @@ static int tegra_sor_late_register(struct drm_connector
*connector)
struct dentry *root = connector->debugfs_entry;
struct tegra_sor *sor = to_sor(output);
+ if (!root) {
+ sor->debugfs_files = NULL;
+ return 0;
+ }
sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
GFP_KERNEL);
if (!sor->debugfs_files)
--
2.32.0
Re: [Intel-gfx] [PATCH 1/5] dri: cleanup debugfs error handling
[AMD Official Use Only] Thanks, Greg and Jani. So I have to do the exact opposite. We do have some NULL dentry check in the drm code. I will remove those instead. Regards, Nirmoy From: Greg KH Sent: Friday, October 8, 2021 1:07 PM To: Jani Nikula Cc: Das, Nirmoy ; dri-de...@lists.freedesktop.org ; intel-gfx@lists.freedesktop.org ; Maarten Lankhorst ; Maxime Ripard ; Thomas Zimmermann ; David Airlie ; Daniel Vetter Subject: Re: [Intel-gfx] [PATCH 1/5] dri: cleanup debugfs error handling On Fri, Oct 08, 2021 at 12:40:47PM +0300, Jani Nikula wrote: > On Fri, 08 Oct 2021, Nirmoy Das wrote: > > Debugfs API returns encoded error instead of NULL. > > This patch cleanups drm debugfs error handling to > > properly set dri and its minor's root dentry to NULL. > > > > Also do not error out if dri/minor debugfs directory > > creation fails as a debugfs error is not a fatal error. > > Cc: Greg > > I thought this is the opposite of what Greg's been telling everyone to > do with debugfs. Yes, that is not good. You should never care about the result of a debugfs_create* call. Just take the result, and if it is a directory, save it off to use it for creating a file, no need to check anything. And then throw it away, later, when you want to remove the directory, look it up with a call to debugfs_lookup() and pass that to debugfs_remove() (which does so recursively). There should never be a need to save, or check, the result of any debugfs call. If so, odds are it is being used incorrectly. thanks, greg k-h
Re: [Intel-gfx] [PATCH 1/5] dri: cleanup debugfs error handling
On Fri, Oct 08, 2021 at 12:40:47PM +0300, Jani Nikula wrote: > On Fri, 08 Oct 2021, Nirmoy Das wrote: > > Debugfs API returns encoded error instead of NULL. > > This patch cleanups drm debugfs error handling to > > properly set dri and its minor's root dentry to NULL. > > > > Also do not error out if dri/minor debugfs directory > > creation fails as a debugfs error is not a fatal error. > > Cc: Greg > > I thought this is the opposite of what Greg's been telling everyone to > do with debugfs. Yes, that is not good. You should never care about the result of a debugfs_create* call. Just take the result, and if it is a directory, save it off to use it for creating a file, no need to check anything. And then throw it away, later, when you want to remove the directory, look it up with a call to debugfs_lookup() and pass that to debugfs_remove() (which does so recursively). There should never be a need to save, or check, the result of any debugfs call. If so, odds are it is being used incorrectly. thanks, greg k-h
Re: [Intel-gfx] [PATCH] dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion
On 08/10/2021 11:21, Christian König wrote:
Am 08.10.21 um 11:50 schrieb Tvrtko Ursulin:
From: Tvrtko Ursulin
Cache the count of shared fences in the iterator to avoid dereferencing
the dma_resv_object outside the RCU protection. Otherwise iterator and
its
users can observe an incosistent state which makes it impossible to use
safely.
Ah, of course! I've been staring at the code the whole morning and
couldn't see it.
Going to write a testcase to cover that.
Such as:
<6> [187.517041] [IGT] gem_sync: executing
<7> [187.536343] i915 :00:02.0: [drm:i915_gem_context_create_ioctl
[i915]] HW context 1 created
<7> [187.536793] i915 :00:02.0: [drm:i915_gem_context_create_ioctl
[i915]] HW context 1 created
<6> [187.551235] [IGT] gem_sync: starting subtest basic-many-each
<1> [188.935462] BUG: kernel NULL pointer dereference, address:
0010
<1> [188.935485] #PF: supervisor write access in kernel mode
<1> [188.935495] #PF: error_code(0x0002) - not-present page
<6> [188.935504] PGD 0 P4D 0
<4> [188.935512] Oops: 0002 [#1] PREEMPT SMP NOPTI
<4> [188.935521] CPU: 2 PID: 1467 Comm: gem_sync Not tainted
5.15.0-rc4-CI-Patchwork_21264+ #1
<4> [188.935535] Hardware name: /NUC6CAYB, BIOS
AYAPLCEL.86A.0049.2018.0508.1356 05/08/2018
<4> [188.935546] RIP: 0010:dma_resv_get_fences+0x116/0x2d0
<4> [188.935560] Code: 10 85 c0 7f c9 be 03 00 00 00 e8 15 8b df ff eb
bd e8 8e c6 ff ff eb b6 41 8b 04 24 49 8b 55 00 48 89 e7 8d 48 01 41
89 0c 24 <4c> 89 34 c2 e8 41 f2 ff ff 49 89 c6 48 85 c0 75 8c 48 8b 44
24 10
<4> [188.935583] RSP: 0018:c900011dbcc8 EFLAGS: 00010202
<4> [188.935593] RAX: RBX: RCX:
0001
<4> [188.935603] RDX: 0010 RSI: 822e343c RDI:
c900011dbcc8
<4> [188.935613] RBP: c900011dbd48 R08: 88812d255bb8 R09:
fffe
<4> [188.935623] R10: 0001 R11: R12:
c900011dbd44
<4> [188.935633] R13: c900011dbd50 R14: 888113d29cc0 R15:
<4> [188.935643] FS: 7f68d17e9700() GS:88827790()
knlGS:
<4> [188.935655] CS: 0010 DS: ES: CR0: 80050033
<4> [188.935665] CR2: 0010 CR3: 00012d0a4000 CR4:
003506e0
<4> [188.935676] Call Trace:
<4> [188.935685] i915_gem_object_wait+0x1ff/0x410 [i915]
<4> [188.935988] i915_gem_wait_ioctl+0xf2/0x2a0 [i915]
<4> [188.936272] ? i915_gem_object_wait+0x410/0x410 [i915]
<4> [188.936533] drm_ioctl_kernel+0xae/0x140
<4> [188.936546] drm_ioctl+0x201/0x3d0
<4> [188.936555] ? i915_gem_object_wait+0x410/0x410 [i915]
<4> [188.936820] ? __fget_files+0xc2/0x1c0
<4> [188.936830] ? __fget_files+0xda/0x1c0
<4> [188.936839] __x64_sys_ioctl+0x6d/0xa0
<4> [188.936848] do_syscall_64+0x3a/0xb0
<4> [188.936859] entry_SYSCALL_64_after_hwframe+0x44/0xae
If the shared object has changed during the RCU unlocked period
callers will correctly handle the restart on the next iteration.
Signed-off-by: Tvrtko Ursulin
Fixes: 96601e8a4755 ("dma-buf: use new iterator in dma_resv_copy_fences")
Fixes: d3c80698c9f5 ("dma-buf: use new iterator in dma_resv_get_fences
v3")
Closes:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Fintel%2F-%2Fissues%2F4274data=04%7C01%7Cchristian.koenig%40amd.com%7C0a73b5d07f5f44cdc5a808d98a4109f9%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637692834972816537%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C2000sdata=jhcO2Q8bGhLTW7b4%2BNn4TE3UCwBbAcQVuceJEwDK0fg%3Dreserved=0
Cc: Christian König
Cc: Daniel Vetter
Cc: Sumit Semwal
Cc: linux-me...@vger.kernel.org
Cc: dri-de...@lists.freedesktop.org
Cc: linaro-mm-...@lists.linaro.org
Maybe we should remove cursor->fences altogether, but either way the
patch is Reviewed-by: Christian König
Please push to drm-misc-next ASAP.
Not sure I can or if my push permissions are limited to Intel branches.
I can try once CI gives a green light.
Regards,
Tvrtko
Thanks,
Christian.
---
drivers/dma-buf/dma-resv.c | 18 ++
include/linux/dma-resv.h | 5 -
2 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c
index a480af9581bd..7b6d881c8904 100644
--- a/drivers/dma-buf/dma-resv.c
+++ b/drivers/dma-buf/dma-resv.c
@@ -333,10 +333,14 @@ static void
dma_resv_iter_restart_unlocked(struct dma_resv_iter *cursor)
{
cursor->seq = read_seqcount_begin(>obj->seq);
cursor->index = -1;
- if (cursor->all_fences)
+ cursor->shared_count = 0;
+ if (cursor->all_fences) {
cursor->fences = dma_resv_shared_list(cursor->obj);
- else
+ if (cursor->fences)
+ cursor->shared_count = cursor->fences->shared_count;
+ } else {
cursor->fences = NULL;
+ }
cursor->is_restarted = true;
}
@@ -363,7 +367,7 @@ static void
Re: [Intel-gfx] [PATCH 04/16] drm/i915: Add all per-lane register definitions for icl combo phy
On Fri, Oct 08, 2021 at 01:21:42PM +0300, Jani Nikula wrote:
> On Wed, 06 Oct 2021, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Add the FOO_LN() register macros for all the icl combo phy registers.
> > Also get rid of the semi-pointless FOO_LN0() variants and just use
> > the parametrized version.
> >
> > Signed-off-by: Ville Syrjälä
>
> Might argue the phy should be before lane, but that's another
> conversation.
Agreed. For some reason these were done in the _exact_ opposite order
to the similar defines for earlier platforms. I was really tempted to
cocci these into conformance but decided to leave that out for now.
The series was getting big enough as is.
> Reviewed-by: Jani Nikula
Thanks.
>
> > ---
> > drivers/gpu/drm/i915/display/icl_dsi.c | 14 +++---
> > drivers/gpu/drm/i915/display/intel_combo_phy.c | 8
> > drivers/gpu/drm/i915/display/intel_ddi.c | 14 +++---
> > drivers/gpu/drm/i915/i915_reg.h| 10 --
> > 4 files changed, 22 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index 9ee62707ec72..168c84a74d30 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -233,7 +233,7 @@ static void dsi_program_swing_and_deemphasis(struct
> > intel_encoder *encoder)
> > * Program voltage swing and pre-emphasis level values as per
> > * table in BSPEC under DDI buffer programing
> > */
> > - tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> > + tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
> > tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
> > tmp |= SCALING_MODE_SEL(0x2);
> > tmp |= TAP2_DISABLE | TAP3_DISABLE;
> > @@ -247,7 +247,7 @@ static void dsi_program_swing_and_deemphasis(struct
> > intel_encoder *encoder)
> > tmp |= RTERM_SELECT(0x6);
> > intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp);
> >
> > - tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
> > + tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
> > tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> > RCOMP_SCALAR_MASK);
> > tmp |= SWING_SEL_UPPER(0x2);
> > @@ -455,7 +455,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct
> > intel_encoder *encoder)
> > tmp &= ~FRC_LATENCY_OPTIM_MASK;
> > tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> > intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp);
> > - tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
> > + tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
> > tmp &= ~FRC_LATENCY_OPTIM_MASK;
> > tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> > intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
> > @@ -470,7 +470,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct
> > intel_encoder *encoder)
> >tmp);
> >
> > tmp = intel_de_read(dev_priv,
> > - ICL_PORT_PCS_DW1_LN0(phy));
> > + ICL_PORT_PCS_DW1_LN(0, phy));
> > tmp &= ~LATENCY_OPTIM_MASK;
> > tmp |= LATENCY_OPTIM_VAL(0x1);
> > intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy),
> > @@ -489,7 +489,7 @@ static void gen11_dsi_voltage_swing_program_seq(struct
> > intel_encoder *encoder)
> >
> > /* clear common keeper enable bit */
> > for_each_dsi_phy(phy, intel_dsi->phys) {
> > - tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
> > + tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
> > tmp &= ~COMMON_KEEPER_EN;
> > intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp);
> > tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy));
> > @@ -510,7 +510,7 @@ static void gen11_dsi_voltage_swing_program_seq(struct
> > intel_encoder *encoder)
> >
> > /* Clear training enable to change swing values */
> > for_each_dsi_phy(phy, intel_dsi->phys) {
> > - tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> > + tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
> > tmp &= ~TX_TRAINING_EN;
> > intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
> > tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
> > @@ -523,7 +523,7 @@ static void gen11_dsi_voltage_swing_program_seq(struct
> > intel_encoder *encoder)
> >
> > /* Set training enable to trigger update */
> > for_each_dsi_phy(phy, intel_dsi->phys) {
> > - tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> > + tmp =
Re: [Intel-gfx] [PATCH 06/16] drm/i915: Extract icl_combo_phy_loadgen_select()
On Wed, 06 Oct 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Pull the convoluted loadgen calculation into a small helper.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 23 ++-
> 1 file changed, 14 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index b8ec53d9e3b0..d06c76694a08 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1023,6 +1023,18 @@ static u8 intel_ddi_dp_preemph_max(struct intel_dp
> *intel_dp)
> return DP_TRAIN_PRE_EMPH_LEVEL_3;
> }
>
> +static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state
> *crtc_state,
> + int lane)
> +{
> + if (crtc_state->port_clock > 60)
> + return 0;
> +
> + if (crtc_state->lane_count == 4)
> + return lane >= 1 ? LOADGEN_SELECT : 0;
> + else
> + return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0;
> +}
> +
> static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>const struct intel_crtc_state
> *crtc_state)
> {
> @@ -1089,11 +1101,8 @@ static void icl_combo_phy_set_signal_levels(struct
> intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> - int width, rate, ln;
> u32 val;
> -
> - width = crtc_state->lane_count;
> - rate = crtc_state->port_clock;
> + int ln;
>
> /*
>* 1. If port type is eDP or DP,
> @@ -1117,11 +1126,7 @@ static void icl_combo_phy_set_signal_levels(struct
> intel_encoder *encoder,
> for (ln = 0; ln < 4; ln++) {
> val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
> val &= ~LOADGEN_SELECT;
> -
> - if ((rate <= 60 && width == 4 && ln >= 1) ||
> - (rate <= 60 && width < 4 && (ln == 1 || ln == 2))) {
> - val |= LOADGEN_SELECT;
> - }
> + val |= icl_combo_phy_loadgen_select(crtc_state, ln);
> intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
> }
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 05/16] drm/i915: Remove dead DKL_TX_LOADGEN_SHARING_PMD_DISABLE stuff
On Wed, 06 Oct 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> DKL_TX_LOADGEN_SHARING_PMD_DISABLE doesn't even seem to exist,
> also the spec says to skip all loadgen stuff.
>
> The code was dead anyway since it wasn't actually writing the value
> anywhere.
>
> Signed-off-by: Ville Syrjälä
I admit not looking this up in spec, but this is dead code removal
anyway...
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 8
> drivers/gpu/drm/i915/i915_reg.h | 1 -
> 2 files changed, 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 0c9ed705af47..b8ec53d9e3b0 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1309,14 +1309,6 @@ static void tgl_dkl_phy_set_signal_levels(struct
> intel_encoder *encoder,
> val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
> val &= ~DKL_TX_DP20BITMODE;
> intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
> -
> - if ((intel_crtc_has_dp_encoder(crtc_state) &&
> - crtc_state->port_clock == 162000) ||
> - (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> - crtc_state->port_clock == 594000))
> - val |= DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
> - else
> - val &= ~DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5e7a55e6ef50..8c8152de643f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11022,7 +11022,6 @@ enum skl_power_gate {
>_DKL_TX_DPCNTL1)
>
> #define _DKL_TX_DPCNTL2 0x2C8
> -#define DKL_TX_LOADGEN_SHARING_PMD_DISABLEREG_BIT(12)
> #define DKL_TX_DP20BITMODE (1 << 2)
> #define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
>_DKL_PHY1_BASE, \
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 04/16] drm/i915: Add all per-lane register definitions for icl combo phy
On Wed, 06 Oct 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Add the FOO_LN() register macros for all the icl combo phy registers.
> Also get rid of the semi-pointless FOO_LN0() variants and just use
> the parametrized version.
>
> Signed-off-by: Ville Syrjälä
Might argue the phy should be before lane, but that's another
conversation.
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 14 +++---
> drivers/gpu/drm/i915/display/intel_combo_phy.c | 8
> drivers/gpu/drm/i915/display/intel_ddi.c | 14 +++---
> drivers/gpu/drm/i915/i915_reg.h| 10 --
> 4 files changed, 22 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 9ee62707ec72..168c84a74d30 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -233,7 +233,7 @@ static void dsi_program_swing_and_deemphasis(struct
> intel_encoder *encoder)
>* Program voltage swing and pre-emphasis level values as per
>* table in BSPEC under DDI buffer programing
>*/
> - tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> + tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
> tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
> tmp |= SCALING_MODE_SEL(0x2);
> tmp |= TAP2_DISABLE | TAP3_DISABLE;
> @@ -247,7 +247,7 @@ static void dsi_program_swing_and_deemphasis(struct
> intel_encoder *encoder)
> tmp |= RTERM_SELECT(0x6);
> intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp);
>
> - tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
> + tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
> tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
>RCOMP_SCALAR_MASK);
> tmp |= SWING_SEL_UPPER(0x2);
> @@ -455,7 +455,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct
> intel_encoder *encoder)
> tmp &= ~FRC_LATENCY_OPTIM_MASK;
> tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp);
> - tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
> + tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
> tmp &= ~FRC_LATENCY_OPTIM_MASK;
> tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
> @@ -470,7 +470,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct
> intel_encoder *encoder)
> tmp);
>
> tmp = intel_de_read(dev_priv,
> - ICL_PORT_PCS_DW1_LN0(phy));
> + ICL_PORT_PCS_DW1_LN(0, phy));
> tmp &= ~LATENCY_OPTIM_MASK;
> tmp |= LATENCY_OPTIM_VAL(0x1);
> intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy),
> @@ -489,7 +489,7 @@ static void gen11_dsi_voltage_swing_program_seq(struct
> intel_encoder *encoder)
>
> /* clear common keeper enable bit */
> for_each_dsi_phy(phy, intel_dsi->phys) {
> - tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
> + tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
> tmp &= ~COMMON_KEEPER_EN;
> intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp);
> tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy));
> @@ -510,7 +510,7 @@ static void gen11_dsi_voltage_swing_program_seq(struct
> intel_encoder *encoder)
>
> /* Clear training enable to change swing values */
> for_each_dsi_phy(phy, intel_dsi->phys) {
> - tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> + tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
> tmp &= ~TX_TRAINING_EN;
> intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
> tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
> @@ -523,7 +523,7 @@ static void gen11_dsi_voltage_swing_program_seq(struct
> intel_encoder *encoder)
>
> /* Set training enable to trigger update */
> for_each_dsi_phy(phy, intel_dsi->phys) {
> - tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> + tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
> tmp |= TX_TRAINING_EN;
> intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
> tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index bacdf8a16bcb..634e8d449457 100644
> ---
Re: [Intel-gfx] [PATCH 03/16] drm/i915: Use standard form terminating condition for lane for loops
On Wed, 06 Oct 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use <4 instead of <=3 as the terminating condition for the
> loops over the 4 lanes.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index d85d731e37fb..b0bd50383d57 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1067,7 +1067,7 @@ static void icl_ddi_combo_vswing_program(struct
> intel_encoder *encoder,
>
> /* Program PORT_TX_DW4 */
> /* We cannot write to GRP. It would overwrite individual loadgen. */
> - for (ln = 0; ln <= 3; ln++) {
> + for (ln = 0; ln < 4; ln++) {
> val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
> val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
>CURSOR_COEFF_MASK);
> @@ -1114,7 +1114,7 @@ static void icl_combo_phy_set_signal_levels(struct
> intel_encoder *encoder,
>* <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
>* > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
>*/
> - for (ln = 0; ln <= 3; ln++) {
> + for (ln = 0; ln < 4; ln++) {
> val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
> val &= ~LOADGEN_SELECT;
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 02/16] drm/i915: Shrink {icl_mg, tgl_dkl}_phy_ddi_buf_trans
On Wed, 06 Oct 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> All the values we have in {icl_mg,tgl_dkl}_phy_ddi_buf_trans
> fit into u8. Shrink the types accordingly.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> index 82fdc5ecd9de..2133984a572b 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> @@ -34,15 +34,15 @@ struct icl_ddi_buf_trans {
> };
>
> struct icl_mg_phy_ddi_buf_trans {
> - u32 cri_txdeemph_override_11_6;
> - u32 cri_txdeemph_override_5_0;
> - u32 cri_txdeemph_override_17_12;
> + u8 cri_txdeemph_override_11_6;
> + u8 cri_txdeemph_override_5_0;
> + u8 cri_txdeemph_override_17_12;
> };
>
> struct tgl_dkl_phy_ddi_buf_trans {
> - u32 vswing;
> - u32 preshoot;
> - u32 de_emphasis;
> + u8 vswing;
> + u8 preshoot;
> + u8 de_emphasis;
> };
>
> struct dg2_snps_phy_buf_trans {
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 01/16] drm/i915: Remove pointless extra namespace from dkl/snps buf trans structs
On Wed, 06 Oct 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The struct itself already has sufficient namespace. No need to
> duplicate it in the members.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++---
> drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h | 12 ++--
> drivers/gpu/drm/i915/display/intel_snps_phy.c | 6 +++---
> 3 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 3f7bbeb3e3cd..d85d731e37fb 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1285,9 +1285,9 @@ static void tgl_dkl_phy_set_signal_levels(struct
> intel_encoder *encoder,
> dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
> DKL_TX_DE_EMPAHSIS_COEFF_MASK |
> DKL_TX_VSWING_CONTROL_MASK);
> - dpcnt_val =
> DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.dkl_vswing_control);
> - dpcnt_val |=
> DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.dkl_de_emphasis_control);
> - dpcnt_val |=
> DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.dkl_preshoot_control);
> + dpcnt_val = DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing);
> + dpcnt_val |=
> DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis);
> + dpcnt_val |= DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot);
>
> for (ln = 0; ln < 2; ln++) {
> intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> index 6cdb8e9073c7..82fdc5ecd9de 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> @@ -40,15 +40,15 @@ struct icl_mg_phy_ddi_buf_trans {
> };
>
> struct tgl_dkl_phy_ddi_buf_trans {
> - u32 dkl_vswing_control;
> - u32 dkl_preshoot_control;
> - u32 dkl_de_emphasis_control;
> + u32 vswing;
> + u32 preshoot;
> + u32 de_emphasis;
> };
>
> struct dg2_snps_phy_buf_trans {
> - u8 snps_vswing;
> - u8 snps_pre_cursor;
> - u8 snps_post_cursor;
> + u8 vswing;
> + u8 pre_cursor;
> + u8 post_cursor;
> };
>
> union intel_ddi_buf_trans_entry {
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> index b18f08c851dc..5e20f340730f 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> @@ -68,9 +68,9 @@ void intel_snps_phy_set_signal_levels(struct intel_encoder
> *encoder,
> for (ln = 0; ln < 4; ln++) {
> u32 val = 0;
>
> - val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN,
> trans->entries[level].snps.snps_vswing);
> - val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE,
> trans->entries[level].snps.snps_pre_cursor);
> - val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST,
> trans->entries[level].snps.snps_post_cursor);
> + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN,
> trans->entries[level].snps.vswing);
> + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE,
> trans->entries[level].snps.pre_cursor);
> + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST,
> trans->entries[level].snps.post_cursor);
>
> intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), val);
> }
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH v2] drm/i915/gt: move remaining debugfs interfaces into gt
Hi Lucas,
> > I am reproposing this patch exactly as it was proposed initially
> > where the original interfaces are kept where they have been
> > originally placed. It might generate some duplicated code but,
> > well, it's debugfs and I don't see any issue. In the future we
> > can transform the upper interfaces to act upon all the GTs and
> > provide information from all the GTs. This is, for example, how
> > the sysfs interfaces will act.
>
> NACK. We've made this mistake in the past for other debugfs files.
> We don't want to do it again just to maintain 2 separate places for
> one year and then finally realize we want to merge them.
In my opinion it's all about what mistake you like the most
because until we will have multi-gt support in upstream all the
patches come with the "promise" of a follow-up and maintenance
cost.
> > The reason I removed them in V1 is because igt as only user is
> > not a strong reason to keep duplicated code, but as Chris
> > suggested offline:
> >
> > "It's debugfs, igt is the primary consumer. CI has to be bridged over
> > changes to the interfaces it is using in any case, as you want
> > comparable results before/after the patches land.
>
> That doesn't mean you have to copy and paste it. It may mean you
> do the implementation in one of them and the other calls that implementation.
> See how I did the deduplication in commit d0c560316d6f ("drm/i915:
> deduplicate frequency dump on debugfs")
In this case, from a user perspective, which gt is the interface
affecting? is it affecting all the system? or gt 0, 1...? Does
the user know? The maintenance cost is that later you will need
to use for_each_gt and make all those interfaces multitile, and
this would be your "promise".
How are you going to do it then? Will every interface iterate and
perform its own action? When you read, whad do you read? all the
gt values in 'or'? in 'and'? Is there any common strategy? Or
will we have inconsistent behaviors?
In sysfs (where we are left with the same questions) some times
ago I proposoed a common solution for all the upper level files
in order to provide the user with a consistent interface all
along the GTs.
This is my "promise" and until then it's just a matter of what
promise and what mistake you like the most.
> Alternative would be to prepare igt already and then add a Test-with:
> in this patch
> series But I think it makes more sense to support both locations
> for some time and then later
> remove the previous one.
Anyway, I can sure do something similar to how you did it, it
might look prettier but it doesn't exclude a follow-up
improvement.
Thanks for the review,
Andi
[Intel-gfx] [PATCH] dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion
From: Tvrtko Ursulin
Cache the count of shared fences in the iterator to avoid dereferencing
the dma_resv_object outside the RCU protection. Otherwise iterator and its
users can observe an incosistent state which makes it impossible to use
safely. Such as:
<6> [187.517041] [IGT] gem_sync: executing
<7> [187.536343] i915 :00:02.0: [drm:i915_gem_context_create_ioctl [i915]]
HW context 1 created
<7> [187.536793] i915 :00:02.0: [drm:i915_gem_context_create_ioctl [i915]]
HW context 1 created
<6> [187.551235] [IGT] gem_sync: starting subtest basic-many-each
<1> [188.935462] BUG: kernel NULL pointer dereference, address: 0010
<1> [188.935485] #PF: supervisor write access in kernel mode
<1> [188.935495] #PF: error_code(0x0002) - not-present page
<6> [188.935504] PGD 0 P4D 0
<4> [188.935512] Oops: 0002 [#1] PREEMPT SMP NOPTI
<4> [188.935521] CPU: 2 PID: 1467 Comm: gem_sync Not tainted
5.15.0-rc4-CI-Patchwork_21264+ #1
<4> [188.935535] Hardware name: /NUC6CAYB, BIOS
AYAPLCEL.86A.0049.2018.0508.1356 05/08/2018
<4> [188.935546] RIP: 0010:dma_resv_get_fences+0x116/0x2d0
<4> [188.935560] Code: 10 85 c0 7f c9 be 03 00 00 00 e8 15 8b df ff eb bd e8 8e
c6 ff ff eb b6 41 8b 04 24 49 8b 55 00 48 89 e7 8d 48 01 41 89 0c 24 <4c> 89 34
c2 e8 41 f2 ff ff 49 89 c6 48 85 c0 75 8c 48 8b 44 24 10
<4> [188.935583] RSP: 0018:c900011dbcc8 EFLAGS: 00010202
<4> [188.935593] RAX: RBX: RCX:
0001
<4> [188.935603] RDX: 0010 RSI: 822e343c RDI:
c900011dbcc8
<4> [188.935613] RBP: c900011dbd48 R08: 88812d255bb8 R09:
fffe
<4> [188.935623] R10: 0001 R11: R12:
c900011dbd44
<4> [188.935633] R13: c900011dbd50 R14: 888113d29cc0 R15:
<4> [188.935643] FS: 7f68d17e9700() GS:88827790()
knlGS:
<4> [188.935655] CS: 0010 DS: ES: CR0: 80050033
<4> [188.935665] CR2: 0010 CR3: 00012d0a4000 CR4:
003506e0
<4> [188.935676] Call Trace:
<4> [188.935685] i915_gem_object_wait+0x1ff/0x410 [i915]
<4> [188.935988] i915_gem_wait_ioctl+0xf2/0x2a0 [i915]
<4> [188.936272] ? i915_gem_object_wait+0x410/0x410 [i915]
<4> [188.936533] drm_ioctl_kernel+0xae/0x140
<4> [188.936546] drm_ioctl+0x201/0x3d0
<4> [188.936555] ? i915_gem_object_wait+0x410/0x410 [i915]
<4> [188.936820] ? __fget_files+0xc2/0x1c0
<4> [188.936830] ? __fget_files+0xda/0x1c0
<4> [188.936839] __x64_sys_ioctl+0x6d/0xa0
<4> [188.936848] do_syscall_64+0x3a/0xb0
<4> [188.936859] entry_SYSCALL_64_after_hwframe+0x44/0xae
If the shared object has changed during the RCU unlocked period
callers will correctly handle the restart on the next iteration.
Signed-off-by: Tvrtko Ursulin
Fixes: 96601e8a4755 ("dma-buf: use new iterator in dma_resv_copy_fences")
Fixes: d3c80698c9f5 ("dma-buf: use new iterator in dma_resv_get_fences v3")
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4274
Cc: Christian König
Cc: Daniel Vetter
Cc: Sumit Semwal
Cc: linux-me...@vger.kernel.org
Cc: dri-de...@lists.freedesktop.org
Cc: linaro-mm-...@lists.linaro.org
---
drivers/dma-buf/dma-resv.c | 18 ++
include/linux/dma-resv.h | 5 -
2 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c
index a480af9581bd..7b6d881c8904 100644
--- a/drivers/dma-buf/dma-resv.c
+++ b/drivers/dma-buf/dma-resv.c
@@ -333,10 +333,14 @@ static void dma_resv_iter_restart_unlocked(struct
dma_resv_iter *cursor)
{
cursor->seq = read_seqcount_begin(>obj->seq);
cursor->index = -1;
- if (cursor->all_fences)
+ cursor->shared_count = 0;
+ if (cursor->all_fences) {
cursor->fences = dma_resv_shared_list(cursor->obj);
- else
+ if (cursor->fences)
+ cursor->shared_count = cursor->fences->shared_count;
+ } else {
cursor->fences = NULL;
+ }
cursor->is_restarted = true;
}
@@ -363,7 +367,7 @@ static void dma_resv_iter_walk_unlocked(struct
dma_resv_iter *cursor)
continue;
} else if (!cursor->fences ||
- cursor->index >= cursor->fences->shared_count) {
+ cursor->index >= cursor->shared_count) {
cursor->fence = NULL;
break;
@@ -448,10 +452,8 @@ int dma_resv_copy_fences(struct dma_resv *dst, struct
dma_resv *src)
dma_resv_list_free(list);
dma_fence_put(excl);
- if (cursor.fences) {
- unsigned int cnt = cursor.fences->shared_count;
-
- list = dma_resv_list_alloc(cnt);
+ if (cursor.shared_count) {
+ list = dma_resv_list_alloc(cursor.shared_count);
Re: [Intel-gfx] [PATCH] drm/i915: Stop using I915_TILING_* in client blit selftest
On Thu, Sep 30, 2021 at 05:58:16PM -0700, Matt Roper wrote:
> The I915_TILING_* definitions in the uapi header are intended solely for
> tiling modes that are visible to the old de-tiling fence ioctls. Since
> modern hardware does not support de-tiling fences, we should not add new
> definitions for new tiling types going forward. However we do want the
> client blit selftest to eventually cover other new tiling modes (such as
> Tile4), so switch it to using its own enum of tiling modes.
>
> Cc: Ville Syrjälä
> Cc: Stanislav Lisovskiy
> Signed-off-by: Matt Roper
> ---
> .../i915/gem/selftests/i915_gem_client_blt.c | 29 ---
> include/uapi/drm/i915_drm.h | 6
> 2 files changed, 24 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> index ecbcbb86ae1e..8402ed925a69 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> @@ -17,13 +17,20 @@
> #include "huge_gem_object.h"
> #include "mock_context.h"
>
> +enum client_tiling {
> + CLIENT_TILING_LINEAR,
> + CLIENT_TILING_X,
> + CLIENT_TILING_Y,
> + CLIENT_NUM_TILING_TYPES
> +};
> +
> #define WIDTH 512
> #define HEIGHT 32
>
> struct blit_buffer {
> struct i915_vma *vma;
> u32 start_val;
> - u32 tiling;
> + enum client_tiling tiling;
> };
>
> struct tiled_blits {
> @@ -53,9 +60,9 @@ static int prepare_blit(const struct tiled_blits *t,
> *cs++ = MI_LOAD_REGISTER_IMM(1);
> *cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
> cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
> - if (src->tiling == I915_TILING_Y)
> + if (src->tiling == CLIENT_TILING_Y)
> cmd |= BCS_SRC_Y;
> - if (dst->tiling == I915_TILING_Y)
> + if (dst->tiling == CLIENT_TILING_Y)
> cmd |= BCS_DST_Y;
> *cs++ = cmd;
>
> @@ -172,7 +179,7 @@ static int tiled_blits_create_buffers(struct tiled_blits
> *t,
>
> t->buffers[i].vma = vma;
> t->buffers[i].tiling =
> - i915_prandom_u32_max_state(I915_TILING_Y + 1, prng);
> + i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng);
> }
>
> return 0;
> @@ -197,17 +204,17 @@ static u64 swizzle_bit(unsigned int bit, u64 offset)
> static u64 tiled_offset(const struct intel_gt *gt,
> u64 v,
> unsigned int stride,
> - unsigned int tiling)
> + enum client_tiling tiling)
> {
> unsigned int swizzle;
> u64 x, y;
>
> - if (tiling == I915_TILING_NONE)
> + if (tiling == CLIENT_TILING_LINEAR)
> return v;
>
> y = div64_u64_rem(v, stride, );
>
> - if (tiling == I915_TILING_X) {
> + if (tiling == CLIENT_TILING_X) {
> v = div64_u64_rem(y, 8, ) * stride * 8;
> v += y * 512;
> v += div64_u64_rem(x, 512, ) << 12;
> @@ -244,12 +251,12 @@ static u64 tiled_offset(const struct intel_gt *gt,
> return v;
> }
>
> -static const char *repr_tiling(int tiling)
> +static const char *repr_tiling(enum client_tiling tiling)
> {
> switch (tiling) {
> - case I915_TILING_NONE: return "linear";
> - case I915_TILING_X: return "X";
> - case I915_TILING_Y: return "Y";
> + case CLIENT_TILING_LINEAR: return "linear";
> + case CLIENT_TILING_X: return "X";
> + case CLIENT_TILING_Y: return "Y";
> default: return "unknown";
> }
> }
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index bde5860b3686..00311a63068e 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1522,6 +1522,12 @@ struct drm_i915_gem_caching {
> #define I915_TILING_NONE 0
> #define I915_TILING_X1
> #define I915_TILING_Y2
> +/*
> + * Do not add new tiling types here. The I915_TILING_* values are for
> + * de-tiling fence registers that no longer exist on modern platforms.
> Although
> + * the hardware may support new types of tiling in general (e.g., Tile4), we
> + * do not need to add them to the uapi that is specific to now-defunct
> ioctls.
> + */
> #define I915_TILING_LAST I915_TILING_Y
I think we should split this one into a separate patch to give it
some visibility. The people who care about gem uapi seem to be in
some kind of early winter hibernation and no one read this.
Apart from that
Reviewed-by: Ville Syrjälä
>
> #define I915_BIT_6_SWIZZLE_NONE 0
> --
> 2.33.0
--
Ville Syrjälä
Intel
