Hi Dave and Daniel,
Only one fix for this round. Sending earlier today due to Holiday in US
tomorrow.
Here goes drm-intel-fixes-2021-11-24:
Fix wakeref handling of PXP suspend.
Thanks,
Rodrigo.
The following changes since commit 136057256686de39cc3a07c2e39ef6bc43003ff6:
Linux 5.16-rc2 (2021
Filed two new issues
https://gitlab.freedesktop.org/drm/intel/-/issues/4632
igt@gem_exec_create@forked@smem - incomplete - No warnings/errors
https://gitlab.freedesktop.org/drm/intel/-/issues/4633
igt@kms_atomic_interruptible@universal-setplane-cursor@dp-1-pipe-a - incomplete
- No warnings/errors
== Series Details ==
Series: drm/i915/ttm: Async migration (rev11)
URL : https://patchwork.freedesktop.org/series/96798/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10921_full -> Patchwork_21672_full
Summary
---
**
== Series Details ==
Series: drm/i915/gvt: Prevent integer overflow in intel_vgpu_emulate_cfg_write()
URL : https://patchwork.freedesktop.org/series/97250/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10924_full -> Patchwork_21677_full
== Series Details ==
Series: drm/i915/ttm: Async migration (rev11)
URL : https://patchwork.freedesktop.org/series/96798/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10921_full -> Patchwork_21672_full
Summary
---
**
== Series Details ==
Series: drm/i915/ttm: Async migration (rev11)
URL : https://patchwork.freedesktop.org/series/96798/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10921_full -> Patchwork_21672_full
Summary
---
**
On Wed, Nov 24, 2021 at 08:45:50AM +, Tvrtko Ursulin wrote:
>
> On 24/11/2021 08:04, Zbigniew Kempczyński wrote:
> > On Tue, Nov 23, 2021 at 09:49:04AM +, Tvrtko Ursulin wrote:
> > >
> > > On 22/11/2021 19:13, Zbigniew Kempczyński wrote:
> > > > In short - we want to enforce alignment ==
Good catch - i missed that. Will fix it. Thanks again.
...alan
On Wed, 2021-11-24 at 12:08 +0200, Jani Nikula wrote:
> On Mon, 22 Nov 2021, Alan Previn wrote:
> > Add GuC's error capture output structures and definitions as how
> > they would appear in GuC log buffer's error capture subregion af
Thanks very much Jani for the detail review of the code... apologies on some of
the styling mishaps.
I will fix them all. I agree completely with the header file comments - my bad
on that - had already
learnt that lesson on pxp side. Will fix accordingly.
...alan
On Wed, 2021-11-24 at 12:06 +0
Thanks Michal for the thorough review of the code (and the other patches). I
will fix them all.
On the register-to-string helper function,
i'll have to think it through because i do want to keep future development
maintenance work when adding new registers simple (in the sense that
adding a singl
== Series Details ==
Series: drm/i915/gvt: Prevent integer overflow in intel_vgpu_emulate_cfg_write()
URL : https://patchwork.freedesktop.org/series/97250/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10924 -> Patchwork_21677
==
Thanks Michal for reviewing the code. I will get all of these fixed.
I still would like continue to have a first patch with a skeleton table of
registers
as the patch that focuses on the infrastructure and another patch just for the
registers.
That sad, to align with your review comments, i sha
On Wed, 2021-11-24 at 11:56 +0100, Thomas Hellström wrote:
>
> On 11/24/21 10:42, Patchwork wrote:
>
> > Project List - Patchwork Patch Details Series: drm/i915/ttm: Async
> > migration (rev11) URL:
> > https://patchwork.freedesktop.org/series/96798/ State: failure
> > Details:
> > https://intel-
On Wed, 24 Nov 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Continue refactoring the FBC code towards multiple FBC
> instances and more flexible plane<->FBC assignment.
There's a lot to like here. I haven't done detailed review, but apart
from the comment on the debugfs split, the series
On Wed, 24 Nov 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> In order to encapsulate FBC harder let's just move the debugfs
> stuff into intel_fbc.c.
Mmmh, I've kind of moved towards a split where i915_debugfs.c and
intel_display_debugfs.c have all the debugfs boilerplate, while the
imple
On Wed, Nov 24, 2021 at 08:55:39AM -0500, Rodrigo Vivi wrote:
> On Wed, Nov 24, 2021 at 08:56:52AM +, Tvrtko Ursulin wrote:
> >
> > On 23/11/2021 19:52, Rodrigo Vivi wrote:
> > > On Tue, Nov 23, 2021 at 09:39:25AM +, Tvrtko Ursulin wrote:
> > > >
> > > > On 17/11/2021 22:49, Vinay Belgaum
On Wed, Nov 24, 2021 at 01:06:47AM +0530, Uma Shankar wrote:
> Enable pipe color support for Display 13 platforms. Currently
> limit to just 10bit gamma and later extend it for logarithmic
> gamma, once the new UAPI is agreed by community and implemented
> by a userspace consumer.
>
> Signed-off-b
On Wed, Nov 24, 2021 at 01:06:49AM +0530, Uma Shankar wrote:
> XE_LPD has 128 Lut entries for Degamma, with additional 3 entries for
> extended range. It has 511 entries for gamma with additional 2 entries
> for extended range.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/i915_pci
On Wed, Nov 24, 2021 at 01:06:48AM +0530, Uma Shankar wrote:
> Enable Pipe Degamma for XE_LPD. Extend the legacy implementation
> to incorparate the extended lut size for XE_LPD.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 12 +---
> 1 file changed
The "offset" is a u32 that comes from the user. The bug is that the
"offset + bytes" operation can have an integer overflow problem which
leads to an out of bounds access.
Fixes: 4d60c5fd3f87 ("drm/i915/gvt: vGPU PCI configuration space
virtualization")
Signed-off-by: Dan Carpenter
---
drivers
== Series Details ==
Series: drm/i915/fbc: More FBC refactoring
URL : https://patchwork.freedesktop.org/series/97239/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10923 -> Patchwork_21674
Summary
---
**FAILURE**
== Series Details ==
Series: sysctl: second set of kernel/sysctl cleanups (rev2)
URL : https://patchwork.freedesktop.org/series/97221/
State : failure
== Summary ==
Applying: hpet: simplify subdirectory registration with register_sysctl()
Applying: i915: simplify subdirectory registration with
== Series Details ==
Series: drm/i915/dmabuf: remove duplicate include in i915_gem_dmabuf.c
URL : https://patchwork.freedesktop.org/series/97244/
State : failure
== Summary ==
Applying: drm/i915/dmabuf: remove duplicate include in i915_gem_dmabuf.c
Using index info to reconstruct a base tree..
On Wed, Nov 24, 2021 at 08:56:52AM +, Tvrtko Ursulin wrote:
>
> On 23/11/2021 19:52, Rodrigo Vivi wrote:
> > On Tue, Nov 23, 2021 at 09:39:25AM +, Tvrtko Ursulin wrote:
> > >
> > > On 17/11/2021 22:49, Vinay Belgaumkar wrote:
> > > > From: Chris Wilson
> > > >
> > > > Everytime we come
On Wed, Nov 24, 2021 at 10:44:09AM +0100, Jan Kara wrote:
> On Tue 23-11-21 12:24:20, Luis Chamberlain wrote:
> > From: Xiaoming Ni
> >
> > There is no need to user boiler plate code to specify a set of base
> > directories we're going to stuff sysctls under. Simplify this by using
> > register_s
== Series Details ==
Series: drm/i915/fbc: More FBC refactoring
URL : https://patchwork.freedesktop.org/series/97239/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
From: Yao Jing
'asm/smp.h' included in 'drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c' is
duplicated. It is clearly included on the 12 line.
Reported-by: Zeal Robot
Signed-off-by: Yao Jing
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
di
== Series Details ==
Series: drm/i915/fbc: More FBC refactoring
URL : https://patchwork.freedesktop.org/series/97239/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
daf75ef5fa24 drm/i915/fbc: Eliminate racy intel_fbc_is_active() usage
af7d3467e59a drm/i915/fbc: Pass whole plane
== Series Details ==
Series: Revert "drm/i915/dg2: Tile 4 plane format support"
URL : https://patchwork.freedesktop.org/series/97231/
State : failure
== Summary ==
Applying: Revert "drm/i915/dg2: Tile 4 plane format support"
Using index info to reconstruct a base tree...
M drivers/gpu/dr
> From: Jason Gunthorpe
> Sent: Fri, 1 Oct 2021 14:52:51 -0300
>
> The css_driver's main purpose is to create/destroy the mdev and relay the
> shutdown, irq, sch_event, and chp_event css_driver ops to the single
> created vfio_device, if it exists.
>
> Reframe the boundary where the css_driver do
From: Ville Syrjälä
Now that each plane tracks its own no_fbc_reason we can print that
out in debugfs, and we can also show which plane is currently
selected for FBC duty.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 18 ++
1 file changed, 18 inse
From: Ville Syrjälä
FBC and double wide pipe are mutually exclusive. Disable FBC when
we have to resort to double wide.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b
From: Ville Syrjälä
Currently we track the FBC plane as a pointer under intel_fbc
and also as a i9xx_plane_id under intel_fbc_state. Just store
the pointer once in the fbc state.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 54
1 file cha
From: Ville Syrjälä
Rename the 'params' to just fbc state.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 138 +++
1 file changed, 68 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/d
From: Ville Syrjälä
fbc->state_cache has now become useless. We can simply update
the reg params directly from the plane/crtc states during
__intel_fbc_enable().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 169 +--
1 file changed, 62 insertio
From: Ville Syrjälä
Don't really see a good reason why we can't just do the vgpu and
modparam checks already in intel_fbc_check_plane().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 22 ++
1 file changed, 10 insertions(+), 12 deletions(-)
dif
From: Ville Syrjälä
Currently a FIFO underrun just causes FBC to be deactivated,
and later checks then prevent it from being reactivated. We
can simpify our lives a bit by logically disabling FBC on
FIFO underruna. This avoids the funny intermediate state where
FBC is logically enabled but can't
From: Ville Syrjälä
In order to better encapsulate the FBC implementation
introduce a small helper to do the plane<->FBC instance
association.
We'll also try to structure the plane init code such
that introducing multiple FBC instances will be easier
down the line.
Signed-off-by: Ville Syrjälä
From: Ville Syrjälä
In the future we may have more than one FBC instance on some
platforms. So let's just allocate it dynamically. This also
lets us fully hide the implementation from prying eyes.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +-
drivers/
From: Ville Syrjälä
The underrun code doesn't need to know any details about FBC, so
just pass in the whole device rather than a specific FBC instance.
We could make this a bit more fine grained by also passing in the
pipe to intel_fbc_handle_fifo_underrun_irq() and letting the FBC
code figure wh
From: Ville Syrjälä
In order to encapsulate FBC harder let's just move the debugfs
stuff into intel_fbc.c.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_debugfs.c | 50 +---
drivers/gpu/drm/i915/display/intel_fbc.c | 110 +-
drivers/gpu/drm/i915
From: Ville Syrjälä
Use an early return to flatten most of __intel_fbc_pre_update().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 40
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
From: Ville Syrjälä
In the future we may have multiple planes on the same pipe
capable of using FBC. Prepare for that by tracking FBC usage
per-plane rather than per-crtc.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 224 +++
drivers/gpu/drm/i
From: Ville Syrjälä
Pass the FBC instance instead of the crtc to a bunch of places.
We also adjust intel_fbc_post_update() to do the
intel_fbc_get_reg_params() things instead of doing it from the lower
level function (which also gets called for front buffer tracking).
Nothing in there will chang
From: Ville Syrjälä
The FBC state cache and params are now nearly identical. Just
use the same structure for both.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 62 +++-
drivers/gpu/drm/i915/i915_drv.h | 36 +-
2 files chan
From: Ville Syrjälä
There's no need to store all this stuff in intel_fbc_state_cache.
Just check it all against the plane/crtc states and store only
what we need. Probably more should get nuked still, but this
is a start.
So what we'll do is:
- each plane will check its own state and update its
From: Ville Syrjälä
There isn't a good reason why we'd have to cache all this
plane state stuff in the FBC state. Instead we can just
pre-calculate what FBC will really need.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 132 +++
drivers/gpu/dr
From: Ville Syrjälä
Move intel_fbc_override_cfb_stride() next to its cousins.
Helps with later patches.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 42
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/
From: Ville Syrjälä
No reason to burden the caller with the details on how the minimum
compression limit is calculated, so just pass in the whole plane
state instead of just the cpp value.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 7 ---
1 file changed, 4
From: Ville Syrjälä
The ilk fbc watermark computation uses intel_fbc_is_active() which
is racy since we don't know whether FBC will be enabled or not at
some point. So let's just assume it will be if both HAS_FBC()
and the modparam agree.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i
From: Ville Syrjälä
Continue refactoring the FBC code towards multiple FBC
instances and more flexible plane<->FBC assignment.
Ville Syrjälä (20):
drm/i915/fbc: Eliminate racy intel_fbc_is_active() usage
drm/i915/fbc: Pass whole plane state to intel_fbc_min_limit()
drm/i915/fbc: Nuke lots
On Wed, 24 Nov 2021, "Lisovskiy, Stanislav"
wrote:
> On Wed, Nov 24, 2021 at 12:23:08PM +0200, Jani Nikula wrote:
>> On Thu, 18 Nov 2021, Stanislav Lisovskiy
>> wrote:
>> > +static bool icl_need_wm1_wa(struct drm_i915_private *i915,
>> > + enum plane_id plane_id)
>>
>> Com
On 11/24/21 10:42, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* drm/i915/ttm: Async migration (rev11)
*URL:* https://patchwork.freedesktop.org/series/96798/
*State:*failure
*Details:*
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21672/index.html
On 23/11/2021 22:39, Arunpravin wrote:
On 18/11/21 12:09 am, Matthew Auld wrote:
On 16/11/2021 20:18, Arunpravin wrote:
- Make drm_buddy_alloc a single function to handle
range allocation and non-range allocation demands
- Implemented a new function alloc_range() which allocates
the
On Wed, Nov 24, 2021 at 12:23:08PM +0200, Jani Nikula wrote:
> On Thu, 18 Nov 2021, Stanislav Lisovskiy
> wrote:
> > Bug in the register unit which results in WM1 register
> > used when only WM0 is enabled on cursor.
> > Software workaround is when only WM0 enabled on cursor,
> > copy contents of
On Thu, 18 Nov 2021, Stanislav Lisovskiy wrote:
> Bug in the register unit which results in WM1 register
> used when only WM0 is enabled on cursor.
> Software workaround is when only WM0 enabled on cursor,
> copy contents of CUR_WM_0[30:0] (exclude the enable bit)
> into CUR_WM_1[30:0].
>
> v2: -
On Fri, 19 Nov 2021, Ville Syrjälä wrote:
> On Mon, Nov 15, 2021 at 02:12:47PM -0500, Rodrigo Vivi wrote:
>> On Fri, Nov 12, 2021 at 09:38:06PM +0200, Ville Syrjala wrote:
>> > From: Ville Syrjälä
>> >
>> > Use REG_BIT() & co. for PIPEMISC* bits, and while at it
>> > fill in the missing ditherin
On Mon, 22 Nov 2021, Alan Previn wrote:
> Add GuC's error capture output structures and definitions as how
> they would appear in GuC log buffer's error capture subregion after
> an error state capture G2H event notification.
If it's for decoding data, should they all have __packed?
>
> Signed-o
On Mon, 22 Nov 2021, Alan Previn wrote:
> + {
> + .list = gen12lp_vec_class_regs,
> + .num_regs = (sizeof(gen12lp_vec_class_regs) / sizeof(struct
> __guc_mmio_reg_descr)),
> + .owner = GUC_CAPTURE_LIST_INDEX_PF,
> + .type = GUC_CAPTURE_LIST_TYPE
On Tue, 23 Nov 2021, Michal Wajdeczko wrote:
> Hi,
>
> just few random nits below
>
> -Michal
>
>
> On 23.11.2021 00:03, Alan Previn wrote:
>> +/* Define all device tables of GuC error capture register lists */
>> +
>> +/* Gen12 LP
>> *
On Tue 23-11-21 12:24:18, Luis Chamberlain wrote:
> There is no need to user boiler plate code to specify a set of base
> directories we're going to stuff sysctls under. Simplify this by using
> register_sysctl() and specifying the directory path directly.
>
> // pycocci sysctl-subdir-register-sys
On Tue 23-11-21 12:24:20, Luis Chamberlain wrote:
> From: Xiaoming Ni
>
> There is no need to user boiler plate code to specify a set of base
> directories we're going to stuff sysctls under. Simplify this by using
> register_sysctl() and specifying the directory path directly.
>
> Move inotify_
On Mon, 22 Nov 2021, Hans de Goede wrote:
> Hi,
>
> On 11/22/21 12:15, Jani Nikula wrote:
>> Follow the convention of corresponding .h for .c.
>>
>> Signed-off-by: Jani Nikula
>
> This series looks good to me:
>
> Reviewed-by: Hans de Goede
>
> For the series.
Thanks for the reviews, pushed to
== Series Details ==
Series: drm/i915/ttm: Async migration (rev11)
URL : https://patchwork.freedesktop.org/series/96798/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10921_full -> Patchwork_21672_full
Summary
---
**
On Wed, Nov 24, 2021 at 11:23:55AM +0200, Stanislav Lisovskiy wrote:
> Tile4 patch still needs an ack from userspace,
> IGT tests and some essential fixes, related to
> new .plane_caps attribute being added.
>
> This reverts commit 3c542cfa8266e3364938d055b3d548b7bed7f08e.
>
> Signed-off-by: Stan
Tile4 patch still needs an ack from userspace,
IGT tests and some essential fixes, related to
new .plane_caps attribute being added.
This reverts commit 3c542cfa8266e3364938d055b3d548b7bed7f08e.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_display.c | 1 -
drivers
On Wed, 24 Nov 2021, cgel@gmail.com wrote:
> From: Yao Jing
>
> 'asm/smp.h' included in 'drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c' is
> duplicated. It is clearly included on the 12 line.
>
> Reported-by: Zeal Robot
> Signed-off-by: Yao Jing
The correct fix is [1].
If you keep sending pat
On 23/11/2021 19:52, Rodrigo Vivi wrote:
On Tue, Nov 23, 2021 at 09:39:25AM +, Tvrtko Ursulin wrote:
On 17/11/2021 22:49, Vinay Belgaumkar wrote:
From: Chris Wilson
Everytime we come to the end of a virtual engine's context, re-randomise
it's siblings[]. As we schedule the siblings' ta
On 24/11/2021 08:04, Zbigniew Kempczyński wrote:
On Tue, Nov 23, 2021 at 09:49:04AM +, Tvrtko Ursulin wrote:
On 22/11/2021 19:13, Zbigniew Kempczyński wrote:
In short - we want to enforce alignment == 0 for gen4+ GEM object
settings.
Before we merge this we need to inspect all UMD we ex
== Series Details ==
Series: drm/i915/ttm: Async migration (rev11)
URL : https://patchwork.freedesktop.org/series/96798/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10921 -> Patchwork_21672
Summary
---
**SUCCESS**
On Tue, Nov 23, 2021 at 09:49:04AM +, Tvrtko Ursulin wrote:
>
> On 22/11/2021 19:13, Zbigniew Kempczyński wrote:
> > In short - we want to enforce alignment == 0 for gen4+ GEM object
> > settings.
> >
> > Before we merge this we need to inspect all UMD we expect can use
> > this. My investiga
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