[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Use less in contexts steal guc id test (rev2)
== Series Details == Series: drm/i915/selftests: Use less in contexts steal guc id test (rev2) URL : https://patchwork.freedesktop.org/series/99179/ State : success == Summary == CI Bug Log - changes from CI_DRM_11120 -> Patchwork_22068 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22068/index.html Participating hosts (46 -> 39) -- Additional (1): fi-pnv-d510 Missing(8): fi-ilk-m540 fi-hsw-4200u fi-glk-dsi fi-icl-u2 fi-bsw-cyan fi-cfl-guc fi-ctg-p8600 fi-bdw-samus Known issues Here are the changes found in Patchwork_22068 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3@smem: - fi-bdw-5557u: [PASS][1] -> [INCOMPLETE][2] ([i915#146]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22068/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html * igt@i915_selftest@live@execlists: - fi-bsw-nick:[PASS][3] -> [INCOMPLETE][4] ([i915#2940]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22068/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@hangcheck: - fi-hsw-4770:[PASS][5] -> [INCOMPLETE][6] ([i915#3303]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22068/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html * igt@prime_vgem@basic-userptr: - fi-pnv-d510:NOTRUN -> [SKIP][7] ([fdo#109271]) +57 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22068/fi-pnv-d510/igt@prime_v...@basic-userptr.html * igt@runner@aborted: - fi-bsw-nick:NOTRUN -> [FAIL][8] ([fdo#109271] / [i915#1436] / [i915#3428] / [i915#4312]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22068/fi-bsw-nick/igt@run...@aborted.html - fi-hsw-4770:NOTRUN -> [FAIL][9] ([fdo#109271] / [i915#1436] / [i915#4312]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22068/fi-hsw-4770/igt@run...@aborted.html Possible fixes * igt@gem_exec_suspend@basic-s0@smem: - fi-tgl-1115g4: [FAIL][10] ([i915#1888]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/fi-tgl-1115g4/igt@gem_exec_suspend@basic...@smem.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22068/fi-tgl-1115g4/igt@gem_exec_suspend@basic...@smem.html Warnings * igt@gem_flink_basic@bad-flink: - fi-skl-6600u: [INCOMPLETE][12] ([i915#4547]) -> [FAIL][13] ([i915#4547]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22068/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html * igt@runner@aborted: - fi-skl-6600u: [FAIL][14] ([i915#2722] / [i915#4312]) -> [FAIL][15] ([i915#4312]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/fi-skl-6600u/igt@run...@aborted.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22068/fi-skl-6600u/igt@run...@aborted.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303 [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547 Build changes - * Linux: CI_DRM_11120 -> Patchwork_22068 CI-20190529: 20190529 CI_DRM_11120: d8e524ded1a6cb24bbd2da0785b04f199c03f1b9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6330: f73008bac9a8db0779264b170f630483e9165764 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_22068: 4ce4c5eb82bc734fe588163e92855de6190b8b5d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4ce4c5eb82bc drm/i915/selftests: Use less in contexts steal guc id test == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22068/index.html
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Don't restart WL for every frequency step (rev2)
== Series Details == Series: drm/i915/selftests: Don't restart WL for every frequency step (rev2) URL : https://patchwork.freedesktop.org/series/99109/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11120_full -> Patchwork_22066_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22066_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22066_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22066_full: ### IGT changes ### Possible regressions * igt@i915_pm_sseu@full-enable: - shard-skl: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22066/shard-skl3/igt@i915_pm_s...@full-enable.html Known issues Here are the changes found in Patchwork_22066_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@in-flight-1us: - shard-tglb: [PASS][2] -> [TIMEOUT][3] ([i915#3063]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-tglb2/igt@gem_...@in-flight-1us.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22066/shard-tglb1/igt@gem_...@in-flight-1us.html * igt@gem_eio@in-flight-contexts-10ms: - shard-skl: NOTRUN -> [TIMEOUT][4] ([i915#3063]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22066/shard-skl1/igt@gem_...@in-flight-contexts-10ms.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-glk: [PASS][5] -> [FAIL][6] ([i915#2842]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-glk8/igt@gem_exec_fair@basic-none-sh...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22066/shard-glk4/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-apl: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl6/igt@gem_exec_fair@basic-n...@vcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22066/shard-apl7/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-tglb7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22066/shard-tglb8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-kbl3/igt@gem_exec_fair@basic-pace-s...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22066/shard-kbl6/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22066/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs0.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][15] -> [SKIP][16] ([i915#2190]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-tglb1/igt@gem_huc_c...@huc-copy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22066/shard-tglb7/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@heavy-multi: - shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22066/shard-kbl4/igt@gem_lmem_swapp...@heavy-multi.html * igt@gem_lmem_swapping@heavy-verify-multi: - shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22066/shard-skl8/igt@gem_lmem_swapp...@heavy-verify-multi.html * igt@gem_render_copy@linear-to-vebox-y-tiled: - shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271]) +42 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22066/shard-apl6/igt@gem_render_c...@linear-to-vebox-y-tiled.html * igt@gem_userptr_blits@unsync-unmap-cycles: - shard-tglb: NOTRUN -> [SKIP][20] ([i915#3297]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22066/shard-tglb3/igt@gem_userptr_bl...@unsync-unmap-cycles.html - shard-iclb: NOTRUN -> [SKIP][21] ([i915#3297]) [21]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dg2: Add Wa_18018781329 (rev4)
== Series Details ==
Series: drm/i915/dg2: Add Wa_18018781329 (rev4)
URL : https://patchwork.freedesktop.org/series/99128/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11120 -> Patchwork_22067
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22067 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22067, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22067/index.html
Participating hosts (46 -> 40)
--
Additional (1): fi-pnv-d510
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-icl-u2 fi-bsw-cyan fi-ctg-p8600
bat-jsl-2 fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22067:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@gtt:
- fi-bdw-5557u: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22067/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html
Known issues
Here are the changes found in Patchwork_22067 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-skl-6600u: NOTRUN -> [SKIP][3] ([fdo#109271]) +21 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22067/fi-skl-6600u/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html
* igt@gem_huc_copy@huc-copy:
- fi-skl-6600u: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22067/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22067/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][6] -> [INCOMPLETE][7] ([i915#3303])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22067/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u: NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22067/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#533])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22067/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510:NOTRUN -> [SKIP][10] ([fdo#109271]) +57 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22067/fi-pnv-d510/igt@prime_v...@basic-userptr.html
* igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#1436] /
[i915#4312])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22067/fi-hsw-4770/igt@run...@aborted.html
Possible fixes
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: [INCOMPLETE][12] ([i915#4547]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22067/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][14] ([i915#4269]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22067/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dg2: Add Wa_18018781329 (rev4)
== Series Details == Series: drm/i915/dg2: Add Wa_18018781329 (rev4) URL : https://patchwork.freedesktop.org/series/99128/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Add Wa_18018781329 (rev4)
== Series Details == Series: drm/i915/dg2: Add Wa_18018781329 (rev4) URL : https://patchwork.freedesktop.org/series/99128/ State : warning == Summary == $ dim checkpatch origin/drm-tip 68a2eaef0efa drm/i915/dg2: Add Wa_18018781329 -:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #9: From: Intel-gfx On Behalf Of Matt Roper -:49: ERROR:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Intel-gfx On Behalf Of Matt Roper' total: 1 errors, 1 warnings, 0 checks, 22 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Don't restart WL for every frequency step (rev2)
== Series Details == Series: drm/i915/selftests: Don't restart WL for every frequency step (rev2) URL : https://patchwork.freedesktop.org/series/99109/ State : success == Summary == CI Bug Log - changes from CI_DRM_11120 -> Patchwork_22066 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22066/index.html Participating hosts (46 -> 38) -- Missing(8): fi-ilk-m540 fi-hsw-4200u fi-icl-u2 fi-bsw-cyan fi-ctg-p8600 fi-kbl-8809g bat-jsl-2 fi-bdw-samus Known issues Here are the changes found in Patchwork_22066 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3@smem: - fi-skl-6600u: [PASS][1] -> [INCOMPLETE][2] ([i915#4547]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22066/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html Possible fixes * igt@i915_selftest@live@hangcheck: - bat-dg1-6: [DMESG-FAIL][3] ([i915#4494]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22066/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [DMESG-WARN][5] ([i915#4269]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22066/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269 [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494 [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547 Build changes - * Linux: CI_DRM_11120 -> Patchwork_22066 CI-20190529: 20190529 CI_DRM_11120: d8e524ded1a6cb24bbd2da0785b04f199c03f1b9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6330: f73008bac9a8db0779264b170f630483e9165764 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_22066: 5de2e0f578c006f2906607ed12f54e0d68e699c5 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5de2e0f578c0 drm/i915/selftests: Don't restart WL for every frequency step == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22066/index.html
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Use less in contexts steal guc id test
== Series Details ==
Series: drm/i915/selftests: Use less in contexts steal guc id test
URL : https://patchwork.freedesktop.org/series/99179/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11120 -> Patchwork_22065
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22065 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22065, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22065/index.html
Participating hosts (46 -> 42)
--
Additional (1): fi-pnv-d510
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22065:
### IGT changes ###
Possible regressions
* igt@gem_exec_suspend@basic-s0@smem:
- fi-kbl-soraka: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/fi-kbl-soraka/igt@gem_exec_suspend@basic...@smem.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22065/fi-kbl-soraka/igt@gem_exec_suspend@basic...@smem.html
Known issues
Here are the changes found in Patchwork_22065 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][3] -> [INCOMPLETE][4] ([i915#3303])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22065/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510:NOTRUN -> [SKIP][5] ([fdo#109271]) +57 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22065/fi-pnv-d510/igt@prime_v...@basic-userptr.html
* igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][6] ([fdo#109271] / [i915#1436] /
[i915#4312])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22065/fi-hsw-4770/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
Build changes
-
* Linux: CI_DRM_11120 -> Patchwork_22065
CI-20190529: 20190529
CI_DRM_11120: d8e524ded1a6cb24bbd2da0785b04f199c03f1b9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6330: f73008bac9a8db0779264b170f630483e9165764 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22065: 4ef99dc507baf4dd0d5a666c83785fa1f69001ef @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4ef99dc507ba drm/i915/selftests: Use less in contexts steal guc id test
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22065/index.html
Re: [Intel-gfx] [PATCH] drm/i915/display: Move cdclk checks to atomic check
On Tue, Jan 18, 2022 at 08:23:26PM +, Srivatsa, Anusha wrote:
>
>
> > -Original Message-
> > From: Jani Nikula
> > Sent: Tuesday, December 21, 2021 1:03 AM
> > To: Srivatsa, Anusha ; intel-
> > g...@lists.freedesktop.org
> > Cc: Syrjala, Ville
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Move cdclk checks to
> > atomic check
> >
> > On Fri, 17 Dec 2021, Anusha Srivatsa wrote:
> > > Checking cdclk conditions during atomic check and preparing for commit
> > > phase so we can have atomic commit as simple as possible. Add the
> > > specific steps to be taken during cdclk changes, prepare for
> > > squashing, crawling and modeset scenarios.
> > > Rename functions intel_cdclk_can_squash() and
> > > intel_cdclk_can_crawl() since they no longer simply check if squashing
> > > and crawling can be performed.
> > >
> > > Cc: Matt Roper
> > > Signed-off-by: Anusha Srivatsa
> > > ---
> > > drivers/gpu/drm/i915/display/intel_cdclk.c| 130 +++---
> > > drivers/gpu/drm/i915/display/intel_cdclk.h| 3 +-
> > > .../drm/i915/display/intel_display_power.c| 2 +-
> > > drivers/gpu/drm/i915/i915_drv.h | 13 ++
> > > 4 files changed, 96 insertions(+), 52 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > index 249f81a80eb7..4a5ddc202c05 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > @@ -1698,12 +1698,15 @@ static void bxt_set_cdclk(struct
> > drm_i915_private *dev_priv,
> > > const struct intel_cdclk_config *cdclk_config,
> > > enum pipe pipe)
> > > {
> > > + struct cdclk_steps *cdclk_steps = dev_priv->cdclk.steps;
> > > int cdclk = cdclk_config->cdclk;
> > > int vco = cdclk_config->vco;
> > > + u32 squash_ctl = 0;
> > > u32 val;
> > > u16 waveform;
> > > int clock;
> > > int ret;
> > > + int i;
> > >
> > > /* Inform power controller of upcoming frequency change. */
> > > if (DISPLAY_VER(dev_priv) >= 11)
> > > @@ -1727,40 +1730,43 @@ static void bxt_set_cdclk(struct
> > drm_i915_private *dev_priv,
> > > return;
> > > }
> > >
> > > - if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 &&
> > vco > 0) {
> > > - if (dev_priv->cdclk.hw.vco != vco)
> > > + for (i = 0; i < CDCLK_ACTIONS; i++) {
> > > + switch (cdclk_steps[i].action) {
> > > + case CDCLK_MODESET:
> > > + if (DISPLAY_VER(dev_priv) >= 11) {
> > > + if (dev_priv->cdclk.hw.vco != 0 &&
> > > + dev_priv->cdclk.hw.vco != vco)
> > > + icl_cdclk_pll_disable(dev_priv);
> > > +
> > > + if (dev_priv->cdclk.hw.vco != vco)
> > > + icl_cdclk_pll_enable(dev_priv, vco);
> > > + } else {
> > > + if (dev_priv->cdclk.hw.vco != 0 &&
> > > + dev_priv->cdclk.hw.vco != vco)
> > > + bxt_de_pll_disable(dev_priv);
> > > +
> > > + if (dev_priv->cdclk.hw.vco != vco)
> > > + bxt_de_pll_enable(dev_priv, vco);
> > > + }
> > > + clock = cdclk;
> > > + break;
> > > + case CDCLK_CRAWL:
> > > adlp_cdclk_pll_crawl(dev_priv, vco);
> > > - } else if (DISPLAY_VER(dev_priv) >= 11) {
> > > - if (dev_priv->cdclk.hw.vco != 0 &&
> > > - dev_priv->cdclk.hw.vco != vco)
> > > - icl_cdclk_pll_disable(dev_priv);
> > > -
> > > - if (dev_priv->cdclk.hw.vco != vco)
> > > - icl_cdclk_pll_enable(dev_priv, vco);
> > > - } else {
> > > - if (dev_priv->cdclk.hw.vco != 0 &&
> > > - dev_priv->cdclk.hw.vco != vco)
> > > - bxt_de_pll_disable(dev_priv);
> > > -
> > > - if (dev_priv->cdclk.hw.vco != vco)
> > > - bxt_de_pll_enable(dev_priv, vco);
> > > - }
> > > -
> > > - waveform = cdclk_squash_waveform(dev_priv, cdclk);
> > > -
> > > - if (waveform)
> > > - clock = vco / 2;
> > > - else
> > > - clock = cdclk;
> > > -
> > > - if (has_cdclk_squasher(dev_priv)) {
> > > - u32 squash_ctl = 0;
> > > -
> > > - if (waveform)
> > > + clock = cdclk;
> > > + break;
> > > + case CDCLK_SQUASH:
> > > + waveform = cdclk_squash_waveform(dev_priv,
> > cdclk_steps[i].cdclk);
> > > + clock = vco / 2;
> > > squash_ctl = CDCLK_SQUASH_ENABLE |
> > > - CDCLK_SQUASH_WINDOW_SIZE(0xf) |
> > waveform;
> > > -
> > > - intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
> > > + CDCLK_SQUASH_WINDOW_SIZE(0xf)
> > | waveform;
> > > +
Re: [Intel-gfx] [PATCH] drm/i915/rpl-s: Add stepping info
On Fri, Jan 21, 2022 at 11:30:23AM -0800, Anusha Srivatsa wrote:
> Add stepping-substepping info in
> accordance to BSpec changes.
>
> Bspec: 53655
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/intel_step.c | 11 ++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_step.c
> b/drivers/gpu/drm/i915/intel_step.c
> index a4b16b9e2e55..74cb9dadcab9 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -122,6 +122,11 @@ static const struct intel_step_info
> dg2_g11_revid_step_tbl[] = {
> [0x5] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 },
> };
>
> +static const struct intel_step_info adls_rpls_revids[] = {
> + [0x4] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_D0 },
> + [0xC] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_C0 },
> +};
> +
> void intel_step_init(struct drm_i915_private *i915)
> {
> const struct intel_step_info *revids = NULL;
> @@ -129,7 +134,11 @@ void intel_step_init(struct drm_i915_private *i915)
> int revid = INTEL_REVID(i915);
> struct intel_step_info step = {};
>
> - if (IS_DG2_G10(i915)) {
> +
> + if (IS_ADLS_RPLS(i915)) {
> + revids = adls_rpls_revids;
> + size = ARRAY_SIZE(adls_rpls_revids);
> + } else if (IS_DG2_G10(i915)) {
We try to keep if/else ladders sorted by platforms' logical progression,
so this should go right above the 'IS_ALDERLAKE_S' case rather than at
the top.
It looks crazy that the revision ID goes backward for the newer
stepping, but that really is how it's supposed to be on this platform.
You might want to mention that in the commit message just so people
don't wonder if it's some kind of mistake/typo.
Matt
> revids = dg2_g10_revid_step_tbl;
> size = ARRAY_SIZE(dg2_g10_revid_step_tbl);
> } else if (IS_DG2_G11(i915)) {
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dg2: Add Wa_18018781329 (rev3)
On Fri, Jan 21, 2022 at 04:35:12PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/dg2: Add Wa_18018781329 (rev3) > URL : https://patchwork.freedesktop.org/series/99128/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8 -> Patchwork_22059 > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_22059 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_22059, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/index.html > > Participating hosts (48 -> 42) > -- > > Additional (1): fi-kbl-soraka > Missing(7): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-adlp-4 > fi-ctg-p8600 fi-pnv-d510 fi-bdw-samus > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_22059: > > ### IGT changes ### > > Possible regressions > > * igt@i915_selftest@live@guc: > - fi-rkl-guc: [PASS][1] -> [DMESG-WARN][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-rkl-guc/igt@i915_selftest@l...@guc.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-rkl-guc/igt@i915_selftest@l...@guc.html <3> [266.138736] i915 :00:02.0: [drm] *ERROR* AUX USBC2/DDI TC2/PHY D: did not complete or timeout within 10ms (status 0xad4003ff) This display error is not related to the GT workaround being applied here. Pressing the re-test button again... Matt > > > Known issues > > > Here are the changes found in Patchwork_22059 that come from known issues: > > ### IGT changes ### > > Issues hit > > * igt@amdgpu/amd_basic@semaphore: > - fi-bdw-5557u: NOTRUN -> [SKIP][3] ([fdo#109271]) +31 similar > issues >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html > > * igt@gem_exec_fence@basic-busy@bcs0: > - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271]) +8 similar issues >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html > > * igt@gem_huc_copy@huc-copy: > - fi-skl-6600u: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190]) >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html > - fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190]) >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html > > * igt@gem_lmem_swapping@parallel-random-engines: > - fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 > similar issues >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-kbl-soraka/igt@gem_lmem_swapp...@parallel-random-engines.html > > * igt@gem_lmem_swapping@verify-random: > - fi-skl-6600u: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 > similar issues >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html > > * igt@i915_selftest@live@gt_pm: > - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][9] ([i915#1886] / > [i915#2291]) >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html > > * igt@kms_chamelium@dp-edid-read: > - fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) > +8 similar issues >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-kbl-soraka/igt@kms_chamel...@dp-edid-read.html > > * igt@kms_chamelium@vga-edid-read: > - fi-skl-6600u: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) > +8 similar issues >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html > - fi-bdw-5557u: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) > +8 similar issues >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-bdw-5557u/igt@kms_chamel...@vga-edid-read.html > > * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: > - fi-skl-6600u: NOTRUN -> [SKIP][13] ([fdo#109271]) +21 similar > issues >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html > > * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: > - fi-skl-6600u: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#533]) >[14]: >
Re: [Intel-gfx] [PATCH] drm/i915: nuke local versions of WARN_ON/WARN_ON_ONCE
On Fri, Jan 21, 2022 at 03:29:57PM +0200, Jani Nikula wrote: In general, we should avoid redefining kernel macros like this. It can get confusing, and what gets used will depend on whether the header is included or not. Moreover, we should prefer drm_WARN_ON() and drm_WARN_ON_ONCE() anyway, which include the stringified error condition in the message. Signed-off-by: Jani Nikula Reviewed-by: Lucas De Marchi Lucas De Marchi
[Intel-gfx] ✓ Fi.CI.IGT: success for Fix up request cancel
== Series Details == Series: Fix up request cancel URL : https://patchwork.freedesktop.org/series/99173/ State : success == Summary == CI Bug Log - changes from CI_DRM_8_full -> Patchwork_22063_full Summary --- **SUCCESS** No regressions found. Participating hosts (10 -> 10) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_22063_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-apl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [FAIL][48], [PASS][49], [PASS][50]) ([i915#4386]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl8/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl8/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl8/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl7/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl7/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl7/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl7/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl6/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl6/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl6/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl4/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl4/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl4/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl3/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl3/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl3/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl2/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl2/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl2/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl2/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl2/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl1/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl1/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl1/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl1/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/shard-apl8/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/shard-apl8/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/shard-apl8/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/shard-apl7/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/shard-apl7/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/shard-apl7/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/shard-apl6/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/shard-apl6/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/shard-apl6/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/shard-apl4/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/shard-apl4/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/shard-apl4/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/shard-apl4/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/shard-apl4/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/shard-apl3/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/shard-apl3/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/shard-apl3/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/shard-apl2/boot.html [44]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: drm device based logging conversions (rev2)
== Series Details == Series: drm/i915/display: drm device based logging conversions (rev2) URL : https://patchwork.freedesktop.org/series/99151/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8 -> Patchwork_22064 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22064 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22064, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22064/index.html Participating hosts (51 -> 41) -- Additional (1): fi-kbl-soraka Missing(11): fi-ilk-m540 shard-tglu bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-ctg-p8600 fi-pnv-d510 shard-rkl shard-dg1 fi-bdw-samus Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22064: ### CI changes ### Possible regressions * boot: - fi-ilk-650: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-ilk-650/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22064/fi-ilk-650/boot.html Known issues Here are the changes found in Patchwork_22064 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271]) +8 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22064/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_exec_suspend@basic-s0@smem: - fi-tgl-1115g4: [PASS][4] -> [FAIL][5] ([i915#1888]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-tgl-1115g4/igt@gem_exec_suspend@basic...@smem.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22064/fi-tgl-1115g4/igt@gem_exec_suspend@basic...@smem.html * igt@gem_flink_basic@bad-flink: - fi-skl-6600u: NOTRUN -> [INCOMPLETE][6] ([i915#4547]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22064/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22064/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22064/fi-kbl-soraka/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@i915_selftest@live@gem_contexts: - fi-kbl-soraka: NOTRUN -> [DMESG-WARN][9] ([i915#4391]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22064/fi-kbl-soraka/igt@i915_selftest@live@gem_contexts.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][10] ([i915#1886] / [i915#2291]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22064/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_chamelium@dp-edid-read: - fi-kbl-soraka: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22064/fi-kbl-soraka/igt@kms_chamel...@dp-edid-read.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22064/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@runner@aborted: - fi-bdw-5557u: NOTRUN -> [FAIL][13] ([i915#2426] / [i915#4312]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22064/fi-bdw-5557u/igt@run...@aborted.html Possible fixes * igt@gem_exec_suspend@basic-s3@smem: - fi-bdw-5557u: [INCOMPLETE][14] ([i915#146]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22064/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html * igt@i915_selftest@live@hangcheck: - bat-dg1-6: [DMESG-FAIL][16] ([i915#4494]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22064/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [DMESG-WARN][18] ([i915#4269]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [19]:
[Intel-gfx] [PATCH] drm/i915/selftests: Use less in contexts steal guc id test
Using more guc_ids in the stealing guc id test has no real benefit. Tearing down lots of contexts all at the same time takes a bit of time due to the H2G / G2H ping-pong with the GuC. On some slower platforms this can cause timeous when flushing the test as the GT isn't idle when this ping-pong is happening. Reduce the number of guc ids to speed up the flushing of the test. Link: https://gitlab.freedesktop.org/drm/intel/-/issues/4821 Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c index d3327b802b761..a115894d5896e 100644 --- a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c @@ -157,7 +157,7 @@ static int intel_guc_steal_guc_ids(void *arg) wakeref = intel_runtime_pm_get(gt->uncore->rpm); engine = intel_selftest_find_any_engine(gt); sv = guc->submission_state.num_guc_ids; - guc->submission_state.num_guc_ids = 4096; + guc->submission_state.num_guc_ids = 512; /* Create spinner to block requests in below loop */ ce[context_index] = intel_context_create(engine); -- 2.34.1
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/rpl-s: Add stepping info
== Series Details == Series: drm/i915/rpl-s: Add stepping info URL : https://patchwork.freedesktop.org/series/99162/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8_full -> Patchwork_22061_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22061_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22061_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22061_full: ### IGT changes ### Possible regressions * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-skl5/igt@gem_soft...@noreloc-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22061/shard-skl8/igt@gem_soft...@noreloc-s3.html Warnings * igt@kms_flip@flip-vs-fences-interruptible@a-vga1: - shard-snb: [DMESG-WARN][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb2/igt@kms_flip@flip-vs-fences-interrupti...@a-vga1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22061/shard-snb5/igt@kms_flip@flip-vs-fences-interrupti...@a-vga1.html Known issues Here are the changes found in Patchwork_22061_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-apl: ([PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29]) -> ([PASS][30], [PASS][31], [FAIL][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54]) ([i915#4386]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl3/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl8/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl8/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl8/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl1/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl1/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl1/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl1/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl7/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl2/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl7/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl2/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl7/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl7/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl2/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl6/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl2/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl6/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl2/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl6/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl4/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl4/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl4/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl3/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl3/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22061/shard-apl1/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22061/shard-apl1/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22061/shard-apl1/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22061/shard-apl1/boot.html [34]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: drm device based logging conversions (rev2)
== Series Details == Series: drm/i915/display: drm device based logging conversions (rev2) URL : https://patchwork.freedesktop.org/series/99151/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: drm device based logging conversions (rev2)
== Series Details == Series: drm/i915/display: drm device based logging conversions (rev2) URL : https://patchwork.freedesktop.org/series/99151/ State : warning == Summary == $ dim checkpatch origin/drm-tip ef1acbbf5c73 drm/i915/snps: convert to drm device based logging a3babf263cdf drm/i915/pps: convert to drm device based logging 61548a8ffb4e drm/i915/hotplug: convert to drm device based logging 65346aba056f drm/i915/dp: convert to drm device based logging 1bb50368c977 drm/i915/plane: convert to drm device based logging and WARN 7fe0ce0527bc drm/i915/sprite: convert to drm device based logging c9b9891ad33e drm/i915/lspcon: convert to drm device based logging -:488: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #488: FILE: drivers/gpu/drm/i915/display/intel_lspcon.c:696: + drm_err(>drm, "LSPCON init failed on port %c\n", port_name(dig_port->base.port)); total: 0 errors, 0 warnings, 1 checks, 451 lines checked 3c5cf4bdfcf2 drm/i915/cdclk: update intel_dump_cdclk_config() logging 4e5d67787a94 drm/i915/cdclk: convert to drm device based logging
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix errors when there is no free DSM
== Series Details == Series: drm/i915: Fix errors when there is no free DSM URL : https://patchwork.freedesktop.org/series/99161/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8_full -> Patchwork_22060_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22060_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22060_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22060_full: ### IGT changes ### Possible regressions * igt@drm_mm@all@replace: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-skl10/igt@drm_mm@a...@replace.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/shard-skl3/igt@drm_mm@a...@replace.html Known issues Here are the changes found in Patchwork_22060_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@parallel-out-fence: - shard-iclb: [PASS][3] -> [SKIP][4] ([i915#4525]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-iclb2/igt@gem_exec_balan...@parallel-out-fence.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/shard-iclb3/igt@gem_exec_balan...@parallel-out-fence.html * igt@gem_exec_fair@basic-deadline: - shard-skl: NOTRUN -> [FAIL][5] ([i915#2846]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/shard-skl10/igt@gem_exec_f...@basic-deadline.html - shard-glk: [PASS][6] -> [FAIL][7] ([i915#2846]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-glk4/igt@gem_exec_f...@basic-deadline.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/shard-glk4/igt@gem_exec_f...@basic-deadline.html - shard-apl: NOTRUN -> [FAIL][8] ([i915#2846]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/shard-apl2/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/shard-iclb2/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/shard-kbl3/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_params@no-blt: - shard-tglb: NOTRUN -> [SKIP][13] ([fdo#109283]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/shard-tglb5/igt@gem_exec_par...@no-blt.html * igt@gem_exec_suspend@basic-s3@smem: - shard-apl: [PASS][14] -> [DMESG-WARN][15] ([i915#180]) +4 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl7/igt@gem_exec_suspend@basic...@smem.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/shard-apl4/igt@gem_exec_suspend@basic...@smem.html * igt@gem_lmem_swapping@parallel-random: - shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +2 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/shard-skl8/igt@gem_lmem_swapp...@parallel-random.html * igt@gem_spin_batch@user-each: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#2898]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-skl8/igt@gem_spin_ba...@user-each.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/shard-skl6/igt@gem_spin_ba...@user-each.html * igt@gem_userptr_blits@dmabuf-sync: - shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3323]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/shard-apl7/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gem_userptr_blits@vma-merge: - shard-skl: NOTRUN -> [FAIL][20] ([i915#3318]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/shard-skl9/igt@gem_userptr_bl...@vma-merge.html * igt@i915_pm_dc@dc9-dpms: - shard-iclb: [PASS][21] -> [SKIP][22] ([i915#4281]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-iclb7/igt@i915_pm...@dc9-dpms.html [22]:
[Intel-gfx] ✓ Fi.CI.BAT: success for Fix up request cancel
== Series Details ==
Series: Fix up request cancel
URL : https://patchwork.freedesktop.org/series/99173/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8 -> Patchwork_22063
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/index.html
Participating hosts (51 -> 41)
--
Additional (1): fi-kbl-soraka
Missing(11): fi-ilk-m540 fi-bxt-dsi shard-tglu bat-dg1-5 fi-hsw-4200u
fi-bsw-cyan bat-adlp-4 fi-ctg-p8600 shard-rkl shard-dg1 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_22063 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +8 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/fi-kbl-soraka/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][4] ([i915#1886] / [i915#2291])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/fi-kbl-soraka/igt@kms_chamel...@dp-edid-read.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#533])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][7] ([i915#2426] / [i915#4312])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/fi-bdw-5557u/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_suspend@basic-s3@smem:
- fi-bdw-5557u: [INCOMPLETE][8] ([i915#146]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
Warnings
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-tgl-1115g4: [SKIP][10] ([fdo#109315] / [i915#2575]) -> [SKIP][11]
([fdo#109315] / [i915#1888] / [i915#2575])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-tgl-1115g4/igt@amdgpu/amd_pr...@i915-to-amd.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/fi-tgl-1115g4/igt@amdgpu/amd_pr...@i915-to-amd.html
* igt@gem_exec_suspend@basic-s3:
- fi-skl-6600u: [FAIL][12] ([i915#4547]) -> [INCOMPLETE][13]
([i915#4547])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22063/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Fix up request cancel
== Series Details == Series: Fix up request cancel URL : https://patchwork.freedesktop.org/series/99173/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix up request cancel
== Series Details == Series: Fix up request cancel URL : https://patchwork.freedesktop.org/series/99173/ State : warning == Summary == $ dim checkpatch origin/drm-tip 14373962443a drm/i915: Add request cancel low level trace point 5fee0be402d5 drm/i915/guc: Cancel requests immediately -:8: WARNING:TYPO_SPELLING: 'cancelation' may be misspelled - perhaps 'cancellation'? #8: cancelation. This not only cancels the request as fast as possible, it ^^^ total: 0 errors, 1 warnings, 0 checks, 106 lines checked
[Intel-gfx] ✗ Fi.CI.BAT: failure for discrete card 64K page support (rev2)
== Series Details ==
Series: discrete card 64K page support (rev2)
URL : https://patchwork.freedesktop.org/series/99119/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8 -> Patchwork_22062
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22062 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22062, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22062/index.html
Participating hosts (51 -> 43)
--
Additional (2): fi-kbl-soraka bat-adls-5
Missing(10): fi-ilk-m540 shard-tglu fi-hsw-4200u fi-bsw-cyan bat-adlp-4
fi-ctg-p8600 fi-kbl-8809g shard-rkl shard-dg1 fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22062:
### IGT changes ###
Possible regressions
* igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22062/fi-hsw-4770/igt@run...@aborted.html
- bat-dg1-6: NOTRUN -> [FAIL][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22062/bat-dg1-6/igt@run...@aborted.html
- fi-rkl-11600: NOTRUN -> [FAIL][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22062/fi-rkl-11600/igt@run...@aborted.html
- bat-dg1-5: NOTRUN -> [FAIL][4]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22062/bat-dg1-5/igt@run...@aborted.html
- fi-bwr-2160:NOTRUN -> [FAIL][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22062/fi-bwr-2160/igt@run...@aborted.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {bat-adls-5}: NOTRUN -> [FAIL][6]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22062/bat-adls-5/igt@run...@aborted.html
- {bat-adlp-6}: [FAIL][7] ([i915#4312]) -> [FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/bat-adlp-6/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22062/bat-adlp-6/igt@run...@aborted.html
- {bat-jsl-2}:NOTRUN -> [FAIL][9]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22062/bat-jsl-2/igt@run...@aborted.html
- {fi-jsl-1}: NOTRUN -> [FAIL][10]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22062/fi-jsl-1/igt@run...@aborted.html
- {bat-jsl-1}:NOTRUN -> [FAIL][11]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22062/bat-jsl-1/igt@run...@aborted.html
- {fi-ehl-2}: NOTRUN -> [FAIL][12]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22062/fi-ehl-2/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_22062 that come from known issues:
### IGT changes ###
Issues hit
* igt@runner@aborted:
- fi-ilk-650: NOTRUN -> [FAIL][13] ([i915#2426])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22062/fi-ilk-650/igt@run...@aborted.html
- fi-pnv-d510:NOTRUN -> [FAIL][14] ([i915#2403])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22062/fi-pnv-d510/igt@run...@aborted.html
- fi-bdw-gvtdvm: NOTRUN -> [FAIL][15] ([i915#2426])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22062/fi-bdw-gvtdvm/igt@run...@aborted.html
- fi-cfl-8109u: NOTRUN -> [FAIL][16] ([i915#2426])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22062/fi-cfl-8109u/igt@run...@aborted.html
- fi-icl-u2: NOTRUN -> [FAIL][17] ([i915#2426] / [i915#3690])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22062/fi-icl-u2/igt@run...@aborted.html
- fi-glk-dsi: NOTRUN -> [FAIL][18] ([i915#2426] / [k.org#202321])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22062/fi-glk-dsi/igt@run...@aborted.html
- fi-snb-2520m: NOTRUN -> [FAIL][19] ([i915#2426])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22062/fi-snb-2520m/igt@run...@aborted.html
- fi-kbl-soraka: NOTRUN -> [FAIL][20] ([i915#2426])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22062/fi-kbl-soraka/igt@run...@aborted.html
- fi-kbl-7500u: NOTRUN -> [FAIL][21] ([i915#2426])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22062/fi-kbl-7500u/igt@run...@aborted.html
- fi-cml-u2: NOTRUN -> [FAIL][22] ([i915#2426])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22062/fi-cml-u2/igt@run...@aborted.html
- fi-ivb-3770:NOTRUN -> [FAIL][23] ([i915#2426])
[23]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for discrete card 64K page support (rev2)
== Series Details == Series: discrete card 64K page support (rev2) URL : https://patchwork.freedesktop.org/series/99119/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for discrete card 64K page support (rev2)
== Series Details == Series: discrete card 64K page support (rev2) URL : https://patchwork.freedesktop.org/series/99119/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9c4bfcca2ca8 drm/i915: add needs_compact_pt flag 5a250a5f13c2 drm/i915: enforce min GTT alignment for discrete cards -:288: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #288: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:457: + if (offset < hole_start + aligned_size) -:300: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #300: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:481: + if (offset + aligned_size > hole_end) -:318: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #318: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:497: + if (offset < hole_start + aligned_size) -:330: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #330: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:520: + if (offset + aligned_size > hole_end) -:348: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #348: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:536: + if (offset < hole_start + aligned_size) -:360: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #360: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:560: + if (offset + aligned_size > hole_end) -:378: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #378: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:576: + if (offset < hole_start + aligned_size) -:390: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #390: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:599: + if (offset + aligned_size > hole_end) total: 0 errors, 8 warnings, 0 checks, 433 lines checked 5e90ba474749 drm/i915: support 64K GTT pages for discrete cards 5f922bd05cb4 drm/i915: add gtt misalignment test 678731d7e28a drm/i915/uapi: document behaviour for DG2 64K support
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/rpl-s: Add stepping info
== Series Details == Series: drm/i915/rpl-s: Add stepping info URL : https://patchwork.freedesktop.org/series/99162/ State : success == Summary == CI Bug Log - changes from CI_DRM_8 -> Patchwork_22061 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22061/index.html Participating hosts (51 -> 42) -- Additional (1): fi-kbl-soraka Missing(10): fi-ilk-m540 shard-tglu fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-ctg-p8600 fi-pnv-d510 shard-rkl shard-dg1 fi-bdw-samus Known issues Here are the changes found in Patchwork_22061 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +8 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22061/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_exec_suspend@basic-s0@smem: - fi-tgl-1115g4: [PASS][2] -> [FAIL][3] ([i915#1888]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-tgl-1115g4/igt@gem_exec_suspend@basic...@smem.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22061/fi-tgl-1115g4/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - fi-skl-6600u: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22061/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html - fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22061/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22061/fi-kbl-soraka/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - fi-skl-6600u: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22061/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][8] ([i915#1886] / [i915#2291]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22061/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_chamelium@dp-edid-read: - fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22061/fi-kbl-soraka/igt@kms_chamel...@dp-edid-read.html * igt@kms_chamelium@vga-edid-read: - fi-skl-6600u: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22061/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-skl-6600u: NOTRUN -> [SKIP][11] ([fdo#109271]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22061/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-skl-6600u: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22061/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html - fi-kbl-soraka: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#533]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22061/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@primary_page_flip: - fi-skl-6600u: NOTRUN -> [FAIL][14] ([i915#4547]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22061/fi-skl-6600u/igt@kms_psr@primary_page_flip.html * igt@runner@aborted: - fi-bdw-5557u: NOTRUN -> [FAIL][15] ([i915#2029] / [i915#4312]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22061/fi-bdw-5557u/igt@run...@aborted.html Possible fixes * igt@gem_exec_suspend@basic-s3@smem: - fi-bdw-5557u: [INCOMPLETE][16] ([i915#146]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22061/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#2029]:
Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Don't check CT descriptor status before CT write / read
On Fri, Jan 21, 2022 at 09:28:46AM +0200, Jani Nikula wrote: > On Thu, 20 Jan 2022, Matthew Brost wrote: > > Don't check CT descriptor status, unless CONFIG_DRM_I915_DEBUG_GUC is > > set, before CT write / read as this could result in a read across the > > PCIe bus thus adding latency to every CT write / read. On well behavied > > systems this vaue should always read as zero. For some reason it doesn't > > the CT channel is broken and will eventually recover from a GT reset, > > albeit the GT reset will not be triggered immediately by seeing that > > descriptor status is non-zero. > > > > v2: > > (CI) > > - Fix build error (hide corrupted label in write function behind > > CONFIG_DRM_I915_DEBUG_GUC) > > > > Signed-off-by: Matthew Brost > > --- > > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 ++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > > b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > > index de89d40abd38d..948cf31429412 100644 > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > > @@ -379,8 +379,10 @@ static int ct_write(struct intel_guc_ct *ct, > > u32 *cmds = ctb->cmds; > > unsigned int i; > > > > +#ifdef CONFIG_DRM_I915_DEBUG_GUC > > if (unlikely(desc->status)) > > goto corrupted; > > +#endif > > Please don't add #ifdefs inline. You can use > IS_ENABLED(CONFIG_DRM_I915_DEBUG_GUC) in if statements, but otherwise > the code needs to be split out to a separate function. > Sure, but I feel like I've actually been by someone else to not use the IS_ENABLED macro and use ifdefs inlines... Matt > BR, > Jani. > > > > > GEM_BUG_ON(tail > size); > > > > @@ -445,11 +447,13 @@ static int ct_write(struct intel_guc_ct *ct, > > > > return 0; > > > > +#ifdef CONFIG_DRM_I915_DEBUG_GUC > > corrupted: > > CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", > > desc->head, desc->tail, desc->status); > > ctb->broken = true; > > return -EPIPE; > > +#endif > > } > > > > /** > > @@ -815,8 +819,10 @@ static int ct_read(struct intel_guc_ct *ct, struct > > ct_incoming_msg **msg) > > if (unlikely(ctb->broken)) > > return -EPIPE; > > > > +#ifdef CONFIG_DRM_I915_DEBUG_GUC > > if (unlikely(desc->status)) > > goto corrupted; > > +#endif > > > > GEM_BUG_ON(head > size); > > -- > Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/rpl-s: Add stepping info
== Series Details == Series: drm/i915/rpl-s: Add stepping info URL : https://patchwork.freedesktop.org/series/99162/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9ecaf578e456 drm/i915/rpl-s: Add stepping info -:33: CHECK:LINE_SPACING: Please don't use multiple blank lines #33: FILE: drivers/gpu/drm/i915/intel_step.c:137: + total: 0 errors, 0 warnings, 1 checks, 23 lines checked
[Intel-gfx] [PATCH 2/2] drm/i915/guc: Cancel requests immediately
Change the preemption timeout to the smallest possible value (1 us) when
disabling scheduling to cancel a request and restore it after
cancelation. This not only cancels the request as fast as possible, it
fixes a bug where the preemption timeout is 0 which results in the
schedule disable hanging forever.
Reported-by: Jani Saarinen
Fixes: 62eaf0ae217d4 ("drm/i915/guc: Support request cancellation")
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/4960
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 5 ++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 46 +++
2 files changed, 31 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 30cd81ad8911a..730998823dbea 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -198,6 +198,11 @@ struct intel_context {
* each priority bucket
*/
u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
+ /**
+* @preemption_timeout: preemption timeout of the context, used
+* to restore this value after request cancellation
+*/
+ u32 preemption_timeout;
} guc_state;
struct {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 3918f1be114fa..966947c450253 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2147,7 +2147,8 @@ static inline u32 get_children_join_value(struct
intel_context *ce,
return __get_parent_scratch(ce)->join[child_index].semaphore;
}
-static void guc_context_policy_init(struct intel_engine_cs *engine,
+static void guc_context_policy_init(struct intel_context *ce,
+ struct intel_engine_cs *engine,
struct guc_lrc_desc *desc)
{
desc->policy_flags = 0;
@@ -2157,7 +2158,8 @@ static void guc_context_policy_init(struct
intel_engine_cs *engine,
/* NB: For both of these, zero means disabled. */
desc->execution_quantum = engine->props.timeslice_duration_ms * 1000;
- desc->preemption_timeout = engine->props.preempt_timeout_ms * 1000;
+ ce->guc_state.preemption_timeout = engine->props.preempt_timeout_ms *
1000;
+ desc->preemption_timeout = ce->guc_state.preemption_timeout;
}
static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
@@ -2193,7 +2195,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
bool loop)
desc->hw_context_desc = ce->lrc.lrca;
desc->priority = ce->guc_state.prio;
desc->context_flags = CONTEXT_REGISTRATION_FLAG_KMD;
- guc_context_policy_init(engine, desc);
+ guc_context_policy_init(ce, engine, desc);
/*
* If context is a parent, we need to register a process descriptor
@@ -2226,7 +2228,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
bool loop)
desc->hw_context_desc = child->lrc.lrca;
desc->priority = ce->guc_state.prio;
desc->context_flags = CONTEXT_REGISTRATION_FLAG_KMD;
- guc_context_policy_init(engine, desc);
+ guc_context_policy_init(child, engine, desc);
}
clear_children_join_go_memory(ce);
@@ -2409,6 +2411,19 @@ static u16 prep_context_pending_disable(struct
intel_context *ce)
return ce->guc_id.id;
}
+static void __guc_context_set_preemption_timeout(struct intel_guc *guc,
+u16 guc_id,
+u32 preemption_timeout)
+{
+ u32 action[] = {
+ INTEL_GUC_ACTION_SET_CONTEXT_PREEMPTION_TIMEOUT,
+ guc_id,
+ preemption_timeout
+ };
+
+ intel_guc_send_busy_loop(guc, action, ARRAY_SIZE(action), 0, true);
+}
+
static struct i915_sw_fence *guc_context_block(struct intel_context *ce)
{
struct intel_guc *guc = ce_to_guc(ce);
@@ -2442,8 +2457,10 @@ static struct i915_sw_fence *guc_context_block(struct
intel_context *ce)
spin_unlock_irqrestore(>guc_state.lock, flags);
- with_intel_runtime_pm(runtime_pm, wakeref)
+ with_intel_runtime_pm(runtime_pm, wakeref) {
+ __guc_context_set_preemption_timeout(guc, guc_id, 1);
__guc_context_sched_disable(guc, ce, guc_id);
+ }
return >guc_state.blocked;
}
@@ -2492,8 +2509,10 @@ static void guc_context_unblock(struct intel_context *ce)
spin_unlock_irqrestore(>guc_state.lock, flags);
- if (enable) {
- with_intel_runtime_pm(runtime_pm, wakeref)
+ with_intel_runtime_pm(runtime_pm, wakeref) {
+
[Intel-gfx] [PATCH 1/2] drm/i915: Add request cancel low level trace point
Add request cancel trace point guarded by
CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINT.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context.h | 1 +
drivers/gpu/drm/i915/i915_trace.h | 10 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
b/drivers/gpu/drm/i915/gt/intel_context.h
index d8c74bbf9aae2..3aed4d77f116c 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -124,6 +124,7 @@ intel_context_is_pinned(struct intel_context *ce)
static inline void intel_context_cancel_request(struct intel_context *ce,
struct i915_request *rq)
{
+ trace_i915_request_cancel(rq);
GEM_BUG_ON(!ce->ops->cancel_request);
return ce->ops->cancel_request(ce, rq);
}
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index 37b5c9e9d260e..d0a11a8bb0ca3 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -324,6 +324,11 @@ DEFINE_EVENT(i915_request, i915_request_add,
);
#if defined(CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS)
+DEFINE_EVENT(i915_request, i915_request_cancel,
+TP_PROTO(struct i915_request *rq),
+TP_ARGS(rq)
+);
+
DEFINE_EVENT(i915_request, i915_request_guc_submit,
TP_PROTO(struct i915_request *rq),
TP_ARGS(rq)
@@ -497,6 +502,11 @@ DEFINE_EVENT(intel_context, intel_context_do_unpin,
#else
#if !defined(TRACE_HEADER_MULTI_READ)
+static inline void
+trace_i915_request_cancel(struct i915_request *rq)
+{
+}
+
static inline void
trace_i915_request_guc_submit(struct i915_request *rq)
{
--
2.34.1
[Intel-gfx] [PATCH 0/2] Fix up request cancel
Fix request cancellation + add request cancel low level trace point. Signed-off-by: Matthew Brost Matthew Brost (2): drm/i915: Add request cancel low level trace point drm/i915/guc: Cancel requests immediately drivers/gpu/drm/i915/gt/intel_context.h | 1 + drivers/gpu/drm/i915/gt/intel_context_types.h | 5 ++ .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 46 +++ drivers/gpu/drm/i915/i915_trace.h | 10 4 files changed, 42 insertions(+), 20 deletions(-) -- 2.34.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix errors when there is no free DSM
== Series Details == Series: drm/i915: Fix errors when there is no free DSM URL : https://patchwork.freedesktop.org/series/99161/ State : success == Summary == CI Bug Log - changes from CI_DRM_8 -> Patchwork_22060 Summary --- **WARNING** Minor unknown changes coming with Patchwork_22060 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22060, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/index.html Participating hosts (51 -> 41) -- Additional (1): fi-kbl-soraka Missing(11): fi-ilk-m540 shard-tglu fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-ctg-p8600 fi-kbl-8809g fi-pnv-d510 shard-rkl shard-dg1 fi-bdw-samus Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22060: ### IGT changes ### Warnings * igt@i915_selftest@live@hangcheck: - bat-dg1-5: [DMESG-FAIL][1] ([i915#4494]) -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html Known issues Here are the changes found in Patchwork_22060 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][3] ([fdo#109271]) +31 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271]) +8 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_exec_suspend@basic-s0@smem: - fi-tgl-1115g4: [PASS][5] -> [FAIL][6] ([i915#1888]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-tgl-1115g4/igt@gem_exec_suspend@basic...@smem.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/fi-tgl-1115g4/igt@gem_exec_suspend@basic...@smem.html * igt@gem_flink_basic@bad-flink: - fi-skl-6600u: NOTRUN -> [FAIL][7] ([i915#4547]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/fi-kbl-soraka/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@i915_selftest@live@execlists: - fi-bsw-nick:[PASS][10] -> [INCOMPLETE][11] ([i915#2940]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][12] ([i915#1886] / [i915#2291]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_chamelium@dp-edid-read: - fi-kbl-soraka: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/fi-kbl-soraka/igt@kms_chamel...@dp-edid-read.html * igt@kms_chamelium@vga-edid-read: - fi-bdw-5557u: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/fi-bdw-5557u/igt@kms_chamel...@vga-edid-read.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-kbl-soraka: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#533]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@runner@aborted: - fi-bsw-nick:NOTRUN -> [FAIL][16] ([fdo#109271] / [i915#1436] / [i915#3428] / [i915#4312]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22060/fi-bsw-nick/igt@run...@aborted.html Possible fixes * igt@gem_exec_suspend@basic-s3@smem: - fi-bdw-5557u: [INCOMPLETE][17] ([i915#146]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html [18]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix errors when there is no free DSM
== Series Details == Series: drm/i915: Fix errors when there is no free DSM URL : https://patchwork.freedesktop.org/series/99161/ State : warning == Summary == $ dim checkpatch origin/drm-tip a3097f607fae drm/i915: Fix errors when there is no free DSM -:20: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #20: i915 :8c:00.0: [drm:i915_gem_init_stolen [i915]] GEN6_STOLEN_RESERVED = 0x0003ff800185 total: 0 errors, 1 warnings, 0 checks, 28 lines checked
Re: [Intel-gfx] [PATCH] drm/i915: Fix errors when there is no free DSM
On Fri, Jan 21, 2022 at 11:24:50AM -0800, José Roberto de Souza wrote:
> Part of DSM(data stolen memory) is reserved for HW functions and GUC
> and in some platform this reserved block takes the whole DSM leaving
> no memory to allocated by i915_gem_object_create_stolen() and friends.
>
> In such cases i915_gem_init_stolen() was not calling drm_mm_init()
> and returning 0, causing errors later when testing memory
> (intel_memory_region_memtest()) and in intel_memory_regions_hw_probe()
> saying setup of memory region failed:
I think you might that a bit backwards. There are a lot of other cases
where don't initialize stolen and still return 0 here. But in those cases
we *don't* call drm_mm_init() and everyone just uses drm_mm_initialized()
to check whether stolen was actually initialized or not.
>
> checking generic (9100 30) vs hw (23fe7e00 200)
> checking generic (9100 30) vs hw (2378 8)
> i915 :8c:00.0: [drm:i915_gem_init_stolen [i915]] GEN6_STOLEN_RESERVED =
> 0x0003ff800185
> i915 :8c:00.0: [drm:i915_gem_init_stolen [i915]] Memory reserved for
> graphics device: 8192K, usable: 0K
> i915 :8c:00.0: Failed to read back from memory region:[mem
> 0x3ff80-0x3ff7f] at [0x237bff80 + 0x] for
> i915_gem_stolen_lmem_setup [i915]; wrote 0, read (ff, ff, ff)
> i915 :8c:00.0: [drm] *ERROR* Failed to setup region 6 (type=3:0), error
> -22
> [drm:intel_gt_setup_lmem [i915]] LMEM: debug trace data region:
> [0x0-0x200]
> i915 :8c:00.0: [drm:intel_gt_setup_lmem [i915]] Local memory: [mem
> 0x-0x3faff]
>
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 9 ++---
> drivers/gpu/drm/i915/intel_memory_region.c | 3 +++
> 2 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> index 26975d8577760..6e90357b2d1fd 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> @@ -495,13 +495,16 @@ static int i915_gem_init_stolen(struct
> intel_memory_region *mem)
>* memory, so just consider the start. */
> reserved_total = stolen_top - reserved_base;
>
> + i915->stolen_usable_size =
> + resource_size(>dsm) - reserved_total;
> +
> drm_dbg(>drm,
> "Memory reserved for graphics device: %lluK, usable: %lluK\n",
> (u64)resource_size(>dsm) >> 10,
> - ((u64)resource_size(>dsm) - reserved_total) >> 10);
> + (u64)i915->stolen_usable_size >> 10);
>
> - i915->stolen_usable_size =
> - resource_size(>dsm) - reserved_total;
> + if (i915->stolen_usable_size == 0)
> + return -ENOMEM;
>
> /* Basic memrange allocator for stolen space. */
> drm_mm_init(>mm.stolen, 0, i915->stolen_usable_size);
> diff --git a/drivers/gpu/drm/i915/intel_memory_region.c
> b/drivers/gpu/drm/i915/intel_memory_region.c
> index c70d7e286a512..317d67fa3a36e 100644
> --- a/drivers/gpu/drm/i915/intel_memory_region.c
> +++ b/drivers/gpu/drm/i915/intel_memory_region.c
> @@ -324,6 +324,9 @@ int intel_memory_regions_hw_probe(struct drm_i915_private
> *i915)
>
> if (IS_ERR(mem)) {
> err = PTR_ERR(mem);
> + if (err == -ENOMEM)
> + continue;
> +
> drm_err(>drm,
> "Failed to setup region(%d) type=%d\n",
> err, type);
> --
> 2.34.1
--
Ville Syrjälä
Intel
[Intel-gfx] [PATCH v4 4/5] drm/i915: add gtt misalignment test
add test to check handling of misaligned offsets and sizes
v4:
* remove spurious blank lines
* explicitly cast intel_region_id to intel_memory_type in misaligned_pin
Reported-by: kernel test robot
Signed-off-by: Robert Beckett
---
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 128 ++
1 file changed, 128 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index b80788a2b7f9..f082b5ff3b5e 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -22,10 +22,12 @@
*
*/
+#include "gt/intel_gtt.h"
#include
#include
#include "gem/i915_gem_context.h"
+#include "gem/i915_gem_region.h"
#include "gem/selftests/mock_context.h"
#include "gt/intel_context.h"
#include "gt/intel_gpu_commands.h"
@@ -1067,6 +1069,120 @@ static int shrink_boom(struct i915_address_space *vm,
return err;
}
+static int misaligned_case(struct i915_address_space *vm, struct
intel_memory_region *mr,
+ u64 addr, u64 size, unsigned long flags)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ int err = 0;
+ u64 expected_vma_size, expected_node_size;
+
+ obj = i915_gem_object_create_region(mr, size, 0, 0);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_put;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, addr | flags);
+ if (err)
+ goto err_put;
+ i915_vma_unpin(vma);
+
+ if (!drm_mm_node_allocated(>node)) {
+ err = -EINVAL;
+ goto err_put;
+ }
+
+ if (i915_vma_misplaced(vma, 0, 0, addr | flags)) {
+ err = -EINVAL;
+ goto err_put;
+ }
+
+ expected_vma_size = round_up(size, 1 <<
(ffs(vma->resource->page_sizes_gtt) - 1));
+ expected_node_size = expected_vma_size;
+
+ if (IS_DG2(vm->i915) && i915_gem_object_is_lmem(obj)) {
+ /* dg2 should expand lmem node to 2MB */
+ expected_vma_size = round_up(size, I915_GTT_PAGE_SIZE_64K);
+ expected_node_size = round_up(size, I915_GTT_PAGE_SIZE_2M);
+ }
+
+ if (vma->size != expected_vma_size || vma->node.size !=
expected_node_size) {
+ err = i915_vma_unbind(vma);
+ err = -EBADSLT;
+ goto err_put;
+ }
+
+ err = i915_vma_unbind(vma);
+ if (err)
+ goto err_put;
+
+ GEM_BUG_ON(drm_mm_node_allocated(>node));
+
+err_put:
+ i915_gem_object_put(obj);
+ cleanup_freed_objects(vm->i915);
+ return err;
+}
+
+static int misaligned_pin(struct i915_address_space *vm,
+ u64 hole_start, u64 hole_end,
+ unsigned long end_time)
+{
+ struct intel_memory_region *mr;
+ enum intel_region_id id;
+ unsigned long flags = PIN_OFFSET_FIXED | PIN_USER;
+ int err = 0;
+ u64 hole_size = hole_end - hole_start;
+
+ if (i915_is_ggtt(vm))
+ flags |= PIN_GLOBAL;
+
+ for_each_memory_region(mr, vm->i915, id) {
+ u64 min_alignment = i915_vm_min_alignment(vm, (enum
intel_memory_type)id);
+ u64 size = min_alignment;
+ u64 addr = round_up(hole_start + (hole_size / 2),
min_alignment);
+
+ /* we can't test < 4k alignment due to flags being encoded in
lower bits */
+ if (min_alignment != I915_GTT_PAGE_SIZE_4K) {
+ err = misaligned_case(vm, mr, addr + (min_alignment /
2), size, flags);
+ /* misaligned should error with -EINVAL*/
+ if (!err)
+ err = -EBADSLT;
+ if (err != -EINVAL)
+ return err;
+ }
+
+ /* test for vma->size expansion to min page size */
+ err = misaligned_case(vm, mr, addr, PAGE_SIZE, flags);
+ if (min_alignment > hole_size) {
+ if (!err)
+ err = -EBADSLT;
+ else if (err == -ENOSPC)
+ err = 0;
+ }
+ if (err)
+ return err;
+
+ /* test for intermediate size not expanding vma->size for large
alignments */
+ err = misaligned_case(vm, mr, addr, size / 2, flags);
+ if (min_alignment > hole_size) {
+ if (!err)
+ err = -EBADSLT;
+ else if (err == -ENOSPC)
+ err = 0;
+ }
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
static int
[Intel-gfx] [PATCH v4 3/5] drm/i915: support 64K GTT pages for discrete cards
From: Matthew Auld
discrete cards optimise 64K GTT pages for local-memory, since everything
should be allocated at 64K granularity. We say goodbye to sparse
entries, and instead get a compact 256B page-table for 64K pages,
which should be more cache friendly. 4K pages for local-memory
are no longer supported by the HW.
v4: don't return uninitialized err in igt_ppgtt_compact
Reported-by: kernel test robot
Signed-off-by: Matthew Auld
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
Signed-off-by: Robert Beckett
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 60 ++
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 108 +-
drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 1 +
4 files changed, 169 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index f36191ebf964..a7d9bdb85d70 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1478,6 +1478,65 @@ static int igt_ppgtt_sanity_check(void *arg)
return err;
}
+static int igt_ppgtt_compact(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem_object *obj;
+ int err;
+
+ /*
+* Simple test to catch issues with compact 64K pages -- since the pt is
+* compacted to 256B that gives us 32 entries per pt, however since the
+* backing page for the pt is 4K, any extra entries we might incorrectly
+* write out should be ignored by the HW. If ever hit such a case this
+* test should catch it since some of our writes would land in scratch.
+*/
+
+ if (!HAS_64K_PAGES(i915)) {
+ pr_info("device lacks compact 64K page support, skipping\n");
+ return 0;
+ }
+
+ if (!HAS_LMEM(i915)) {
+ pr_info("device lacks LMEM support, skipping\n");
+ return 0;
+ }
+
+ /* We want the range to cover multiple page-table boundaries. */
+ obj = i915_gem_object_create_lmem(i915, SZ_4M, 0);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ err = i915_gem_object_pin_pages_unlocked(obj);
+ if (err)
+ goto out_put;
+
+ if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_64K) {
+ pr_info("LMEM compact unable to allocate huge-page(s)\n");
+ goto out_unpin;
+ }
+
+ /*
+* Disable 2M GTT pages by forcing the page-size to 64K for the GTT
+* insertion.
+*/
+ obj->mm.page_sizes.sg = I915_GTT_PAGE_SIZE_64K;
+
+ err = igt_write_huge(i915, obj);
+ if (err)
+ pr_err("LMEM compact write-huge failed\n");
+
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+out_put:
+ i915_gem_object_put(obj);
+
+ if (err == -ENOMEM)
+ err = 0;
+
+ return err;
+}
+
static int igt_tmpfs_fallback(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -1735,6 +1794,7 @@ int i915_gem_huge_page_live_selftests(struct
drm_i915_private *i915)
SUBTEST(igt_tmpfs_fallback),
SUBTEST(igt_ppgtt_smoke_huge),
SUBTEST(igt_ppgtt_sanity_check),
+ SUBTEST(igt_ppgtt_compact),
};
if (!HAS_PPGTT(i915)) {
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index c43e724afa9f..62471730266c 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -233,6 +233,8 @@ static u64 __gen8_ppgtt_clear(struct i915_address_space *
const vm,
start, end, lvl);
} else {
unsigned int count;
+ unsigned int pte = gen8_pd_index(start, 0);
+ unsigned int num_ptes;
u64 *vaddr;
count = gen8_pt_count(start, end);
@@ -242,10 +244,18 @@ static u64 __gen8_ppgtt_clear(struct i915_address_space *
const vm,
atomic_read(>used));
GEM_BUG_ON(!count || count >= atomic_read(>used));
+ num_ptes = count;
+ if (pt->is_compact) {
+ GEM_BUG_ON(num_ptes % 16);
+ GEM_BUG_ON(pte % 16);
+ num_ptes /= 16;
+ pte /= 16;
+ }
+
vaddr = px_vaddr(pt);
- memset64(vaddr + gen8_pd_index(start, 0),
+ memset64(vaddr + pte,
vm->scratch[0]->encode,
-count);
+num_ptes);
[Intel-gfx] [PATCH v4 5/5] drm/i915/uapi: document behaviour for DG2 64K support
From: Matthew Auld
On discrete platforms like DG2, we need to support a minimum page size
of 64K when dealing with device local-memory. This is quite tricky for
various reasons, so try to document the new implicit uapi for this.
v3: fix typos and less emphasis
v2: Fixed suggestions on formatting [Daniel]
Signed-off-by: Matthew Auld
Signed-off-by: Ramalingam C
Signed-off-by: Robert Beckett
Acked-by: Jordan Justen
Reviewed-by: Ramalingam C
cc: Simon Ser
cc: Pekka Paalanen
Cc: Jordan Justen
Cc: Kenneth Graunke
Cc: mesa-...@lists.freedesktop.org
Cc: Tony Ye
Cc: Slawomir Milczarek
---
include/uapi/drm/i915_drm.h | 44 -
1 file changed, 39 insertions(+), 5 deletions(-)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 5e678917da70..77e5e74c32c1 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1118,10 +1118,16 @@ struct drm_i915_gem_exec_object2 {
/**
* When the EXEC_OBJECT_PINNED flag is specified this is populated by
* the user with the GTT offset at which this object will be pinned.
+*
* When the I915_EXEC_NO_RELOC flag is specified this must contain the
* presumed_offset of the object.
+*
* During execbuffer2 the kernel populates it with the value of the
* current GTT offset of the object, for future presumed_offset writes.
+*
+* See struct drm_i915_gem_create_ext for the rules when dealing with
+* alignment restrictions with I915_MEMORY_CLASS_DEVICE, on devices with
+* minimum page sizes, like DG2.
*/
__u64 offset;
@@ -3145,11 +3151,39 @@ struct drm_i915_gem_create_ext {
*
* The (page-aligned) allocated size for the object will be returned.
*
-* Note that for some devices we have might have further minimum
-* page-size restrictions(larger than 4K), like for device local-memory.
-* However in general the final size here should always reflect any
-* rounding up, if for example using the
I915_GEM_CREATE_EXT_MEMORY_REGIONS
-* extension to place the object in device local-memory.
+*
+* DG2 64K min page size implications:
+*
+* On discrete platforms, starting from DG2, we have to contend with GTT
+* page size restrictions when dealing with I915_MEMORY_CLASS_DEVICE
+* objects. Specifically the hardware only supports 64K or larger GTT
+* page sizes for such memory. The kernel will already ensure that all
+* I915_MEMORY_CLASS_DEVICE memory is allocated using 64K or larger page
+* sizes underneath.
+*
+* Note that the returned size here will always reflect any required
+* rounding up done by the kernel, i.e 4K will now become 64K on devices
+* such as DG2.
+*
+* Special DG2 GTT address alignment requirement:
+*
+* The GTT alignment will also need to be at least 2M for such objects.
+*
+* Note that due to how the hardware implements 64K GTT page support, we
+* have some further complications:
+*
+* 1) The entire PDE (which covers a 2MB virtual address range), must
+* contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same
+* PDE is forbidden by the hardware.
+*
+* 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM
+* objects.
+*
+* To keep things simple for userland, we mandate that any GTT mappings
+* must be aligned to and rounded up to 2MB. As this only wastes virtual
+* address space and avoids userland having to copy any needlessly
+* complicated PDE sharing scheme (coloring) and only affects DG2, this
+* is deemed to be a good compromise.
*/
__u64 size;
/**
--
2.25.1
[Intel-gfx] [PATCH v4 0/5] discrete card 64K page support
This series continues support for 64K pages for discrete cards. It supersedes the 64K patches from https://patchwork.freedesktop.org/series/95686/#rev4 Changes since that series: - set min alignment for DG2 to 2MB in i915_address_space_init - replace coloring with simpler 2MB VA alignment for lmem buffers - enforce alignment to 2MB for lmem objects on DG2 in i915_vma_insert - expand vma reservation to round up to 2MB on DG2 in i915_vma_insert - add alignment test v2: rebase and fix for async vma that landed v3: * fix uapi doc typos * add needs_compact_pt flag patch * cleanup vma expansion to use vm->min_alignment instead of hard coding v4: * fix err return in igt_ppgtt_compact test * placate ci robot with explicit enum conversion in misaligned_pin * remove some blank lines Matthew Auld (3): drm/i915: enforce min GTT alignment for discrete cards drm/i915: support 64K GTT pages for discrete cards drm/i915/uapi: document behaviour for DG2 64K support Ramalingam C (1): drm/i915: add needs_compact_pt flag Robert Beckett (1): drm/i915: add gtt misalignment test .../gpu/drm/i915/gem/selftests/huge_pages.c | 60 + .../i915/gem/selftests/i915_gem_client_blt.c | 23 +- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 108 - drivers/gpu/drm/i915/gt/intel_gtt.c | 12 + drivers/gpu/drm/i915/gt/intel_gtt.h | 18 ++ drivers/gpu/drm/i915/gt/intel_ppgtt.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 10 +- drivers/gpu/drm/i915/i915_pci.c | 2 + drivers/gpu/drm/i915/i915_vma.c | 9 + drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 224 +++--- include/uapi/drm/i915_drm.h | 44 +++- 12 files changed, 460 insertions(+), 52 deletions(-) -- 2.25.1
[Intel-gfx] [PATCH v4 2/5] drm/i915: enforce min GTT alignment for discrete cards
From: Matthew Auld
For local-memory objects we need to align the GTT addresses
to 64K, both for the ppgtt and ggtt.
We need to support vm->min_alignment > 4K, depending
on the vm itself and the type of object we are inserting.
With this in mind update the GTT selftests to take this
into account.
For compact-pt we further align and pad lmem object GTT addresses
to 2MB to ensure PDEs contain consistent page sizes as
required by the HW.
v3:
* use needs_compact_pt flag to discriminate between
64K and 64K with compact-pt
* add i915_vm_obj_min_alignment
* use i915_vm_obj_min_alignment to round up vma reservation
if compact-pt instead of hard coding
Signed-off-by: Matthew Auld
Signed-off-by: Ramalingam C
Signed-off-by: Robert Beckett
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
.../i915/gem/selftests/i915_gem_client_blt.c | 23 +++--
drivers/gpu/drm/i915/gt/intel_gtt.c | 12 +++
drivers/gpu/drm/i915/gt/intel_gtt.h | 15 +++
drivers/gpu/drm/i915/i915_vma.c | 9 ++
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 96 ---
5 files changed, 114 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index c8ff8bf0986d..f0bfce53258f 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -39,6 +39,7 @@ struct tiled_blits {
struct blit_buffer scratch;
struct i915_vma *batch;
u64 hole;
+ u64 align;
u32 width;
u32 height;
};
@@ -410,14 +411,21 @@ tiled_blits_create(struct intel_engine_cs *engine, struct
rnd_state *prng)
goto err_free;
}
- hole_size = 2 * PAGE_ALIGN(WIDTH * HEIGHT * 4);
+ t->align = I915_GTT_PAGE_SIZE_2M; /* XXX worst case, derive from vm! */
+ t->align = max(t->align,
+ i915_vm_min_alignment(t->ce->vm, INTEL_MEMORY_LOCAL));
+ t->align = max(t->align,
+ i915_vm_min_alignment(t->ce->vm, INTEL_MEMORY_SYSTEM));
+
+ hole_size = 2 * round_up(WIDTH * HEIGHT * 4, t->align);
hole_size *= 2; /* room to maneuver */
- hole_size += 2 * I915_GTT_MIN_ALIGNMENT;
+ hole_size += 2 * t->align; /* padding on either side */
mutex_lock(>ce->vm->mutex);
memset(, 0, sizeof(hole));
err = drm_mm_insert_node_in_range(>ce->vm->mm, ,
- hole_size, 0, I915_COLOR_UNEVICTABLE,
+ hole_size, t->align,
+ I915_COLOR_UNEVICTABLE,
0, U64_MAX,
DRM_MM_INSERT_BEST);
if (!err)
@@ -428,7 +436,7 @@ tiled_blits_create(struct intel_engine_cs *engine, struct
rnd_state *prng)
goto err_put;
}
- t->hole = hole.start + I915_GTT_MIN_ALIGNMENT;
+ t->hole = hole.start + t->align;
pr_info("Using hole at %llx\n", t->hole);
err = tiled_blits_create_buffers(t, WIDTH, HEIGHT, prng);
@@ -455,7 +463,7 @@ static void tiled_blits_destroy(struct tiled_blits *t)
static int tiled_blits_prepare(struct tiled_blits *t,
struct rnd_state *prng)
{
- u64 offset = PAGE_ALIGN(t->width * t->height * 4);
+ u64 offset = round_up(t->width * t->height * 4, t->align);
u32 *map;
int err;
int i;
@@ -486,8 +494,7 @@ static int tiled_blits_prepare(struct tiled_blits *t,
static int tiled_blits_bounce(struct tiled_blits *t, struct rnd_state *prng)
{
- u64 offset =
- round_up(t->width * t->height * 4, 2 * I915_GTT_MIN_ALIGNMENT);
+ u64 offset = round_up(t->width * t->height * 4, 2 * t->align);
int err;
/* We want to check position invariant tiling across GTT eviction */
@@ -500,7 +507,7 @@ static int tiled_blits_bounce(struct tiled_blits *t, struct
rnd_state *prng)
/* Reposition so that we overlap the old addresses, and slightly off */
err = tiled_blit(t,
->buffers[2], t->hole + I915_GTT_MIN_ALIGNMENT,
+>buffers[2], t->hole + t->align,
>buffers[1], t->hole + 3 * offset / 2);
if (err)
return err;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 46be4197b93f..df23ebdfc994 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -223,6 +223,18 @@ void i915_address_space_init(struct i915_address_space
*vm, int subclass)
GEM_BUG_ON(!vm->total);
drm_mm_init(>mm, 0, vm->total);
+
+ memset64(vm->min_alignment, I915_GTT_MIN_ALIGNMENT,
+ARRAY_SIZE(vm->min_alignment));
+
+ if (HAS_64K_PAGES(vm->i915) &&
[Intel-gfx] [PATCH v4 1/5] drm/i915: add needs_compact_pt flag
From: Ramalingam C
Add a new platform flag, needs_compact_pt, to mark the requirement of
compact pt layout support for the ppGTT when using 64K GTT pages.
With this flag has_64k_pages will only indicate requirement of 64K
GTT page sizes or larger for device local memory access.
Suggested-by: Matthew Auld
Signed-off-by: Ramalingam C
Signed-off-by: Robert Beckett
---
drivers/gpu/drm/i915/i915_drv.h | 10 +++---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 44c1f98144b4..1258b7779705 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1512,12 +1512,16 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
/*
* Set this flag, when platform requires 64K GTT page sizes or larger for
- * device local memory access. Also this flag implies that we require or
- * at least support the compact PT layout for the ppGTT when using the 64K
- * GTT pages.
+ * device local memory access.
*/
#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
+/* Set this flag when platform doesn't allow both 64k pages and 4k pages in
+ * the same PT. this flag means we need to support compact PT layout for the
+ * ppGTT when using the 64K GTT pages.
+ */
+#define NEEDS_COMPACT_PT(dev_priv) (INTEL_INFO(dev_priv)->needs_compact_pt)
+
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 4081fd50ba9d..799b56569ef5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1028,6 +1028,7 @@ static const struct intel_device_info xehpsdv_info = {
PLATFORM(INTEL_XEHPSDV),
.display = { },
.has_64k_pages = 1,
+ .needs_compact_pt = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
@@ -1045,6 +1046,7 @@ static const struct intel_device_info dg2_info = {
.media.rel = 55,
PLATFORM(INTEL_DG2),
.has_64k_pages = 1,
+ .needs_compact_pt = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) |
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 3699b1c539ea..c8aaf646430c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -130,6 +130,7 @@ enum intel_ppgtt_type {
/* Keep has_* in alphabetical order */ \
func(has_64bit_reloc); \
func(has_64k_pages); \
+ func(needs_compact_pt); \
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
func(has_global_mocs); \
--
2.25.1
[Intel-gfx] [PATCH] drm/i915/rpl-s: Add stepping info
Add stepping-substepping info in
accordance to BSpec changes.
Bspec: 53655
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_step.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index a4b16b9e2e55..74cb9dadcab9 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -122,6 +122,11 @@ static const struct intel_step_info
dg2_g11_revid_step_tbl[] = {
[0x5] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 },
};
+static const struct intel_step_info adls_rpls_revids[] = {
+ [0x4] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_D0 },
+ [0xC] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_C0 },
+};
+
void intel_step_init(struct drm_i915_private *i915)
{
const struct intel_step_info *revids = NULL;
@@ -129,7 +134,11 @@ void intel_step_init(struct drm_i915_private *i915)
int revid = INTEL_REVID(i915);
struct intel_step_info step = {};
- if (IS_DG2_G10(i915)) {
+
+ if (IS_ADLS_RPLS(i915)) {
+ revids = adls_rpls_revids;
+ size = ARRAY_SIZE(adls_rpls_revids);
+ } else if (IS_DG2_G10(i915)) {
revids = dg2_g10_revid_step_tbl;
size = ARRAY_SIZE(dg2_g10_revid_step_tbl);
} else if (IS_DG2_G11(i915)) {
--
2.25.1
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: nuke local versions of WARN_ON/WARN_ON_ONCE
== Series Details == Series: drm/i915: nuke local versions of WARN_ON/WARN_ON_ONCE URL : https://patchwork.freedesktop.org/series/99155/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8_full -> Patchwork_22058_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22058_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22058_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22058_full: ### IGT changes ### Possible regressions * igt@kms_flip@flip-vs-suspend-interruptible@a-vga1: - shard-snb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb7/igt@kms_flip@flip-vs-suspend-interrupti...@a-vga1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/shard-snb4/igt@kms_flip@flip-vs-suspend-interrupti...@a-vga1.html Warnings * igt@gem_create@create-massive: - shard-iclb: [DMESG-WARN][3] ([i915#3002]) -> [DMESG-WARN][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-iclb8/igt@gem_cre...@create-massive.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/shard-iclb2/igt@gem_cre...@create-massive.html - shard-snb: [DMESG-WARN][5] ([i915#3002]) -> [DMESG-WARN][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb7/igt@gem_cre...@create-massive.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/shard-snb6/igt@gem_cre...@create-massive.html - shard-kbl: [DMESG-WARN][7] ([i915#3002]) -> [DMESG-WARN][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-kbl7/igt@gem_cre...@create-massive.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/shard-kbl1/igt@gem_cre...@create-massive.html - shard-tglb: [DMESG-WARN][9] ([i915#3002] / [i915#4856]) -> [DMESG-WARN][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-tglb2/igt@gem_cre...@create-massive.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/shard-tglb5/igt@gem_cre...@create-massive.html * igt@gem_userptr_blits@input-checking: - shard-skl: [DMESG-WARN][11] ([i915#3002]) -> [DMESG-WARN][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-skl6/igt@gem_userptr_bl...@input-checking.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/shard-skl8/igt@gem_userptr_bl...@input-checking.html - shard-tglb: [DMESG-WARN][13] ([i915#3002] / [i915#4857]) -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-tglb5/igt@gem_userptr_bl...@input-checking.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/shard-tglb2/igt@gem_userptr_bl...@input-checking.html - shard-apl: [DMESG-WARN][15] ([i915#3002]) -> [DMESG-WARN][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl2/igt@gem_userptr_bl...@input-checking.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/shard-apl4/igt@gem_userptr_bl...@input-checking.html - shard-glk: [DMESG-WARN][17] ([i915#3002]) -> [DMESG-WARN][18] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-glk8/igt@gem_userptr_bl...@input-checking.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/shard-glk5/igt@gem_userptr_bl...@input-checking.html Known issues Here are the changes found in Patchwork_22058_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-apl7/igt@gem_ctx_isolation@preservation...@vcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/shard-apl2/igt@gem_ctx_isolation@preservation...@vcs0.html * igt@gem_eio@kms: - shard-tglb: [PASS][21] -> [FAIL][22] ([i915#232]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-tglb6/igt@gem_...@kms.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/shard-tglb5/igt@gem_...@kms.html * igt@gem_exec_balancer@parallel-out-fence: - shard-iclb: [PASS][23] -> [SKIP][24] ([i915#4525]) +2 similar issues [23]:
[Intel-gfx] [PATCH] drm/i915: Fix errors when there is no free DSM
Part of DSM(data stolen memory) is reserved for HW functions and GUC
and in some platform this reserved block takes the whole DSM leaving
no memory to allocated by i915_gem_object_create_stolen() and friends.
In such cases i915_gem_init_stolen() was not calling drm_mm_init()
and returning 0, causing errors later when testing memory
(intel_memory_region_memtest()) and in intel_memory_regions_hw_probe()
saying setup of memory region failed:
checking generic (9100 30) vs hw (23fe7e00 200)
checking generic (9100 30) vs hw (2378 8)
i915 :8c:00.0: [drm:i915_gem_init_stolen [i915]] GEN6_STOLEN_RESERVED =
0x0003ff800185
i915 :8c:00.0: [drm:i915_gem_init_stolen [i915]] Memory reserved for
graphics device: 8192K, usable: 0K
i915 :8c:00.0: Failed to read back from memory region:[mem
0x3ff80-0x3ff7f] at [0x237bff80 + 0x] for
i915_gem_stolen_lmem_setup [i915]; wrote 0, read (ff, ff, ff)
i915 :8c:00.0: [drm] *ERROR* Failed to setup region 6 (type=3:0), error -22
[drm:intel_gt_setup_lmem [i915]] LMEM: debug trace data region: [0x0-0x200]
i915 :8c:00.0: [drm:intel_gt_setup_lmem [i915]] Local memory: [mem
0x-0x3faff]
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 9 ++---
drivers/gpu/drm/i915/intel_memory_region.c | 3 +++
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 26975d8577760..6e90357b2d1fd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -495,13 +495,16 @@ static int i915_gem_init_stolen(struct
intel_memory_region *mem)
* memory, so just consider the start. */
reserved_total = stolen_top - reserved_base;
+ i915->stolen_usable_size =
+ resource_size(>dsm) - reserved_total;
+
drm_dbg(>drm,
"Memory reserved for graphics device: %lluK, usable: %lluK\n",
(u64)resource_size(>dsm) >> 10,
- ((u64)resource_size(>dsm) - reserved_total) >> 10);
+ (u64)i915->stolen_usable_size >> 10);
- i915->stolen_usable_size =
- resource_size(>dsm) - reserved_total;
+ if (i915->stolen_usable_size == 0)
+ return -ENOMEM;
/* Basic memrange allocator for stolen space. */
drm_mm_init(>mm.stolen, 0, i915->stolen_usable_size);
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c
b/drivers/gpu/drm/i915/intel_memory_region.c
index c70d7e286a512..317d67fa3a36e 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -324,6 +324,9 @@ int intel_memory_regions_hw_probe(struct drm_i915_private
*i915)
if (IS_ERR(mem)) {
err = PTR_ERR(mem);
+ if (err == -ENOMEM)
+ continue;
+
drm_err(>drm,
"Failed to setup region(%d) type=%d\n",
err, type);
--
2.34.1
Re: [Intel-gfx] [PATCH 2/3] drm/i915/guc: Add work queue to trigger a GT reset
On 1/20/2022 20:31, Matthew Brost wrote:
The G2H handler needs to be flushed during a GT reset but a G2H
indicating engine reset failure can trigger a GT reset. Add a worker to
trigger the GT rest when an engine reset failure is received to break
this circular dependency.
v2:
(John Harrison)
- Store engine reset mask
- Fix typo in commit message
v3:
(John Harrison)
- Fix another typo in commit message
- s/reset_*/reset_fail_*/
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 9 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +--
2 files changed, 42 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 9d26a86fe557a..d59bbf49d1c2b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -119,6 +119,15 @@ struct intel_guc {
* function as it might be in an atomic context (no sleeping)
*/
struct work_struct destroyed_worker;
+ /**
+* @reset_fail_worker: worker to trigger a GT reset after an
+* engine reset fails
+*/
+ struct work_struct reset_fail_worker;
+ /**
+* @reset_fail_mask: mask of engines that failed to reset
+*/
+ intel_engine_mask_t reset_fail_mask;
} submission_state;
/**
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 3918f1be114fa..9a3f503d201aa 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1731,6 +1731,7 @@ void intel_guc_submission_reset_finish(struct intel_guc
*guc)
}
static void destroyed_worker_func(struct work_struct *w);
+static void reset_fail_worker_func(struct work_struct *w);
/*
* Set up the memory resources to be shared with the GuC (via the GGTT)
@@ -1761,6 +1762,8 @@ int intel_guc_submission_init(struct intel_guc *guc)
INIT_LIST_HEAD(>submission_state.destroyed_contexts);
INIT_WORK(>submission_state.destroyed_worker,
destroyed_worker_func);
+ INIT_WORK(>submission_state.reset_fail_worker,
+ reset_fail_worker_func);
guc->submission_state.guc_ids_bitmap =
bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL);
@@ -4026,6 +4029,26 @@ guc_lookup_engine(struct intel_guc *guc, u8 guc_class,
u8 instance)
return gt->engine_class[engine_class][instance];
}
+static void reset_fail_worker_func(struct work_struct *w)
+{
+ struct intel_guc *guc = container_of(w, struct intel_guc,
+
submission_state.reset_fail_worker);
+ struct intel_gt *gt = guc_to_gt(guc);
+ intel_engine_mask_t reset_fail_mask;
+ unsigned long flags;
+
+ spin_lock_irqsave(>submission_state.lock, flags);
+ reset_fail_mask = guc->submission_state.reset_fail_mask;
+ guc->submission_state.reset_fail_mask = 0;
+ spin_unlock_irqrestore(>submission_state.lock, flags);
+
+ if (likely(reset_fail_mask))
+ intel_gt_handle_error(gt, reset_fail_mask,
+ I915_ERROR_CAPTURE,
+ "GuC failed to reset engine mask=0x%x\n",
+ reset_fail_mask);
+}
+
int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
const u32 *msg, u32 len)
{
@@ -4033,6 +4056,7 @@ int intel_guc_engine_failure_process_msg(struct intel_guc
*guc,
struct intel_gt *gt = guc_to_gt(guc);
u8 guc_class, instance;
u32 reason;
+ unsigned long flags;
if (unlikely(len != 3)) {
drm_err(>i915->drm, "Invalid length %u", len);
@@ -4057,10 +4081,15 @@ int intel_guc_engine_failure_process_msg(struct
intel_guc *guc,
drm_err(>i915->drm, "GuC engine reset request failed on %d:%d (%s)
because 0x%08X",
guc_class, instance, engine->name, reason);
- intel_gt_handle_error(gt, engine->mask,
- I915_ERROR_CAPTURE,
- "GuC failed to reset %s (reason=0x%08x)\n",
- engine->name, reason);
+ spin_lock_irqsave(>submission_state.lock, flags);
+ guc->submission_state.reset_fail_mask |= engine->mask;
+ spin_unlock_irqrestore(>submission_state.lock, flags);
+
+ /*
+* A GT reset flushes this worker queue (G2H handler) so we must use
+* another worker to trigger a GT reset.
+*/
+ queue_work(system_unbound_wq, >submission_state.reset_fail_worker);
return 0;
}
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915: Reject bigjoiner if the pipe doesn't support it
== Series Details == Series: series starting with [1/3] drm/i915: Reject bigjoiner if the pipe doesn't support it URL : https://patchwork.freedesktop.org/series/99152/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8_full -> Patchwork_22057_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22057_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22057_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22057_full: ### IGT changes ### Possible regressions * igt@kms_flip@flip-vs-suspend-interruptible@c-edp1: - shard-skl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/shard-skl8/igt@kms_flip@flip-vs-suspend-interrupti...@c-edp1.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite: - shard-iclb: [PASS][2] -> [DMESG-WARN][3] +19 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-iclb5/igt@kms_frontbuffer_track...@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/shard-iclb6/igt@kms_frontbuffer_track...@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html * igt@syncobj_timeline@etime-single-wait-all-submitted: - shard-skl: [PASS][4] -> [INCOMPLETE][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-skl7/igt@syncobj_timel...@etime-single-wait-all-submitted.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/shard-skl2/igt@syncobj_timel...@etime-single-wait-all-submitted.html Known issues Here are the changes found in Patchwork_22057_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@in-flight-suspend: - shard-kbl: [PASS][6] -> [INCOMPLETE][7] ([i915#180] / [i915#3614]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-kbl1/igt@gem_...@in-flight-suspend.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/shard-kbl1/igt@gem_...@in-flight-suspend.html * igt@gem_exec_fair@basic-deadline: - shard-skl: NOTRUN -> [FAIL][8] ([i915#2846]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/shard-skl1/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [PASS][9] -> [FAIL][10] ([i915#2842]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_params@no-blt: - shard-tglb: NOTRUN -> [SKIP][11] ([fdo#109283]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/shard-tglb3/igt@gem_exec_par...@no-blt.html * igt@gem_exec_schedule@submit-early-slice@vecs0: - shard-skl: [PASS][12] -> [INCOMPLETE][13] ([i915#3797]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-skl2/igt@gem_exec_schedule@submit-early-sl...@vecs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/shard-skl3/igt@gem_exec_schedule@submit-early-sl...@vecs0.html * igt@gem_lmem_swapping@parallel-random: - shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/shard-skl9/igt@gem_lmem_swapp...@parallel-random.html * igt@gem_userptr_blits@dmabuf-sync: - shard-apl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#3323]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/shard-apl8/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gem_userptr_blits@vma-merge: - shard-skl: NOTRUN -> [FAIL][16] ([i915#3318]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/shard-skl8/igt@gem_userptr_bl...@vma-merge.html * igt@i915_selftest@live@hangcheck: - shard-snb: [PASS][17] -> [INCOMPLETE][18] ([i915#3921]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb2/igt@i915_selftest@l...@hangcheck.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/shard-snb7/igt@i915_selftest@l...@hangcheck.html * igt@kms_big_fb@x-tiled-32bpp-rotate-180: - shard-glk: [PASS][19] -> [DMESG-WARN][20] ([i915#118]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-glk6/igt@kms_big...@x-tiled-32bpp-rotate-180.html [20]:
Re: [Intel-gfx] [PATCH 1/3] drm: add writeback pointers to drm_connector
+ laurent on this
Hi Suraj
On 1/11/2022 2:17 AM, Kandpal, Suraj wrote:
Changing drm_connector and drm_encoder feilds to pointers in
drm_writeback_connector as the elements of struct
drm_writeback_connector are:
struct drm_writeback_connector {
struct drm_connector base;
struct drm_encoder encoder;
Similarly the elements of intel_encoder and intel_connector
are:
struct intel_encoder {
struct drm_encoder base;
struct intel_connector {
struct drm_connector base;
The function drm_writeback_connector_init() will initialize the
drm_connector and drm_encoder and attach them as well.
Since the drm_connector/encoder are both struct in
drm_writeback_connector and intel_connector/encoder, we need
one of them to be a pointer so we can reference them or else we
will be pointing to 2 seprate instances.
Usually the struct defined in drm framework pointing to any
struct will be pointer and allocating them and initialization
will be done with the users.
Like struct drm_connector and drm_encoder are part of drm
framework and the users of these such as i915 have included them
in their struct intel_connector and intel_encoder. Likewise
struct drm_writeback_connector is a special connector and hence
is not a user of drm_connector and hence this should be pointers.
Adding drm_writeback_connector to drm_connector so that
writeback_connector can be fetched from drm_connector as the previous
container_of method won't work due to change in the feilds of
drm_connector and drm_encoder in drm_writeback_connector.
Note:The corresponding ripple effect due to the above changes namely in
two drivers as I can see it komeda and vkms have been dealt with in the
upcoming patches of this series.
Signed-off-by: Kandpal, Suraj
Jani pointed me to this thread as i had posted something similar here :
https://patchwork.freedesktop.org/patch/470296/ but since this thread
was posted earlier, we can discuss further here.
Overall, its similar to what I had posted in the RFC and your commit
text also covers my concerns too.
One question I have about your change is since you have changed
wb_connector::encoder to be a pointer, i saw the other changes in the
series but they do not allocate an encoder. Would this not affect the
other drivers which are assuming that the encoder in wb_connector is
struct drm_encoder encoder and not struct drm_encoder* encoder.
Your changes fix the compilation issue but wouldnt this crash as encoder
wasnt allocated for other drivers.
---
drivers/gpu/drm/drm_writeback.c | 19 ++-
include/drm/drm_connector.h | 3 +++
include/drm/drm_writeback.h | 6 +++---
3 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/drm_writeback.c b/drivers/gpu/drm/drm_writeback.c
index dccf4504f1bb..47238db42363 100644
--- a/drivers/gpu/drm/drm_writeback.c
+++ b/drivers/gpu/drm/drm_writeback.c
@@ -87,7 +87,7 @@ static const char *drm_writeback_fence_get_driver_name(struct
dma_fence *fence)
struct drm_writeback_connector *wb_connector =
fence_to_wb_connector(fence);
- return wb_connector->base.dev->driver->name;
+ return wb_connector->base->dev->driver->name;
}
static const char *
@@ -177,7 +177,7 @@ int drm_writeback_connector_init(struct drm_device *dev,
const u32 *formats, int n_formats)
{
struct drm_property_blob *blob;
- struct drm_connector *connector = _connector->base;
+ struct drm_connector *connector = wb_connector->base;
struct drm_mode_config *config = >mode_config;
int ret = create_writeback_properties(dev);
@@ -189,14 +189,15 @@ int drm_writeback_connector_init(struct drm_device *dev,
if (IS_ERR(blob))
return PTR_ERR(blob);
- drm_encoder_helper_add(_connector->encoder, enc_helper_funcs);
- ret = drm_encoder_init(dev, _connector->encoder,
+ drm_encoder_helper_add(wb_connector->encoder, enc_helper_funcs);
+ ret = drm_encoder_init(dev, wb_connector->encoder,
_writeback_encoder_funcs,
DRM_MODE_ENCODER_VIRTUAL, NULL);
if (ret)
goto fail;
connector->interlace_allowed = 0;
+ connector->wb_connector = wb_connector;
ret = drm_connector_init(dev, connector, con_funcs,
DRM_MODE_CONNECTOR_WRITEBACK);
@@ -204,7 +205,7 @@ int drm_writeback_connector_init(struct drm_device *dev,
goto connector_fail;
ret = drm_connector_attach_encoder(connector,
- _connector->encoder);
+ wb_connector->encoder);
if (ret)
goto attach_fail;
@@ -233,7 +234,7 @@ int drm_writeback_connector_init(struct drm_device *dev,
attach_fail:
drm_connector_cleanup(connector);
connector_fail:
-
Re: [Intel-gfx] [PATCH 1/6] drm/i915: Clean up pre-skl primary plane registers
On Fri, 2022-01-21 at 13:30 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_BIT() & co. for the pre-skl primary plane registers.
> Also give everything a consistent namespace.
>
> v2: s/DSP/DISP/ to avoid confusion (José)
> Use DISP_WIDTH rather than DISP_POS_X for DSPSIZE (José)
> Deal with gvt
>
Reviewed-by: José Roberto de Souza
> Cc: José Roberto de Souza
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c| 99 +
> drivers/gpu/drm/i915/display/intel_display.c | 13 +--
> drivers/gpu/drm/i915/gvt/display.c | 4 +-
> drivers/gpu/drm/i915/gvt/fb_decoder.c| 18 ++--
> drivers/gpu/drm/i915/i915_reg.h | 108 +++
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 6 files changed, 128 insertions(+), 116 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
> b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index fc6f05146a9f..54f8776ca6b3 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -155,51 +155,51 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
> *crtc_state,
> unsigned int rotation = plane_state->hw.rotation;
> u32 dspcntr;
>
> - dspcntr = DISPLAY_PLANE_ENABLE;
> + dspcntr = DISP_ENABLE;
>
> if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) ||
> IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
> - dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
> + dspcntr |= DISP_TRICKLE_FEED_DISABLE;
>
> switch (fb->format->format) {
> case DRM_FORMAT_C8:
> - dspcntr |= DISPPLANE_8BPP;
> + dspcntr |= DISP_FORMAT_8BPP;
> break;
> case DRM_FORMAT_XRGB1555:
> - dspcntr |= DISPPLANE_BGRX555;
> + dspcntr |= DISP_FORMAT_BGRX555;
> break;
> case DRM_FORMAT_ARGB1555:
> - dspcntr |= DISPPLANE_BGRA555;
> + dspcntr |= DISP_FORMAT_BGRA555;
> break;
> case DRM_FORMAT_RGB565:
> - dspcntr |= DISPPLANE_BGRX565;
> + dspcntr |= DISP_FORMAT_BGRX565;
> break;
> case DRM_FORMAT_XRGB:
> - dspcntr |= DISPPLANE_BGRX888;
> + dspcntr |= DISP_FORMAT_BGRX888;
> break;
> case DRM_FORMAT_XBGR:
> - dspcntr |= DISPPLANE_RGBX888;
> + dspcntr |= DISP_FORMAT_RGBX888;
> break;
> case DRM_FORMAT_ARGB:
> - dspcntr |= DISPPLANE_BGRA888;
> + dspcntr |= DISP_FORMAT_BGRA888;
> break;
> case DRM_FORMAT_ABGR:
> - dspcntr |= DISPPLANE_RGBA888;
> + dspcntr |= DISP_FORMAT_RGBA888;
> break;
> case DRM_FORMAT_XRGB2101010:
> - dspcntr |= DISPPLANE_BGRX101010;
> + dspcntr |= DISP_FORMAT_BGRX101010;
> break;
> case DRM_FORMAT_XBGR2101010:
> - dspcntr |= DISPPLANE_RGBX101010;
> + dspcntr |= DISP_FORMAT_RGBX101010;
> break;
> case DRM_FORMAT_ARGB2101010:
> - dspcntr |= DISPPLANE_BGRA101010;
> + dspcntr |= DISP_FORMAT_BGRA101010;
> break;
> case DRM_FORMAT_ABGR2101010:
> - dspcntr |= DISPPLANE_RGBA101010;
> + dspcntr |= DISP_FORMAT_RGBA101010;
> break;
> case DRM_FORMAT_XBGR16161616F:
> - dspcntr |= DISPPLANE_RGBX161616;
> + dspcntr |= DISP_FORMAT_RGBX161616;
> break;
> default:
> MISSING_CASE(fb->format->format);
> @@ -208,13 +208,13 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
> *crtc_state,
>
> if (DISPLAY_VER(dev_priv) >= 4 &&
> fb->modifier == I915_FORMAT_MOD_X_TILED)
> - dspcntr |= DISPPLANE_TILED;
> + dspcntr |= DISP_TILED;
>
> if (rotation & DRM_MODE_ROTATE_180)
> - dspcntr |= DISPPLANE_ROTATE_180;
> + dspcntr |= DISP_ROTATE_180;
>
> if (rotation & DRM_MODE_REFLECT_X)
> - dspcntr |= DISPPLANE_MIRROR;
> + dspcntr |= DISP_MIRROR;
>
> return dspcntr;
> }
> @@ -354,13 +354,13 @@ static u32 i9xx_plane_ctl_crtc(const struct
> intel_crtc_state *crtc_state)
> u32 dspcntr = 0;
>
> if (crtc_state->gamma_enable)
> - dspcntr |= DISPPLANE_GAMMA_ENABLE;
> + dspcntr |= DISP_PIPE_GAMMA_ENABLE;
>
> if (crtc_state->csc_enable)
> - dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
> + dspcntr |= DISP_PIPE_CSC_ENABLE;
>
> if (DISPLAY_VER(dev_priv) < 5)
> - dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
> + dspcntr |= DISP_PIPE_SEL(crtc->pipe);
>
> return dspcntr;
> }
> @@ -437,9 +437,9 @@ static void i9xx_plane_update_noarm(struct intel_plane
> *plane,
>*
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: drm device based logging conversions
== Series Details == Series: drm/i915/display: drm device based logging conversions URL : https://patchwork.freedesktop.org/series/99151/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8_full -> Patchwork_22056_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22056_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22056_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22056_full: ### CI changes ### Possible regressions * boot: - shard-snb: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [FAIL][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb4/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb4/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb2/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb2/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb2/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb2/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb2/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb7/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb7/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb7/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb7/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb7/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb6/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb6/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb6/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb6/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb6/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb5/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb5/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb5/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb5/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb5/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb4/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb4/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-snb4/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/shard-snb4/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/shard-snb7/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/shard-snb7/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/shard-snb7/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/shard-snb7/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/shard-snb7/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/shard-snb6/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/shard-snb6/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/shard-snb6/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/shard-snb6/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/shard-snb6/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/shard-snb6/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/shard-snb5/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/shard-snb5/boot.html [40]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dg2: Add Wa_18018781329 (rev3)
== Series Details == Series: drm/i915/dg2: Add Wa_18018781329 (rev3) URL : https://patchwork.freedesktop.org/series/99128/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8 -> Patchwork_22059 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22059 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22059, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/index.html Participating hosts (48 -> 42) -- Additional (1): fi-kbl-soraka Missing(7): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-ctg-p8600 fi-pnv-d510 fi-bdw-samus Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22059: ### IGT changes ### Possible regressions * igt@i915_selftest@live@guc: - fi-rkl-guc: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-rkl-guc/igt@i915_selftest@l...@guc.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-rkl-guc/igt@i915_selftest@l...@guc.html Known issues Here are the changes found in Patchwork_22059 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][3] ([fdo#109271]) +31 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271]) +8 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_huc_copy@huc-copy: - fi-skl-6600u: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html - fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-kbl-soraka/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - fi-skl-6600u: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][9] ([i915#1886] / [i915#2291]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_chamelium@dp-edid-read: - fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-kbl-soraka/igt@kms_chamel...@dp-edid-read.html * igt@kms_chamelium@vga-edid-read: - fi-skl-6600u: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html - fi-bdw-5557u: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-bdw-5557u/igt@kms_chamel...@vga-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-skl-6600u: NOTRUN -> [SKIP][13] ([fdo#109271]) +21 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-skl-6600u: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#533]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html - fi-kbl-soraka: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#533]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22059/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-cml-u2: [PASS][16] -> [FAIL][17] ([fdo#103375]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-cml-u2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [17]:
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Reject bigjoiner if the pipe doesn't support it
On Fri, Jan 21, 2022 at 05:55:24PM +0200, Ville Syrjälä wrote:
> On Fri, Jan 21, 2022 at 04:03:09PM +0200, Jani Nikula wrote:
> > On Fri, 21 Jan 2022, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Check that our crtc can in fact be the bigjoiner master before
> > > we let the modeset proceed with bigjoiner enabled.
> > >
> > > Signed-off-by: Ville Syrjälä
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 16
> > > 1 file changed, 16 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 0964b2403e2d..36e547bd0cbe 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -4102,6 +4102,14 @@ static u8 bigjoiner_pipes(struct drm_i915_private
> > > *i915)
> > > return 0;
> > > }
> > >
> > > +static u8 bigjoiner_master_pipes(struct drm_i915_private *i915)
> > > +{
> > > + u8 pipes = bigjoiner_pipes(i915);
> > > +
> > > + /* last pipe can not be master */
> > > + return pipes & (pipes >> 1);
> > > +}
> > > +
> > > static bool transcoder_ddi_func_is_enabled(struct drm_i915_private
> > > *dev_priv,
> > > enum transcoder cpu_transcoder)
> > > {
> > > @@ -7600,6 +7608,7 @@ static int intel_atomic_check_bigjoiner(struct
> > > intel_atomic_state *state,
> > > struct intel_crtc_state *old_crtc_state,
> > > struct intel_crtc_state *new_crtc_state)
> > > {
> > > + struct drm_i915_private *i915 = to_i915(state->base.dev);
> > > struct intel_crtc_state *slave_crtc_state, *master_crtc_state;
> > > struct intel_crtc *slave_crtc, *master_crtc;
> > >
> > > @@ -7615,6 +7624,13 @@ static int intel_atomic_check_bigjoiner(struct
> > > intel_atomic_state *state,
> > > if (!new_crtc_state->bigjoiner)
> > > return 0;
> > >
> > > + if ((bigjoiner_master_pipes(i915) & BIT(crtc->pipe)) == 0) {
> >
> > Feels like the check should be in
> > intel_dsc_get_bigjoiner_{secondary,primary}.
>
> The master pipe is selected by userspace. intel_dsc_get_bigjoiner_primary()
> is not relevant here.
Hmm. I guess the intel_dsc_get_bigjoiner_secondary()->NULL is
in fact sufficient on current hardware since only pipe A can
be non-joinable, and the dsc code already rejects the transcoder A
case. Although it only claims to do that due to it not supporting
dsc, but luckily that happens to be the same thing as no-joiner since
there is no uncompressed joiner either.
But to be 100% clear should probably do something along the lines
proposed here. I'm actually think we nuke all these crtc pointers/etc.
and just go for some kind of pipe bitmask based approach everywhere.
So this probaly needs a bit more through all around.
--
Ville Syrjälä
Intel
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dg2: Add Wa_18018781329 (rev3)
== Series Details == Series: drm/i915/dg2: Add Wa_18018781329 (rev3) URL : https://patchwork.freedesktop.org/series/99128/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Add Wa_18018781329 (rev3)
== Series Details == Series: drm/i915/dg2: Add Wa_18018781329 (rev3) URL : https://patchwork.freedesktop.org/series/99128/ State : warning == Summary == $ dim checkpatch origin/drm-tip 66b0cf558d66 drm/i915/dg2: Add Wa_18018781329 -:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #9: From: Intel-gfx On Behalf Of Matt Roper -:49: ERROR:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Intel-gfx On Behalf Of Matt Roper' total: 1 errors, 1 warnings, 0 checks, 22 lines checked
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Futher optimize plane updates
== Series Details == Series: drm/i915: Futher optimize plane updates URL : https://patchwork.freedesktop.org/series/99149/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8_full -> Patchwork_22055_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22055_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22055_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22055_full: ### IGT changes ### Possible regressions * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size: - shard-iclb: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-iclb6/igt@kms_cursor_leg...@cursor-vs-flip-atomic-transitions-varying-size.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb7/igt@kms_cursor_leg...@cursor-vs-flip-atomic-transitions-varying-size.html * igt@perf@stress-open-close: - shard-iclb: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-iclb2/igt@p...@stress-open-close.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb5/igt@p...@stress-open-close.html Known issues Here are the changes found in Patchwork_22055_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@parallel-out-fence: - shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-iclb2/igt@gem_exec_balan...@parallel-out-fence.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb5/igt@gem_exec_balan...@parallel-out-fence.html * igt@gem_exec_capture@pi@bcs0: - shard-skl: NOTRUN -> [INCOMPLETE][7] ([i915#4547]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-skl9/igt@gem_exec_capture@p...@bcs0.html * igt@gem_exec_fair@basic-deadline: - shard-skl: NOTRUN -> [FAIL][8] ([i915#2846]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-skl4/igt@gem_exec_f...@basic-deadline.html - shard-glk: [PASS][9] -> [FAIL][10] ([i915#2846]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-glk4/igt@gem_exec_f...@basic-deadline.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-glk7/igt@gem_exec_f...@basic-deadline.html - shard-apl: NOTRUN -> [FAIL][11] ([i915#2846]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-apl6/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [PASS][14] -> [FAIL][15] ([i915#2842]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-kbl7/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][16] ([i915#2842]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb1/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][17] -> [FAIL][18] ([i915#2842]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-tglb6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-tglb7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-kbl: [PASS][19] -> [SKIP][20] ([fdo#109271]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/shard-kbl7/igt@gem_exec_fair@basic-p...@vcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-kbl3/igt@gem_exec_fair@basic-p...@vcs0.html * igt@gem_exec_params@no-blt: - shard-tglb: NOTRUN -> [SKIP][21] ([fdo#109283]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-tglb6/igt@gem_exec_par...@no-blt.html * igt@gem_huc_copy@huc-copy: - shard-tglb:
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Reject bigjoiner if the pipe doesn't support it
On Fri, Jan 21, 2022 at 04:03:09PM +0200, Jani Nikula wrote:
> On Fri, 21 Jan 2022, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Check that our crtc can in fact be the bigjoiner master before
> > we let the modeset proceed with bigjoiner enabled.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 16
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 0964b2403e2d..36e547bd0cbe 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -4102,6 +4102,14 @@ static u8 bigjoiner_pipes(struct drm_i915_private
> > *i915)
> > return 0;
> > }
> >
> > +static u8 bigjoiner_master_pipes(struct drm_i915_private *i915)
> > +{
> > + u8 pipes = bigjoiner_pipes(i915);
> > +
> > + /* last pipe can not be master */
> > + return pipes & (pipes >> 1);
> > +}
> > +
> > static bool transcoder_ddi_func_is_enabled(struct drm_i915_private
> > *dev_priv,
> >enum transcoder cpu_transcoder)
> > {
> > @@ -7600,6 +7608,7 @@ static int intel_atomic_check_bigjoiner(struct
> > intel_atomic_state *state,
> > struct intel_crtc_state *old_crtc_state,
> > struct intel_crtc_state *new_crtc_state)
> > {
> > + struct drm_i915_private *i915 = to_i915(state->base.dev);
> > struct intel_crtc_state *slave_crtc_state, *master_crtc_state;
> > struct intel_crtc *slave_crtc, *master_crtc;
> >
> > @@ -7615,6 +7624,13 @@ static int intel_atomic_check_bigjoiner(struct
> > intel_atomic_state *state,
> > if (!new_crtc_state->bigjoiner)
> > return 0;
> >
> > + if ((bigjoiner_master_pipes(i915) & BIT(crtc->pipe)) == 0) {
>
> Feels like the check should be in
> intel_dsc_get_bigjoiner_{secondary,primary}.
The master pipe is selected by userspace. intel_dsc_get_bigjoiner_primary()
is not relevant here.
side note: A lot of that code really should be moved out of intel_vdsc.c
since we also have the uncompressed joiner to consider. Should probably
do a global s/bigjoiner/joiner/ as well since afaik "bigjoiner" refers
specifically to the compressed joiner.
--
Ville Syrjälä
Intel
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: nuke local versions of WARN_ON/WARN_ON_ONCE
== Series Details ==
Series: drm/i915: nuke local versions of WARN_ON/WARN_ON_ONCE
URL : https://patchwork.freedesktop.org/series/99155/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8 -> Patchwork_22058
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/index.html
Participating hosts (48 -> 42)
--
Additional (1): fi-kbl-soraka
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-ctg-p8600
fi-pnv-d510 fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22058:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling:
- {bat-adlp-6}: [DMESG-WARN][1] ([i915#4954]) -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/bat-adlp-6/igt@kms_addfb_ba...@addfb25-framebuffer-vs-set-tiling.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/bat-adlp-6/igt@kms_addfb_ba...@addfb25-framebuffer-vs-set-tiling.html
Known issues
Here are the changes found in Patchwork_22058 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u: NOTRUN -> [SKIP][3] ([fdo#109271]) +31 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271]) +8 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html
* igt@gem_exec_suspend@basic-s0@smem:
- fi-tgl-1115g4: [PASS][5] -> [FAIL][6] ([i915#1888])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-tgl-1115g4/igt@gem_exec_suspend@basic...@smem.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/fi-tgl-1115g4/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-skl-6600u: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html
- fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/fi-kbl-soraka/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +3
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][11] ([i915#1886] / [i915#2291])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8
similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/fi-kbl-soraka/igt@kms_chamel...@dp-edid-read.html
* igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html
- fi-bdw-5557u: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8
similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/fi-bdw-5557u/igt@kms_chamel...@vga-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u: NOTRUN -> [SKIP][15] ([fdo#109271]) +21 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#533])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
- fi-kbl-soraka: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#533])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22058/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
Possible fixes
*
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: nuke local versions of WARN_ON/WARN_ON_ONCE
== Series Details == Series: drm/i915: nuke local versions of WARN_ON/WARN_ON_ONCE URL : https://patchwork.freedesktop.org/series/99155/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Reject bigjoiner if the pipe doesn't support it
== Series Details ==
Series: series starting with [1/3] drm/i915: Reject bigjoiner if the pipe
doesn't support it
URL : https://patchwork.freedesktop.org/series/99152/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8 -> Patchwork_22057
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/index.html
Participating hosts (48 -> 42)
--
Additional (1): fi-kbl-soraka
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-icl-u2 bat-adlp-4
fi-ctg-p8600 fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22057:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_suspend@basic-s0@smem:
- {fi-ehl-2}: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-ehl-2/igt@gem_exec_suspend@basic...@smem.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/fi-ehl-2/igt@gem_exec_suspend@basic...@smem.html
- {bat-jsl-2}:[PASS][3] -> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/bat-jsl-2/igt@gem_exec_suspend@basic...@smem.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/bat-jsl-2/igt@gem_exec_suspend@basic...@smem.html
- {bat-jsl-1}:[PASS][5] -> [DMESG-WARN][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/bat-jsl-1/igt@gem_exec_suspend@basic...@smem.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/bat-jsl-1/igt@gem_exec_suspend@basic...@smem.html
- {fi-jsl-1}: [PASS][7] -> [DMESG-WARN][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-jsl-1/igt@gem_exec_suspend@basic...@smem.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/fi-jsl-1/igt@gem_exec_suspend@basic...@smem.html
Known issues
Here are the changes found in Patchwork_22057 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u: NOTRUN -> [SKIP][9] ([fdo#109271]) +31 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271]) +8 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-skl-6600u: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#2190])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html
- fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#2190])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) +3
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html
* igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +3
similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][15] ([i915#1886] / [i915#2291])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][16] -> [INCOMPLETE][17] ([i915#3303])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +8
similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-bdw-5557u: NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111827]) +8
similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u: NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827]) +8
similar issues
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22057/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html
*
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use per-device debugs for bigjoiner stuff
On Fri, 21 Jan 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Specify which device we're talking about when spewing
> bigjoiner debugs.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 21 +++-
> 1 file changed, 12 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 36e547bd0cbe..9fb72c356208 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7633,9 +7633,10 @@ static int intel_atomic_check_bigjoiner(struct
> intel_atomic_state *state,
>
> slave_crtc = intel_dsc_get_bigjoiner_secondary(crtc);
> if (!slave_crtc) {
> - DRM_DEBUG_KMS("[CRTC:%d:%s] Big joiner configuration requires "
> - "CRTC + 1 to be used, doesn't exist\n",
> - crtc->base.base.id, crtc->base.name);
> + drm_dbg_kms(>drm,
> + "[CRTC:%d:%s] Big joiner configuration requires "
> + "CRTC + 1 to be used, doesn't exist\n",
> + crtc->base.base.id, crtc->base.name);
> return -EINVAL;
> }
>
> @@ -7649,16 +7650,18 @@ static int intel_atomic_check_bigjoiner(struct
> intel_atomic_state *state,
> if (slave_crtc_state->uapi.enable)
> goto claimed;
>
> - DRM_DEBUG_KMS("[CRTC:%d:%s] Used as slave for big joiner\n",
> - slave_crtc->base.base.id, slave_crtc->base.name);
> + drm_dbg_kms(>drm,
> + "[CRTC:%d:%s] Used as slave for big joiner\n",
> + slave_crtc->base.base.id, slave_crtc->base.name);
>
> return copy_bigjoiner_crtc_state(slave_crtc_state, new_crtc_state);
>
> claimed:
> - DRM_DEBUG_KMS("[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
> - "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
> - slave_crtc->base.base.id, slave_crtc->base.name,
> - master_crtc->base.base.id, master_crtc->base.name);
> + drm_dbg_kms(>drm,
> + "[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
> + "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
> + slave_crtc->base.base.id, slave_crtc->base.name,
> + master_crtc->base.base.id, master_crtc->base.name);
> return -EINVAL;
> }
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 2/3] drm/i915: Simplify intel_dsc_source_support()
On Fri, 21 Jan 2022, Ville Syrjala wrote: > From: Ville Syrjälä > > We can simplify the icl check in intel_dsc_source_support() > by noting that the only case when DSC is not supported is when > using transcoder A. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_vdsc.c | 7 +-- > 1 file changed, 1 insertion(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c > b/drivers/gpu/drm/i915/display/intel_vdsc.c > index 9b05f93ed8bc..3faea903b9ae 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -341,19 +341,14 @@ bool intel_dsc_source_support(const struct > intel_crtc_state *crtc_state) > const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > struct drm_i915_private *i915 = to_i915(crtc->base.dev); > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > - enum pipe pipe = crtc->pipe; > > if (!INTEL_INFO(i915)->display.has_dsc) > return false; > > - /* On TGL, DSC is supported on all Pipes */ > if (DISPLAY_VER(i915) >= 12) > return true; > > - if (DISPLAY_VER(i915) >= 11 && > - (pipe != PIPE_A || cpu_transcoder == TRANSCODER_EDP || > - cpu_transcoder == TRANSCODER_DSI_0 || > - cpu_transcoder == TRANSCODER_DSI_1)) > + if (DISPLAY_VER(i915) >= 11 && cpu_transcoder != TRANSCODER_A) > return true; > > return false; -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Reject bigjoiner if the pipe doesn't support it
On Fri, 21 Jan 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Check that our crtc can in fact be the bigjoiner master before
> we let the modeset proceed with bigjoiner enabled.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 16
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 0964b2403e2d..36e547bd0cbe 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4102,6 +4102,14 @@ static u8 bigjoiner_pipes(struct drm_i915_private
> *i915)
> return 0;
> }
>
> +static u8 bigjoiner_master_pipes(struct drm_i915_private *i915)
> +{
> + u8 pipes = bigjoiner_pipes(i915);
> +
> + /* last pipe can not be master */
> + return pipes & (pipes >> 1);
> +}
> +
> static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
> enum transcoder cpu_transcoder)
> {
> @@ -7600,6 +7608,7 @@ static int intel_atomic_check_bigjoiner(struct
> intel_atomic_state *state,
> struct intel_crtc_state *old_crtc_state,
> struct intel_crtc_state *new_crtc_state)
> {
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> struct intel_crtc_state *slave_crtc_state, *master_crtc_state;
> struct intel_crtc *slave_crtc, *master_crtc;
>
> @@ -7615,6 +7624,13 @@ static int intel_atomic_check_bigjoiner(struct
> intel_atomic_state *state,
> if (!new_crtc_state->bigjoiner)
> return 0;
>
> + if ((bigjoiner_master_pipes(i915) & BIT(crtc->pipe)) == 0) {
Feels like the check should be in
intel_dsc_get_bigjoiner_{secondary,primary}.
They already contain the check that the next/prev pipe exists, which
(silly me) I thought was enough.
BR,
Jani.
> + drm_dbg_kms(>drm,
> + "[CRTC:%d:%s] Bigjoiner not available on this
> pipe\n",
> + crtc->base.base.id, crtc->base.name);
> + return -EINVAL;
> + }
> +
> slave_crtc = intel_dsc_get_bigjoiner_secondary(crtc);
> if (!slave_crtc) {
> DRM_DEBUG_KMS("[CRTC:%d:%s] Big joiner configuration requires "
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: drm device based logging conversions
== Series Details == Series: drm/i915/display: drm device based logging conversions URL : https://patchwork.freedesktop.org/series/99151/ State : success == Summary == CI Bug Log - changes from CI_DRM_8 -> Patchwork_22056 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/index.html Participating hosts (48 -> 36) -- Additional (1): fi-kbl-soraka Missing(13): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-icl-u2 fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 bat-rpls-1 fi-bdw-samus bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_22056 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +31 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271]) +8 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_exec_suspend@basic-s0@smem: - fi-tgl-1115g4: [PASS][3] -> [FAIL][4] ([i915#1888]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-tgl-1115g4/igt@gem_exec_suspend@basic...@smem.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/fi-tgl-1115g4/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@i915_selftest@live@gt_lrc: - fi-bsw-n3050: [PASS][7] -> [DMESG-FAIL][8] ([i915#2373]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][9] ([i915#1886] / [i915#2291]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@hangcheck: - fi-hsw-4770:[PASS][10] -> [INCOMPLETE][11] ([i915#4785]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@dp-crc-fast: - fi-bdw-5557u: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-kbl-soraka: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#533]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@runner@aborted: - fi-hsw-4770:NOTRUN -> [FAIL][15] ([fdo#109271] / [i915#1436] / [i915#4312]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/fi-hsw-4770/igt@run...@aborted.html - fi-bsw-n3050: NOTRUN -> [FAIL][16] ([fdo#109271] / [i915#1436] / [i915#3428] / [i915#4312]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/fi-bsw-n3050/igt@run...@aborted.html Possible fixes * igt@gem_exec_suspend@basic-s3@smem: - fi-bdw-5557u: [INCOMPLETE][17] ([i915#146]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [DMESG-WARN][19] ([i915#4269]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22056/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html Warnings *
[Intel-gfx] [PATCH] drm/i915: nuke local versions of WARN_ON/WARN_ON_ONCE
In general, we should avoid redefining kernel macros like this. It can
get confusing, and what gets used will depend on whether the header is
included or not. Moreover, we should prefer drm_WARN_ON() and
drm_WARN_ON_ONCE() anyway, which include the stringified error condition
in the message.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_utils.h | 15 ---
1 file changed, 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_utils.h
b/drivers/gpu/drm/i915/i915_utils.h
index 7a5925072466..bfafd0afd117 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -37,21 +37,6 @@ struct timer_list;
#define FDO_BUG_URL
"https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs;
-#undef WARN_ON
-/* Many gcc seem to no see through this and fall over :( */
-#if 0
-#define WARN_ON(x) ({ \
- bool __i915_warn_cond = (x); \
- if (__builtin_constant_p(__i915_warn_cond)) \
- BUILD_BUG_ON(__i915_warn_cond); \
- WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
-#else
-#define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
-#endif
-
-#undef WARN_ON_ONCE
-#define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x)
")")
-
#define MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
__stringify(x), (long)(x))
--
2.30.2
Re: [Intel-gfx] [GIT PULL] PCI fixes for v5.17
The pull request you sent on Thu, 20 Jan 2022 14:48:17 -0600: > git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git > tags/pci-v5.17-fixes-1 has been merged into torvalds/linux.git: https://git.kernel.org/torvalds/c/4141a5e694588897cbec955bc4a646075dc0afd7 Thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/prtracker.html
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Futher optimize plane updates
== Series Details == Series: drm/i915: Futher optimize plane updates URL : https://patchwork.freedesktop.org/series/99149/ State : success == Summary == CI Bug Log - changes from CI_DRM_8 -> Patchwork_22055 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/index.html Participating hosts (48 -> 36) -- Additional (1): fi-kbl-soraka Missing(13): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-pnv-d510 bat-rpls-1 fi-bdw-samus bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_22055 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +8 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_exec_suspend@basic-s0@smem: - fi-tgl-1115g4: [PASS][2] -> [FAIL][3] ([i915#1888]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-tgl-1115g4/igt@gem_exec_suspend@basic...@smem.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-tgl-1115g4/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - fi-skl-6600u: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html - fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@verify-random: - fi-skl-6600u: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html * igt@i915_selftest@live: - fi-skl-6600u: NOTRUN -> [INCOMPLETE][8] ([i915#4794]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-skl-6600u/igt@i915_selft...@live.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][9] ([i915#1886] / [i915#2291]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@hangcheck: - fi-hsw-4770:[PASS][10] -> [INCOMPLETE][11] ([i915#3303]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@vga-edid-read: - fi-skl-6600u: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-skl-6600u: NOTRUN -> [SKIP][14] ([fdo#109271]) +3 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-skl-6600u: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#533]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html - fi-kbl-soraka: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#533]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@runner@aborted: - fi-bdw-5557u: NOTRUN -> [FAIL][17] ([i915#2426] / [i915#4312]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-bdw-5557u/igt@run...@aborted.html - fi-hsw-4770:NOTRUN -> [FAIL][18] ([fdo#109271] / [i915#1436] / [i915#4312]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-hsw-4770/igt@run...@aborted.html Possible fixes * igt@gem_exec_suspend@basic-s3@smem: - fi-bdw-5557u: [INCOMPLETE][19] ([i915#146]) -> [PASS][20] [19]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: drm device based logging conversions
== Series Details == Series: drm/i915/display: drm device based logging conversions URL : https://patchwork.freedesktop.org/series/99151/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: drm device based logging conversions
== Series Details == Series: drm/i915/display: drm device based logging conversions URL : https://patchwork.freedesktop.org/series/99151/ State : warning == Summary == $ dim checkpatch origin/drm-tip a43bb8c04dce drm/i915/snps: convert to drm device based logging 6813c31ef162 drm/i915/pps: convert to drm device based logging e6787b198d3f drm/i915/hotplug: convert to drm device based logging aea8c9dd191f drm/i915/dp: convert to drm device based logging 44a70cd142f4 drm/i915/plane: convert to drm device based logging and WARN 05aea95dab19 drm/i915/sprite: convert to drm device based logging 4a21e470add5 drm/i915/lspcon: convert to drm device based logging -:488: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #488: FILE: drivers/gpu/drm/i915/display/intel_lspcon.c:696: + drm_err(>drm, "LSPCON init failed on port %c\n", port_name(dig_port->base.port)); total: 0 errors, 0 warnings, 1 checks, 451 lines checked f258150a08fa drm/i915/cdclk: update intel_dump_cdclk_config() logging 2d89bd8afec9 drm/i915/cdclk: convert to drm device based logging
[Intel-gfx] ✗ Fi.CI.IGT: failure for Async flip optimization for DG2 (rev4)
== Series Details == Series: Async flip optimization for DG2 (rev4) URL : https://patchwork.freedesktop.org/series/98981/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7_full -> Patchwork_22054_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22054_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22054_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22054_full: ### IGT changes ### Possible regressions * igt@sysfs_heartbeat_interval@mixed@vecs0: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-tglb1/igt@sysfs_heartbeat_interval@mi...@vecs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22054/shard-tglb3/igt@sysfs_heartbeat_interval@mi...@vecs0.html Known issues Here are the changes found in Patchwork_22054_full that come from known issues: ### CI changes ### Possible fixes * boot: - shard-glk: ([PASS][3], [PASS][4], [PASS][5], [FAIL][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27]) ([i915#4392]) -> ([PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk4/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk4/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk3/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk3/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk3/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk3/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk2/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk2/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk2/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk1/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk1/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk1/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk9/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk9/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk8/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk8/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk8/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk7/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk7/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk6/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk6/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk5/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk5/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk5/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/shard-glk4/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22054/shard-glk9/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22054/shard-glk8/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22054/shard-glk8/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22054/shard-glk9/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22054/shard-glk9/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22054/shard-glk1/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22054/shard-glk1/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22054/shard-glk1/boot.html [36]:
Re: [Intel-gfx] [PATCH 0/9] drm/i915/display: drm device based logging conversions
On Fri, Jan 21, 2022 at 03:00:29PM +0200, Jani Nikula wrote: > Purge some accumulated drm device based logging changes from my local > branches. > > Jani Nikula (9): > drm/i915/snps: convert to drm device based logging > drm/i915/pps: convert to drm device based logging > drm/i915/hotplug: convert to drm device based logging > drm/i915/dp: convert to drm device based logging > drm/i915/plane: convert to drm device based logging and WARN > drm/i915/sprite: convert to drm device based logging > drm/i915/lspcon: convert to drm device based logging > drm/i915/cdclk: update intel_dump_cdclk_config() logging > drm/i915/cdclk: convert to drm device based logging Eyeballed it quickly. Looks all right to me. Series is Reviewed-by: Ville Syrjälä > > .../gpu/drm/i915/display/intel_atomic_plane.c | 5 +- > drivers/gpu/drm/i915/display/intel_cdclk.c| 23 +-- > drivers/gpu/drm/i915/display/intel_cdclk.h| 3 +- > drivers/gpu/drm/i915/display/intel_display.c | 2 +- > .../drm/i915/display/intel_display_power.c| 2 +- > drivers/gpu/drm/i915/display/intel_dp.c | 35 +++-- > drivers/gpu/drm/i915/display/intel_hotplug.c | 14 +- > drivers/gpu/drm/i915/display/intel_lspcon.c | 142 ++ > drivers/gpu/drm/i915/display/intel_pps.c | 22 +-- > drivers/gpu/drm/i915/display/intel_snps_phy.c | 29 ++-- > drivers/gpu/drm/i915/display/intel_sprite.c | 24 +-- > .../drm/i915/display/skl_universal_plane.c| 10 +- > 12 files changed, 169 insertions(+), 142 deletions(-) > > -- > 2.30.2 -- Ville Syrjälä Intel
[Intel-gfx] [PATCH 3/3] drm/i915: Use per-device debugs for bigjoiner stuff
From: Ville Syrjälä
Specify which device we're talking about when spewing
bigjoiner debugs.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 21 +++-
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 36e547bd0cbe..9fb72c356208 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7633,9 +7633,10 @@ static int intel_atomic_check_bigjoiner(struct
intel_atomic_state *state,
slave_crtc = intel_dsc_get_bigjoiner_secondary(crtc);
if (!slave_crtc) {
- DRM_DEBUG_KMS("[CRTC:%d:%s] Big joiner configuration requires "
- "CRTC + 1 to be used, doesn't exist\n",
- crtc->base.base.id, crtc->base.name);
+ drm_dbg_kms(>drm,
+ "[CRTC:%d:%s] Big joiner configuration requires "
+ "CRTC + 1 to be used, doesn't exist\n",
+ crtc->base.base.id, crtc->base.name);
return -EINVAL;
}
@@ -7649,16 +7650,18 @@ static int intel_atomic_check_bigjoiner(struct
intel_atomic_state *state,
if (slave_crtc_state->uapi.enable)
goto claimed;
- DRM_DEBUG_KMS("[CRTC:%d:%s] Used as slave for big joiner\n",
- slave_crtc->base.base.id, slave_crtc->base.name);
+ drm_dbg_kms(>drm,
+ "[CRTC:%d:%s] Used as slave for big joiner\n",
+ slave_crtc->base.base.id, slave_crtc->base.name);
return copy_bigjoiner_crtc_state(slave_crtc_state, new_crtc_state);
claimed:
- DRM_DEBUG_KMS("[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
- "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
- slave_crtc->base.base.id, slave_crtc->base.name,
- master_crtc->base.base.id, master_crtc->base.name);
+ drm_dbg_kms(>drm,
+ "[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
+ "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
+ slave_crtc->base.base.id, slave_crtc->base.name,
+ master_crtc->base.base.id, master_crtc->base.name);
return -EINVAL;
}
--
2.32.0
[Intel-gfx] [PATCH 2/3] drm/i915: Simplify intel_dsc_source_support()
From: Ville Syrjälä We can simplify the icl check in intel_dsc_source_support() by noting that the only case when DSC is not supported is when using transcoder A. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vdsc.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 9b05f93ed8bc..3faea903b9ae 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -341,19 +341,14 @@ bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state) const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - enum pipe pipe = crtc->pipe; if (!INTEL_INFO(i915)->display.has_dsc) return false; - /* On TGL, DSC is supported on all Pipes */ if (DISPLAY_VER(i915) >= 12) return true; - if (DISPLAY_VER(i915) >= 11 && - (pipe != PIPE_A || cpu_transcoder == TRANSCODER_EDP || -cpu_transcoder == TRANSCODER_DSI_0 || -cpu_transcoder == TRANSCODER_DSI_1)) + if (DISPLAY_VER(i915) >= 11 && cpu_transcoder != TRANSCODER_A) return true; return false; -- 2.32.0
[Intel-gfx] [PATCH 1/3] drm/i915: Reject bigjoiner if the pipe doesn't support it
From: Ville Syrjälä
Check that our crtc can in fact be the bigjoiner master before
we let the modeset proceed with bigjoiner enabled.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 0964b2403e2d..36e547bd0cbe 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4102,6 +4102,14 @@ static u8 bigjoiner_pipes(struct drm_i915_private *i915)
return 0;
}
+static u8 bigjoiner_master_pipes(struct drm_i915_private *i915)
+{
+ u8 pipes = bigjoiner_pipes(i915);
+
+ /* last pipe can not be master */
+ return pipes & (pipes >> 1);
+}
+
static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
enum transcoder cpu_transcoder)
{
@@ -7600,6 +7608,7 @@ static int intel_atomic_check_bigjoiner(struct
intel_atomic_state *state,
struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state)
{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_crtc_state *slave_crtc_state, *master_crtc_state;
struct intel_crtc *slave_crtc, *master_crtc;
@@ -7615,6 +7624,13 @@ static int intel_atomic_check_bigjoiner(struct
intel_atomic_state *state,
if (!new_crtc_state->bigjoiner)
return 0;
+ if ((bigjoiner_master_pipes(i915) & BIT(crtc->pipe)) == 0) {
+ drm_dbg_kms(>drm,
+ "[CRTC:%d:%s] Bigjoiner not available on this
pipe\n",
+ crtc->base.base.id, crtc->base.name);
+ return -EINVAL;
+ }
+
slave_crtc = intel_dsc_get_bigjoiner_secondary(crtc);
if (!slave_crtc) {
DRM_DEBUG_KMS("[CRTC:%d:%s] Big joiner configuration requires "
--
2.32.0
[Intel-gfx] [PATCH 9/9] drm/i915/cdclk: convert to drm device based logging
Prefer drm device based logging.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index c4b48b831ced..4b140a014ca8 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1625,7 +1625,7 @@ static void adlp_cdclk_pll_crawl(struct drm_i915_private
*dev_priv, int vco)
/* Timeout 200us */
if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE,
BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
- DRM_ERROR("timeout waiting for FREQ change request ack\n");
+ drm_err(_priv->drm, "timeout waiting for FREQ change
request ack\n");
val &= ~BXT_DE_PLL_FREQ_REQ;
intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
--
2.30.2
[Intel-gfx] [PATCH 8/9] drm/i915/cdclk: update intel_dump_cdclk_config() logging
Gather some intel_dump_cdclk_config() changes together to avoid extra
churn: Rename to intel_cdclk_dump_config() to following naming
conventions. Pass in i915. Use i915 for struct drm_device based
logging. Switch to KMS drm debug class.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cdclk.c| 21 ++-
drivers/gpu/drm/i915/display/intel_cdclk.h| 3 ++-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
.../drm/i915/display/intel_display_power.c| 2 +-
4 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 7e20967307df..c4b48b831ced 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1156,7 +1156,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private
*dev_priv)
goto sanitize;
intel_update_cdclk(dev_priv);
- intel_dump_cdclk_config(_priv->cdclk.hw, "Current CDCLK");
+ intel_cdclk_dump_config(dev_priv, _priv->cdclk.hw, "Current CDCLK");
/* Is PLL enabled and locked ? */
if (dev_priv->cdclk.hw.vco == 0 ||
@@ -1817,7 +1817,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private
*dev_priv)
int cdclk, clock, vco;
intel_update_cdclk(dev_priv);
- intel_dump_cdclk_config(_priv->cdclk.hw, "Current CDCLK");
+ intel_cdclk_dump_config(dev_priv, _priv->cdclk.hw, "Current CDCLK");
if (dev_priv->cdclk.hw.vco == 0 ||
dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
@@ -2057,13 +2057,14 @@ static bool intel_cdclk_changed(const struct
intel_cdclk_config *a,
a->voltage_level != b->voltage_level;
}
-void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
+void intel_cdclk_dump_config(struct drm_i915_private *i915,
+const struct intel_cdclk_config *cdclk_config,
const char *context)
{
- DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz,
voltage level %d\n",
-context, cdclk_config->cdclk, cdclk_config->vco,
-cdclk_config->ref, cdclk_config->bypass,
-cdclk_config->voltage_level);
+ drm_dbg_kms(>drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d
kHz, voltage level %d\n",
+ context, cdclk_config->cdclk, cdclk_config->vco,
+ cdclk_config->ref, cdclk_config->bypass,
+ cdclk_config->voltage_level);
}
/**
@@ -2087,7 +2088,7 @@ static void intel_set_cdclk(struct drm_i915_private
*dev_priv,
if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->cdclk_funcs->set_cdclk))
return;
- intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
+ intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to");
for_each_intel_encoder_with_psr(_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2130,8 +2131,8 @@ static void intel_set_cdclk(struct drm_i915_private
*dev_priv,
if (drm_WARN(_priv->drm,
intel_cdclk_changed(_priv->cdclk.hw, cdclk_config),
"cdclk state doesn't match!\n")) {
- intel_dump_cdclk_config(_priv->cdclk.hw, "[hw state]");
- intel_dump_cdclk_config(cdclk_config, "[sw state]");
+ intel_cdclk_dump_config(dev_priv, _priv->cdclk.hw, "[hw
state]");
+ intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]");
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 71dd84740ae3..df66f66fbad0 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -62,7 +62,8 @@ bool intel_cdclk_needs_modeset(const struct
intel_cdclk_config *a,
const struct intel_cdclk_config *b);
void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
-void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
+void intel_cdclk_dump_config(struct drm_i915_private *i915,
+const struct intel_cdclk_config *cdclk_config,
const char *context);
int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 0964b2403e2d..ebd786021793 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9478,7 +9478,7 @@ void intel_modeset_init_hw(struct drm_i915_private *i915)
cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state);
[Intel-gfx] [PATCH 7/9] drm/i915/lspcon: convert to drm device based logging
Prefer drm device based logging. Do some related dev_priv->i915 and
dp->intel_dp renames while at it.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_lspcon.c | 142 +++-
1 file changed, 76 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index e879d36c31ad..3d62a1d79f9c 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -78,11 +78,12 @@ static const char *lspcon_mode_name(enum drm_lspcon_mode
mode)
static bool lspcon_detect_vendor(struct intel_lspcon *lspcon)
{
struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
+ struct drm_i915_private *i915 = dp_to_i915(dp);
struct drm_dp_dpcd_ident *ident;
u32 vendor_oui;
if (drm_dp_read_desc(>aux, >desc, drm_dp_is_branch(dp->dpcd))) {
- DRM_ERROR("Can't read description\n");
+ drm_err(>drm, "Can't read description\n");
return false;
}
@@ -93,16 +94,16 @@ static bool lspcon_detect_vendor(struct intel_lspcon
*lspcon)
switch (vendor_oui) {
case LSPCON_VENDOR_MCA_OUI:
lspcon->vendor = LSPCON_VENDOR_MCA;
- DRM_DEBUG_KMS("Vendor: Mega Chips\n");
+ drm_dbg_kms(>drm, "Vendor: Mega Chips\n");
break;
case LSPCON_VENDOR_PARADE_OUI:
lspcon->vendor = LSPCON_VENDOR_PARADE;
- DRM_DEBUG_KMS("Vendor: Parade Tech\n");
+ drm_dbg_kms(>drm, "Vendor: Parade Tech\n");
break;
default:
- DRM_ERROR("Invalid/Unknown vendor OUI\n");
+ drm_err(>drm, "Invalid/Unknown vendor OUI\n");
return false;
}
@@ -119,21 +120,19 @@ static u32 get_hdr_status_reg(struct intel_lspcon *lspcon)
void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon)
{
- struct intel_digital_port *dig_port =
- container_of(lspcon, struct intel_digital_port, lspcon);
- struct drm_device *dev = dig_port->base.base.dev;
- struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
+ struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 hdr_caps;
int ret;
- ret = drm_dp_dpcd_read(>aux, get_hdr_status_reg(lspcon),
+ ret = drm_dp_dpcd_read(_dp->aux, get_hdr_status_reg(lspcon),
_caps, 1);
if (ret < 0) {
- drm_dbg_kms(dev, "HDR capability detection failed\n");
+ drm_dbg_kms(>drm, "HDR capability detection failed\n");
lspcon->hdr_supported = false;
} else if (hdr_caps & 0x1) {
- drm_dbg_kms(dev, "LSPCON capable of HDR\n");
+ drm_dbg_kms(>drm, "LSPCON capable of HDR\n");
lspcon->hdr_supported = true;
}
}
@@ -141,11 +140,12 @@ void lspcon_detect_hdr_capability(struct intel_lspcon
*lspcon)
static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon
*lspcon)
{
struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
enum drm_lspcon_mode current_mode;
struct i2c_adapter *adapter = _dp->aux.ddc;
if (drm_lspcon_get_mode(intel_dp->aux.drm_dev, adapter, _mode))
{
- DRM_DEBUG_KMS("Error reading LSPCON mode\n");
+ drm_dbg_kms(>drm, "Error reading LSPCON mode\n");
return DRM_LSPCON_MODE_INVALID;
}
return current_mode;
@@ -154,22 +154,24 @@ static enum drm_lspcon_mode
lspcon_get_current_mode(struct intel_lspcon *lspcon)
static enum drm_lspcon_mode lspcon_wait_mode(struct intel_lspcon *lspcon,
enum drm_lspcon_mode mode)
{
+ struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
enum drm_lspcon_mode current_mode;
current_mode = lspcon_get_current_mode(lspcon);
if (current_mode == mode)
goto out;
- DRM_DEBUG_KMS("Waiting for LSPCON mode %s to settle\n",
- lspcon_mode_name(mode));
+ drm_dbg_kms(>drm, "Waiting for LSPCON mode %s to settle\n",
+ lspcon_mode_name(mode));
wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode, 400);
if (current_mode != mode)
- DRM_ERROR("LSPCON mode hasn't settled\n");
+ drm_err(>drm, "LSPCON mode hasn't settled\n");
out:
- DRM_DEBUG_KMS("Current LSPCON mode %s\n",
- lspcon_mode_name(current_mode));
+ drm_dbg_kms(>drm, "Current LSPCON mode %s\n",
+ lspcon_mode_name(current_mode));
return current_mode;
}
@@ -178,44 +180,47 @@ static int
[Intel-gfx] [PATCH 6/9] drm/i915/sprite: convert to drm device based logging
Prefer drm device based logging.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_sprite.c | 24 +++--
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 7ffca5669ab9..2d71294aaceb 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -53,6 +53,7 @@
int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
{
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
struct drm_rect *src = _state->uapi.src;
u32 src_x, src_y, src_w, src_h, hsub, vsub;
@@ -94,14 +95,14 @@ int intel_plane_check_src_coordinates(struct
intel_plane_state *plane_state)
hsub = vsub = max(hsub, vsub);
if (src_x % hsub || src_w % hsub) {
- DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of %u
(rotated: %s)\n",
- src_x, src_w, hsub, yesno(rotated));
+ drm_dbg_kms(>drm, "src x/w (%u, %u) must be a multiple of
%u (rotated: %s)\n",
+ src_x, src_w, hsub, yesno(rotated));
return -EINVAL;
}
if (src_y % vsub || src_h % vsub) {
- DRM_DEBUG_KMS("src y/h (%u, %u) must be a multiple of %u
(rotated: %s)\n",
- src_y, src_h, vsub, yesno(rotated));
+ drm_dbg_kms(>drm, "src y/h (%u, %u) must be a multiple of
%u (rotated: %s)\n",
+ src_y, src_h, vsub, yesno(rotated));
return -EINVAL;
}
@@ -1332,6 +1333,7 @@ static int
g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
const struct drm_rect *src = _state->uapi.src;
const struct drm_rect *dst = _state->uapi.dst;
@@ -1357,7 +1359,7 @@ g4x_sprite_check_scaling(struct intel_crtc_state
*crtc_state,
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
if (src_h & 1) {
- DRM_DEBUG_KMS("Source height must be even with
interlaced modes\n");
+ drm_dbg_kms(>drm, "Source height must be even
with interlaced modes\n");
return -EINVAL;
}
min_height = 6;
@@ -1369,20 +1371,20 @@ g4x_sprite_check_scaling(struct intel_crtc_state
*crtc_state,
if (src_w < min_width || src_h < min_height ||
src_w > 2048 || src_h > 2048) {
- DRM_DEBUG_KMS("Source dimensions (%dx%d) exceed hardware limits
(%dx%d - %dx%d)\n",
- src_w, src_h, min_width, min_height, 2048, 2048);
+ drm_dbg_kms(>drm, "Source dimensions (%dx%d) exceed
hardware limits (%dx%d - %dx%d)\n",
+ src_w, src_h, min_width, min_height, 2048, 2048);
return -EINVAL;
}
if (width_bytes > 4096) {
- DRM_DEBUG_KMS("Fetch width (%d) exceeds hardware max with
scaling (%u)\n",
- width_bytes, 4096);
+ drm_dbg_kms(>drm, "Fetch width (%d) exceeds hardware max
with scaling (%u)\n",
+ width_bytes, 4096);
return -EINVAL;
}
if (stride > 4096) {
- DRM_DEBUG_KMS("Stride (%u) exceeds hardware max with scaling
(%u)\n",
- stride, 4096);
+ drm_dbg_kms(>drm, "Stride (%u) exceeds hardware max with
scaling (%u)\n",
+ stride, 4096);
return -EINVAL;
}
--
2.30.2
[Intel-gfx] [PATCH 5/9] drm/i915/plane: convert to drm device based logging and WARN
Prefer drm device based logging and WARN.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 5 +++--
drivers/gpu/drm/i915/display/skl_universal_plane.c | 10 ++
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index c2c512cd8ec0..dd51818f6684 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -601,6 +601,7 @@ int intel_atomic_plane_check_clipping(struct
intel_plane_state *plane_state,
int min_scale, int max_scale,
bool can_position)
{
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
struct drm_framebuffer *fb = plane_state->hw.fb;
struct drm_rect *src = _state->uapi.src;
struct drm_rect *dst = _state->uapi.dst;
@@ -619,7 +620,7 @@ int intel_atomic_plane_check_clipping(struct
intel_plane_state *plane_state,
hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
if (hscale < 0 || vscale < 0) {
- DRM_DEBUG_KMS("Invalid scaling of plane\n");
+ drm_dbg_kms(>drm, "Invalid scaling of plane\n");
drm_rect_debug_print("src: ", src, true);
drm_rect_debug_print("dst: ", dst, false);
return -ERANGE;
@@ -644,7 +645,7 @@ int intel_atomic_plane_check_clipping(struct
intel_plane_state *plane_state,
if (!can_position && plane_state->uapi.visible &&
!drm_rect_equals(dst, )) {
- DRM_DEBUG_KMS("Plane must cover entire CRTC\n");
+ drm_dbg_kms(>drm, "Plane must cover entire CRTC\n");
drm_rect_debug_print("dst: ", dst, false);
drm_rect_debug_print("clip: ", , false);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 72dcc341bb1f..1223075595ff 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -961,6 +961,7 @@ static u32 glk_plane_color_ctl(const struct
intel_crtc_state *crtc_state,
static u32 skl_surf_address(const struct intel_plane_state *plane_state,
int color_plane)
{
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
u32 offset = plane_state->view.color_plane[color_plane].offset;
@@ -969,11 +970,11 @@ static u32 skl_surf_address(const struct
intel_plane_state *plane_state,
* The DPT object contains only one vma, so the VMA's offset
* within the DPT is always 0.
*/
- WARN_ON(plane_state->dpt_vma->node.start);
- WARN_ON(offset & 0x1f);
+ drm_WARN_ON(>drm, plane_state->dpt_vma->node.start);
+ drm_WARN_ON(>drm, offset & 0x1f);
return offset >> 9;
} else {
- WARN_ON(offset & 0xfff);
+ drm_WARN_ON(>drm, offset & 0xfff);
return offset;
}
}
@@ -1350,6 +1351,7 @@ static int skl_plane_check_dst_coordinates(const struct
intel_crtc_state *crtc_s
static int skl_plane_check_nv12_rotation(const struct intel_plane_state
*plane_state)
{
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
unsigned int rotation = plane_state->hw.rotation;
int src_w = drm_rect_width(_state->uapi.src) >> 16;
@@ -1359,7 +1361,7 @@ static int skl_plane_check_nv12_rotation(const struct
intel_plane_state *plane_s
src_w & 3 &&
(rotation == DRM_MODE_ROTATE_270 ||
rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) {
- DRM_DEBUG_KMS("src width must be multiple of 4 for rotated
planar YUV\n");
+ drm_dbg_kms(>drm, "src width must be multiple of 4 for
rotated planar YUV\n");
return -EINVAL;
}
--
2.30.2
[Intel-gfx] [PATCH 4/9] drm/i915/dp: convert to drm device based logging
Prefer drm device based logging.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 35 ++---
1 file changed, 20 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index cb726cee9e1d..9acbf8c59f6b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -704,7 +704,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
i915->max_cdclk_freq * 48 /
intel_dp_mode_to_fec_clock(mode_clock);
- DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
+ drm_dbg_kms(>drm, "Max big joiner bpp: %u\n",
max_bpp_bigjoiner);
bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
}
@@ -2919,7 +2919,8 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct
drm_dp_vsc_sdp *vsc,
}
static ssize_t
-intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe
*drm_infoframe,
+intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
+const struct hdmi_drm_infoframe
*drm_infoframe,
struct dp_sdp *sdp,
size_t size)
{
@@ -2935,12 +2936,12 @@ intel_dp_hdr_metadata_infoframe_sdp_pack(const struct
hdmi_drm_infoframe *drm_in
len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
if (len < 0) {
- DRM_DEBUG_KMS("buffer size is smaller than hdr metadata
infoframe\n");
+ drm_dbg_kms(>drm, "buffer size is smaller than hdr
metadata infoframe\n");
return -ENOSPC;
}
if (len != infoframe_size) {
- DRM_DEBUG_KMS("wrong static hdr metadata size\n");
+ drm_dbg_kms(>drm, "wrong static hdr metadata size\n");
return -ENOSPC;
}
@@ -3013,7 +3014,8 @@ static void intel_write_dp_sdp(struct intel_encoder
*encoder,
sizeof(sdp));
break;
case HDMI_PACKET_TYPE_GAMUT_METADATA:
- len =
intel_dp_hdr_metadata_infoframe_sdp_pack(_state->infoframes.drm.drm,
+ len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
+
_state->infoframes.drm.drm,
,
sizeof(sdp));
break;
default:
@@ -3421,22 +3423,22 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp,
switch (data->phy_pattern) {
case DP_PHY_TEST_PATTERN_NONE:
- DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
+ drm_dbg_kms(_priv->drm, "Disable Phy Test Pattern\n");
intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
break;
case DP_PHY_TEST_PATTERN_D10_2:
- DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
+ drm_dbg_kms(_priv->drm, "Set D10.2 Phy Test Pattern\n");
intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
break;
case DP_PHY_TEST_PATTERN_ERROR_COUNT:
- DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
+ drm_dbg_kms(_priv->drm, "Set Error Count Phy Test
Pattern\n");
intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
DDI_DP_COMP_CTL_ENABLE |
DDI_DP_COMP_CTL_SCRAMBLED_0);
break;
case DP_PHY_TEST_PATTERN_PRBS7:
- DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
+ drm_dbg_kms(_priv->drm, "Set PRBS7 Phy Test Pattern\n");
intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
break;
@@ -3446,7 +3448,8 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp,
* current firmware of DPR-100 could not set it, so hardcoding
* now for complaince test.
*/
- DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0
0x0f83e0f8 0xf83e\n");
+ drm_dbg_kms(_priv->drm,
+ "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0
0x0f83e0f8 0xf83e\n");
pattern_val = 0x3e0f83e0;
intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
pattern_val = 0x0f83e0f8;
@@ -3463,7 +3466,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp,
* current firmware of DPR-100 could not set it, so hardcoding
* now for complaince test.
*/
-
[Intel-gfx] [PATCH 3/9] drm/i915/hotplug: convert to drm device based logging
Prefer drm device based logging.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hotplug.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 955f6d07b0e1..912b7003dcfa 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -281,13 +281,13 @@ intel_encoder_hotplug(struct intel_encoder *encoder,
ret = true;
if (ret) {
- DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s
(epoch counter %llu->%llu)\n",
- connector->base.base.id,
- connector->base.name,
- drm_get_connector_status_name(old_status),
-
drm_get_connector_status_name(connector->base.status),
- old_epoch_counter,
- connector->base.epoch_counter);
+ drm_dbg_kms(dev, "[CONNECTOR:%d:%s] status updated from %s to
%s (epoch counter %llu->%llu)\n",
+ connector->base.base.id,
+ connector->base.name,
+ drm_get_connector_status_name(old_status),
+
drm_get_connector_status_name(connector->base.status),
+ old_epoch_counter,
+ connector->base.epoch_counter);
return INTEL_HOTPLUG_CHANGED;
}
return INTEL_HOTPLUG_UNCHANGED;
--
2.30.2
[Intel-gfx] [PATCH 2/9] drm/i915/pps: convert to drm device based logging
Prefer drm device based logging.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_pps.c | 22 +-
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index e9c679bb1b2e..9c986e8932f8 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1131,16 +1131,20 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp,
struct edp_power_seq *seq)
}
static void
-intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
+intel_pps_dump_state(struct intel_dp *intel_dp, const char *state_name,
+const struct edp_power_seq *seq)
{
- DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
- state_name,
- seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+ drm_dbg_kms(>drm, "%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
+ state_name,
+ seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
}
static void
intel_pps_verify_state(struct intel_dp *intel_dp)
{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct edp_power_seq hw;
struct edp_power_seq *sw = _dp->pps.pps_delays;
@@ -1148,9 +1152,9 @@ intel_pps_verify_state(struct intel_dp *intel_dp)
if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
- DRM_ERROR("PPS state mismatch\n");
- intel_pps_dump_state("sw", sw);
- intel_pps_dump_state("hw", );
+ drm_err(>drm, "PPS state mismatch\n");
+ intel_pps_dump_state(intel_dp, "sw", sw);
+ intel_pps_dump_state(intel_dp, "hw", );
}
}
@@ -1168,7 +1172,7 @@ static void pps_init_delays(struct intel_dp *intel_dp)
intel_pps_readout_hw_state(intel_dp, );
- intel_pps_dump_state("cur", );
+ intel_pps_dump_state(intel_dp, "cur", );
vbt = dev_priv->vbt.edp.pps;
/* On Toshiba Satellite P50-C-18C system the VBT T12 delay
@@ -1200,7 +1204,7 @@ static void pps_init_delays(struct intel_dp *intel_dp)
* too. */
spec.t11_t12 = (510 + 100) * 10;
- intel_pps_dump_state("vbt", );
+ intel_pps_dump_state(intel_dp, "vbt", );
/* Use the max of the register settings and vbt. If both are
* unset, fall back to the spec limits. */
--
2.30.2
[Intel-gfx] [PATCH 1/9] drm/i915/snps: convert to drm device based logging
Prefer drm device based logging. Do some dev_priv->i915 conversions
while at it.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_snps_phy.c | 29 ++-
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 718bfdbae9c8..8573a458811a 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -24,18 +24,18 @@
* since it is not handled by the shared DPLL framework as on other platforms.
*/
-void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv)
+void intel_snps_phy_wait_for_calibration(struct drm_i915_private *i915)
{
enum phy phy;
for_each_phy_masked(phy, ~0) {
- if (!intel_phy_is_snps(dev_priv, phy))
+ if (!intel_phy_is_snps(i915, phy))
continue;
- if (intel_de_wait_for_clear(dev_priv, ICL_PHY_MISC(phy),
+ if (intel_de_wait_for_clear(i915, ICL_PHY_MISC(phy),
DG2_PHY_DP_TX_ACK_MASK, 25))
- DRM_ERROR("SNPS PHY %c failed to calibrate after
25ms.\n",
- phy);
+ drm_err(>drm, "SNPS PHY %c failed to calibrate
after 25ms.\n",
+ phy);
}
}
@@ -776,6 +776,7 @@ intel_mpllb_tables_get(struct intel_crtc_state *crtc_state,
int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
const struct intel_mpllb_state * const *tables;
int i;
@@ -787,8 +788,8 @@ int intel_mpllb_calc_state(struct intel_crtc_state
*crtc_state,
* until we have a proper algorithm under a valid
* license.
*/
- DRM_DEBUG_KMS("Can't support HDMI link rate %d\n",
- crtc_state->port_clock);
+ drm_dbg_kms(>drm, "Can't support HDMI link rate
%d\n",
+ crtc_state->port_clock);
return -EINVAL;
}
}
@@ -855,7 +856,7 @@ void intel_mpllb_enable(struct intel_encoder *encoder,
* dp_mpllb_state interface signal.
*/
if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 5))
- DRM_ERROR("Port %c PLL not locked\n", phy_name(phy));
+ drm_dbg_kms(_priv->drm, "Port %c PLL not locked\n",
phy_name(phy));
/*
* 11. If the frequency will result in a change to the voltage
@@ -868,8 +869,8 @@ void intel_mpllb_enable(struct intel_encoder *encoder,
void intel_mpllb_disable(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
i915_reg_t enable_reg = (phy <= PHY_D ?
DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
@@ -882,21 +883,21 @@ void intel_mpllb_disable(struct intel_encoder *encoder)
*/
/* 2. Software programs DPLL_ENABLE [PLL Enable] to "0" */
- intel_uncore_rmw(_priv->uncore, enable_reg, PLL_ENABLE, 0);
+ intel_uncore_rmw(>uncore, enable_reg, PLL_ENABLE, 0);
/*
* 4. Software programs SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "0".
* This will allow the PLL to stop running.
*/
- intel_uncore_rmw(_priv->uncore, SNPS_PHY_MPLLB_DIV(phy),
+ intel_uncore_rmw(>uncore, SNPS_PHY_MPLLB_DIV(phy),
SNPS_PHY_MPLLB_FORCE_EN, 0);
/*
* 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment
* (dp_txX_ack) that the new transmitter setting request is completed.
*/
- if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_LOCK, 5))
- DRM_ERROR("Port %c PLL not locked\n", phy_name(phy));
+ if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 5))
+ drm_err(>drm, "Port %c PLL not locked\n", phy_name(phy));
/*
* 6. If the frequency will result in a change to the voltage
--
2.30.2
[Intel-gfx] [PATCH 0/9] drm/i915/display: drm device based logging conversions
Purge some accumulated drm device based logging changes from my local branches. Jani Nikula (9): drm/i915/snps: convert to drm device based logging drm/i915/pps: convert to drm device based logging drm/i915/hotplug: convert to drm device based logging drm/i915/dp: convert to drm device based logging drm/i915/plane: convert to drm device based logging and WARN drm/i915/sprite: convert to drm device based logging drm/i915/lspcon: convert to drm device based logging drm/i915/cdclk: update intel_dump_cdclk_config() logging drm/i915/cdclk: convert to drm device based logging .../gpu/drm/i915/display/intel_atomic_plane.c | 5 +- drivers/gpu/drm/i915/display/intel_cdclk.c| 23 +-- drivers/gpu/drm/i915/display/intel_cdclk.h| 3 +- drivers/gpu/drm/i915/display/intel_display.c | 2 +- .../drm/i915/display/intel_display_power.c| 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 35 +++-- drivers/gpu/drm/i915/display/intel_hotplug.c | 14 +- drivers/gpu/drm/i915/display/intel_lspcon.c | 142 ++ drivers/gpu/drm/i915/display/intel_pps.c | 22 +-- drivers/gpu/drm/i915/display/intel_snps_phy.c | 29 ++-- drivers/gpu/drm/i915/display/intel_sprite.c | 24 +-- .../drm/i915/display/skl_universal_plane.c| 10 +- 12 files changed, 169 insertions(+), 142 deletions(-) -- 2.30.2
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Futher optimize plane updates
== Series Details == Series: drm/i915: Futher optimize plane updates URL : https://patchwork.freedesktop.org/series/99149/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [PATCH v9 3/6] drm: implement top-down allocation method
On 19/01/2022 11:37, Arunpravin wrote:
Implemented a function which walk through the order list,
compares the offset and returns the maximum offset block,
this method is unpredictable in obtaining the high range
address blocks which depends on allocation and deallocation.
for instance, if driver requests address at a low specific
range, allocator traverses from the root block and splits
the larger blocks until it reaches the specific block and
in the process of splitting, lower orders in the freelist
are occupied with low range address blocks and for the
subsequent TOPDOWN memory request we may return the low
range blocks.To overcome this issue, we may go with the
below approach.
The other approach, sorting each order list entries in
ascending order and compares the last entry of each
order list in the freelist and return the max block.
This creates sorting overhead on every drm_buddy_free()
request and split up of larger blocks for a single page
request.
v2:
- Fix alignment issues(Matthew Auld)
- Remove unnecessary list_empty check(Matthew Auld)
- merged the below patch to see the feature in action
- add top-down alloc support to i915 driver
Signed-off-by: Arunpravin
---
drivers/gpu/drm/drm_buddy.c | 36 ---
drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 3 ++
include/drm/drm_buddy.h | 1 +
3 files changed, 35 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index 954e31962c74..6aa5c1ce25bf 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -371,6 +371,26 @@ alloc_range_bias(struct drm_buddy *mm,
return ERR_PTR(err);
}
+static struct drm_buddy_block *
+get_maxblock(struct list_head *head)
+{
+ struct drm_buddy_block *max_block = NULL, *node;
+
+ max_block = list_first_entry_or_null(head,
+struct drm_buddy_block,
+link);
+ if (!max_block)
+ return NULL;
+
+ list_for_each_entry(node, head, link) {
+ if (drm_buddy_block_offset(node) >
+ drm_buddy_block_offset(max_block))
+ max_block = node;
+ }
If we feed in the knowledge of the visible_size(or perhaps implement
that generically as "zones"), I think this can be done more efficiently.
It could also be useful to track directly in the allocator how much of
the visible_size is still available, rather than having to do that in
the upper levels by scanning the entire list. But hopefully in practice
this should be good enough for our needs,
Reviewed-by: Matthew Auld
+
+ return max_block;
+}
+
static struct drm_buddy_block *
alloc_from_freelist(struct drm_buddy *mm,
unsigned int order,
@@ -381,11 +401,17 @@ alloc_from_freelist(struct drm_buddy *mm,
int err;
for (i = order; i <= mm->max_order; ++i) {
- block = list_first_entry_or_null(>free_list[i],
-struct drm_buddy_block,
-link);
- if (block)
- break;
+ if (flags & DRM_BUDDY_TOPDOWN_ALLOCATION) {
+ block = get_maxblock(>free_list[i]);
+ if (block)
+ break;
+ } else {
+ block = list_first_entry_or_null(>free_list[i],
+struct drm_buddy_block,
+link);
+ if (block)
+ break;
+ }
}
if (!block)
diff --git a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
index 1411f4cf1f21..3662434b64bb 100644
--- a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
+++ b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
@@ -53,6 +53,9 @@ static int i915_ttm_buddy_man_alloc(struct
ttm_resource_manager *man,
INIT_LIST_HEAD(_res->blocks);
bman_res->mm = mm;
+ if (place->flags & TTM_PL_FLAG_TOPDOWN)
+ bman_res->flags |= DRM_BUDDY_TOPDOWN_ALLOCATION;
+
if (place->fpfn || lpfn != man->size)
bman_res->flags |= DRM_BUDDY_RANGE_ALLOCATION;
diff --git a/include/drm/drm_buddy.h b/include/drm/drm_buddy.h
index 865664b90a8a..424fc443115e 100644
--- a/include/drm/drm_buddy.h
+++ b/include/drm/drm_buddy.h
@@ -28,6 +28,7 @@
})
#define DRM_BUDDY_RANGE_ALLOCATION (1 << 0)
+#define DRM_BUDDY_TOPDOWN_ALLOCATION (1 << 1)
struct drm_buddy_block {
#define DRM_BUDDY_HEADER_OFFSET GENMASK_ULL(63, 12)
Re: [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
On Fri, Jan 21, 2022 at 10:06:15AM +0200, Stanislav Lisovskiy wrote:
> In terms of async flip optimization we don't to allocate
> extra ddb space, so lets skip it.
>
> v2: - Extracted min ddb async flip check to separate function
> (Ville Syrjälä)
> - Used this function to prevent false positive WARN
> to be triggered(Ville Syrjälä)
>
> v3: - Renamed dg2_need_min_ddb to need_min_ddb thus making
> it more universal.
> - Also used DISPLAY_VER instead of IS_DG2(Ville Syrjälä)
> - Use rate = 0 instead of just setting extra = 0, thus
> letting other planes to use extra ddb and avoiding WARN
> (Ville Syrjälä)
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/intel_pm.c | 17 +
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5fb022a2a4d7..18fb35c480ef 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5118,6 +5118,12 @@ static bool icl_need_wm1_wa(struct drm_i915_private
> *i915,
> (IS_DISPLAY_VER(i915, 12, 13) && plane_id == PLANE_CURSOR);
> }
>
> +static bool needs_min_ddb(struct drm_i915_private *i915,
> + struct intel_crtc_state *crtc_state)
s/needs/use/ to match the wm0 counterpart?
Could use a comment as well perhaps, or maybe just put this right
next to the wm0 counterpart so the reader can see both together and
make the connection.
Hmm. Actually I think this would also need the plane->async_flip
check here too or else we'll drop all the planes to min ddb
instead of just the plane doing async flips.
Oh, and I think we need this same thing when calculating the
total_data_rate or else the numbers won't match.
> +{
> + return DISPLAY_VER(i915) >= 13 && crtc_state->uapi.async_flip;
> +}
> +
> static int
> skl_allocate_plane_ddb(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> @@ -5225,9 +5231,14 @@ skl_allocate_plane_ddb(struct intel_atomic_state
> *state,
> break;
>
> rate = crtc_state->plane_data_rate[plane_id];
> +
> + if (needs_min_ddb(dev_priv, crtc_state))
> + rate = 0;
> +
> extra = min_t(u16, alloc_size,
> DIV64_U64_ROUND_UP(alloc_size * rate,
>total_data_rate));
> +
> total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
> alloc_size -= extra;
> total_data_rate -= rate;
> @@ -5236,13 +5247,19 @@ skl_allocate_plane_ddb(struct intel_atomic_state
> *state,
> break;
>
> rate = crtc_state->uv_plane_data_rate[plane_id];
> +
> + if (needs_min_ddb(dev_priv, crtc_state))
> + rate = 0;
> +
> extra = min_t(u16, alloc_size,
> DIV64_U64_ROUND_UP(alloc_size * rate,
>total_data_rate));
> +
> uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
> alloc_size -= extra;
> total_data_rate -= rate;
> }
> +
> drm_WARN_ON(_priv->drm, alloc_size != 0 || total_data_rate != 0);
>
> /* Set the actual DDB start/end points for each plane */
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH v9 2/6] drm: improve drm_buddy_alloc function
On 19/01/2022 11:37, Arunpravin wrote:
- Make drm_buddy_alloc a single function to handle
range allocation and non-range allocation demands
- Implemented a new function alloc_range() which allocates
the requested power-of-two block comply with range limitations
- Moved order computation and memory alignment logic from
i915 driver to drm buddy
v2:
merged below changes to keep the build unbroken
- drm_buddy_alloc_range() becomes obsolete and may be removed
- enable ttm range allocation (fpfn / lpfn) support in i915 driver
- apply enhanced drm_buddy_alloc() function to i915 driver
v3(Matthew Auld):
- Fix alignment issues and remove unnecessary list_empty check
- add more validation checks for input arguments
- make alloc_range() block allocations as bottom-up
- optimize order computation logic
- replace uint64_t with u64, which is preferred in the kernel
v4(Matthew Auld):
- keep drm_buddy_alloc_range() function implementation for generic
actual range allocations
- keep alloc_range() implementation for end bias allocations
v5(Matthew Auld):
- modify drm_buddy_alloc() passing argument place->lpfn to lpfn
as place->lpfn will currently always be zero for i915
v6(Matthew Auld):
- fixup potential uaf - If we are unlucky and can't allocate
enough memory when splitting blocks, where we temporarily
end up with the given block and its buddy on the respective
free list, then we need to ensure we delete both blocks,
and no just the buddy, before potentially freeing them
Hmm, not sure we really want to squash existing bug fixes into this
patch. Perhaps bring in [1] to the start of your series? i915_buddy is
gone now. Alternatively I can resend such that it applies on top
drm_buddy. Your choice.
[1] https://patchwork.freedesktop.org/patch/469806/?series=98953=1
- fix warnings reported by kernel test robot
Signed-off-by: Arunpravin
---
drivers/gpu/drm/drm_buddy.c | 326 +-
drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 67 ++--
drivers/gpu/drm/i915/i915_ttm_buddy_manager.h | 2 +
include/drm/drm_buddy.h | 22 +-
4 files changed, 293 insertions(+), 124 deletions(-)
diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index d60878bc9c20..954e31962c74 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -282,23 +282,99 @@ void drm_buddy_free_list(struct drm_buddy *mm, struct
list_head *objects)
}
EXPORT_SYMBOL(drm_buddy_free_list);
-/**
- * drm_buddy_alloc_blocks - allocate power-of-two blocks
- *
- * @mm: DRM buddy manager to allocate from
- * @order: size of the allocation
- *
- * The order value here translates to:
- *
- * 0 = 2^0 * mm->chunk_size
- * 1 = 2^1 * mm->chunk_size
- * 2 = 2^2 * mm->chunk_size
- *
- * Returns:
- * allocated ptr to the _buddy_block on success
- */
-struct drm_buddy_block *
-drm_buddy_alloc_blocks(struct drm_buddy *mm, unsigned int order)
+static inline bool overlaps(u64 s1, u64 e1, u64 s2, u64 e2)
+{
+ return s1 <= e2 && e1 >= s2;
+}
+
+static inline bool contains(u64 s1, u64 e1, u64 s2, u64 e2)
+{
+ return s1 <= s2 && e1 >= e2;
+}
+
+static struct drm_buddy_block *
+alloc_range_bias(struct drm_buddy *mm,
+u64 start, u64 end,
+unsigned int order)
+{
+ struct drm_buddy_block *block;
+ struct drm_buddy_block *buddy;
+ LIST_HEAD(dfs);
+ int err;
+ int i;
+
+ end = end - 1;
+
+ for (i = 0; i < mm->n_roots; ++i)
+ list_add_tail(>roots[i]->tmp_link, );
+
+ do {
+ u64 block_start;
+ u64 block_end;
+
+ block = list_first_entry_or_null(,
+struct drm_buddy_block,
+tmp_link);
+ if (!block)
+ break;
+
+ list_del(>tmp_link);
+
+ if (drm_buddy_block_order(block) < order)
+ continue;
+
+ block_start = drm_buddy_block_offset(block);
+ block_end = block_start + drm_buddy_block_size(mm, block) - 1;
+
+ if (!overlaps(start, end, block_start, block_end))
+ continue;
+
+ if (drm_buddy_block_is_allocated(block))
+ continue;
+
+ if (contains(start, end, block_start, block_end) &&
+ order == drm_buddy_block_order(block)) {
+ /*
+* Find the free block within the range.
+*/
+ if (drm_buddy_block_is_free(block))
+ return block;
+
+ continue;
+ }
+
+ if (!drm_buddy_block_is_split(block)) {
+ err = split_block(mm, block);
+ if
Re: [Intel-gfx] [PATCH 3/4] drm/i915: Use wm0 only during async flips for DG2
On Fri, Jan 21, 2022 at 10:06:14AM +0200, Stanislav Lisovskiy wrote:
> This optimization allows to achieve higher perfomance
> during async flips.
> For the first async flip we have to still temporarily
> switch to sync flip, in order to reprogram plane
> watermarks, so this requires taking into account
> old plane state's do_async_flip flag.
>
> v2: - Removed redundant new_plane_state->do_async_flip
> check from needs_async_flip_wm_override condition
> (Ville Syrjälä)
> - Extract dg2_async_flip_optimization to separate
> function(Ville Syrjälä)
> - Check for plane->async_flip instead of plane_id
> (Ville Syrjälä)
>
> v3: - Rename "needs_async_flip_wm_override" to
> "intel_plane_do_async_flip" and move all the required
> checks there (Ville Syrjälä)
> - Rename "dg2_async_flip_optimization" to
> "use_minimal_wm0_only" (Ville Syrjälä)
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 24 +++-
> drivers/gpu/drm/i915/intel_pm.c | 12 +-
> 2 files changed, 34 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 9996daa036a0..3b86ede01b57 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4910,6 +4910,28 @@ static bool needs_scaling(const struct
> intel_plane_state *state)
> return (src_w != dst_w || src_h != dst_h);
> }
>
> +static bool intel_plane_do_async_flip(struct intel_plane *plane,
> + const struct intel_crtc_state
> *new_crtc_state,
> + const struct intel_crtc_state
> *old_crtc_state)
I think typically we put the old state before the new state.
Sadly the compiler can't help us with these so we should try
to be consistent to avoid accidental mishaps.
> +{
> + struct drm_i915_private *i915 = to_i915(new_crtc_state->uapi.crtc->dev);
Would be a bit shorter to grab this from plane->base.dev
> +
> + if (!plane->async_flip)
> + return false;
> +
> + if (!new_crtc_state->uapi.async_flip)
> + return false;
> +
> + /*
> + * In platforms after DISPLAY13, we might need to override
> + * first async flip in order to change watermark levels
> + * as part of optimization.
> + * So for those, we are checking if this is a first async flip.
> + * For platforms earlier than DISPLAY13 we always do async flip.
> + */
> + return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip;
> +}
> +
> int intel_plane_atomic_calc_changes(const struct intel_crtc_state
> *old_crtc_state,
> struct intel_crtc_state *new_crtc_state,
> const struct intel_plane_state
> *old_plane_state,
> @@ -5029,7 +5051,7 @@ int intel_plane_atomic_calc_changes(const struct
> intel_crtc_state *old_crtc_stat
>needs_scaling(new_plane_state
> new_crtc_state->disable_lp_wm = true;
>
> - if (new_crtc_state->uapi.async_flip && plane->async_flip)
> + if (intel_plane_do_async_flip(plane, new_crtc_state, old_crtc_state))
> new_plane_state->do_async_flip = true;
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 35d0bd8c6e57..5fb022a2a4d7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5510,6 +5510,15 @@ static int skl_wm_max_lines(struct drm_i915_private
> *dev_priv)
> return 31;
> }
>
> +static bool use_minimal_wm0_only(struct drm_i915_private *i915,
We can dig out 'i915' from eg. the plane, so no need for the
caller to pass it in.
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane *plane)
> +{
Atypical 'const' still on the plane pointer here.
Apart from those lgtm
Reviewed-by: Ville Syrjälä
> + return DISPLAY_VER(i915) >= 13 &&
> +crtc_state->uapi.async_flip &&
> +plane->async_flip;
> +}
> +
> static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
>const struct intel_plane *plane,
>int level,
> @@ -5523,7 +5532,8 @@ static void skl_compute_plane_wm(const struct
> intel_crtc_state *crtc_state,
> uint_fixed_16_16_t selected_result;
> u32 blocks, lines, min_ddb_alloc = 0;
>
> - if (latency == 0) {
> + if (latency == 0 ||
> + (use_minimal_wm0_only(dev_priv, crtc_state, plane) && level > 0)) {
> /* reject it */
> result->min_ddb_alloc = U16_MAX;
> return;
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH 6/7] drm: Document fdinfo format specification
On 20/01/2022 16:44, Rob Clark wrote: On Wed, Jan 19, 2022 at 7:09 AM Daniel Vetter wrote: On Thu, Jan 06, 2022 at 04:55:35PM +, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Proposal to standardise the fdinfo text format as optionally output by DRM drivers. Idea is that a simple but, well defined, spec will enable generic userspace tools to be written while at the same time avoiding a more heavy handed approach of adding a mid-layer to DRM. i915 implements a subset of the spec, everything apart from the memory stats currently, and a matching intel_gpu_top tool exists. Open is to see if AMD can migrate to using the proposed GPU utilisation key-value pairs, or if they are not workable to see whether to go vendor specific, or if a standardised alternative can be found which is workable for both drivers. Same for the memory utilisation key-value pairs proposal. v2: * Update for removal of name and pid. v3: * 'Drm-driver' tag will be obtained from struct drm_driver.name. (Daniel) Signed-off-by: Tvrtko Ursulin Cc: David M Nieto Cc: Christian König Cc: Daniel Vetter Cc: Daniel Stone Cc: Chris Healy Acked-by: Christian König I'm assuming this ack here and later on is a "amdgpu plans to use this too" kind of affair. Especially also in the lights of eventually using matching semantics for cgroups and everything else tied to gpu execution resource management. If not I'm mildly worried that we're creating fake-standard stuff here which cannot actually be used by anything resembling driver-agnostic userspace. I think I could implement something like this for drm/msm. I am a bit uncertain about the memory stats (ie. how are we intended to account for imported/exported/shared bo's)? But we already track cycles+time per submit for devfreq, it would be pretty easy to add per drm_file counters to accumulate the per-submit results. We could even track per-context (submitqueue) for processes that have more than a single context, although not sure if that is useful. Interesting tidbit is that the whole i915 work started from a customer request to expose just that (per context) in a form akin to getrusage(2). I think this kind of introspection capability is interesting but as it is driver specific territory it's only anecdotal for what this thread is concerned. And I think there is probably some room for shared helper to print parts other than the per-engine stats (and maybe memory stats, although even that could be a shared implementation for some drivers).. with a driver callback for the non-generic parts, ie. something like: drm_driver::show_client_stats(struct drm_file *, struct drm_printer *) but that can come later. If there is a tool somewhere that displays this info, that would be useful for testing my implementation. I have a patch to Intel specific intel_gpu_top (see https://patchwork.freedesktop.org/patch/468491/?series=98555=1). I'll have a look to see how much work would it be to extract common bits into a library and write a quick agnostic tool using it. Regards, Tvrtko
Re: [Intel-gfx] [PATCH 2/4] drm/i915: Introduce do_async_flip flag to intel_plane_state
On Fri, Jan 21, 2022 at 10:06:13AM +0200, Stanislav Lisovskiy wrote:
> There might be various logical contructs when we might want
> to enable async flip, so lets calculate those and set this
> flag, so that there is no need in long conditions in other
> places.
>
> v2: - Set do_async_flip flag to False, if no async flip needed.
> Lets not rely that it will be 0-initialized, but set
> explicitly, so that the logic is clear as well.
>
> v3: - Clear do_async_flip in intel_plane_duplicate_state(Ville Syrjälä)
> - Check with do_async_flip also when calling
> intel_crtc_{enable,disable}_flip_done(Ville Syrjälä)
>
> Signed-off-by: Stanislav Lisovskiy
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_atomic_plane.c | 3 ++-
> drivers/gpu/drm/i915/display/intel_display.c | 9 +++--
> drivers/gpu/drm/i915/display/intel_display_types.h | 3 +++
> 3 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index d1344e9c06de..9d79ab987b2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -109,6 +109,7 @@ intel_plane_duplicate_state(struct drm_plane *plane)
> intel_state->ggtt_vma = NULL;
> intel_state->dpt_vma = NULL;
> intel_state->flags = 0;
> + intel_state->do_async_flip = false;
>
> /* add reference to fb */
> if (intel_state->hw.fb)
> @@ -491,7 +492,7 @@ void intel_plane_update_arm(struct intel_plane *plane,
>
> trace_intel_plane_update_arm(>base, crtc);
>
> - if (crtc_state->uapi.async_flip && plane->async_flip)
> + if (plane_state->do_async_flip)
> plane->async_flip(plane, crtc_state, plane_state, true);
> else
> plane->update_arm(plane, crtc_state, plane_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 55cd453c4ce5..9996daa036a0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1369,7 +1369,8 @@ static void intel_crtc_enable_flip_done(struct
> intel_atomic_state *state,
> for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> if (plane->enable_flip_done &&
> plane->pipe == crtc->pipe &&
> - update_planes & BIT(plane->id))
> + update_planes & BIT(plane->id) &&
> + plane_state->do_async_flip)
> plane->enable_flip_done(plane);
> }
> }
> @@ -1387,7 +1388,8 @@ static void intel_crtc_disable_flip_done(struct
> intel_atomic_state *state,
> for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> if (plane->disable_flip_done &&
> plane->pipe == crtc->pipe &&
> - update_planes & BIT(plane->id))
> + update_planes & BIT(plane->id) &&
> + plane_state->do_async_flip)
> plane->disable_flip_done(plane);
> }
> }
> @@ -5027,6 +5029,9 @@ int intel_plane_atomic_calc_changes(const struct
> intel_crtc_state *old_crtc_stat
>needs_scaling(new_plane_state
> new_crtc_state->disable_lp_wm = true;
>
> + if (new_crtc_state->uapi.async_flip && plane->async_flip)
> + new_plane_state->do_async_flip = true;
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 41e3dd25a78f..6b107872ad39 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -634,6 +634,9 @@ struct intel_plane_state {
>
> struct intel_fb_view view;
>
> + /* Indicates if async flip is required */
> + bool do_async_flip;
> +
> /* Plane pxp decryption state */
> bool decrypt;
>
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH 1/4] drm/i915: Pass plane to watermark calculation functions
On Fri, Jan 21, 2022 at 10:06:12AM +0200, Stanislav Lisovskiy wrote:
> Sometimes we might need to change the way we calculate
> watermarks, based on which particular plane it is calculated
> for. Thus it would be convenient to pass plane struct to those
> functions.
>
> v2: Pass plane instead of plane_id
> v3: Do not pass plane to skl_cursor_allocation(Ville Syrjälä)
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
> .../gpu/drm/i915/display/intel_atomic_plane.h | 3 +++
> drivers/gpu/drm/i915/intel_pm.c | 20 +--
> 3 files changed, 18 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index c2c512cd8ec0..d1344e9c06de 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -373,7 +373,7 @@ int intel_plane_atomic_check_with_state(const struct
> intel_crtc_state *old_crtc_
> old_plane_state,
> new_plane_state);
> }
>
> -static struct intel_plane *
> +struct intel_plane *
> intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)
> {
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> index 7907f601598e..c1499bb7370e 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> @@ -16,10 +16,13 @@ struct intel_crtc;
> struct intel_crtc_state;
> struct intel_plane;
> struct intel_plane_state;
> +enum plane_id;
>
> unsigned int intel_adjusted_rate(const struct drm_rect *src,
>const struct drm_rect *dst,
>unsigned int rate);
> +struct intel_plane *intel_crtc_get_plane(struct intel_crtc *crtc,
> + enum plane_id plane_id);
You're no longer using that, so can stay static.
> unsigned int intel_plane_pixel_rate(const struct intel_crtc_state
> *crtc_state,
> const struct intel_plane_state
> *plane_state);
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3981aa856cc2..35d0bd8c6e57 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4252,7 +4252,9 @@ static int skl_compute_wm_params(const struct
> intel_crtc_state *crtc_state,
>u64 modifier, unsigned int rotation,
>u32 plane_pixel_rate, struct skl_wm_params *wp,
>int color_plane);
> +
> static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane *plane,
>int level,
>unsigned int latency,
>const struct skl_wm_params *wp,
> @@ -4268,6 +4270,7 @@ skl_cursor_allocation(const struct intel_crtc_state
> *crtc_state,
> struct skl_wm_level wm = {};
> int ret, min_ddb_alloc = 0;
> struct skl_wm_params wp;
> + const struct intel_plane *cursor_plane =
> to_intel_plane(crtc_state->uapi.crtc->cursor);
I think just 'plane' would suffice since we know from the context what
it is. Also sticking to the reverse christmas tree order would look a
bit neater imo.
>
> ret = skl_compute_wm_params(crtc_state, 256,
> drm_format_info(DRM_FORMAT_ARGB),
> @@ -4279,7 +4282,7 @@ skl_cursor_allocation(const struct intel_crtc_state
> *crtc_state,
> for (level = 0; level <= max_level; level++) {
> unsigned int latency = dev_priv->wm.skl_latency[level];
>
> - skl_compute_plane_wm(crtc_state, level, latency, , , );
> + skl_compute_plane_wm(crtc_state, cursor_plane, level, latency,
> , , );
> if (wm.min_ddb_alloc == U16_MAX)
> break;
>
> @@ -5508,6 +5511,7 @@ static int skl_wm_max_lines(struct drm_i915_private
> *dev_priv)
> }
>
> static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane *plane,
>int level,
>unsigned int latency,
>const struct skl_wm_params *wp,
> @@ -5635,6 +5639,7 @@ static void skl_compute_plane_wm(const struct
> intel_crtc_state *crtc_state,
>
> static void
> skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane *plane,
> const struct skl_wm_params *wm_params,
> struct skl_wm_level *levels)
> {
> @@ -5646,7 +5651,7 @@ skl_compute_wm_levels(const
[Intel-gfx] ✓ Fi.CI.BAT: success for Async flip optimization for DG2 (rev4)
== Series Details == Series: Async flip optimization for DG2 (rev4) URL : https://patchwork.freedesktop.org/series/98981/ State : success == Summary == CI Bug Log - changes from CI_DRM_7 -> Patchwork_22054 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22054/index.html Participating hosts (46 -> 35) -- Missing(11): fi-ilk-m540 bat-dg1-6 fi-hsw-4200u fi-icl-u2 fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-bdw-samus bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_22054 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3@smem: - fi-bdw-5557u: [PASS][1] -> [INCOMPLETE][2] ([i915#146]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22054/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html * igt@i915_selftest@live@hangcheck: - fi-hsw-4770:[PASS][3] -> [INCOMPLETE][4] ([i915#3303]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22054/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html * igt@runner@aborted: - fi-hsw-4770:NOTRUN -> [FAIL][5] ([fdo#109271] / [i915#1436] / [i915#4312]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22054/fi-hsw-4770/igt@run...@aborted.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 Build changes - * Linux: CI_DRM_7 -> Patchwork_22054 CI-20190529: 20190529 CI_DRM_7: 78a44103a76675b9916b8f0c1e9d1da370f2830f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6329: 38f656fdd61119105ecfa2c4dac157cd7dcad204 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_22054: 57d60bca103b41d7c7469748a7c7d5feeb94e9b3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 57d60bca103b drm/i915: Don't allocate extra ddb during async flip for DG2 8a01e4903796 drm/i915: Use wm0 only during async flips for DG2 3328aa934fa7 drm/i915: Introduce do_async_flip flag to intel_plane_state a21feb89e84d drm/i915: Pass plane to watermark calculation functions == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22054/index.html
[Intel-gfx] [PATCH 6/6] drm/i915: Make pre-skl sprite plane registers unlocked
From: Ville Syrjälä
Drop the locks around sprite plane register writes. The
lock isn't needed since each plane's register are neatly
contained on their own cachelines.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 45 -
1 file changed, 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 7ffca5669ab9..0376fc48c011 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -429,9 +429,6 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
int crtc_y = plane_state->uapi.dst.y1;
u32 crtc_w = drm_rect_width(_state->uapi.dst);
u32 crtc_h = drm_rect_height(_state->uapi.dst);
- unsigned long irqflags;
-
- spin_lock_irqsave(_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
plane_state->view.color_plane[0].mapping_stride);
@@ -439,8 +436,6 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
SP_POS_Y(crtc_y) | SP_POS_X(crtc_x));
intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
SP_HEIGHT(crtc_h - 1) | SP_WIDTH(crtc_w - 1));
-
- spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
}
static void
@@ -456,14 +451,11 @@ vlv_sprite_update_arm(struct intel_plane *plane,
u32 x = plane_state->view.color_plane[0].x;
u32 y = plane_state->view.color_plane[0].y;
u32 sprctl, linear_offset;
- unsigned long irqflags;
sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state);
linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
- spin_lock_irqsave(_priv->uncore.lock, irqflags);
-
if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
chv_sprite_update_csc(plane_state);
@@ -493,8 +485,6 @@ vlv_sprite_update_arm(struct intel_plane *plane,
vlv_sprite_update_clrc(plane_state);
vlv_sprite_update_gamma(plane_state);
-
- spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
}
static void
@@ -504,14 +494,9 @@ vlv_sprite_disable_arm(struct intel_plane *plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
enum plane_id plane_id = plane->id;
- unsigned long irqflags;
-
- spin_lock_irqsave(_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), 0);
intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), 0);
-
- spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
}
static bool
@@ -861,15 +846,12 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
u32 src_w = drm_rect_width(_state->uapi.src) >> 16;
u32 src_h = drm_rect_height(_state->uapi.src) >> 16;
u32 sprscale = 0;
- unsigned long irqflags;
if (crtc_w != src_w || crtc_h != src_h)
sprscale = SPRITE_SCALE_ENABLE |
SPRITE_SRC_WIDTH(src_w - 1) |
SPRITE_SRC_HEIGHT(src_h - 1);
- spin_lock_irqsave(_priv->uncore.lock, irqflags);
-
intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
plane_state->view.color_plane[0].mapping_stride);
intel_de_write_fw(dev_priv, SPRPOS(pipe),
@@ -878,8 +860,6 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
SPRITE_HEIGHT(crtc_h - 1) | SPRITE_WIDTH(crtc_w - 1));
if (IS_IVYBRIDGE(dev_priv))
intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
-
- spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
}
static void
@@ -894,14 +874,11 @@ ivb_sprite_update_arm(struct intel_plane *plane,
u32 x = plane_state->view.color_plane[0].x;
u32 y = plane_state->view.color_plane[0].y;
u32 sprctl, linear_offset;
- unsigned long irqflags;
sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state);
linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
- spin_lock_irqsave(_priv->uncore.lock, irqflags);
-
if (key->flags) {
intel_de_write_fw(dev_priv, SPRKEYVAL(pipe), key->min_value);
intel_de_write_fw(dev_priv, SPRKEYMSK(pipe),
@@ -930,8 +907,6 @@ ivb_sprite_update_arm(struct intel_plane *plane,
intel_plane_ggtt_offset(plane_state) +
sprsurf_offset);
ivb_sprite_update_gamma(plane_state);
-
- spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
}
static void
@@ -940,17 +915,12 @@ ivb_sprite_disable_arm(struct intel_plane *plane,
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
- unsigned long irqflags;
-
- spin_lock_irqsave(_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, SPRCTL(pipe), 0);
/* Disable the scaler */
if
[Intel-gfx] [PATCH 4/6] drm/i915: Make cursor plane registers unlocked
From: Ville Syrjälä
Drop the locks around cursor plane register writes. The
lock isn't needed since each plane's register are neatly
contained on their own cachelines.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cursor.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index 2ade8fdd9bdd..625c1fb68273 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -255,7 +255,6 @@ static void i845_cursor_update_arm(struct intel_plane
*plane,
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
u32 cntl = 0, base = 0, pos = 0, size = 0;
- unsigned long irqflags;
if (plane_state && plane_state->uapi.visible) {
unsigned int width = drm_rect_width(_state->uapi.dst);
@@ -270,8 +269,6 @@ static void i845_cursor_update_arm(struct intel_plane
*plane,
pos = intel_cursor_position(plane_state);
}
- spin_lock_irqsave(_priv->uncore.lock, irqflags);
-
/* On these chipsets we can only modify the base/size/stride
* whilst the cursor is disabled.
*/
@@ -290,8 +287,6 @@ static void i845_cursor_update_arm(struct intel_plane
*plane,
} else {
intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
}
-
- spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
}
static void i845_cursor_disable_arm(struct intel_plane *plane,
@@ -492,7 +487,6 @@ static void i9xx_cursor_update_arm(struct intel_plane
*plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
- unsigned long irqflags;
if (plane_state && plane_state->uapi.visible) {
int width = drm_rect_width(_state->uapi.dst);
@@ -508,8 +502,6 @@ static void i9xx_cursor_update_arm(struct intel_plane
*plane,
pos = intel_cursor_position(plane_state);
}
- spin_lock_irqsave(_priv->uncore.lock, irqflags);
-
/*
* On some platforms writing CURCNTR first will also
* cause CURPOS to be armed by the CURBASE write.
@@ -555,8 +547,6 @@ static void i9xx_cursor_update_arm(struct intel_plane
*plane,
intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
intel_de_write_fw(dev_priv, CURBASE(pipe), base);
}
-
- spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
}
static void i9xx_cursor_disable_arm(struct intel_plane *plane,
--
2.32.0
[Intel-gfx] [PATCH 5/6] drm/i915: Make most pre-skl primary plane registers unlocked
From: Ville Syrjälä
Drop the locks around most primary plane register writes.
The lock isn't needed since each plane's register are neatly
contained on their own cachelines.
The one exception we have to make is DSPADDR/DSPSURF which is
(ab)used to also trigger FBC nukes on pre-snb (since the
hardware doesn't seem to have any dedicated mechanism to
trigger nukes). So we need to keep the lock around it to
protect against the rmw performed by the fbc code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 24 +--
1 file changed, 9 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 54f8776ca6b3..bab1027a11f3 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -418,9 +418,6 @@ static void i9xx_plane_update_noarm(struct intel_plane
*plane,
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
- unsigned long irqflags;
-
- spin_lock_irqsave(_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
plane_state->view.color_plane[0].mapping_stride);
@@ -441,8 +438,6 @@ static void i9xx_plane_update_noarm(struct intel_plane
*plane,
intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w -
1));
}
-
- spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
}
static void i9xx_plane_update_arm(struct intel_plane *plane,
@@ -465,8 +460,6 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
else
dspaddr_offset = linear_offset;
- spin_lock_irqsave(_priv->uncore.lock, irqflags);
-
if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
@@ -496,13 +489,15 @@ static void i9xx_plane_update_arm(struct intel_plane
*plane,
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
+
+ /* lock to protect against rmw in fbc nuke */
+ spin_lock_irqsave(_priv->uncore.lock, irqflags);
if (DISPLAY_VER(dev_priv) >= 4)
intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
intel_plane_ggtt_offset(plane_state) +
dspaddr_offset);
else
intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
intel_plane_ggtt_offset(plane_state) +
dspaddr_offset);
-
spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
}
@@ -540,14 +535,14 @@ static void i9xx_plane_disable_arm(struct intel_plane
*plane,
*/
dspcntr = i9xx_plane_ctl_crtc(crtc_state);
- spin_lock_irqsave(_priv->uncore.lock, irqflags);
-
intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
+
+ /* lock to protect against rmw in fbc nuke */
+ spin_lock_irqsave(_priv->uncore.lock, irqflags);
if (DISPLAY_VER(dev_priv) >= 4)
intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
else
intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0);
-
spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
}
@@ -566,8 +561,10 @@ g4x_primary_async_flip(struct intel_plane *plane,
if (async_flip)
dspcntr |= DISP_ASYNC_FLIP;
- spin_lock_irqsave(_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
+
+ /* lock to protect against rmw in fbc nuke */
+ spin_lock_irqsave(_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
intel_plane_ggtt_offset(plane_state) +
dspaddr_offset);
spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
@@ -582,12 +579,9 @@ vlv_primary_async_flip(struct intel_plane *plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
u32 dspaddr_offset = plane_state->view.color_plane[0].offset;
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
- unsigned long irqflags;
- spin_lock_irqsave(_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, DSPADDR_VLV(i9xx_plane),
intel_plane_ggtt_offset(plane_state) +
dspaddr_offset);
- spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
}
static void
--
2.32.0
[Intel-gfx] [PATCH 3/6] drm/i915: Make skl+ universal plane registers unlocked
From: Ville Syrjälä
Drop the locks around most universal plane register writes.
The lock isn't needed since each plane's register are neatly
contained on their own cachelines.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/skl_universal_plane.c| 35 ---
1 file changed, 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 07c64ea5b362..c2596b6aa3ab 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -615,16 +615,11 @@ skl_plane_disable_arm(struct intel_plane *plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
- unsigned long irqflags;
-
- spin_lock_irqsave(_priv->uncore.lock, irqflags);
skl_write_plane_wm(plane, crtc_state);
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
-
- spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
}
static void
@@ -634,9 +629,6 @@ icl_plane_disable_arm(struct intel_plane *plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
- unsigned long irqflags;
-
- spin_lock_irqsave(_priv->uncore.lock, irqflags);
if (icl_is_hdr_plane(dev_priv, plane_id))
intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0);
@@ -646,8 +638,6 @@ icl_plane_disable_arm(struct intel_plane *plane,
intel_psr2_disable_plane_sel_fetch(plane, crtc_state);
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
-
- spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
}
static bool
@@ -1105,7 +1095,6 @@ skl_plane_update_noarm(struct intel_plane *plane,
int crtc_y = plane_state->uapi.dst.y1;
u32 src_w = drm_rect_width(_state->uapi.src) >> 16;
u32 src_h = drm_rect_height(_state->uapi.src) >> 16;
- unsigned long irqflags;
/* The scaler will handle the output position */
if (plane_state->scaler_id >= 0) {
@@ -1113,8 +1102,6 @@ skl_plane_update_noarm(struct intel_plane *plane,
crtc_y = 0;
}
- spin_lock_irqsave(_priv->uncore.lock, irqflags);
-
intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
PLANE_STRIDE_(stride));
intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
@@ -1123,8 +1110,6 @@ skl_plane_update_noarm(struct intel_plane *plane,
PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
skl_write_plane_wm(plane, crtc_state);
-
- spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
}
static void
@@ -1138,7 +1123,6 @@ skl_plane_update_arm(struct intel_plane *plane,
u32 x = plane_state->view.color_plane[0].x;
u32 y = plane_state->view.color_plane[0].y;
u32 plane_ctl, plane_color_ctl = 0;
- unsigned long irqflags;
plane_ctl = plane_state->ctl |
skl_plane_ctl_crtc(crtc_state);
@@ -1147,8 +1131,6 @@ skl_plane_update_arm(struct intel_plane *plane,
plane_color_ctl = plane_state->color_ctl |
glk_plane_color_ctl_crtc(crtc_state);
- spin_lock_irqsave(_priv->uncore.lock, irqflags);
-
intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
skl_plane_keyval(plane_state));
intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id),
skl_plane_keymsk(plane_state));
intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id),
skl_plane_keymax(plane_state));
@@ -1184,8 +1166,6 @@ skl_plane_update_arm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
skl_plane_surf(plane_state, 0));
-
- spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
}
static void
@@ -1206,7 +1186,6 @@ icl_plane_update_noarm(struct intel_plane *plane,
int src_w = drm_rect_width(_state->uapi.src) >> 16;
int src_h = drm_rect_height(_state->uapi.src) >> 16;
u32 plane_color_ctl;
- unsigned long irqflags;
plane_color_ctl = plane_state->color_ctl |
glk_plane_color_ctl_crtc(crtc_state);
@@ -1217,8 +1196,6 @@ icl_plane_update_noarm(struct intel_plane *plane,
crtc_y = 0;
}
- spin_lock_irqsave(_priv->uncore.lock, irqflags);
-
intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
PLANE_STRIDE_(stride));
intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
@@ -1262,8 +1239,6 @@ icl_plane_update_noarm(struct intel_plane *plane,
[Intel-gfx] [PATCH 2/6] drm/i915: Optimize icl+ universal plane programming
From: Ville Syrjälä
On icl+ all plane registers are armed by PLANE_SURF, so we can
move almost everything over into the update_noarm() hook.
The PLANE_CTL write has to stay in the icl_update_arm() hook though
as it still exhibits the somewhat annoying self-arming behaviour
when the plane transitioning from disabled to enabled.
We could either do a full split for skl+ vs. icl+, or we could try
some other kind of split where we'd eg. keep most things in the skl+
functions and call them from the icl+ functions. I think a full split
is probably the cleaner approach since we've anyway accumulated quite
a bit of icl+ specific things, so that is what I opted to do.
Some i915_update_info stats for tgl:
before: after:
Updates: 5043 Updates: 5043
| |
1us | 1us |
|** |***
4us |** 4us |
|** |***
16us |*** 16us |**
| |*
66us | 66us |
| |
262us | 262us |
| |
1ms | 1ms |
| |
4ms | 4ms |
| |
17ms | 17ms |
| |
Min update: 3494ns Min update: 2983ns
Max update: 49491ns Max update: 39986ns
Average update: 18031ns Average update: 13423ns
Overruns > 100us: 0 Overruns > 100us: 0
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/skl_universal_plane.c| 195 ++
1 file changed, 155 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 72dcc341bb1f..07c64ea5b362 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -619,6 +619,25 @@ skl_plane_disable_arm(struct intel_plane *plane,
spin_lock_irqsave(_priv->uncore.lock, irqflags);
+ skl_write_plane_wm(plane, crtc_state);
+
+ intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
+
+ spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
+}
+
+static void
+icl_plane_disable_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ enum plane_id plane_id = plane->id;
+ enum pipe pipe = plane->pipe;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(_priv->uncore.lock, irqflags);
+
if (icl_is_hdr_plane(dev_priv, plane_id))
intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0);
@@ -1064,7 +1083,7 @@ static void icl_plane_csc_load_black(struct intel_plane
*plane)
intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0);
}
-static int skl_plane_color_plane(const struct intel_plane_state *plane_state)
+static int icl_plane_color_plane(const struct intel_plane_state *plane_state)
{
/* Program the UV plane on planar master */
if (plane_state->planar_linked_plane && !plane_state->planar_slave)
@@ -1081,9 +1100,7 @@ skl_plane_update_noarm(struct intel_plane *plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
- int color_plane = skl_plane_color_plane(plane_state);
- u32 stride = skl_plane_stride(plane_state, color_plane);
- const struct drm_framebuffer *fb = plane_state->hw.fb;
+ u32 stride = skl_plane_stride(plane_state, 0);
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
u32 src_w = drm_rect_width(_state->uapi.src) >> 16;
@@ -1098,12 +1115,109 @@ skl_plane_update_noarm(struct intel_plane *plane,
spin_lock_irqsave(_priv->uncore.lock, irqflags);
+ intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
+ PLANE_STRIDE_(stride));
+ intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
+ PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x));
+ intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
+ PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
+
+ skl_write_plane_wm(plane, crtc_state);
+
+ spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
+}
+
+static void
+skl_plane_update_arm(struct intel_plane *plane,
+const struct intel_crtc_state *crtc_state,
[Intel-gfx] [PATCH 1/6] drm/i915: Clean up pre-skl primary plane registers
From: Ville Syrjälä
Use REG_BIT() & co. for the pre-skl primary plane registers.
Also give everything a consistent namespace.
v2: s/DSP/DISP/ to avoid confusion (José)
Use DISP_WIDTH rather than DISP_POS_X for DSPSIZE (José)
Deal with gvt
Cc: José Roberto de Souza
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c| 99 +
drivers/gpu/drm/i915/display/intel_display.c | 13 +--
drivers/gpu/drm/i915/gvt/display.c | 4 +-
drivers/gpu/drm/i915/gvt/fb_decoder.c| 18 ++--
drivers/gpu/drm/i915/i915_reg.h | 108 +++
drivers/gpu/drm/i915/intel_pm.c | 2 +-
6 files changed, 128 insertions(+), 116 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index fc6f05146a9f..54f8776ca6b3 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -155,51 +155,51 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
*crtc_state,
unsigned int rotation = plane_state->hw.rotation;
u32 dspcntr;
- dspcntr = DISPLAY_PLANE_ENABLE;
+ dspcntr = DISP_ENABLE;
if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) ||
IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
- dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
+ dspcntr |= DISP_TRICKLE_FEED_DISABLE;
switch (fb->format->format) {
case DRM_FORMAT_C8:
- dspcntr |= DISPPLANE_8BPP;
+ dspcntr |= DISP_FORMAT_8BPP;
break;
case DRM_FORMAT_XRGB1555:
- dspcntr |= DISPPLANE_BGRX555;
+ dspcntr |= DISP_FORMAT_BGRX555;
break;
case DRM_FORMAT_ARGB1555:
- dspcntr |= DISPPLANE_BGRA555;
+ dspcntr |= DISP_FORMAT_BGRA555;
break;
case DRM_FORMAT_RGB565:
- dspcntr |= DISPPLANE_BGRX565;
+ dspcntr |= DISP_FORMAT_BGRX565;
break;
case DRM_FORMAT_XRGB:
- dspcntr |= DISPPLANE_BGRX888;
+ dspcntr |= DISP_FORMAT_BGRX888;
break;
case DRM_FORMAT_XBGR:
- dspcntr |= DISPPLANE_RGBX888;
+ dspcntr |= DISP_FORMAT_RGBX888;
break;
case DRM_FORMAT_ARGB:
- dspcntr |= DISPPLANE_BGRA888;
+ dspcntr |= DISP_FORMAT_BGRA888;
break;
case DRM_FORMAT_ABGR:
- dspcntr |= DISPPLANE_RGBA888;
+ dspcntr |= DISP_FORMAT_RGBA888;
break;
case DRM_FORMAT_XRGB2101010:
- dspcntr |= DISPPLANE_BGRX101010;
+ dspcntr |= DISP_FORMAT_BGRX101010;
break;
case DRM_FORMAT_XBGR2101010:
- dspcntr |= DISPPLANE_RGBX101010;
+ dspcntr |= DISP_FORMAT_RGBX101010;
break;
case DRM_FORMAT_ARGB2101010:
- dspcntr |= DISPPLANE_BGRA101010;
+ dspcntr |= DISP_FORMAT_BGRA101010;
break;
case DRM_FORMAT_ABGR2101010:
- dspcntr |= DISPPLANE_RGBA101010;
+ dspcntr |= DISP_FORMAT_RGBA101010;
break;
case DRM_FORMAT_XBGR16161616F:
- dspcntr |= DISPPLANE_RGBX161616;
+ dspcntr |= DISP_FORMAT_RGBX161616;
break;
default:
MISSING_CASE(fb->format->format);
@@ -208,13 +208,13 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
*crtc_state,
if (DISPLAY_VER(dev_priv) >= 4 &&
fb->modifier == I915_FORMAT_MOD_X_TILED)
- dspcntr |= DISPPLANE_TILED;
+ dspcntr |= DISP_TILED;
if (rotation & DRM_MODE_ROTATE_180)
- dspcntr |= DISPPLANE_ROTATE_180;
+ dspcntr |= DISP_ROTATE_180;
if (rotation & DRM_MODE_REFLECT_X)
- dspcntr |= DISPPLANE_MIRROR;
+ dspcntr |= DISP_MIRROR;
return dspcntr;
}
@@ -354,13 +354,13 @@ static u32 i9xx_plane_ctl_crtc(const struct
intel_crtc_state *crtc_state)
u32 dspcntr = 0;
if (crtc_state->gamma_enable)
- dspcntr |= DISPPLANE_GAMMA_ENABLE;
+ dspcntr |= DISP_PIPE_GAMMA_ENABLE;
if (crtc_state->csc_enable)
- dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
+ dspcntr |= DISP_PIPE_CSC_ENABLE;
if (DISPLAY_VER(dev_priv) < 5)
- dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
+ dspcntr |= DISP_PIPE_SEL(crtc->pipe);
return dspcntr;
}
@@ -437,9 +437,9 @@ static void i9xx_plane_update_noarm(struct intel_plane
*plane,
* program whatever is there.
*/
intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
- (crtc_y << 16) | crtc_x);
+
[Intel-gfx] [PATCH 0/6] drm/i915: Futher optimize plane updates
From: Ville Syrjälä Optimize icl+ plane updates by moving most register writes into the .update_noarm() hook. Also stop taking uncore.lock for plane register writes as well Ville Syrjälä (6): drm/i915: Clean up pre-skl primary plane registers drm/i915: Optimize icl+ universal plane programming drm/i915: Make skl+ universal plane registers unlocked drm/i915: Make cursor plane registers unlocked drm/i915: Make most pre-skl primary plane registers unlocked drm/i915: Make pre-skl sprite plane registers unlocked drivers/gpu/drm/i915/display/i9xx_plane.c | 123 ++- drivers/gpu/drm/i915/display/intel_cursor.c | 10 - drivers/gpu/drm/i915/display/intel_display.c | 13 +- drivers/gpu/drm/i915/display/intel_sprite.c | 45 .../drm/i915/display/skl_universal_plane.c| 196 -- drivers/gpu/drm/i915/gvt/display.c| 4 +- drivers/gpu/drm/i915/gvt/fb_decoder.c | 18 +- drivers/gpu/drm/i915/i915_reg.h | 108 ++ drivers/gpu/drm/i915/intel_pm.c | 2 +- 9 files changed, 275 insertions(+), 244 deletions(-) -- 2.32.0
Re: [Intel-gfx] [PATCH RESEND 7/7] drm/i915/mst: only ack the ESI we actually handled
On Thu, 20 Jan 2022, "Shankar, Uma" wrote:
>> -Original Message-
>> From: Nikula, Jani
>> Sent: Thursday, January 20, 2022 4:32 PM
>> To: Shankar, Uma ; intel-gfx@lists.freedesktop.org
>> Subject: Re: [Intel-gfx] [PATCH RESEND 7/7] drm/i915/mst: only ack the ESI we
>> actually handled
>>
>> On Thu, 20 Jan 2022, "Shankar, Uma" wrote:
>> >> -Original Message-
>> >> From: Intel-gfx On Behalf
>> >> Of Jani Nikula
>> >> Sent: Wednesday, January 12, 2022 4:33 PM
>> >> To: intel-gfx@lists.freedesktop.org
>> >> Cc: Nikula, Jani
>> >> Subject: [Intel-gfx] [PATCH RESEND 7/7] drm/i915/mst: only ack the
>> >> ESI we actually handled
>> >>
>> >> Seems odd that we clear all event status indicators if we've only
>> >> handled some. Only clear the ones we've handled.
>> >
>> > Looks Good to me.
>> > Reviewed-by: Uma Shankar
>>
>> Thanks, please also see v2 of this patch I accidentally posted to the old
>> thread first. I
>> guess you were replying to two threads too. :)
>
> Yeah seems reply got mixed up. I have replied on correct versions now.
Many thanks for the reviews, pushed to drm-intel-next.
BR,
Jani.
>
> Regards,
> Uma Shankar
>
>> BR,
>> Jani
>>
>> >
>> >> Signed-off-by: Jani Nikula
>> >> ---
>> >> drivers/gpu/drm/i915/display/intel_dp.c | 20
>> >> 1 file changed, 12 insertions(+), 8 deletions(-)
>> >>
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> >> b/drivers/gpu/drm/i915/display/intel_dp.c
>> >> index 95e9f7220ab8..548419a4ead8 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> >> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> >> @@ -3625,13 +3625,17 @@ static void
>> >> intel_dp_handle_test_request(struct
>> >> intel_dp *intel_dp) }
>> >>
>> >> static void
>> >> -intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, bool
>> >> *handled)
>> >> +intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
>> >> {
>> >> - drm_dp_mst_hpd_irq(_dp->mst_mgr, esi, handled);
>> >> + bool handled = false;
>> >> +
>> >> + drm_dp_mst_hpd_irq(_dp->mst_mgr, esi, );
>> >> + if (handled)
>> >> + ack[1] |= DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY;
>> >>
>> >> if (esi[1] & DP_CP_IRQ) {
>> >> intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
>> >> - *handled = true;
>> >> + ack[1] |= DP_CP_IRQ;
>> >> }
>> >> }
>> >>
>> >> @@ -3683,7 +3687,7 @@ intel_dp_check_mst_status(struct intel_dp
>> >> *intel_dp)
>> >>
>> >> for (;;) {
>> >> u8 esi[4] = {};
>> >> - bool handled;
>> >> + u8 ack[4] = {};
>> >>
>> >> if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
>> >> drm_dbg_kms(>drm,
>> >> @@ -3699,15 +3703,15 @@ intel_dp_check_mst_status(struct intel_dp
>> *intel_dp)
>> >> esi[3] & LINK_STATUS_CHANGED) {
>> >> if (!intel_dp_mst_link_status(intel_dp))
>> >> link_ok = false;
>> >> - handled = true;
>> >> + ack[3] |= LINK_STATUS_CHANGED;
>> >> }
>> >>
>> >> - intel_dp_mst_hpd_irq(intel_dp, esi, );
>> >> + intel_dp_mst_hpd_irq(intel_dp, esi, ack);
>> >>
>> >> - if (!handled)
>> >> + if (!memchr_inv(ack, 0, sizeof(ack)))
>> >> break;
>> >>
>> >> - if (!intel_dp_ack_sink_irq_esi(intel_dp, esi))
>> >> + if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
>> >> drm_dbg_kms(>drm, "Failed to ack ESI\n");
>> >> }
>> >>
>> >> --
>> >> 2.30.2
>> >
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Async flip optimization for DG2 (rev4)
== Series Details == Series: Async flip optimization for DG2 (rev4) URL : https://patchwork.freedesktop.org/series/98981/ State : warning == Summary == $ dim checkpatch origin/drm-tip a21feb89e84d drm/i915: Pass plane to watermark calculation functions 3328aa934fa7 drm/i915: Introduce do_async_flip flag to intel_plane_state 8a01e4903796 drm/i915: Use wm0 only during async flips for DG2 -:9: WARNING:TYPO_SPELLING: 'perfomance' may be misspelled - perhaps 'performance'? #9: This optimization allows to achieve higher perfomance ^^ total: 0 errors, 1 warnings, 0 checks, 60 lines checked 57d60bca103b drm/i915: Don't allocate extra ddb during async flip for DG2
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dg2: Add Wa_18018781329 (rev2)
== Series Details ==
Series: drm/i915/dg2: Add Wa_18018781329 (rev2)
URL : https://patchwork.freedesktop.org/series/99128/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7 -> Patchwork_22053
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22053 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22053, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22053/index.html
Participating hosts (46 -> 36)
--
Additional (1): fi-pnv-d510
Missing(11): fi-jsl-1 fi-ilk-m540 bat-dg1-6 fi-hsw-4200u fi-bsw-cyan
bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-bdw-samus bat-jsl-2 bat-jsl-1
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22053:
### IGT changes ###
Possible regressions
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-hsw-4770:[PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/fi-hsw-4770/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22053/fi-hsw-4770/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@dmabuf:
- {fi-tgl-dsi}: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/fi-tgl-dsi/igt@i915_selftest@l...@dmabuf.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22053/fi-tgl-dsi/igt@i915_selftest@l...@dmabuf.html
Known issues
Here are the changes found in Patchwork_22053 that come from known issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@read_all_entries:
- fi-kbl-soraka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982] /
[i915#262])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22053/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html
* igt@gem_huc_copy@huc-copy:
- fi-skl-6600u: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22053/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22053/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html
* igt@i915_selftest@live:
- fi-skl-6600u: NOTRUN -> [FAIL][9] ([i915#4547])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22053/fi-skl-6600u/igt@i915_selft...@live.html
* igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22053/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u: NOTRUN -> [SKIP][11] ([fdo#109271]) +3 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22053/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22053/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510:NOTRUN -> [SKIP][13] ([fdo#109271]) +57 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22053/fi-pnv-d510/igt@prime_v...@basic-userptr.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][14] ([i915#2426] / [i915#4312])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22053/fi-bdw-5557u/igt@run...@aborted.html
Possible fixes
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: [FAIL][15] ([i915#4547]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22053/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][17] ([i915#4269]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[18]:
Re: [Intel-gfx] linux-next: build warning after merge of the drm-misc tree
Hi Stepen,
On 1/20/22 04:18, Stephen Rothwell wrote:
> Hi all,
>
> On Fri, 15 Oct 2021 20:54:22 +1100 Stephen Rothwell
> wrote:
>>
>> After merging the drm-misc tree, today's linux-next build (htmldocs)
>> produced this warning:
>>
>> Documentation/gpu/drm-kms-helpers:451:
>> /home/sfr/next/next/drivers/gpu/drm/drm_privacy_screen.c:270: WARNING:
>> Inline emphasis start-string without end-string.
>>
>> Introduced by commit
>>
>> 8a12b170558a ("drm/privacy-screen: Add notifier support (v2)")
>
> I am still getting this warning.
Sorry I completely missed your original report on this between
all the other kernel related emails.
I'll prepare a fix for this coming Monday.
Regards,
Hans
