[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for reference
== Series Details == Series: series starting with [1/2] drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for reference URL : https://patchwork.freedesktop.org/series/99301/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11129_full -> Patchwork_22093_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22093_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22093_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 10) -- Missing(1): shard-tglu Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22093_full: ### IGT changes ### Possible regressions * igt@gem_create@create-massive: - shard-kbl: NOTRUN -> [DMESG-WARN][1] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22093/shard-kbl3/igt@gem_cre...@create-massive.html * igt@gem_userptr_blits@input-checking: - shard-skl: NOTRUN -> [DMESG-WARN][2] +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22093/shard-skl10/igt@gem_userptr_bl...@input-checking.html - shard-apl: NOTRUN -> [DMESG-WARN][3] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22093/shard-apl7/igt@gem_userptr_bl...@input-checking.html * igt@kms_flip@flip-vs-fences-interruptible@a-vga1: - shard-snb: [PASS][4] -> [INCOMPLETE][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-snb6/igt@kms_flip@flip-vs-fences-interrupti...@a-vga1.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22093/shard-snb6/igt@kms_flip@flip-vs-fences-interrupti...@a-vga1.html Known issues Here are the changes found in Patchwork_22093_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@parallel-balancer: - shard-iclb: [PASS][6] -> [SKIP][7] ([i915#4525]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb2/igt@gem_exec_balan...@parallel-balancer.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22093/shard-iclb7/igt@gem_exec_balan...@parallel-balancer.html * igt@gem_exec_fair@basic-deadline: - shard-skl: NOTRUN -> [FAIL][8] ([i915#2846]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22093/shard-skl6/igt@gem_exec_f...@basic-deadline.html - shard-glk: [PASS][9] -> [FAIL][10] ([i915#2846]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-glk9/igt@gem_exec_f...@basic-deadline.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22093/shard-glk1/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-skl: NOTRUN -> [SKIP][11] ([fdo#109271]) +179 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22093/shard-skl10/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-glk: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-glk8/igt@gem_exec_fair@basic-none-sh...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22093/shard-glk5/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-tglb: NOTRUN -> [FAIL][14] ([i915#2842]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22093/shard-tglb3/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [PASS][15] -> [FAIL][16] ([i915#2842]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-kbl3/igt@gem_exec_fair@basic-n...@vcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22093/shard-kbl4/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][17] ([i915#2842]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22093/shard-iclb4/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-tglb: [PASS][18] -> [FAIL][19] ([i915#2842]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-tglb2/igt@gem_exec_fair@basic-pace-s...@rcs0.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22093/shard-tglb2/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613]) +2 similar issues [20]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for Fix up request cancel (rev3)
== Series Details == Series: Fix up request cancel (rev3) URL : https://patchwork.freedesktop.org/series/99173/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11130 -> Patchwork_22095 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22095 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22095, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/index.html Participating hosts (39 -> 42) -- Additional (7): fi-kbl-soraka bat-dg1-6 bat-dg1-5 bat-adlp-4 bat-rpls-1 bat-jsl-2 bat-jsl-1 Missing(4): fi-ctg-p8600 fi-bsw-cyan fi-hsw-4200u fi-pnv-d510 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22095: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gtt: - fi-bdw-5557u: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11130/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html * igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling: - bat-adlp-4: NOTRUN -> [DMESG-WARN][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-adlp-4/igt@kms_addfb_ba...@addfb25-framebuffer-vs-set-tiling.html Known issues Here are the changes found in Patchwork_22095 that come from known issues: ### IGT changes ### Issues hit * igt@fbdev@info: - bat-dg1-6: NOTRUN -> [SKIP][4] ([i915#2582]) +4 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-dg1-6/igt@fb...@info.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_exec_gttfill@basic: - bat-dg1-6: NOTRUN -> [SKIP][6] ([i915#4086]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-dg1-6/igt@gem_exec_gttf...@basic.html - bat-dg1-5: NOTRUN -> [SKIP][7] ([i915#4086]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-dg1-5/igt@gem_exec_gttf...@basic.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - bat-adlp-4: NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-adlp-4/igt@gem_lmem_swapp...@basic.html - fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +3 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@gem_mmap@basic: - bat-dg1-6: NOTRUN -> [SKIP][11] ([i915#4083]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-dg1-6/igt@gem_m...@basic.html - bat-dg1-5: NOTRUN -> [SKIP][12] ([i915#4083]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-dg1-5/igt@gem_m...@basic.html * igt@gem_tiled_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][13] ([i915#4077]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-dg1-6/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-5: NOTRUN -> [SKIP][14] ([i915#4077]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-dg1-5/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-dg1-5: NOTRUN -> [SKIP][15] ([i915#4079]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-dg1-5/igt@gem_tiled_pread_basic.html - bat-adlp-4: NOTRUN -> [SKIP][16] ([i915#3282]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-adlp-4/igt@gem_tiled_pread_basic.html - bat-dg1-6: NOTRUN -> [SKIP][17] ([i915#4079]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-dg1-6/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg1-5: NOTRUN -> [SKIP][18] ([i915#1155]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22095/bat-dg1-5/igt@i915_pm_backli...@basic-brightness.html - bat-dg1-6: NOTRUN -> [SKIP][19] ([i915#1155]) [19]:
Re: [Intel-gfx] [PATCH v2 5/5] drm/i915: Move dsc/joiner enable into hsw_crtc_enable()
On Tue, Jan 25, 2022 at 08:50:47AM +0200, Jani Nikula wrote:
> On Tue, 25 Jan 2022, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Lift the dsc/joiner enable up from the wonky places where it
> > currently sits (ddi .pre_enable() or icl_ddi_bigjoiner_pre_enable())
> > into hsw_crtc_enable() where we write the other per-pipe stuff
> > as well. Makes the transcoder vs. pipe split less confusing.
> >
> > For DSI this results in slight reordering between the dsc/joiner
> > enable vs. transcoder timings setup, but I can't really think
> > why that should cause any issues since the transcoder isn't yet
> > enabled at that point.
> >
> > v2: Take care of dsi (Jani)
> >
> > Cc: Jani Nikula
> > Signed-off-by: Ville Syrjälä
>
> Reviewed-by: Jani Nikula
>
> One question inline.
>
> > ---
> > drivers/gpu/drm/i915/display/icl_dsi.c | 2 --
> > drivers/gpu/drm/i915/display/intel_ddi.c | 6 --
> > drivers/gpu/drm/i915/display/intel_display.c | 12 +---
> > 3 files changed, 5 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index 95f49535fa6e..16a611f7d659 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -1233,8 +1233,6 @@ static void gen11_dsi_pre_enable(struct
> > intel_atomic_state *state,
> >
> > intel_dsc_dsi_pps_write(encoder, pipe_config);
> >
> > - intel_dsc_enable(pipe_config);
> > -
> > /* step6c: configure transcoder timings */
> > gen11_dsi_set_transcoder_timings(encoder, pipe_config);
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 2f20abc5122d..5d1f7d6218c5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -2425,9 +2425,6 @@ static void tgl_ddi_pre_enable_dp(struct
> > intel_atomic_state *state,
> > intel_ddi_enable_fec(encoder, crtc_state);
> >
> > intel_dsc_dp_pps_write(encoder, crtc_state);
> > -
> > - if (!crtc_state->bigjoiner)
> > - intel_dsc_enable(crtc_state);
> > }
> >
> > static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
> > @@ -2493,9 +2490,6 @@ static void hsw_ddi_pre_enable_dp(struct
> > intel_atomic_state *state,
> > intel_ddi_enable_pipe_clock(encoder, crtc_state);
> >
> > intel_dsc_dp_pps_write(encoder, crtc_state);
> > -
> > - if (!crtc_state->bigjoiner)
> > - intel_dsc_enable(crtc_state);
> > }
> >
> > static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index d2906434ab3f..13b1de03640d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1974,7 +1974,6 @@ static void hsw_set_frame_start_delay(const struct
> > intel_crtc_state *crtc_state)
> > static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
> > const struct intel_crtc_state
> > *crtc_state)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > struct intel_crtc_state *master_crtc_state;
> > struct intel_crtc *master_crtc;
> > struct drm_connector_state *conn_state;
> > @@ -2004,12 +2003,6 @@ static void icl_ddi_bigjoiner_pre_enable(struct
> > intel_atomic_state *state,
> >
> > if (crtc_state->bigjoiner_slave)
> > intel_encoders_pre_enable(state, master_crtc);
> > -
> > - /* need to enable VDSC, which we skipped in pre-enable */
> > - intel_dsc_enable(crtc_state);
> > -
> > - if (DISPLAY_VER(dev_priv) >= 13)
> > - intel_uncompressed_joiner_enable(crtc_state);
> > }
> >
> > static void hsw_configure_cpu_transcoder(const struct intel_crtc_state
> > *crtc_state)
> > @@ -2057,6 +2050,11 @@ static void hsw_crtc_enable(struct
> > intel_atomic_state *state,
> > icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
> > }
> >
> > + intel_dsc_enable(new_crtc_state);
> > +
> > + if (DISPLAY_VER(dev_priv) >= 13)
> > + intel_uncompressed_joiner_enable(new_crtc_state);
> > +
>
> Should this call be moved inside intel_dsc_enable()? I mean it's not
> compression, but it's the same splitter/joiner/etc. block that handles
> all of this?
We probably want to restructure the code a bit more so that
it's not all pretending to be about dsc. Dunno if we should just have
some dss_enable() thing to configure everything about the
splitter/joiner stuff. Although maybe there are some conflicting
sequencing requirements for MSO, so maybe not all of it can go into
the same place? In which case I quess we should just have some kind
of joiner_enable() thing.
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH v2] drm/edid: Support type 7 timings
On Sun, 23 Jan 2022, Yaroslav Bolyukin wrote:
> Per VESA DisplayID Standard v2.0: Type VII Timing – Detailed Timing Data
>
> Definitions were already provided as type I, but not used
>
> Signed-off-by: Yaroslav Bolyukin
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/drm_edid.c | 12
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 12893e7be..5f2ae5bfa 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -5405,7 +5405,8 @@ u32 drm_add_display_info(struct drm_connector
> *connector, const struct edid *edi
> }
>
> static struct drm_display_mode *drm_mode_displayid_detailed(struct
> drm_device *dev,
> - struct
> displayid_detailed_timings_1 *timings)
> + struct
> displayid_detailed_timings_1 *timings,
> + bool type_7)
> {
> struct drm_display_mode *mode;
> unsigned pixel_clock = (timings->pixel_clock[0] |
> @@ -5426,7 +5427,8 @@ static struct drm_display_mode
> *drm_mode_displayid_detailed(struct drm_device *d
> if (!mode)
> return NULL;
>
> - mode->clock = pixel_clock * 10;
> + /* resolution is kHz for type VII, and 10 kHz for type I */
> + mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
> mode->hdisplay = hactive;
> mode->hsync_start = mode->hdisplay + hsync;
> mode->hsync_end = mode->hsync_start + hsync_width;
> @@ -5457,6 +5459,7 @@ static int add_displayid_detailed_1_modes(struct
> drm_connector *connector,
> int num_timings;
> struct drm_display_mode *newmode;
> int num_modes = 0;
> + bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
> /* blocks must be multiple of 20 bytes length */
> if (block->num_bytes % 20)
> return 0;
> @@ -5465,7 +5468,7 @@ static int add_displayid_detailed_1_modes(struct
> drm_connector *connector,
> for (i = 0; i < num_timings; i++) {
> struct displayid_detailed_timings_1 *timings = >timings[i];
>
> - newmode = drm_mode_displayid_detailed(connector->dev, timings);
> + newmode = drm_mode_displayid_detailed(connector->dev, timings,
> type_7);
> if (!newmode)
> continue;
>
> @@ -5484,7 +5487,8 @@ static int add_displayid_detailed_modes(struct
> drm_connector *connector,
>
> displayid_iter_edid_begin(edid, );
> displayid_iter_for_each(block, ) {
> - if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING)
> + if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
> + block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
> num_modes += add_displayid_detailed_1_modes(connector,
> block);
> }
> displayid_iter_end();
>
> base-commit: 99613159ad749543621da8238acf1a122880144e
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH v2 5/5] drm/i915: Move dsc/joiner enable into hsw_crtc_enable()
On Tue, 25 Jan 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Lift the dsc/joiner enable up from the wonky places where it
> currently sits (ddi .pre_enable() or icl_ddi_bigjoiner_pre_enable())
> into hsw_crtc_enable() where we write the other per-pipe stuff
> as well. Makes the transcoder vs. pipe split less confusing.
>
> For DSI this results in slight reordering between the dsc/joiner
> enable vs. transcoder timings setup, but I can't really think
> why that should cause any issues since the transcoder isn't yet
> enabled at that point.
>
> v2: Take care of dsi (Jani)
>
> Cc: Jani Nikula
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
One question inline.
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 2 --
> drivers/gpu/drm/i915/display/intel_ddi.c | 6 --
> drivers/gpu/drm/i915/display/intel_display.c | 12 +---
> 3 files changed, 5 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 95f49535fa6e..16a611f7d659 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1233,8 +1233,6 @@ static void gen11_dsi_pre_enable(struct
> intel_atomic_state *state,
>
> intel_dsc_dsi_pps_write(encoder, pipe_config);
>
> - intel_dsc_enable(pipe_config);
> -
> /* step6c: configure transcoder timings */
> gen11_dsi_set_transcoder_timings(encoder, pipe_config);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 2f20abc5122d..5d1f7d6218c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2425,9 +2425,6 @@ static void tgl_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
> intel_ddi_enable_fec(encoder, crtc_state);
>
> intel_dsc_dp_pps_write(encoder, crtc_state);
> -
> - if (!crtc_state->bigjoiner)
> - intel_dsc_enable(crtc_state);
> }
>
> static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
> @@ -2493,9 +2490,6 @@ static void hsw_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
> intel_ddi_enable_pipe_clock(encoder, crtc_state);
>
> intel_dsc_dp_pps_write(encoder, crtc_state);
> -
> - if (!crtc_state->bigjoiner)
> - intel_dsc_enable(crtc_state);
> }
>
> static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index d2906434ab3f..13b1de03640d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1974,7 +1974,6 @@ static void hsw_set_frame_start_delay(const struct
> intel_crtc_state *crtc_state)
> static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
>const struct intel_crtc_state
> *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc_state *master_crtc_state;
> struct intel_crtc *master_crtc;
> struct drm_connector_state *conn_state;
> @@ -2004,12 +2003,6 @@ static void icl_ddi_bigjoiner_pre_enable(struct
> intel_atomic_state *state,
>
> if (crtc_state->bigjoiner_slave)
> intel_encoders_pre_enable(state, master_crtc);
> -
> - /* need to enable VDSC, which we skipped in pre-enable */
> - intel_dsc_enable(crtc_state);
> -
> - if (DISPLAY_VER(dev_priv) >= 13)
> - intel_uncompressed_joiner_enable(crtc_state);
> }
>
> static void hsw_configure_cpu_transcoder(const struct intel_crtc_state
> *crtc_state)
> @@ -2057,6 +2050,11 @@ static void hsw_crtc_enable(struct intel_atomic_state
> *state,
> icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
> }
>
> + intel_dsc_enable(new_crtc_state);
> +
> + if (DISPLAY_VER(dev_priv) >= 13)
> + intel_uncompressed_joiner_enable(new_crtc_state);
> +
Should this call be moved inside intel_dsc_enable()? I mean it's not
compression, but it's the same splitter/joiner/etc. block that handles
all of this?
BR,
Jani.
> intel_set_pipe_src_size(new_crtc_state);
> if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> bdw_set_pipemisc(new_crtc_state);
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Fix up request cancel (rev3)
== Series Details == Series: Fix up request cancel (rev3) URL : https://patchwork.freedesktop.org/series/99173/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix up request cancel (rev3)
== Series Details == Series: Fix up request cancel (rev3) URL : https://patchwork.freedesktop.org/series/99173/ State : warning == Summary == $ dim checkpatch origin/drm-tip b01d46d0bed9 drm/i915: Add request cancel low level trace point bf264f6cff19 drm/i915/guc: Cancel requests immediately 0902137e128a drm/i915/execlists: Fix execlists request cancellation corner case -:85: CHECK:LINE_SPACING: Please don't use multiple blank lines #85: FILE: drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c:346: + + total: 0 errors, 0 warnings, 1 checks, 135 lines checked f3a864288387 drm/i915/selftests: Set preemption timeout to zero in cancel reset test
[Intel-gfx] [PATCH v2 5/5] drm/i915: Move dsc/joiner enable into hsw_crtc_enable()
From: Ville Syrjälä
Lift the dsc/joiner enable up from the wonky places where it
currently sits (ddi .pre_enable() or icl_ddi_bigjoiner_pre_enable())
into hsw_crtc_enable() where we write the other per-pipe stuff
as well. Makes the transcoder vs. pipe split less confusing.
For DSI this results in slight reordering between the dsc/joiner
enable vs. transcoder timings setup, but I can't really think
why that should cause any issues since the transcoder isn't yet
enabled at that point.
v2: Take care of dsi (Jani)
Cc: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 --
drivers/gpu/drm/i915/display/intel_ddi.c | 6 --
drivers/gpu/drm/i915/display/intel_display.c | 12 +---
3 files changed, 5 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 95f49535fa6e..16a611f7d659 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1233,8 +1233,6 @@ static void gen11_dsi_pre_enable(struct
intel_atomic_state *state,
intel_dsc_dsi_pps_write(encoder, pipe_config);
- intel_dsc_enable(pipe_config);
-
/* step6c: configure transcoder timings */
gen11_dsi_set_transcoder_timings(encoder, pipe_config);
}
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 2f20abc5122d..5d1f7d6218c5 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2425,9 +2425,6 @@ static void tgl_ddi_pre_enable_dp(struct
intel_atomic_state *state,
intel_ddi_enable_fec(encoder, crtc_state);
intel_dsc_dp_pps_write(encoder, crtc_state);
-
- if (!crtc_state->bigjoiner)
- intel_dsc_enable(crtc_state);
}
static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -2493,9 +2490,6 @@ static void hsw_ddi_pre_enable_dp(struct
intel_atomic_state *state,
intel_ddi_enable_pipe_clock(encoder, crtc_state);
intel_dsc_dp_pps_write(encoder, crtc_state);
-
- if (!crtc_state->bigjoiner)
- intel_dsc_enable(crtc_state);
}
static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d2906434ab3f..13b1de03640d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1974,7 +1974,6 @@ static void hsw_set_frame_start_delay(const struct
intel_crtc_state *crtc_state)
static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
const struct intel_crtc_state
*crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *master_crtc_state;
struct intel_crtc *master_crtc;
struct drm_connector_state *conn_state;
@@ -2004,12 +2003,6 @@ static void icl_ddi_bigjoiner_pre_enable(struct
intel_atomic_state *state,
if (crtc_state->bigjoiner_slave)
intel_encoders_pre_enable(state, master_crtc);
-
- /* need to enable VDSC, which we skipped in pre-enable */
- intel_dsc_enable(crtc_state);
-
- if (DISPLAY_VER(dev_priv) >= 13)
- intel_uncompressed_joiner_enable(crtc_state);
}
static void hsw_configure_cpu_transcoder(const struct intel_crtc_state
*crtc_state)
@@ -2057,6 +2050,11 @@ static void hsw_crtc_enable(struct intel_atomic_state
*state,
icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
}
+ intel_dsc_enable(new_crtc_state);
+
+ if (DISPLAY_VER(dev_priv) >= 13)
+ intel_uncompressed_joiner_enable(new_crtc_state);
+
intel_set_pipe_src_size(new_crtc_state);
if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
bdw_set_pipemisc(new_crtc_state);
--
2.34.1
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate
== Series Details == Series: series starting with [1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate URL : https://patchwork.freedesktop.org/series/99278/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11129_full -> Patchwork_22089_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22089_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22089_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 10) -- Missing(1): shard-tglu Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22089_full: ### IGT changes ### Possible regressions * igt@gem_create@create-massive: - shard-kbl: NOTRUN -> [DMESG-WARN][1] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-kbl1/igt@gem_cre...@create-massive.html - shard-skl: NOTRUN -> [DMESG-WARN][2] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-skl9/igt@gem_cre...@create-massive.html * igt@gem_userptr_blits@input-checking: - shard-apl: NOTRUN -> [DMESG-WARN][3] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-apl6/igt@gem_userptr_bl...@input-checking.html * igt@kms_flip@flip-vs-modeset-vs-hang@a-edp1: - shard-tglb: [PASS][4] -> [INCOMPLETE][5] +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-tglb3/igt@kms_flip@flip-vs-modeset-vs-h...@a-edp1.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-tglb7/igt@kms_flip@flip-vs-modeset-vs-h...@a-edp1.html Known issues Here are the changes found in Patchwork_22089_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-kbl: [PASS][6] -> [INCOMPLETE][7] ([i915#794]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-kbl6/igt@gem_ctx_isolation@preservation...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-kbl4/igt@gem_ctx_isolation@preservation...@rcs0.html * igt@gem_ctx_isolation@preservation-s3@vcs1: - shard-tglb: [PASS][8] -> [DMESG-WARN][9] ([i915#2411] / [i915#2867]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-tglb2/igt@gem_ctx_isolation@preservation...@vcs1.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-tglb6/igt@gem_ctx_isolation@preservation...@vcs1.html * igt@gem_ctx_persistence@many-contexts: - shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2410]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-tglb1/igt@gem_ctx_persiste...@many-contexts.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-tglb7/igt@gem_ctx_persiste...@many-contexts.html * igt@gem_exec_balancer@parallel: - shard-iclb: [PASS][12] -> [SKIP][13] ([i915#4525]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb4/igt@gem_exec_balan...@parallel.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-iclb7/igt@gem_exec_balan...@parallel.html * igt@gem_exec_capture@pi@rcs0: - shard-skl: [PASS][14] -> [INCOMPLETE][15] ([i915#4547]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-skl7/igt@gem_exec_capture@p...@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-skl10/igt@gem_exec_capture@p...@rcs0.html * igt@gem_exec_fair@basic-deadline: - shard-kbl: NOTRUN -> [FAIL][16] ([i915#2846]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-kbl1/igt@gem_exec_f...@basic-deadline.html - shard-skl: NOTRUN -> [FAIL][17] ([i915#2846]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-skl8/igt@gem_exec_f...@basic-deadline.html - shard-glk: [PASS][18] -> [FAIL][19] ([i915#2846]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-glk9/igt@gem_exec_f...@basic-deadline.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-glk7/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-glk: [PASS][20] -> [FAIL][21] ([i915#2842]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-glk8/igt@gem_exec_fair@basic-none-sh...@rcs0.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/shard-glk2/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-tglb: [PASS][22] ->
Re: [Intel-gfx] [PATCH 5/5] drm/i915: Move dsc/joiner enable into hsw_crtc_enable()
On Tue, Jan 25, 2022 at 07:40:04AM +0200, Jani Nikula wrote: > On Mon, 24 Jan 2022, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Lift the dsc/joiner enable up from the wonky places where it > > currently sits (ddi .pre_enable() or icl_ddi_bigjoiner_pre_enable()) > > into hsw_crtc_enable() where we write the other per-pipe stuff > > as well. Makes the transcoder vs. pipe split less confusing. > > > > What about the enable call in DSI? Hrm. Looks safeish to relocate as well. It will reorder things vs. the transcoder timings setup, but can't really think why that should matter I'm actually thinking of reordering these a bit for DP/DHMI as well. Would let us move the whole hsw_configure_cpu_transcoder() call into the ddi .pre_enable(). Though MST may get in the way of that plan :/ -- Ville Syrjälä Intel
Re: [Intel-gfx] [PATCH 1/2] drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for reference
On Mon, 24 Jan 2022, Umesh Nerlige Ramappa
wrote:
> All timestamps returned by GuC for GuC PMU busyness are captured from
> GUC PM TIMESTAMP. Since this timestamp does not tick when GuC goes idle,
> kmd uses RING_TIMESTAMP to measure busyness of an engine with an active
> context. In further stress testing, the MMIO read of the RING_TIMESTAMP
> is seen to cause a rare hang. Resolve the issue by using gt specific
> timestamp from PM which is in sync with the GuC PM timestamp.
>
> Fixes: 77cdd054dd2c ("drm/i915/pmu: Connect engine busyness stats from GuC to
> pmu")
> Signed-off-by: Umesh Nerlige Ramappa
> Reviewed-by: Alan Previn
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc.h| 5 ++
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 56 ++-
> drivers/gpu/drm/i915/i915_reg.h | 3 +-
> 3 files changed, 50 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index d59bbf49d1c2..697d9d66acef 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -215,6 +215,11 @@ struct intel_guc {
>* context usage for overflows.
>*/
> struct delayed_work work;
> +
> + /**
> + * @shift: Right shift value for the gpm timestamp
> + */
> + u32 shift;
> } timestamp;
>
> #ifdef CONFIG_DRM_I915_SELFTEST
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 1331ff91c5b0..66760f5df0c1 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1150,23 +1150,51 @@ static void guc_update_engine_gt_clks(struct
> intel_engine_cs *engine)
> }
> }
>
> -static void guc_update_pm_timestamp(struct intel_guc *guc,
> - struct intel_engine_cs *engine,
> - ktime_t *now)
> +static u32 gpm_timestamp_shift(struct intel_gt *gt)
> {
> - u32 gt_stamp_now, gt_stamp_hi;
> + intel_wakeref_t wakeref;
> + u32 reg, shift;
> +
> + with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> + reg = intel_uncore_read(gt->uncore, RPM_CONFIG0);
> +
> + shift = (reg & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
> + GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT;
> +
> + return 3 - shift;
> +}
> +
> +static u64 gpm_timestamp(struct intel_gt *gt)
> +{
> + u32 lo, hi, old_hi, loop = 0;
> +
> + hi = intel_uncore_read(gt->uncore, MISC_STATUS1);
> + do {
> + lo = intel_uncore_read(gt->uncore, MISC_STATUS0);
> + old_hi = hi;
> + hi = intel_uncore_read(gt->uncore, MISC_STATUS1);
> + } while (old_hi != hi && loop++ < 2);
> +
> + return ((u64)hi << 32) | lo;
> +}
See intel_uncore_read64_2x32().
> +
> +static void guc_update_pm_timestamp(struct intel_guc *guc, ktime_t *now)
> +{
> + struct intel_gt *gt = guc_to_gt(guc);
> + u32 gt_stamp_lo, gt_stamp_hi;
> + u64 gpm_ts;
>
> lockdep_assert_held(>timestamp.lock);
>
> gt_stamp_hi = upper_32_bits(guc->timestamp.gt_stamp);
> - gt_stamp_now = intel_uncore_read(engine->uncore,
> - RING_TIMESTAMP(engine->mmio_base));
> + gpm_ts = gpm_timestamp(gt) >> guc->timestamp.shift;
> + gt_stamp_lo = lower_32_bits(gpm_ts);
> *now = ktime_get();
>
> - if (gt_stamp_now < lower_32_bits(guc->timestamp.gt_stamp))
> + if (gt_stamp_lo < lower_32_bits(guc->timestamp.gt_stamp))
> gt_stamp_hi++;
>
> - guc->timestamp.gt_stamp = ((u64)gt_stamp_hi << 32) | gt_stamp_now;
> + guc->timestamp.gt_stamp = ((u64)gt_stamp_hi << 32) | gt_stamp_lo;
> }
>
> /*
> @@ -1210,7 +1238,7 @@ static ktime_t guc_engine_busyness(struct
> intel_engine_cs *engine, ktime_t *now)
> stats_saved = *stats;
> gt_stamp_saved = guc->timestamp.gt_stamp;
> guc_update_engine_gt_clks(engine);
> - guc_update_pm_timestamp(guc, engine, now);
> + guc_update_pm_timestamp(guc, now);
> intel_gt_pm_put_async(gt);
> if (i915_reset_count(gpu_error) != reset_count) {
> *stats = stats_saved;
> @@ -1242,8 +1270,8 @@ static void __reset_guc_busyness_stats(struct intel_guc
> *guc)
>
> spin_lock_irqsave(>timestamp.lock, flags);
>
> + guc_update_pm_timestamp(guc, );
> for_each_engine(engine, gt, id) {
> - guc_update_pm_timestamp(guc, engine, );
> guc_update_engine_gt_clks(engine);
> engine->stats.guc.prev_total = 0;
> }
> @@ -1260,10 +1288,11 @@ static void __update_guc_busyness_stats(struct
> intel_guc *guc)
> ktime_t unused;
>
> spin_lock_irqsave(>timestamp.lock, flags);
> - for_each_engine(engine, gt, id) {
Re: [Intel-gfx] [PATCH 5/5] drm/i915: Move dsc/joiner enable into hsw_crtc_enable()
On Mon, 24 Jan 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Lift the dsc/joiner enable up from the wonky places where it
> currently sits (ddi .pre_enable() or icl_ddi_bigjoiner_pre_enable())
> into hsw_crtc_enable() where we write the other per-pipe stuff
> as well. Makes the transcoder vs. pipe split less confusing.
>
What about the enable call in DSI?
BR,
Jani.
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 6 --
> drivers/gpu/drm/i915/display/intel_display.c | 12 +---
> 2 files changed, 5 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 2f20abc5122d..5d1f7d6218c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2425,9 +2425,6 @@ static void tgl_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
> intel_ddi_enable_fec(encoder, crtc_state);
>
> intel_dsc_dp_pps_write(encoder, crtc_state);
> -
> - if (!crtc_state->bigjoiner)
> - intel_dsc_enable(crtc_state);
> }
>
> static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
> @@ -2493,9 +2490,6 @@ static void hsw_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
> intel_ddi_enable_pipe_clock(encoder, crtc_state);
>
> intel_dsc_dp_pps_write(encoder, crtc_state);
> -
> - if (!crtc_state->bigjoiner)
> - intel_dsc_enable(crtc_state);
> }
>
> static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index d2906434ab3f..13b1de03640d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1974,7 +1974,6 @@ static void hsw_set_frame_start_delay(const struct
> intel_crtc_state *crtc_state)
> static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
>const struct intel_crtc_state
> *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc_state *master_crtc_state;
> struct intel_crtc *master_crtc;
> struct drm_connector_state *conn_state;
> @@ -2004,12 +2003,6 @@ static void icl_ddi_bigjoiner_pre_enable(struct
> intel_atomic_state *state,
>
> if (crtc_state->bigjoiner_slave)
> intel_encoders_pre_enable(state, master_crtc);
> -
> - /* need to enable VDSC, which we skipped in pre-enable */
> - intel_dsc_enable(crtc_state);
> -
> - if (DISPLAY_VER(dev_priv) >= 13)
> - intel_uncompressed_joiner_enable(crtc_state);
> }
>
> static void hsw_configure_cpu_transcoder(const struct intel_crtc_state
> *crtc_state)
> @@ -2057,6 +2050,11 @@ static void hsw_crtc_enable(struct intel_atomic_state
> *state,
> icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
> }
>
> + intel_dsc_enable(new_crtc_state);
> +
> + if (DISPLAY_VER(dev_priv) >= 13)
> + intel_uncompressed_joiner_enable(new_crtc_state);
> +
> intel_set_pipe_src_size(new_crtc_state);
> if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> bdw_set_pipemisc(new_crtc_state);
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/5] drm/i915: Skip dsc readout if the transcoder is disabled
== Series Details == Series: series starting with [1/5] drm/i915: Skip dsc readout if the transcoder is disabled URL : https://patchwork.freedesktop.org/series/99276/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11129_full -> Patchwork_22088_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22088_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22088_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 10) -- Missing(1): shard-tglu Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22088_full: ### IGT changes ### Possible regressions * igt@gem_create@create-massive: - shard-kbl: NOTRUN -> [DMESG-WARN][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22088/shard-kbl4/igt@gem_cre...@create-massive.html * igt@gem_exec_whisper@basic-contexts-priority: - shard-tglb: [PASS][2] -> [INCOMPLETE][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-tglb1/igt@gem_exec_whis...@basic-contexts-priority.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22088/shard-tglb5/igt@gem_exec_whis...@basic-contexts-priority.html * igt@gem_userptr_blits@input-checking: - shard-skl: NOTRUN -> [DMESG-WARN][4] +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22088/shard-skl6/igt@gem_userptr_bl...@input-checking.html - shard-apl: NOTRUN -> [DMESG-WARN][5] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22088/shard-apl6/igt@gem_userptr_bl...@input-checking.html * igt@kms_cursor_legacy@all-pipes-torture-bo: - shard-skl: [PASS][6] -> [INCOMPLETE][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-skl6/igt@kms_cursor_leg...@all-pipes-torture-bo.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22088/shard-skl5/igt@kms_cursor_leg...@all-pipes-torture-bo.html Known issues Here are the changes found in Patchwork_22088_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-apl: ([PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32]) -> ([PASS][33], [PASS][34], [PASS][35], [FAIL][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57]) ([i915#4386]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl1/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl1/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl1/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl1/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl2/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl2/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl2/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl2/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl3/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl3/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl3/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl4/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl4/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl4/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl6/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl6/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl6/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl6/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl7/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl7/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl7/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl8/boot.html [30]:
Re: [Intel-gfx] [PATCH 4/5] drm/i915: Extract hsw_configure_cpu_transcoder()
On Mon, 24 Jan 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Pull the transcoder specific modeset steps into a single place.
> With bigoiner we need to keep in mind wheher we're dealing with
> the transcoder or the pipe, and a slightly higher level split makes
> that easier.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 38
> 1 file changed, 23 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index c23c854f212f..d2906434ab3f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2012,6 +2012,27 @@ static void icl_ddi_bigjoiner_pre_enable(struct
> intel_atomic_state *state,
> intel_uncompressed_joiner_enable(crtc_state);
> }
>
> +static void hsw_configure_cpu_transcoder(const struct intel_crtc_state
> *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> + intel_set_transcoder_timings(crtc_state);
> +
> + if (cpu_transcoder != TRANSCODER_EDP)
> + intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
> +crtc_state->pixel_multiplier - 1);
> +
> + if (crtc_state->has_pch_encoder)
> + intel_cpu_transcoder_set_m_n(crtc_state,
> + _state->fdi_m_n, NULL);
> +
> + hsw_set_frame_start_delay(crtc_state);
> +
> + hsw_set_transconf(crtc_state);
> +}
> +
> static void hsw_crtc_enable(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> @@ -2040,21 +2061,8 @@ static void hsw_crtc_enable(struct intel_atomic_state
> *state,
> if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> bdw_set_pipemisc(new_crtc_state);
>
> - if (!new_crtc_state->bigjoiner_slave &&
> !transcoder_is_dsi(cpu_transcoder)) {
> - intel_set_transcoder_timings(new_crtc_state);
> -
> - if (cpu_transcoder != TRANSCODER_EDP)
> - intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
> -new_crtc_state->pixel_multiplier - 1);
> -
> - if (new_crtc_state->has_pch_encoder)
> - intel_cpu_transcoder_set_m_n(new_crtc_state,
> - _crtc_state->fdi_m_n,
> NULL);
> -
> - hsw_set_frame_start_delay(new_crtc_state);
> -
> - hsw_set_transconf(new_crtc_state);
> - }
> + if (!new_crtc_state->bigjoiner_slave &&
> !transcoder_is_dsi(cpu_transcoder))
> + hsw_configure_cpu_transcoder(new_crtc_state);
>
> crtc->active = true;
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 1/5] drm/i915: Skip dsc readout if the transcoder is disabled
On Mon, 24 Jan 2022, Ville Syrjala wrote: > From: Ville Syrjälä > > Tryingf to do readout when we don't even have a cpu transcoder > is not a great idea. Don't do it. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_display.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 80bc52425e47..e32a7a1e7ba0 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -4380,13 +4380,13 @@ static bool hsw_get_pipe_config(struct intel_crtc > *crtc, > active = true; > } > > + if (!active) > + goto out; > + > intel_dsc_get_config(pipe_config); > if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config->dsc.compression_enable) > intel_uncompressed_joiner_get_config(pipe_config); > > - if (!active) > - goto out; > - > if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || > DISPLAY_VER(dev_priv) >= 11) > intel_get_transcoder_timings(crtc, pipe_config); -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate
On Mon, 24 Jan 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use DISPLAY_VER rather than GRAPHICS_VER to determine
> availability of display hardware features.
>
> Signed-off-by: Ville Syrjälä
On both patches,
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_drv.h | 18 +-
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 44c1f98144b4..e2b8409f9174 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1463,8 +1463,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
> (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
>
> -#define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
> -#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11 || \
> +#define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4)
> +#define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \
> IS_GEMINILAKE(dev_priv) || \
> IS_KABYLAKE(dev_priv))
>
> @@ -1476,9 +1476,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define SUPPORTS_TV(dev_priv)
> (INTEL_INFO(dev_priv)->display.supports_tv)
> #define I915_HAS_HOTPLUG(dev_priv)
> (INTEL_INFO(dev_priv)->display.has_hotplug)
>
> -#define HAS_FW_BLC(dev_priv) (GRAPHICS_VER(dev_priv) > 2)
> +#define HAS_FW_BLC(dev_priv) (DISPLAY_VER(dev_priv) > 2)
> #define HAS_FBC(dev_priv)(INTEL_INFO(dev_priv)->display.fbc_mask != 0)
> -#define HAS_CUR_FBC(dev_priv)(!HAS_GMCH(dev_priv) &&
> GRAPHICS_VER(dev_priv) >= 7)
> +#define HAS_CUR_FBC(dev_priv)(!HAS_GMCH(dev_priv) &&
> DISPLAY_VER(dev_priv) >= 7)
>
> #define HAS_IPS(dev_priv)(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
>
> @@ -1491,7 +1491,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
> #define HAS_PSR_HW_TRACKING(dev_priv) \
> (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
> -#define HAS_PSR2_SEL_FETCH(dev_priv) (GRAPHICS_VER(dev_priv) >= 12)
> +#define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12)
> #define HAS_TRANSCODER(dev_priv, trans)
> ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0)
>
> #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
> @@ -1502,7 +1502,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_DMC(dev_priv)(INTEL_INFO(dev_priv)->display.has_dmc)
>
> -#define HAS_MSO(i915)(GRAPHICS_VER(i915) >= 12)
> +#define HAS_MSO(i915)(DISPLAY_VER(i915) >= 12)
>
> #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
> #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
> @@ -1535,7 +1535,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
>
> -#define HAS_LSPCON(dev_priv) (IS_GRAPHICS_VER(dev_priv, 9, 10))
> +#define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
>
> /* DPF == dynamic parity feature */
> #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
> @@ -1549,7 +1549,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->display.pipe_mask != 0)
>
> -#define HAS_VRR(i915)(GRAPHICS_VER(i915) >= 11)
> +#define HAS_VRR(i915)(DISPLAY_VER(i915) >= 11)
>
> #define HAS_ASYNC_FLIPS(i915)(DISPLAY_VER(i915) >= 5)
>
> @@ -1579,7 +1579,7 @@ i915_print_iommu_status(struct drm_i915_private *i915,
> struct drm_printer *p);
>
> static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
> *dev_priv)
> {
> - return GRAPHICS_VER(dev_priv) >= 6 && intel_vtd_active(dev_priv);
> + return DISPLAY_VER(dev_priv) >= 6 && intel_vtd_active(dev_priv);
> }
>
> static inline bool
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH] drm/i915/overlay: Prevent divide by zero bugs in scaling
On Mon, Jan 24, 2022 at 03:24:09PM +0300, Dan Carpenter wrote:
> Smatch detected a divide by zero bug in check_overlay_scaling().
>
> drivers/gpu/drm/i915/display/intel_overlay.c:976 check_overlay_scaling()
> error: potential divide by zero bug '/ rec->dst_height'.
> drivers/gpu/drm/i915/display/intel_overlay.c:980 check_overlay_scaling()
> error: potential divide by zero bug '/ rec->dst_width'.
>
> Prevent this by ensuring that the dst height and width are non-zero.
>
> Fixes: 02e792fbaadb ("drm/i915: implement drmmode overlay support v4")
> Signed-off-by: Dan Carpenter
Thanks. Pushed to drm-intel-next.
> ---
> >From static analysis. Not tested.
>
> drivers/gpu/drm/i915/display/intel_overlay.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c
> b/drivers/gpu/drm/i915/display/intel_overlay.c
> index 1a376e9a1ff3..d610e48cab94 100644
> --- a/drivers/gpu/drm/i915/display/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/display/intel_overlay.c
> @@ -959,6 +959,9 @@ static int check_overlay_dst(struct intel_overlay
> *overlay,
> const struct intel_crtc_state *pipe_config =
> overlay->crtc->config;
>
> + if (rec->dst_height == 0 || rec->dst_width == 0)
> + return -EINVAL;
> +
> if (rec->dst_x < pipe_config->pipe_src_w &&
> rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w &&
> rec->dst_y < pipe_config->pipe_src_h &&
> --
> 2.20.1
--
Ville Syrjälä
Intel
[Intel-gfx] ✗ Fi.CI.IGT: failure for Fix up request cancel (rev2)
== Series Details == Series: Fix up request cancel (rev2) URL : https://patchwork.freedesktop.org/series/99173/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11129_full -> Patchwork_22087_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22087_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22087_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 10) -- Missing(1): shard-tglu Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22087_full: ### IGT changes ### Possible regressions * igt@gem_create@create-massive: - shard-kbl: NOTRUN -> [DMESG-WARN][1] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22087/shard-kbl7/igt@gem_cre...@create-massive.html - shard-apl: NOTRUN -> [DMESG-WARN][2] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22087/shard-apl1/igt@gem_cre...@create-massive.html * igt@gem_linear_blits@interruptible: - shard-glk: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-glk4/igt@gem_linear_bl...@interruptible.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22087/shard-glk5/igt@gem_linear_bl...@interruptible.html * igt@gem_userptr_blits@input-checking: - shard-skl: NOTRUN -> [DMESG-WARN][5] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22087/shard-skl2/igt@gem_userptr_bl...@input-checking.html Known issues Here are the changes found in Patchwork_22087_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-kbl: [PASS][6] -> [INCOMPLETE][7] ([i915#794]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-kbl6/igt@gem_ctx_isolation@preservation...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22087/shard-kbl4/igt@gem_ctx_isolation@preservation...@rcs0.html * igt@gem_ctx_sseu@mmap-args: - shard-apl: NOTRUN -> [SKIP][8] ([fdo#109271]) +59 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22087/shard-apl7/igt@gem_ctx_s...@mmap-args.html * igt@gem_eio@in-flight-contexts-10ms: - shard-skl: [PASS][9] -> [TIMEOUT][10] ([i915#3063]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-skl7/igt@gem_...@in-flight-contexts-10ms.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22087/shard-skl9/igt@gem_...@in-flight-contexts-10ms.html * igt@gem_eio@in-flight-contexts-immediate: - shard-tglb: [PASS][11] -> [TIMEOUT][12] ([i915#3063]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-tglb6/igt@gem_...@in-flight-contexts-immediate.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22087/shard-tglb2/igt@gem_...@in-flight-contexts-immediate.html * igt@gem_eio@unwedge-stress: - shard-iclb: [PASS][13] -> [TIMEOUT][14] ([i915#2481] / [i915#3070]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb7/igt@gem_...@unwedge-stress.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22087/shard-iclb3/igt@gem_...@unwedge-stress.html * igt@gem_exec_balancer@parallel: - shard-iclb: [PASS][15] -> [SKIP][16] ([i915#4525]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb4/igt@gem_exec_balan...@parallel.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22087/shard-iclb5/igt@gem_exec_balan...@parallel.html * igt@gem_exec_capture@pi@rcs0: - shard-skl: [PASS][17] -> [INCOMPLETE][18] ([i915#4547]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-skl7/igt@gem_exec_capture@p...@rcs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22087/shard-skl4/igt@gem_exec_capture@p...@rcs0.html * igt@gem_exec_fair@basic-deadline: - shard-skl: NOTRUN -> [FAIL][19] ([i915#2846]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22087/shard-skl7/igt@gem_exec_f...@basic-deadline.html - shard-glk: [PASS][20] -> [FAIL][21] ([i915#2846]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-glk9/igt@gem_exec_f...@basic-deadline.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22087/shard-glk7/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-skl: NOTRUN -> [SKIP][22] ([fdo#109271]) +125 similar issues [22]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: make static read-only array page_count const
== Series Details == Series: drm/i915/selftests: make static read-only array page_count const URL : https://patchwork.freedesktop.org/series/99252/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11129_full -> Patchwork_22085_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22085_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22085_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 10) -- Missing(1): shard-tglu Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22085_full: ### IGT changes ### Possible regressions * igt@gem_create@create-massive: - shard-kbl: NOTRUN -> [DMESG-WARN][1] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-kbl1/igt@gem_cre...@create-massive.html * igt@gem_userptr_blits@input-checking: - shard-skl: NOTRUN -> [DMESG-WARN][2] +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-skl10/igt@gem_userptr_bl...@input-checking.html - shard-apl: NOTRUN -> [DMESG-WARN][3] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-apl7/igt@gem_userptr_bl...@input-checking.html Known issues Here are the changes found in Patchwork_22085_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@many-contexts: - shard-iclb: [PASS][4] -> [FAIL][5] ([i915#2410]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb6/igt@gem_ctx_persiste...@many-contexts.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-iclb3/igt@gem_ctx_persiste...@many-contexts.html - shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2410]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-tglb1/igt@gem_ctx_persiste...@many-contexts.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-tglb3/igt@gem_ctx_persiste...@many-contexts.html * igt@gem_eio@in-flight-contexts-10ms: - shard-skl: [PASS][8] -> [TIMEOUT][9] ([i915#3063]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-skl7/igt@gem_...@in-flight-contexts-10ms.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-skl9/igt@gem_...@in-flight-contexts-10ms.html * igt@gem_eio@in-flight-contexts-1us: - shard-iclb: [PASS][10] -> [TIMEOUT][11] ([i915#3070]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb7/igt@gem_...@in-flight-contexts-1us.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-iclb2/igt@gem_...@in-flight-contexts-1us.html * igt@gem_eio@unwedge-stress: - shard-iclb: [PASS][12] -> [TIMEOUT][13] ([i915#2481] / [i915#3070]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb7/igt@gem_...@unwedge-stress.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-iclb2/igt@gem_...@unwedge-stress.html * igt@gem_exec_capture@pi@vecs0: - shard-skl: NOTRUN -> [INCOMPLETE][14] ([i915#4547]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-skl2/igt@gem_exec_capture@p...@vecs0.html * igt@gem_exec_fair@basic-deadline: - shard-skl: NOTRUN -> [FAIL][15] ([i915#2846]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-skl1/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271]) +95 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-skl10/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-glk: [PASS][17] -> [FAIL][18] ([i915#2842]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-glk8/igt@gem_exec_fair@basic-none-sh...@rcs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-glk2/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-tglb: NOTRUN -> [FAIL][19] ([i915#2842]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/shard-tglb2/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-kbl: [PASS][20] -> [FAIL][21] ([i915#2842]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-kbl4/igt@gem_exec_fair@basic-pace-s...@rcs0.html [21]:
[Intel-gfx] ✓ Fi.CI.BAT: success for Second round of i915_reg.h splitting (rev2)
== Series Details ==
Series: Second round of i915_reg.h splitting (rev2)
URL : https://patchwork.freedesktop.org/series/99079/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22094
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/index.html
Participating hosts (51 -> 45)
--
Additional (1): fi-pnv-d510
Missing(7): shard-tglu fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 shard-rkl
shard-dg1 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_22094 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-pnv-d510:NOTRUN -> [SKIP][1] ([fdo#109271]) +39 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html
* igt@i915_selftest@live:
- fi-skl-6600u: NOTRUN -> [FAIL][2] ([i915#4547])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-skl-6600u/igt@i915_selft...@live.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][3] ([i915#2927] / [i915#4528])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-pnv-d510/igt@i915_selftest@l...@requests.html
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][4] ([fdo#109271] / [i915#2403] /
[i915#4312])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-pnv-d510/igt@run...@aborted.html
- fi-skl-6600u: NOTRUN -> [FAIL][5] ([i915#1436] / [i915#4312])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-skl-6600u/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}: [DMESG-FAIL][6] ([i915#541]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
- fi-bsw-kefka: [DMESG-FAIL][8] ([i915#541]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [DMESG-FAIL][10] ([i915#4494]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][12] ([i915#4269]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
Warnings
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][14] -> [DMESG-FAIL][15] ([i915#4494])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
- fi-hsw-4770:[INCOMPLETE][16] ([i915#3303]) -> [INCOMPLETE][17]
([i915#4785])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Build changes
-
* Linux:
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/edid: Support type 7 timings
== Series Details == Series: drm/edid: Support type 7 timings URL : https://patchwork.freedesktop.org/series/99250/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11129_full -> Patchwork_22082_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22082_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22082_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 10) -- Missing(1): shard-tglu Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22082_full: ### IGT changes ### Possible regressions * igt@gem_userptr_blits@input-checking: - shard-apl: NOTRUN -> [DMESG-WARN][1] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-apl1/igt@gem_userptr_bl...@input-checking.html Known issues Here are the changes found in Patchwork_22082_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@many-contexts: - shard-tglb: [PASS][2] -> [FAIL][3] ([i915#2410]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-tglb1/igt@gem_ctx_persiste...@many-contexts.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-tglb1/igt@gem_ctx_persiste...@many-contexts.html * igt@gem_ctx_persistence@smoketest: - shard-tglb: [PASS][4] -> [FAIL][5] ([i915#2896]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-tglb3/igt@gem_ctx_persiste...@smoketest.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-tglb6/igt@gem_ctx_persiste...@smoketest.html * igt@gem_eio@in-flight-contexts-10ms: - shard-iclb: [PASS][6] -> [TIMEOUT][7] ([i915#3070]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb8/igt@gem_...@in-flight-contexts-10ms.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-iclb5/igt@gem_...@in-flight-contexts-10ms.html * igt@gem_exec_balancer@parallel-balancer: - shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb2/igt@gem_exec_balan...@parallel-balancer.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-iclb3/igt@gem_exec_balan...@parallel-balancer.html * igt@gem_exec_fair@basic-deadline: - shard-skl: NOTRUN -> [FAIL][10] ([i915#2846]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-skl9/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: NOTRUN -> [FAIL][11] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-kbl4/igt@gem_exec_fair@basic-none-s...@rcs0.html - shard-tglb: NOTRUN -> [FAIL][12] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-tglb5/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#2842]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-kbl3/igt@gem_exec_fair@basic-n...@vcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-kbl7/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][15] ([i915#2842]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-iclb4/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-tglb: [PASS][16] -> [FAIL][17] ([i915#2842]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-tglb2/igt@gem_exec_fair@basic-pace-s...@rcs0.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-tglb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_lmem_swapping@basic: - shard-kbl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-kbl7/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@smem-oom: - shard-skl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-skl8/igt@gem_lmem_swapp...@smem-oom.html * igt@gem_pread@exhaustion: - shard-kbl: NOTRUN -> [WARN][20] ([i915#2658]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/shard-kbl1/igt@gem_pr...@exhaustion.html - shard-skl: NOTRUN -> [WARN][21]
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Second round of i915_reg.h splitting (rev2)
== Series Details == Series: Second round of i915_reg.h splitting (rev2) URL : https://patchwork.freedesktop.org/series/99079/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Second round of i915_reg.h splitting (rev2)
== Series Details ==
Series: Second round of i915_reg.h splitting (rev2)
URL : https://patchwork.freedesktop.org/series/99079/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
48db4167e8d0 drm/i915/perf: Move OA regs to their own header
-:39: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 1023 lines checked
0a70f3e5b4bc drm/i915/perf: Express OA register ranges with i915_range
-:32: ERROR:OPEN_BRACE: open brace '{' following function definitions go on the
next line
#32: FILE: drivers/gpu/drm/i915/i915_perf.c:3867:
+static bool reg_in_range_table(u32 addr, const struct i915_range *table) {
-:89: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#89: FILE: drivers/gpu/drm/i915/i915_perf.c:3914:
+ { .start = 0x182300, .end = 0x1823a4 },$
-:90: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#90: FILE: drivers/gpu/drm/i915/i915_perf.c:3915:
+ {}$
total: 1 errors, 2 warnings, 0 checks, 524 lines checked
35f45d644995 drm/i915: Parameterize R_PWR_CLK_STATE register definition
75196de08f35 drm/i915: Parameterize MI_PREDICATE registers
e304eedf6882 drm/i915: Move GT registers to their own header file
-:181: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#181:
new file mode 100644
-:294: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#294: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:109:
+#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 <<
GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
-:296: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#296: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:111:
+#define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK(0x3 <<
GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
-:411: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#411: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:226:
+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 <<
GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
-:415: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#415: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:230:
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 <<
GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
-:421: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#421: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:236:
+#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK(0x3 <<
GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
-:741: WARNING:LONG_LINE_COMMENT: line length of 104 exceeds 100 columns
#741: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:556:
+#define PXVFREQ(fstart)_MMIO(0x0 + (fstart) * 4) /*
P[0-15]VIDFREQ (0x1114c) (Ironlake) */
-:780: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#780: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:595:
+#define MEMCTL_CMD_STS (1 << 12) /* write 1 triggers command, clears
+when command complete */
-:780: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a
separate line
#780: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:595:
+when command complete */
-:893: WARNING:LONG_LINE_COMMENT: line length of 134 exceeds 100 columns
#893: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:708:
+#define IMPROMOEN(1 << 10) /* promo is immediate or delayed
until next idle interval (only for timeout method above) */
-:980: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'cxt_reg' - possible
side-effects?
#980: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:795:
+#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
+ GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
+ GEN6_CXT_PIPELINE_SIZE(cxt_reg))
-:990: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ctx_reg' - possible
side-effects?
#990: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:805:
+#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
+GEN7_CXT_VFSTATE_SIZE(ctx_reg))
-:1560: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'slice' - possible
side-effects?
#1560: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:1375:
+#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
+((slice) % 3) * 0x4)
-:1567: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'slice' - possible
side-effects?
#1567: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:1382:
+#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
+((slice) % 3) * 0x8)
-:1570: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'slice' - possible
side-effects?
#1570: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:1385:
+#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
+((slice) % 3) * 0x8)
total: 0 errors, 10 warnings, 5 checks, 3535 lines checked
033e2e31ec1c drm/i915: Only
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for reference
== Series Details ==
Series: series starting with [1/2] drm/i915/pmu: Use PM timestamp instead of
RING TIMESTAMP for reference
URL : https://patchwork.freedesktop.org/series/99301/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22093
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22093/index.html
Participating hosts (51 -> 43)
--
Missing(8): shard-tglu fi-hsw-4200u fi-bsw-cyan fi-ilk-650 fi-ctg-p8600
shard-rkl shard-dg1 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_22093 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@late_gt_pm:
- fi-bsw-nick:[PASS][1] -> [DMESG-FAIL][2] ([i915#2927] /
[i915#3428])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22093/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
* igt@kms_psr@primary_page_flip:
- fi-skl-6600u: [PASS][3] -> [FAIL][4] ([i915#4547])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22093/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
* igt@runner@aborted:
- fi-skl-6600u: NOTRUN -> [FAIL][5] ([i915#4312])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22093/fi-skl-6600u/igt@run...@aborted.html
- fi-bsw-nick:NOTRUN -> [FAIL][6] ([fdo#109271] / [i915#1436] /
[i915#3428] / [i915#4312])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22093/fi-bsw-nick/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}: [DMESG-FAIL][7] ([i915#541]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22093/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
- fi-bsw-kefka: [DMESG-FAIL][9] ([i915#541]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22093/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
Warnings
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][11] -> [DMESG-FAIL][12] ([i915#4494])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22093/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Build changes
-
* Linux: CI_DRM_11129 -> Patchwork_22093
CI-20190529: 20190529
CI_DRM_11129: 0b83d3cf9f9eab03ec804d56ac2686320a64f3ee @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6330: f73008bac9a8db0779264b170f630483e9165764 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22093: 4e9418c964cee10547ef67bdde75703f8de1fea0 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4e9418c964ce drm/i915/pmu: Fix KMD and GuC race on accessing busyness
9fe230d0 drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for
reference
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22093/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for reference
== Series Details == Series: series starting with [1/2] drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for reference URL : https://patchwork.freedesktop.org/series/99301/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Fix NULL vs IS_ERR checking for kernel_context (rev2)
== Series Details == Series: drm/i915/selftests: Fix NULL vs IS_ERR checking for kernel_context (rev2) URL : https://patchwork.freedesktop.org/series/98685/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11129_full -> Patchwork_22081_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22081_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22081_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 10) -- Missing(1): shard-tglu Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22081_full: ### IGT changes ### Possible regressions * igt@gem_create@create-massive: - shard-skl: NOTRUN -> [DMESG-WARN][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/shard-skl8/igt@gem_cre...@create-massive.html * igt@gem_userptr_blits@input-checking: - shard-apl: NOTRUN -> [DMESG-WARN][2] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/shard-apl2/igt@gem_userptr_bl...@input-checking.html - shard-kbl: NOTRUN -> [DMESG-WARN][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/shard-kbl7/igt@gem_userptr_bl...@input-checking.html Known issues Here are the changes found in Patchwork_22081_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-kbl: [PASS][4] -> [INCOMPLETE][5] ([i915#794]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-kbl6/igt@gem_ctx_isolation@preservation...@rcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/shard-kbl4/igt@gem_ctx_isolation@preservation...@rcs0.html * igt@gem_eio@in-flight-immediate: - shard-skl: [PASS][6] -> [TIMEOUT][7] ([i915#3063]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-skl6/igt@gem_...@in-flight-immediate.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/shard-skl8/igt@gem_...@in-flight-immediate.html * igt@gem_exec_balancer@parallel: - shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb4/igt@gem_exec_balan...@parallel.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/shard-iclb7/igt@gem_exec_balan...@parallel.html * igt@gem_exec_capture@pi@rcs0: - shard-skl: [PASS][10] -> [INCOMPLETE][11] ([i915#4547]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-skl7/igt@gem_exec_capture@p...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/shard-skl9/igt@gem_exec_capture@p...@rcs0.html * igt@gem_exec_fair@basic-deadline: - shard-glk: [PASS][12] -> [FAIL][13] ([i915#2846]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-glk9/igt@gem_exec_f...@basic-deadline.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/shard-glk1/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-glk: [PASS][14] -> [FAIL][15] ([i915#2842]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-glk8/igt@gem_exec_fair@basic-none-sh...@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/shard-glk9/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: NOTRUN -> [FAIL][16] ([i915#2842]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/shard-kbl7/igt@gem_exec_fair@basic-none-s...@rcs0.html - shard-apl: NOTRUN -> [FAIL][17] ([i915#2842]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/shard-apl7/igt@gem_exec_fair@basic-none-s...@rcs0.html - shard-tglb: NOTRUN -> [FAIL][18] ([i915#2842]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/shard-tglb2/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-kbl: [PASS][19] -> [FAIL][20] ([i915#2842]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-kbl3/igt@gem_exec_fair@basic-n...@rcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/shard-kbl3/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-tglb: [PASS][21] -> [FAIL][22] ([i915#2842]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-tglb2/igt@gem_exec_fair@basic-pace-s...@rcs0.html [22]:
[Intel-gfx] [PATCH v2 2/6] drm/i915/perf: Express OA register ranges with i915_range
Let's use 'struct i915_range' to express sets of b-counter and mux
registers in the perf code. This makes the code more similar to how we
handle things like multicast register ranges, forcewake tables, shadow
tables, etc. and also lets us avoid needing symbolic register name
definitions for the various range end points. With this change, many of
the OA register definitions are no longer used in the code, so we can
drop their #define's for simplicity.
v2: Drop 'inline' from reg_in_range_table(). (Jani)
Cc: Jani Nikula
Cc: Umesh Nerlige Ramappa
Cc: Lionel Landwerlin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_perf.c | 120 +---
drivers/gpu/drm/i915/i915_perf_oa_regs.h | 360 ---
2 files changed, 77 insertions(+), 403 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 20af83517cb1..804e87b6ed0c 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3864,80 +3864,114 @@ static bool gen8_is_valid_flex_addr(struct i915_perf
*perf, u32 addr)
return false;
}
-#define ADDR_IN_RANGE(addr, start, end) \
- ((addr) >= (start) && \
-(addr) <= (end))
+static bool reg_in_range_table(u32 addr, const struct i915_range *table) {
+ while (table->start || table->end) {
+ if (addr >= table->start && addr <= table->end)
+ return true;
+
+ table++;
+ }
-#define REG_IN_RANGE(addr, start, end) \
- ((addr) >= i915_mmio_reg_offset(start) && \
-(addr) <= i915_mmio_reg_offset(end))
+ return false;
+}
#define REG_EQUAL(addr, mmio) \
((addr) == i915_mmio_reg_offset(mmio))
-static bool gen7_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
-{
- return REG_IN_RANGE(addr, OASTARTTRIG1, OASTARTTRIG8) ||
- REG_IN_RANGE(addr, OAREPORTTRIG1, OAREPORTTRIG8) ||
- REG_IN_RANGE(addr, OACEC0_0, OACEC7_1);
-}
+static const struct i915_range gen7_oa_b_counters[] = {
+ { .start = 0x2710, .end = 0x272c }, /* OASTARTTRIG[1-8] */
+ { .start = 0x2740, .end = 0x275c }, /* OAREPORTTRIG[1-8] */
+ { .start = 0x2770, .end = 0x27ac }, /* OACEC[0-7][0-1] */
+ {}
+};
+
+static const struct i915_range gen12_oa_b_counters[] = {
+ { .start = 0x2b2c, .end = 0x2b2c }, /* GEN12_OAG_OA_PESS */
+ { .start = 0xd900, .end = 0xd91c }, /* GEN12_OAG_OASTARTTRIG[1-8] */
+ { .start = 0xd920, .end = 0xd93c }, /* GEN12_OAG_OAREPORTTRIG1[1-8]
*/
+ { .start = 0xd940, .end = 0xd97c }, /* GEN12_OAG_CEC[0-7][0-1] */
+ { .start = 0xdc00, .end = 0xdc3c }, /* GEN12_OAG_SCEC[0-7][0-1] */
+ { .start = 0xdc40, .end = 0xdc40 }, /* GEN12_OAG_SPCTR_CNF */
+ { .start = 0xdc44, .end = 0xdc44 }, /* GEN12_OAA_DBG_REG */
+ {}
+};
+
+static const struct i915_range gen7_oa_mux_regs[] = {
+ { .start = 0x91b8, .end = 0x91cc }, /* OA_PERFCNT[1-2],
OA_PERFMATRIX */
+ { .start = 0x9800, .end = 0x9888 }, /* MICRO_BP0_0 - NOA_WRITE */
+ { .start = 0xe180, .end = 0xe180 }, /* HALF_SLICE_CHICKEN2 */
+ {}
+};
-static bool gen7_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
+static const struct i915_range hsw_oa_mux_regs[] = {
+ { .start = 0x09e80, .end = 0x09ea4 }, /* HSW_MBVID2_NOA[0-9] */
+ { .start = 0x09ec0, .end = 0x09ec0 }, /* HSW_MBVID2_MISR0 */
+ { .start = 0x25100, .end = 0x2ff90 },
+ {}
+};
+
+static const struct i915_range chv_oa_mux_regs[] = {
+ { .start = 0x182300, .end = 0x1823a4 },
+ {}
+};
+
+static const struct i915_range gen8_oa_mux_regs[] = {
+ { .start = 0x0d00, .end = 0x0d2c }, /* RPM_CONFIG[0-1],
NOA_CONFIG[0-8] */
+ { .start = 0x20cc, .end = 0x20cc }, /* WAIT_FOR_RC6_EXIT */
+ {}
+};
+
+static const struct i915_range gen11_oa_mux_regs[] = {
+ { .start = 0x91c8, .end = 0x91dc }, /* OA_PERFCNT[3-4] */
+ {}
+};
+
+static const struct i915_range gen12_oa_mux_regs[] = {
+ { .start = 0x0d00, .end = 0x0d2c }, /* RPM_CONFIG[0-1],
NOA_CONFIG[0-8] */
+ { .start = 0x9840, .end = 0x9840 }, /* GDT_CHICKEN_BITS */
+ { .start = 0x9884, .end = 0x9888 }, /* NOA_WRITE */
+ { .start = 0x20cc, .end = 0x20cc }, /* WAIT_FOR_RC6_EXIT */
+ {}
+};
+
+static bool gen7_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
{
- return REG_EQUAL(addr, HALF_SLICE_CHICKEN2) ||
- REG_IN_RANGE(addr, MICRO_BP0_0, NOA_WRITE) ||
- REG_IN_RANGE(addr, OA_PERFCNT1_LO, OA_PERFCNT2_HI) ||
- REG_IN_RANGE(addr, OA_PERFMATRIX_LO, OA_PERFMATRIX_HI);
+ return reg_in_range_table(addr, gen7_oa_b_counters);
}
static bool gen8_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
{
- return gen7_is_valid_mux_addr(perf, addr) ||
- REG_EQUAL(addr, WAIT_FOR_RC6_EXIT) ||
-
[Intel-gfx] [PATCH v2 1/6] drm/i915/perf: Move OA regs to their own header
The OA unit registers are only used by the perf code; move them to their own header file. Cc: Jani Nikula Cc: Umesh Nerlige Ramappa Cc: Lionel Landwerlin Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gvt/scheduler.c | 1 + drivers/gpu/drm/i915/i915_perf.c | 1 + drivers/gpu/drm/i915/i915_perf_oa_regs.h | 497 +++ drivers/gpu/drm/i915/i915_reg.h | 485 -- 4 files changed, 499 insertions(+), 485 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_perf_oa_regs.h diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index 42a0c9ae0a73..ecd90dbd9544 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -43,6 +43,7 @@ #include "i915_drv.h" #include "i915_gem_gtt.h" +#include "i915_perf_oa_regs.h" #include "gvt.h" #define RING_CTX_OFF(x) \ diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index da4045c9df4e..20af83517cb1 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -208,6 +208,7 @@ #include "i915_drv.h" #include "i915_perf.h" +#include "i915_perf_oa_regs.h" /* HW requires this to be a power of two, between 128k and 16M, though driver * is currently generally designed assuming the largest 16M size is used such diff --git a/drivers/gpu/drm/i915/i915_perf_oa_regs.h b/drivers/gpu/drm/i915/i915_perf_oa_regs.h new file mode 100644 index ..5896ed43f5c4 --- /dev/null +++ b/drivers/gpu/drm/i915/i915_perf_oa_regs.h @@ -0,0 +1,497 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2022 Intel Corporation + */ + +#ifndef __INTEL_PERF_OA_REGS__ +#define __INTEL_PERF_OA_REGS__ + +#include "i915_reg_defs.h" + +#define GEN7_OACONTROL _MMIO(0x2360) +#define GEN7_OACONTROL_CTX_MASK 0xF000 +#define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F +#define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6 +#define GEN7_OACONTROL_TIMER_ENABLE (1 << 5) +#define GEN7_OACONTROL_FORMAT_A13 (0 << 2) +#define GEN7_OACONTROL_FORMAT_A29 (1 << 2) +#define GEN7_OACONTROL_FORMAT_A13_B8_C8(2 << 2) +#define GEN7_OACONTROL_FORMAT_A29_B8_C8(3 << 2) +#define GEN7_OACONTROL_FORMAT_B4_C8 (4 << 2) +#define GEN7_OACONTROL_FORMAT_A45_B8_C8(5 << 2) +#define GEN7_OACONTROL_FORMAT_B4_C8_A16(6 << 2) +#define GEN7_OACONTROL_FORMAT_C4_B8 (7 << 2) +#define GEN7_OACONTROL_FORMAT_SHIFT 2 +#define GEN7_OACONTROL_PER_CTX_ENABLE (1 << 1) +#define GEN7_OACONTROL_ENABLE (1 << 0) + +#define GEN8_OACTXID _MMIO(0x2364) + +#define GEN8_OA_DEBUG _MMIO(0x2B04) +#define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS(1 << 5) +#define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6) +#define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2) +#define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1) + +#define GEN8_OACONTROL _MMIO(0x2B00) +#define GEN8_OA_REPORT_FORMAT_A12 (0 << 2) +#define GEN8_OA_REPORT_FORMAT_A12_B8_C8(2 << 2) +#define GEN8_OA_REPORT_FORMAT_A36_B8_C8(5 << 2) +#define GEN8_OA_REPORT_FORMAT_C4_B8 (7 << 2) +#define GEN8_OA_REPORT_FORMAT_SHIFT 2 +#define GEN8_OA_SPECIFIC_CONTEXT_ENABLE(1 << 1) +#define GEN8_OA_COUNTER_ENABLE (1 << 0) + +#define GEN8_OACTXCONTROL _MMIO(0x2360) +#define GEN8_OA_TIMER_PERIOD_MASK 0x3F +#define GEN8_OA_TIMER_PERIOD_SHIFT2 +#define GEN8_OA_TIMER_ENABLE (1 << 1) +#define GEN8_OA_COUNTER_RESUME(1 << 0) + +#define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */ +#define GEN7_OABUFFER_OVERRUN_DISABLE (1 << 3) +#define GEN7_OABUFFER_EDGE_TRIGGER(1 << 2) +#define GEN7_OABUFFER_STOP_RESUME_ENABLE (1 << 1) +#define GEN7_OABUFFER_RESUME (1 << 0) + +#define GEN8_OABUFFER_UDW _MMIO(0x23b4) +#define GEN8_OABUFFER _MMIO(0x2b14) +#define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */ + +#define GEN7_OASTATUS1 _MMIO(0x2364) +#define GEN7_OASTATUS1_TAIL_MASK 0xffc0 +#define GEN7_OASTATUS1_COUNTER_OVERFLOW(1 << 2) +#define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1) +#define GEN7_OASTATUS1_REPORT_LOST(1 << 0) + +#define GEN7_OASTATUS2 _MMIO(0x2368) +#define GEN7_OASTATUS2_HEAD_MASK 0xffc0 +#define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */ + +#define GEN8_OASTATUS _MMIO(0x2b08) +#define GEN8_OASTATUS_TAIL_POINTER_WRAP(1 << 17) +#define GEN8_OASTATUS_HEAD_POINTER_WRAP(1 << 16) +#define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3) +#define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2) +#define GEN8_OASTATUS_OABUFFER_OVERFLOW(1 << 1) +#define GEN8_OASTATUS_REPORT_LOST (1 << 0) + +#define GEN8_OAHEADPTR _MMIO(0x2B0C) +#define GEN8_OAHEADPTR_MASK0xffc0 +#define GEN8_OATAILPTR _MMIO(0x2B10) +#define GEN8_OATAILPTR_MASK0xffc0 + +#define
[Intel-gfx] [PATCH v2 4/6] drm/i915: Parameterize MI_PREDICATE registers
The various MI_PREDICATE registers have per-engine instances. Today we
only utilize the RCS0 instance of each, but that will likely change in
the future; switch to parameterized register definitions to make these
easier to work with going forward.
Of special note is MI_PREDICATE_RESULT_2; we only use it in one place in
the driver today in HSW-specific code. It turns out that the bspec
(page 94) lists two different offsets for this register on HSW; one is
in the standard location shared by all other platforms (base + 0x3bc)
and the other is an unusual location (0x2214). We're using the second,
non-standard offset in i915 today; that offset doesn't exist on any
other platforms (and it's not even 100% clear that it's correct for HSW)
so I've renamed the current non-standard definition to
HSW_MI_PREDICATE_RESULT_2; the new cross-platform parameterized macro
(which is still unused at the moment) uses the standard offset.
Cc: Jani Nikula
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 11 +++
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/i915_cmd_parser.c | 4 ++--
drivers/gpu/drm/i915/i915_perf.c| 8
drivers/gpu/drm/i915/i915_reg.h | 11 +--
5 files changed, 19 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
index daf4a241cf77..e9fec6214073 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -142,6 +142,17 @@
(REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
+#define MI_PREDICATE_RESULT_2(base)_MMIO((base) + 0x3bc)
+#define LOWER_SLICE_ENABLED (1 << 0)
+#define LOWER_SLICE_DISABLED (0 << 0)
+#define MI_PREDICATE_SRC0(base)_MMIO((base) + 0x400)
+#define MI_PREDICATE_SRC0_UDW(base)_MMIO((base) + 0x400 + 4)
+#define MI_PREDICATE_SRC1(base)_MMIO((base) + 0x408)
+#define MI_PREDICATE_SRC1_UDW(base)_MMIO((base) + 0x408 + 4)
+#define MI_PREDICATE_DATA(base)_MMIO((base) + 0x410)
+#define MI_PREDICATE_RESULT(base) _MMIO((base) + 0x418)
+#define MI_PREDICATE_RESULT_1(base)_MMIO((base) + 0x41c)
+
#define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
#define PP_DIR_DCLV_2G 0x
#define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 622cdfed8a8b..3889efb3ffa4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -209,7 +209,7 @@ int intel_gt_init_hw(struct intel_gt *gt)
if (IS_HASWELL(i915))
intel_uncore_write(uncore,
- MI_PREDICATE_RESULT_2,
+ HSW_MI_PREDICATE_RESULT_2,
IS_HSW_GT3(i915) ?
LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 96c398051084..332b8ffb58f8 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -611,8 +611,8 @@ static const struct drm_i915_reg_descriptor
gen7_render_regs[] = {
REG64(PS_INVOCATION_COUNT),
REG64(PS_DEPTH_COUNT),
REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
- REG64(MI_PREDICATE_SRC0),
- REG64(MI_PREDICATE_SRC1),
+ REG64_IDX(MI_PREDICATE_SRC0, RENDER_RING_BASE),
+ REG64_IDX(MI_PREDICATE_SRC1, RENDER_RING_BASE),
REG32(GEN7_3DPRIM_END_OFFSET),
REG32(GEN7_3DPRIM_START_VERTEX),
REG32(GEN7_3DPRIM_VERTEX_COUNT),
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 1253e396a911..547a242c5e49 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1684,7 +1684,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
stream, cs, true /* save */, CS_GPR(i),
INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
cs = save_restore_register(
- stream, cs, true /* save */, MI_PREDICATE_RESULT_1,
+ stream, cs, true /* save */,
MI_PREDICATE_RESULT_1(RENDER_RING_BASE),
INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
/* First timestamp snapshot location. */
@@ -1738,7 +1738,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
*/
*cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
*cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
- *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1);
+ *cs++ =
[Intel-gfx] [PATCH v2 3/6] drm/i915: Parameterize R_PWR_CLK_STATE register definition
At the moment we only use R_PWR_CLK_STATE in the context of the RCS
engine, but upcoming support for compute engines will start using
instances relative to the CCS engine base offsets. Let's parameterize
the register and move it to the engine reg header.
Cc: Jani Nikula
Signed-off-by: Matt Roper
---
.../gpu/drm/i915/gem/selftests/i915_gem_context.c | 3 ++-
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 15 +++
drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 15 ---
5 files changed, 20 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 80d99b9c694f..7cc4fa8f8c56 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -8,6 +8,7 @@
#include "gem/i915_gem_pm.h"
#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_requests.h"
#include "gt/intel_reset.h"
@@ -894,7 +895,7 @@ static int rpcs_query_batch(struct drm_i915_gem_object
*rpcs, struct i915_vma *v
return PTR_ERR(cmd);
*cmd++ = MI_STORE_REGISTER_MEM_GEN8;
- *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);
+ *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE));
*cmd++ = lower_32_bits(vma->node.start);
*cmd++ = upper_32_bits(vma->node.start);
*cmd = MI_BATCH_BUFFER_END;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
index 60511f310767..daf4a241cf77 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -77,6 +77,21 @@
#define RING_INSTPM(base) _MMIO((base) + 0xc0)
#define RING_CMD_CCTL(base)_MMIO((base) + 0xc4)
#define ACTHD(base)_MMIO((base) + 0xc8)
+#define GEN8_R_PWR_CLK_STATE(base) _MMIO((base) + 0xc8)
+#define GEN8_RPCS_ENABLE (1 << 31)
+#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
+#define GEN8_RPCS_S_CNT_SHIFT15
+#define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
+#define GEN11_RPCS_S_CNT_SHIFT 12
+#define GEN11_RPCS_S_CNT_MASK(0x3f <<
GEN11_RPCS_S_CNT_SHIFT)
+#define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
+#define GEN8_RPCS_SS_CNT_SHIFT 8
+#define GEN8_RPCS_SS_CNT_MASK(0x7 <<
GEN8_RPCS_SS_CNT_SHIFT)
+#define GEN8_RPCS_EU_MAX_SHIFT 4
+#define GEN8_RPCS_EU_MAX_MASK(0xf <<
GEN8_RPCS_EU_MAX_SHIFT)
+#define GEN8_RPCS_EU_MIN_SHIFT 0
+#define GEN8_RPCS_EU_MIN_MASK(0xf <<
GEN8_RPCS_EU_MIN_SHIFT)
+
#define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
#define RESET_CTL_CAT_ERROR REG_BIT(2)
#define RESET_CTL_READY_TO_RESET REG_BIT(1)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index bdf09051b8a0..f161087f30d0 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -4,7 +4,7 @@
*/
#include "i915_drv.h"
-#include "intel_lrc_reg.h"
+#include "intel_engine_regs.h"
#include "intel_sseu.h"
void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 804e87b6ed0c..1253e396a911 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2420,7 +2420,7 @@ gen12_configure_all_contexts(struct i915_perf_stream
*stream,
{
struct flex regs[] = {
{
- GEN8_R_PWR_CLK_STATE,
+ GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
CTX_R_PWR_CLK_STATE,
},
};
@@ -2440,7 +2440,7 @@ lrc_configure_all_contexts(struct i915_perf_stream
*stream,
#define ctx_flexeuN(N) (ctx_flexeu0 + 2 * (N) + 1)
struct flex regs[] = {
{
- GEN8_R_PWR_CLK_STATE,
+ GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
CTX_R_PWR_CLK_STATE,
},
{
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7f8f88904077..573dea4516ef 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -272,21 +272,6 @@
#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
#define GEN12_SFC_DONE_MAX 4
-#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
-#define GEN8_RPCS_ENABLE (1 << 31)
-#define
[Intel-gfx] [PATCH v2 6/6] drm/i915: Only include i915_reg.h from .c files
Several of our i915 header files, have been including i915_reg.h. This means that any change to i915_reg.h will trigger a full rebuild of pretty much every file of the driver, even those that don't have any kind of register access. Let's delete the i915_reg.h include from all headers and include an explicit include from the .c files that truly need the register definitions; those that need a definition of i915_reg_t for a function definition can get it from i915_reg_defs.h instead. We also remove two non-register #define's (VLV_DISPLAY_BASE and GEN12_SFC_DONE_MAX) into i915_reg_defs.h to allow us to drop the i915_reg.h include from a couple of headers. There's probably a lot more header dependency optimization possible, but the changes here roughly cut the number of files compiled after 'touch i915_reg.h' in half --- a good first step. Cc: Jani Nikula Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/g4x_hdmi.h | 2 +- drivers/gpu/drm/i915/display/intel_atomic.c | 1 + drivers/gpu/drm/i915/display/intel_bios.c | 1 + drivers/gpu/drm/i915/display/intel_bw.c | 1 + drivers/gpu/drm/i915/display/intel_crt.h | 2 +- drivers/gpu/drm/i915/display/intel_ddi.h | 2 +- drivers/gpu/drm/i915/display/intel_de.h | 1 - drivers/gpu/drm/i915/display/intel_display_power.h| 1 - drivers/gpu/drm/i915/display/intel_dmc.h | 2 +- drivers/gpu/drm/i915/display/intel_dp.h | 2 -- drivers/gpu/drm/i915/display/intel_dsb.h | 2 +- drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 1 + drivers/gpu/drm/i915/display/intel_dvo_dev.h | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.h | 2 -- drivers/gpu/drm/i915/display/intel_lvds.h | 2 +- drivers/gpu/drm/i915/display/intel_sdvo.h | 2 +- drivers/gpu/drm/i915/display/intel_tc.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 1 + drivers/gpu/drm/i915/gem/i915_gem_tiling.c| 1 + drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 1 + drivers/gpu/drm/i915/gt/intel_engine.h| 1 - drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 1 + drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c| 1 + drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 1 + drivers/gpu/drm/i915/gt/intel_llc.c | 1 + drivers/gpu/drm/i915/gt/intel_rc6.c | 1 + drivers/gpu/drm/i915/gt/intel_rc6.h | 2 +- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 1 + drivers/gpu/drm/i915/gt/intel_workarounds_types.h | 2 +- drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h | 1 - drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h| 2 +- drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 1 + drivers/gpu/drm/i915/gt/uc/intel_huc.h| 2 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 + drivers/gpu/drm/i915/gvt/aperture_gm.c| 1 + drivers/gpu/drm/i915/gvt/display.c| 1 + drivers/gpu/drm/i915/gvt/dmabuf.c | 1 + drivers/gpu/drm/i915/gvt/edid.c | 1 + drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 + drivers/gpu/drm/i915/gvt/handlers.c | 1 + drivers/gpu/drm/i915/gvt/interrupt.c | 1 + drivers/gpu/drm/i915/gvt/interrupt.h | 2 +- drivers/gpu/drm/i915/gvt/mmio.c | 1 + drivers/gpu/drm/i915/gvt/mmio_context.h | 1 - drivers/gpu/drm/i915/i915_cmd_parser.c| 1 + drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_perf_types.h| 2 +- drivers/gpu/drm/i915/i915_reg.h | 3 --- drivers/gpu/drm/i915/i915_reg_defs.h | 4 drivers/gpu/drm/i915/intel_dram.c | 1 + drivers/gpu/drm/i915/intel_pcode.c| 1 + drivers/gpu/drm/i915/intel_pm.h | 1 - drivers/gpu/drm/i915/intel_sbi.c | 1 + drivers/gpu/drm/i915/intel_uncore.h | 2 +- drivers/gpu/drm/i915/vlv_sideband.c | 1 + 56 files changed, 49 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.h b/drivers/gpu/drm/i915/display/g4x_hdmi.h index 7aca14b602c6..db9a93bc9321 100644 --- a/drivers/gpu/drm/i915/display/g4x_hdmi.h +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.h @@ -8,7 +8,7 @@ #include -#include "i915_reg.h" +#include "i915_reg_defs.h" enum port; struct drm_i915_private; diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c index 1080741d1561..093904065112 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.c +++ b/drivers/gpu/drm/i915/display/intel_atomic.c @@ -35,6
[Intel-gfx] [PATCH v2 0/6] Second round of i915_reg.h splitting
Let's continue to split our giant i915_reg.h file into more logical domain-specific headers. In addition to a bunch of register definition segregation, the final patch of this series ensures that i915_reg.h is only #include'd from .c files that truly need its definitions (and removes all of the places it was included by other headers). This significantly reduces how much of the driver code gets rebuilt after a modifications to i915_reg.h. There's still more work to do after this series (especially moving display registers to their own header(s)). We'll also need to do a lot of cleanup of the definitions themselves in a future series --- for now the definitions have mostly been moved to new locations as-is without modification to order, coding-style, etc. v2: - Drop 'inline' from reg_in_range_table() - Add missing #include to intel_pxp_irq.c Cc: Jani Nikula Cc: Lucas De Marchi Acked-by: Jani Nikula Matt Roper (6): drm/i915/perf: Move OA regs to their own header drm/i915/perf: Express OA register ranges with i915_range drm/i915: Parameterize R_PWR_CLK_STATE register definition drm/i915: Parameterize MI_PREDICATE registers drm/i915: Move GT registers to their own header file drm/i915: Only include i915_reg.h from .c files drivers/gpu/drm/i915/display/g4x_hdmi.h |2 +- drivers/gpu/drm/i915/display/intel_atomic.c |1 + drivers/gpu/drm/i915/display/intel_bios.c |1 + drivers/gpu/drm/i915/display/intel_bw.c |1 + drivers/gpu/drm/i915/display/intel_crt.h |2 +- drivers/gpu/drm/i915/display/intel_ddi.h |2 +- drivers/gpu/drm/i915/display/intel_de.h |1 - .../drm/i915/display/intel_display_power.h|1 - drivers/gpu/drm/i915/display/intel_dmc.h |2 +- drivers/gpu/drm/i915/display/intel_dp.h |2 - drivers/gpu/drm/i915/display/intel_dsb.h |2 +- drivers/gpu/drm/i915/display/intel_dsi_vbt.c |1 + drivers/gpu/drm/i915/display/intel_dvo_dev.h |2 +- drivers/gpu/drm/i915/display/intel_hdmi.h |2 - drivers/gpu/drm/i915/display/intel_lvds.h |2 +- drivers/gpu/drm/i915/display/intel_sdvo.h |2 +- drivers/gpu/drm/i915/display/intel_tc.c |1 + drivers/gpu/drm/i915/gem/i915_gem_stolen.c|1 + drivers/gpu/drm/i915/gem/i915_gem_tiling.c|1 + .../i915/gem/selftests/i915_gem_client_blt.c |3 +- .../drm/i915/gem/selftests/i915_gem_context.c |3 +- drivers/gpu/drm/i915/gt/gen2_engine_cs.c |1 + drivers/gpu/drm/i915/gt/gen6_ppgtt.c |1 + drivers/gpu/drm/i915/gt/gen7_renderclear.c|1 + drivers/gpu/drm/i915/gt/gen8_engine_cs.c |3 +- drivers/gpu/drm/i915/gt/intel_engine.h|1 - drivers/gpu/drm/i915/gt/intel_engine_cs.c |1 + drivers/gpu/drm/i915/gt/intel_engine_regs.h | 26 + .../drm/i915/gt/intel_execlists_submission.c |1 + drivers/gpu/drm/i915/gt/intel_ggtt.c |1 + drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c |2 + drivers/gpu/drm/i915/gt/intel_gt.c|3 +- .../gpu/drm/i915/gt/intel_gt_clock_utils.c|2 + drivers/gpu/drm/i915/gt/intel_gt_irq.c|2 +- drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c |2 + drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c |1 + drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1542 + drivers/gpu/drm/i915/gt/intel_gtt.c |1 + drivers/gpu/drm/i915/gt/intel_llc.c |1 + drivers/gpu/drm/i915/gt/intel_lrc.c |1 + drivers/gpu/drm/i915/gt/intel_mocs.c |2 +- drivers/gpu/drm/i915/gt/intel_rc6.c |2 + drivers/gpu/drm/i915/gt/intel_rc6.h |2 +- drivers/gpu/drm/i915/gt/intel_region_lmem.c |1 + drivers/gpu/drm/i915/gt/intel_reset.c |2 + .../gpu/drm/i915/gt/intel_ring_submission.c |1 + drivers/gpu/drm/i915/gt/intel_rps.c |1 + drivers/gpu/drm/i915/gt/intel_sseu.c |3 +- drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c |1 + drivers/gpu/drm/i915/gt/intel_workarounds.c |1 + .../gpu/drm/i915/gt/intel_workarounds_types.h |2 +- .../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h |1 - drivers/gpu/drm/i915/gt/uc/intel_guc.c|1 + drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c|1 + drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c |1 + drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h|2 +- drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c |2 + .../gpu/drm/i915/gt/uc/intel_guc_submission.c |1 + drivers/gpu/drm/i915/gt/uc/intel_huc.h|2 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c |1 + drivers/gpu/drm/i915/gvt/aperture_gm.c|1 + drivers/gpu/drm/i915/gvt/cmd_parser.c |1 + drivers/gpu/drm/i915/gvt/display.c|1 + drivers/gpu/drm/i915/gvt/dmabuf.c |1 + drivers/gpu/drm/i915/gvt/edid.c |1 + drivers/gpu/drm/i915/gvt/fb_decoder.c |1 +
[Intel-gfx] [PATCH 1/2] drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for reference
All timestamps returned by GuC for GuC PMU busyness are captured from
GUC PM TIMESTAMP. Since this timestamp does not tick when GuC goes idle,
kmd uses RING_TIMESTAMP to measure busyness of an engine with an active
context. In further stress testing, the MMIO read of the RING_TIMESTAMP
is seen to cause a rare hang. Resolve the issue by using gt specific
timestamp from PM which is in sync with the GuC PM timestamp.
Fixes: 77cdd054dd2c ("drm/i915/pmu: Connect engine busyness stats from GuC to
pmu")
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 5 ++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 56 ++-
drivers/gpu/drm/i915/i915_reg.h | 3 +-
3 files changed, 50 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index d59bbf49d1c2..697d9d66acef 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -215,6 +215,11 @@ struct intel_guc {
* context usage for overflows.
*/
struct delayed_work work;
+
+ /**
+* @shift: Right shift value for the gpm timestamp
+*/
+ u32 shift;
} timestamp;
#ifdef CONFIG_DRM_I915_SELFTEST
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 1331ff91c5b0..66760f5df0c1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1150,23 +1150,51 @@ static void guc_update_engine_gt_clks(struct
intel_engine_cs *engine)
}
}
-static void guc_update_pm_timestamp(struct intel_guc *guc,
- struct intel_engine_cs *engine,
- ktime_t *now)
+static u32 gpm_timestamp_shift(struct intel_gt *gt)
{
- u32 gt_stamp_now, gt_stamp_hi;
+ intel_wakeref_t wakeref;
+ u32 reg, shift;
+
+ with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+ reg = intel_uncore_read(gt->uncore, RPM_CONFIG0);
+
+ shift = (reg & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
+ GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT;
+
+ return 3 - shift;
+}
+
+static u64 gpm_timestamp(struct intel_gt *gt)
+{
+ u32 lo, hi, old_hi, loop = 0;
+
+ hi = intel_uncore_read(gt->uncore, MISC_STATUS1);
+ do {
+ lo = intel_uncore_read(gt->uncore, MISC_STATUS0);
+ old_hi = hi;
+ hi = intel_uncore_read(gt->uncore, MISC_STATUS1);
+ } while (old_hi != hi && loop++ < 2);
+
+ return ((u64)hi << 32) | lo;
+}
+
+static void guc_update_pm_timestamp(struct intel_guc *guc, ktime_t *now)
+{
+ struct intel_gt *gt = guc_to_gt(guc);
+ u32 gt_stamp_lo, gt_stamp_hi;
+ u64 gpm_ts;
lockdep_assert_held(>timestamp.lock);
gt_stamp_hi = upper_32_bits(guc->timestamp.gt_stamp);
- gt_stamp_now = intel_uncore_read(engine->uncore,
-RING_TIMESTAMP(engine->mmio_base));
+ gpm_ts = gpm_timestamp(gt) >> guc->timestamp.shift;
+ gt_stamp_lo = lower_32_bits(gpm_ts);
*now = ktime_get();
- if (gt_stamp_now < lower_32_bits(guc->timestamp.gt_stamp))
+ if (gt_stamp_lo < lower_32_bits(guc->timestamp.gt_stamp))
gt_stamp_hi++;
- guc->timestamp.gt_stamp = ((u64)gt_stamp_hi << 32) | gt_stamp_now;
+ guc->timestamp.gt_stamp = ((u64)gt_stamp_hi << 32) | gt_stamp_lo;
}
/*
@@ -1210,7 +1238,7 @@ static ktime_t guc_engine_busyness(struct intel_engine_cs
*engine, ktime_t *now)
stats_saved = *stats;
gt_stamp_saved = guc->timestamp.gt_stamp;
guc_update_engine_gt_clks(engine);
- guc_update_pm_timestamp(guc, engine, now);
+ guc_update_pm_timestamp(guc, now);
intel_gt_pm_put_async(gt);
if (i915_reset_count(gpu_error) != reset_count) {
*stats = stats_saved;
@@ -1242,8 +1270,8 @@ static void __reset_guc_busyness_stats(struct intel_guc
*guc)
spin_lock_irqsave(>timestamp.lock, flags);
+ guc_update_pm_timestamp(guc, );
for_each_engine(engine, gt, id) {
- guc_update_pm_timestamp(guc, engine, );
guc_update_engine_gt_clks(engine);
engine->stats.guc.prev_total = 0;
}
@@ -1260,10 +1288,11 @@ static void __update_guc_busyness_stats(struct
intel_guc *guc)
ktime_t unused;
spin_lock_irqsave(>timestamp.lock, flags);
- for_each_engine(engine, gt, id) {
- guc_update_pm_timestamp(guc, engine, );
+
+ guc_update_pm_timestamp(guc, );
+ for_each_engine(engine, gt, id)
guc_update_engine_gt_clks(engine);
- }
+
[Intel-gfx] [PATCH 2/2] drm/i915/pmu: Fix KMD and GuC race on accessing busyness
GuC updates shared memory and KMD reads it. Since this is not
synchronized, we run into a race where the value read is inconsistent.
Sometimes the inconsistency is in reading the upper MSB bytes of the
last_switch_in value. 2 types of cases are seen - upper 8 bits are zero
and upper 24 bits are zero. Since these are non-zero values, it is
not trivial to determine validity of these values. Instead we read the
values multiple times until they are consistent. In test runs, 3
attempts results in consistent values. The upper bound is set to 6
attempts and may need to be tuned as per any new occurences.
Since the duration that gt is parked can vary, the patch also updates
the gt timestamp on unpark before starting the worker.
v2:
- Initialize i
- Use READ_ONCE to access engine record
Fixes: 77cdd054dd2c ("drm/i915/pmu: Connect engine busyness stats from GuC to
pmu")
Signed-off-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 58 +--
1 file changed, 54 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 66760f5df0c1..75079e17e5b8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1114,6 +1114,19 @@ __extend_last_switch(struct intel_guc *guc, u64
*prev_start, u32 new_start)
if (new_start == lower_32_bits(*prev_start))
return;
+ /*
+* When gt is unparked, we update the gt timestamp and start the ping
+* worker that updates the gt_stamp every POLL_TIME_CLKS. As long as gt
+* is unparked, all switched in contexts will have a start time that is
+* within +/- POLL_TIME_CLKS of the most recent gt_stamp.
+*
+* If neither gt_stamp nor new_start has rolled over, then the
+* gt_stamp_hi does not need to be adjusted, however if one of them has
+* rolled over, we need to adjust gt_stamp_hi accordingly.
+*
+* The below conditions address the cases of new_start rollover and
+* gt_stamp_last rollover respectively.
+*/
if (new_start < gt_stamp_last &&
(new_start - gt_stamp_last) <= POLL_TIME_CLKS)
gt_stamp_hi++;
@@ -1125,17 +1138,45 @@ __extend_last_switch(struct intel_guc *guc, u64
*prev_start, u32 new_start)
*prev_start = ((u64)gt_stamp_hi << 32) | new_start;
}
-static void guc_update_engine_gt_clks(struct intel_engine_cs *engine)
+/*
+ * GuC updates shared memory and KMD reads it. Since this is not synchronized,
+ * we run into a race where the value read is inconsistent. Sometimes the
+ * inconsistency is in reading the upper MSB bytes of the last_in value when
+ * this race occurs. 2 types of cases are seen - upper 8 bits are zero and
upper
+ * 24 bits are zero. Since these are non-zero values, it is non-trivial to
+ * determine validity of these values. Instead we read the values multiple
times
+ * until they are consistent. In test runs, 3 attempts results in consistent
+ * values. The upper bound is set to 6 attempts and may need to be tuned as per
+ * any new occurences.
+ */
+static void __get_engine_usage_record(struct intel_engine_cs *engine,
+ u32 *last_in, u32 *id, u32 *total)
{
struct guc_engine_usage_record *rec = intel_guc_engine_usage(engine);
+ int i = 0;
+
+ do {
+ *last_in = READ_ONCE(rec->last_switch_in_stamp);
+ *id = READ_ONCE(rec->current_context_index);
+ *total = READ_ONCE(rec->total_runtime);
+
+ if (READ_ONCE(rec->last_switch_in_stamp) == *last_in &&
+ READ_ONCE(rec->current_context_index) == *id &&
+ READ_ONCE(rec->total_runtime) == *total)
+ break;
+ } while (++i < 6);
+}
+
+static void guc_update_engine_gt_clks(struct intel_engine_cs *engine)
+{
struct intel_engine_guc_stats *stats = >stats.guc;
struct intel_guc *guc = >gt->uc.guc;
- u32 last_switch = rec->last_switch_in_stamp;
- u32 ctx_id = rec->current_context_index;
- u32 total = rec->total_runtime;
+ u32 last_switch, ctx_id, total;
lockdep_assert_held(>timestamp.lock);
+ __get_engine_usage_record(engine, _switch, _id, );
+
stats->running = ctx_id != ~0U && last_switch;
if (stats->running)
__extend_last_switch(guc, >start_gt_clk, last_switch);
@@ -1237,6 +1278,10 @@ static ktime_t guc_engine_busyness(struct
intel_engine_cs *engine, ktime_t *now)
if (!in_reset && intel_gt_pm_get_if_awake(gt)) {
stats_saved = *stats;
gt_stamp_saved = guc->timestamp.gt_stamp;
+ /*
+* Update gt_clks, then gt timestamp to simplify the 'gt_stamp -
+* start_gt_clk' calculation below for active engines.
+*/
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/rpl-s: Add stepping info (rev3)
== Series Details ==
Series: drm/i915/rpl-s: Add stepping info (rev3)
URL : https://patchwork.freedesktop.org/series/99162/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22092
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22092 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22092, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22092/index.html
Participating hosts (51 -> 43)
--
Additional (1): fi-pnv-d510
Missing(9): shard-tglu fi-hsw-4200u fi-icl-u2 fi-bsw-cyan fi-ctg-p8600
shard-rkl shard-dg1 bat-jsl-2 fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22092:
### IGT changes ###
Possible regressions
* igt@gem_exec_suspend@basic-s0@smem:
- fi-glk-dsi: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-glk-dsi/igt@gem_exec_suspend@basic...@smem.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22092/fi-glk-dsi/igt@gem_exec_suspend@basic...@smem.html
Known issues
Here are the changes found in Patchwork_22092 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#109315]) +17
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22092/fi-hsw-4770/igt@amdgpu/amd_ba...@semaphore.html
* igt@gem_huc_copy@huc-copy:
- fi-pnv-d510:NOTRUN -> [SKIP][4] ([fdo#109271]) +39 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22092/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html
* igt@i915_selftest@live@hangcheck:
- fi-ivb-3770:[PASS][5] -> [INCOMPLETE][6] ([i915#3303])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-ivb-3770/igt@i915_selftest@l...@hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22092/fi-ivb-3770/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][7] ([i915#2927] / [i915#4528])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22092/fi-pnv-d510/igt@i915_selftest@l...@requests.html
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][8] ([fdo#109271] / [i915#2403] /
[i915#4312])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22092/fi-pnv-d510/igt@run...@aborted.html
- fi-ivb-3770:NOTRUN -> [FAIL][9] ([fdo#109271] / [i915#4312])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22092/fi-ivb-3770/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}: [DMESG-FAIL][10] ([i915#541]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22092/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
- fi-bsw-kefka: [DMESG-FAIL][12] ([i915#541]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22092/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][14] -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22092/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
- fi-hsw-4770:[INCOMPLETE][16] ([i915#3303]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22092/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4528]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/rpl-s: Add stepping info (rev2)
== Series Details ==
Series: drm/i915/rpl-s: Add stepping info (rev2)
URL : https://patchwork.freedesktop.org/series/99162/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22091
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22091/index.html
Participating hosts (51 -> 42)
--
Missing(9): shard-tglu fi-hsw-4200u fi-icl-u2 fi-bsw-cyan fi-ctg-p8600
shard-rkl shard-dg1 bat-jsl-2 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_22091 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: [PASS][1] -> [INCOMPLETE][2] ([i915#4547])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22091/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}: [DMESG-FAIL][3] ([i915#541]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22091/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
- fi-bsw-kefka: [DMESG-FAIL][5] ([i915#541]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22091/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [DMESG-FAIL][7] ([i915#4494]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22091/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
Warnings
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][9] -> [DMESG-FAIL][10] ([i915#4494] /
[i915#4957])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22091/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
- fi-hsw-4770:[INCOMPLETE][11] ([i915#3303]) -> [INCOMPLETE][12]
([i915#4785])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22091/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Build changes
-
* Linux: CI_DRM_11129 -> Patchwork_22091
CI-20190529: 20190529
CI_DRM_11129: 0b83d3cf9f9eab03ec804d56ac2686320a64f3ee @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6330: f73008bac9a8db0779264b170f630483e9165764 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22091: ae8b0b24992ae00c8ee4a71e05302f26135912ab @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ae8b0b24992a drm/i915/rpl-s: Add stepping info
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22091/index.html
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/rpl-s: Add stepping info (rev3)
== Series Details == Series: drm/i915/rpl-s: Add stepping info (rev3) URL : https://patchwork.freedesktop.org/series/99162/ State : warning == Summary == $ dim checkpatch origin/drm-tip adb56d9bb11b drm/i915/rpl-s: Add stepping info -:38: CHECK:LINE_SPACING: Please don't use multiple blank lines #38: FILE: drivers/gpu/drm/i915/intel_step.c:137: + total: 0 errors, 0 warnings, 1 checks, 27 lines checked
Re: [Intel-gfx] [v2] drm/i915/rpl-s: Add stepping info
> -Original Message-
> From: Roper, Matthew D
> Sent: Monday, January 24, 2022 5:06 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v2] drm/i915/rpl-s: Add stepping info
>
> On Mon, Jan 24, 2022 at 04:16:35PM -0800, Anusha Srivatsa wrote:
> > Add stepping-substepping info in
> > accordance to BSpec changes.
> > Though it looks weird, the revision ID for the newer stepping is
> > indeed backwards and is in accordance to the spec.
> >
> > v2: Rearrange the platforms in logical order (Matt)
> >
> > Bspec: 53655
> > Cc: Roper, Matthew D
>
> Git tools like send-email get very confused when they try to parse "Last,
> First" name ordering. It's best to use "First Last" with no comma to avoid
> problems.
Yeah, realized it immediately after hitting send :-/
> > Signed-off-by: Anusha Srivatsa
> > ---
> > drivers/gpu/drm/i915/intel_step.c | 9 +
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_step.c
> > b/drivers/gpu/drm/i915/intel_step.c
> > index a4b16b9e2e55..be055eb0b610 100644
> > --- a/drivers/gpu/drm/i915/intel_step.c
> > +++ b/drivers/gpu/drm/i915/intel_step.c
> > @@ -122,6 +122,11 @@ static const struct intel_step_info
> dg2_g11_revid_step_tbl[] = {
> > [0x5] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 },
> };
> >
> > +static const struct intel_step_info adls_rpls_revids[] = {
> > + [0x4] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_D0 },
> > + [0xC] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_C0 },
> };
> > +
> > void intel_step_init(struct drm_i915_private *i915) {
> > const struct intel_step_info *revids = NULL; @@ -129,6 +134,7 @@
> > void intel_step_init(struct drm_i915_private *i915)
> > int revid = INTEL_REVID(i915);
> > struct intel_step_info step = {};
> >
> > +
>
> Unwanted extra line here, but we can just fix that up (and the cc line
> above) while applying the patch.
>
> Reviewed-by: Matt Roper
Thanks!
Anusha
> > if (IS_DG2_G10(i915)) {
> > revids = dg2_g10_revid_step_tbl;
> > size = ARRAY_SIZE(dg2_g10_revid_step_tbl);
> > @@ -141,6 +147,9 @@ void intel_step_init(struct drm_i915_private *i915)
> > } else if (IS_ALDERLAKE_P(i915)) {
> > revids = adlp_revids;
> > size = ARRAY_SIZE(adlp_revids);
> > + } else if (IS_ADLS_RPLS(i915)) {
> > +revids = adls_rpls_revids;
> > +size = ARRAY_SIZE(adls_rpls_revids);
> > } else if (IS_ALDERLAKE_S(i915)) {
> > revids = adls_revids;
> > size = ARRAY_SIZE(adls_revids);
> > --
> > 2.25.1
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
Re: [Intel-gfx] [v2] drm/i915/rpl-s: Add stepping info
On Mon, Jan 24, 2022 at 04:16:35PM -0800, Anusha Srivatsa wrote:
> Add stepping-substepping info in
> accordance to BSpec changes.
> Though it looks weird, the revision ID
> for the newer stepping is indeed backwards
> and is in accordance to the spec.
>
> v2: Rearrange the platforms in logical order (Matt)
>
> Bspec: 53655
> Cc: Roper, Matthew D
Git tools like send-email get very confused when they try to parse
"Last, First" name ordering. It's best to use "First Last" with no
comma to avoid problems.
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/intel_step.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_step.c
> b/drivers/gpu/drm/i915/intel_step.c
> index a4b16b9e2e55..be055eb0b610 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -122,6 +122,11 @@ static const struct intel_step_info
> dg2_g11_revid_step_tbl[] = {
> [0x5] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 },
> };
>
> +static const struct intel_step_info adls_rpls_revids[] = {
> + [0x4] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_D0 },
> + [0xC] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_C0 },
> +};
> +
> void intel_step_init(struct drm_i915_private *i915)
> {
> const struct intel_step_info *revids = NULL;
> @@ -129,6 +134,7 @@ void intel_step_init(struct drm_i915_private *i915)
> int revid = INTEL_REVID(i915);
> struct intel_step_info step = {};
>
> +
Unwanted extra line here, but we can just fix that up (and the cc line
above) while applying the patch.
Reviewed-by: Matt Roper
> if (IS_DG2_G10(i915)) {
> revids = dg2_g10_revid_step_tbl;
> size = ARRAY_SIZE(dg2_g10_revid_step_tbl);
> @@ -141,6 +147,9 @@ void intel_step_init(struct drm_i915_private *i915)
> } else if (IS_ALDERLAKE_P(i915)) {
> revids = adlp_revids;
> size = ARRAY_SIZE(adlp_revids);
> + } else if (IS_ADLS_RPLS(i915)) {
> +revids = adls_rpls_revids;
> +size = ARRAY_SIZE(adls_rpls_revids);
> } else if (IS_ALDERLAKE_S(i915)) {
> revids = adls_revids;
> size = ARRAY_SIZE(adls_revids);
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
[Intel-gfx] [RESEND] drm/i915/rpl-s: Add stepping info
Add stepping-substepping info in
accordance to BSpec changes.
Though it looks weird, the revision ID
for the newer stepping is indeed backwards
and is in accordance to the spec.
v2: Rearrange the platforms in logical order (Matt)
Bspec: 53655
Cc: Roper, Matthew D
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_step.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index a4b16b9e2e55..9012e4b76a49 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -122,6 +122,11 @@ static const struct intel_step_info
dg2_g11_revid_step_tbl[] = {
[0x5] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 },
};
+static const struct intel_step_info adls_rpls_revids[] = {
+ [0x4] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_D0 },
+ [0xC] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_C0 },
+};
+
void intel_step_init(struct drm_i915_private *i915)
{
const struct intel_step_info *revids = NULL;
@@ -129,6 +134,7 @@ void intel_step_init(struct drm_i915_private *i915)
int revid = INTEL_REVID(i915);
struct intel_step_info step = {};
+
if (IS_DG2_G10(i915)) {
revids = dg2_g10_revid_step_tbl;
size = ARRAY_SIZE(dg2_g10_revid_step_tbl);
@@ -141,6 +147,9 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_ALDERLAKE_P(i915)) {
revids = adlp_revids;
size = ARRAY_SIZE(adlp_revids);
+ } else if (IS_ADLS_RPLS(i915)) {
+ revids = adls_rpls_revids;
+ size = ARRAY_SIZE(adls_rpls_revids);
} else if (IS_ALDERLAKE_S(i915)) {
revids = adls_revids;
size = ARRAY_SIZE(adls_revids);
--
2.25.1
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/rpl-s: Add stepping info (rev2)
== Series Details == Series: drm/i915/rpl-s: Add stepping info (rev2) URL : https://patchwork.freedesktop.org/series/99162/ State : warning == Summary == $ dim checkpatch origin/drm-tip ae8b0b24992a drm/i915/rpl-s: Add stepping info -:38: CHECK:LINE_SPACING: Please don't use multiple blank lines #38: FILE: drivers/gpu/drm/i915/intel_step.c:137: + -:47: ERROR:CODE_INDENT: code indent should use tabs where possible #47: FILE: drivers/gpu/drm/i915/intel_step.c:151: +revids = adls_rpls_revids;$ -:47: WARNING:LEADING_SPACE: please, no spaces at the start of a line #47: FILE: drivers/gpu/drm/i915/intel_step.c:151: +revids = adls_rpls_revids;$ -:48: ERROR:CODE_INDENT: code indent should use tabs where possible #48: FILE: drivers/gpu/drm/i915/intel_step.c:152: +size = ARRAY_SIZE(adls_rpls_revids);$ -:48: WARNING:LEADING_SPACE: please, no spaces at the start of a line #48: FILE: drivers/gpu/drm/i915/intel_step.c:152: +size = ARRAY_SIZE(adls_rpls_revids);$ total: 2 errors, 2 warnings, 1 checks, 27 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate
== Series Details ==
Series: series starting with [1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where
appropriate
URL : https://patchwork.freedesktop.org/series/99278/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22089
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/index.html
Participating hosts (50 -> 44)
--
Additional (1): fi-pnv-d510
Missing(7): shard-tglu fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-kbl-8809g
shard-dg1 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_22089 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17
similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/fi-hsw-4770/igt@amdgpu/amd_ba...@semaphore.html
* igt@gem_huc_copy@huc-copy:
- fi-pnv-d510:NOTRUN -> [SKIP][2] ([fdo#109271]) +57 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html
* igt@i915_selftest@live:
- fi-skl-6600u: NOTRUN -> [FAIL][3] ([i915#4547])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/fi-skl-6600u/igt@i915_selft...@live.html
* igt@runner@aborted:
- fi-skl-6600u: NOTRUN -> [FAIL][4] ([i915#1436] / [i915#4312])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/fi-skl-6600u/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}: [DMESG-FAIL][5] ([i915#541]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
- fi-bsw-kefka: [DMESG-FAIL][7] ([i915#541]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][9] -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
- fi-hsw-4770:[INCOMPLETE][11] ([i915#3303]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
Warnings
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [DMESG-FAIL][13] ([i915#4494]) -> [DMESG-FAIL][14]
([i915#4494] / [i915#4957])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22089/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Build changes
-
* Linux: CI_DRM_11129 -> Patchwork_22089
CI-20190529: 20190529
CI_DRM_11129: 0b83d3cf9f9eab03ec804d56ac2686320a64f3ee @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6330: f73008bac9a8db0779264b170f630483e9165764 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22089: bb2df423a3f8a56bb754542a56eb5c148f8e3aa0 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
bb2df423a3f8 drm/i915: Introduce ilk_pch_pre_enable()
cf24e52f7816 drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate
== Logs ==
For more details see:
[Intel-gfx] ✗ Fi.CI.BUILD: failure for linux-next: manual merge of the drm-intel-gt tree with the drm-intel tree
== Series Details == Series: linux-next: manual merge of the drm-intel-gt tree with the drm-intel tree URL : https://patchwork.freedesktop.org/series/99294/ State : failure == Summary == Applying: linux-next: manual merge of the drm-intel-gt tree with the drm-intel tree error: sha1 information is lacking or useless (drivers/gpu/drm/i915/i915_gem_evict.h). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 linux-next: manual merge of the drm-intel-gt tree with the drm-intel tree When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".
[Intel-gfx] [v2] drm/i915/rpl-s: Add stepping info
Add stepping-substepping info in
accordance to BSpec changes.
Though it looks weird, the revision ID
for the newer stepping is indeed backwards
and is in accordance to the spec.
v2: Rearrange the platforms in logical order (Matt)
Bspec: 53655
Cc: Roper, Matthew D
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_step.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index a4b16b9e2e55..be055eb0b610 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -122,6 +122,11 @@ static const struct intel_step_info
dg2_g11_revid_step_tbl[] = {
[0x5] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 },
};
+static const struct intel_step_info adls_rpls_revids[] = {
+ [0x4] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_D0 },
+ [0xC] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_C0 },
+};
+
void intel_step_init(struct drm_i915_private *i915)
{
const struct intel_step_info *revids = NULL;
@@ -129,6 +134,7 @@ void intel_step_init(struct drm_i915_private *i915)
int revid = INTEL_REVID(i915);
struct intel_step_info step = {};
+
if (IS_DG2_G10(i915)) {
revids = dg2_g10_revid_step_tbl;
size = ARRAY_SIZE(dg2_g10_revid_step_tbl);
@@ -141,6 +147,9 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_ALDERLAKE_P(i915)) {
revids = adlp_revids;
size = ARRAY_SIZE(adlp_revids);
+ } else if (IS_ADLS_RPLS(i915)) {
+revids = adls_rpls_revids;
+size = ARRAY_SIZE(adls_rpls_revids);
} else if (IS_ALDERLAKE_S(i915)) {
revids = adls_revids;
size = ARRAY_SIZE(adls_revids);
--
2.25.1
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate
== Series Details == Series: series starting with [1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate URL : https://patchwork.freedesktop.org/series/99278/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate
== Series Details == Series: series starting with [1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate URL : https://patchwork.freedesktop.org/series/99278/ State : warning == Summary == $ dim checkpatch origin/drm-tip cf24e52f7816 drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate -:25: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #25: FILE: drivers/gpu/drm/i915/i915_drv.h:1467: +#define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \ IS_GEMINILAKE(dev_priv) || \ IS_KABYLAKE(dev_priv)) -:37: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #37: FILE: drivers/gpu/drm/i915/i915_drv.h:1481: +#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7) total: 0 errors, 0 warnings, 2 checks, 61 lines checked bb2df423a3f8 drm/i915: Introduce ilk_pch_pre_enable()
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Skip dsc readout if the transcoder is disabled
== Series Details ==
Series: series starting with [1/5] drm/i915: Skip dsc readout if the transcoder
is disabled
URL : https://patchwork.freedesktop.org/series/99276/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22088
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22088/index.html
Participating hosts (48 -> 44)
--
Missing(4): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22088:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@hangcheck:
- {fi-ehl-2}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22088/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html
Known issues
Here are the changes found in Patchwork_22088 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#109315]) +17
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22088/fi-hsw-4770/igt@amdgpu/amd_ba...@semaphore.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}: [DMESG-FAIL][4] ([i915#541]) -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22088/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
- fi-bsw-kefka: [DMESG-FAIL][6] ([i915#541]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22088/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][8] -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22088/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
- fi-hsw-4770:[INCOMPLETE][10] ([i915#3303]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22088/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
[i915#750]: https://gitlab.freedesktop.org/drm/intel/issues/750
Build changes
-
* Linux: CI_DRM_11129 -> Patchwork_22088
CI-20190529: 20190529
CI_DRM_11129: 0b83d3cf9f9eab03ec804d56ac2686320a64f3ee @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6330: f73008bac9a8db0779264b170f630483e9165764 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22088: a03ade7fb36b09b011ab38bde9f9bb0fead40d7c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a03ade7fb36b drm/i915: Move dsc/joiner enable into hsw_crtc_enable()
641def635453 drm/i915: Extract hsw_configure_cpu_transcoder()
0e6833221e18 drm/i915: Use per-device debugs for bigjoiner stuff
dae73ac4ae6a drm/i915: Simplify intel_dsc_source_support()
b783b841501d drm/i915: Skip dsc readout if the transcoder is disabled
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22088/index.html
[Intel-gfx] ✓ Fi.CI.BAT: success for Fix up request cancel (rev2)
== Series Details ==
Series: Fix up request cancel (rev2)
URL : https://patchwork.freedesktop.org/series/99173/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22087
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22087/index.html
Participating hosts (48 -> 43)
--
Missing(5): fi-hsw-4200u fi-bsw-cyan fi-icl-u2 fi-ctg-p8600 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_22087 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3@smem:
- fi-snb-2600:[PASS][1] -> [DMESG-WARN][2] ([i915#4913])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-snb-2600/igt@gem_exec_suspend@basic...@smem.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22087/fi-snb-2600/igt@gem_exec_suspend@basic...@smem.html
* igt@kms_psr@primary_page_flip:
- fi-skl-6600u: [PASS][3] -> [FAIL][4] ([i915#4547])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22087/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
* igt@runner@aborted:
- fi-skl-6600u: NOTRUN -> [FAIL][5] ([i915#4312])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22087/fi-skl-6600u/igt@run...@aborted.html
- fi-bdw-5557u: NOTRUN -> [FAIL][6] ([i915#2426] / [i915#4312])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22087/fi-bdw-5557u/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}: [DMESG-FAIL][7] ([i915#541]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22087/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
- fi-bsw-kefka: [DMESG-FAIL][9] ([i915#541]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22087/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [DMESG-FAIL][11] ([i915#4494]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22087/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
Warnings
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][13] -> [DMESG-FAIL][14] ([i915#4494])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22087/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
- fi-hsw-4770:[INCOMPLETE][15] ([i915#3303]) -> [INCOMPLETE][16]
([i915#4785])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22087/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4562]: https://gitlab.freedesktop.org/drm/intel/issues/4562
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
[i915#4913]: https://gitlab.freedesktop.org/drm/intel/issues/4913
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Build changes
-
* Linux: CI_DRM_11129 -> Patchwork_22087
CI-20190529: 20190529
CI_DRM_11129: 0b83d3cf9f9eab03ec804d56ac2686320a64f3ee @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6330: f73008bac9a8db0779264b170f630483e9165764 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22087: 8a5938d99c50adeced0139269015a91bc9ec126b @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8a5938d99c50 drm/i915/selftests: Set preemption timeout to zero in cancel reset
test
bebfc9866392 drm/i915/execlists: Fix execlists request cancellation corner case
f478dcc4fbab drm/i915/guc: Cancel requests immediately
[Intel-gfx] linux-next: manual merge of the drm-intel-gt tree with the drm-intel tree
Hi all,
Today's linux-next merge of the drm-intel-gt tree got a conflict in:
drivers/gpu/drm/i915/i915_drv.h
between commit:
2ef97818d3aa ("drm/i915: split out i915_gem_evict.h from i915_drv.h")
from the drm-intel tree and commit:
7e00897be8bf ("drm/i915: Add object locking to i915_gem_evict_for_node and
i915_gem_evict_something, v2.")
from the drm-intel-gt tree.
I fixed it up (I used the former and adde the following merge fix patch)
and can carry the fix as necessary. This is now fixed as far as linux-next
is concerned, but any non trivial conflicts should be mentioned to your
upstream maintainer when your tree is submitted for merging. You may
also want to consider cooperating with the maintainer of the conflicting
tree to minimise any particularly complex conflicts.
From: Stephen Rothwell
Date: Tue, 25 Jan 2022 09:44:44 +1100
Subject: [PATCH] merge fix for "drm/i915: split out i915_gem_evict.h from
i915_drv.h"
Signed-off-by: Stephen Rothwell
---
drivers/gpu/drm/i915/i915_gem_evict.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.h
b/drivers/gpu/drm/i915/i915_gem_evict.h
index d4478b6ad11b..bd6e78abd530 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.h
+++ b/drivers/gpu/drm/i915/i915_gem_evict.h
@@ -12,11 +12,13 @@ struct drm_mm_node;
struct i915_address_space;
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
+ struct i915_gem_ww_ctx *ww,
u64 min_size, u64 alignment,
unsigned long color,
u64 start, u64 end,
unsigned flags);
int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
+struct i915_gem_ww_ctx *ww,
struct drm_mm_node *node,
unsigned int flags);
int i915_gem_evict_vm(struct i915_address_space *vm);
--
2.34.1
But then I also needed due to commit:
6945c53bc712 ("drm/i915: Add locking to i915_gem_evict_vm(), v3.")
From: Stephen Rothwell
Date: Tue, 25 Jan 2022 09:51:55 +1100
Subject: [PATCH] extra merge fix for "drm/i915: split out i915_gem_evict.h from
i915_drv.h"
Signed-off-by: Stephen Rothwell
---
drivers/gpu/drm/i915/i915_gem_evict.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.h
b/drivers/gpu/drm/i915/i915_gem_evict.h
index bd6e78abd530..b7f8e9435b2c 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.h
+++ b/drivers/gpu/drm/i915/i915_gem_evict.h
@@ -21,6 +21,7 @@ int __must_check i915_gem_evict_for_node(struct
i915_address_space *vm,
struct i915_gem_ww_ctx *ww,
struct drm_mm_node *node,
unsigned int flags);
-int i915_gem_evict_vm(struct i915_address_space *vm);
+int i915_gem_evict_vm(struct i915_address_space *vm,
+ struct i915_gem_ww_ctx *ww);
#endif /* __I915_GEM_EVICT_H__ */
--
2.34.1
And then this due to commit
e849f7e70860 ("drm/i915: Call i915_gem_evict_vm in vm_fault_gtt to prevent
new ENOSPC errors, v2.")
(and the above commit)
From: Stephen Rothwell
Date: Tue, 25 Jan 2022 10:02:16 +1100
Subject: [PATCH] extra 2 merge fix for "drm/i915: split out i915_gem_evict.h
from i915_drv.h"
Signed-off-by: Stephen Rothwell
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 4afad1604a6a..a69787999d09 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -21,6 +21,7 @@
#include "i915_trace.h"
#include "i915_user_extensions.h"
#include "i915_gem_ttm.h"
+#include "i915_gem_evict.h"
#include "i915_vma.h"
static inline bool
--
2.34.1
--
Cheers,
Stephen Rothwell
pgpcUy7YKGP2P.pgp
Description: OpenPGP digital signature
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Fix up request cancel (rev2)
== Series Details == Series: Fix up request cancel (rev2) URL : https://patchwork.freedesktop.org/series/99173/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix up request cancel (rev2)
== Series Details == Series: Fix up request cancel (rev2) URL : https://patchwork.freedesktop.org/series/99173/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9d38a07fb177 drm/i915: Add request cancel low level trace point f478dcc4fbab drm/i915/guc: Cancel requests immediately bebfc9866392 drm/i915/execlists: Fix execlists request cancellation corner case -:85: CHECK:LINE_SPACING: Please don't use multiple blank lines #85: FILE: drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c:346: + + total: 0 errors, 0 warnings, 1 checks, 135 lines checked 8a5938d99c50 drm/i915/selftests: Set preemption timeout to zero in cancel reset test
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: make static read-only array page_count const
== Series Details ==
Series: drm/i915/selftests: make static read-only array page_count const
URL : https://patchwork.freedesktop.org/series/99252/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22085
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/index.html
Participating hosts (48 -> 45)
--
Additional (1): fi-pnv-d510
Missing(4): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Known issues
Here are the changes found in Patchwork_22085 that come from known issues:
### CI changes ###
Issues hit
* boot:
- fi-bxt-dsi: [PASS][1] -> [FAIL][2] ([i915#4912])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-bxt-dsi/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/fi-bxt-dsi/boot.html
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#109315]) +17
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/fi-hsw-4770/igt@amdgpu/amd_ba...@semaphore.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u: [PASS][4] -> [INCOMPLETE][5] ([i915#4547])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
- fi-bdw-5557u: [PASS][6] -> [INCOMPLETE][7] ([i915#146])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-pnv-d510:NOTRUN -> [SKIP][8] ([fdo#109271]) +57 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html
* igt@i915_selftest@live@late_gt_pm:
- fi-bsw-nick:[PASS][9] -> [DMESG-FAIL][10] ([i915#2927] /
[i915#3428])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
* igt@runner@aborted:
- fi-bsw-nick:NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#1436] /
[i915#3428] / [i915#4312])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/fi-bsw-nick/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}: [DMESG-FAIL][12] ([i915#541]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
- fi-bsw-kefka: [DMESG-FAIL][14] ([i915#541]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][16] ([i915#3303]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
Warnings
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][18] -> [DMESG-FAIL][19] ([i915#4494])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22085/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4912]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/overlay: Prevent divide by zero bugs in scaling
== Series Details == Series: drm/i915/overlay: Prevent divide by zero bugs in scaling URL : https://patchwork.freedesktop.org/series/99242/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11128_full -> Patchwork_22079_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22079_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22079_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (13 -> 10) -- Missing(3): shard-rkl shard-dg1 shard-tglu Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22079_full: ### IGT changes ### Possible regressions * igt@gem_create@create-massive: - shard-kbl: NOTRUN -> [DMESG-WARN][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/shard-kbl1/igt@gem_cre...@create-massive.html * igt@gem_userptr_blits@input-checking: - shard-skl: NOTRUN -> [DMESG-WARN][2] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/shard-skl8/igt@gem_userptr_bl...@input-checking.html - shard-apl: NOTRUN -> [DMESG-WARN][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/shard-apl4/igt@gem_userptr_bl...@input-checking.html * igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled: - shard-glk: [PASS][4] -> [FAIL][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11128/shard-glk5/igt@kms_draw_...@draw-method-rgb565-pwrite-untiled.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/shard-glk9/igt@kms_draw_...@draw-method-rgb565-pwrite-untiled.html Known issues Here are the changes found in Patchwork_22079_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@in-flight-contexts-10ms: - shard-skl: NOTRUN -> [TIMEOUT][6] ([i915#3063]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/shard-skl9/igt@gem_...@in-flight-contexts-10ms.html * igt@gem_eio@in-flight-contexts-immediate: - shard-tglb: [PASS][7] -> [TIMEOUT][8] ([i915#3063]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11128/shard-tglb8/igt@gem_...@in-flight-contexts-immediate.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/shard-tglb1/igt@gem_...@in-flight-contexts-immediate.html * igt@gem_exec_balancer@parallel-out-fence: - shard-iclb: [PASS][9] -> [SKIP][10] ([i915#4525]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11128/shard-iclb1/igt@gem_exec_balan...@parallel-out-fence.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/shard-iclb3/igt@gem_exec_balan...@parallel-out-fence.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11128/shard-iclb5/igt@gem_exec_fair@basic-none-sh...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/shard-iclb6/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-apl: [PASS][13] -> [FAIL][14] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11128/shard-apl4/igt@gem_exec_fair@basic-n...@vecs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/shard-apl8/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][15] -> [FAIL][16] ([i915#2842]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11128/shard-glk4/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/shard-glk3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-kbl: [PASS][17] -> [FAIL][18] ([i915#2842]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11128/shard-kbl3/igt@gem_exec_fair@basic-p...@vcs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/shard-kbl4/igt@gem_exec_fair@basic-p...@vcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][19] -> [FAIL][20] ([i915#2849]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11128/shard-iclb6/igt@gem_exec_fair@basic-throt...@rcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_whisper@basic-contexts-all: - shard-glk: [PASS][21] -> [DMESG-WARN][22] ([i915#118]) +1 similar issue [21]:
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Async flip optimization for DG2 (rev8)
== Series Details == Series: Async flip optimization for DG2 (rev8) URL : https://patchwork.freedesktop.org/series/98981/ State : failure == Summary == Applying: drm/i915: Pass plane to watermark calculation functions Applying: drm/i915: Introduce do_async_flip flag to intel_plane_state Applying: drm/i915: Use wm0 only during async flips for DG2 Applying: drm/i915: Don't allocate extra ddb during async flip for DG2 error: sha1 information is lacking or useless (drivers/gpu/drm/i915/intel_pm.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0004 drm/i915: Don't allocate extra ddb during async flip for DG2 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".
[Intel-gfx] linux-next: manual merge of the drm-intel tree with Linus' tree
Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in:
drivers/gpu/drm/i915/intel_pm.c
between commit:
cca084692394 ("drm/i915: Use per device iommu check")
from Linus' tree and commit:
8172375ea95a ("drm/i915: Remove zombie async flip vt-d w/a")
from the drm-intel tree.
I fixed it up (the latter removed the code modified by the former, so
I just did that) and can carry the fix as necessary. This is now fixed
as far as linux-next is concerned, but any non trivial conflicts should
be mentioned to your upstream maintainer when your tree is submitted for
merging. You may also want to consider cooperating with the maintainer
of the conflicting tree to minimise any particularly complex conflicts.
--
Cheers,
Stephen Rothwell
pgpnCh0SfU4dT.pgp
Description: OpenPGP digital signature
[Intel-gfx] linux-next: manual merge of the drm-intel tree with Linus' tree
Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in:
drivers/gpu/drm/i915/i915_reg.h
between commit:
77cdd054dd2c ("drm/i915/pmu: Connect engine busyness stats from GuC to pmu")
from Linus' tree and commit:
202b1f4c1234 ("drm/i915/gt: Move engine registers to their own header")
from the drm-intel tree.
I fixed it up (see below - maybe should be done better?) and can carry the
fix as necessary. This is now fixed as far as linux-next is concerned,
but any non trivial conflicts should be mentioned to your upstream
maintainer when your tree is submitted for merging. You may also want
to consider cooperating with the maintainer of the conflicting tree to
minimise any particularly complex conflicts.
--
Cheers,
Stephen Rothwell
diff --cc drivers/gpu/drm/i915/i915_reg.h
index 971d601fe751,cf168c3e0471..
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@@ -2661,52 -1825,7 +1843,9 @@@
#define AUX_INV REG_BIT(0)
#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
#define VEBOX_HWS_PGA_GEN7_MMIO(0x04380)
- #define RING_ACTHD(base) _MMIO((base) + 0x74)
- #define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
- #define RING_NOPID(base) _MMIO((base) + 0x94)
- #define RING_IMR(base)_MMIO((base) + 0xa8)
- #define RING_HWSTAM(base) _MMIO((base) + 0x98)
- #define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
- #define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
- #define TAIL_ADDR 0x0018
- #define HEAD_WRAP_COUNT 0xFFE0
- #define HEAD_WRAP_ONE 0x0020
- #define HEAD_ADDR 0x001C
- #define RING_NR_PAGES 0x001FF000
- #define RING_REPORT_MASK0x0006
- #define RING_REPORT_64K 0x0002
- #define RING_REPORT_128K0x0004
- #define RING_NO_REPORT 0x
- #define RING_VALID_MASK 0x0001
- #define RING_VALID 0x0001
- #define RING_INVALID0x
- #define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */
- #define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */
- #define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
+#define GUCPMTIMESTAMP _MMIO(0xC3E8)
+
- /* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
- #define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8)
- #define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4)
-
- #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
- #define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
- #define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28)/* CFL+ & Gen11+ */
- #define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28)
- #define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28)
- #define RING_FORCE_TO_NONPRIV_ACCESS_INVALID(3 << 28)
- #define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28)
- #define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ &
Gen11+ */
- #define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
- #define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
- #define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
- #define RING_FORCE_TO_NONPRIV_RANGE_MASK(3 << 0)
- #define RING_FORCE_TO_NONPRIV_MASK_VALID\
- (RING_FORCE_TO_NONPRIV_RANGE_MASK \
- | RING_FORCE_TO_NONPRIV_ACCESS_MASK)
- #define RING_MAX_NONPRIV_SLOTS 12
-
#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
@@@ -2778,27 -1885,7 +1905,10 @@@
#define GEN2_INSTDONE _MMIO(0x2090)
#define NOPID _MMIO(0x2094)
#define HWSTAM_MMIO(0x2098)
- #define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0)
- #define RING_BBSTATE(base)_MMIO((base) + 0x110)
- #define RING_BB_PPGTT (1 << 5)
- #define RING_SBBADDR(base)_MMIO((base) + 0x114) /* hsw+ */
- #define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */
- #define RING_SBBADDR_UDW(base)_MMIO((base) + 0x11c) /* gen8+ */
- #define RING_BBADDR(base) _MMIO((base) + 0x140)
- #define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */
- #define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */
- #define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+
*/
- #define RING_INDIRECT_CTX_OFFSET(base)_MMIO((base) + 0x1c8) /* gen8+
*/
- #define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */
-
- #define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10)
- #define IECPUNIT_CLKGATE_DISREG_BIT(22)
+#define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18)
+#define ALNUNIT_CLKGATE_DIS REG_BIT(13)
+
#define ERROR_GEN6_MMIO(0x40a0)
#define GEN7_ERR_INT _MMIO(0x44040)
#define ERR_INT_POISON (1 << 31)
pgpUvlxnhLXiA.pgp
Description:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: make static read-only array page_count const
== Series Details == Series: drm/i915/selftests: make static read-only array page_count const URL : https://patchwork.freedesktop.org/series/99252/ State : warning == Summary == $ dim checkpatch origin/drm-tip fb32ff7638fd drm/i915/selftests: make static read-only array page_count const -:24: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: Colin Ian King ' != 'Signed-off-by: Colin Ian King ' total: 0 errors, 1 warnings, 0 checks, 8 lines checked
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/11] drm/radeon: use ttm_resource_manager_debug
== Series Details == Series: series starting with [01/11] drm/radeon: use ttm_resource_manager_debug URL : https://patchwork.freedesktop.org/series/99249/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22083 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22083 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22083, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22083/index.html Participating hosts (48 -> 44) -- Missing(4): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22083: ### IGT changes ### Possible regressions * igt@gem_busy@busy@all: - fi-ilk-650: [PASS][1] -> [FAIL][2] +14 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-ilk-650/igt@gem_busy@b...@all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22083/fi-ilk-650/igt@gem_busy@b...@all.html - fi-snb-2520m: [PASS][3] -> [FAIL][4] +6 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-snb-2520m/igt@gem_busy@b...@all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22083/fi-snb-2520m/igt@gem_busy@b...@all.html * igt@gem_exec_fence@basic-await@bcs0: - fi-cml-u2: [PASS][5] -> [FAIL][6] +18 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-cml-u2/igt@gem_exec_fence@basic-aw...@bcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22083/fi-cml-u2/igt@gem_exec_fence@basic-aw...@bcs0.html * igt@gem_exec_fence@basic-await@vcs0: - fi-elk-e7500: [PASS][7] -> [FAIL][8] +12 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-elk-e7500/igt@gem_exec_fence@basic-aw...@vcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22083/fi-elk-e7500/igt@gem_exec_fence@basic-aw...@vcs0.html - fi-glk-j4005: [PASS][9] -> [FAIL][10] +18 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-glk-j4005/igt@gem_exec_fence@basic-aw...@vcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22083/fi-glk-j4005/igt@gem_exec_fence@basic-aw...@vcs0.html - fi-kbl-7567u: [PASS][11] -> [FAIL][12] +20 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-kbl-7567u/igt@gem_exec_fence@basic-aw...@vcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22083/fi-kbl-7567u/igt@gem_exec_fence@basic-aw...@vcs0.html * igt@gem_exec_fence@basic-await@vcs1: - fi-bdw-gvtdvm: [PASS][13] -> [FAIL][14] +20 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-bdw-gvtdvm/igt@gem_exec_fence@basic-aw...@vcs1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22083/fi-bdw-gvtdvm/igt@gem_exec_fence@basic-aw...@vcs1.html * igt@gem_exec_fence@basic-await@vecs0: - fi-kbl-guc: [PASS][15] -> [FAIL][16] +16 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-kbl-guc/igt@gem_exec_fence@basic-aw...@vecs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22083/fi-kbl-guc/igt@gem_exec_fence@basic-aw...@vecs0.html - fi-kbl-x1275: [PASS][17] -> [FAIL][18] +18 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-kbl-x1275/igt@gem_exec_fence@basic-aw...@vecs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22083/fi-kbl-x1275/igt@gem_exec_fence@basic-aw...@vecs0.html * igt@gem_exec_fence@basic-busy@rcs0: - fi-bsw-n3050: [PASS][19] -> [FAIL][20] +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-bsw-n3050/igt@gem_exec_fence@basic-b...@rcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22083/fi-bsw-n3050/igt@gem_exec_fence@basic-b...@rcs0.html - fi-bsw-nick:[PASS][21] -> [FAIL][22] +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-bsw-nick/igt@gem_exec_fence@basic-b...@rcs0.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22083/fi-bsw-nick/igt@gem_exec_fence@basic-b...@rcs0.html * igt@gem_exec_fence@basic-busy@vcs0: - fi-skl-6700k2: [PASS][23] -> [FAIL][24] +18 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-skl-6700k2/igt@gem_exec_fence@basic-b...@vcs0.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22083/fi-skl-6700k2/igt@gem_exec_fence@basic-b...@vcs0.html - fi-ivb-3770:[PASS][25] ->
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Add basic support for flat-CCS bo evictions
== Series Details == Series: Add basic support for flat-CCS bo evictions URL : https://patchwork.freedesktop.org/series/99248/ State : failure == Summary == Applying: drm/i915/flat-CCS: Add GEM bo structure fields for flat-CCS Applying: drm/i915/flat-CCS: Add flat CCS plane capabilities and modifiers Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_fb.c M drivers/gpu/drm/i915/display/intel_fb.h Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/display/intel_fb.h CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_fb.h Auto-merging drivers/gpu/drm/i915/display/intel_fb.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_fb.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0002 drm/i915/flat-CCS: Add flat CCS plane capabilities and modifiers When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/11] drm/radeon: use ttm_resource_manager_debug
== Series Details == Series: series starting with [01/11] drm/radeon: use ttm_resource_manager_debug URL : https://patchwork.freedesktop.org/series/99249/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/11] drm/radeon: use ttm_resource_manager_debug
== Series Details == Series: series starting with [01/11] drm/radeon: use ttm_resource_manager_debug URL : https://patchwork.freedesktop.org/series/99249/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5647bdbd9dd6 dma-buf: consolidate dma_fence subclass checking -:117: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: "Christian König" ' != 'Signed-off-by: Christian König ' total: 0 errors, 1 warnings, 0 checks, 84 lines checked da6a598d08b2 dma-buf: warn about dma_fence_array container rules v2 -:44: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: "Christian König" ' != 'Signed-off-by: Christian König ' total: 0 errors, 1 warnings, 0 checks, 20 lines checked edbef78ca254 dma-buf: Warn about dma_fence_chain container rules v2 -:38: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: "Christian König" ' != 'Signed-off-by: Christian König ' total: 0 errors, 1 warnings, 0 checks, 14 lines checked ece7651171f3 dma-buf: warn about containers in dma_resv object -:31: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: "Christian König" ' != 'Signed-off-by: Christian König ' total: 0 errors, 1 warnings, 0 checks, 11 lines checked dfa23eb99c11 dma-buf: Add dma_fence_array_for_each (v2) -:75: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'fence' - possible side-effects? #75: FILE: include/linux/dma-fence-array.h:73: +#define dma_fence_array_for_each(fence, index, head) \ + for (index = 0, fence = dma_fence_array_first(head); fence; \ +++(index), fence = dma_fence_array_next(head, index)) -:75: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects? #75: FILE: include/linux/dma-fence-array.h:73: +#define dma_fence_array_for_each(fence, index, head) \ + for (index = 0, fence = dma_fence_array_first(head); fence; \ +++(index), fence = dma_fence_array_next(head, index)) -:75: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'head' - possible side-effects? #75: FILE: include/linux/dma-fence-array.h:73: +#define dma_fence_array_for_each(fence, index, head) \ + for (index = 0, fence = dma_fence_array_first(head); fence; \ +++(index), fence = dma_fence_array_next(head, index)) -:90: ERROR:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author '"Christian König" ' total: 1 errors, 0 warnings, 3 checks, 57 lines checked bef780ab04c3 dma-buf: add dma_fence_chain_contained helper -:64: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: "Christian König" ' != 'Signed-off-by: Christian König ' total: 0 errors, 1 warnings, 0 checks, 39 lines checked 51cb2edeadac drm/amdgpu: use dma_fence_chain_contained -:29: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: "Christian König" ' != 'Signed-off-by: Christian König ' total: 0 errors, 1 warnings, 0 checks, 12 lines checked 5b0a478c7391 drm/i915: use dma_fence extractor functions -:235: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: "Christian König" ' != 'Signed-off-by: Christian König ' total: 0 errors, 1 warnings, 0 checks, 197 lines checked 8a7ed5aee675 drm/vmwgfx: remove vmw_wait_dma_fence -:101: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: "Christian König" ' != 'Signed-off-by: Christian König ' total: 0 errors, 1 warnings, 0 checks, 69 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/edid: Support type 7 timings
== Series Details ==
Series: drm/edid: Support type 7 timings
URL : https://patchwork.freedesktop.org/series/99250/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22082
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/index.html
Participating hosts (48 -> 42)
--
Missing(6): fi-hsw-4200u fi-bsw-cyan fi-snb-2520m fi-ctg-p8600 bat-jsl-2
fi-bdw-samus
Known issues
Here are the changes found in Patchwork_22082 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17
similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/fi-hsw-4770/igt@amdgpu/amd_ba...@semaphore.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-bdw-5557u: [PASS][2] -> [INCOMPLETE][3] ([i915#146])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: [PASS][4] -> [FAIL][5] ([i915#4547])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
* igt@runner@aborted:
- fi-skl-6600u: NOTRUN -> [FAIL][6] ([i915#4312])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/fi-skl-6600u/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}: [DMESG-FAIL][7] ([i915#541]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
- fi-bsw-kefka: [DMESG-FAIL][9] ([i915#541]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
- fi-hsw-4770:[INCOMPLETE][13] ([i915#3303]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
Warnings
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [DMESG-FAIL][15] ([i915#4494]) -> [DMESG-FAIL][16]
([i915#4494] / [i915#4957])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22082/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Build changes
-
* Linux: CI_DRM_11129 -> Patchwork_22082
CI-20190529: 20190529
CI_DRM_11129: 0b83d3cf9f9eab03ec804d56ac2686320a64f3ee @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6330: f73008bac9a8db0779264b170f630483e9165764 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22082: 9735d3ddba6d11ae273018b5b11eda91924bcc7e @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9735d3ddba6d drm/edid: Support type 7 timings
== Logs ==
For more details see:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/edid: Support type 7 timings
== Series Details == Series: drm/edid: Support type 7 timings URL : https://patchwork.freedesktop.org/series/99250/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9735d3ddba6d drm/edid: Support type 7 timings -:24: WARNING:LONG_LINE: line length of 105 exceeds 100 columns #24: FILE: drivers/gpu/drm/drm_edid.c:5443: + struct displayid_detailed_timings_1 *timings, total: 0 errors, 1 warnings, 0 checks, 42 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Fix NULL vs IS_ERR checking for kernel_context (rev2)
== Series Details ==
Series: drm/i915/selftests: Fix NULL vs IS_ERR checking for kernel_context
(rev2)
URL : https://patchwork.freedesktop.org/series/98685/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22081
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/index.html
Participating hosts (48 -> 43)
--
Additional (1): fi-pnv-d510
Missing(6): fi-hsw-4200u fi-bsw-cyan fi-icl-u2 fi-ctg-p8600 bat-jsl-2
fi-bdw-samus
Known issues
Here are the changes found in Patchwork_22081 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17
similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/fi-hsw-4770/igt@amdgpu/amd_ba...@semaphore.html
* igt@gem_huc_copy@huc-copy:
- fi-pnv-d510:NOTRUN -> [SKIP][2] ([fdo#109271]) +57 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html
* igt@i915_selftest@live:
- fi-skl-6600u: NOTRUN -> [FAIL][3] ([i915#4547])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/fi-skl-6600u/igt@i915_selft...@live.html
* igt@runner@aborted:
- fi-skl-6600u: NOTRUN -> [FAIL][4] ([i915#1436] / [i915#4312])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/fi-skl-6600u/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}: [DMESG-FAIL][5] ([i915#541]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
- fi-bsw-kefka: [DMESG-FAIL][7] ([i915#541]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [DMESG-FAIL][9] ([i915#4494]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
- fi-hsw-4770:[INCOMPLETE][11] ([i915#3303]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
Warnings
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][13] -> [DMESG-FAIL][14] ([i915#4494])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Build changes
-
* Linux: CI_DRM_11129 -> Patchwork_22081
CI-20190529: 20190529
CI_DRM_11129: 0b83d3cf9f9eab03ec804d56ac2686320a64f3ee @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6330: f73008bac9a8db0779264b170f630483e9165764 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22081: 98230459e3fca1681d65097e961e2ca374e39bac @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
98230459e3fc drm/i915/selftests: Fix NULL vs IS_ERR checking for kernel_context
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22081/index.html
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Lock dpt_obj around set_cache_level.
== Series Details ==
Series: drm/i915: Lock dpt_obj around set_cache_level.
URL : https://patchwork.freedesktop.org/series/99245/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22080
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22080 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22080, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/index.html
Participating hosts (48 -> 43)
--
Missing(5): fi-hsw-4200u fi-bsw-cyan fi-icl-u2 fi-ctg-p8600 fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22080:
### IGT changes ###
Possible regressions
* igt@gem_sync@basic-each:
- fi-skl-6600u: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-skl-6600u/igt@gem_s...@basic-each.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/fi-skl-6600u/igt@gem_s...@basic-each.html
* igt@kms_busy@basic@modeset:
- bat-adlp-4: NOTRUN -> [DMESG-WARN][3] +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/bat-adlp-4/igt@kms_busy@ba...@modeset.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_busy@basic@flip:
- {bat-adlp-6}: NOTRUN -> [DMESG-WARN][4] +1 similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/bat-adlp-6/igt@kms_busy@ba...@flip.html
Known issues
Here are the changes found in Patchwork_22080 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#109315]) +17
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/fi-hsw-4770/igt@amdgpu/amd_ba...@semaphore.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u: [PASS][6] -> [FAIL][7] ([fdo#103375])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
* igt@runner@aborted:
- fi-skl-6600u: NOTRUN -> [FAIL][8] ([i915#2722] / [i915#4312])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/fi-skl-6600u/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}: [DMESG-FAIL][9] ([i915#541]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
- fi-bsw-kefka: [DMESG-FAIL][11] ([i915#541]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][13] ([i915#3303]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling:
- bat-adlp-4: [DMESG-WARN][15] -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-adlp-4/igt@kms_addfb_ba...@addfb25-framebuffer-vs-set-tiling.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/bat-adlp-4/igt@kms_addfb_ba...@addfb25-framebuffer-vs-set-tiling.html
- {bat-adlp-6}: [DMESG-WARN][17] -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-adlp-6/igt@kms_addfb_ba...@addfb25-framebuffer-vs-set-tiling.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/bat-adlp-6/igt@kms_addfb_ba...@addfb25-framebuffer-vs-set-tiling.html
Warnings
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][19] -> [DMESG-FAIL][20] ([i915#4494])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22080/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it
Re: [Intel-gfx] [PATCH 01/11] drm/radeon: use ttm_resource_manager_debug
Am 24.01.22 um 17:33 schrieb Thomas Hellström: On Mon, 2022-01-24 at 14:03 +0100, Christian König wrote: Instead of calling the debug operation directly. Signed-off-by: Christian König Reviewed-by: Huang Rui The first two patches seem unrelated to the series. No idea what happened here, those two are already upstream. I probably just forgot to pull drm-misc-next changes from a different system. Also is there a chance of a series cover-letter? Going to add one the next time, but I though it would be pretty clear what this is now about. Thanks, Christian. Thanks, Thomas --- drivers/gpu/drm/radeon/radeon_ttm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 11b21d605584..0d1283cdc8fb 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -802,7 +802,7 @@ static int radeon_mm_vram_dump_table_show(struct seq_file *m, void *unused) TTM_PL_VRAM); struct drm_printer p = drm_seq_file_printer(m); - man->func->debug(man, ); + ttm_resource_manager_debug(man, ); return 0; } @@ -820,7 +820,7 @@ static int radeon_mm_gtt_dump_table_show(struct seq_file *m, void *unused) TTM_PL_TT); struct drm_printer p = drm_seq_file_printer(m); - man->func->debug(man, ); + ttm_resource_manager_debug(man, ); return 0; }
Re: [Intel-gfx] [PATCH 06/11] dma-buf: warn about containers in dma_resv object
Am 24.01.22 um 17:36 schrieb Thomas Hellström (Intel): On 1/24/22 14:03, Christian König wrote: Drivers should not add containers as shared fences to the dma_resv object, instead each fence should be added individually. Signed-off-by: Christian König Reviewed-by: Daniel Vetter Reviewed-by: Thomas Hellström Is there any indication that this triggers on existing drivers? There used to be a case in amdgpu which triggered this, but at least I'm not aware of any in the current code. Christian. Thomas
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Lock dpt_obj around set_cache_level.
== Series Details == Series: drm/i915: Lock dpt_obj around set_cache_level. URL : https://patchwork.freedesktop.org/series/99245/ State : warning == Summary == $ dim checkpatch origin/drm-tip f8d0f6b03553 drm/i915: Lock dpt_obj around set_cache_level. -:8: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #8: <6> [184.578145] [IGT] kms_addfb_basic: starting subtest addfb25-framebuffer-vs-set-tiling total: 0 errors, 1 warnings, 0 checks, 12 lines checked
Re: [Intel-gfx] [PATCH 2/7] drm/i915/guc: Add XE_LP registers for GuC error state capture.
Internal feedback is to exactly match the register dumps
output as it did in execlist, however it seems that the
register dump function in execlist targetting the GT subsystem
also includes non-GT registers like display-related ones that
GuC doesn't manage. So for that, I will have to break up
the execlist function into global-non-gt vs global-gt and then
call the former for both GuC and non-GuC cases (skipping latter
when GuC is doing the dump).
...alan
On Tue, 2022-01-18 at 02:03 -0800, Alan Previn wrote:
> Add device specific tables and register lists to cover different engines
> class types for GuC error state capture for XE_LP products.
>
> Also, add runtime allocation and freeing of extended register lists
> for registers that need steering identifiers that depend on
> the detected HW config.
>
> Signed-off-by: Alan Previn
> ---
> drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 2 +
> .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 208 +++---
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 4 +-
> 3 files changed, 186 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> index 20c537274e60..6adfb5c07bcf 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> @@ -19,20 +19,84 @@
> * NOTE: For engine-registers, GuC only needs the register offsets
> * from the engine-mmio-base
> */
> +#define COMMON_GEN12BASE_GLOBAL() \
> + {GEN12_FAULT_TLB_DATA0,0, 0, "GEN12_FAULT_TLB_DATA0"}, \
> + {GEN12_FAULT_TLB_DATA1,0, 0, "GEN12_FAULT_TLB_DATA1"}, \
> + {FORCEWAKE_MT, 0, 0, "FORCEWAKE_MT"}, \
> + {DERRMR, 0, 0, "DERRMR"}, \
> + {GEN12_AUX_ERR_DBG,0, 0, "GEN12_AUX_ERR_DBG"}, \
> + {GEN12_GAM_DONE, 0, 0, "GEN12_GAM_DONE"}, \
> + {GEN11_GUC_SG_INTR_ENABLE, 0, 0, "GEN11_GUC_SG_INTR_ENABLE"}, \
> + {GEN11_CRYPTO_RSVD_INTR_ENABLE, 0, 0, "GEN11_CRYPTO_RSVD_INTR_ENABLE"},
> \
> + {GEN11_GUNIT_CSME_INTR_ENABLE, 0, 0, "GEN11_GUNIT_CSME_INTR_ENABLE"}, \
> + {GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0, 0,
> "GEN11_GPM_WGBOXPERF_INTR_ENABLE"}, \
> + {GEN8_DE_MISC_IER, 0, 0, "GEN8_DE_MISC_IER"}, \
> + {GEN12_RING_FAULT_REG, 0, 0, "GEN12_RING_FAULT_REG"}
> +
[Intel-gfx] [PATCH 2/2] drm/i915: Introduce ilk_pch_pre_enable()
From: Ville Syrjälä
Complete the ilk pch modeset abstraction by adding ilk_pch_pre_enable().
I did the disable vs. post_disable split already for the disable
sequence, but the enable sequence was still left with the naked
ilk_fdi_pll_enable() call for some reason.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_pch_display.c | 14 ++
drivers/gpu/drm/i915/display/intel_pch_display.h | 2 ++
3 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 80bc52425e47..1c82cfc54bd4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1858,10 +1858,7 @@ static void ilk_crtc_enable(struct intel_atomic_state
*state,
intel_encoders_pre_enable(state, crtc);
if (new_crtc_state->has_pch_encoder) {
- /* Note: FDI PLL enabling _must_ be done before we enable the
-* cpu pipes, hence this is separate from all the other fdi/pch
-* enabling. */
- ilk_fdi_pll_enable(new_crtc_state);
+ ilk_pch_pre_enable(state, crtc);
} else {
assert_fdi_tx_disabled(dev_priv, pipe);
assert_fdi_rx_disabled(dev_priv, pipe);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c
b/drivers/gpu/drm/i915/display/intel_pch_display.c
index a55c4bfacd0d..0c528c612cb2 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -211,6 +211,20 @@ static void ilk_disable_pch_transcoder(struct intel_crtc
*crtc)
}
}
+void ilk_pch_pre_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+
+ /*
+* Note: FDI PLL enabling _must_ be done before we enable the
+* cpu pipes, hence this is separate from all the other fdi/pch
+* enabling.
+*/
+ ilk_fdi_pll_enable(crtc_state);
+}
+
/*
* Enable PCH resources required for PCH ports:
* - PCH PLLs
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.h
b/drivers/gpu/drm/i915/display/intel_pch_display.h
index 2c387fe3a467..f915fa4241d7 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.h
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.h
@@ -10,6 +10,8 @@ struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
+void ilk_pch_pre_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
void ilk_pch_enable(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void ilk_pch_disable(struct intel_atomic_state *state,
--
2.34.1
[Intel-gfx] [PATCH 1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate
From: Ville Syrjälä
Use DISPLAY_VER rather than GRAPHICS_VER to determine
availability of display hardware features.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 44c1f98144b4..e2b8409f9174 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1463,8 +1463,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
-#define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
-#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11 || \
+#define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4)
+#define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \
IS_GEMINILAKE(dev_priv) || \
IS_KABYLAKE(dev_priv))
@@ -1476,9 +1476,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define SUPPORTS_TV(dev_priv)
(INTEL_INFO(dev_priv)->display.supports_tv)
#define I915_HAS_HOTPLUG(dev_priv)
(INTEL_INFO(dev_priv)->display.has_hotplug)
-#define HAS_FW_BLC(dev_priv) (GRAPHICS_VER(dev_priv) > 2)
+#define HAS_FW_BLC(dev_priv) (DISPLAY_VER(dev_priv) > 2)
#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.fbc_mask != 0)
-#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && GRAPHICS_VER(dev_priv)
>= 7)
+#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv)
>= 7)
#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
@@ -1491,7 +1491,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
#define HAS_PSR_HW_TRACKING(dev_priv) \
(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
-#define HAS_PSR2_SEL_FETCH(dev_priv)(GRAPHICS_VER(dev_priv) >= 12)
+#define HAS_PSR2_SEL_FETCH(dev_priv)(DISPLAY_VER(dev_priv) >= 12)
#define HAS_TRANSCODER(dev_priv, trans)
((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0)
#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
@@ -1502,7 +1502,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_DMC(dev_priv) (INTEL_INFO(dev_priv)->display.has_dmc)
-#define HAS_MSO(i915) (GRAPHICS_VER(i915) >= 12)
+#define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
@@ -1535,7 +1535,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
-#define HAS_LSPCON(dev_priv) (IS_GRAPHICS_VER(dev_priv, 9, 10))
+#define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
/* DPF == dynamic parity feature */
#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
@@ -1549,7 +1549,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->display.pipe_mask != 0)
-#define HAS_VRR(i915) (GRAPHICS_VER(i915) >= 11)
+#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
#define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
@@ -1579,7 +1579,7 @@ i915_print_iommu_status(struct drm_i915_private *i915,
struct drm_printer *p);
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
*dev_priv)
{
- return GRAPHICS_VER(dev_priv) >= 6 && intel_vtd_active(dev_priv);
+ return DISPLAY_VER(dev_priv) >= 6 && intel_vtd_active(dev_priv);
}
static inline bool
--
2.34.1
[Intel-gfx] [PATCH 4/5] drm/i915: Extract hsw_configure_cpu_transcoder()
From: Ville Syrjälä
Pull the transcoder specific modeset steps into a single place.
With bigoiner we need to keep in mind wheher we're dealing with
the transcoder or the pipe, and a slightly higher level split makes
that easier.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 38
1 file changed, 23 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index c23c854f212f..d2906434ab3f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2012,6 +2012,27 @@ static void icl_ddi_bigjoiner_pre_enable(struct
intel_atomic_state *state,
intel_uncompressed_joiner_enable(crtc_state);
}
+static void hsw_configure_cpu_transcoder(const struct intel_crtc_state
*crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+ intel_set_transcoder_timings(crtc_state);
+
+ if (cpu_transcoder != TRANSCODER_EDP)
+ intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
+ crtc_state->pixel_multiplier - 1);
+
+ if (crtc_state->has_pch_encoder)
+ intel_cpu_transcoder_set_m_n(crtc_state,
+_state->fdi_m_n, NULL);
+
+ hsw_set_frame_start_delay(crtc_state);
+
+ hsw_set_transconf(crtc_state);
+}
+
static void hsw_crtc_enable(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -2040,21 +2061,8 @@ static void hsw_crtc_enable(struct intel_atomic_state
*state,
if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
bdw_set_pipemisc(new_crtc_state);
- if (!new_crtc_state->bigjoiner_slave &&
!transcoder_is_dsi(cpu_transcoder)) {
- intel_set_transcoder_timings(new_crtc_state);
-
- if (cpu_transcoder != TRANSCODER_EDP)
- intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
- new_crtc_state->pixel_multiplier - 1);
-
- if (new_crtc_state->has_pch_encoder)
- intel_cpu_transcoder_set_m_n(new_crtc_state,
-_crtc_state->fdi_m_n,
NULL);
-
- hsw_set_frame_start_delay(new_crtc_state);
-
- hsw_set_transconf(new_crtc_state);
- }
+ if (!new_crtc_state->bigjoiner_slave &&
!transcoder_is_dsi(cpu_transcoder))
+ hsw_configure_cpu_transcoder(new_crtc_state);
crtc->active = true;
--
2.34.1
[Intel-gfx] [PATCH 5/5] drm/i915: Move dsc/joiner enable into hsw_crtc_enable()
From: Ville Syrjälä
Lift the dsc/joiner enable up from the wonky places where it
currently sits (ddi .pre_enable() or icl_ddi_bigjoiner_pre_enable())
into hsw_crtc_enable() where we write the other per-pipe stuff
as well. Makes the transcoder vs. pipe split less confusing.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 6 --
drivers/gpu/drm/i915/display/intel_display.c | 12 +---
2 files changed, 5 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 2f20abc5122d..5d1f7d6218c5 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2425,9 +2425,6 @@ static void tgl_ddi_pre_enable_dp(struct
intel_atomic_state *state,
intel_ddi_enable_fec(encoder, crtc_state);
intel_dsc_dp_pps_write(encoder, crtc_state);
-
- if (!crtc_state->bigjoiner)
- intel_dsc_enable(crtc_state);
}
static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -2493,9 +2490,6 @@ static void hsw_ddi_pre_enable_dp(struct
intel_atomic_state *state,
intel_ddi_enable_pipe_clock(encoder, crtc_state);
intel_dsc_dp_pps_write(encoder, crtc_state);
-
- if (!crtc_state->bigjoiner)
- intel_dsc_enable(crtc_state);
}
static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d2906434ab3f..13b1de03640d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1974,7 +1974,6 @@ static void hsw_set_frame_start_delay(const struct
intel_crtc_state *crtc_state)
static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
const struct intel_crtc_state
*crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *master_crtc_state;
struct intel_crtc *master_crtc;
struct drm_connector_state *conn_state;
@@ -2004,12 +2003,6 @@ static void icl_ddi_bigjoiner_pre_enable(struct
intel_atomic_state *state,
if (crtc_state->bigjoiner_slave)
intel_encoders_pre_enable(state, master_crtc);
-
- /* need to enable VDSC, which we skipped in pre-enable */
- intel_dsc_enable(crtc_state);
-
- if (DISPLAY_VER(dev_priv) >= 13)
- intel_uncompressed_joiner_enable(crtc_state);
}
static void hsw_configure_cpu_transcoder(const struct intel_crtc_state
*crtc_state)
@@ -2057,6 +2050,11 @@ static void hsw_crtc_enable(struct intel_atomic_state
*state,
icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
}
+ intel_dsc_enable(new_crtc_state);
+
+ if (DISPLAY_VER(dev_priv) >= 13)
+ intel_uncompressed_joiner_enable(new_crtc_state);
+
intel_set_pipe_src_size(new_crtc_state);
if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
bdw_set_pipemisc(new_crtc_state);
--
2.34.1
[Intel-gfx] [PATCH 3/5] drm/i915: Use per-device debugs for bigjoiner stuff
From: Ville Syrjälä
Specify which device we're talking about when spewing
bigjoiner debugs.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 22
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e32a7a1e7ba0..c23c854f212f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7600,6 +7600,7 @@ static int intel_atomic_check_bigjoiner(struct
intel_atomic_state *state,
struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state)
{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_crtc_state *slave_crtc_state, *master_crtc_state;
struct intel_crtc *slave_crtc, *master_crtc;
@@ -7617,9 +7618,10 @@ static int intel_atomic_check_bigjoiner(struct
intel_atomic_state *state,
slave_crtc = intel_dsc_get_bigjoiner_secondary(crtc);
if (!slave_crtc) {
- DRM_DEBUG_KMS("[CRTC:%d:%s] Big joiner configuration requires "
- "CRTC + 1 to be used, doesn't exist\n",
- crtc->base.base.id, crtc->base.name);
+ drm_dbg_kms(>drm,
+ "[CRTC:%d:%s] Big joiner configuration requires "
+ "CRTC + 1 to be used, doesn't exist\n",
+ crtc->base.base.id, crtc->base.name);
return -EINVAL;
}
@@ -7633,16 +7635,18 @@ static int intel_atomic_check_bigjoiner(struct
intel_atomic_state *state,
if (slave_crtc_state->uapi.enable)
goto claimed;
- DRM_DEBUG_KMS("[CRTC:%d:%s] Used as slave for big joiner\n",
- slave_crtc->base.base.id, slave_crtc->base.name);
+ drm_dbg_kms(>drm,
+ "[CRTC:%d:%s] Used as slave for big joiner\n",
+ slave_crtc->base.base.id, slave_crtc->base.name);
return copy_bigjoiner_crtc_state(slave_crtc_state, new_crtc_state);
claimed:
- DRM_DEBUG_KMS("[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
- "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
- slave_crtc->base.base.id, slave_crtc->base.name,
- master_crtc->base.base.id, master_crtc->base.name);
+ drm_dbg_kms(>drm,
+ "[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
+ "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
+ slave_crtc->base.base.id, slave_crtc->base.name,
+ master_crtc->base.base.id, master_crtc->base.name);
return -EINVAL;
}
--
2.34.1
[Intel-gfx] [PATCH 2/5] drm/i915: Simplify intel_dsc_source_support()
From: Ville Syrjälä We can simplify the icl check in intel_dsc_source_support() by noting that the only case when DSC is not supported is when using transcoder A. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vdsc.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 9b05f93ed8bc..3faea903b9ae 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -341,19 +341,14 @@ bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state) const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - enum pipe pipe = crtc->pipe; if (!INTEL_INFO(i915)->display.has_dsc) return false; - /* On TGL, DSC is supported on all Pipes */ if (DISPLAY_VER(i915) >= 12) return true; - if (DISPLAY_VER(i915) >= 11 && - (pipe != PIPE_A || cpu_transcoder == TRANSCODER_EDP || -cpu_transcoder == TRANSCODER_DSI_0 || -cpu_transcoder == TRANSCODER_DSI_1)) + if (DISPLAY_VER(i915) >= 11 && cpu_transcoder != TRANSCODER_A) return true; return false; -- 2.34.1
[Intel-gfx] [PATCH 1/5] drm/i915: Skip dsc readout if the transcoder is disabled
From: Ville Syrjälä Tryingf to do readout when we don't even have a cpu transcoder is not a great idea. Don't do it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 80bc52425e47..e32a7a1e7ba0 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4380,13 +4380,13 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, active = true; } + if (!active) + goto out; + intel_dsc_get_config(pipe_config); if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config->dsc.compression_enable) intel_uncompressed_joiner_get_config(pipe_config); - if (!active) - goto out; - if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || DISPLAY_VER(dev_priv) >= 11) intel_get_transcoder_timings(crtc, pipe_config); -- 2.34.1
Re: [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
On Mon, Jan 24, 2022 at 03:52:34PM +0200, Stanislav Lisovskiy wrote:
> In terms of async flip optimization we don't to allocate
> extra ddb space, so lets skip it.
>
> v2: - Extracted min ddb async flip check to separate function
> (Ville Syrjälä)
> - Used this function to prevent false positive WARN
> to be triggered(Ville Syrjälä)
>
> v3: - Renamed dg2_need_min_ddb to need_min_ddb thus making
> it more universal.
> - Also used DISPLAY_VER instead of IS_DG2(Ville Syrjälä)
> - Use rate = 0 instead of just setting extra = 0, thus
> letting other planes to use extra ddb and avoiding WARN
> (Ville Syrjälä)
>
> v4: - Renamed needs_min_ddb as s/needs/use/ to match
> the wm0 counterpart(Ville Syrjälä)
> - Added plane->async_flip check to use_min_ddb(now
> passing plane as a parameter to do that)(Ville Syrjälä)
> - Account for use_min_ddb also when calculating total data rate
> (Ville Syrjälä)
>
> v5:
> - Use for_each_intel_plane_on_crtc instead of for_each_intel_plane_id
> to get plane->async_flip check and account for all planes(Ville Syrjälä)
> - Fix line wrapping(Ville Syrjälä)
> - Set plane data rate conditionally, avoiding on redundant assignment
> (Ville Syrjälä)
> - Removed redundant whitespace(Ville Syrjälä)
> - Handle use_min_ddb case in skl_plane_relative_data_rate instead of
> icl_get_total_relative_data_rate(Ville Syrjälä)
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/intel_pm.c | 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0bb4c941f950..bb147e5a77b6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4906,6 +4906,16 @@ static u8 skl_compute_dbuf_slices(struct intel_crtc
> *crtc, u8 active_pipes)
> return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0;
> }
>
> +static bool use_min_ddb(const struct intel_crtc_state *crtc_state,
> + struct intel_plane *plane)
> +{
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> +
> + return DISPLAY_VER(i915) >= 13 &&
> +crtc_state->uapi.async_flip &&
> +plane->async_flip;
> +}
> +
> static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
>struct intel_plane *plane)
> {
> @@ -4934,6 +4944,14 @@ skl_plane_relative_data_rate(const struct
> intel_crtc_state *crtc_state,
> if (plane->id == PLANE_CURSOR)
> return 0;
>
> + /*
> + * We calculate extra ddb based on ratio plane rate/total data rate
> + * in case, in some cases we should not allocate extra ddb for the
> plane,
> + * so do not count its data rate, if this is the case.
> + */
> + if (use_min_ddb(crtc_state, plane))
> + return 0;
> +
> if (color_plane == 1 &&
> !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
> return 0;
Yeah this looks nice and simple. Only minor nit is that I'd probably
have put it after this ccs vs. planar related thing which is a more
static decision than the async flip optimization.
Reviewed-by: Ville Syrjälä
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH V2 0/7] DRM kmap() fixes and kmap_local_page() conversions
On Mon, Jan 24, 2022 at 01:08:26PM +0100, Christian König wrote: > Am 24.01.22 um 02:54 schrieb ira.we...@intel.com: > > From: Ira Weiny > > > > Changes from V1: > > Use memcpy_to_page() where appropriate > > Rebased to latest > > > > The kmap() call may cause issues with work being done with persistent > > memory. > > For this and other reasons it is being deprecated. > > I'm really wondering how we should be able to implement the kernel mapping > without kmap in TTM. > > > This series starts by converting the last easy kmap() uses in the drm tree > > to > > kmap_local_page(). > > > > The final 2 patches fix bugs found while working on the ttm_bo_kmap_ttm() > > conversion. They are valid fixes but were found via code inspection not > > because of any actual bug so don't require a stable tag.[1] > > > > There is one more call to kmap() used in ttm_bo_kmap_ttm(). Unfortunately, > > fixing this is not straight forward so it is left to future work.[2] > > Patches #2, #4, #6 and #7 are Reviewed-by: Christian König > Christian, Would you prefer I send those 4 to you as a separate series? > > How to you now want to push those upstream? I can pick them up for the AMD > tree like Daniel suggested or you can push them through something else. You picking them up from this series is ok as well. Daniel will you take #1, #3, and #5? Thanks, Ira > > Regards, > Christian. > > > > > [1] > > https://lore.kernel.org/lkml/fb71af05-a889-8f6e-031b-426b58a64...@amd.com/ > > [2] > > https://lore.kernel.org/lkml/20211215210949.gw3538...@iweiny-desk2.sc.intel.com/ > > > > > > Ira Weiny (7): > > drm/i915: Replace kmap() with kmap_local_page() > > drm/amd: Replace kmap() with kmap_local_page() > > drm/gma: Remove calls to kmap() > > drm/radeon: Replace kmap() with kmap_local_page() > > drm/msm: Alter comment to use kmap_local_page() > > drm/amdgpu: Ensure kunmap is called on error > > drm/radeon: Ensure kunmap is called on error > > > > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 > > drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 1 + > > drivers/gpu/drm/gma500/gma_display.c | 6 ++ > > drivers/gpu/drm/gma500/mmu.c | 8 > > drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 6 ++ > > drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 8 > > drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 4 ++-- > > drivers/gpu/drm/i915/gt/shmem_utils.c | 7 ++- > > drivers/gpu/drm/i915/i915_gem.c | 8 > > drivers/gpu/drm/i915/i915_gpu_error.c | 4 ++-- > > drivers/gpu/drm/msm/msm_gem_submit.c | 4 ++-- > > drivers/gpu/drm/radeon/radeon_ttm.c | 4 ++-- > > drivers/gpu/drm/radeon/radeon_uvd.c | 1 + > > 13 files changed, 32 insertions(+), 37 deletions(-) > > > > -- > > 2.31.1 > > >
Re: [Intel-gfx] [RFC PATCH 5/5] drm/i915/flat-CCS: handle creation and destruction of flat CCS bo's
On Mon, 2022-01-24 at 17:24 +0100, Thomas Hellström wrote: > Hi, Adrian > > On 1/21/22 23:22, Adrian Larumbe wrote: > > When a flat-CCS lmem-bound BO is evicted onto smem for the first > > time, a > > separate swap gem object is created to hold the contents of the CCS > > block. > > It is assumed that, for a flat-CCS bo to be migrated back onto > > lmem, it > > should've begun its life in lmem. > > > > It also handles destruction of the swap bo when the original TTM > > object > > reaches the end of its life. > > > > Signed-off-by: Adrian Larumbe > > > While allocating a separate object for the CCS data is certainly > possible, it poses some additional difficulties that have not been > addressed here. > > The CCS object needs to share the dma_resv of the original object. > That > is because the CCS object needs to be locked and validated when we > process it, and we > can only trylock within the ttm move callback which might therefore > fail > and isn't sufficient on swapin. We'd need to create some > i915_gem_object_create_region_locked() that wraps > ttm_bo_init_reserved(). Actually that would be a function to create with a reservation object shared from another object. /Thomas
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/overlay: Prevent divide by zero bugs in scaling
== Series Details == Series: drm/i915/overlay: Prevent divide by zero bugs in scaling URL : https://patchwork.freedesktop.org/series/99242/ State : success == Summary == CI Bug Log - changes from CI_DRM_11128 -> Patchwork_22079 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/index.html Participating hosts (47 -> 37) -- Missing(10): bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-bdw-samus bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_22079 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/fi-hsw-4770/igt@amdgpu/amd_ba...@cs-gfx.html * igt@gem_flink_basic@bad-flink: - fi-skl-6600u: [PASS][2] -> [FAIL][3] ([i915#4547]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11128/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html * igt@i915_selftest@live@execlists: - fi-bsw-kefka: [PASS][4] -> [INCOMPLETE][5] ([i915#2940]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11128/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b: - fi-cfl-8109u: [PASS][6] -> [DMESG-WARN][7] ([i915#295]) +11 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11128/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html * igt@runner@aborted: - fi-bsw-kefka: NOTRUN -> [FAIL][8] ([fdo#109271] / [i915#1436] / [i915#3428] / [i915#4312]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/fi-bsw-kefka/igt@run...@aborted.html Possible fixes * igt@i915_selftest@live@hangcheck: - fi-hsw-4770:[INCOMPLETE][9] ([i915#4785]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11128/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [DMESG-WARN][11] ([i915#4269]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11128/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html Warnings * igt@runner@aborted: - fi-skl-6600u: [FAIL][13] ([i915#1436] / [i915#4312]) -> [FAIL][14] ([i915#4312]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11128/fi-skl-6600u/igt@run...@aborted.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/fi-skl-6600u/igt@run...@aborted.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295 [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428 [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547 [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785 Build changes - * Linux: CI_DRM_11128 -> Patchwork_22079 CI-20190529: 20190529 CI_DRM_11128: 49bb8f6f465751bc71103784fe7603409fee @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6330: f73008bac9a8db0779264b170f630483e9165764 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_22079: f8e4ab5e3cd4369d9b7cd1c36d192d4feda748cd @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f8e4ab5e3cd4 drm/i915/overlay: Prevent divide by zero bugs in scaling == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22079/index.html
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dg2: Add Wa_18018781329 (rev7)
On Sun, Jan 23, 2022 at 11:33:55PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/dg2: Add Wa_18018781329 (rev7)
> URL : https://patchwork.freedesktop.org/series/99128/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11120_full -> Patchwork_22072_full
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_22072_full absolutely need to
> be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_22072_full, please notify your bug team to allow
> them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Participating hosts (10 -> 11)
> --
>
> Additional (1): shard-tglu
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_22072_full:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@i915_pm_sseu@full-enable:
> - shard-skl: NOTRUN -> [FAIL][1]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22072/shard-skl6/igt@i915_pm_s...@full-enable.html
https://gitlab.freedesktop.org/drm/intel/-/issues/3524 is back.
Patch applied to drm-intel-gt-next. Thanks Swathi for the review.
Matt
>
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@gem_ctx_persistence@smoketest:
> - {shard-tglu}: NOTRUN -> [INCOMPLETE][2]
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22072/shard-tglu-7/igt@gem_ctx_persiste...@smoketest.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_22072_full that come from known
> issues:
>
> ### CI changes ###
>
> Issues hit
>
> * boot:
> - shard-apl: ([PASS][3], [PASS][4], [PASS][5], [PASS][6],
> [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12],
> [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18],
> [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24],
> [PASS][25], [PASS][26], [PASS][27]) -> ([PASS][28], [PASS][29], [PASS][30],
> [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36],
> [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42],
> [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48],
> [PASS][49], [PASS][50], [FAIL][51], [PASS][52]) ([i915#4386])
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl1/boot.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl1/boot.html
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl1/boot.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl1/boot.html
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl2/boot.html
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl2/boot.html
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl2/boot.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl2/boot.html
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl3/boot.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl3/boot.html
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl3/boot.html
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl4/boot.html
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl4/boot.html
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl4/boot.html
>[17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl6/boot.html
>[18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl6/boot.html
>[19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl6/boot.html
>[20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl6/boot.html
>[21]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl7/boot.html
>[22]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl7/boot.html
>[23]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl7/boot.html
>[24]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl7/boot.html
>[25]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl8/boot.html
>[26]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl8/boot.html
>[27]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11120/shard-apl8/boot.html
>[28]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22072/shard-apl2/boot.html
>[29]:
>
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: fix header file inclusion for might_alloc() (rev4)
== Series Details == Series: drm/i915: fix header file inclusion for might_alloc() (rev4) URL : https://patchwork.freedesktop.org/series/99215/ State : failure == Summary == Applying: drm/i915: fix header file inclusion for might_alloc() Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_vma_resource.c Falling back to patching base and 3-way merge... No changes -- Patch already applied.
Re: [Intel-gfx] [PATCH 2/3] drm/arm/komeda : change driver to use drm_writeback_connector.base pointer
This makes sense given the other patches in your series, but it seems as
yet no one has anything to say about this. I don't have anything
specific to comment on other than it seems to make the correct changes
to komeda given the rest.
Reviewed-by: Carsten Haitzler
On 1/11/22 10:18, Kandpal, Suraj wrote:
Making changes to komeda driver because we had to change
drm_writeback_connector.base into a pointer the reason for which is
expained in the Patch (drm: add writeback pointers to drm_connector).
Signed-off-by: Kandpal, Suraj
---
drivers/gpu/drm/arm/display/komeda/komeda_crtc.c | 2 +-
drivers/gpu/drm/arm/display/komeda/komeda_kms.h | 3 ++-
drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c | 9 +
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
index 59172acb9738..eb37f41c1790 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
@@ -265,7 +265,7 @@ komeda_crtc_do_flush(struct drm_crtc *crtc,
if (slave && has_bit(slave->id, kcrtc_st->affected_pipes))
komeda_pipeline_update(slave, old->state);
- conn_st = wb_conn ? wb_conn->base.base.state : NULL;
+ conn_st = wb_conn ? wb_conn->base.base->state : NULL;
if (conn_st && conn_st->writeback_job)
drm_writeback_queue_job(_conn->base, conn_st);
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_kms.h b/drivers/gpu/drm/arm/display/komeda/komeda_kms.h
index 456f3c435719..8d83883a1d99 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_kms.h
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_kms.h
@@ -53,6 +53,7 @@ struct komeda_plane_state {
* struct komeda_wb_connector
*/
struct komeda_wb_connector {
+ struct drm_connector conn;
/** @base: _writeback_connector */
struct drm_writeback_connector base;
@@ -136,7 +137,7 @@ struct komeda_kms_dev {
static inline bool is_writeback_only(struct drm_crtc_state *st)
{
struct komeda_wb_connector *wb_conn = to_kcrtc(st->crtc)->wb_conn;
- struct drm_connector *conn = wb_conn ? _conn->base.base : NULL;
+ struct drm_connector *conn = wb_conn ? wb_conn->base.base : NULL;
return conn && (st->connector_mask == BIT(drm_connector_index(conn)));
}
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
b/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
index e465cc4879c9..0caaf483276d 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
@@ -51,7 +51,7 @@ komeda_wb_encoder_atomic_check(struct drm_encoder *encoder,
return -EINVAL;
}
- wb_layer = to_kconn(to_wb_conn(conn_st->connector))->wb_layer;
+ wb_layer =
to_kconn(drm_connector_to_writeback(conn_st->connector))->wb_layer;
/*
* No need for a full modested when the only connector changed is the
@@ -123,7 +123,7 @@ komeda_wb_connector_fill_modes(struct drm_connector
*connector,
static void komeda_wb_connector_destroy(struct drm_connector *connector)
{
drm_connector_cleanup(connector);
- kfree(to_kconn(to_wb_conn(connector)));
+ kfree(to_kconn(drm_connector_to_writeback(connector)));
}
static const struct drm_connector_funcs komeda_wb_connector_funcs = {
@@ -155,6 +155,7 @@ static int komeda_wb_connector_add(struct komeda_kms_dev
*kms,
kwb_conn->wb_layer = kcrtc->master->wb_layer;
wb_conn = _conn->base;
+ wb_conn->base = _conn->conn;
wb_conn->encoder.possible_crtcs = BIT(drm_crtc_index(>base));
formats = komeda_get_layer_fourcc_list(>fmt_tbl,
@@ -171,9 +172,9 @@ static int komeda_wb_connector_add(struct komeda_kms_dev
*kms,
return err;
}
- drm_connector_helper_add(_conn->base, _wb_conn_helper_funcs);
+ drm_connector_helper_add(wb_conn->base, _wb_conn_helper_funcs);
- info = _conn->base.base.display_info;
+ info = _conn->base.base->display_info;
info->bpc = __fls(kcrtc->master->improc->supported_color_depths);
info->color_formats = kcrtc->master->improc->supported_color_formats;
Re: [Intel-gfx] [PATCH 08/11] dma-buf: add dma_fence_chain_contained helper
On 1/24/22 14:03, Christian König wrote:
It's a reoccurring pattern that we need to extract the fence
from a dma_fence_chain object. Add a helper for this.
Signed-off-by: Christian König
Reviewed-by: Thomas Hellström
---
drivers/dma-buf/dma-fence-chain.c | 6 ++
include/linux/dma-fence-chain.h | 15 +++
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/dma-buf/dma-fence-chain.c
b/drivers/dma-buf/dma-fence-chain.c
index 084c6927b735..06f8ef97c6e8 100644
--- a/drivers/dma-buf/dma-fence-chain.c
+++ b/drivers/dma-buf/dma-fence-chain.c
@@ -148,8 +148,7 @@ static bool dma_fence_chain_enable_signaling(struct
dma_fence *fence)
dma_fence_get(>base);
dma_fence_chain_for_each(fence, >base) {
- struct dma_fence_chain *chain = to_dma_fence_chain(fence);
- struct dma_fence *f = chain ? chain->fence : fence;
+ struct dma_fence *f = dma_fence_chain_contained(fence);
dma_fence_get(f);
if (!dma_fence_add_callback(f, >cb, dma_fence_chain_cb)) {
@@ -165,8 +164,7 @@ static bool dma_fence_chain_enable_signaling(struct
dma_fence *fence)
static bool dma_fence_chain_signaled(struct dma_fence *fence)
{
dma_fence_chain_for_each(fence, fence) {
- struct dma_fence_chain *chain = to_dma_fence_chain(fence);
- struct dma_fence *f = chain ? chain->fence : fence;
+ struct dma_fence *f = dma_fence_chain_contained(fence);
if (!dma_fence_is_signaled(f)) {
dma_fence_put(fence);
diff --git a/include/linux/dma-fence-chain.h b/include/linux/dma-fence-chain.h
index ee906b659694..10d51bcdf7b7 100644
--- a/include/linux/dma-fence-chain.h
+++ b/include/linux/dma-fence-chain.h
@@ -66,6 +66,21 @@ to_dma_fence_chain(struct dma_fence *fence)
return container_of(fence, struct dma_fence_chain, base);
}
+/**
+ * dma_fence_chain_contained - return the contained fence
+ * @fence: the fence to test
+ *
+ * If the fence is a dma_fence_chain the function returns the fence contained
+ * inside the chain object, otherwise it returns the fence itself.
+ */
+static inline struct dma_fence *
+dma_fence_chain_contained(struct dma_fence *fence)
+{
+ struct dma_fence_chain *chain = to_dma_fence_chain(fence);
+
+ return chain ? chain->fence : fence;
+}
+
/**
* dma_fence_chain_alloc
*
Re: [Intel-gfx] [PATCH 06/11] dma-buf: warn about containers in dma_resv object
On 1/24/22 14:03, Christian König wrote: Drivers should not add containers as shared fences to the dma_resv object, instead each fence should be added individually. Signed-off-by: Christian König Reviewed-by: Daniel Vetter Reviewed-by: Thomas Hellström Is there any indication that this triggers on existing drivers? Thomas
Re: [Intel-gfx] [PATCH 01/11] drm/radeon: use ttm_resource_manager_debug
On Mon, 2022-01-24 at 14:03 +0100, Christian König wrote: > Instead of calling the debug operation directly. > > Signed-off-by: Christian König > Reviewed-by: Huang Rui The first two patches seem unrelated to the series. Also is there a chance of a series cover-letter? Thanks, Thomas > --- > drivers/gpu/drm/radeon/radeon_ttm.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c > b/drivers/gpu/drm/radeon/radeon_ttm.c > index 11b21d605584..0d1283cdc8fb 100644 > --- a/drivers/gpu/drm/radeon/radeon_ttm.c > +++ b/drivers/gpu/drm/radeon/radeon_ttm.c > @@ -802,7 +802,7 @@ static int radeon_mm_vram_dump_table_show(struct > seq_file *m, void *unused) > > TTM_PL_VRAM); > struct drm_printer p = drm_seq_file_printer(m); > > - man->func->debug(man, ); > + ttm_resource_manager_debug(man, ); > return 0; > } > > @@ -820,7 +820,7 @@ static int radeon_mm_gtt_dump_table_show(struct > seq_file *m, void *unused) > > TTM_PL_TT); > struct drm_printer p = drm_seq_file_printer(m); > > - man->func->debug(man, ); > + ttm_resource_manager_debug(man, ); > return 0; > } >
Re: [Intel-gfx] [PATCH 04/11] dma-buf: warn about dma_fence_array container rules v2
On Mon, 2022-01-24 at 14:03 +0100, Christian König wrote: > It's not allowed to nest another dma_fence container into a > dma_fence_array > or otherwise we can run into recursion. > > Warn about that when we create a dma_fence_array. > > v2: fix comment style and typo in the warning pointed out by Thomas > > Signed-off-by: Christian König > Reviewed-by: Daniel Vetter Reviewed-by: Thomas Hellström > --- > drivers/dma-buf/dma-fence-array.c | 14 ++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/dma-buf/dma-fence-array.c b/drivers/dma-buf/dma- > fence-array.c > index 3e07f961e2f3..cb1bacb5a42b 100644 > --- a/drivers/dma-buf/dma-fence-array.c > +++ b/drivers/dma-buf/dma-fence-array.c > @@ -176,6 +176,20 @@ struct dma_fence_array > *dma_fence_array_create(int num_fences, > > array->base.error = PENDING_ERROR; > > + /* > + * dma_fence_array objects should never contain any other > fence > + * containers or otherwise we run into recursion and > potential kernel > + * stack overflow on operations on the dma_fence_array. > + * > + * The correct way of handling this is to flatten out the > array by the > + * caller instead. > + * > + * Enforce this here by checking that we don't create a > dma_fence_array > + * with any container inside. > + */ > + while (num_fences--) > + WARN_ON(dma_fence_is_container(fences[num_fences])); > + > return array; > } > EXPORT_SYMBOL(dma_fence_array_create);
Re: [Intel-gfx] [RFC PATCH 5/5] drm/i915/flat-CCS: handle creation and destruction of flat CCS bo's
Hi, Adrian
On 1/21/22 23:22, Adrian Larumbe wrote:
When a flat-CCS lmem-bound BO is evicted onto smem for the first time, a
separate swap gem object is created to hold the contents of the CCS block.
It is assumed that, for a flat-CCS bo to be migrated back onto lmem, it
should've begun its life in lmem.
It also handles destruction of the swap bo when the original TTM object
reaches the end of its life.
Signed-off-by: Adrian Larumbe
While allocating a separate object for the CCS data is certainly
possible, it poses some additional difficulties that have not been
addressed here.
The CCS object needs to share the dma_resv of the original object. That
is because the CCS object needs to be locked and validated when we process it,
and we
can only trylock within the ttm move callback which might therefore fail
and isn't sufficient on swapin. We'd need to create some
i915_gem_object_create_region_locked() that wraps ttm_bo_init_reserved().
Furthermore destruction also becomes complicated, as the main object
owns a refcount on the CCS object, but the CCS object also needs a
refcount on the dma_resv part of the main object which will create a
refcount loop requiring an additional dma_resv refcount for objects to
resolve, similar to how we've solved this for shared dma_resv shared with vms.
Also shouldn't we be destroying the CCS object when data is moved back into
lmem?
Anyway, when we've earlier discussed how to handle this, we've discussed a
solution where the struct ttm_tt was given an inflated size on creation to
accommodate also the CCS data at the end. That would waste some memory if we
ever were to migrate such an object to system while decompressing, but
otherwise greatly simplify the handling. Basically we'd only look at whether
the object is flat-CCS enabled in i915_ttm_tt_create() and inflate the ttm_tt
size.
This requires an additional size parameter to ttm_tt_init(), but I've once discussed this with Christian König, and he didn't seem to object at the time. (+CC Christian König).
Thanks,
Thomas
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 11 +++
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 78 +++-
2 files changed, 87 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 84cae740b4a5..24708d6bfd9c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -474,11 +474,22 @@ static int i915_ttm_shrink(struct drm_i915_gem_object
*obj, unsigned int flags)
static void i915_ttm_delete_mem_notify(struct ttm_buffer_object *bo)
{
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
+ struct drm_i915_private *i915 =
+ container_of(bo->bdev, typeof(*i915), bdev);
if (likely(obj)) {
__i915_gem_object_pages_fini(obj);
i915_ttm_free_cached_io_rsgt(obj);
}
+
+ if (HAS_FLAT_CCS(i915) && obj->flat_css.enabled) {
+ struct drm_i915_gem_object *swap_obj = obj->flat_css.swap;
+
+ if (swap_obj) {
+ swap_obj->base.funcs->free(_obj->base);
+ obj->flat_css.swap = NULL;
+ }
+ }
}
static struct i915_refct_sgt *i915_ttm_tt_get_st(struct ttm_tt *ttm)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 1de306c03aaf..3479c4a37bd8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -162,6 +162,56 @@ int i915_ttm_move_notify(struct ttm_buffer_object *bo)
return 0;
}
+static int
+i915_ccs_handle_move(struct drm_i915_gem_object *obj,
+struct ttm_resource *dst_mem)
+{
+ struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
+ struct drm_i915_private *i915 = container_of(bo->bdev, typeof(*i915),
+bdev);
+ struct intel_memory_region *dst_reg;
+ size_t ccs_blk_size;
+ int ret;
+
+ dst_reg = i915_ttm_region(bo->bdev, dst_mem->mem_type);
+ ccs_blk_size = GET_CCS_SIZE(i915, obj->base.size);
+
+ if (dst_reg->type != INTEL_MEMORY_LOCAL &&
+ dst_reg->type != INTEL_MEMORY_SYSTEM) {
+ DRM_DEBUG_DRIVER("Wrong memory region when using flat CCS.\n");
+ return -EINVAL;
+ }
+
+ if (dst_reg->type == INTEL_MEMORY_LOCAL &&
+ (obj->flat_css.swap == NULL ||
!i915_gem_object_has_pages(obj->flat_css.swap))) {
+ /*
+* All BOs begin their life cycle in smem, even if meant to be
+* lmem-bound. Then, upon running the execbuf2 ioctl, get moved
+* onto lmem before first use. Therefore, migrating a flat-CCS
+* lmem-only buffer into lmem means a CCS swap buffer had
already
+* been allocated when first
Re: [Intel-gfx] [PATCH V2 3/7] drm/gma: Remove calls to kmap()
On Sun, Jan 23, 2022 at 05:54:05PM -0800, ira.we...@intel.com wrote:
> From: Ira Weiny
>
> kmap() is being deprecated and these instances are easy to convert to
> kmap_local_page().
>
> Furthermore, in gma_crtc_cursor_set() use the memcpy_from_page() helper
> instead of an open coded use of kmap_local_page().
>
> Signed-off-by: Ira Weiny
Applied to drm-misc-next, the others should all have full time maintainers
to make sure the patches land. Pls holler if not.
Thanks, Daniel
> ---
> drivers/gpu/drm/gma500/gma_display.c | 6 ++
> drivers/gpu/drm/gma500/mmu.c | 8
> 2 files changed, 6 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/gma500/gma_display.c
> b/drivers/gpu/drm/gma500/gma_display.c
> index 99da3118131a..60ba7de59139 100644
> --- a/drivers/gpu/drm/gma500/gma_display.c
> +++ b/drivers/gpu/drm/gma500/gma_display.c
> @@ -335,7 +335,7 @@ int gma_crtc_cursor_set(struct drm_crtc *crtc,
> struct psb_gem_object *pobj;
> struct psb_gem_object *cursor_pobj = gma_crtc->cursor_pobj;
> struct drm_gem_object *obj;
> - void *tmp_dst, *tmp_src;
> + void *tmp_dst;
> int ret = 0, i, cursor_pages;
>
> /* If we didn't get a handle then turn the cursor off */
> @@ -400,9 +400,7 @@ int gma_crtc_cursor_set(struct drm_crtc *crtc,
> /* Copy the cursor to cursor mem */
> tmp_dst = dev_priv->vram_addr + cursor_pobj->offset;
> for (i = 0; i < cursor_pages; i++) {
> - tmp_src = kmap(pobj->pages[i]);
> - memcpy(tmp_dst, tmp_src, PAGE_SIZE);
> - kunmap(pobj->pages[i]);
> + memcpy_from_page(tmp_dst, pobj->pages[i], 0, PAGE_SIZE);
> tmp_dst += PAGE_SIZE;
> }
>
> diff --git a/drivers/gpu/drm/gma500/mmu.c b/drivers/gpu/drm/gma500/mmu.c
> index fe9ace2a7967..a70b01ccdf70 100644
> --- a/drivers/gpu/drm/gma500/mmu.c
> +++ b/drivers/gpu/drm/gma500/mmu.c
> @@ -184,17 +184,17 @@ struct psb_mmu_pd *psb_mmu_alloc_pd(struct
> psb_mmu_driver *driver,
> pd->invalid_pte = 0;
> }
>
> - v = kmap(pd->dummy_pt);
> + v = kmap_local_page(pd->dummy_pt);
> for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i)
> v[i] = pd->invalid_pte;
>
> - kunmap(pd->dummy_pt);
> + kunmap_local(v);
>
> - v = kmap(pd->p);
> + v = kmap_local_page(pd->p);
> for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i)
> v[i] = pd->invalid_pde;
>
> - kunmap(pd->p);
> + kunmap_local(v);
>
> clear_page(kmap(pd->dummy_page));
> kunmap(pd->dummy_page);
> --
> 2.31.1
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
Re: [Intel-gfx] [RFC PATCH 4/5] drm/i915/flat-CCS: handle CCS block blit for bo migrations
On Fri, 21 Jan 2022, Adrian Larumbe wrote:
> Because the smem-evicted bo that holds the CCS block has to be blitted
> separately from the original compressed bo, two sets of PTEs have to
> be emitted for every bo copy.
>
> This commit is partially based off another commit from Ramalingam C
> , currently under discussion.
>
> Signed-off-by: Adrian Larumbe
> ---
> drivers/gpu/drm/i915/gt/intel_migrate.c| 288 +++--
> drivers/gpu/drm/i915/gt/intel_migrate.h| 2 +
> drivers/gpu/drm/i915/gt/selftest_migrate.c | 3 +-
> 3 files changed, 207 insertions(+), 86 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
> b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index 716f2f51c7f9..da0fcc42c43c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -447,14 +447,183 @@ static bool wa_1209644611_applies(int ver, u32 size)
> return height % 4 == 3 && height <= 8;
> }
>
> +static inline u32 *i915_flush_dw(u32 *cmd, u64 dst, u32 flags)
As a general rule, please don't use the inline keyword in .c files, just
let the compiler decide. It's a premature optimization. And you won't
get warnings if it's unused.
BR,
Jani.
> +{
> + /* Mask the 3 LSB to use the PPGTT address space */
> + *cmd++ = MI_FLUSH_DW | flags;
> + *cmd++ = lower_32_bits(dst);
> + *cmd++ = upper_32_bits(dst);
> +
> + return cmd;
> +}
> +
> +static u32 calc_ctrl_surf_instr_size(struct drm_i915_private *i915, int
> +size)
> +{
> + u32 num_cmds, num_blks, total_size;
> +
> + if (!GET_CCS_SIZE(i915, size))
> + return 0;
> +
> + /*
> + * XY_CTRL_SURF_COPY_BLT transfers CCS in 256 byte
> + * blocks. one XY_CTRL_SURF_COPY_BLT command can
> + * trnasfer upto 1024 blocks.
> + */
> + num_blks = (GET_CCS_SIZE(i915, size) +
> +(NUM_CCS_BYTES_PER_BLOCK - 1)) >> 8;
> + num_cmds = (num_blks + (NUM_CCS_BLKS_PER_XFER - 1)) >> 10;
> + total_size = (XY_CTRL_SURF_INSTR_SIZE) * num_cmds;
> +
> + /*
> + * We need to add a flush before and after
> + * XY_CTRL_SURF_COPY_BLT
> + */
> + total_size += 2 * MI_FLUSH_DW_SIZE;
> + return total_size;
> +}
> +
> +static u32 *_i915_ctrl_surf_copy_blt(u32 *cmd, u64 src_addr, u64 dst_addr,
> + u8 src_mem_access, u8 dst_mem_access,
> + int src_mocs, int dst_mocs,
> + u16 num_ccs_blocks)
> +{
> + int i = num_ccs_blocks;
> +
> + /*
> + * The XY_CTRL_SURF_COPY_BLT instruction is used to copy the CCS
> + * data in and out of the CCS region.
> + *
> + * We can copy at most 1024 blocks of 256 bytes using one
> + * XY_CTRL_SURF_COPY_BLT instruction.
> + *
> + * In case we need to copy more than 1024 blocks, we need to add
> + * another instruction to the same batch buffer.
> + *
> + * 1024 blocks of 256 bytes of CCS represent a total 256KB of CCS.
> + *
> + * 256 KB of CCS represents 256 * 256 KB = 64 MB of LMEM.
> + */
> + do {
> + /*
> + * We use logical AND with 1023 since the size field
> + * takes values which is in the range of 0 - 1023
> + */
> + *cmd++ = ((XY_CTRL_SURF_COPY_BLT) |
> + (src_mem_access << SRC_ACCESS_TYPE_SHIFT) |
> + (dst_mem_access << DST_ACCESS_TYPE_SHIFT) |
> + (((i - 1) & 1023) << CCS_SIZE_SHIFT));
> + *cmd++ = lower_32_bits(src_addr);
> + *cmd++ = ((upper_32_bits(src_addr) & 0x) |
> + (src_mocs << XY_CTRL_SURF_MOCS_SHIFT));
> + *cmd++ = lower_32_bits(dst_addr);
> + *cmd++ = ((upper_32_bits(dst_addr) & 0x) |
> + (dst_mocs << XY_CTRL_SURF_MOCS_SHIFT));
> + src_addr += SZ_64M;
> + dst_addr += SZ_64M;
> + i -= NUM_CCS_BLKS_PER_XFER;
> + } while (i > 0);
> +
> + return cmd;
> +}
> +
> +
> +static int emit_ccs(struct i915_request *rq,
> + struct sgt_dma *it_lmem,
> + enum i915_cache_level lmem_cache_level,
> + struct sgt_dma *it_css,
> + enum i915_cache_level css_cache_level,
> + bool lmem2smem,
> + int size)
> +{
> + struct drm_i915_private *i915 = rq->engine->i915;
> + u32 num_ccs_blks = (GET_CCS_SIZE(i915, size) +
> + NUM_CCS_BYTES_PER_BLOCK - 1) >> 8;
> + struct sgt_dma *it_src, *it_dst;
> + enum i915_cache_level src_cache_level;
> + enum i915_cache_level dst_cache_level;
> + u8 src_access, dst_access;
> + u32 src_offset, dst_offset;
> + u32 ccs_ring_size;
> + int err, len;
> + u32 *cs;
> +
> + ccs_ring_size = calc_ctrl_surf_instr_size(i915, size);
> +
> + err = emit_no_arbitration(rq);
Re: [Intel-gfx] [RFC PATCH 3/5] drm/i915/flat-CCS: move GET_CCS_SIZE macro into driver-wide header
On Fri, 21 Jan 2022, Adrian Larumbe wrote:
> It has to be used by other files other than low-level migration code.
Maybe, but i915_drv.h is not the dumping ground for this
stuff. Especially you shouldn't add anything in i915_drv.h that requires
you to pull in other headers. The goal is to go in the completely
opposite direction.
BR,
Jani.
>
> Signed-off-by: Adrian Larumbe
> ---
> drivers/gpu/drm/i915/gt/intel_migrate.c | 1 -
> drivers/gpu/drm/i915/i915_drv.h | 5 +
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
> b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index a210c911905e..716f2f51c7f9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -16,7 +16,6 @@ struct insert_pte_data {
> };
>
> #define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */
> -#define GET_CCS_SIZE(i915, size) (HAS_FLAT_CCS(i915) ? (size) >> 8 : 0)
>
> static bool engine_supports_migration(struct intel_engine_cs *engine)
> {
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5623892ceab9..6b890a6674e4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -105,6 +105,7 @@
> #include "i915_request.h"
> #include "i915_scheduler.h"
> #include "gt/intel_timeline.h"
> +#include "gt/intel_gpu_commands.h"
> #include "i915_vma.h"
>
>
> @@ -1526,6 +1527,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_FLAT_CCS(dev_priv) (INTEL_INFO(dev_priv)->has_flat_ccs)
>
> +#define GET_CCS_SIZE(i915, size) (HAS_FLAT_CCS(i915) ? \
> + DIV_ROUND_UP(size, NUM_CCS_BYTES_PER_BLOCK) \
> + 0)
> +
> #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
>
> #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH] drm/i915: Lock dpt_obj around set_cache_level.
On 1/24/22 14:02, Maarten Lankhorst wrote:
set_cache_level may unbind the object, which will result in the below
lockdep splat:
<6> [184.578145] [IGT] kms_addfb_basic: starting subtest
addfb25-framebuffer-vs-set-tiling
<4> [184.578220] [ cut here ]
<4> [184.578221] WARN_ON(debug_locks &&
!(lock_is_held(&(&((obj)->base.resv)->lock.base)->dep_map) != 0))
<4> [184.578237] WARNING: CPU: 6 PID: 5544 at
drivers/gpu/drm/i915/i915_gem.c:123 i915_gem_object_unbind+0x4a9/0x510 [i915]
<4> [184.578323] Modules linked in: vgem drm_shmem_helper snd_hda_codec_hdmi
i915 mei_hdcp x86_pkg_temp_thermal snd_hda_intel coretemp crct10dif_pclmul
snd_intel_dspcfg crc32_pclmul ttm snd_hda_codec ghash_clmulni_intel snd_hwdep
drm_kms_helper snd_hda_core e1000e mei_me syscopyarea ptp snd_pcm sysfillrect mei
pps_core sysimgblt fb_sys_fops prime_numbers intel_lpss_pci smsc75xx usbnet mii
<4> [184.578349] CPU: 6 PID: 5544 Comm: kms_addfb_basic Not tainted
5.16.0-CI-Patchwork_22006+ #1
<4> [184.578351] Hardware name: Intel Corporation Alder Lake Client
Platform/AlderLake-P DDR4 RVP, BIOS ADLPFWI1.R00.2422.A00.2110131104 10/13/2021
<4> [184.578352] RIP: 0010:i915_gem_object_unbind+0x4a9/0x510 [i915]
<4> [184.578424] Code: 00 be ff ff ff ff 48 8d 78 68 e8 a2 6e 2b e1 85 c0 0f 85 b1 fb
ff ff 48 c7 c6 48 37 9e a0 48 c7 c7 d9 fc a1 a0 e8 a3 54 26 e1 <0f> 0b e9 97 fb ff ff
31 ed 48 8b 5c 24 58 65 48 33 1c 25 28 00 00
<4> [184.578426] RSP: 0018:c900013b3b68 EFLAGS: 00010286
<4> [184.578428] RAX: RBX: c900013b3bb0 RCX:
0001
<4> [184.578429] RDX: 8001 RSI: 8230b42d RDI:
<4> [184.578430] RBP: 888120e1 R08: R09:
c0007fff
<4> [184.578431] R10: 0001 R11: c900013b3980 R12:
8881176ea740
<4> [184.578432] R13: 888120e1 R14: R15:
0001
<4> [184.578433] FS: 7f65074f5e40() GS:8f30()
knlGS:
<4> [184.578435] CS: 0010 DS: ES: CR0: 80050033
<4> [184.578436] CR2: 7fff4420ede8 CR3: 00010c2f2005 CR4:
00770ee0
<4> [184.578437] PKRU: 5554
<4> [184.578438] Call Trace:
<4> [184.578439]
<4> [184.578440] ? dma_resv_iter_first_unlocked+0x78/0xf0
<4> [184.578447] intel_dpt_create+0x88/0x220 [i915]
<4> [184.578530] intel_framebuffer_init+0x5b8/0x620 [i915]
<4> [184.578612] intel_framebuffer_create+0x3d/0x60 [i915]
<4> [184.578691] intel_user_framebuffer_create+0x18f/0x2c0 [i915]
<4> [184.578775] drm_internal_framebuffer_create+0x36d/0x4c0
<4> [184.578779] drm_mode_addfb2+0x2f/0xd0
<4> [184.578781] ? drm_mode_addfb_ioctl+0x10/0x10
<4> [184.578784] drm_ioctl_kernel+0xac/0x140
<4> [184.578787] drm_ioctl+0x201/0x3d0
<4> [184.578789] ? drm_mode_addfb_ioctl+0x10/0x10
<4> [184.578796] __x64_sys_ioctl+0x6a/0xa0
<4> [184.578800] do_syscall_64+0x37/0xb0
<4> [184.578803] entry_SYSCALL_64_after_hwframe+0x44/0xae
<4> [184.578805] RIP: 0033:0x7f6506736317
<4> [184.578807] Code: b3 66 90 48 8b 05 71 4b 2d 00 64 c7 00 26 00 00 00 48 c7 c0 ff
ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73
01 c3 48 8b 0d 41 4b 2d 00 f7 d8 64 89 01 48
<4> [184.578808] RSP: 002b:7fff44211a98 EFLAGS: 0246 ORIG_RAX:
0010
<4> [184.578810] RAX: ffda RBX: 0006 RCX:
7f6506736317
<4> [184.578811] RDX: 7fff44211b30 RSI: c06864b8 RDI:
0006
<4> [184.578812] RBP: 7fff44211b30 R08: 7fff44311170 R09:
<4> [184.578813] R10: 0008 R11: 0246 R12:
c06864b8
<4> [184.578813] R13: 0006 R14: R15:
<4> [184.578819]
<4> [184.578820] irq event stamp: 47931
<4> [184.578821] hardirqs last enabled at (47937): []
__up_console_sem+0x62/0x70
<4> [184.578824] hardirqs last disabled at (47942): []
__up_console_sem+0x47/0x70
<4> [184.578826] softirqs last enabled at (47340): []
__do_softirq+0x32d/0x493
<4> [184.578828] softirqs last disabled at (47335): []
irq_exit_rcu+0xa6/0xe0
<4> [184.578830] ---[ end trace f17ec219f892c7d4 ]---
Fixes: 0f341974cbc2 ("drm/i915: Add i915_vma_unbind_unlocked, and take obj lock for
i915_vma_unbind, v2.")
Signed-off-by: Maarten Lankhorst
Testcase: kms_addfb_basic
---
drivers/gpu/drm/i915/display/intel_dpt.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
LGTM. Reviewed-by: Thomas Hellström
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
b/drivers/gpu/drm/i915/display/intel_dpt.c
index 63a83d5f85a1..c2f8f853db90 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -253,7 +253,11 @@ intel_dpt_create(struct intel_framebuffer *fb)
if (IS_ERR(dpt_obj))
return ERR_CAST(dpt_obj);
- ret = i915_gem_object_set_cache_level(dpt_obj, I915_CACHE_NONE);
+ ret =
Re: [Intel-gfx] [PATCH 11/11] drm/vmwgfx: remove vmw_wait_dma_fence
On Mon, 2022-01-24 at 14:03 +0100, Christian König wrote: > Decomposing fence containers don't seem to make any sense here. > > So just remove the function entirely and call dma_fence_wait() > directly. > > Signed-off-by: Christian König > Cc: VMware Graphics > Cc: Zack Rusin Looks good. That's a great cleanup. Reviewed-by: Zack Rusin
[Intel-gfx] [PATCH 3/4] drm/i915/execlists: Fix execlists request cancellation corner case
More than 1 request can be submitted to a single ELSP at a time if
multiple requests are ready run to on the same context. When a request
is canceled it is marked bad, an idle pulse is triggered to the engine
(high priority kernel request), the execlists scheduler sees that
running request is bad and sets preemption timeout to minimum value (1
ms). This fails to work if multiple requests are combined on the ELSP as
only the most recent request is stored in the execlists schedule (the
request stored in the ELSP isn't marked bad, thus preemption timeout
isn't set to the minimum value). If the preempt timeout is configured to
zero, the engine is permanently hung. This is shown by an upcoming
selftest.
To work around this, mark the idle pulse with a flag to force a preempt
with the minimum value.
Fixes: 38b237eab2bc7 ("drm/i915: Individual request cancellation")
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 23 +++
.../gpu/drm/i915/gt/intel_engine_heartbeat.h | 1 +
.../drm/i915/gt/intel_execlists_submission.c | 18 ++-
drivers/gpu/drm/i915/i915_request.h | 6 +
4 files changed, 38 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index a3698f611f457..efd1c719b4072 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -243,7 +243,8 @@ void intel_engine_init_heartbeat(struct intel_engine_cs
*engine)
INIT_DELAYED_WORK(>heartbeat.work, heartbeat);
}
-static int __intel_engine_pulse(struct intel_engine_cs *engine)
+static int __intel_engine_pulse(struct intel_engine_cs *engine,
+ bool force_preempt)
{
struct i915_sched_attr attr = { .priority = I915_PRIORITY_BARRIER };
struct intel_context *ce = engine->kernel_context;
@@ -258,6 +259,8 @@ static int __intel_engine_pulse(struct intel_engine_cs
*engine)
return PTR_ERR(rq);
__set_bit(I915_FENCE_FLAG_SENTINEL, >fence.flags);
+ if (force_preempt)
+ __set_bit(I915_FENCE_FLAG_FORCE_PREEMPT, >fence.flags);
heartbeat_commit(rq, );
GEM_BUG_ON(rq->sched.attr.priority < I915_PRIORITY_BARRIER);
@@ -299,7 +302,7 @@ int intel_engine_set_heartbeat(struct intel_engine_cs
*engine,
/* recheck current execution */
if (intel_engine_has_preemption(engine)) {
- err = __intel_engine_pulse(engine);
+ err = __intel_engine_pulse(engine, false);
if (err)
set_heartbeat(engine, saved);
}
@@ -312,7 +315,8 @@ int intel_engine_set_heartbeat(struct intel_engine_cs
*engine,
return err;
}
-int intel_engine_pulse(struct intel_engine_cs *engine)
+static int _intel_engine_pulse(struct intel_engine_cs *engine,
+ bool force_preempt)
{
struct intel_context *ce = engine->kernel_context;
int err;
@@ -325,7 +329,7 @@ int intel_engine_pulse(struct intel_engine_cs *engine)
err = -EINTR;
if (!mutex_lock_interruptible(>timeline->mutex)) {
- err = __intel_engine_pulse(engine);
+ err = __intel_engine_pulse(engine, force_preempt);
mutex_unlock(>timeline->mutex);
}
@@ -334,6 +338,17 @@ int intel_engine_pulse(struct intel_engine_cs *engine)
return err;
}
+int intel_engine_pulse(struct intel_engine_cs *engine)
+{
+ return _intel_engine_pulse(engine, false);
+}
+
+
+int intel_engine_pulse_force_preempt(struct intel_engine_cs *engine)
+{
+ return _intel_engine_pulse(engine, true);
+}
+
int intel_engine_flush_barriers(struct intel_engine_cs *engine)
{
struct i915_sched_attr attr = { .priority = I915_PRIORITY_MIN };
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
index 5da6d809a87a2..d9c8386754cb3 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
@@ -21,6 +21,7 @@ void intel_gt_park_heartbeats(struct intel_gt *gt);
void intel_gt_unpark_heartbeats(struct intel_gt *gt);
int intel_engine_pulse(struct intel_engine_cs *engine);
+int intel_engine_pulse_force_preempt(struct intel_engine_cs *engine);
int intel_engine_flush_barriers(struct intel_engine_cs *engine);
#endif /* INTEL_ENGINE_HEARTBEAT_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 960a9aaf4f3a3..f0c2024058731 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1222,26 +1222,29 @@ static void record_preemption(struct
intel_engine_execlists *execlists)
}
static unsigned long
[Intel-gfx] [PATCH 2/4] drm/i915/guc: Cancel requests immediately
Change the preemption timeout to the smallest possible value (1 us) when
disabling scheduling to cancel a request and restore it after
cancellation. This not only cancels the request as fast as possible, it
fixes a bug where the preemption timeout is 0 which results in the
schedule disable hanging forever.
Reported-by: Jani Saarinen
Fixes: 62eaf0ae217d4 ("drm/i915/guc: Support request cancellation")
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/4960
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 5 ++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 46 +++
2 files changed, 31 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 30cd81ad8911a..730998823dbea 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -198,6 +198,11 @@ struct intel_context {
* each priority bucket
*/
u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
+ /**
+* @preemption_timeout: preemption timeout of the context, used
+* to restore this value after request cancellation
+*/
+ u32 preemption_timeout;
} guc_state;
struct {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 3918f1be114fa..966947c450253 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2147,7 +2147,8 @@ static inline u32 get_children_join_value(struct
intel_context *ce,
return __get_parent_scratch(ce)->join[child_index].semaphore;
}
-static void guc_context_policy_init(struct intel_engine_cs *engine,
+static void guc_context_policy_init(struct intel_context *ce,
+ struct intel_engine_cs *engine,
struct guc_lrc_desc *desc)
{
desc->policy_flags = 0;
@@ -2157,7 +2158,8 @@ static void guc_context_policy_init(struct
intel_engine_cs *engine,
/* NB: For both of these, zero means disabled. */
desc->execution_quantum = engine->props.timeslice_duration_ms * 1000;
- desc->preemption_timeout = engine->props.preempt_timeout_ms * 1000;
+ ce->guc_state.preemption_timeout = engine->props.preempt_timeout_ms *
1000;
+ desc->preemption_timeout = ce->guc_state.preemption_timeout;
}
static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
@@ -2193,7 +2195,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
bool loop)
desc->hw_context_desc = ce->lrc.lrca;
desc->priority = ce->guc_state.prio;
desc->context_flags = CONTEXT_REGISTRATION_FLAG_KMD;
- guc_context_policy_init(engine, desc);
+ guc_context_policy_init(ce, engine, desc);
/*
* If context is a parent, we need to register a process descriptor
@@ -2226,7 +2228,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
bool loop)
desc->hw_context_desc = child->lrc.lrca;
desc->priority = ce->guc_state.prio;
desc->context_flags = CONTEXT_REGISTRATION_FLAG_KMD;
- guc_context_policy_init(engine, desc);
+ guc_context_policy_init(child, engine, desc);
}
clear_children_join_go_memory(ce);
@@ -2409,6 +2411,19 @@ static u16 prep_context_pending_disable(struct
intel_context *ce)
return ce->guc_id.id;
}
+static void __guc_context_set_preemption_timeout(struct intel_guc *guc,
+u16 guc_id,
+u32 preemption_timeout)
+{
+ u32 action[] = {
+ INTEL_GUC_ACTION_SET_CONTEXT_PREEMPTION_TIMEOUT,
+ guc_id,
+ preemption_timeout
+ };
+
+ intel_guc_send_busy_loop(guc, action, ARRAY_SIZE(action), 0, true);
+}
+
static struct i915_sw_fence *guc_context_block(struct intel_context *ce)
{
struct intel_guc *guc = ce_to_guc(ce);
@@ -2442,8 +2457,10 @@ static struct i915_sw_fence *guc_context_block(struct
intel_context *ce)
spin_unlock_irqrestore(>guc_state.lock, flags);
- with_intel_runtime_pm(runtime_pm, wakeref)
+ with_intel_runtime_pm(runtime_pm, wakeref) {
+ __guc_context_set_preemption_timeout(guc, guc_id, 1);
__guc_context_sched_disable(guc, ce, guc_id);
+ }
return >guc_state.blocked;
}
@@ -2492,8 +2509,10 @@ static void guc_context_unblock(struct intel_context *ce)
spin_unlock_irqrestore(>guc_state.lock, flags);
- if (enable) {
- with_intel_runtime_pm(runtime_pm, wakeref)
+ with_intel_runtime_pm(runtime_pm, wakeref) {
+
[Intel-gfx] [PATCH 1/4] drm/i915: Add request cancel low level trace point
Add request cancel trace point guarded by
CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINT.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context.h | 1 +
drivers/gpu/drm/i915/i915_trace.h | 10 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
b/drivers/gpu/drm/i915/gt/intel_context.h
index d8c74bbf9aae2..3aed4d77f116c 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -124,6 +124,7 @@ intel_context_is_pinned(struct intel_context *ce)
static inline void intel_context_cancel_request(struct intel_context *ce,
struct i915_request *rq)
{
+ trace_i915_request_cancel(rq);
GEM_BUG_ON(!ce->ops->cancel_request);
return ce->ops->cancel_request(ce, rq);
}
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index 37b5c9e9d260e..d0a11a8bb0ca3 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -324,6 +324,11 @@ DEFINE_EVENT(i915_request, i915_request_add,
);
#if defined(CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS)
+DEFINE_EVENT(i915_request, i915_request_cancel,
+TP_PROTO(struct i915_request *rq),
+TP_ARGS(rq)
+);
+
DEFINE_EVENT(i915_request, i915_request_guc_submit,
TP_PROTO(struct i915_request *rq),
TP_ARGS(rq)
@@ -497,6 +502,11 @@ DEFINE_EVENT(intel_context, intel_context_do_unpin,
#else
#if !defined(TRACE_HEADER_MULTI_READ)
+static inline void
+trace_i915_request_cancel(struct i915_request *rq)
+{
+}
+
static inline void
trace_i915_request_guc_submit(struct i915_request *rq)
{
--
2.34.1
[Intel-gfx] [PATCH 0/4] Fix up request cancel
Fix request cancellation + add request cancel low level trace point. v2: - Update cancel reset selftest preemption timeout value to zero - Fix bug in execlists cancel code Signed-off-by: Matthew Brost Matthew Brost (4): drm/i915: Add request cancel low level trace point drm/i915/guc: Cancel requests immediately drm/i915/execlists: Fix execlists request cancellation corner case drm/i915/selftests: Set preemption timeout to zero in cancel reset test drivers/gpu/drm/i915/gt/intel_context.h | 1 + drivers/gpu/drm/i915/gt/intel_context_types.h | 5 ++ .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 23 -- .../gpu/drm/i915/gt/intel_engine_heartbeat.h | 1 + .../drm/i915/gt/intel_execlists_submission.c | 18 +--- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 46 +++ drivers/gpu/drm/i915/i915_request.h | 6 +++ drivers/gpu/drm/i915/i915_trace.h | 10 drivers/gpu/drm/i915/selftests/i915_request.c | 7 +-- 9 files changed, 84 insertions(+), 33 deletions(-) -- 2.34.1
[Intel-gfx] [PATCH 4/4] drm/i915/selftests: Set preemption timeout to zero in cancel reset test
Set the preemption timeout to zero to prove that request cancellation with preemption disabled works. Also this seals a race between a possible preemption and request cancellation. Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/selftests/i915_request.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index 2a99dd7c2fe8a..e522e24129f9b 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -790,8 +790,9 @@ static int __cancel_completed(struct intel_engine_cs *engine) * wait for spinner to start, create a NOP request and submit it, cancel the * spinner, wait for spinner to complete and verify it failed with an error, * finally wait for NOP request to complete verify it succeeded without an - * error. Preemption timeout also reduced / restored so test runs in a timely - * maner. + * error. Preemption timeout also set to zero to ensure cancellation works with + * preemption disabled and to ensure the NOP request doesn't trigger a + * preemption on the spinner sealing a race between a preemption and the cancel. */ static int __cancel_reset(struct drm_i915_private *i915, struct intel_engine_cs *engine) @@ -807,7 +808,7 @@ static int __cancel_reset(struct drm_i915_private *i915, return 0; preempt_timeout_ms = engine->props.preempt_timeout_ms; - engine->props.preempt_timeout_ms = 100; + engine->props.preempt_timeout_ms = 0; if (igt_spinner_init(, engine->gt)) goto out_restore; -- 2.34.1
Re: [Intel-gfx] [PATCH 0/9] drm/i915/display: drm device based logging conversions
On Fri, 21 Jan 2022, Ville Syrjälä wrote: > On Fri, Jan 21, 2022 at 03:00:29PM +0200, Jani Nikula wrote: >> Purge some accumulated drm device based logging changes from my local >> branches. >> >> Jani Nikula (9): >> drm/i915/snps: convert to drm device based logging >> drm/i915/pps: convert to drm device based logging >> drm/i915/hotplug: convert to drm device based logging >> drm/i915/dp: convert to drm device based logging >> drm/i915/plane: convert to drm device based logging and WARN >> drm/i915/sprite: convert to drm device based logging >> drm/i915/lspcon: convert to drm device based logging >> drm/i915/cdclk: update intel_dump_cdclk_config() logging >> drm/i915/cdclk: convert to drm device based logging > > Eyeballed it quickly. Looks all right to me. > > Series is > Reviewed-by: Ville Syrjälä Thanks, pushed to drm-intel-next. BR, Jani. > >> >> .../gpu/drm/i915/display/intel_atomic_plane.c | 5 +- >> drivers/gpu/drm/i915/display/intel_cdclk.c| 23 +-- >> drivers/gpu/drm/i915/display/intel_cdclk.h| 3 +- >> drivers/gpu/drm/i915/display/intel_display.c | 2 +- >> .../drm/i915/display/intel_display_power.c| 2 +- >> drivers/gpu/drm/i915/display/intel_dp.c | 35 +++-- >> drivers/gpu/drm/i915/display/intel_hotplug.c | 14 +- >> drivers/gpu/drm/i915/display/intel_lspcon.c | 142 ++ >> drivers/gpu/drm/i915/display/intel_pps.c | 22 +-- >> drivers/gpu/drm/i915/display/intel_snps_phy.c | 29 ++-- >> drivers/gpu/drm/i915/display/intel_sprite.c | 24 +-- >> .../drm/i915/display/skl_universal_plane.c| 10 +- >> 12 files changed, 169 insertions(+), 142 deletions(-) >> >> -- >> 2.30.2 -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
In terms of async flip optimization we don't to allocate
extra ddb space, so lets skip it.
v2: - Extracted min ddb async flip check to separate function
(Ville Syrjälä)
- Used this function to prevent false positive WARN
to be triggered(Ville Syrjälä)
v3: - Renamed dg2_need_min_ddb to need_min_ddb thus making
it more universal.
- Also used DISPLAY_VER instead of IS_DG2(Ville Syrjälä)
- Use rate = 0 instead of just setting extra = 0, thus
letting other planes to use extra ddb and avoiding WARN
(Ville Syrjälä)
v4: - Renamed needs_min_ddb as s/needs/use/ to match
the wm0 counterpart(Ville Syrjälä)
- Added plane->async_flip check to use_min_ddb(now
passing plane as a parameter to do that)(Ville Syrjälä)
- Account for use_min_ddb also when calculating total data rate
(Ville Syrjälä)
v5:
- Use for_each_intel_plane_on_crtc instead of for_each_intel_plane_id
to get plane->async_flip check and account for all planes(Ville Syrjälä)
- Fix line wrapping(Ville Syrjälä)
- Set plane data rate conditionally, avoiding on redundant assignment
(Ville Syrjälä)
- Removed redundant whitespace(Ville Syrjälä)
- Handle use_min_ddb case in skl_plane_relative_data_rate instead of
icl_get_total_relative_data_rate(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0bb4c941f950..bb147e5a77b6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4906,6 +4906,16 @@ static u8 skl_compute_dbuf_slices(struct intel_crtc
*crtc, u8 active_pipes)
return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0;
}
+static bool use_min_ddb(const struct intel_crtc_state *crtc_state,
+ struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ return DISPLAY_VER(i915) >= 13 &&
+ crtc_state->uapi.async_flip &&
+ plane->async_flip;
+}
+
static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
struct intel_plane *plane)
{
@@ -4934,6 +4944,14 @@ skl_plane_relative_data_rate(const struct
intel_crtc_state *crtc_state,
if (plane->id == PLANE_CURSOR)
return 0;
+ /*
+* We calculate extra ddb based on ratio plane rate/total data rate
+* in case, in some cases we should not allocate extra ddb for the
plane,
+* so do not count its data rate, if this is the case.
+*/
+ if (use_min_ddb(crtc_state, plane))
+ return 0;
+
if (color_plane == 1 &&
!intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
return 0;
--
2.24.1.485.gad05a3d8e5
