[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Use drm_clflush* instead of clflush

== Series Details == Series: Use drm_clflush* instead of clflush URL : https://patchwork.freedesktop.org/series/100717/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use drm_clflush* instead of clflush

== Series Details == Series: Use drm_clflush* instead of clflush URL : https://patchwork.freedesktop.org/series/100717/ State : warning == Summary == $ dim checkpatch origin/drm-tip 86596975e130 drm: Add arch arm64 for drm_clflush_virt_range -:35: WARNING:LINE_SPACING: Missing a blank line aft

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Do not complain about stale reset notifications (rev3)

== Series Details == Series: drm/i915/guc: Do not complain about stale reset notifications (rev3) URL : https://patchwork.freedesktop.org/series/2/ State : success == Summary == CI Bug Log - changes from CI_DRM_11285 -> Patchwork_22406

Re: [Intel-gfx] [PATCH v5 07/10] drm/i915/guc: Extract GuC error capture lists on G2H notification.

Folks, a brief update: over the last few weeks of internal reviews, testing and debug, another redesign has been implemented for this patch (the extraction of error capture information). When experiencing back to back error capture notifications (as part of multiple dependent engine resets), if a

[Intel-gfx] ✗ Fi.CI.BUILD: failure for GuC HWCONFIG with documentation (rev6)

== Series Details == Series: GuC HWCONFIG with documentation (rev6) URL : https://patchwork.freedesktop.org/series/99787/ State : failure == Summary == Applying: drm/i915/guc: Add fetch of hwconfig table Applying: drm/i915/uapi: Add query for hwconfig blob Applying: drm/i915/uapi: Add struct d

Re: [Intel-gfx] [PATCH v2] drm/i915/psr: Set "SF Partial Frame Enable" also on full update

Addressed comments from Jose and Paul in version 3. On Thu, 2022-02-24 at 15:02 -0500, Lyude Paul wrote: > Also - I realized this is missing an appropriate Fixes: tag for the > commit > that enabled PSR2 selective fetch on tigerlake in the first place > > On Wed, 2022-02-23 at 17:32 +, Souza,

[Intel-gfx] [PATCH v3] drm/i915/psr: Set "SF Partial Frame Enable" also on full update

Currently we are observing occasional screen flickering when PSR2 selective fetch is enabled. More specifically glitch seems to happen on full frame update when cursor moves to coords x = -1 or y = -1. According to Bspec SF Single full frame should not be set if SF Partial Frame Enable is not set.

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v6,1/2] drm/vrr: Set VRR capable prop only if it is attached to connector

== Series Details == Series: series starting with [v6,1/2] drm/vrr: Set VRR capable prop only if it is attached to connector URL : https://patchwork.freedesktop.org/series/100712/ State : success == Summary == CI Bug Log - changes from CI_DRM_11285 -> Patchwork_22405 =

Re: [Intel-gfx] [PATCH v5 1/4] drm/i915/guc: Add fetch of hwconfig table

John Harrison writes: > On 2/22/2022 02:36, Jordan Justen wrote: >> From: John Harrison >> >> Implement support for fetching the hardware description table from the >> GuC. The call is made twice - once without a destination buffer to >> query the size and then a second time to fill in the buffe

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v6,1/2] drm/vrr: Set VRR capable prop only if it is attached to connector

== Series Details == Series: series starting with [v6,1/2] drm/vrr: Set VRR capable prop only if it is attached to connector URL : https://patchwork.freedesktop.org/series/100712/ State : warning == Summary == $ dim checkpatch origin/drm-tip 783e65f81a2e drm/vrr: Set VRR capable prop only if

[Intel-gfx] ✓ Fi.CI.BAT: success for Prep work for next GuC release (rev3)

== Series Details == Series: Prep work for next GuC release (rev3) URL : https://patchwork.freedesktop.org/series/99805/ State : success == Summary == CI Bug Log - changes from CI_DRM_11285 -> Patchwork_22404 Summary --- **SUCCESS**

[Intel-gfx] ✓ Fi.CI.IGT: success for hda/i915: split wait for component binding

== Series Details == Series: hda/i915: split wait for component binding URL : https://patchwork.freedesktop.org/series/100661/ State : success == Summary == CI Bug Log - changes from CI_DRM_11277_full -> Patchwork_22391_full Summary ---

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Prep work for next GuC release (rev3)

== Series Details == Series: Prep work for next GuC release (rev3) URL : https://patchwork.freedesktop.org/series/99805/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Allow users to disable PSR2 (rev2)

== Series Details == Series: drm/i915/display: Allow users to disable PSR2 (rev2) URL : https://patchwork.freedesktop.org/series/100658/ State : success == Summary == CI Bug Log - changes from CI_DRM_11285 -> Patchwork_22403 Summary ---

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Optimize CSC updates for ilk+

== Series Details == Series: drm/i915: Optimize CSC updates for ilk+ URL : https://patchwork.freedesktop.org/series/100693/ State : success == Summary == CI Bug Log - changes from CI_DRM_11285 -> Patchwork_22402 Summary --- **SUCCESS

[Intel-gfx] [PATCH v12 0/6] Use drm_clflush* instead of clflush

This patch series re-work a few i915 functions to use drm_clflush_virt_range instead of calling clflush or clflushopt directly. This will prevent errors when building for non-x86 architectures. v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_status_page and added more patches to convert addi

[Intel-gfx] [PATCH v12 6/6] drm/i915/gt: replace cache_clflush_range

Replace all occurrence of cache_clflush_range with drm_clflush_virt_range. This will prevent compile errors on non-x86 platforms. Signed-off-by: Michael Cheng Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++-- drivers/gpu/drm/i915/gt/intel_execli

[Intel-gfx] [PATCH v12 5/6] drm/i915/: Re-work clflush_write32

Use drm_clflush_virt_range instead of clflushopt and remove the memory barrier, since drm_clflush_virt_range takes care of that. v2(Michael Cheng): Use sizeof(*addr) instead of sizeof(addr) to get the actual size of the page. Thanks to Matt Roper for pointing

[Intel-gfx] [PATCH v12 1/6] drm: Add arch arm64 for drm_clflush_virt_range

Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou performs a flush by first performing a clean, follow by an invalidation operation. v2 (Michael Cheng): Use correct macro for cleaning and invalidation the dcache. Thanks Tvrtko for the suggestion. v3 (Michael

[Intel-gfx] [PATCH v12 3/6] drm/i915/gt: Drop invalidate_csb_entries

Drop invalidate_csb_entries and directly call drm_clflush_virt_range. This allows for one less function call, and prevent complier errors when building for non-x86 architectures. v2(Michael Cheng): Drop invalidate_csb_entries function and directly invoke drm_clflush_virt_range.

[Intel-gfx] [PATCH v12 4/6] drm/i915/gt: Re-work reset_csb

Use drm_clflush_virt_range instead of directly invoking clflush. This will prevent compiler errors when building for non-x86 architectures. v2(Michael Cheng): Remove extra clflush v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range takes care of it. v4(Michae

[Intel-gfx] [PATCH v12 2/6] drm/i915/gt: Re-work intel_write_status_page

Re-work intel_write_status_page to use drm_clflush_virt_range. This will prevent compiler errors when building for non-x86 architectures. Signed-off-by: Michael Cheng Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_engine.h | 13 - 1 file changed, 4 insertions(+), 9 deleti

[Intel-gfx] [PATCH] drm/i915/guc: Add fetch of hwconfig table

From: John Harrison Implement support for fetching the hardware description table from the GuC. The call is made twice - once without a destination buffer to query the size and then a second time to fill in the buffer. The table is stored in the GT structure so that it can be fetched once at dri

Re: [Intel-gfx] [PATCH v5 1/4] drm/i915/guc: Add fetch of hwconfig table

On 2/22/2022 02:36, Jordan Justen wrote: From: John Harrison Implement support for fetching the hardware description table from the GuC. The call is made twice - once without a destination buffer to query the size and then a second time to fill in the buffer. Note that the table is only availa

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for GuC HWCONFIG with documentation (rev5)

On 2/22/2022 04:03, Patchwork wrote: Project List - Patchwork *Patch Details* *Series:* GuC HWCONFIG with documentation (rev5) *URL:* https://patchwork.freedesktop.org/series/99787/ *State:*success *Details:* https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22348/index.html

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Check stolen memory size before calling drm_mm_init (rev4)

== Series Details == Series: drm/i915: Check stolen memory size before calling drm_mm_init (rev4) URL : https://patchwork.freedesktop.org/series/99917/ State : success == Summary == CI Bug Log - changes from CI_DRM_11277_full -> Patchwork_22390_full

[Intel-gfx] [PATCH v3] drm/i915/guc: Do not complain about stale reset notifications

From: John Harrison It is possible for reset notifications to arrive for a context that is in the process of being banned. So don't flag these as an error, just report it as informational (because it is still useful to know that resets are happening even if they are being ignored). v2: Better wo

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Set "SF Partial Frame Enable" also on full update (rev3)

== Series Details == Series: drm/i915/psr: Set "SF Partial Frame Enable" also on full update (rev3) URL : https://patchwork.freedesktop.org/series/100633/ State : success == Summary == CI Bug Log - changes from CI_DRM_11284 -> Patchwork_22401 ===

[Intel-gfx] [PATCH v6 1/2] drm/vrr: Set VRR capable prop only if it is attached to connector

VRR capable property is not attached by default to the connector It is attached only if VRR is supported. So if the driver tries to call drm core set prop function without it being attached that causes NULL dereference. Cc: Jani Nikula Cc: Ville Syrjälä Cc: dri-de...@lists.freedesktop.org Signed

[Intel-gfx] [PATCH v6 2/2] drm/i915/display/vrr: Reset VRR capable property on a long hpd

With some VRR panels, user can turn VRR ON/OFF on the fly from the panel settings. When VRR is turned OFF ,sends a long HPD to the driver clearing the Ignore MSA bit in the DPCD. Currently the driver parses that onevery HPD but fails to reset the corresponding VRR Capable Connector property. Henc

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/psr: Set "SF Partial Frame Enable" also on full update (rev3)

== Series Details == Series: drm/i915/psr: Set "SF Partial Frame Enable" also on full update (rev3) URL : https://patchwork.freedesktop.org/series/100633/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separa

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dg2: Skip output init on PHY calibration failure

== Series Details == Series: drm/i915/dg2: Skip output init on PHY calibration failure URL : https://patchwork.freedesktop.org/series/100650/ State : success == Summary == CI Bug Log - changes from CI_DRM_11277_full -> Patchwork_22388_full

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: s/JSP2/ICP2/ PCH

== Series Details == Series: drm/i915: s/JSP2/ICP2/ PCH URL : https://patchwork.freedesktop.org/series/100689/ State : success == Summary == CI Bug Log - changes from CI_DRM_11283 -> Patchwork_22400 Summary --- **SUCCESS** No regr

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: s/JSP2/ICP2/ PCH

== Series Details == Series: drm/i915: s/JSP2/ICP2/ PCH URL : https://patchwork.freedesktop.org/series/100689/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: s/JSP2/ICP2/ PCH

== Series Details == Series: drm/i915: s/JSP2/ICP2/ PCH URL : https://patchwork.freedesktop.org/series/100689/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0862321e317b drm/i915: s/JSP2/ICP2/ PCH -:9: WARNING:REPEATED_WORD: Possible repeated word: 'to' #9: This JSP2 PCH actua

[Intel-gfx] [PATCH v2 7/8] drm/i915/guc: Drop obsolete H2G definitions

From: John Harrison The CTB registration process changed significantly a while back using a single KLV based H2G. So drop the original and now obsolete H2G definitions. Signed-off-by: John Harrison Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 2 --

[Intel-gfx] [PATCH v2 3/8] drm/i915/guc: Better name for context id limit

From: John Harrison The LRC descriptor pool is going away. So, stop using it as the limit for how many context ids are available. Instead, size the pool according to the number of contexts allowed. Note that this is just a naming change, the actual limit is identical in value. While at it, also

[Intel-gfx] [PATCH v2 4/8] drm/i915/guc: Split guc_lrc_desc_pin apart

From: John Harrison The LRC descriptor pool is going away. Further, the function that was populating it was also doing a bunch of logic about the context registration sequence. So, split that code apart into separate state setup and try to register functions. Note that some of those 'try to regis

[Intel-gfx] [PATCH v2 1/8] drm/i915/guc: Do not conflate lrc_desc with GuC id for registration

From: John Harrison The LRC descriptor pool is going away. So, stop using it as a check for context registration, use the GuC id instead (being the thing that actually gets registered with the GuC). Also, rename the set/clear/query helper functions for context id mappings to better reflect their

[Intel-gfx] [PATCH v2 2/8] drm/i915/guc: Add an explicit 'submission_initialized' flag

From: John Harrison The LRC descriptor pool is going away. So, stop using it as a check for whether submission has been initialised or not. Signed-off-by: John Harrison Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 ++ drivers/gpu/drm/i915/gt/uc

[Intel-gfx] [PATCH v2 6/8] drm/i915/guc: Rename desc_idx to ctx_id

From: John Harrison The LRC descriptor pool is going away. So, stop naming context ids as descriptor pool indecies. While at it, add a bunch of missing line feeds to some error messages. Signed-off-by: John Harrison Reviewed-by: Daniele Ceraolo Spurio --- .../gpu/drm/i915/gt/uc/intel_guc_sub

[Intel-gfx] [PATCH v2 5/8] drm/i915/guc: Move lrc desc setup to where it is needed

From: John Harrison The LRC descriptor was being initialised early on in the context registration sequence. It could then be determined that the actual registration needs to be delayed and the descriptor would be wiped out. This is inefficient, so move the setup to later in the process after the

[Intel-gfx] [PATCH v2 8/8] drm/i915/guc: Fix potential invalid pointer dereferences when decoding G2Hs

From: John Harrison Some G2H handlers were reading the context id field from the payload before checking the payload met the minimum length required. Signed-off-by: John Harrison Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 -- 1 file chang

[Intel-gfx] [PATCH v2 0/8] Prep work for next GuC release

From: John Harrison The next GuC firmware release includes some significant backwards breaking API changes. One such is that there is no longer an LRC descriptor pool. A bunch of prep work for that change can be done in advance - the descriptor pool was being used for things it shouldn't really h

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Be more gentle when exiting non-persistent contexts (rev3)

== Series Details == Series: drm/i915: Be more gentle when exiting non-persistent contexts (rev3) URL : https://patchwork.freedesktop.org/series/93420/ State : success == Summary == CI Bug Log - changes from CI_DRM_11283 -> Patchwork_22399

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: make a handful of read-only arrays static const (rev2)

== Series Details == Series: drm/i915: make a handful of read-only arrays static const (rev2) URL : https://patchwork.freedesktop.org/series/100570/ State : success == Summary == CI Bug Log - changes from CI_DRM_11277_full -> Patchwork_22386_full ===

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Be more gentle when exiting non-persistent contexts (rev3)

== Series Details == Series: drm/i915: Be more gentle when exiting non-persistent contexts (rev3) URL : https://patchwork.freedesktop.org/series/93420/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separatel

[Intel-gfx] ✗ Fi.CI.BAT: failure for Replace VT-d workaround with guard pages (rev3)

== Series Details == Series: Replace VT-d workaround with guard pages (rev3) URL : https://patchwork.freedesktop.org/series/97492/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11283 -> Patchwork_22398 Summary --- **

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Replace VT-d workaround with guard pages (rev3)

== Series Details == Series: Replace VT-d workaround with guard pages (rev3) URL : https://patchwork.freedesktop.org/series/97492/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/cdclk: Add cdclk check to atomic check

== Series Details == Series: drm/i915/cdclk: Add cdclk check to atomic check URL : https://patchwork.freedesktop.org/series/100671/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/mm: Add an iterator to optimally walk over holes suitable for an allocation (rev4)

== Series Details == Series: drm/mm: Add an iterator to optimally walk over holes suitable for an allocation (rev4) URL : https://patchwork.freedesktop.org/series/100136/ State : success == Summary == CI Bug Log - changes from CI_DRM_11282 -> Patchwork_22396 ==

Re: [Intel-gfx] [PATCH 5/8] drm/i915/guc: Move lrc desc setup to where it is needed

On 2/23/2022 18:03, Ceraolo Spurio, Daniele wrote: On 2/23/2022 12:23 PM, John Harrison wrote: On 2/22/2022 17:12, Ceraolo Spurio, Daniele wrote: On 2/17/2022 3:52 PM, john.c.harri...@intel.com wrote: From: John Harrison The LRC descriptor was being initialised early on in the context regist

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/mm: Add an iterator to optimally walk over holes suitable for an allocation (rev4)

== Series Details == Series: drm/mm: Add an iterator to optimally walk over holes suitable for an allocation (rev4) URL : https://patchwork.freedesktop.org/series/100136/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/mm: Add an iterator to optimally walk over holes suitable for an allocation (rev4)

== Series Details == Series: drm/mm: Add an iterator to optimally walk over holes suitable for an allocation (rev4) URL : https://patchwork.freedesktop.org/series/100136/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1a82dfc67642 drm/mm: Add an iterator to optimally walk over

Re: [Intel-gfx] [PATCH 0/3] drm/helpers: Make the suballocation manager drm generic.

Op 23-02-2022 om 16:11 schreef Christian König: > Am 23.02.22 um 14:51 schrieb Maarten Lankhorst: >> Second version of the patch. I didn't fix the copyright (which ame up >> in the previous version), as I feel the original author should send a >> patch for that. >> >> I've made the suballocator int

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/helpers: Make the suballocation manager drm generic. (rev2)

== Series Details == Series: drm/helpers: Make the suballocation manager drm generic. (rev2) URL : https://patchwork.freedesktop.org/series/99713/ State : success == Summary == CI Bug Log - changes from CI_DRM_11277_full -> Patchwork_22385_full =

[Intel-gfx] [PATCH v2] drm/i915/display: Allow users to disable PSR2

Some users are suffering with PSR2 issues that are under debug or issues that were root caused to panel firmware bugs, to make life of those users easier here adding a option to disable PSR2 with kernel parameters so they can still benefit from PSR1 power savings. Using the same enable_psr that is

Re: [Intel-gfx] [PATCH 0/3] Improve anti-pre-emption w/a for compute workloads

On 2/23/2022 04:00, Tvrtko Ursulin wrote: On 23/02/2022 02:22, John Harrison wrote: On 2/22/2022 01:53, Tvrtko Ursulin wrote: On 18/02/2022 21:33, john.c.harri...@intel.com wrote: From: John Harrison Compute workloads are inherently not pre-emptible on current hardware. Thus the pre-emption

Re: [Intel-gfx] [PATCH v2] drm/i915/psr: Set "SF Partial Frame Enable" also on full update

Also - I realized this is missing an appropriate Fixes: tag for the commit that enabled PSR2 selective fetch on tigerlake in the first place On Wed, 2022-02-23 at 17:32 +, Souza, Jose wrote: > On Wed, 2022-02-23 at 14:48 +0200, Jouni Högander wrote: > > Currently we are observing occasional sc

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev4)

Hi, > -Original Message- > From: Navare, Manasi D > Sent: torstai 24. helmikuuta 2022 21.00 > To: intel-gfx@lists.freedesktop.org > Cc: Sarvela, Tomi P ; Syrjala, Ville > ; Saarinen, Jani ; Nikula, > Jani > > Subject: RE: ✗ Fi.CI.BAT: failure for drm/i915/display/vrr: Reset VRR capable

Re: [Intel-gfx] [PATCH 1/3] drm/i915/guc: Limit scheduling properties to avoid overflow

On 2/24/2022 11:19, John Harrison wrote: [snip] I'll change it to _uses_ and repost, then. [    7.683149] kernel BUG at drivers/gpu/drm/i915/gt/uc/intel_guc.h:367! Told you that one went bang. John.

Re: [Intel-gfx] [PATCH v2] drm/i915/psr: Set "SF Partial Frame Enable" also on full update

I'm back so I will try this patch on my machine and see if it helps, thank you! On Wed, 2022-02-23 at 14:48 +0200, Jouni Högander wrote: > Currently we are observing occasional screen flickering when > PSR2 selective fetch is enabled. More specifically glitch seems > to happen on full frame update

Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: Make the heartbeat play nice with long pre-emption timeouts

On 2/24/2022 03:41, Tvrtko Ursulin wrote: On 23/02/2022 20:00, John Harrison wrote: On 2/23/2022 05:58, Tvrtko Ursulin wrote: On 23/02/2022 02:45, John Harrison wrote: On 2/22/2022 03:19, Tvrtko Ursulin wrote: On 18/02/2022 21:33, john.c.harri...@intel.com wrote: From: John Harrison Comput

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix cursor coordinates on bigjoiner slave (rev3)

== Series Details == Series: drm/i915: Fix cursor coordinates on bigjoiner slave (rev3) URL : https://patchwork.freedesktop.org/series/100154/ State : success == Summary == CI Bug Log - changes from CI_DRM_11277_full -> Patchwork_22384_full

Re: [Intel-gfx] [PATCH 1/3] drm/i915/guc: Limit scheduling properties to avoid overflow

On 2/24/2022 01:59, Tvrtko Ursulin wrote: On 23/02/2022 19:03, John Harrison wrote: On 2/23/2022 04:13, Tvrtko Ursulin wrote: On 23/02/2022 02:11, John Harrison wrote: On 2/22/2022 01:52, Tvrtko Ursulin wrote: On 18/02/2022 21:33, john.c.harri...@intel.com wrote: From: John Harrison GuC co

[Intel-gfx] ✗ Fi.CI.BAT: failure for Bump DMC to v2.16 on ADL-P

== Series Details == Series: Bump DMC to v2.16 on ADL-P URL : https://patchwork.freedesktop.org/series/100666/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11279 -> Patchwork_22395 Summary --- **FAILURE** Serious

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev4)

Hi, I fixed the regression in this patch and resent it, it still has BAT failures, I wanted to understand if it failed to boot some of the machines again or the errors flagged here are the known errors. Regards Manasi From: Patchwork Sent: Thursday, February 24, 2022 10:45 AM To: Navare, Mana

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev4)

== Series Details == Series: drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev4) URL : https://patchwork.freedesktop.org/series/98801/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11279 -> Patchwork_22394

Re: [Intel-gfx] [PATCH] drm/i915: s/JSP2/ICP2/ PCH

Acked-by: Vivek Kasireddy > -Original Message- > From: Ville Syrjala > Sent: Thursday, February 24, 2022 5:22 AM > To: intel-gfx@lists.freedesktop.org > Cc: Roper, Matthew D ; Kasireddy, Vivek > > Subject: [PATCH] drm/i915: s/JSP2/ICP2/ PCH > > From: Ville Syrjälä > > This JSP2 PCH a

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Set "SF Partial Frame Enable" also on full update (rev2)

== Series Details == Series: drm/i915/psr: Set "SF Partial Frame Enable" also on full update (rev2) URL : https://patchwork.freedesktop.org/series/100633/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11276 -> Patchwork_22382 ===

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev4)

== Series Details == Series: drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev4) URL : https://patchwork.freedesktop.org/series/98801/ State : warning == Summary == $ dim checkpatch origin/drm-tip 244f36e5190c drm/i915/display/vrr: Reset VRR capable property on a long hpd -:1

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dmc: Do not try loading wrong DMC version

== Series Details == Series: drm/i915/dmc: Do not try loading wrong DMC version URL : https://patchwork.freedesktop.org/series/100664/ State : success == Summary == CI Bug Log - changes from CI_DRM_11279 -> Patchwork_22393 Summary ---

Re: [Intel-gfx] [PATCH v2] drm/i915/display: Use unions per platform in intel_dpll_hw_state

On Thu, Feb 24, 2022 at 07:48:10PM +0200, Souza, Jose wrote: > On Thu, 2022-02-24 at 17:39 +0200, Ville Syrjälä wrote: > > On Thu, Feb 24, 2022 at 01:49:36PM +, Souza, Jose wrote: > > > On Thu, 2022-02-24 at 15:25 +0200, Ville Syrjälä wrote: > > > > On Thu, Feb 24, 2022 at 01:17:35PM +, Sou

Re: [Intel-gfx] [PATCH v2] drm/i915/display: Use unions per platform in intel_dpll_hw_state

On Thu, Feb 24, 2022 at 05:48:10PM +, Souza, Jose wrote: > On Thu, 2022-02-24 at 17:39 +0200, Ville Syrjälä wrote: > > On Thu, Feb 24, 2022 at 01:49:36PM +, Souza, Jose wrote: > > > On Thu, 2022-02-24 at 15:25 +0200, Ville Syrjälä wrote: > > > > On Thu, Feb 24, 2022 at 01:17:35PM +, Sou

[Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm-intel-gt tree

Hi all, Today's linux-next merge of the drm-intel tree got a conflict in: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c between commit: 721fd84ea1fe9 ("drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for reference") from the drm-intel-gt tree and commit: b3f74938d6566 ("dr

Re: [Intel-gfx] [PATCH v2] drm/i915/display: Use unions per platform in intel_dpll_hw_state

On Thu, 2022-02-24 at 17:39 +0200, Ville Syrjälä wrote: > On Thu, Feb 24, 2022 at 01:49:36PM +, Souza, Jose wrote: > > On Thu, 2022-02-24 at 15:25 +0200, Ville Syrjälä wrote: > > > On Thu, Feb 24, 2022 at 01:17:35PM +, Souza, Jose wrote: > > > > On Thu, 2022-02-24 at 12:20 +0200, Ville Syrj

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dmc: Do not try loading wrong DMC version

== Series Details == Series: drm/i915/dmc: Do not try loading wrong DMC version URL : https://patchwork.freedesktop.org/series/100664/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1548d273add7 drm/i915/dmc: Do not try loading wrong DMC version -:14: WARNING:COMMIT_LOG_LONG_LIN

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Move bigjoiner refactoring (rev2)

== Series Details == Series: drm/i915: Move bigjoiner refactoring (rev2) URL : https://patchwork.freedesktop.org/series/100195/ State : success == Summary == CI Bug Log - changes from CI_DRM_11276_full -> Patchwork_22383_full Summary --

Re: [Intel-gfx] [PATCH 2/2] hda/i915: split the wait for the component binding

On Thu, Feb 24, 2022 at 01:22:03AM +0530, Ramalingam C wrote: Split the wait for component binding from i915 in multiples of sysctl_hung_task_timeout_secs. This helps to avoid the possible kworker thread hung detection given below. <3>[ 60.946316] INFO: task kworker/11:1:104 blocked for more t

Re: [Intel-gfx] [PATCH v3 3/5] drm/i915: Make cursor plane registers unlocked

On Thu, Feb 24, 2022 at 04:37:03PM +0200, Lisovskiy, Stanislav wrote: > On Fri, Feb 11, 2022 at 11:26:04AM +0200, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Drop the locks around cursor plane register writes. The > > lock isn't needed since each plane's register are neatly > > contained

[Intel-gfx] [PATCH 0/4] drm/i915: Optimize CSC updates for ilk+

From: Ville Syrjälä As we did with plane updates we can split the color management updates to noarm+arm pair. The CSC matrix coefficients can all be written in the noarm hook, with just the PIPE_CSC_mode (the arming register) left behind in the arm hook. Also make the scaler/pfit completely lock

[Intel-gfx] [PATCH 4/4] drm/i915: Split pipe+output CSC programming to noarm+arm pair

From: Ville Syrjälä Move most of the pipe+output CSC programming to the .color_commit_noarm() hook which runs before vblank evasion. Only PIPE_CSC_MODE (the arming register) needs to remain in inside the critical section. A test case that just updates the CTM in a loop produces the following i91

[Intel-gfx] [PATCH 3/4] drm/i915: Split color_commit() into noarm+arm pair

From: Ville Syrjälä To reduce the amount of registers written during the vblank evade critical section let's also split the .color_commit() hook to noarm+arm pair. The noarm hook runs before the vblank evasion with the arm hook staying inside the critical section. Just the framework here, actual

[Intel-gfx] [PATCH 2/4] drm/i915: Make ilk+ pfit regiser unlocked

From: Ville Syrjälä The ilk+ panel fitter register are sitting nicely on their own cacheline, so no need for global serialization via uncore.lock. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 18 +- 1 file changed, 9 insertions(+), 9 deletions

[Intel-gfx] [PATCH 1/4] drm/i915: Remove locks around skl+ scaler programming

From: Ville Syrjälä All the skl+ scaler registers are suitably confined to their own cachelines so we don't need the uncore.lock to globally serialize access to these registers. We actually already dropped some of this in commit 14ad15296d1f ("drm/i915: Make skl+ universal plane registers unlocke

Re: [Intel-gfx] [PATCH 2/2] hda/i915: split the wait for the component binding

Hi, On Thu, 24 Feb 2022, Ramalingam C wrote: > Split the wait for component binding from i915 in multiples of > sysctl_hung_task_timeout_secs. This helps to avoid the possible kworker > thread hung detection given below. while I understand the problem, I'm not sure whether a simpler option shoul

[Intel-gfx] ✗ Fi.CI.IGT: failure for Use drm_clflush* instead of clflush (rev11)

== Series Details == Series: Use drm_clflush* instead of clflush (rev11) URL : https://patchwork.freedesktop.org/series/99450/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11276_full -> Patchwork_22381_full Summary ---

Re: [Intel-gfx] [PATCH 1/2] kernel/hung_task: Exporting sysctl_hung_task_timeout_secs

On Thu, Feb 24, 2022 at 01:22:02AM +0530, Ramalingam C wrote: Exporting sysctl_hung_task_timeout_secs, to make it available for other kernel modules. I guess this should only be done if second patch is accepted by sound subsystem maintainers. If it is, then I'd do some changes in the commit mes

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: Use unions per platform in intel_dpll_hw_state (rev3)

== Series Details == Series: drm/i915/display: Use unions per platform in intel_dpll_hw_state (rev3) URL : https://patchwork.freedesktop.org/series/100577/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11278 -> Patchwork_22392 ==

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] HAX: drm/i915: Clarify vma lifetime (rev3)

== Series Details == Series: series starting with [1/2] HAX: drm/i915: Clarify vma lifetime (rev3) URL : https://patchwork.freedesktop.org/series/100593/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11276_full -> Patchwork_22380_full ==

Re: [Intel-gfx] [PATCH v2] drm/i915/display: Use unions per platform in intel_dpll_hw_state

On Thu, Feb 24, 2022 at 01:49:36PM +, Souza, Jose wrote: > On Thu, 2022-02-24 at 15:25 +0200, Ville Syrjälä wrote: > > On Thu, Feb 24, 2022 at 01:17:35PM +, Souza, Jose wrote: > > > On Thu, 2022-02-24 at 12:20 +0200, Ville Syrjälä wrote: > > > > On Wed, Feb 23, 2022 at 12:55:51PM -0800, Jos

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: Use unions per platform in intel_dpll_hw_state (rev3)

== Series Details == Series: drm/i915/display: Use unions per platform in intel_dpll_hw_state (rev3) URL : https://patchwork.freedesktop.org/series/100577/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separ

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: fix one mem leak in mmap_offset_attach() (rev3)

== Series Details == Series: drm/i915: fix one mem leak in mmap_offset_attach() (rev3) URL : https://patchwork.freedesktop.org/series/100532/ State : success == Summary == CI Bug Log - changes from CI_DRM_11276_full -> Patchwork_22378_full

[Intel-gfx] ✓ Fi.CI.BAT: success for hda/i915: split wait for component binding

== Series Details == Series: hda/i915: split wait for component binding URL : https://patchwork.freedesktop.org/series/100661/ State : success == Summary == CI Bug Log - changes from CI_DRM_11277 -> Patchwork_22391 Summary --- **SUCC

Re: [Intel-gfx] [PATCH v2 2/5] drm/i915: Make skl+ universal plane registers unlocked

On Thu, Feb 10, 2022 at 08:24:00AM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Drop the locks around most universal plane register writes. > The lock isn't needed since each plane's register are neatly > contained on their own cachelines. > > Signed-off-by: Ville Syrjälä Reviewed-by:

Re: [Intel-gfx] [PATCH v3 3/5] drm/i915: Make cursor plane registers unlocked

On Fri, Feb 11, 2022 at 11:26:04AM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Drop the locks around cursor plane register writes. The > lock isn't needed since each plane's register are neatly > contained on their own cachelines. > > The locking did have a secondary effect of disablin

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dg1: Remove require_force_probe protection (rev2)

== Series Details == Series: drm/i915/dg1: Remove require_force_probe protection (rev2) URL : https://patchwork.freedesktop.org/series/100601/ State : success == Summary == CI Bug Log - changes from CI_DRM_11276_full -> Patchwork_22377_full

Re: [Intel-gfx] [PATCH] drm/i915/display: Allow users to disable PSR2

On Thu, Feb 24, 2022 at 02:15:44PM +, Souza, Jose wrote: > + Rodrigo > > On Thu, 2022-02-24 at 15:11 +0200, Ville Syrjälä wrote: > > On Thu, Feb 24, 2022 at 03:06:30PM +0200, Ville Syrjälä wrote: > > > On Thu, Feb 24, 2022 at 01:01:24PM +, Souza, Jose wrote: > > > > On Thu, 2022-02-24 at 1

Re: [Intel-gfx] [PATCH] drm/i915/display: Allow users to disable PSR2

On Thu, Feb 24, 2022 at 02:15:44PM +, Souza, Jose wrote: > + Rodrigo > > On Thu, 2022-02-24 at 15:11 +0200, Ville Syrjälä wrote: > > On Thu, Feb 24, 2022 at 03:06:30PM +0200, Ville Syrjälä wrote: > > > On Thu, Feb 24, 2022 at 01:01:24PM +, Souza, Jose wrote: > > > > On Thu, 2022-02-24 at 1

Re: [Intel-gfx] [PATCH] drm/i915/display: Allow users to disable PSR2

+ Rodrigo On Thu, 2022-02-24 at 15:11 +0200, Ville Syrjälä wrote: > On Thu, Feb 24, 2022 at 03:06:30PM +0200, Ville Syrjälä wrote: > > On Thu, Feb 24, 2022 at 01:01:24PM +, Souza, Jose wrote: > > > On Thu, 2022-02-24 at 12:12 +0200, Ville Syrjälä wrote: > > > > On Wed, Feb 23, 2022 at 11:41:03

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