> -Original Message-
> From: Deak, Imre
> Sent: Monday, April 4, 2022 7:09 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Gupta, Anshuman ; Kahola, Mika
> ; Heikkila, Juha-pekka pekka.heikk...@intel.com>; C, Ramalingam
> Subject: [PATCH 4/4] drm/i915/dg2: Add support for DG2 clear
== Series Details ==
Series: drm/i915/display: Fix warnings about PSR lock not held
URL : https://patchwork.freedesktop.org/series/102298/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11468 -> Patchwork_22804
Summary
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: fixup min_alignment usage
URL : https://patchwork.freedesktop.org/series/102295/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11467 -> Patchwork_22803
On 3/31/2022 8:20 AM, Daniel Vetter wrote:
The stuff never really worked, and leads to lots of fun because it
out-of-order frees atomic states. Which upsets KASAN, among other
things.
For async updates we now have a more solid solution with the
->atomic_async_check and ->atomic_async_commit
== Series Details ==
Series: drm/i915/rps: Centralize computation of freq caps (rev6)
URL : https://patchwork.freedesktop.org/series/101606/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11467 -> Patchwork_22802
Summary
== Series Details ==
Series: drm/i915/rps: Centralize computation of freq caps (rev6)
URL : https://patchwork.freedesktop.org/series/101606/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/bios: Rework BDB block handling and PNPID->panel_type matching
(rev6)
URL : https://patchwork.freedesktop.org/series/102213/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11467 -> Patchwork_22801
== Series Details ==
Series: drm/i915/bios: Rework BDB block handling and PNPID->panel_type matching
(rev6)
URL : https://patchwork.freedesktop.org/series/102213/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be
== Series Details ==
Series: drm/i915/bios: Rework BDB block handling and PNPID->panel_type matching
(rev6)
URL : https://patchwork.freedesktop.org/series/102213/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fdfc2be08fd7 drm/i915/bios: Use the cached BDB version
8dc5af439d5d
== Series Details ==
Series: drm/i915: consider min_page_size when migrating
URL : https://patchwork.freedesktop.org/series/102288/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11467 -> Patchwork_22800
Summary
---
== Series Details ==
Series: drm/i915/selftests: handle more rounding
URL : https://patchwork.freedesktop.org/series/102285/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11465_full -> Patchwork_22798_full
Summary
---
== Series Details ==
Series: drm/i915: program wm blocks to at least blocks required per line (rev3)
URL : https://patchwork.freedesktop.org/series/102149/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11467 -> Patchwork_22799
On Thu, Mar 31, 2022 at 8:20 AM Daniel Vetter wrote:
>
> The stuff never really worked, and leads to lots of fun because it
> out-of-order frees atomic states. Which upsets KASAN, among other
> things.
>
> For async updates we now have a more solid solution with the
> ->atomic_async_check and
Commit 3b6f409547fb ("drm/i915/display/psr: Lock and unlock PSR around
pipe updates") did not took into account async flips with PSR1 and
PSR2 HW tracking, causing PSR lock not be held and causing warnings
when intel_psr2_program_trans_man_trk_ctl() is executed.
So here taking the PSR lock before
> -Original Message-
> From: De Marchi, Lucas
> Sent: Wednesday, April 6, 2022 10:46 AM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/dmc: Add MMIO range restrictions
>
> On Wed, Apr 06, 2022 at 10:16:55AM -0700, Anusha
On Tue, Apr 05, 2022 at 10:53:43PM -0700, Lucas De Marchi wrote:
On Tue, Apr 05, 2022 at 09:02:42PM -0700, Matt Roper wrote:
On Mon, Apr 04, 2022 at 05:11:49PM -0700, Lucas De Marchi wrote:
Since gen6 we use FPGA_DBG register to detect unclaimed MMIO registers.
This register is in the display
On Tue, Apr 05, 2022 at 11:05:55AM -0700, Casey Bowman wrote:
@Jani/Lucas, any other thoughts here?
This is now applied. Thanks.
Tvrtko / Jani / Rodrigo,
There was a small conflict due to s/intel_vtd_active/i915_vtd_active/
in drm-intel-next. I added a fixup to drm-rerere.
Lucas De Marchi
The compact-pt layout restrictions should only apply to the ppGTT. Also
make this play nice on platforms that only have the 64K GTT restriction,
and not the compact-pt thing.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Nirmoy Das
---
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 12
Trying to cast the region id into the region type doesn't work too well,
since the i915_vm_min_alignment() won't give us the correct value for
the stolen-lmem case.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Nirmoy Das
---
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 2 +-
1 file
== Series Details ==
Series: drm/i915/selftests: handle more rounding
URL : https://patchwork.freedesktop.org/series/102285/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11465 -> Patchwork_22798
Summary
---
On Wed, 06 Apr 2022 03:09:45 -0700, Anshuman Gupta wrote:
> On 2022-03-24 at 01:24:35 +0530, Ashutosh Dixit wrote:
> > +/* "Caps" frequencies should be converted to MHz using intel_gpu_freq() */
> IMHO, if this exported function deserves a comment, it should Kernel Doc
> comment.
> for an example
Freq caps (i.e. RP0, RP1 and RPn frequencies) are read from HW. However the
formats (bit positions, widths, registers and units) of these vary for
different generations with even more variations arriving in the future. In
order not to have to do identical computation for these caps in multiple
From: Ville Syrjälä
Apparently when the VBT panel_type==0xff we should trawl through
the PNPID table and check for a match against the EDID. If a
match is found the index gives us the panel_type.
Tried to match the Windows behaviour here with first looking
for an exact match, and if one isn't
From: Ville Syrjälä
Apparently when the VBT panel_type==0xff we should trawl through
the PNPID table and check for a match against the EDID. If a
match is found the index gives us the panel_type.
Tried to match the Windows behaviour here with first looking
for an exact match, and if one isn't
From: Ville Syrjälä
Move the panel specific VBT parsing to happen during the
output probing stage. Needs to be done because the VBT
parsing will need to look at the EDID to determine
the correct panel_type on some machines.
v2: Do intel_bios_init_panel() a bit earlier for vlv_dsi
== Series Details ==
Series: drm/i915/bios: Rework BDB block handling and PNPID->panel_type matching
(rev4)
URL : https://patchwork.freedesktop.org/series/102213/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11465 -> Patchwork_22797
We can only force migrate an object if the existing object size is
compatible with the new destinations min_page_size for the region.
Currently we blow up with something like:
[ 2857.497462] kernel BUG at drivers/gpu/drm/i915/gt/intel_migrate.c:431!
[ 2857.497497] invalid opcode: [#1]
== Series Details ==
Series: drm/i915/bios: Rework BDB block handling and PNPID->panel_type matching
(rev4)
URL : https://patchwork.freedesktop.org/series/102213/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be
== Series Details ==
Series: drm/i915/bios: Rework BDB block handling and PNPID->panel_type matching
(rev4)
URL : https://patchwork.freedesktop.org/series/102213/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b4e5171b664d drm/i915/bios: Use the cached BDB version
91a6a31d6e40
On Tue, Apr 5, 2022 at 1:09 AM Tvrtko Ursulin
wrote:
>
>
> On 04/04/2022 16:36, Daniel Vetter wrote:
> > On Mon, Apr 04, 2022 at 10:23:53AM +0100, Tvrtko Ursulin wrote:
> >>
> >> + Dave and Daniel
> >>
> >> Guys, are you okay with merging this via drm-intel-gt-next? It is one new
> >> file at
On Wed, Apr 06, 2022 at 08:14:58PM +0300, Lisovskiy, Stanislav wrote:
> On Wed, Apr 06, 2022 at 05:01:39PM +0300, Ville Syrjälä wrote:
> > On Wed, Apr 06, 2022 at 04:45:26PM +0300, Lisovskiy, Stanislav wrote:
> > > On Wed, Apr 06, 2022 at 03:48:02PM +0300, Ville Syrjälä wrote:
> > > > On Mon, Apr
On Wed, Apr 06, 2022 at 10:16:55AM -0700, Anusha Srivatsa wrote:
-Original Message-
From: De Marchi, Lucas
Sent: Tuesday, April 5, 2022 11:03 AM
To: Srivatsa, Anusha
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/dmc: Add MMIO range restrictions
On
In configurations with single DRAM channel, for usecases like
4K 60 Hz, FIFO underruns are observed quite frequently. Looks
like the wm0 watermark values need to bumped up because the wm0
memory latency calculations are probably not taking the DRAM
channel's impact into account.
As per the Bspec
Reviewed-by: Nirmoy Das
On 4/6/2022 7:30 PM, Matthew Auld wrote:
Ensure we account for potential rounding up of lmem objects.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5485
Signed-off-by: Matthew Auld
Cc: Nirmoy Das
---
drivers/gpu/drm/i915/gt/selftest_migrate.c | 6 --
Ensure we account for potential rounding up of lmem objects.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5485
Signed-off-by: Matthew Auld
Cc: Nirmoy Das
---
drivers/gpu/drm/i915/gt/selftest_migrate.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git
> -Original Message-
> From: De Marchi, Lucas
> Sent: Tuesday, April 5, 2022 11:03 AM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/dmc: Add MMIO range restrictions
>
> On Tue, Apr 05, 2022 at 10:14:29AM -0700, Anusha
On Wed, Apr 06, 2022 at 05:01:39PM +0300, Ville Syrjälä wrote:
> On Wed, Apr 06, 2022 at 04:45:26PM +0300, Lisovskiy, Stanislav wrote:
> > On Wed, Apr 06, 2022 at 03:48:02PM +0300, Ville Syrjälä wrote:
> > > On Mon, Apr 04, 2022 at 04:49:18PM +0300, Vinod Govindapillai wrote:
> > > > In
On Tue, Apr 05, 2022 at 11:41:18AM -0700, Lucas De Marchi wrote:
From: Kai Vehmanen
In systems with only a discrete i915 GPU, the acomp init will
always timeout for the PCH HDA controller instance.
Avoid the timeout by checking the PCI device hierarchy
whether any display class PCI device can
On Thu, Mar 31, 2022 at 01:43:43PM -0700, Casey Bowman wrote:
Splitting i915_run_as_guest into a more arch-friendly function
as non-x86 builds do not support this functionality.
Signed-off-by: Casey Bowman
Acked-by: Tvrtko Ursulin
now we have CI results and they look ok. I reworded the
On Tue, 2022-04-05 at 21:50 +, Patchwork wrote:
Patch Details
Series: series starting with [CI,1/3] drm/i915/display/psr: Set partial frame
enable when forcing full frame fetch
URL:https://patchwork.freedesktop.org/series/102209/
State: failure
Details:
On Thu, Mar 31, 2022 at 10:16:02AM -0700, Lucas De Marchi wrote:
On Wed, Mar 23, 2022 at 06:46:38PM +0100, Zbigniew Kempczyński wrote:
This reverts commit 904ebf2ba89edaeba5c7c10540e43dba63541dc6.
Failures on dg2 tests were caused by invalid alignment when local memory
was in use. Changes
== Series Details ==
Series: drm/i915/uc: use io memcpy functions for device memory copy
URL : https://patchwork.freedesktop.org/series/102258/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11461_full -> Patchwork_22796_full
On Wed, 2022-04-06 at 17:01 +0300, Ville Syrjälä wrote:
> On Wed, Apr 06, 2022 at 04:45:26PM +0300, Lisovskiy, Stanislav wrote:
> > On Wed, Apr 06, 2022 at 03:48:02PM +0300, Ville Syrjälä wrote:
> > > On Mon, Apr 04, 2022 at 04:49:18PM +0300, Vinod Govindapillai wrote:
> > > > In configurations
In configurations with single DRAM channel, for usecases like
4K 60 Hz, FIFO underruns are observed quite frequently. Looks
like the wm0 watermark values need to bumped up because the wm0
memory latency calculations are probably not taking the DRAM
channel's impact into account.
As per the Bspec
On Wed, Apr 06, 2022 at 04:45:26PM +0300, Lisovskiy, Stanislav wrote:
> On Wed, Apr 06, 2022 at 03:48:02PM +0300, Ville Syrjälä wrote:
> > On Mon, Apr 04, 2022 at 04:49:18PM +0300, Vinod Govindapillai wrote:
> > > In configurations with single DRAM channel, for usecases like
> > > 4K 60 Hz, FIFO
On Wed, Apr 06, 2022 at 03:48:02PM +0300, Ville Syrjälä wrote:
> On Mon, Apr 04, 2022 at 04:49:18PM +0300, Vinod Govindapillai wrote:
> > In configurations with single DRAM channel, for usecases like
> > 4K 60 Hz, FIFO underruns are observed quite frequently. Looks
> > like the wm0 watermark
From: Ville Syrjälä
We need to start parsing stuff from the tail end of the LFP data block.
This is made awkward by the fact that the fp_timing table has variable
size. So we must use a bit more finesse to get the tail end, and to
make sure we allocate enough memory for it to make sure our
From: Ville Syrjälä
Modern VBTs no longer contain the LFP data table pointers
block (41). We are expecting to have one in order to be able
to parse the LFP data block (42), so let's make one up.
Since the fp_timing table has variable size we must somehow
determine its size. Rather than just
From: Ville Syrjälä
Make a copy of each VB data block with a guaranteed minimum
size. The extra (if any) will just be left zeroed.
This means we don't have to worry about going out of bounds
when accessing any of the structure members. Otherwise that
could easliy happen if we simply get the
On Wed, 6 Apr 2022 at 08:52, Christian König
wrote:
>
> That should now be handled by the common dma_resv framework.
>
> Signed-off-by: Christian König
> Reviewed-by: Daniel Vetter
> Cc: intel-gfx@lists.freedesktop.org
> ---
> drivers/gpu/drm/i915/gem/i915_gem_object.c| 41
On Mon, Apr 04, 2022 at 04:49:18PM +0300, Vinod Govindapillai wrote:
> In configurations with single DRAM channel, for usecases like
> 4K 60 Hz, FIFO underruns are observed quite frequently. Looks
> like the wm0 watermark values need to bumped up because the wm0
> memory latency calculations are
> -Original Message-
> From: Tvrtko Ursulin
> Sent: Wednesday, April 6, 2022 4:23 PM
> To: Gupta, Anshuman ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/pmu: Drop redundant
> IS_VALLEYVIEW check in __get_rc6() (rev2)
>
>
> On
On 06/04/2022 11:36, Anshuman Gupta wrote:
On 2022-03-15 at 05:27:39 +0530, Patchwork wrote:
Pushed to drm-intel-next.
Thanks for review and patch.
Probably better if went through drm-intel-gt-next (not the files it
touches are mostly in gt/ and registers have GT in their names, and RC6
is
== Series Details ==
Series: drm/i915/uc: use io memcpy functions for device memory copy
URL : https://patchwork.freedesktop.org/series/102258/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11461 -> Patchwork_22796
Summary
On 2022-03-15 at 05:27:39 +0530, Patchwork wrote:
Pushed to drm-intel-next.
Thanks for review and patch.
Br,
Anshuman Gupta.
>Patch Details
>
>Series: drm/i915/pmu: Drop redundant IS_VALLEYVIEW check in __get_rc6()
>(rev2)
>URL: [1]https://patchwork.freedesktop.org/series/101301/
On Wed, 2022-04-06 at 12:58 +0300, Lisovskiy, Stanislav wrote:
> On Wed, Apr 06, 2022 at 12:19:19PM +0300, Govindapillai, Vinod wrote:
> > Hi,
> >
> > On Wed, 2022-04-06 at 10:48 +0300, Lisovskiy, Stanislav wrote:
> > > On Wed, Apr 06, 2022 at 12:51:29AM +0300, Govindapillai, Vinod wrote:
> > > >
On 2022-03-24 at 01:24:35 +0530, Ashutosh Dixit wrote:
> Freq caps (i.e. RP0, RP1 and RPn frequencies) are read from HW. However the
> formats (bit positions, widths, registers and units) of these vary for
> different generations with even more variations arriving in the future. In
> order not to
On Wed, Apr 06, 2022 at 12:19:19PM +0300, Govindapillai, Vinod wrote:
> Hi,
>
> On Wed, 2022-04-06 at 10:48 +0300, Lisovskiy, Stanislav wrote:
> > On Wed, Apr 06, 2022 at 12:51:29AM +0300, Govindapillai, Vinod wrote:
> > > Hi Stan
> > >
> > > Nice Find! Couple of clarifications, please check
== Series Details ==
Series: linux-next: build failure after merge of the drm-misc tree
URL : https://patchwork.freedesktop.org/series/102234/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11459_full -> Patchwork_22795_full
On Wed, 2022-04-06 at 11:14 +0300, Lisovskiy, Stanislav wrote:
> On Mon, Apr 04, 2022 at 04:49:18PM +0300, Vinod Govindapillai wrote:
> > In configurations with single DRAM channel, for usecases like
> > 4K 60 Hz, FIFO underruns are observed quite frequently. Looks
> > like the wm0 watermark
Hi,
On Wed, 2022-04-06 at 10:48 +0300, Lisovskiy, Stanislav wrote:
> On Wed, Apr 06, 2022 at 12:51:29AM +0300, Govindapillai, Vinod wrote:
> > Hi Stan
> >
> > Nice Find! Couple of clarifications, please check inline...
> >
> > On Tue, 2022-04-05 at 13:41 +0300, Stanislav Lisovskiy wrote:
> > >
When copying RSA use io memcpy functions if the destination address
contains a GPU local memory address. Considering even the source
address can be on local memory, a bounce buffer is used to copy from io
to io.
The intention of this patch is to make i915 portable outside x86 mainly
on ARM64.
== Series Details ==
Series: GSC support (rev4)
URL : https://patchwork.freedesktop.org/series/102160/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11459_full -> Patchwork_22793_full
Summary
---
**FAILURE**
On Mon, Apr 04, 2022 at 04:49:18PM +0300, Vinod Govindapillai wrote:
> In configurations with single DRAM channel, for usecases like
> 4K 60 Hz, FIFO underruns are observed quite frequently. Looks
> like the wm0 watermark values need to bumped up because the wm0
> memory latency calculations are
== Series Details ==
Series: Splitting intel-gtt calls for non-x86 platforms (rev8)
URL : https://patchwork.freedesktop.org/series/101552/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11459_full -> Patchwork_22792_full
On Wed, Apr 06, 2022 at 12:51:29AM +0300, Govindapillai, Vinod wrote:
> Hi Stan
>
> Nice Find! Couple of clarifications, please check inline...
>
> On Tue, 2022-04-05 at 13:41 +0300, Stanislav Lisovskiy wrote:
> > Currently skl_pcode_try_request function doesn't
> > properly handle return value
On 05/04/2022 17:05, Daniel Vetter wrote:
On Tue, Apr 05, 2022 at 04:53:45PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Mixup in rebasing and patchwork re-runs made me push the wrong version of
the patch. Or I even forgot to send out the fixed version. Fix it up.
Signed-off-by:
== Series Details ==
Series: fbcon cleanups
URL : https://patchwork.freedesktop.org/series/102223/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11459_full -> Patchwork_22791_full
Summary
---
**FAILURE**
Serious
suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/intel-lab-lkp/linux/commits/Anusha-Srivatsa/drm-i915-dmc-Add-MMIO-range-restrictions/20220406-011821
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-rhel-8.3
== Series Details ==
Series: Splitting up platform-specific calls (rev2)
URL : https://patchwork.freedesktop.org/series/102041/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11459_full -> Patchwork_22790_full
Summary
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