Re: [Intel-gfx] [PATCH v3] uapi/drm/i915: Document memory residency and Flat-CCS capability of obj

[Jordan Justen]

On 2022-05-13 05:31:00, Lionel Landwerlin wrote:
> On 02/05/2022 17:15, Ramalingam C wrote:
> > Capture the impact of memory region preference list of the objects, on
> > their memory residency and Flat-CCS capability.
> >
> > v2:
> >Fix the Flat-CCS capability of an obj with {lmem, smem} preference
> >list [Thomas]
> > v3:
> >Reworded the doc [Matt]
> >
> > Signed-off-by: Ramalingam C 
> > cc: Matthew Auld 
> > cc: Thomas Hellstrom 
> > cc: Daniel Vetter 
> > cc: Jon Bloomfield 
> > cc: Lionel Landwerlin 
> > cc: Kenneth Graunke 
> > cc: mesa-...@lists.freedesktop.org
> > cc: Jordan Justen 
> > cc: Tony Ye 
> > Reviewed-by: Matthew Auld 
> > ---
> >   include/uapi/drm/i915_drm.h | 16 
> >   1 file changed, 16 insertions(+)
> >
> > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > index a2def7b27009..b7e1c2fe08dc 100644
> > --- a/include/uapi/drm/i915_drm.h
> > +++ b/include/uapi/drm/i915_drm.h
> > @@ -3443,6 +3443,22 @@ struct drm_i915_gem_create_ext {
> >* At which point we get the object handle in 
> > _i915_gem_create_ext.handle,
> >* along with the final object size in _i915_gem_create_ext.size, 
> > which
> >* should account for any rounding up, if required.
> > + *
> > + * Note that userspace has no means of knowing the current backing region
> > + * for objects where @num_regions is larger than one. The kernel will only
> > + * ensure that the priority order of the @regions array is honoured, either
> > + * when initially placing the object, or when moving memory around due to
> > + * memory pressure
> > + *
> > + * On Flat-CCS capable HW, compression is supported for the objects 
> > residing
> > + * in I915_MEMORY_CLASS_DEVICE. When such objects (compressed) has other
> > + * memory class in @regions and migrated (by I915, due to memory
> > + * constrain) to the non I915_MEMORY_CLASS_DEVICE region, then I915 needs 
> > to
> > + * decompress the content. But I915 dosen't have the required information 
> > to
> > + * decompress the userspace compressed objects.
> > + *
> > + * So I915 supports Flat-CCS, only on the objects which can reside only on
> > + * I915_MEMORY_CLASS_DEVICE regions.
> 
> I think it's fine to assume Flat-CSS surface will always be in lmem.
> 
> I see no issue for the Anv Vulkan driver.
> 
> Maybe Nanley or Ken can speak for the Iris GL driver?
> 

Acked-by: Jordan Justen 

I think Nanley has accounted for this on iris with:

https://gitlab.freedesktop.org/mesa/mesa/-/commit/42a865730ef72574e179b56a314f30fdccc6cba8

-Jordan

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: disable HPD workers before display driver unregister (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915/display: disable HPD workers before display driver unregister 
(rev6)
URL   : https://patchwork.freedesktop.org/series/103811/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11651_full -> Patchwork_103811v6_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_103811v6_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_eio@in-flight-contexts-1us:
- shard-snb:  [PASS][1] -> [FAIL][2] ([i915#4409])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11651/shard-snb4/igt@gem_...@in-flight-contexts-1us.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/shard-snb6/igt@gem_...@in-flight-contexts-1us.html

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][3] -> [TIMEOUT][4] ([i915#3063])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11651/shard-tglb7/igt@gem_...@unwedge-stress.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/shard-tglb6/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11651/shard-iclb1/igt@gem_exec_balan...@parallel-balancer.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/shard-iclb6/igt@gem_exec_balan...@parallel-balancer.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][7] -> [FAIL][8] ([i915#2846])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11651/shard-glk3/igt@gem_exec_f...@basic-deadline.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/shard-glk5/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none@rcs0:
- shard-kbl:  [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11651/shard-kbl7/igt@gem_exec_fair@basic-n...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/shard-kbl7/igt@gem_exec_fair@basic-n...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][11] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/shard-iclb1/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][12] -> [SKIP][13] ([i915#2190])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11651/shard-tglb1/igt@gem_huc_c...@huc-copy.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/shard-tglb6/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@heavy-multi:
- shard-iclb: NOTRUN -> [SKIP][14] ([i915#4613])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/shard-iclb5/igt@gem_lmem_swapp...@heavy-multi.html

  * igt@gem_lmem_swapping@parallel-random-verify:
- shard-skl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/shard-skl3/igt@gem_lmem_swapp...@parallel-random-verify.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk:  [PASS][16] -> [FAIL][17] ([i915#644])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11651/shard-glk2/igt@gem_pp...@flink-and-close-vma-leak.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/shard-glk1/igt@gem_pp...@flink-and-close-vma-leak.html

  * igt@gem_pread@exhaustion:
- shard-kbl:  NOTRUN -> [WARN][18] ([i915#2658])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/shard-kbl6/igt@gem_pr...@exhaustion.html

  * igt@gem_pxp@create-regular-buffer:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#4270])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/shard-iclb5/igt@gem_...@create-regular-buffer.html

  * igt@gem_render_copy@yf-tiled-to-vebox-linear:
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#768])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/shard-iclb5/igt@gem_render_c...@yf-tiled-to-vebox-linear.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-kbl:  NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#3323])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/shard-kbl3/igt@gem_userptr_bl...@dmabuf-sync.html

  * igt@gen7_exec_parse@basic-offset:
- shard-apl:  NOTRUN -> [SKIP][22] ([fdo#109271]) +28 similar issues
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/shard-apl1/igt@gen7_exec_pa...@basic-offset.html

  * igt@gen9_exec_parse@allowed-single:
- shard-apl:  [PASS][23] -> [DMESG-WARN][24] ([i915#5566] / 
[i915#716])
   [23]: 

Re: [Intel-gfx] [PATCH i-g-t] tests/core_hotunplug: Check sysfs reads after hotunplug

[Dixit, Ashutosh]

On Fri, 13 May 2022 02:31:28 -0700, Tvrtko Ursulin wrote:
>
> From: Tvrtko Ursulin 
>
> Leave some sysfs files open and attempt to read from them after hotunplug.

A few minor comments below but otherwise LGTM:

Reviewed-by: Ashutosh Dixit 

> Signed-off-by: Tvrtko Ursulin 
> Cc: Ashutosh Dixit 
> ---
>  tests/core_hotunplug.c | 62 ++
>  1 file changed, 62 insertions(+)
>
> diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c
> index 02eae19e1e16..c3831541202d 100644
> --- a/tests/core_hotunplug.c
> +++ b/tests/core_hotunplug.c
> @@ -602,6 +602,59 @@ static void hotreplug_lateclose(struct hotunplug *priv)
>   igt_assert_f(healthcheck(priv, false), "%s\n", priv->failure);
>  }
>
> +static void hotunplug_sysfs(struct hotunplug *priv)
> +{
> + int i915, sysfs;
> + struct {
> + int fd;
> + const char *path;
> + char buf[256];
> + } *item, items[] = {
> + { .fd = -1, .path = "error" },
> + { .fd = -1, .path = "gt_act_freq_mhz" },
> + { .fd = -1, .path = "gt/gt0/rps_act_freq_mhz" },
> + { .fd = -1, .path = "gt/gt0/rc6_residency_ms" },
> + { .fd = -1, .path = "engine/rcs0/name" },
> + { .fd = -1, .path = "engine/bcs0/name" },
> + { .path = NULL },
> + };
> + unsigned int cnt = 0;
> +
> + pre_check(priv);
> +
> + i915 = local_drm_open_driver(false, "", " for hot unplug");
> + sysfs = igt_sysfs_open(i915);
> + igt_require(sysfs >= 0);
> + for (item = [0]; item->path; item++) {
> + item->fd = openat(sysfs, item->path, O_RDONLY);
> + cnt += item->fd >= 0;
> + }
> + close(sysfs);
> + close_device(i915, " ", "sysfs open ");
> +
> + igt_require(cnt >= 3);

igt_require(cnt) ?

> +
> + device_unplug(priv, "hot ", 60);

Not sure what happens when there are child devices etc. Anyway it's being
used elsewhere too so probably ok.

Also maybe unbind (instead of remove) using driver_unbind() is sufficient?

> +
> + sleep(2);

Device remove via sysfs:
echo 1 > /sys/bus/pci/devices/\:03\:00.0/remove
is most likely synchronous but anyway...

> +
> + for (item = [0]; item->path; item++) {
> + ssize_t len;
> + int err;
> +
> + if (item->fd < 0)
> + continue;
> +
> + len = read(item->fd, item->buf, sizeof(item->buf));
> + err = len < 0 ? -errno : 0;
> + close(item->fd);
> + igt_debug("%s='%s' (%d)\n", item->path, item->buf, err);
> + igt_assert_eq(err, -ENODEV);
> + }
> +
> + igt_assert_f(healthcheck(priv, false), "%s\n", priv->failure);
> +}
> +
>  /* Main */
>
>  igt_main
> @@ -735,6 +788,15 @@ igt_main
>   recover();
>   }
>
> + igt_subtest_group {
> + igt_describe("Check if sysfs files left open can be safely 
> accessed after hotunplug.");
> + igt_subtest("hotunplug-sysfs")
> + hotunplug_sysfs();
> +
> + igt_fixture
> + recover();
> + }
> +
>   igt_fixture {
>   post_healthcheck();
>
> --
> 2.32.0
>

Re: [Intel-gfx] [PATCH v3] drm/i915: Enable Tile4 tiling mode

[Matt Roper]

On Fri, May 13, 2022 at 10:47:54AM +0200, Nirmoy Das wrote:
> From: Bommu Krishnaiah 
> 
> Enable Tile4 tiling mode on platform that supports
> Tile4 but no TileY like DG2.

Drive-by comment:  the patch description doesn't match what the code is
actually doing.  Tile4 is already enabled on these platforms (e.g., see
"drm/i915/dg2: Tile 4 plane format support").

This patch appears to just be updating selftest code, not enabling
anything new.


Matt

> 
> v3: add a function to find X-tile availability for a platform.
> v2: disable X-tile for iGPU in fastblit
> fix checkpath --strict warnings
> 
> Signed-off-by: Bommu Krishnaiah 
> Co-developed-by: Nirmoy Das 
> Signed-off-by: Nirmoy Das 
> ---
>  .../i915/gem/selftests/i915_gem_client_blt.c  | 250 ++
>  drivers/gpu/drm/i915/gt/intel_gpu_commands.h  |  22 ++
>  2 files changed, 227 insertions(+), 45 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c 
> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> index ddd0772fd828..3cfc621ef363 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> @@ -6,6 +6,7 @@
>  #include "i915_selftest.h"
>  
>  #include "gt/intel_context.h"
> +#include "gt/intel_engine_regs.h"
>  #include "gt/intel_engine_user.h"
>  #include "gt/intel_gpu_commands.h"
>  #include "gt/intel_gt.h"
> @@ -18,10 +19,71 @@
>  #include "huge_gem_object.h"
>  #include "mock_context.h"
>  
> +#define OW_SIZE 16  /* in bytes */
> +#define F_SUBTILE_SIZE 64   /* in bytes */
> +#define F_TILE_WIDTH 128/* in bytes */
> +#define F_TILE_HEIGHT 32/* in pixels */
> +#define F_SUBTILE_WIDTH  OW_SIZE/* in bytes */
> +#define F_SUBTILE_HEIGHT 4  /* in pixels */
> +
> +static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp)
> +{
> + int tile_base;
> + int tile_x, tile_y;
> + int swizzle, subtile;
> + int pixel_size = bpp / 8;
> + int pos;
> +
> + /*
> +  * Subtile remapping for F tile. Note that map[a]==b implies map[b]==a
> +  * so we can use the same table to tile and until.
> +  */
> + static const u8 f_subtile_map[] = {
> +  0,  1,  2,  3,  8,  9, 10, 11,
> +  4,  5,  6,  7, 12, 13, 14, 15,
> + 16, 17, 18, 19, 24, 25, 26, 27,
> + 20, 21, 22, 23, 28, 29, 30, 31,
> + 32, 33, 34, 35, 40, 41, 42, 43,
> + 36, 37, 38, 39, 44, 45, 46, 47,
> + 48, 49, 50, 51, 56, 57, 58, 59,
> + 52, 53, 54, 55, 60, 61, 62, 63
> + };
> +
> + x *= pixel_size;
> + /*
> +  * Where does the 4k tile start (in bytes)?  This is the same for Y and
> +  * F so we can use the Y-tile algorithm to get to that point.
> +  */
> + tile_base =
> + y / F_TILE_HEIGHT * stride * F_TILE_HEIGHT +
> + x / F_TILE_WIDTH * 4096;
> +
> + /* Find pixel within tile */
> + tile_x = x % F_TILE_WIDTH;
> + tile_y = y % F_TILE_HEIGHT;
> +
> + /* And figure out the subtile within the 4k tile */
> + subtile = tile_y / F_SUBTILE_HEIGHT * 8 + tile_x / F_SUBTILE_WIDTH;
> +
> + /* Swizzle the subtile number according to the bspec diagram */
> + swizzle = f_subtile_map[subtile];
> +
> + /* Calculate new position */
> + pos = tile_base +
> + swizzle * F_SUBTILE_SIZE +
> + tile_y % F_SUBTILE_HEIGHT * OW_SIZE +
> + tile_x % F_SUBTILE_WIDTH;
> +
> + GEM_BUG_ON(!IS_ALIGNED(pos, pixel_size));
> +
> + return pos / pixel_size * 4;
> +}
> +
>  enum client_tiling {
>   CLIENT_TILING_LINEAR,
>   CLIENT_TILING_X,
>   CLIENT_TILING_Y,
> + CLIENT_TILING_4,
>   CLIENT_NUM_TILING_TYPES
>  };
>  
> @@ -45,6 +107,36 @@ struct tiled_blits {
>   u32 height;
>  };
>  
> +static bool supports_x_tiling(const struct drm_i915_private *i915)
> +{
> + int gen = GRAPHICS_VER(i915);
> +
> + if (gen < 12)
> + return true;
> +
> + if (!HAS_LMEM(i915) || IS_DG1(i915))
> + return false;
> +
> + return true;
> +}
> +
> +static bool fast_blit_ok(const struct blit_buffer *buf)
> +{
> + int gen = GRAPHICS_VER(buf->vma->vm->i915);
> +
> + if (gen < 9)
> + return false;
> +
> + if (gen < 12)
> + return true;
> +
> + /* filter out platforms with unsupported X-tile support in fastblit */
> + if (buf->tiling == CLIENT_TILING_X && 
> !supports_x_tiling(buf->vma->vm->i915))
> + return false;
> +
> + return true;
> +}
> +
>  static int prepare_blit(const struct tiled_blits *t,
>   struct blit_buffer *dst,
>   struct blit_buffer *src,
> @@ -59,51 +151,103 @@ static int prepare_blit(const struct tiled_blits *t,
>   if (IS_ERR(cs))
>   return PTR_ERR(cs);
>  
> - *cs++ = 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: disable HPD workers before display driver unregister (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915/display: disable HPD workers before display driver unregister 
(rev6)
URL   : https://patchwork.freedesktop.org/series/103811/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11651 -> Patchwork_103811v6


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/index.html

Participating hosts (41 -> 40)
--

  Additional (1): bat-dg1-5 
  Missing(2): fi-kbl-soraka bat-rpls-2 

Known issues


  Here are the changes found in Patchwork_103811v6 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@fbdev@write:
- bat-dg1-5:  NOTRUN -> [SKIP][1] ([i915#2582]) +4 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/bat-dg1-5/igt@fb...@write.html

  * igt@gem_mmap@basic:
- bat-dg1-5:  NOTRUN -> [SKIP][2] ([i915#4083])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/bat-dg1-5/igt@gem_m...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-dg1-5:  NOTRUN -> [SKIP][3] ([i915#4077]) +2 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/bat-dg1-5/igt@gem_tiled_fence_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-dg1-5:  NOTRUN -> [SKIP][4] ([i915#4079]) +1 similar issue
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/bat-dg1-5/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
- bat-dg1-5:  NOTRUN -> [SKIP][5] ([i915#1155])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/bat-dg1-5/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@gem:
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][6] ([i915#4528])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/fi-pnv-d510/igt@i915_selftest@l...@gem.html
- fi-blb-e6850:   NOTRUN -> [DMESG-FAIL][7] ([i915#4528])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/fi-blb-e6850/igt@i915_selftest@l...@gem.html

  * igt@i915_selftest@live@gem_contexts:
- fi-bdw-5557u:   [PASS][8] -> [INCOMPLETE][9] ([i915#5502] / 
[i915#5801])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11651/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html

  * igt@i915_selftest@live@gt_engines:
- bat-dg1-5:  NOTRUN -> [INCOMPLETE][10] ([i915#4418])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/bat-dg1-5/igt@i915_selftest@live@gt_engines.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-5:  NOTRUN -> [SKIP][11] ([i915#4215])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/bat-dg1-5/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg1-5:  NOTRUN -> [SKIP][12] ([i915#4212]) +7 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/bat-dg1-5/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_busy@basic:
- bat-dg1-5:  NOTRUN -> [SKIP][13] ([i915#4303])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/bat-dg1-5/igt@kms_b...@basic.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-ivb-3770:NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/fi-ivb-3770/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- bat-dg1-5:  NOTRUN -> [SKIP][15] ([fdo#111827]) +7 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/bat-dg1-5/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg1-5:  NOTRUN -> [SKIP][16] ([i915#4103] / [i915#4213]) +1 
similar issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/bat-dg1-5/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_flip@basic-flip-vs-dpms:
- bat-dg1-5:  NOTRUN -> [SKIP][17] ([i915#4078]) +23 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/bat-dg1-5/igt@kms_f...@basic-flip-vs-dpms.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-dg1-5:  NOTRUN -> [SKIP][18] ([fdo#109285])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/bat-dg1-5/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_psr@primary_page_flip:
- bat-dg1-5:  NOTRUN -> [SKIP][19] ([i915#1072] / [i915#4078]) +3 
similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103811v6/bat-dg1-5/igt@kms_psr@primary_page_flip.html

  * 

[Intel-gfx] ✓ Fi.CI.IGT: success for Fixes for selective fetch area calculation (rev5)

[Patchwork]

== Series Details ==

Series: Fixes for selective fetch area calculation (rev5)
URL   : https://patchwork.freedesktop.org/series/103659/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11649_full -> Patchwork_103659v5_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_103659v5_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_hdr@bpc-switch@pipe-a-edp-1}:
- shard-skl:  [PASS][1] -> [FAIL][2] +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11649/shard-skl7/igt@kms_hdr@bpc-swi...@pipe-a-edp-1.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/shard-skl8/igt@kms_hdr@bpc-swi...@pipe-a-edp-1.html

  
Known issues


  Here are the changes found in Patchwork_103659v5_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_create@create-massive:
- shard-skl:  NOTRUN -> [DMESG-WARN][3] ([i915#4991])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/shard-skl3/igt@gem_cre...@create-massive.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-kbl:  NOTRUN -> [DMESG-WARN][4] ([i915#5076] / [i915#5614])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/shard-kbl6/igt@gem_exec_balan...@parallel-keep-submit-fence.html

  * igt@gem_exec_fair@basic-flow@rcs0:
- shard-skl:  NOTRUN -> [SKIP][5] ([fdo#109271]) +213 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/shard-skl10/igt@gem_exec_fair@basic-f...@rcs0.html
- shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2842]) +1 similar issue
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11649/shard-tglb7/igt@gem_exec_fair@basic-f...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/shard-tglb7/igt@gem_exec_fair@basic-f...@rcs0.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-tglb: NOTRUN -> [FAIL][8] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/shard-tglb8/igt@gem_exec_fair@basic-none-r...@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl:  [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11649/shard-apl4/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/shard-apl4/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk:  [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar 
issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11649/shard-glk7/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/shard-glk2/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_flush@basic-uc-ro-default:
- shard-snb:  [PASS][13] -> [SKIP][14] ([fdo#109271]) +1 similar 
issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11649/shard-snb7/igt@gem_exec_fl...@basic-uc-ro-default.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/shard-snb6/igt@gem_exec_fl...@basic-uc-ro-default.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
- shard-tglb: NOTRUN -> [SKIP][15] ([i915#4613])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/shard-tglb8/igt@gem_lmem_swapp...@heavy-verify-multi.html

  * igt@gem_lmem_swapping@heavy-verify-random:
- shard-skl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +2 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/shard-skl10/igt@gem_lmem_swapp...@heavy-verify-random.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- shard-apl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/shard-apl6/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-kbl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/shard-kbl6/igt@gem_lmem_swapp...@parallel-random-verify-ccs.html

  * igt@gem_pread@exhaustion:
- shard-apl:  NOTRUN -> [WARN][19] ([i915#2658])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/shard-apl2/igt@gem_pr...@exhaustion.html
- shard-snb:  NOTRUN -> [WARN][20] ([i915#2658])
   [20]: 

Re: [Intel-gfx] [PATCH] drm/i915/guc/rc: Use i915_probe_error instead of drm_error

[Teres Alexis, Alan Previn]

Nit: not sure why we use ERR_PTR for int when calling func was also returning 
an int.
Anyway, that was how the original code was, so:

Reviewed-by: Alan Previn 


On Thu, 2022-05-05 at 22:41 -0700, Vinay Belgaumkar wrote:
> To avoid false positives in error injection cases.
> 
> Signed-off-by: Vinay Belgaumkar 
> ---
>  drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c 
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
> index e00661fb0853..8f8dd05835c5 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
> @@ -49,7 +49,6 @@ static int guc_action_control_gucrc(struct intel_guc *guc, 
> bool enable)
>  static int __guc_rc_control(struct intel_guc *guc, bool enable)
>  {
>   struct intel_gt *gt = guc_to_gt(guc);
> - struct drm_device *drm = _to_gt(guc)->i915->drm;
>   int ret;
>  
>   if (!intel_uc_uses_guc_rc(>uc))
> @@ -60,8 +59,8 @@ static int __guc_rc_control(struct intel_guc *guc, bool 
> enable)
>  
>   ret = guc_action_control_gucrc(guc, enable);
>   if (ret) {
> - drm_err(drm, "Failed to %s GuC RC (%pe)\n",
> - str_enable_disable(enable), ERR_PTR(ret));
> + i915_probe_error(guc_to_gt(guc)->i915, "Failed to %s GuC RC 
> (%pe)\n",
> +  str_enable_disable(enable), ERR_PTR(ret));
>   return ret;
>   }
>  
> -- 
> 2.35.1
> 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Media freq factor and per-gt enhancements/fixes (rev6)

[Vudum, Lakshminarayana]

I have reopened the https://gitlab.freedesktop.org/drm/intel/-/issues/4440
igt@prime_self_import@reimport-vs-gem_close-race - fail - Failed assertion: 
obj_count == 0,error: -2 != 0

"{igt@i915_pm_freq_mult@media-freq@gt0" is not yet in CI bug log.

Thanks,
Lakshmi.

-Original Message-
From: Dixit, Ashutosh  
Sent: Friday, May 13, 2022 12:19 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana 

Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915: Media freq factor and per-gt 
enhancements/fixes (rev6)

On Thu, 12 May 2022 23:58:55 -0700, Patchwork wrote:
>
> Patch Details
>
>  Series:  drm/i915: Media freq factor and per-gt enhancements/fixes (rev6)
>  URL:  https://patchwork.freedesktop.org/series/102665/
>  State:  failure
>  Details:  
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102665v6/index.html
>
> CI Bug Log - changes from CI_DRM_11646_full -> Patchwork_102665v6_full
>
> FAILURE
>
> Possible regressions
>
> * {igt@i915_pm_freq_mult@media-freq@gt0} (NEW):
>
>  * shard-iclb: NOTRUN -> SKIP

This skip is expected, this new IGT will skip on unsupported platforms.

>
> * igt@prime_self_import@export-vs-gem_close-race:
>
>  * shard-tglb: PASS -> FAIL

This failure is unrelated. It is seen here too:

https://patchwork.freedesktop.org/series/99867/

Thanks.
--
Ashutosh

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/d12+: Disable DMC firmware flip queue handlers (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/d12+: Disable DMC firmware flip queue handlers (rev3)
URL   : https://patchwork.freedesktop.org/series/103888/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11649_full -> Patchwork_103888v3_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_103888v3_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-apl:  [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +2 similar 
issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11649/shard-apl1/igt@gem_ctx_isolation@preservation...@rcs0.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/shard-apl8/igt@gem_ctx_isolation@preservation...@rcs0.html

  * igt@gem_eio@in-flight-contexts-10ms:
- shard-skl:  [PASS][3] -> [TIMEOUT][4] ([i915#3063])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11649/shard-skl10/igt@gem_...@in-flight-contexts-10ms.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/shard-skl8/igt@gem_...@in-flight-contexts-10ms.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-kbl:  NOTRUN -> [DMESG-WARN][5] ([i915#5076] / [i915#5614])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/shard-kbl6/igt@gem_exec_balan...@parallel-keep-submit-fence.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][6] -> [FAIL][7] ([i915#2846])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11649/shard-glk6/igt@gem_exec_f...@basic-deadline.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/shard-glk5/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-tglb: NOTRUN -> [FAIL][8] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/shard-tglb6/igt@gem_exec_fair@basic-none-r...@rcs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11649/shard-tglb3/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/shard-tglb2/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk:  [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11649/shard-glk7/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/shard-glk9/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_flush@basic-uc-set-default:
- shard-snb:  [PASS][13] -> [SKIP][14] ([fdo#109271]) +5 similar 
issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11649/shard-snb2/igt@gem_exec_fl...@basic-uc-set-default.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/shard-snb6/igt@gem_exec_fl...@basic-uc-set-default.html

  * igt@gem_exec_params@no-blt:
- shard-iclb: NOTRUN -> [SKIP][15] ([fdo#109283])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/shard-iclb6/igt@gem_exec_par...@no-blt.html

  * igt@gem_exec_params@secure-non-root:
- shard-iclb: NOTRUN -> [SKIP][16] ([fdo#112283])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/shard-iclb6/igt@gem_exec_par...@secure-non-root.html

  * igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][17] -> [SKIP][18] ([i915#2190])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11649/shard-tglb2/igt@gem_huc_c...@huc-copy.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/shard-tglb6/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
- shard-tglb: NOTRUN -> [SKIP][19] ([i915#4613])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/shard-tglb6/igt@gem_lmem_swapp...@heavy-verify-multi.html

  * igt@gem_lmem_swapping@heavy-verify-random:
- shard-skl:  NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/shard-skl2/igt@gem_lmem_swapp...@heavy-verify-random.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- shard-apl:  NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4613])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/shard-apl4/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-kbl:  NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [22]: 

Re: [Intel-gfx] [PATCH v5 1/2] drm/i915/psr: Use full update In case of area calculation fails

[Souza, Jose]

On Fri, 2022-05-13 at 17:28 +0300, Jouni Högander wrote:
> Currently we have some corner cases where area calculation fails.  For
> these sel fetch area calculation ends up having update area as y1 = 0,
> y2 = 4. Instead of these values safer option is full update.
> 
> One of such for example is big fb with offset. We don't have usable
> offset in psr2_sel_fetch_update. Currently it's open what is the
> proper way to fix this corner case. Use full update for now.
> 
> v2: Commit message modified
> v3: Print out debug info once when area calculation fails
> v4: Use drm_info_once
> v5: pipeA -> "pipe %c", pipe_name(crtc-pipe)
> 

Reviewed-by: José Roberto de Souza 

> Cc: José Roberto de Souza 
> Cc: Mika Kahola 
> Signed-off-by: Jouni Högander 
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 14 ++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 06db407e2749..fecdaaeac39e 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1685,6 +1685,7 @@ static bool psr2_sel_fetch_pipe_state_supported(const 
> struct intel_crtc_state *c
>  int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>   struct intel_crtc *crtc)
>  {
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>   struct intel_crtc_state *crtc_state = 
> intel_atomic_get_new_crtc_state(state, crtc);
>   struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = 
> -1 };
>   struct intel_plane_state *new_plane_state, *old_plane_state;
> @@ -1770,6 +1771,19 @@ int intel_psr2_sel_fetch_update(struct 
> intel_atomic_state *state,
>   clip_area_update(_clip, _area);
>   }
>  
> + /*
> +  * TODO: For now we are just using full update in case
> +  * selective fetch area calculation fails. To optimize this we
> +  * should identify cases where this happens and fix the area
> +  * calculation for those.
> +  */
> + if (pipe_clip.y1 == -1) {
> + drm_info_once(_priv->drm,
> +   "Selective fetch area calculation failed in pipe 
> %c\n",
> +   pipe_name(crtc->pipe));
> + full_update = true;
> + }
> +
>   if (full_update)
>   goto skip_sel_fetch_set_loop;
>  

[Intel-gfx] [PATCH v6] drm/i915/display: disable HPD workers before display driver unregister

[Andrzej Hajda]

Handling HPD during driver removal is pointless, and can cause different
use-after-free/concurrency issues:
1. Setup of deferred fbdev after fbdev unregistration.
2. Access to DP-AUX after DP-AUX removal.

Below stacktraces of both cases observed on CI:

[272.634530] general protection fault, probably for non-canonical address 
0x6b6b6b6b6b6b6b6b:  [#1] PREEMPT SMP NOPTI
[272.634536] CPU: 0 PID: 6030 Comm: i915_selftest Tainted: G U
5.18.0-rc5-CI_DRM_11603-g12dccf4f5eef+ #1
[272.634541] Hardware name: Intel Corporation Raptor Lake Client Platform/RPL-S 
ADP-S DDR5 UDIMM CRB, BIOS RPLSFWI1.R00.2397.A01.2109300731 09/30/2021
[272.634545] RIP: 0010:fb_do_apertures_overlap.part.14+0x26/0x60
...
[272.634582] Call Trace:
[272.634583]  
[272.634585]  do_remove_conflicting_framebuffers+0x59/0xa0
[272.634589]  remove_conflicting_framebuffers+0x2d/0xc0
[272.634592]  remove_conflicting_pci_framebuffers+0xc8/0x110
[272.634595]  drm_aperture_remove_conflicting_pci_framebuffers+0x52/0x70
[272.634604]  i915_driver_probe+0x63a/0xdd0 [i915]

[283.405824] cpu_latency_qos_update_request called for unknown object
[283.405866] WARNING: CPU: 2 PID: 240 at kernel/power/qos.c:296 
cpu_latency_qos_update_request+0x2d/0x100
[283.405912] CPU: 2 PID: 240 Comm: kworker/u64:9 Not tainted 
5.18.0-rc6-Patchwork_103738v3-g1672d1c43e43+ #1
[283.405915] Hardware name: Intel Corporation Raptor Lake Client Platform/RPL-S 
ADP-S DDR5 UDIMM CRB, BIOS RPLSFWI1.R00.2397.A01.2109300731 09/30/2021
[283.405916] Workqueue: i915-dp i915_digport_work_func [i915]
[283.406020] RIP: 0010:cpu_latency_qos_update_request+0x2d/0x100
...
[283.406040] Call Trace:
[283.406041]  
[283.406044]  intel_dp_aux_xfer+0x60e/0x8e0 [i915]
[283.406131]  ? finish_swait+0x80/0x80
[283.406139]  intel_dp_aux_transfer+0xc5/0x2b0 [i915]
[283.406218]  drm_dp_dpcd_access+0x79/0x130 [drm_display_helper]
[283.406227]  drm_dp_dpcd_read+0xe2/0xf0 [drm_display_helper]
[283.406233]  intel_dp_hpd_pulse+0x134/0x570 [i915]
[283.406308]  ? __down_killable+0x70/0x140
[283.406313]  i915_digport_work_func+0xba/0x150 [i915]

Signed-off-by: Andrzej Hajda 
---
Hi all,

This is my Nth attempt to solve some old CI bug[1].
v-2: caused issues in kms code [2],
v-1: revealed that not only fbdev does not like HPD on removal [3],
v3: lacks drm_kms_helper_poll_disable[4]
v4: added dump_stack to detect late fb registration
v5: added intel_dp_mst_suspend to stop late fb registration
v6: removed dump_stack with hope everything is handled

Moreover this is quite rare bug, but due to specific configuration
of one of CI machines it appears there very frequently.
Forgive me spamming the list.

[1]: https://gitlab.freedesktop.org/drm/intel/-/issues/5329
[2]: https://patchwork.freedesktop.org/series/103621/
[3]: https://patchwork.freedesktop.org/series/103738/
[4]: https://patchwork.freedesktop.org/series/103811/

Regards
Andrzej
---
 drivers/gpu/drm/i915/display/intel_display.c | 11 ---
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 806d50b302ab92..007bc6daef7d31 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10486,13 +10486,6 @@ void intel_modeset_driver_remove_noirq(struct 
drm_i915_private *i915)
 */
intel_hpd_poll_fini(i915);
 
-   /*
-* MST topology needs to be suspended so we don't have any calls to
-* fbdev after it's finalized. MST will be destroyed later as part of
-* drm_mode_config_cleanup()
-*/
-   intel_dp_mst_suspend(i915);
-
/* poll work can call into fbdev, hence clean that up afterwards */
intel_fbdev_fini(i915);
 
@@ -10584,6 +10577,10 @@ void intel_display_driver_unregister(struct 
drm_i915_private *i915)
if (!HAS_DISPLAY(i915))
return;
 
+   intel_dp_mst_suspend(i915);
+   intel_hpd_cancel_work(i915);
+   drm_kms_helper_poll_disable(>drm);
+
intel_fbdev_unregister(i915);
intel_audio_deinit(i915);
 
-- 
2.25.1

[Intel-gfx] ✓ Fi.CI.BAT: success for Fixes for selective fetch area calculation (rev5)

[Patchwork]

== Series Details ==

Series: Fixes for selective fetch area calculation (rev5)
URL   : https://patchwork.freedesktop.org/series/103659/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11649 -> Patchwork_103659v5


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/index.html

Participating hosts (39 -> 39)
--

  Additional (1): fi-blb-e6850 
  Missing(1): bat-adlm-1 

Known issues


  Here are the changes found in Patchwork_103659v5 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [PASS][1] -> [INCOMPLETE][2] ([i915#3303] / 
[i915#4785])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11649/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   NOTRUN -> [DMESG-FAIL][3] ([i915#4528])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_force_connector_basic@force-connector-state:
- fi-bdw-gvtdvm:  [PASS][5] -> [DMESG-WARN][6] ([i915#5922])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11649/fi-bdw-gvtdvm/igt@kms_force_connector_ba...@force-connector-state.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/fi-bdw-gvtdvm/igt@kms_force_connector_ba...@force-connector-state.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-blb-e6850:   NOTRUN -> [SKIP][7] ([fdo#109271]) +39 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/fi-blb-e6850/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@runner@aborted:
- fi-bdw-gvtdvm:  NOTRUN -> [FAIL][8] ([i915#4312])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/fi-bdw-gvtdvm/igt@run...@aborted.html
- fi-hsw-g3258:   NOTRUN -> [FAIL][9] ([fdo#109271] / [i915#4312])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/fi-hsw-g3258/igt@run...@aborted.html
- fi-blb-e6850:   NOTRUN -> [FAIL][10] ([fdo#109271] / [i915#2403] / 
[i915#4312])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/fi-blb-e6850/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_heartbeat:
- {fi-jsl-1}: [DMESG-FAIL][11] ([i915#5334]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11649/fi-jsl-1/igt@i915_selftest@live@gt_heartbeat.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/fi-jsl-1/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][13] ([i915#4785]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11649/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@migrate:
- {bat-dg2-9}:[DMESG-WARN][15] ([i915#5763]) -> [PASS][16] +1 
similar issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11649/bat-dg2-9/igt@i915_selftest@l...@migrate.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/bat-dg2-9/igt@i915_selftest@l...@migrate.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- {bat-adlp-6}:   [DMESG-WARN][17] ([i915#3576]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11649/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103659v5/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#5334]: 

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: individualize fences before adding

[Patchwork]

== Series Details ==

Series: drm/i915: individualize fences before adding
URL   : https://patchwork.freedesktop.org/series/103981/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11649 -> Patchwork_103981v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_103981v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_103981v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103981v1/index.html

Participating hosts (39 -> 40)
--

  Additional (3): fi-blb-e6850 fi-icl-u2 bat-dg1-5 
  Missing(2): bat-adlm-1 bat-jsl-2 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_103981v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@gem:
- fi-blb-e6850:   NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103981v1/fi-blb-e6850/igt@i915_selftest@l...@gem.html

  
Known issues


  Here are the changes found in Patchwork_103981v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@fbdev@write:
- bat-dg1-5:  NOTRUN -> [SKIP][2] ([i915#2582]) +4 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103981v1/bat-dg1-5/igt@fb...@write.html

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103981v1/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103981v1/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_mmap@basic:
- bat-dg1-5:  NOTRUN -> [SKIP][5] ([i915#4083])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103981v1/bat-dg1-5/igt@gem_m...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-dg1-5:  NOTRUN -> [SKIP][6] ([i915#4077]) +2 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103981v1/bat-dg1-5/igt@gem_tiled_fence_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-dg1-5:  NOTRUN -> [SKIP][7] ([i915#4079]) +1 similar issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103981v1/bat-dg1-5/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
- bat-dg1-5:  NOTRUN -> [SKIP][8] ([i915#1155])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103981v1/bat-dg1-5/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@gt_engines:
- bat-dg1-5:  NOTRUN -> [INCOMPLETE][9] ([i915#4418])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103981v1/bat-dg1-5/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@gtt:
- fi-bdw-5557u:   [PASS][10] -> [INCOMPLETE][11] ([i915#5685])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11649/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103981v1/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-5:  NOTRUN -> [SKIP][12] ([i915#4215])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103981v1/bat-dg1-5/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg1-5:  NOTRUN -> [SKIP][13] ([i915#4212]) +7 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103981v1/bat-dg1-5/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_busy@basic:
- bat-dg1-5:  NOTRUN -> [SKIP][14] ([i915#4303])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103981v1/bat-dg1-5/igt@kms_b...@basic.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103981v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][16] ([fdo#111827]) +8 similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103981v1/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
- bat-dg1-5:  NOTRUN -> [SKIP][17] ([fdo#111827]) +7 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103981v1/bat-dg1-5/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2:  NOTRUN -> [SKIP][18] ([fdo#109278]) +2 

[Intel-gfx] [PATCH v5 2/2] drm/i915: Ensure damage clip area is within pipe area

[Jouni Högander]

Current update area calculation is not handling situation where
e.g. cursor plane is fully or partially outside pipe area.

Fix this by checking damage area against pipe_src area using
drm_rect_intersect.

v2: Set x1 and x2 in damaged_area initialization
v3: Move drm_rect_intersect into clip_area_update
v4: draw_area -> pipe_src

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5440
Cc: José Roberto de Souza 
Cc: Mika Kahola 

Reviewed-by: José Roberto de Souza 
Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_psr.c | 23 ---
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index fecdaaeac39e..36356893c7ca 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1618,8 +1618,12 @@ static void psr2_man_trk_ctl_calc(struct 
intel_crtc_state *crtc_state,
 }
 
 static void clip_area_update(struct drm_rect *overlap_damage_area,
-struct drm_rect *damage_area)
+struct drm_rect *damage_area,
+struct drm_rect *pipe_src)
 {
+   if (!drm_rect_intersect(damage_area, pipe_src))
+   return;
+
if (overlap_damage_area->y1 == -1) {
overlap_damage_area->y1 = damage_area->y1;
overlap_damage_area->y2 = damage_area->y2;
@@ -1709,7 +1713,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state 
*state,
 */
for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
 new_plane_state, i) {
-   struct drm_rect src, damaged_area = { .y1 = -1 };
+   struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1,
+ .x2 = INT_MAX };
struct drm_atomic_helper_damage_iter iter;
struct drm_rect clip;
 
@@ -1736,20 +1741,23 @@ int intel_psr2_sel_fetch_update(struct 
intel_atomic_state *state,
if (old_plane_state->uapi.visible) {
damaged_area.y1 = old_plane_state->uapi.dst.y1;
damaged_area.y2 = old_plane_state->uapi.dst.y2;
-   clip_area_update(_clip, _area);
+   clip_area_update(_clip, _area,
+_state->pipe_src);
}
 
if (new_plane_state->uapi.visible) {
damaged_area.y1 = new_plane_state->uapi.dst.y1;
damaged_area.y2 = new_plane_state->uapi.dst.y2;
-   clip_area_update(_clip, _area);
+   clip_area_update(_clip, _area,
+_state->pipe_src);
}
continue;
} else if (new_plane_state->uapi.alpha != 
old_plane_state->uapi.alpha) {
/* If alpha changed mark the whole plane area as 
damaged */
damaged_area.y1 = new_plane_state->uapi.dst.y1;
damaged_area.y2 = new_plane_state->uapi.dst.y2;
-   clip_area_update(_clip, _area);
+   clip_area_update(_clip, _area,
+_state->pipe_src);
continue;
}
 
@@ -1760,7 +1768,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state 
*state,
   _plane_state->uapi);
drm_atomic_for_each_plane_damage(, ) {
if (drm_rect_intersect(, ))
-   clip_area_update(_area, );
+   clip_area_update(_area, ,
+_state->pipe_src);
}
 
if (damaged_area.y1 == -1)
@@ -1768,7 +1777,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state 
*state,
 
damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1;
damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1;
-   clip_area_update(_clip, _area);
+   clip_area_update(_clip, _area, 
_state->pipe_src);
}
 
/*
-- 
2.25.1

[Intel-gfx] [PATCH v5 1/2] drm/i915/psr: Use full update In case of area calculation fails

[Jouni Högander]

Currently we have some corner cases where area calculation fails.  For
these sel fetch area calculation ends up having update area as y1 = 0,
y2 = 4. Instead of these values safer option is full update.

One of such for example is big fb with offset. We don't have usable
offset in psr2_sel_fetch_update. Currently it's open what is the
proper way to fix this corner case. Use full update for now.

v2: Commit message modified
v3: Print out debug info once when area calculation fails
v4: Use drm_info_once
v5: pipeA -> "pipe %c", pipe_name(crtc-pipe)

Cc: José Roberto de Souza 
Cc: Mika Kahola 
Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_psr.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 06db407e2749..fecdaaeac39e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1685,6 +1685,7 @@ static bool psr2_sel_fetch_pipe_state_supported(const 
struct intel_crtc_state *c
 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
struct intel_crtc *crtc)
 {
+   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *crtc_state = 
intel_atomic_get_new_crtc_state(state, crtc);
struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = 
-1 };
struct intel_plane_state *new_plane_state, *old_plane_state;
@@ -1770,6 +1771,19 @@ int intel_psr2_sel_fetch_update(struct 
intel_atomic_state *state,
clip_area_update(_clip, _area);
}
 
+   /*
+* TODO: For now we are just using full update in case
+* selective fetch area calculation fails. To optimize this we
+* should identify cases where this happens and fix the area
+* calculation for those.
+*/
+   if (pipe_clip.y1 == -1) {
+   drm_info_once(_priv->drm,
+ "Selective fetch area calculation failed in pipe 
%c\n",
+ pipe_name(crtc->pipe));
+   full_update = true;
+   }
+
if (full_update)
goto skip_sel_fetch_set_loop;
 
-- 
2.25.1

[Intel-gfx] [PATCH v5 0/2] Fixes for selective fetch area calculation

[Jouni Högander]

Currently selective fetch area calculation ends up as bogus area in
at least following cases:

1. Updated plane is partially or fully outside pipe area
2. Big fb with only part of memory area used for plane

These end up as y1 = 0, y2 = 4 or y2 being outside pipe area. This
patch set addresses these by ensuring update area is within pipe area
or by falling back to full update.

v5:
 - pipeA -> "pipe %c", pipe_name(crtc-pipe)
v4:
 - draw_area -> pipe_src
 - drm_dbg_once dropped and drm_info_once used instead
v3:
 - Add drm_dbg_once* and use it when sel fetch area calculation fails
 - Move drm_rect_intersect to clip_area_update
v2:
 - Update commit message of first patch
 - Set damaged_area x1 and x2 during initialization

Cc: José Roberto de Souza 
Cc: Mika Kahola 
Cc: Mark Pearson 

Jouni Högander (2):
  drm/i915/psr: Use full update In case of area calculation fails
  drm/i915: Ensure damage clip area is within pipe area

 drivers/gpu/drm/i915/display/intel_psr.c | 37 +++-
 1 file changed, 30 insertions(+), 7 deletions(-)

-- 
2.25.1

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/d12+: Disable DMC firmware flip queue handlers (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/d12+: Disable DMC firmware flip queue handlers (rev3)
URL   : https://patchwork.freedesktop.org/series/103888/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11649 -> Patchwork_103888v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/index.html

Participating hosts (39 -> 40)
--

  Additional (3): fi-blb-e6850 fi-rkl-11600 fi-icl-u2 
  Missing(2): bat-adlm-1 bat-jsl-2 

Known issues


  Here are the changes found in Patchwork_103888v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-rkl-11600:   NOTRUN -> [SKIP][1] ([i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html
- fi-icl-u2:  NOTRUN -> [SKIP][2] ([i915#2190])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-rkl-11600:   NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/fi-rkl-11600/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_tiled_pread_basic:
- fi-rkl-11600:   NOTRUN -> [SKIP][5] ([i915#3282])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/fi-rkl-11600/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-rkl-11600:   NOTRUN -> [SKIP][6] ([i915#3012])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   NOTRUN -> [DMESG-FAIL][7] ([i915#4528])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-rkl-11600:   NOTRUN -> [SKIP][9] ([fdo#111827]) +8 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/fi-rkl-11600/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][10] ([fdo#111827]) +8 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-rkl-11600:   NOTRUN -> [SKIP][11] ([i915#4070] / [i915#4103]) +1 
similar issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/fi-rkl-11600/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2:  NOTRUN -> [SKIP][12] ([fdo#109278]) +2 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-rkl-11600:   NOTRUN -> [SKIP][13] ([fdo#109285] / [i915#4098])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/fi-rkl-11600/igt@kms_force_connector_ba...@force-load-detect.html
- fi-icl-u2:  NOTRUN -> [SKIP][14] ([fdo#109285])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-blb-e6850:   NOTRUN -> [SKIP][15] ([fdo#109271]) +39 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/fi-blb-e6850/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
- fi-rkl-11600:   NOTRUN -> [SKIP][16] ([i915#4070] / [i915#533])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/fi-rkl-11600/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@primary_mmap_gtt:
- fi-rkl-11600:   NOTRUN -> [SKIP][17] ([i915#1072]) +3 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103888v3/fi-rkl-11600/igt@kms_psr@primary_mmap_gtt.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2:  NOTRUN -> [SKIP][18] ([i915#3555])
   [18]: 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/d12+: Disable DMC firmware flip queue handlers (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/d12+: Disable DMC firmware flip queue handlers (rev3)
URL   : https://patchwork.freedesktop.org/series/103888/
State : warning

== Summary ==

Error: dim checkpatch failed
50de1ff7239e drm/i915/d12+: Disable DMC firmware flip queue handlers
-:164: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dmc_id' - possible 
side-effects?
#164: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:24:
+#define _DMC_REG_MMIO_BASE(i915, dmc_id) \
+   ((dmc_id) == DMC_FW_MAIN ? __DMC_REG_MMIO_BASE : \
+  __PIPEDMC_REG_MMIO_BASE(i915, dmc_id))

total: 0 errors, 0 warnings, 1 checks, 157 lines checked

Re: [Intel-gfx] [PATCH v4 2/2] drm/i915: Ensure damage clip area is within pipe area

[Souza, Jose]

On Fri, 2022-05-13 at 15:30 +0300, Jouni Högander wrote:
> Current update area calculation is not handling situation where
> e.g. cursor plane is fully or partially outside pipe area.
> 
> Fix this by checking damage area against pipe_src area using
> drm_rect_intersect.
> 
> v2: Set x1 and x2 in damaged_area initialization
> v3: Move drm_rect_intersect into clip_area_update
> v4: draw_area -> pipe_src

Reviewed-by: José Roberto de Souza 

> 
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5440
> Cc: José Roberto de Souza 
> Cc: Mika Kahola 
> Signed-off-by: Jouni Högander 
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 23 ---
>  1 file changed, 16 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 1f031ebc1456..18058252037d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1618,8 +1618,12 @@ static void psr2_man_trk_ctl_calc(struct 
> intel_crtc_state *crtc_state,
>  }
>  
>  static void clip_area_update(struct drm_rect *overlap_damage_area,
> -  struct drm_rect *damage_area)
> +  struct drm_rect *damage_area,
> +  struct drm_rect *pipe_src)
>  {
> + if (!drm_rect_intersect(damage_area, pipe_src))
> + return;
> +
>   if (overlap_damage_area->y1 == -1) {
>   overlap_damage_area->y1 = damage_area->y1;
>   overlap_damage_area->y2 = damage_area->y2;
> @@ -1709,7 +1713,8 @@ int intel_psr2_sel_fetch_update(struct 
> intel_atomic_state *state,
>*/
>   for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
>new_plane_state, i) {
> - struct drm_rect src, damaged_area = { .y1 = -1 };
> + struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1,
> +   .x2 = INT_MAX };
>   struct drm_atomic_helper_damage_iter iter;
>   struct drm_rect clip;
>  
> @@ -1736,20 +1741,23 @@ int intel_psr2_sel_fetch_update(struct 
> intel_atomic_state *state,
>   if (old_plane_state->uapi.visible) {
>   damaged_area.y1 = old_plane_state->uapi.dst.y1;
>   damaged_area.y2 = old_plane_state->uapi.dst.y2;
> - clip_area_update(_clip, _area);
> + clip_area_update(_clip, _area,
> +  _state->pipe_src);
>   }
>  
>   if (new_plane_state->uapi.visible) {
>   damaged_area.y1 = new_plane_state->uapi.dst.y1;
>   damaged_area.y2 = new_plane_state->uapi.dst.y2;
> - clip_area_update(_clip, _area);
> + clip_area_update(_clip, _area,
> +  _state->pipe_src);
>   }
>   continue;
>   } else if (new_plane_state->uapi.alpha != 
> old_plane_state->uapi.alpha) {
>   /* If alpha changed mark the whole plane area as 
> damaged */
>   damaged_area.y1 = new_plane_state->uapi.dst.y1;
>   damaged_area.y2 = new_plane_state->uapi.dst.y2;
> - clip_area_update(_clip, _area);
> + clip_area_update(_clip, _area,
> +  _state->pipe_src);
>   continue;
>   }
>  
> @@ -1760,7 +1768,8 @@ int intel_psr2_sel_fetch_update(struct 
> intel_atomic_state *state,
>  _plane_state->uapi);
>   drm_atomic_for_each_plane_damage(, ) {
>   if (drm_rect_intersect(, ))
> - clip_area_update(_area, );
> + clip_area_update(_area, ,
> +  _state->pipe_src);
>   }
>  
>   if (damaged_area.y1 == -1)
> @@ -1768,7 +1777,7 @@ int intel_psr2_sel_fetch_update(struct 
> intel_atomic_state *state,
>  
>   damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1;
>   damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1;
> - clip_area_update(_clip, _area);
> + clip_area_update(_clip, _area, 
> _state->pipe_src);
>   }
>  
>   /*

Re: [Intel-gfx] [PATCH v4 1/2] drm/i915/psr: Use full update In case of area calculation fails

[Souza, Jose]

On Fri, 2022-05-13 at 15:30 +0300, Jouni Högander wrote:
> Currently we have some corner cases where area calculation fails.  For
> these sel fetch area calculation ends up having update area as y1 = 0,
> y2 = 4. Instead of these values safer option is full update.
> 
> One of such for example is big fb with offset. We don't have usable
> offset in psr2_sel_fetch_update. Currently it's open what is the
> proper way to fix this corner case. Use full update for now.
> 
> v2: Commit message modified
> v3: Print out debug info once when area calculation fails
> v4: Use drm_info_once
> 
> Cc: José Roberto de Souza 
> Cc: Mika Kahola 
> Signed-off-by: Jouni Högander 
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 12 
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 06db407e2749..1f031ebc1456 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1685,6 +1685,7 @@ static bool psr2_sel_fetch_pipe_state_supported(const 
> struct intel_crtc_state *c
>  int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>   struct intel_crtc *crtc)
>  {
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>   struct intel_crtc_state *crtc_state = 
> intel_atomic_get_new_crtc_state(state, crtc);
>   struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = 
> -1 };
>   struct intel_plane_state *new_plane_state, *old_plane_state;
> @@ -1770,6 +1771,17 @@ int intel_psr2_sel_fetch_update(struct 
> intel_atomic_state *state,
>   clip_area_update(_clip, _area);
>   }
>  
> + /*
> +  * TODO: For now we are just using full update in case
> +  * selective fetch area calculation fails. To optimize this we
> +  * should identify cases where this happens and fix the area
> +  * calculation for those.
> +  */
> + if (pipe_clip.y1 == -1) {
> + drm_info_once(_priv->drm, "Selective fetch area calculation 
> failed in pipeA");

Please do not hardcode to pipe A, get the pipe from state and print it.

> + full_update = true;
> + }
> +
>   if (full_update)
>   goto skip_sel_fetch_set_loop;
>  

Re: [Intel-gfx] [PATCH v3] uapi/drm/i915: Document memory residency and Flat-CCS capability of obj

[Lionel Landwerlin]

On 02/05/2022 17:15, Ramalingam C wrote:

Capture the impact of memory region preference list of the objects, on
their memory residency and Flat-CCS capability.

v2:
   Fix the Flat-CCS capability of an obj with {lmem, smem} preference
   list [Thomas]
v3:
   Reworded the doc [Matt]

Signed-off-by: Ramalingam C 
cc: Matthew Auld 
cc: Thomas Hellstrom 
cc: Daniel Vetter 
cc: Jon Bloomfield 
cc: Lionel Landwerlin 
cc: Kenneth Graunke 
cc: mesa-...@lists.freedesktop.org
cc: Jordan Justen 
cc: Tony Ye 
Reviewed-by: Matthew Auld 
---
  include/uapi/drm/i915_drm.h | 16 
  1 file changed, 16 insertions(+)

diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index a2def7b27009..b7e1c2fe08dc 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -3443,6 +3443,22 @@ struct drm_i915_gem_create_ext {
   * At which point we get the object handle in _i915_gem_create_ext.handle,
   * along with the final object size in _i915_gem_create_ext.size, which
   * should account for any rounding up, if required.
+ *
+ * Note that userspace has no means of knowing the current backing region
+ * for objects where @num_regions is larger than one. The kernel will only
+ * ensure that the priority order of the @regions array is honoured, either
+ * when initially placing the object, or when moving memory around due to
+ * memory pressure
+ *
+ * On Flat-CCS capable HW, compression is supported for the objects residing
+ * in I915_MEMORY_CLASS_DEVICE. When such objects (compressed) has other
+ * memory class in @regions and migrated (by I915, due to memory
+ * constrain) to the non I915_MEMORY_CLASS_DEVICE region, then I915 needs to
+ * decompress the content. But I915 dosen't have the required information to
+ * decompress the userspace compressed objects.
+ *
+ * So I915 supports Flat-CCS, only on the objects which can reside only on
+ * I915_MEMORY_CLASS_DEVICE regions.



I think it's fine to assume Flat-CSS surface will always be in lmem.

I see no issue for the Anv Vulkan driver.


Maybe Nanley or Ken can speak for the Iris GL driver?


-Lionel



   */
  struct drm_i915_gem_create_ext_memory_regions {
/** @base: Extension link. See struct i915_user_extension. */

[Intel-gfx] [PATCH v4 2/2] drm/i915: Ensure damage clip area is within pipe area

[Jouni Högander]

Current update area calculation is not handling situation where
e.g. cursor plane is fully or partially outside pipe area.

Fix this by checking damage area against pipe_src area using
drm_rect_intersect.

v2: Set x1 and x2 in damaged_area initialization
v3: Move drm_rect_intersect into clip_area_update
v4: draw_area -> pipe_src

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5440
Cc: José Roberto de Souza 
Cc: Mika Kahola 
Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_psr.c | 23 ---
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 1f031ebc1456..18058252037d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1618,8 +1618,12 @@ static void psr2_man_trk_ctl_calc(struct 
intel_crtc_state *crtc_state,
 }
 
 static void clip_area_update(struct drm_rect *overlap_damage_area,
-struct drm_rect *damage_area)
+struct drm_rect *damage_area,
+struct drm_rect *pipe_src)
 {
+   if (!drm_rect_intersect(damage_area, pipe_src))
+   return;
+
if (overlap_damage_area->y1 == -1) {
overlap_damage_area->y1 = damage_area->y1;
overlap_damage_area->y2 = damage_area->y2;
@@ -1709,7 +1713,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state 
*state,
 */
for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
 new_plane_state, i) {
-   struct drm_rect src, damaged_area = { .y1 = -1 };
+   struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1,
+ .x2 = INT_MAX };
struct drm_atomic_helper_damage_iter iter;
struct drm_rect clip;
 
@@ -1736,20 +1741,23 @@ int intel_psr2_sel_fetch_update(struct 
intel_atomic_state *state,
if (old_plane_state->uapi.visible) {
damaged_area.y1 = old_plane_state->uapi.dst.y1;
damaged_area.y2 = old_plane_state->uapi.dst.y2;
-   clip_area_update(_clip, _area);
+   clip_area_update(_clip, _area,
+_state->pipe_src);
}
 
if (new_plane_state->uapi.visible) {
damaged_area.y1 = new_plane_state->uapi.dst.y1;
damaged_area.y2 = new_plane_state->uapi.dst.y2;
-   clip_area_update(_clip, _area);
+   clip_area_update(_clip, _area,
+_state->pipe_src);
}
continue;
} else if (new_plane_state->uapi.alpha != 
old_plane_state->uapi.alpha) {
/* If alpha changed mark the whole plane area as 
damaged */
damaged_area.y1 = new_plane_state->uapi.dst.y1;
damaged_area.y2 = new_plane_state->uapi.dst.y2;
-   clip_area_update(_clip, _area);
+   clip_area_update(_clip, _area,
+_state->pipe_src);
continue;
}
 
@@ -1760,7 +1768,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state 
*state,
   _plane_state->uapi);
drm_atomic_for_each_plane_damage(, ) {
if (drm_rect_intersect(, ))
-   clip_area_update(_area, );
+   clip_area_update(_area, ,
+_state->pipe_src);
}
 
if (damaged_area.y1 == -1)
@@ -1768,7 +1777,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state 
*state,
 
damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1;
damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1;
-   clip_area_update(_clip, _area);
+   clip_area_update(_clip, _area, 
_state->pipe_src);
}
 
/*
-- 
2.25.1

[Intel-gfx] [PATCH v4 0/2] Fixes for selective fetch area calculation

[Jouni Högander]

Currently selective fetch area calculation ends up as bogus area in
at least following cases:

1. Updated plane is partially or fully outside pipe area
2. Big fb with only part of memory area used for plane

These end up as y1 = 0, y2 = 4 or y2 being outside pipe area. This
patch set addresses these by ensuring update area is within pipe area
or by falling back to full update.

v4:
 - draw_area -> pipe_src
 - drm_dbg_once dropped and drm_info_once used instead
v3:
 - Add drm_dbg_once* and use it when sel fetch area calculation fails
 - Move drm_rect_intersect to clip_area_update
v2:
 - Update commit message of first patch
 - Set damaged_area x1 and x2 during initialization

Cc: José Roberto de Souza 
Cc: Mika Kahola 
Cc: Mark Pearson 

Jouni Högander (2):
  drm/i915/psr: Use full update In case of area calculation fails
  drm/i915: Ensure damage clip area is within pipe area

 drivers/gpu/drm/i915/display/intel_psr.c | 35 +++-
 1 file changed, 28 insertions(+), 7 deletions(-)

-- 
2.25.1

[Intel-gfx] [PATCH v4 1/2] drm/i915/psr: Use full update In case of area calculation fails

[Jouni Högander]

Currently we have some corner cases where area calculation fails.  For
these sel fetch area calculation ends up having update area as y1 = 0,
y2 = 4. Instead of these values safer option is full update.

One of such for example is big fb with offset. We don't have usable
offset in psr2_sel_fetch_update. Currently it's open what is the
proper way to fix this corner case. Use full update for now.

v2: Commit message modified
v3: Print out debug info once when area calculation fails
v4: Use drm_info_once

Cc: José Roberto de Souza 
Cc: Mika Kahola 
Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_psr.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 06db407e2749..1f031ebc1456 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1685,6 +1685,7 @@ static bool psr2_sel_fetch_pipe_state_supported(const 
struct intel_crtc_state *c
 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
struct intel_crtc *crtc)
 {
+   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *crtc_state = 
intel_atomic_get_new_crtc_state(state, crtc);
struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = 
-1 };
struct intel_plane_state *new_plane_state, *old_plane_state;
@@ -1770,6 +1771,17 @@ int intel_psr2_sel_fetch_update(struct 
intel_atomic_state *state,
clip_area_update(_clip, _area);
}
 
+   /*
+* TODO: For now we are just using full update in case
+* selective fetch area calculation fails. To optimize this we
+* should identify cases where this happens and fix the area
+* calculation for those.
+*/
+   if (pipe_clip.y1 == -1) {
+   drm_info_once(_priv->drm, "Selective fetch area calculation 
failed in pipeA");
+   full_update = true;
+   }
+
if (full_update)
goto skip_sel_fetch_set_loop;
 
-- 
2.25.1

Re: [Intel-gfx] [PATCH] drm/i915/audio: fix audio code enable/disable pipe logging

[Jani Nikula]

On Thu, 12 May 2022, Ville Syrjälä  wrote:
> On Thu, May 12, 2022 at 07:16:38PM +0300, Jani Nikula wrote:
>> Need to use pipe_name(pipe) instead of pipe directly.
>> 
>> Fixes: 1f31e35f2e88 ("drm/i915/audio: unify audio codec enable/disable debug 
>> logging")
>> Cc: Ville Syrjälä 
>> Signed-off-by: Jani Nikula 
>
> Reviewed-by: Ville Syrjälä 

Thanks, pushed to din.

BR,
Jani.
>
>> ---
>>  drivers/gpu/drm/i915/display/intel_audio.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c 
>> b/drivers/gpu/drm/i915/display/intel_audio.c
>> index 1c87bf66b092..f0f0dfce27ce 100644
>> --- a/drivers/gpu/drm/i915/display/intel_audio.c
>> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
>> @@ -827,7 +827,7 @@ void intel_audio_codec_enable(struct intel_encoder 
>> *encoder,
>>  drm_dbg_kms(_priv->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Enable 
>> audio codec on pipe %c, %u bytes ELD\n",
>>  connector->base.id, connector->name,
>>  encoder->base.base.id, encoder->base.name,
>> -pipe, drm_eld_size(connector->eld));
>> +pipe_name(pipe), drm_eld_size(connector->eld));
>>  
>>  /* FIXME precompute the ELD in .compute_config() */
>>  if (!connector->eld[0])
>> @@ -888,7 +888,7 @@ void intel_audio_codec_disable(struct intel_encoder 
>> *encoder,
>>  
>>  drm_dbg_kms(_priv->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Disable 
>> audio codec on pipe %c\n",
>>  connector->base.id, connector->name,
>> -encoder->base.base.id, encoder->base.name, pipe);
>> +encoder->base.base.id, encoder->base.name, pipe_name(pipe));
>>  
>>  if (dev_priv->audio.funcs)
>>  dev_priv->audio.funcs->audio_codec_disable(encoder,
>> -- 
>> 2.30.2

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH] drm/i915: individualize fences before adding

[Nirmoy Das]

_i915_vma_move_to_active() can receive > 1 fence for
multiple batch buffer submission so make sure to
individualize fences before adding to dma_resv obj

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5614
Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/i915/i915_vma.c | 17 +
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 4f6db539571a..f987fc1264c0 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -23,6 +23,7 @@
  */
 
 #include 
+#include 
 #include 
 
 #include "display/intel_frontbuffer.h"
@@ -1840,8 +1841,12 @@ int _i915_vma_move_to_active(struct i915_vma *vma,
}
 
if (fence) {
-   dma_resv_add_fence(vma->obj->base.resv, fence,
-  DMA_RESV_USAGE_WRITE);
+   int idx;
+   struct dma_fence *curr;
+
+   dma_fence_array_for_each(curr, idx, fence)
+   dma_resv_add_fence(vma->obj->base.resv, curr,
+  DMA_RESV_USAGE_WRITE);
obj->write_domain = I915_GEM_DOMAIN_RENDER;
obj->read_domains = 0;
}
@@ -1853,8 +1858,12 @@ int _i915_vma_move_to_active(struct i915_vma *vma,
}
 
if (fence) {
-   dma_resv_add_fence(vma->obj->base.resv, fence,
-  DMA_RESV_USAGE_READ);
+   int idx;
+   struct dma_fence *curr;
+
+   dma_fence_array_for_each(curr, idx, fence)
+   dma_resv_add_fence(vma->obj->base.resv, curr,
+  DMA_RESV_USAGE_READ);
obj->write_domain = 0;
}
}
-- 
2.35.1

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Enable Tile4 tiling mode (rev3)

[Das, Nirmoy]

On 5/13/2022 1:01 PM, Patchwork wrote:

Project List - Patchwork *Patch Details*
*Series:*   drm/i915: Enable Tile4 tiling mode (rev3)
*URL:*  https://patchwork.freedesktop.org/series/103881/
*State:*failure
*Details:* 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/index.html



  CI Bug Log - changes from CI_DRM_11646_full -> Patchwork_103881v3_full


Summary

*FAILURE*

Serious unknown changes coming with Patchwork_103881v3_full absolutely 
need to be

verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_103881v3_full, please notify your bug team to 
allow them
to document this new failure mode, which will reduce false positives 
in CI.



Participating hosts (11 -> 11)

No changes in participating hosts


Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_103881v3_full:



  IGT changes


Possible regressions

  * igt@kms_cursor_crc@pipe-a-cursor-dpms:
  o shard-tglb: PASS


-> INCOMPLETE





This is unrelated as this patch only changes igt@i915_selftest@live@client


Regards,

Nirmoy


 *


Known issues

Here are the changes found in Patchwork_103881v3_full that come from 
known issues:



  IGT changes


Issues hit

 *

igt@gem_exec_fair@basic-deadline:

  o shard-kbl: PASS


-> FAIL


(i915#2846 )
 *

igt@gem_exec_fair@basic-none@vcs0:

  o shard-apl: PASS


-> FAIL


(i915#2842 )
 *

igt@gem_exec_fair@basic-pace@vecs0:

  o shard-glk: PASS


-> FAIL


(i915#2842
) +2
similar issues
 *

igt@gem_exec_flush@basic-batch-kernel-default-wb:

  o shard-snb: PASS


-> SKIP


(fdo#109271
) +3
similar issues
 *

igt@gem_lmem_swapping@heavy-random:

  o shard-tglb: NOTRUN -> SKIP


(i915#4613 )
 *

igt@gem_lmem_swapping@heavy-verify-random:

 o

shard-kbl: NOTRUN -> SKIP


(fdo#109271
 /
i915#4613 )

 o

shard-skl: NOTRUN -> SKIP


(fdo#109271
 /
i915#4613
) +2
similar issues

 *

igt@gem_pwrite@basic-exhaustion:

  o shard-apl: NOTRUN -> WARN


(i915#2658 )
 *

igt@gem_pxp@display-protected-crc:

  o shard-tglb: NOTRUN -> SKIP


(i915#4270 )
 *

igt@gem_userptr_blits@unsync-overlap:

  o shard-tglb: NOTRUN -> SKIP

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Enable Tile4 tiling mode (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable Tile4 tiling mode (rev3)
URL   : https://patchwork.freedesktop.org/series/103881/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11646_full -> Patchwork_103881v3_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_103881v3_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_103881v3_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_103881v3_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_cursor_crc@pipe-a-cursor-dpms:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-tglb3/igt@kms_cursor_...@pipe-a-cursor-dpms.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb8/igt@kms_cursor_...@pipe-a-cursor-dpms.html

  
Known issues


  Here are the changes found in Patchwork_103881v3_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fair@basic-deadline:
- shard-kbl:  [PASS][3] -> [FAIL][4] ([i915#2846])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-kbl6/igt@gem_exec_f...@basic-deadline.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-kbl6/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-apl:  [PASS][5] -> [FAIL][6] ([i915#2842])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-apl4/igt@gem_exec_fair@basic-n...@vcs0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-apl8/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
- shard-glk:  [PASS][7] -> [FAIL][8] ([i915#2842]) +2 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-glk6/igt@gem_exec_fair@basic-p...@vecs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-glk1/igt@gem_exec_fair@basic-p...@vecs0.html

  * igt@gem_exec_flush@basic-batch-kernel-default-wb:
- shard-snb:  [PASS][9] -> [SKIP][10] ([fdo#109271]) +3 similar 
issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-snb7/igt@gem_exec_fl...@basic-batch-kernel-default-wb.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-snb6/igt@gem_exec_fl...@basic-batch-kernel-default-wb.html

  * igt@gem_lmem_swapping@heavy-random:
- shard-tglb: NOTRUN -> [SKIP][11] ([i915#4613])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@gem_lmem_swapp...@heavy-random.html

  * igt@gem_lmem_swapping@heavy-verify-random:
- shard-kbl:  NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-kbl4/igt@gem_lmem_swapp...@heavy-verify-random.html
- shard-skl:  NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) +2 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-skl8/igt@gem_lmem_swapp...@heavy-verify-random.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-apl:  NOTRUN -> [WARN][14] ([i915#2658])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-apl1/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_pxp@display-protected-crc:
- shard-tglb: NOTRUN -> [SKIP][15] ([i915#4270])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@gem_...@display-protected-crc.html

  * igt@gem_userptr_blits@unsync-overlap:
- shard-tglb: NOTRUN -> [SKIP][16] ([i915#3297])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@gem_userptr_bl...@unsync-overlap.html

  * igt@gen9_exec_parse@allowed-single:
- shard-glk:  [PASS][17] -> [DMESG-WARN][18] ([i915#5566] / 
[i915#716])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-glk4/igt@gen9_exec_pa...@allowed-single.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-glk1/igt@gen9_exec_pa...@allowed-single.html

  * igt@gen9_exec_parse@bb-start-cmd:
- shard-tglb: NOTRUN -> [SKIP][19] ([i915#2527] / [i915#2856])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@gen9_exec_pa...@bb-start-cmd.html

  * igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#658])
   [20]: 

Re: [Intel-gfx] [PATCH] drm/i915: Fix CFI violation with show_dynamic_id()

[Tvrtko Ursulin]

On 12/05/2022 22:17, Nathan Chancellor wrote:

When an attribute group is created with sysfs_create_group(), the
->sysfs_ops() callback is set to kobj_sysfs_ops, which sets the ->show()
callback to kobj_attr_show(). kobj_attr_show() uses container_of() to
get the ->show() callback from the attribute it was passed, meaning the
->show() callback needs to be the same type as the ->show() callback in
'struct kobj_attribute'.

However, show_dynamic_id() has the type of the ->show() callback in
'struct device_attribute', which causes a CFI violation when opening the
'id' sysfs node under drm/card0/metrics. This happens to work because
the layout of 'struct kobj_attribute' and 'struct device_attribute' are
the same, so the container_of() cast happens to allow the ->show()
callback to still work.

Change the type of show_dynamic_id() to match the ->show() callback in
'struct kobj_attributes' and update the type of sysfs_metric_id to
match, which resolves the CFI violation.

Fixes: f89823c21224 ("drm/i915/perf: Implement I915_PERF_ADD/REMOVE_CONFIG 
interface")
Signed-off-by: Nathan Chancellor 


Merged to drm-intel-gt-next, thanks for the fix and reviews!

Regards,

Tvrtko


---
  drivers/gpu/drm/i915/i915_perf.c   | 4 ++--
  drivers/gpu/drm/i915/i915_perf_types.h | 2 +-
  2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 0a9c3fcc09b1..1577ab6754db 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4050,8 +4050,8 @@ static struct i915_oa_reg *alloc_oa_regs(struct i915_perf 
*perf,
return ERR_PTR(err);
  }
  
-static ssize_t show_dynamic_id(struct device *dev,

-  struct device_attribute *attr,
+static ssize_t show_dynamic_id(struct kobject *kobj,
+  struct kobj_attribute *attr,
   char *buf)
  {
struct i915_oa_config *oa_config =
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h 
b/drivers/gpu/drm/i915/i915_perf_types.h
index 473a3c0544bb..05cb9a335a97 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -55,7 +55,7 @@ struct i915_oa_config {
  
  	struct attribute_group sysfs_metric;

struct attribute *attrs[2];
-   struct device_attribute sysfs_metric_id;
+   struct kobj_attribute sysfs_metric_id;
  
  	struct kref ref;

struct rcu_head rcu;

base-commit: 7ecc3cc8a7b39f08eee9aea7b718187583342a70

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix CFI violation with show_dynamic_id()

[Patchwork]

== Series Details ==

Series: drm/i915: Fix CFI violation with show_dynamic_id()
URL   : https://patchwork.freedesktop.org/series/103968/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11646_full -> Patchwork_103968v1_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_103968v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][1] ([i915#2842])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_fair@basic-pace@vecs0:
- shard-glk:  [PASS][2] -> [FAIL][3] ([i915#2842]) +2 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-glk6/igt@gem_exec_fair@basic-p...@vecs0.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/shard-glk2/igt@gem_exec_fair@basic-p...@vecs0.html

  * igt@gem_exec_flush@basic-batch-kernel-default-wb:
- shard-snb:  [PASS][4] -> [SKIP][5] ([fdo#109271]) +2 similar 
issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-snb7/igt@gem_exec_fl...@basic-batch-kernel-default-wb.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/shard-snb6/igt@gem_exec_fl...@basic-batch-kernel-default-wb.html

  * igt@gem_exec_whisper@basic-fds-forked-all:
- shard-tglb: [PASS][6] -> [INCOMPLETE][7] ([i915#5966])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-tglb7/igt@gem_exec_whis...@basic-fds-forked-all.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/shard-tglb2/igt@gem_exec_whis...@basic-fds-forked-all.html

  * igt@gem_lmem_swapping@heavy-random:
- shard-tglb: NOTRUN -> [SKIP][8] ([i915#4613])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/shard-tglb3/igt@gem_lmem_swapp...@heavy-random.html

  * igt@gem_lmem_swapping@heavy-verify-random:
- shard-skl:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +2 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/shard-skl4/igt@gem_lmem_swapp...@heavy-verify-random.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-apl:  NOTRUN -> [WARN][10] ([i915#2658])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/shard-apl4/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_pxp@display-protected-crc:
- shard-tglb: NOTRUN -> [SKIP][11] ([i915#4270])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/shard-tglb3/igt@gem_...@display-protected-crc.html

  * igt@gem_userptr_blits@unsync-overlap:
- shard-tglb: NOTRUN -> [SKIP][12] ([i915#3297])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/shard-tglb3/igt@gem_userptr_bl...@unsync-overlap.html

  * igt@gen7_exec_parse@basic-rejected:
- shard-iclb: NOTRUN -> [SKIP][13] ([fdo#109289])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/shard-iclb8/igt@gen7_exec_pa...@basic-rejected.html

  * igt@gen9_exec_parse@bb-start-cmd:
- shard-tglb: NOTRUN -> [SKIP][14] ([i915#2527] / [i915#2856])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/shard-tglb3/igt@gen9_exec_pa...@bb-start-cmd.html

  * igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-tglb: NOTRUN -> [SKIP][15] ([fdo#109506] / [i915#2411])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/shard-tglb3/igt@i915_pm_...@modeset-pc8-residency-stress.html

  * igt@i915_query@query-topology-unsupported:
- shard-tglb: NOTRUN -> [SKIP][16] ([fdo#109302])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/shard-tglb3/igt@i915_qu...@query-topology-unsupported.html

  * igt@i915_selftest@live@hangcheck:
- shard-snb:  [PASS][17] -> [INCOMPLETE][18] ([i915#3921])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-snb5/igt@i915_selftest@l...@hangcheck.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/shard-snb6/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#5286])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/shard-iclb8/igt@kms_big...@4-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
- shard-tglb: NOTRUN -> [SKIP][20] ([i915#5286]) +1 similar issue
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/shard-tglb3/igt@kms_big...@4-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
- shard-apl: 

[Intel-gfx] [PATCH v3] drm/i915/d12+: Disable DMC firmware flip queue handlers

[Imre Deak]

Based on a bspec update the DMC firmware's flip queue handling events
need to be disabled before enabling DC5/6. i915 doesn't use the flip
queue feature atm, so disable it already after loading the firmware.
This removes some overhead of the event handler which runs at a 1 kHz
frequency.

Bspec: 49193, 72486, 72487

v2:
- Fix the DMC pipe A register offsets for GEN12.
- Disable the events on DG2 only on pipe A..D .
v3: (Lucas)
- Add TODO: to clarify the disabling sequence on all D13+
- s/intel_dmc_has_fw_payload/has_dmc_id_fw/
- s/simple_flipq/flipq/
- s/_GEN12,_GEN13/TGL_,ADLP_/
- s/MAINDMC/DMC/

Signed-off-by: Imre Deak 
Reviewed-by: Anusha Srivatsa  # v1
Reviewed-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/display/intel_dmc.c  | 90 ++-
 drivers/gpu/drm/i915/display/intel_dmc_regs.h | 41 +
 2 files changed, 130 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c 
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 2f01aca4d9810..7f50d697acaff 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -248,9 +248,14 @@ struct stepping_info {
char substepping;
 };
 
+static bool has_dmc_id_fw(struct drm_i915_private *i915, int dmc_id)
+{
+   return i915->dmc.dmc_info[dmc_id].payload;
+}
+
 bool intel_dmc_has_payload(struct drm_i915_private *i915)
 {
-   return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
+   return has_dmc_id_fw(i915, DMC_FW_MAIN);
 }
 
 static const struct stepping_info *
@@ -272,6 +277,82 @@ static void gen9_set_dc_state_debugmask(struct 
drm_i915_private *dev_priv)
intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
 }
 
+static void
+disable_flip_queue_event(struct drm_i915_private *i915,
+i915_reg_t ctl_reg, i915_reg_t htp_reg)
+{
+   u32 event_ctl;
+   u32 event_htp;
+
+   event_ctl = intel_de_read(i915, ctl_reg);
+   event_htp = intel_de_read(i915, htp_reg);
+   if (event_ctl != (DMC_EVT_CTL_ENABLE |
+ DMC_EVT_CTL_RECURRING |
+ REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
+DMC_EVT_CTL_TYPE_EDGE_0_1) |
+ REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
+DMC_EVT_CTL_EVENT_ID_CLK_MSEC)) ||
+   !event_htp) {
+   drm_dbg_kms(>drm,
+   "Unexpected DMC event configuration (control %08x 
htp %08x)\n",
+   event_ctl, event_htp);
+   return;
+   }
+
+   intel_de_write(i915, ctl_reg,
+  REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
+ DMC_EVT_CTL_TYPE_EDGE_0_1) |
+  REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
+ DMC_EVT_CTL_EVENT_ID_FALSE));
+   intel_de_write(i915, htp_reg, 0);
+}
+
+static bool
+get_flip_queue_event_regs(struct drm_i915_private *i915, int dmc_id,
+ i915_reg_t *ctl_reg, i915_reg_t *htp_reg)
+{
+   switch (dmc_id) {
+   case DMC_FW_MAIN:
+   if (DISPLAY_VER(i915) == 12) {
+   *ctl_reg = DMC_EVT_CTL(i915, dmc_id, 3);
+   *htp_reg = DMC_EVT_HTP(i915, dmc_id, 3);
+
+   return true;
+   }
+   break;
+   case DMC_FW_PIPEA ... DMC_FW_PIPED:
+   /* TODO: check if the following applies to all D13+ platforms. 
*/
+   if (IS_DG2(i915)) {
+   *ctl_reg = DMC_EVT_CTL(i915, dmc_id, 2);
+   *htp_reg = DMC_EVT_HTP(i915, dmc_id, 2);
+
+   return true;
+   }
+   break;
+   }
+
+   return false;
+}
+
+static void
+disable_all_flip_queue_events(struct drm_i915_private *i915)
+{
+   int dmc_id;
+
+   for (dmc_id = 0; dmc_id < DMC_FW_MAX; dmc_id++) {
+   i915_reg_t ctl_reg;
+   i915_reg_t htp_reg;
+
+   if (!has_dmc_id_fw(i915, dmc_id))
+   continue;
+
+   if (!get_flip_queue_event_regs(i915, dmc_id, _reg, 
_reg))
+   continue;
+
+   disable_flip_queue_event(i915, ctl_reg, htp_reg);
+   }
+}
+
 /**
  * intel_dmc_load_program() - write the firmware from memory to register.
  * @dev_priv: i915 drm device.
@@ -312,6 +393,13 @@ void intel_dmc_load_program(struct drm_i915_private 
*dev_priv)
dev_priv->dmc.dc_state = 0;
 
gen9_set_dc_state_debugmask(dev_priv);
+
+   /*
+* Flip queue events need to be disabled before enabling DC5/6.
+* i915 doesn't use the flip queue feature, so disable it already
+* here.
+*/
+   disable_all_flip_queue_events(dev_priv);
 }
 
 void assert_dmc_loaded(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable Tile4 tiling mode (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable Tile4 tiling mode (rev3)
URL   : https://patchwork.freedesktop.org/series/103881/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11646 -> Patchwork_103881v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/index.html

Participating hosts (40 -> 39)
--

  Additional (4): bat-dg2-8 bat-jsl-2 fi-icl-u2 fi-hsw-4770 
  Missing(5): fi-rkl-11600 bat-dg1-6 fi-bsw-cyan bat-adlp-6 bat-rpls-2 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_103881v3:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_suspend@basic-s0@smem:
- {fi-ehl-2}: [DMESG-WARN][1] ([i915#5122]) -> [DMESG-WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/fi-ehl-2/igt@gem_exec_suspend@basic...@smem.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/fi-ehl-2/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- {bat-dg2-8}:NOTRUN -> [SKIP][3] +1 similar issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/bat-dg2-8/igt@i915_pm_...@basic-pci-d3-state.html

  
Known issues


  Here are the changes found in Patchwork_103881v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271]) +9 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/fi-hsw-4770/igt@gem_huc_c...@huc-copy.html
- fi-icl-u2:  NOTRUN -> [SKIP][5] ([i915#2190])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#3012])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][9] ([fdo#111827]) +8 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2:  NOTRUN -> [SKIP][10] ([fdo#109278]) +2 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2:  NOTRUN -> [SKIP][11] ([fdo#109285])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-hsw-4770:NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@primary_mmap_gtt:
- fi-hsw-4770:NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1072]) +3 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2:  NOTRUN -> [SKIP][14] ([i915#3555])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/fi-icl-u2/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- fi-icl-u2:  NOTRUN -> [SKIP][15] ([i915#3301])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/fi-icl-u2/igt@prime_v...@basic-userptr.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_timelines:
- {bat-dg2-9}:[DMESG-WARN][16] ([i915#5763]) -> [PASS][17] +1 
similar issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/bat-dg2-9/igt@i915_selftest@live@gt_timelines.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/bat-dg2-9/igt@i915_selftest@live@gt_timelines.html

  
  {name}: This element is suppressed. This means it is 

[Intel-gfx] [PATCH i-g-t] tests/core_hotunplug: Check sysfs reads after hotunplug

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Leave some sysfs files open and attempt to read from them after hotunplug.

Signed-off-by: Tvrtko Ursulin 
Cc: Ashutosh Dixit 
---
 tests/core_hotunplug.c | 62 ++
 1 file changed, 62 insertions(+)

diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c
index 02eae19e1e16..c3831541202d 100644
--- a/tests/core_hotunplug.c
+++ b/tests/core_hotunplug.c
@@ -602,6 +602,59 @@ static void hotreplug_lateclose(struct hotunplug *priv)
igt_assert_f(healthcheck(priv, false), "%s\n", priv->failure);
 }
 
+static void hotunplug_sysfs(struct hotunplug *priv)
+{
+   int i915, sysfs;
+   struct {
+   int fd;
+   const char *path;
+   char buf[256];
+   } *item, items[] = {
+   { .fd = -1, .path = "error" },
+   { .fd = -1, .path = "gt_act_freq_mhz" },
+   { .fd = -1, .path = "gt/gt0/rps_act_freq_mhz" },
+   { .fd = -1, .path = "gt/gt0/rc6_residency_ms" },
+   { .fd = -1, .path = "engine/rcs0/name" },
+   { .fd = -1, .path = "engine/bcs0/name" },
+   { .path = NULL },
+   };
+   unsigned int cnt = 0;
+
+   pre_check(priv);
+
+   i915 = local_drm_open_driver(false, "", " for hot unplug");
+   sysfs = igt_sysfs_open(i915);
+   igt_require(sysfs >= 0);
+   for (item = [0]; item->path; item++) {
+   item->fd = openat(sysfs, item->path, O_RDONLY);
+   cnt += item->fd >= 0;
+   }
+   close(sysfs);
+   close_device(i915, " ", "sysfs open ");
+
+   igt_require(cnt >= 3);
+
+   device_unplug(priv, "hot ", 60);
+
+   sleep(2);
+
+   for (item = [0]; item->path; item++) {
+   ssize_t len;
+   int err;
+
+   if (item->fd < 0)
+   continue;
+
+   len = read(item->fd, item->buf, sizeof(item->buf));
+   err = len < 0 ? -errno : 0;
+   close(item->fd);
+   igt_debug("%s='%s' (%d)\n", item->path, item->buf, err);
+   igt_assert_eq(err, -ENODEV);
+   }
+
+   igt_assert_f(healthcheck(priv, false), "%s\n", priv->failure);
+}
+
 /* Main */
 
 igt_main
@@ -735,6 +788,15 @@ igt_main
recover();
}
 
+   igt_subtest_group {
+   igt_describe("Check if sysfs files left open can be safely 
accessed after hotunplug.");
+   igt_subtest("hotunplug-sysfs")
+   hotunplug_sysfs();
+
+   igt_fixture
+   recover();
+   }
+
igt_fixture {
post_healthcheck();
 
-- 
2.32.0

Re: [Intel-gfx] [PATCH 6/8] drm/i915/gt: Fix memory leaks in per-gt sysfs

[Tvrtko Ursulin]

On 13/05/2022 06:05, Dixit, Ashutosh wrote:

On Thu, 12 May 2022 00:48:08 -0700, Tvrtko Ursulin wrote:

Hi Tvrtko,


On 12/05/2022 00:15, Dixit, Ashutosh wrote:

On Tue, 10 May 2022 03:41:57 -0700, Andrzej Hajda wrote:

On 10.05.2022 11:48, Tvrtko Ursulin wrote:

On 10/05/2022 10:39, Andrzej Hajda wrote:

On 10.05.2022 10:18, Tvrtko Ursulin wrote:


Was there closure/agreement on the matter of whether or not there is
a potential race between "kfree(gt)" and sysfs access (last put from
sysfs that is)? I've noticed Andrzej and Ashutosh were discussing it
but did not read all the details.



Not really :)
IMO docs are against this practice, Ashutosh shows examples of this
practice in code and according to his analysis it is safe.
I gave up looking for contradictions :) Either it is OK, kobject is
not fully shared object, docs are obsolete and needs update, either
the patch is wrong.
Anyway finally I tend to accept this solution, I failed to prove it is
wrong :)


Like a question of whether hotunplug can be triggered while userspace
is sitting in a sysfs hook? Final kfree then has to be delayed until
userspace exists.

Btw where is the "kfree(gt)" for the tiles on the PCI remove path? I
can't find it.. Do we have a leak?


intel_gt_tile_cleanup ?


Called from intel_gt_release_all, whose only caller is the failure path
of i915_driver_probe. Feels like something is missing?


This is final proof this patch is safe - no kfree, no UAF :)

Apparently it is broken in internal branch as well.
Should I take care of it?


See Daniele's comment here:

https://patchwork.freedesktop.org/patch/478856/?series=101551=1


Yeah we found that same leak yesterday, or the day before in this thread.


We clean up the gt sysfs during PCI device remove (i915_driver_remove ->
i915_driver_unregister -> intel_gt_driver_unregister ->
intel_gt_sysfs_unregister (added in this patch)). But from Daniele's mail
it appears that "kfree(gt)" can only be done from i915_driver_release().

So as long as i915_driver_release() always happens after
i915_driver_remove() (which seems to be the case though I couldn't figure
out why (i.e. who is putting the final reference of the drm device)) there
is no UAF and no race. Thanks!


No worried by the unknown?


Well if release() happens before or during remove() then (as is clear from
Daniele's mail) we have a much bigger problem than sysfs on our hands and
will see UAF crashes during device remove/unbind. But as far as we know no
such crashes have been reported.


I had a quick look whether core_hotunplug tests for sysfs interactions
but couldn't spot it. What I had in mind is userspace stuck in a sysfs
hook (say read into a userfaultfd buffer) with device hotunplug in
parallel. Maybe it is all handled already, not claiming that it isn't.


This is the 20 year old issue mentioned by Andrzej here:
https://lwn.net/Articles/36850/

So I thought I'll try this out today and see what actually happens to
settle this. And you will see it makes perfect sense. So this is what I
did:

* Change IGT to add a 20 second sleep after opening a sysfs file
* In that 20 second period, with an open fd, unbind the device using:
echo -n ":03:00.0" > /sys/bus/pci/drivers/i915/unbind
   And also rmmod i915.

So this is what we see when we do this:
* As soon as the device is unbound, the complete i915 sysfs tree (under
   /sys/card/drm/card0) is cleanly removed (even with the open fd in IGT).
* The fd open in IGT is now orphan/invalid, so when IGT resumes and tries
   to use that fd IGT crashes.
* So no problem with device unbind but if IGT is still hanging around rmmod
   fails (saying module is in use, most likely due to the still open drm fd)
   but after IGT is completely killed rmmod is also fine.

So this confirms all this is correctly handled.


I was unsure what does "IGT crashes" exactly meant so I went to try it 
out myself. It's -ENODEV from read(2) it receives so it all indeed seems 
handled fine.


Although hotunplug seems generally very unhealthy, at least on 
5.18.0-rc8 I tested on.. I'll send my subtest to the mailing list in 
case it is consider useful to have it.


Regards,

Tvrtko



Separately, note that kobject_put's introduced in this patch are only
needed for freeing the memory allocated for the kobject's themselves (or
their containing struct's). kobject_put's don't play a role in cleaning up
the sysfs hierarchy itself (which will get cleaned up even without the
kobject_put's). Further, child kobject's take a reference on their parents
so child kobjects need a kobject_put before the parent kobject_put to free
the memory allocated for the parent (i.e. doing a kobject_put on the parent
will not automatically free all the child kobjects).

Thanks.
--
Ashutosh

[Intel-gfx] [PATCH v3] drm/i915: Enable Tile4 tiling mode

[Nirmoy Das]

From: Bommu Krishnaiah 

Enable Tile4 tiling mode on platform that supports
Tile4 but no TileY like DG2.

v3: add a function to find X-tile availability for a platform.
v2: disable X-tile for iGPU in fastblit
fix checkpath --strict warnings

Signed-off-by: Bommu Krishnaiah 
Co-developed-by: Nirmoy Das 
Signed-off-by: Nirmoy Das 
---
 .../i915/gem/selftests/i915_gem_client_blt.c  | 250 ++
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h  |  22 ++
 2 files changed, 227 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index ddd0772fd828..3cfc621ef363 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -6,6 +6,7 @@
 #include "i915_selftest.h"
 
 #include "gt/intel_context.h"
+#include "gt/intel_engine_regs.h"
 #include "gt/intel_engine_user.h"
 #include "gt/intel_gpu_commands.h"
 #include "gt/intel_gt.h"
@@ -18,10 +19,71 @@
 #include "huge_gem_object.h"
 #include "mock_context.h"
 
+#define OW_SIZE 16  /* in bytes */
+#define F_SUBTILE_SIZE 64   /* in bytes */
+#define F_TILE_WIDTH 128/* in bytes */
+#define F_TILE_HEIGHT 32/* in pixels */
+#define F_SUBTILE_WIDTH  OW_SIZE/* in bytes */
+#define F_SUBTILE_HEIGHT 4  /* in pixels */
+
+static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp)
+{
+   int tile_base;
+   int tile_x, tile_y;
+   int swizzle, subtile;
+   int pixel_size = bpp / 8;
+   int pos;
+
+   /*
+* Subtile remapping for F tile. Note that map[a]==b implies map[b]==a
+* so we can use the same table to tile and until.
+*/
+   static const u8 f_subtile_map[] = {
+0,  1,  2,  3,  8,  9, 10, 11,
+4,  5,  6,  7, 12, 13, 14, 15,
+   16, 17, 18, 19, 24, 25, 26, 27,
+   20, 21, 22, 23, 28, 29, 30, 31,
+   32, 33, 34, 35, 40, 41, 42, 43,
+   36, 37, 38, 39, 44, 45, 46, 47,
+   48, 49, 50, 51, 56, 57, 58, 59,
+   52, 53, 54, 55, 60, 61, 62, 63
+   };
+
+   x *= pixel_size;
+   /*
+* Where does the 4k tile start (in bytes)?  This is the same for Y and
+* F so we can use the Y-tile algorithm to get to that point.
+*/
+   tile_base =
+   y / F_TILE_HEIGHT * stride * F_TILE_HEIGHT +
+   x / F_TILE_WIDTH * 4096;
+
+   /* Find pixel within tile */
+   tile_x = x % F_TILE_WIDTH;
+   tile_y = y % F_TILE_HEIGHT;
+
+   /* And figure out the subtile within the 4k tile */
+   subtile = tile_y / F_SUBTILE_HEIGHT * 8 + tile_x / F_SUBTILE_WIDTH;
+
+   /* Swizzle the subtile number according to the bspec diagram */
+   swizzle = f_subtile_map[subtile];
+
+   /* Calculate new position */
+   pos = tile_base +
+   swizzle * F_SUBTILE_SIZE +
+   tile_y % F_SUBTILE_HEIGHT * OW_SIZE +
+   tile_x % F_SUBTILE_WIDTH;
+
+   GEM_BUG_ON(!IS_ALIGNED(pos, pixel_size));
+
+   return pos / pixel_size * 4;
+}
+
 enum client_tiling {
CLIENT_TILING_LINEAR,
CLIENT_TILING_X,
CLIENT_TILING_Y,
+   CLIENT_TILING_4,
CLIENT_NUM_TILING_TYPES
 };
 
@@ -45,6 +107,36 @@ struct tiled_blits {
u32 height;
 };
 
+static bool supports_x_tiling(const struct drm_i915_private *i915)
+{
+   int gen = GRAPHICS_VER(i915);
+
+   if (gen < 12)
+   return true;
+
+   if (!HAS_LMEM(i915) || IS_DG1(i915))
+   return false;
+
+   return true;
+}
+
+static bool fast_blit_ok(const struct blit_buffer *buf)
+{
+   int gen = GRAPHICS_VER(buf->vma->vm->i915);
+
+   if (gen < 9)
+   return false;
+
+   if (gen < 12)
+   return true;
+
+   /* filter out platforms with unsupported X-tile support in fastblit */
+   if (buf->tiling == CLIENT_TILING_X && 
!supports_x_tiling(buf->vma->vm->i915))
+   return false;
+
+   return true;
+}
+
 static int prepare_blit(const struct tiled_blits *t,
struct blit_buffer *dst,
struct blit_buffer *src,
@@ -59,51 +151,103 @@ static int prepare_blit(const struct tiled_blits *t,
if (IS_ERR(cs))
return PTR_ERR(cs);
 
-   *cs++ = MI_LOAD_REGISTER_IMM(1);
-   *cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
-   cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
-   if (src->tiling == CLIENT_TILING_Y)
-   cmd |= BCS_SRC_Y;
-   if (dst->tiling == CLIENT_TILING_Y)
-   cmd |= BCS_DST_Y;
-   *cs++ = cmd;
-
-   cmd = MI_FLUSH_DW;
-   if (ver >= 8)
-   cmd++;
-   *cs++ = cmd;
-   *cs++ = 0;
-   *cs++ = 0;
-   *cs++ = 0;
-
-   cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix CFI violation with show_dynamic_id()

[Patchwork]

== Series Details ==

Series: drm/i915: Fix CFI violation with show_dynamic_id()
URL   : https://patchwork.freedesktop.org/series/103968/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11646 -> Patchwork_103968v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/index.html

Participating hosts (40 -> 42)
--

  Additional (5): bat-dg2-8 bat-adlm-1 fi-icl-u2 fi-hsw-4770 bat-jsl-2 
  Missing(3): fi-bsw-cyan bat-dg1-6 fi-pnv-d510 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_103968v1:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rpm@basic-pci-d3-state:
- {bat-dg2-8}:NOTRUN -> [SKIP][1] +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/bat-dg2-8/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@i915_selftest@live@requests:
- {bat-adlm-1}:   NOTRUN -> [INCOMPLETE][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/bat-adlm-1/igt@i915_selftest@l...@requests.html

  
Known issues


  Here are the changes found in Patchwork_103968v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271]) +9 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/fi-hsw-4770/igt@gem_huc_c...@huc-copy.html
- fi-icl-u2:  NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#3012])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@gem:
- fi-blb-e6850:   NOTRUN -> [DMESG-FAIL][7] ([i915#4528])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/fi-blb-e6850/igt@i915_selftest@l...@gem.html

  * igt@i915_selftest@live@gtt:
- fi-bdw-5557u:   [PASS][8] -> [DMESG-FAIL][9] ([i915#3674])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html
- fi-icl-u2:  NOTRUN -> [INCOMPLETE][10] ([i915#4324])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/fi-icl-u2/igt@i915_selftest@l...@gtt.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][12] ([fdo#111827]) +7 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2:  NOTRUN -> [SKIP][13] ([fdo#109278]) +2 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2:  NOTRUN -> [SKIP][14] ([fdo#109285])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-hsw-4770:NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#533])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@primary_mmap_gtt:
- fi-hsw-4770:NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#1072]) +3 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2:  NOTRUN -> [SKIP][17] ([i915#3555])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103968v1/fi-icl-u2/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- fi-icl-u2:  NOTRUN -> [SKIP][18] 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Fix CFI violation with show_dynamic_id()

[Patchwork]

== Series Details ==

Series: drm/i915: Fix CFI violation with show_dynamic_id()
URL   : https://patchwork.freedesktop.org/series/103968/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [5.18 regression] drm/i915 BYT rendering broken due to "Remove short-term pins from execbuf, v6" #forregzbot

[Thorsten Leemhuis]

TWIMC: this mail is primarily send for documentation purposes and for
regzbot, my Linux kernel regression tracking bot. These mails usually
contain '#forregzbot' in the subject, to make them easy to spot and filter.

On 09.05.22 09:01, Thorsten Leemhuis wrote:
> [TLDR: I'm adding this regression report to the list of tracked
> regressions; all text from me you find below is based on a few templates
> paragraphs you might have encountered already already in similar form.]
> 
> Hi, this is your Linux kernel regression tracker. Top-posting for once,
> to make this easily accessible to everyone.
> 
> Thanks for the report.
> 
> To be sure below issue doesn't fall through the cracks unnoticed, I'm
> adding it to regzbot, my Linux kernel regression tracking bot:
> 
> #regzbot ^introduced b5cfe6f7a6e1
> #regzbot title drm/i915: BYT rendering broken due to "Remove short-term
> pins from execbuf, v6"
> #regzbot ignore-activity

#regzbot link: https://gitlab.freedesktop.org/drm/intel/-/issues/5806
#regzbot monitor:
https://lore.kernel.org/all/2022055219.46507-1-maarten.lankho...@linux.intel.com/

> This isn't a regression? This issue or a fix for it are already
> discussed somewhere else? It was fixed already? You want to clarify when
> the regression started to happen? Or point out I got the title or
> something else totally wrong? Then just reply -- ideally with also
> telling regzbot about it, as explained here:
> https://linux-regtracking.leemhuis.info/tracked-regression/
> 
> Reminder for developers: When fixing the issue, add 'Link:' tags
> pointing to the report (the mail this one replied to), as the kernel's
> documentation call for; above page explains why this is important for
> tracked regressions.
> 
> Ciao, Thorsten (wearing his 'the Linux kernel's regression tracker' hat)
> 
> P.S.: As the Linux kernel's regression tracker I deal with a lot of
> reports and sometimes miss something important when writing mails like
> this. If that's the case here, don't hesitate to tell me in a public
> reply, it's in everyone's interest to set the public record straight.
> 
> 
> 
> On 08.05.22 16:38, Hans de Goede wrote:
>> Hi All,
>>
>> When running a 5.18-rc4 (and -rc5) kernel on a Chuwi Hi 8, which is
>> a Bay Trail based tablet with 2G RAM and a 1200x1920 DSI panel.
>> I noticed that gnome-shell was misrendering. Many UI elements were
>> missing (they were all black) and at the gdm login screen (which is
>> a special gnome-shell session) the screen often was entirely black
>> until I move the cursor around and then various things got
>> highlighted after which they sometimes stuck around and sometimes
>> they disappeared again after the highlight.
>>
>> Since this problem does not happen with various 5.17.y kernels I
>> believe that this is a kernel regression in 5.18. I've bisected this
>> and the bisect points to:
>>
>> commit b5cfe6f7a6e1 ("drm/i915: Remove short-term pins from execbuf, v6.")
>>
>> from Maarten. This commit cleanly reverts on top of 5.18-rc5 and
>> I can confirm that 5.18-rc5 with b5cfe6f7a6e1 reverted fixes things.
>>
>> I would be more then happy to test any possible fixes for this.
>>
>> Regards,
>>
>> Hans
>>
>>
>>

Re: [Intel-gfx] [PATCH v2] drm/i915/d12+: Disable DMC firmware flip queue handlers

[Imre Deak]

On Thu, May 12, 2022 at 03:37:14PM -0700, Lucas De Marchi wrote:
> On Thu, May 12, 2022 at 10:47:46PM +0300, Imre Deak wrote:
> > On Thu, May 12, 2022 at 10:56:11AM -0700, Lucas De Marchi wrote:
> > > On Thu, May 12, 2022 at 12:37:05PM +0300, Imre Deak wrote:
> > > > Based on a bspec update the DMC firmware's flip queue handling events
> > > > need to be disabled before enabling DC5/6. i915 doesn't use the flip
> > > > queue feature atm, so disable it already after loading the firmware.
> > > > This removes some overhead of the event handler which runs at a 1 kHz
> > > > frequency.
> > > >
> > > > Bspec: 49193, 72486, 72487
> > > >
> > > > v2:
> > > > - Fix the DMC pipe A register offsets for GEN12.
> > > > - Disable the events on DG2 only on pipe A..D .
> > > >
> > > > Signed-off-by: Imre Deak 
> > > > Reviewed-by: Anusha Srivatsa  # v1
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_dmc.c  | 89 ++-
> > > > drivers/gpu/drm/i915/display/intel_dmc_regs.h | 41 +
> > > > 2 files changed, 129 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c 
> > > > b/drivers/gpu/drm/i915/display/intel_dmc.c
> > > > index 257cf662f9f4b..0ede8c86c6ccb 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > > > @@ -244,9 +244,14 @@ struct stepping_info {
> > > > char substepping;
> > > > };
> > > >
> > > > +static bool intel_dmc_has_fw_payload(struct drm_i915_private *i915, 
> > > > int dmc_id)
> > > 
> > > in several places, including this file, we are trying to keep the
> > > convention of not using intel_ prefix for non-exported functions.
> > > 
> > > has_dmc_id_fw() here would read better IMO.
> > 
> > Ok.
> > 
> > > > +{
> > > > +   return i915->dmc.dmc_info[dmc_id].payload;
> > > > +}
> > > > +
> > > > bool intel_dmc_has_payload(struct drm_i915_private *i915)
> > > > {
> > > > -   return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
> > > > +   return intel_dmc_has_fw_payload(i915, DMC_FW_MAIN);
> > > > }
> > > >
> > > > static const struct stepping_info *
> > > > @@ -268,6 +273,81 @@ static void gen9_set_dc_state_debugmask(struct 
> > > > drm_i915_private *dev_priv)
> > > > intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
> > > > }
> > > >
> > > > +static void
> > > > +disable_simple_flip_queue_event(struct drm_i915_private *i915,
> > > > +   i915_reg_t ctl_reg, i915_reg_t htp_reg)
> > > > +{
> > > > +   u32 event_ctl;
> > > > +   u32 event_htp;
> > > > +
> > > > +   event_ctl = intel_de_read(i915, ctl_reg);
> > > > +   event_htp = intel_de_read(i915, htp_reg);
> > > > +   if (event_ctl != (DMC_EVT_CTL_ENABLE |
> > > > + DMC_EVT_CTL_RECURRING |
> > > > + REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
> > > > +DMC_EVT_CTL_TYPE_EDGE_0_1) |
> > > > + REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
> > > > +
> > > > DMC_EVT_CTL_EVENT_ID_CLK_MSEC)) ||
> > > > +   !event_htp) {
> > > > +   drm_dbg_kms(>drm,
> > > > +   "Unexpected DMC event configuration 
> > > > (control %08x htp %08x)\n",
> > > > +   event_ctl, event_htp);
> > > > +   return;
> > > > +   }
> > > 
> > > why are we doing this if we just want to disable? If we will always keep
> > > it disabled, then just writing the right values would be simpler.
> > 
> > The requirement to disable flip queues explicitly came only now,
> > somewhat as a surprise. Future firmware versions will disable it by
> > default, but it's not clear at which point and how the ABI will change
> > then. So I'd like to keep the above check for any such ABI change in
> > place at least until those plans get clarified to us.
> 
> humn... It seems weird to log "Unexpected DMC event... " if we are
> expecting that in future it will be disabled. But since it's a debug
> message only, it's not a big thing.
> 
> Later are you expecting to separate the an if condition like below?
> 
>   if (!(event_ctl & DMC_EVT_CTL_ENABLE)) {
>   drm_dbg_kms(>drm, "Skip flip queue disabling: already 
> disabled\n");
>   return;
>   }

I think after noticing via the above debug message that a given
platform/fw revision changed the MMIO list so that it doesn't enable the
flip queue events, we should adjust the platform/fw revision checks to
not call the disabling function for those.

> > > > +
> > > > +   intel_de_write(i915, ctl_reg,
> > > > +  REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
> > > > + DMC_EVT_CTL_TYPE_EDGE_0_1) |
> > > > +  REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
> > > > + DMC_EVT_CTL_EVENT_ID_FALSE));
> > > > +   

[Intel-gfx] [CI] drm/i915: Fix CFI violation with show_dynamic_id()

[Tvrtko Ursulin]

From: Nathan Chancellor 

When an attribute group is created with sysfs_create_group(), the
->sysfs_ops() callback is set to kobj_sysfs_ops, which sets the ->show()
callback to kobj_attr_show(). kobj_attr_show() uses container_of() to
get the ->show() callback from the attribute it was passed, meaning the
->show() callback needs to be the same type as the ->show() callback in
'struct kobj_attribute'.

However, show_dynamic_id() has the type of the ->show() callback in
'struct device_attribute', which causes a CFI violation when opening the
'id' sysfs node under drm/card0/metrics. This happens to work because
the layout of 'struct kobj_attribute' and 'struct device_attribute' are
the same, so the container_of() cast happens to allow the ->show()
callback to still work.

Change the type of show_dynamic_id() to match the ->show() callback in
'struct kobj_attributes' and update the type of sysfs_metric_id to
match, which resolves the CFI violation.

Fixes: f89823c21224 ("drm/i915/perf: Implement I915_PERF_ADD/REMOVE_CONFIG 
interface")
Signed-off-by: Nathan Chancellor 
Reviewed-by: Kees Cook 
Reviewed-by: Sami Tolvanen 
---
 drivers/gpu/drm/i915/i915_perf.c   | 4 ++--
 drivers/gpu/drm/i915/i915_perf_types.h | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 0a9c3fcc09b1..1577ab6754db 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4050,8 +4050,8 @@ static struct i915_oa_reg *alloc_oa_regs(struct i915_perf 
*perf,
return ERR_PTR(err);
 }
 
-static ssize_t show_dynamic_id(struct device *dev,
-  struct device_attribute *attr,
+static ssize_t show_dynamic_id(struct kobject *kobj,
+  struct kobj_attribute *attr,
   char *buf)
 {
struct i915_oa_config *oa_config =
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h 
b/drivers/gpu/drm/i915/i915_perf_types.h
index 473a3c0544bb..05cb9a335a97 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -55,7 +55,7 @@ struct i915_oa_config {
 
struct attribute_group sysfs_metric;
struct attribute *attrs[2];
-   struct device_attribute sysfs_metric_id;
+   struct kobj_attribute sysfs_metric_id;
 
struct kref ref;
struct rcu_head rcu;
-- 
2.32.0

Re: [Intel-gfx] [PATCH] drm/i915: Enable Tile4 tiling mode

[Das, Nirmoy]

On 5/13/2022 7:47 AM, Zbigniew Kempczyński wrote:

On Thu, May 12, 2022 at 03:26:00PM +0200, Nirmoy Das wrote:

From: Bommu Krishnaiah 

Enable Tile4 tiling mode on platform that supports
Tile4 but no TileY like DG2.

v2: disable X-tile for iGPU in fastblit
 fix checkpath --strict warnings

Signed-off-by: Bommu Krishnaiah 
Co-developed-by: Nirmoy Das 
Signed-off-by: Nirmoy Das 
---
  .../i915/gem/selftests/i915_gem_client_blt.c  | 235 ++
  drivers/gpu/drm/i915/gt/intel_gpu_commands.h  |  22 ++
  2 files changed, 212 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index ddd0772fd828..e16661029c78 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -6,6 +6,7 @@
  #include "i915_selftest.h"
  
  #include "gt/intel_context.h"

+#include "gt/intel_engine_regs.h"
  #include "gt/intel_engine_user.h"
  #include "gt/intel_gpu_commands.h"
  #include "gt/intel_gt.h"
@@ -18,10 +19,71 @@
  #include "huge_gem_object.h"
  #include "mock_context.h"
  
+#define OW_SIZE 16  /* in bytes */

+#define F_SUBTILE_SIZE 64   /* in bytes */
+#define F_TILE_WIDTH 128/* in bytes */
+#define F_TILE_HEIGHT 32/* in pixels */
+#define F_SUBTILE_WIDTH  OW_SIZE/* in bytes */
+#define F_SUBTILE_HEIGHT 4  /* in pixels */
+
+static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp)
+{
+   int tile_base;
+   int tile_x, tile_y;
+   int swizzle, subtile;
+   int pixel_size = bpp / 8;
+   int pos;
+
+   /*
+* Subtile remapping for F tile. Note that map[a]==b implies map[b]==a
+* so we can use the same table to tile and until.
+*/
+   static const u8 f_subtile_map[] = {
+0,  1,  2,  3,  8,  9, 10, 11,
+4,  5,  6,  7, 12, 13, 14, 15,
+   16, 17, 18, 19, 24, 25, 26, 27,
+   20, 21, 22, 23, 28, 29, 30, 31,
+   32, 33, 34, 35, 40, 41, 42, 43,
+   36, 37, 38, 39, 44, 45, 46, 47,
+   48, 49, 50, 51, 56, 57, 58, 59,
+   52, 53, 54, 55, 60, 61, 62, 63
+   };
+
+   x *= pixel_size;
+   /*
+* Where does the 4k tile start (in bytes)?  This is the same for Y and
+* F so we can use the Y-tile algorithm to get to that point.
+*/
+   tile_base =
+   y / F_TILE_HEIGHT * stride * F_TILE_HEIGHT +
+   x / F_TILE_WIDTH * 4096;
+
+   /* Find pixel within tile */
+   tile_x = x % F_TILE_WIDTH;
+   tile_y = y % F_TILE_HEIGHT;
+
+   /* And figure out the subtile within the 4k tile */
+   subtile = tile_y / F_SUBTILE_HEIGHT * 8 + tile_x / F_SUBTILE_WIDTH;
+
+   /* Swizzle the subtile number according to the bspec diagram */
+   swizzle = f_subtile_map[subtile];
+
+   /* Calculate new position */
+   pos = tile_base +
+   swizzle * F_SUBTILE_SIZE +
+   tile_y % F_SUBTILE_HEIGHT * OW_SIZE +
+   tile_x % F_SUBTILE_WIDTH;
+
+   GEM_BUG_ON(!IS_ALIGNED(pos, pixel_size));
+
+   return pos / pixel_size * 4;
+}
+
  enum client_tiling {
CLIENT_TILING_LINEAR,
CLIENT_TILING_X,
CLIENT_TILING_Y,
+   CLIENT_TILING_4,
CLIENT_NUM_TILING_TYPES
  };
  
@@ -45,6 +107,21 @@ struct tiled_blits {

u32 height;
  };
  
+static bool fast_blit_ok(struct blit_buffer *buf)

+{
+   int gen = GRAPHICS_VER(buf->vma->vm->i915);
+
+   if (gen < 9)
+   return false;
+
+   if (gen < 12)
+   return true;
+
+   /* filter out platforms with unsupported X-tile support(iGPUs and DG1) 
in fastblit */
+   return !((IS_DG1(buf->vma->vm->i915) || (gen == 12 && 
!HAS_LMEM(buf->vma->vm->i915))) &&
+   buf->tiling == CLIENT_TILING_X);
+}
+

What would you say for this:

static bool supports_x_tiling(const struct drm_i915_private *i915)
{
int gen = GRAPHICS_VER(i915);

if (gen < 12)
return true;

if (!HAS_LMEM(i915) || IS_DG1(i915))
return false;

return true;
}

static bool fast_blit_ok(const struct blit_buffer *buf)
{
int gen = GRAPHICS_VER(buf->vma->vm->i915);

if (gen < 9)
return false;

if (gen < 12)
return true;

/* filter out platforms with unsupported X-tile support in fastblit */
if (buf->tiling == CLIENT_TILING_X && 
!supports_x_tiling(buf->vma->vm->i915))
return false;

return true;
}



Looks better, I  resend with that.


Thanks,

Nirmoy



Rest code looks good to me.

--
Zbigniew


  static int prepare_blit(const struct tiled_blits *t,
struct blit_buffer *dst,
struct blit_buffer *src,
@@ -59,51 

[Intel-gfx] [PULL] drm-misc-fixes

[Maxime Ripard]

Hi Dave, Daniel,

Here's this week drm-misc-fixes. drm-misc-next-fixes is empty at the
moment, so there won't be a PR for it this week.

Thanks!
Maxime

drm-misc-fixes-2022-05-13:
Multiple fixes to fbdev to address a regression at unregistration, an
iommu detection improvement for nouveau, a memory leak fix for nouveau,
pointer dereference fix for dma_buf_file_release(), and a build breakage
fix for vc4
The following changes since commit c5eb0a61238dd6faf37f58c9ce61c9980aaffd7a:

  Linux 5.18-rc6 (2022-05-08 13:54:17 -0700)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2022-05-13

for you to fetch changes up to 6fed53de560768bde6d701a7c79c253b45b259e3:

  drm/vc4: hdmi: Fix build error for implicit function declaration (2022-05-12 
11:01:19 +0200)


Multiple fixes to fbdev to address a regression at unregistration, an
iommu detection improvement for nouveau, a memory leak fix for nouveau,
pointer dereference fix for dma_buf_file_release(), and a build breakage
fix for vc4


Charan Teja Reddy (1):
  dma-buf: call dma_buf_stats_setup after dmabuf is in valid list

Christophe JAILLET (1):
  drm/nouveau: Fix a potential theorical leak in 
nouveau_get_backlight_name()

Daniel Vetter (1):
  fbdev: Prevent possible use-after-free in fb_release()

Hui Tang (1):
  drm/vc4: hdmi: Fix build error for implicit function declaration

Javier Martinez Canillas (5):
  Revert "fbdev: Make fb_release() return -ENODEV if fbdev was unregistered"
  fbdev: simplefb: Cleanup fb_info in .fb_destroy rather than .remove
  fbdev: efifb: Cleanup fb_info in .fb_destroy rather than .remove
  fbdev: vesafb: Cleanup fb_info in .fb_destroy rather than .remove
  fbdev: efifb: Fix a use-after-free due early fb_info cleanup

Maarten Lankhorst (1):
  Merge remote-tracking branch 'drm/drm-fixes' into drm-misc-fixes

Robin Murphy (1):
  drm/nouveau/tegra: Stop using iommu_present()

 drivers/dma-buf/dma-buf.c  | 8 
 drivers/gpu/drm/nouveau/nouveau_backlight.c| 9 +
 drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 2 +-
 drivers/gpu/drm/vc4/vc4_hdmi.c | 1 +
 drivers/video/fbdev/core/fbmem.c   | 5 +
 drivers/video/fbdev/core/fbsysfs.c | 4 
 drivers/video/fbdev/efifb.c| 9 -
 drivers/video/fbdev/simplefb.c | 8 +++-
 drivers/video/fbdev/vesafb.c   | 8 +++-
 9 files changed, 38 insertions(+), 16 deletions(-)


signature.asc
Description: PGP signature

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Media freq factor and per-gt enhancements/fixes (rev6)

[Dixit, Ashutosh]

On Thu, 12 May 2022 23:58:55 -0700, Patchwork wrote:
>
> Patch Details
>
>  Series:  drm/i915: Media freq factor and per-gt enhancements/fixes (rev6)
>  URL:  https://patchwork.freedesktop.org/series/102665/
>  State:  failure
>  Details:  
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102665v6/index.html
>
> CI Bug Log - changes from CI_DRM_11646_full -> Patchwork_102665v6_full
>
> FAILURE
>
> Possible regressions
>
> * {igt@i915_pm_freq_mult@media-freq@gt0} (NEW):
>
>  * shard-iclb: NOTRUN -> SKIP

This skip is expected, this new IGT will skip on unsupported platforms.

>
> * igt@prime_self_import@export-vs-gem_close-race:
>
>  * shard-tglb: PASS -> FAIL

This failure is unrelated. It is seen here too:

https://patchwork.freedesktop.org/series/99867/

Thanks.
--
Ashutosh