== Series Details ==
Series: drm/i915/pvc: Add Wa_16015675438:pvc
URL : https://patchwork.freedesktop.org/series/104689/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11723_full -> Patchwork_104689v1_full
Summary
---
== Series Details ==
Series: drm/i915/pvc: GuC depriv applies to PVC
URL : https://patchwork.freedesktop.org/series/104688/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11723_full -> Patchwork_104688v1_full
Summary
== Series Details ==
Series: drm/i915/pvc: Add register steering
URL : https://patchwork.freedesktop.org/series/104691/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11724 -> Patchwork_104691v1
Summary
---
> On Thu, 02 Jun 2022, Animesh Manna wrote:
> > From: Arun R Murthy
> >
> > With the enablement of dual eDP, there will have to exist two entries
> > of backlight sysfs file. In order to avoid sysfs file name
> > duplication, the file names are prepended with the connector name.
>
> Fixed by
== Series Details ==
Series: drm/i915/pvc: Add register steering
URL : https://patchwork.freedesktop.org/series/104691/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Thu, 02 Jun 2022 16:55:50 -0700, Matt Roper wrote:
>
> On Thu, Jun 02, 2022 at 04:36:02PM -0700, Dixit, Ashutosh wrote:
> > On Fri, 27 May 2022 16:41:28 -0700, Matt Roper wrote:
> > >
> > > On Thu, May 26, 2022 at 12:00:42PM -0700, Ashutosh Dixit wrote:
> > > > Create a gt/gtN/.defaults
== Series Details ==
Series: drm/i915: Parse more eDP link rate stuff from VBT (rev3)
URL : https://patchwork.freedesktop.org/series/104615/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11721_full -> Patchwork_104615v3_full
On Fri, Jun 03, 2022 at 12:53:08AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/display/adlp: More updates to voltage swing table
> URL : https://patchwork.freedesktop.org/series/104661/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11719_full
== Series Details ==
Series: drm/i915/pvc: Add Wa_16015675438:pvc
URL : https://patchwork.freedesktop.org/series/104689/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11723 -> Patchwork_104689v1
Summary
---
== Series Details ==
Series: drm/i915/pvc: GuC depriv applies to PVC
URL : https://patchwork.freedesktop.org/series/104688/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11723 -> Patchwork_104688v1
Summary
---
From: John Harrison
Update to the latest master version of the DRM UAPI header file.
NB: Had to remove '__user' keywords as they do not appear to be
supported outside of kernel builds.
Signed-off-by: John Harrison
---
include/drm-uapi/i915_drm.h | 410
1
From: Rodrigo Vivi
Newer platforms have an embedded table giving details about that
platform's hardware configuration. This table can be retrieved from
the KMD via the existing query API. So add a test for it as both an
example of how to fetch the table and to validate the contents as much
as is
From: John Harrison
Various UMDs require hardware configuration information about the
current platform. A new interface has been added to the KMD to return
this information. So, add a test for the new interface.
Also, update to the latest DRM UAPI header file that contains the new
query enums.
Ponte Vecchio no longer has MSLICE or LNCF steering, but the bspec does
document several new types of multicast register ranges. Fortunately,
most of the different MCR types all provide valid values at instance
(0,0) so there's no need to read fuse registers and calculate a valid
instance. We'll
== Series Details ==
Series: drm/i915/display/adlp: More updates to voltage swing table
URL : https://patchwork.freedesktop.org/series/104661/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11719_full -> Patchwork_104661v1_full
== Series Details ==
Series: drm/i915/pvc: Add Wa_16015675438:pvc
URL : https://patchwork.freedesktop.org/series/104689/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Thu, Jun 02, 2022 at 04:36:02PM -0700, Dixit, Ashutosh wrote:
> On Fri, 27 May 2022 16:41:28 -0700, Matt Roper wrote:
> >
> > On Thu, May 26, 2022 at 12:00:42PM -0700, Ashutosh Dixit wrote:
> > > Create a gt/gtN/.defaults directory (similar to
> > > engine//.defaults) to expose default
From: Badal Nilawar
Even though PVC doesn't have an RCS engine, this workaround updates a
register in the 0x2xxx range that traditionally belongs to the RCS. We
need to set a special flag to tell the GuC that the presence of an "RCS"
register on a CCS save/restore list is okay/expected.
Cc:
On Fri, 27 May 2022 16:41:28 -0700, Matt Roper wrote:
>
> On Thu, May 26, 2022 at 12:00:42PM -0700, Ashutosh Dixit wrote:
> > Create a gt/gtN/.defaults directory (similar to
> > engine//.defaults) to expose default parameter values for each
> > gt in sysfs. This allows userspace to restore default
We missed this setting in the initial device info patch's definition of
XE_HPC_FEATURES.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index
== Series Details ==
Series: drm/i915/guc: Check ctx while waiting for response
URL : https://patchwork.freedesktop.org/series/104672/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11721_full -> Patchwork_104672v1_full
On Thu, Jun 02, 2022 at 12:45:42PM +0300, Jani Nikula wrote:
> Split out audio registers to a header of its own to reduce the size of
> i915_reg.h.
>
> TODO: Remove direct audio register access from intel_ddi.c. However,
> unification of audio get config is cumbersome due to the audio enable
>
Hello! This is just a reminder that the CFP for XDC in 2022 is still open!
The 2022 X.Org Developers Conference is being held in conjunction with
the 2022 Wine Developers Conference. This is a meeting to bring
together developers working on all things open graphics (Linux kernel,
Mesa, DRM,
On Thu, Jun 02, 2022 at 01:17:30PM -0700, José Roberto de Souza wrote:
> This workaround brings some regressions to DG2 and if really necessary
> for DG2 an alternative workaround will be implemented.
>
> BSpec: 54077
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt Roper
> ---
>
Failure is associated to the GEN9 generic bug and re-reported.
https://gitlab.freedesktop.org/drm/intel/-/issues/6075
[GEN9 only] Few tests - No logs
Thanks,
Lakshmi.
-Original Message-
From: Roper, Matthew D
Sent: Thursday, June 2, 2022 10:16 AM
To: intel-gfx@lists.freedesktop.org
Cc:
== Series Details ==
Series: drm/i915: Parse more eDP link rate stuff from VBT (rev3)
URL : https://patchwork.freedesktop.org/series/104615/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11721 -> Patchwork_104615v3
Summary
== Series Details ==
Series: drm/i915/display/fbc: Do not apply WA 22014263786 to DG2
URL : https://patchwork.freedesktop.org/series/104678/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11721 -> Patchwork_104678v1
Summary
== Series Details ==
Series: drm/i915/display/adlp: More updates to voltage swing table
URL : https://patchwork.freedesktop.org/series/104661/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11719 -> Patchwork_104661v1
From: Ville Syrjälä
The eDP BDB block has gained yet another max link rate field.
Let's parse it and consult it during the source rate filtering.
v2: *20 instead of *2 to get the correct units (Jani)
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
We're not parsing the 5.4 Gbps value for the old eDP fast link
training link rate, nor are we parsing the new fast link training
link rate field. Remedy both.
Also we'll now use the actual link rate instead of the DPCD BW
register value.
Note that we're not even using this
On Wed, Jun 01, 2022 at 07:13:16PM -0700, Zeng, Oak wrote:
Regards,
Oak
-Original Message-
From: dri-devel On Behalf Of
Niranjana Vishwanathapura
Sent: May 17, 2022 2:32 PM
To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; Vetter,
Daniel
Cc: Brost, Matthew ;
On Thu, Jun 2, 2022 at 3:11 PM Niranjana Vishwanathapura <
niranjana.vishwanathap...@intel.com> wrote:
> On Wed, Jun 01, 2022 at 01:28:36PM -0700, Matthew Brost wrote:
> >On Wed, Jun 01, 2022 at 05:25:49PM +0300, Lionel Landwerlin wrote:
> >> On 17/05/2022 21:32, Niranjana Vishwanathapura wrote:
On Thu, Jun 02, 2022 at 09:22:46AM -0700, Matthew Brost wrote:
On Thu, Jun 02, 2022 at 08:42:13AM +0300, Lionel Landwerlin wrote:
On 02/06/2022 00:18, Matthew Brost wrote:
> On Wed, Jun 01, 2022 at 05:25:49PM +0300, Lionel Landwerlin wrote:
> > On 17/05/2022 21:32, Niranjana Vishwanathapura
This workaround brings some regressions to DG2 and if really necessary
for DG2 an alternative workaround will be implemented.
BSpec: 54077
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
On Thu, Jun 2, 2022 at 7:42 AM Lionel Landwerlin
wrote:
>
> On 02/06/2022 00:18, Matthew Brost wrote:
> > On Wed, Jun 01, 2022 at 05:25:49PM +0300, Lionel Landwerlin wrote:
> >> On 17/05/2022 21:32, Niranjana Vishwanathapura wrote:
> >>> +VM_BIND/UNBIND ioctl will immediately start
On Wed, Jun 01, 2022 at 01:28:36PM -0700, Matthew Brost wrote:
On Wed, Jun 01, 2022 at 05:25:49PM +0300, Lionel Landwerlin wrote:
On 17/05/2022 21:32, Niranjana Vishwanathapura wrote:
> +VM_BIND/UNBIND ioctl will immediately start binding/unbinding the mapping in
an
> +async worker. The
== Series Details ==
Series: Dual LFP/EDP enablement
URL : https://patchwork.freedesktop.org/series/104663/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11720_full -> Patchwork_104663v1_full
Summary
---
**FAILURE**
== Series Details ==
Series: drm/i915/guc: Check ctx while waiting for response
URL : https://patchwork.freedesktop.org/series/104672/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11721 -> Patchwork_104672v1
Summary
On Thu, Jun 02, 2022 at 12:38:48PM +0300, Jani Nikula wrote:
> On Wed, 01 Jun 2022, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > We're not parsing the 5.4 Gbps value for the old eDP fast link
> > training link rate, nor are we parsing the new fast link training
> > link rate field.
== Series Details ==
Series: drm/i915/guc: Check ctx while waiting for response
URL : https://patchwork.freedesktop.org/series/104672/
State : warning
== Summary ==
Error: dim checkpatch failed
b5d975cdaf5a drm/i915/guc: Check ctx while waiting for response
-:6: WARNING:COMMIT_LOG_LONG_LINE:
We are seeing error message of "No response for request". Some cases happened
while waiting for response and reset/suspend action was triggered. In this
case, no response is not an error, active requests will be cancelled.
This patch will handle this condition and change the error message into
On Thu, Jun 02, 2022 at 04:31:23PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/display/adlp: More updates to voltage swing table
> URL : https://patchwork.freedesktop.org/series/104661/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11719 ->
On Tue, May 24, 2022 at 01:39:28PM +0300, Jani Nikula wrote:
> Add default action when .get_modes() not set. This also defines what a
> .get_modes() hook should do.
>
> Cc: David Airlie
> Cc: Daniel Vetter
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/drm_probe_helper.c | 14
On Tue, May 24, 2022 at 01:39:26PM +0300, Jani Nikula wrote:
> Add a new function drm_edid_connector_update() to replace the
> combination of calls drm_connector_update_edid_property() and
> drm_add_edid_modes(). Usually they are called in the drivers in this
> order, however the former needs
On Thu, 02 Jun 2022, Ville Syrjälä wrote:
> On Tue, May 24, 2022 at 01:39:23PM +0300, Jani Nikula wrote:
>> Add drm_edid based block count and data access helper functions that
>> take the EDID allocated size into account.
>>
>> At the moment, the allocated size should always match the EDID size
On Tue, May 24, 2022 at 01:39:23PM +0300, Jani Nikula wrote:
> Add drm_edid based block count and data access helper functions that
> take the EDID allocated size into account.
>
> At the moment, the allocated size should always match the EDID size
> indicated by the extension count, but this
== Series Details ==
Series: Dual LFP/EDP enablement
URL : https://patchwork.freedesktop.org/series/104663/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11720 -> Patchwork_104663v1
Summary
---
**SUCCESS**
No
== Series Details ==
Series: drm/i915/display/adlp: More updates to voltage swing table
URL : https://patchwork.freedesktop.org/series/104661/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11719 -> Patchwork_104661v1
On Thu, Jun 02, 2022 at 08:42:13AM +0300, Lionel Landwerlin wrote:
> On 02/06/2022 00:18, Matthew Brost wrote:
> > On Wed, Jun 01, 2022 at 05:25:49PM +0300, Lionel Landwerlin wrote:
> > > On 17/05/2022 21:32, Niranjana Vishwanathapura wrote:
> > > > +VM_BIND/UNBIND ioctl will immediately start
On Thu, Jun 02, 2022 at 01:28:40AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Add extra registers to GPU error dump
> URL : https://patchwork.freedesktop.org/series/104630/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11717_full ->
On Thu, Jun 02, 2022 at 07:27:19PM +0530, Balasubramani Vivekanandan wrote:
> Voltage swing table updated for eDP HBR3
>
> Bspec: 49291
Pending CI results
Reviewed-by: Matt Atwood
> Signed-off-by: Balasubramani Vivekanandan
>
> ---
> drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 6
== Series Details ==
Series: Dual LFP/EDP enablement
URL : https://patchwork.freedesktop.org/series/104663/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Dual LFP/EDP enablement
URL : https://patchwork.freedesktop.org/series/104663/
State : warning
== Summary ==
Error: dim checkpatch failed
45c6598f2be3 drm/i915/bios: calculate drrs mode using panel index for dual LFP
0416548d3850 drm/i915/display: Use panel index
On Thu, 02 Jun 2022, Animesh Manna wrote:
> From: Nischal Varide
>
> Tigerlake and newer has two instances of PPS, to support up to two
> eDP panels.
>
> Signed-off-by: Nischal Varide
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_pps.c | 3 ++-
> 1 file changed, 2
On Thu, 02 Jun 2022, Animesh Manna wrote:
> From: Arun R Murthy
>
> With the enablement of dual eDP, there will have to exist two entries of
> backlight sysfs file. In order to avoid sysfs file name duplication, the
> file names are prepended with the connector name.
Fixed by 20f85ef89d94
On Thu, 02 Jun 2022, Animesh Manna wrote:
> There will be separate entry of backlight info for each
> LFP in VBT. Panel index is used for deriving backlight info
> of the respective panel.
Same here, unnecessary. panel_type *is* panel index.
BR,
Jani.
>
> Signed-off-by: Animesh Manna
> ---
>
On Thu, 02 Jun 2022, Animesh Manna wrote:
> There will be separate entry for eack LFP in VBT. Panel index is
> used for deriving panel timing info of the respective panel.
This is completely unnecessary once you handle panel_type properly as
explained in reply to the previous patch.
BR,
Jani.
On Thu, 02 Jun 2022, Jani Nikula wrote:
> On Thu, 02 Jun 2022, Animesh Manna wrote:
>> Dual LFP may have different panel and based on panel index
>> respective 2 bits store the drrs mode info for each panel. So panel
>> index is used for deriving drrs mode of the rspective panel.
>>
>>
On Thu, 02 Jun 2022, Animesh Manna wrote:
> Dual LFP may have different panel and based on panel index
> respective 2 bits store the drrs mode info for each panel. So panel
> index is used for deriving drrs mode of the rspective panel.
>
> Signed-off-by: Animesh Manna
> ---
>
On Wed, 2022-06-01 at 14:06 -0700, Matt Roper wrote:
> From: Stuart Summers
>
> Our internal teams have identified a few additional engine registers
> that are worth inspecting in error state dumps during development &
> debug. Let's capture and print them as part of our error dump.
>
> For
On Wed, Jun 01, 2022 at 08:52:08PM +, Patchwork wrote:
> == Series Details ==
>
> Series: i915: SSEU handling updates
> URL : https://patchwork.freedesktop.org/series/104611/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11717_full -> Patchwork_104611v1_full
>
From: Nischal Varide
Tigerlake and newer has two instances of PPS, to support up to two
eDP panels.
Signed-off-by: Nischal Varide
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_pps.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Arun R Murthy
With the enablement of dual eDP, there will have to exist two entries of
backlight sysfs file. In order to avoid sysfs file name duplication, the
file names are prepended with the connector name.
Signed-off-by: Arun R Murthy
---
There will be separate entry of backlight info for each
LFP in VBT. Panel index is used for deriving backlight info
of the respective panel.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_bios.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
There will be separate entry for eack LFP in VBT. Panel index is
used for deriving panel timing info of the respective panel.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_bios.c | 26 ---
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git
Dual LFP may have different panel and based on panel index
respective 2 bits store the drrs mode info for each panel. So panel
index is used for deriving drrs mode of the rspective panel.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/icl_dsi.c| 2 +-
This patch series read the separate entry for each
LFP from VBT and populate the structure, which will be used
for enablement of the respective panel.
Port sync implementation is not part of this patch series.
Will be taken up later as per requrement.
This patch series do the initial enablement
Voltage swing table updated for eDP HBR3
Bspec: 49291
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
== Series Details ==
Series: drm/i915/regs: split out intel audio register definitions
URL : https://patchwork.freedesktop.org/series/104645/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11719_full -> Patchwork_104645v1_full
On 01.06.2022 08:07, Matt Roper wrote:
> This series reworks i915's internal handling of slice/subslice/EU (SSEU)
>
> data to represent platforms like Xe_HP in a more natural manner and to
>
== Series Details ==
Series: drm/i915/regs: split out intel audio register definitions
URL : https://patchwork.freedesktop.org/series/104645/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11719 -> Patchwork_104645v1
== Series Details ==
Series: drm/i915/regs: split out intel audio register definitions
URL : https://patchwork.freedesktop.org/series/104645/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/regs: split out intel audio register definitions
URL : https://patchwork.freedesktop.org/series/104645/
State : warning
== Summary ==
Error: dim checkpatch failed
977753637a20 drm/i915/regs: split out intel audio register definitions
Traceback (most
Split out audio registers to a header of its own to reduce the size of
i915_reg.h.
TODO: Remove direct audio register access from intel_ddi.c. However,
unification of audio get config is cumbersome due to the audio enable
bit being in the DP or HDMI registers on older platforms.
Signed-off-by:
On Wed, 01 Jun 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The eDP BDB block has gained yet another max link rate field.
> Let's parse it and consult it during the source rate filtering.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 4
>
On Wed, 01 Jun 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We're not parsing the 5.4 Gbps value for the old eDP fast link
> training link rate, nor are we parsing the new fast link training
> link rate field. Remedy both.
>
> Note that we're not even using this information for anything
On Wed, 01 Jun 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We'll need to know the VBT panel_type before we can determine the
> maximum link rate for eDP. To that end move
> intel_dp_set_source_rates() & co. to be called after the per-panel
> VBT parsing has been done.
>
> I'm not
77 matches
Mail list logo
