[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix workarounds on Gen2-3
== Series Details ==
Series: drm/i915: Fix workarounds on Gen2-3
URL : https://patchwork.freedesktop.org/series/111067/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12398_full -> Patchwork_111067v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (9 -> 11)
--
Additional (2): shard-rkl shard-dg1
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_111067v1_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_backlight@bad-brightness:
- {shard-rkl}:NOTRUN -> [SKIP][1] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111067v1/shard-rkl-5/igt@i915_pm_backli...@bad-brightness.html
* {igt@i915_pm_backlight@fade-with-suspend}:
- {shard-dg1}:NOTRUN -> [SKIP][2] +2 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111067v1/shard-dg1-15/igt@i915_pm_backli...@fade-with-suspend.html
Known issues
Here are the changes found in Patchwork_111067v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [PASS][3] -> [FAIL][4] ([i915#6268])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-tglb8/igt@gem_ctx_e...@basic-nohangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111067v1/shard-tglb7/igt@gem_ctx_e...@basic-nohangcheck.html
* igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#4793])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-skl4/igt@gem_ctx_isolation@preservation...@vecs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111067v1/shard-skl4/igt@gem_ctx_isolation@preservation...@vecs0.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [PASS][7] -> [SKIP][8] ([i915#4525])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-iclb1/igt@gem_exec_balan...@parallel-balancer.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111067v1/shard-iclb3/igt@gem_exec_balan...@parallel-balancer.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-tglb6/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111067v1/shard-tglb5/igt@gem_exec_fair@basic-none-sh...@rcs0.html
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk1/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111067v1/shard-glk9/igt@gem_exec_fair@basic-none-sh...@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][13] -> [FAIL][14] ([i915#2842])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-apl6/igt@gem_exec_fair@basic-none-s...@rcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111067v1/shard-apl2/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_suspend@basic-s4-devices@smem:
- shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271]) +2 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111067v1/shard-skl1/igt@gem_exec_suspend@basic-s4-devi...@smem.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][16] -> [SKIP][17] ([i915#2190])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-tglb2/igt@gem_huc_c...@huc-copy.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111067v1/shard-tglb6/igt@gem_huc_c...@huc-copy.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-skl: [PASS][18] -> [INCOMPLETE][19] ([i915#7231])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-skl9/igt@gem_workarou...@suspend-resume-fd.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111067v1/shard-skl4/igt@gem_workarou...@suspend-resume-fd.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][20] -> [FAIL][21] ([i915#3989] / [i915#454])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-iclb1/igt@i915_pm...@dc6-psr.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111067v1/shard-iclb3/igt@i915_pm...@dc6-psr.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [PASS][22] -> [SKIP][23] ([i915#4281])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-iclb8/igt@i915_pm...@dc9-dpms.html
[23]:
Re: [Intel-gfx] [PATCH v3] drm/i915/mtl: Enable Idle Messaging for GSC CS
On 19-11-2022 00:07, Vivi, Rodrigo wrote:
On Sat, 2022-11-19 at 00:03 +0530, Badal Nilawar wrote:
From: Vinay Belgaumkar
By defaut idle messaging is disabled for GSC CS so to unblock RC6
entry on media tile idle messaging need to be enabled.
v2:
- Fix review comments (Vinay)
- Set GSC idle hysteresis as per spec (Badal)
v3:
- Fix review comments (Rodrigo)
Bspec: 71496
Cc: Daniele Ceraolo Spurio
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Badal Nilawar
Reviewed-by: Vinay Belgaumkar
He is the author of the patch, no?!
or you can remove this or change the author to be you and keep his
reviewed-by...
or I can just remove his rv-b while merging.. just let me know..
As he is original author I will prefer not to change it. You can remove
his rv-b while merging.
Regards,
Badal
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 18 ++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index b0a4a2dbe3ee..e971b153fda9 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -15,6 +15,22 @@
#include "intel_rc6.h"
#include "intel_ring.h"
#include "shmem_utils.h"
+#include "intel_gt_regs.h"
+
+static void intel_gsc_idle_msg_enable(struct intel_engine_cs
*engine)
+{
+ struct drm_i915_private *i915 = engine->i915;
+
+ if (IS_METEORLAKE(i915) && engine->id == GSC0) {
+ intel_uncore_write(engine->gt->uncore,
+ RC_PSMI_CTRL_GSCCS,
+
_MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));
+ /* hysteresis 0xA=5us as recommended in spec*/
+ intel_uncore_write(engine->gt->uncore,
+ PWRCTX_MAXCNT_GSCCS,
+ 0xA);
+ }
+}
static void dbg_poison_ce(struct intel_context *ce)
{
@@ -275,6 +291,8 @@ void intel_engine_init__pm(struct intel_engine_cs
*engine)
intel_wakeref_init(>wakeref, rpm, _ops);
intel_engine_init_heartbeat(engine);
+
+ intel_gsc_idle_msg_enable(engine);
}
/**
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index c3cd92691795..80a979e6f6be 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -917,6 +917,10 @@
#define MSG_IDLE_FW_MASK REG_GENMASK(13, 9)
#define MSG_IDLE_FW_SHIFT 9
+#defineRC_PSMI_CTRL_GSCCS _MMIO(0x11a050)
+#define IDLE_MSG_DISABLE REG_BIT(0)
+#definePWRCTX_MAXCNT_GSCCS _MMIO(0x11a054)
+
#define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
#define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dvo: DVO init fixes/cleanps
== Series Details ==
Series: drm/i915/dvo: DVO init fixes/cleanps
URL : https://patchwork.freedesktop.org/series/111066/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12398_full -> Patchwork_111066v1_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_111066v1_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_111066v1_full, please notify your bug team to allow
them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 11)
--
Additional (2): shard-rkl shard-dg1
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_111066v1_full:
### IGT changes ###
Warnings
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-tglb: [FAIL][1] ([i915#2411] / [i915#4767]) ->
[INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-tglb1/igt@kms_fbcon_...@fbc-suspend.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/shard-tglb5/igt@kms_fbcon_...@fbc-suspend.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_eio@suspend:
- {shard-dg1}:NOTRUN -> [INCOMPLETE][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/shard-dg1-13/igt@gem_...@suspend.html
* {igt@i915_pm_backlight@fade-with-suspend}:
- {shard-rkl}:NOTRUN -> [SKIP][4] +1 similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/shard-rkl-4/igt@i915_pm_backli...@fade-with-suspend.html
- {shard-dg1}:NOTRUN -> [SKIP][5] +2 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/shard-dg1-17/igt@i915_pm_backli...@fade-with-suspend.html
Known issues
Here are the changes found in Patchwork_111066v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [PASS][6] -> [FAIL][7] ([i915#6268])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-tglb8/igt@gem_ctx_e...@basic-nohangcheck.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/shard-tglb1/igt@gem_ctx_e...@basic-nohangcheck.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-iclb1/igt@gem_exec_balan...@parallel-balancer.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/shard-iclb5/igt@gem_exec_balan...@parallel-balancer.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-tglb6/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/shard-tglb3/igt@gem_exec_fair@basic-none-sh...@rcs0.html
- shard-glk: [PASS][12] -> [FAIL][13] ([i915#2842])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk1/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/shard-glk3/igt@gem_exec_fair@basic-none-sh...@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][14] -> [SKIP][15] ([i915#2190])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-tglb2/igt@gem_huc_c...@huc-copy.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/shard-tglb7/igt@gem_huc_c...@huc-copy.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][16] -> [DMESG-WARN][17] ([i915#5566] /
[i915#716])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-apl3/igt@gen9_exec_pa...@allowed-single.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/shard-apl6/igt@gen9_exec_pa...@allowed-single.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-skl: [PASS][18] -> [DMESG-FAIL][19] ([i915#5334])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-skl10/igt@i915_selftest@live@gt_heartbeat.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/shard-skl10/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_suspend@basic-s2idle-without-i915:
- shard-snb: [PASS][20] -> [SKIP][21] ([fdo#109271])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-snb5/igt@i915_susp...@basic-s2idle-without-i915.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/shard-snb5/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@i915_suspend@sysfs-reader:
- shard-apl:
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix timeout handling when retiring requests (rev2)
== Series Details ==
Series: drm/i915: Fix timeout handling when retiring requests (rev2)
URL : https://patchwork.freedesktop.org/series/110964/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12398_full -> Patchwork_110964v2_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_110964v2_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_110964v2_full, please notify your bug team to allow
them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 11)
--
Additional (2): shard-rkl shard-dg1
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_110964v2_full:
### IGT changes ###
Possible regressions
*
igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-tglb7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscal...@pipe-a-valid-mode.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/shard-tglb6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscal...@pipe-a-valid-mode.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@i915_pm_backlight@fade-with-suspend}:
- {shard-rkl}:NOTRUN -> [SKIP][3] +2 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/shard-rkl-5/igt@i915_pm_backli...@fade-with-suspend.html
- {shard-dg1}:NOTRUN -> [SKIP][4] +2 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/shard-dg1-18/igt@i915_pm_backli...@fade-with-suspend.html
Known issues
Here are the changes found in Patchwork_110964v2_full that come from known
issues:
### CI changes ###
Issues hit
* boot:
- shard-glk: ([PASS][5], [PASS][6], [PASS][7], [PASS][8],
[PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14],
[PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20],
[PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26],
[PASS][27], [PASS][28], [PASS][29]) -> ([PASS][30], [PASS][31], [PASS][32],
[PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38],
[PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44],
[PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50],
[FAIL][51], [PASS][52], [PASS][53], [PASS][54]) ([i915#4392])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk5/boot.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk5/boot.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk5/boot.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk6/boot.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk6/boot.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk6/boot.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk7/boot.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk7/boot.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk7/boot.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk8/boot.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk8/boot.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk8/boot.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk9/boot.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk9/boot.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk9/boot.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk1/boot.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk1/boot.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk1/boot.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk1/boot.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk2/boot.html
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk2/boot.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk2/boot.html
[27]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk3/boot.html
[28]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk3/boot.html
[29]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/shard-glk3/boot.html
[30]:
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/display: Add missing checks for cdclk crawling (rev2)
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Add missing checks for
cdclk crawling (rev2)
URL : https://patchwork.freedesktop.org/series/111045/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12403 -> Patchwork_111045v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v2/index.html
Participating hosts (43 -> 41)
--
Additional (2): fi-hsw-4770 fi-tgl-dsi
Missing(4): fi-ctg-p8600 fi-ilk-m540 fi-rkl-11600 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_111045v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([i915#7073])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12403/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v2/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html
* igt@gem_softpin@allocator-basic-reserve:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271]) +11 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v2/fi-hsw-4770/igt@gem_soft...@allocator-basic-reserve.html
* igt@i915_selftest@live@execlists:
- fi-bdw-gvtdvm: [PASS][4] -> [INCOMPLETE][5] ([i915#2940])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12403/fi-bdw-gvtdvm/igt@i915_selftest@l...@execlists.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v2/fi-bdw-gvtdvm/igt@i915_selftest@l...@execlists.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v2/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
- bat-adlp-4: NOTRUN -> [SKIP][7] ([fdo#111827])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v2/bat-adlp-4/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v2/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-adlp-4: NOTRUN -> [SKIP][9] ([i915#3546])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v2/bat-adlp-4/igt@kms_pipe_crc_ba...@suspend-read-crc.html
- fi-kbl-7567u: NOTRUN -> [SKIP][10] ([fdo#109271])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v2/fi-kbl-7567u/igt@kms_pipe_crc_ba...@suspend-read-crc.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#1072]) +3
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v2/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
* igt@runner@aborted:
- fi-bdw-gvtdvm: NOTRUN -> [FAIL][12] ([i915#4312])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v2/fi-bdw-gvtdvm/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rpls-2}: [DMESG-WARN][13] ([i915#6434]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12403/bat-rpls-2/igt@gem_exec_suspend@basic...@smem.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v2/bat-rpls-2/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@hangcheck:
- {fi-ehl-2}: [INCOMPLETE][15] ([i915#5153] / [i915#6106] /
[i915#7351]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12403/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v2/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@migrate:
- bat-adlp-4: [INCOMPLETE][17] ([i915#7308] / [i915#7348]) ->
[PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12403/bat-adlp-4/igt@i915_selftest@l...@migrate.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v2/bat-adlp-4/igt@i915_selftest@l...@migrate.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-kbl-7567u: [INCOMPLETE][19] ([i915#4817]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12403/fi-kbl-7567u/igt@i915_susp...@basic-s3-without-i915.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v2/fi-kbl-7567u/igt@i915_susp...@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]:
[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/3] drm/i915/display: Add missing checks for cdclk crawling (rev2)
== Series Details == Series: series starting with [1/3] drm/i915/display: Add missing checks for cdclk crawling (rev2) URL : https://patchwork.freedesktop.org/series/111045/ State : warning == Summary == Error: make htmldocs had i915 warnings ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/display: Add missing checks for cdclk crawling (rev2)
== Series Details == Series: series starting with [1/3] drm/i915/display: Add missing checks for cdclk crawling (rev2) URL : https://patchwork.freedesktop.org/series/111045/ State : warning == Summary == Error: dim checkpatch failed 2934471a6919 drm/i915/display: Add missing checks for cdclk crawling f7ff44e0745c drm/i915/display: Do both crawl and squash when changing cdclk -:62: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #62: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1736: + const struct intel_cdclk_config *old_cdclk_config, -:63: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #63: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1737: + const struct intel_cdclk_config *new_cdclk_config, -:174: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 26) #174: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1854: + if (DISPLAY_VER(dev_priv) >= 14) + /* NOOP */; -:206: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 19) #206: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1885: + if (DISPLAY_VER(dev_priv) >= 14) [...] +*/; total: 0 errors, 4 warnings, 0 checks, 220 lines checked eb9eda5c9027 drm/i915/display: Add CDCLK Support for MTL
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Add missing CDCLK Squash support for MTL
== Series Details ==
Series: drm/i915/display: Add missing CDCLK Squash support for MTL
URL : https://patchwork.freedesktop.org/series/111087/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12403 -> Patchwork_111087v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111087v1/index.html
Participating hosts (43 -> 40)
--
Additional (1): fi-hsw-4770
Missing(4): fi-ctg-p8600 fi-ilk-m540 fi-rkl-11600 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_111087v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[PASS][1] -> [FAIL][2] ([i915#7229])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12403/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111087v1/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
* igt@gem_softpin@allocator-basic-reserve:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271]) +11 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111087v1/fi-hsw-4770/igt@gem_soft...@allocator-basic-reserve.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111087v1/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111087v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- fi-kbl-7567u: NOTRUN -> [SKIP][6] ([fdo#109271])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111087v1/fi-kbl-7567u/igt@kms_pipe_crc_ba...@suspend-read-crc.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1072]) +3
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111087v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
Possible fixes
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rplp-1}: [DMESG-WARN][8] ([i915#2867]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12403/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111087v1/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
- {bat-rpls-2}: [DMESG-WARN][10] ([i915#6434]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12403/bat-rpls-2/igt@gem_exec_suspend@basic...@smem.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111087v1/bat-rpls-2/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@hangcheck:
- {fi-ehl-2}: [INCOMPLETE][12] ([i915#5153] / [i915#6106] /
[i915#7351]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12403/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111087v1/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@migrate:
- {bat-adlp-6}: [INCOMPLETE][14] ([i915#7348]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12403/bat-adlp-6/igt@i915_selftest@l...@migrate.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111087v1/bat-adlp-6/igt@i915_selftest@l...@migrate.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-kbl-7567u: [INCOMPLETE][16] ([i915#4817]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12403/fi-kbl-7567u/igt@i915_susp...@basic-s3-without-i915.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111087v1/fi-kbl-7567u/igt@i915_susp...@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153
[i915#6106]: https://gitlab.freedesktop.org/drm/intel/issues/6106
[i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
[i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
[i915#7328]: https://gitlab.freedesktop.org/drm/intel/issues/7328
[i915#7346]:
Re: [Intel-gfx] [PATCH v3] drm/i915/hdmi: SPD infoframe update for discrete
On Thu, Oct 27, 2022 at 03:13:15PM -0700, Taylor, Clinton A wrote:
> Replace internal with discrete of dgfx platforms.
I think you meant 'integrated' rather than 'internal' here?
Is there any value in trying to give a rough family name in the product
description for discrete platforms? E.g.,
IS_DG2 -> "Arc GPU"
IS_DG1 -> "Iris Xe Discrete GPU"
IS_DGFX -> "Discrete GPU" (general fallback)
other -> "Integrated gfx"
Not sure if it's really worth the effort to keep updating this as new
product families come out or not. Either way,
Reviewed-by: Matt Roper
>
> v2: commit title reword (Jani)
> v3: use variable name i915 (Jani)
> Cc: Jani Nikula
> Signed-off-by: Taylor, Clinton A
> ---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 02f8374ea51f..7c5133871897 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -766,6 +766,7 @@ intel_hdmi_compute_spd_infoframe(struct intel_encoder
> *encoder,
>struct intel_crtc_state *crtc_state,
>struct drm_connector_state *conn_state)
> {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> struct hdmi_spd_infoframe *frame = _state->infoframes.spd.spd;
> int ret;
>
> @@ -775,7 +776,10 @@ intel_hdmi_compute_spd_infoframe(struct intel_encoder
> *encoder,
> crtc_state->infoframes.enable |=
> intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
>
> - ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
> + if (IS_DGFX(i915))
> + ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx");
> + else
> + ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
> if (drm_WARN_ON(encoder->base.dev, ret))
> return false;
>
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH v7 00/20] drm/i915/vm_bind: Add VM_BIND functionality
On Sat, 2022-11-12 at 23:57 -0800, Niranjana Vishwanathapura wrote: > DRM_I915_GEM_VM_BIND/UNBIND ioctls allows UMD to bind/unbind GEM > buffer objects (BOs) or sections of a BOs at specified GPU virtual > addresses on a specified address space (VM). Multiple mappings can map > to the same physical pages of an object (aliasing). These mappings (also > referred to as persistent mappings) will be persistent across multiple > GPU submissions (execbuf calls) issued by the UMD, without user having > to provide a list of all required mappings during each submission (as > required by older execbuf mode). > > This patch series support VM_BIND version 1, as described by the param > I915_PARAM_VM_BIND_VERSION. > > Add new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only works in > vm_bind mode. The vm_bind mode only works with this new execbuf3 ioctl. > The new execbuf3 ioctl will not have any execlist support and all the > legacy support like relocations etc., are removed. > > NOTEs: > * It is based on below VM_BIND design+uapi rfc. > Documentation/gpu/rfc/i915_vm_bind.rst Just as a FYI to everyone, there is a Mesa Iris implementation that makes use of this series here: https://gitlab.freedesktop.org/pzanoni/mesa/-/commits/upstream-vmbind/ Some notes on it: - Tested on TGL and Alchemist (aka DG2). - The code still has a lot of TODOs and some FIXMEs. - It was somewhat tested with the common Linux benchmarks (Dota 2, Manhattan, Xonotic, etc.) and survived most of what I threw at it. The only problems I saw so far are: - Sometimes you get a random GPU hang with Dota 2, but it seems to go away if you use INTEL_DEBUG=nofc . I'm investigating it right now. - Very very rarely DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD returns EINVAL and we don't properly recover. I am still trying to understand this one, it's once in a blue moon that it happens. - Performance seems to be mostly equivalent to non-vm-bind, but I haven't spent a lot of time really gathering numbers since I'm mostly debugging things. Using VM_PRIVATE BOs is the key here, you cut Dota's performance by almost half if you don't use private BOs. Considering how ABYSMALLY slower things get, I would assume there's probably something the Kernel could do here to handle things a little faster. The 'perf' tool shows a lot of i915 fence-related functions wasting CPU time when we don't use private BOs. - I am not really sure whether the implicit tracking code actually works or not. It doesn't really seem to make much of a difference if I remove it entirely, but I'm still planning to spend more time analyzing this. If anybody knows of a workload that will absolutely fail if we get this wrong, please tell me. - There's the whole frontbuffer tracking discussion from v6 that's still pending resolution. - The Vulkan implementation will come later. I wanted to sort all the GL details later so I don't make the same mistakes twice. - I really dislike how we have to handle the lack of implicit tracking support. The code is excessive and racy. See export_bo_sync_state(), import_bo_sync_state() and their caller from src/gallium/drivers/iris/iris_batch.c. Suggestions for Mesa improvements are welcome, but I would really really really prefer to have a way to just tell execbuffer3 to handle implicit tracking for these buffers for me in an atomic way. - I kinda wish execbuffer3 still accepted a pointer to struct drm_i915_gem_exec_fence in addition to struct drm_i915_gem_timeline_fence, since we already have to keep a list of exec_fences for execbuf2, and then in the execbuf3 we convert them to the new format. We could also do the opposite and leave execbuf2 with the slower path. But I could live without this, no problem. - Credits to Ken, Jason, Lionel, Niranjana, Nanley, Daniel and everybody else who helped me sort things out here. Is this ready to be merged to the Kernel? Maybe, but I'd like us to sort these things out first: 1. Get conclusion regarding the frontbuffer tracking issue first. 2. Get some validation from more experienced people (*winks at Jason*) that our approach with implicit tracking is correct here. Or convince Niranjana to add a way to pass buffers for implicit tracking so the Kernel can atomically inside execbuf3 what we're trying to do with 8 ioctls. 3. Fix all the Mesa bugs so we're 100% sure they're not design flaws of the Kernel. But that's just my humble opinion. Thanks, Paulo > > * The IGT RFC series is posted as, > [PATCH i-g-t v7 0/13] vm_bind: Add VM_BIND validation support > > v2: Address various review comments > v3: Address review comments and other fixes > v4: Remove vm_unbind out fence uapi which is not supported yet, > replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode() > v5: Render kernel-doc, use PIN_NOEVICT, limit vm_bind support to > non-recoverable faults > v6: Rebased, minor fixes, add reserved fields to drm_i915_gem_vm_bind, > add new patch for async vm_unbind support > v7: Rebased, minor
Re: [Intel-gfx] [PATCH v3] drm/i915/mtl: Media GT and Render GT share common GGTT
On Tue, Nov 15, 2022 at 08:34:54PM +0530, Aravind Iddamsetty wrote:
> On XE_LPM+ platforms the media engines are carved out into a separate
> GT but have a common GGTMMADR address range which essentially makes
> the GGTT address space to be shared between media and render GT. As a
> result any updates in GGTT shall invalidate TLB of GTs sharing it and
> similarly any operation on GGTT requiring an action on a GT will have to
> involve all GTs sharing it. setup_private_pat was being done on a per
> GGTT based as that doesn't touch any GGTT structures moved it to per GT
> based.
>
> BSPEC: 63834
>
> v2:
> 1. Add details to commit msg
> 2. includes fix for failure to add item to ggtt->gt_list, as suggested
> by Lucas
> 3. as ggtt_flush() is used only for ggtt drop i915_is_ggtt check within
> it.
> 4. setup_private_pat moved out of intel_gt_tiles_init
>
> v3:
> 1. Move out for_each_gt from i915_driver.c (Jani Nikula)
>
> Cc: Matt Roper
> Signed-off-by: Aravind Iddamsetty
> ---
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 54 +--
> drivers/gpu/drm/i915/gt/intel_gt.c| 13 +-
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
> drivers/gpu/drm/i915/gt/intel_gtt.h | 4 ++
> drivers/gpu/drm/i915/i915_driver.c| 12 ++---
> drivers/gpu/drm/i915/i915_gem.c | 2 +
> drivers/gpu/drm/i915/i915_gem_evict.c | 51 +++--
> drivers/gpu/drm/i915/i915_vma.c | 5 ++-
> drivers/gpu/drm/i915/selftests/i915_gem.c | 2 +
> 9 files changed, 111 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index 8145851ad23d..7644738b9cdb 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -8,6 +8,7 @@
> #include
> #include
>
> +#include
> #include
> #include
>
> @@ -196,10 +197,13 @@ void i915_ggtt_suspend_vm(struct i915_address_space *vm)
>
> void i915_ggtt_suspend(struct i915_ggtt *ggtt)
> {
> + struct intel_gt *gt;
> +
> i915_ggtt_suspend_vm(>vm);
> ggtt->invalidate(ggtt);
>
> - intel_gt_check_and_clear_faults(ggtt->vm.gt);
> + list_for_each_entry(gt, >gt_list, ggtt_link)
> + intel_gt_check_and_clear_faults(gt);
> }
>
> void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
> @@ -225,16 +229,21 @@ static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
>
> static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
> {
> - struct intel_uncore *uncore = ggtt->vm.gt->uncore;
> struct drm_i915_private *i915 = ggtt->vm.i915;
>
> gen8_ggtt_invalidate(ggtt);
>
> - if (GRAPHICS_VER(i915) >= 12)
> - intel_uncore_write_fw(uncore, GEN12_GUC_TLB_INV_CR,
> - GEN12_GUC_TLB_INV_CR_INVALIDATE);
> - else
> - intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> + if (GRAPHICS_VER(i915) >= 12) {
> + struct intel_gt *gt;
> +
> + list_for_each_entry(gt, >gt_list, ggtt_link)
> + intel_uncore_write_fw(gt->uncore,
> + GEN12_GUC_TLB_INV_CR,
> + GEN12_GUC_TLB_INV_CR_INVALIDATE);
> + } else {
> + intel_uncore_write_fw(ggtt->vm.gt->uncore,
> + GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> + }
> }
>
> u64 gen8_ggtt_pte_encode(dma_addr_t addr,
> @@ -986,8 +995,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
>
> ggtt->vm.pte_encode = gen8_ggtt_pte_encode;
>
> - setup_private_pat(ggtt->vm.gt);
> -
> return ggtt_probe_common(ggtt, size);
> }
>
> @@ -1196,7 +1203,14 @@ static int ggtt_probe_hw(struct i915_ggtt *ggtt,
> struct intel_gt *gt)
> */
> int i915_ggtt_probe_hw(struct drm_i915_private *i915)
> {
> - int ret;
> + struct intel_gt *gt;
> + int ret, i;
> +
> + for_each_gt(gt, i915, i) {
> + ret = intel_gt_assign_ggtt(gt);
> + if (ret)
> + return ret;
> + }
>
> ret = ggtt_probe_hw(to_gt(i915)->ggtt, to_gt(i915));
> if (ret)
> @@ -1208,6 +1222,19 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
> return 0;
> }
>
> +struct i915_ggtt *i915_ggtt_create(struct drm_i915_private *i915)
> +{
> + struct i915_ggtt *ggtt;
> +
> + ggtt = drmm_kzalloc(>drm, sizeof(*ggtt), GFP_KERNEL);
> + if (!ggtt)
> + return ERR_PTR(-ENOMEM);
> +
> + INIT_LIST_HEAD(>gt_list);
> +
> + return ggtt;
> +}
> +
> int i915_ggtt_enable_hw(struct drm_i915_private *i915)
> {
> if (GRAPHICS_VER(i915) < 6)
> @@ -1296,9 +1323,11 @@ bool i915_ggtt_resume_vm(struct i915_address_space *vm)
>
> void i915_ggtt_resume(struct i915_ggtt *ggtt)
> {
> + struct intel_gt *gt;
> bool flush;
>
> - intel_gt_check_and_clear_faults(ggtt->vm.gt);
> + list_for_each_entry(gt, >gt_list,
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Remove non-existent pipes from bigjoiner pipe mask
== Series Details == Series: drm/i915: Remove non-existent pipes from bigjoiner pipe mask URL : https://patchwork.freedesktop.org/series/111086/ State : success == Summary == CI Bug Log - changes from CI_DRM_12402 -> Patchwork_111086v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111086v1/index.html Participating hosts (43 -> 29) -- Additional (1): fi-kbl-soraka Missing(15): bat-dg1-7 fi-ilk-m540 fi-bdw-samus bat-dg2-8 bat-adlm-1 bat-dg2-9 bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-hsw-4770 bat-adln-1 bat-rplp-1 bat-rpls-2 bat-dg2-11 bat-jsl-1 Known issues Here are the changes found in Patchwork_111086v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_gttfill@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +9 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111086v1/fi-kbl-soraka/igt@gem_exec_gttf...@basic.html * igt@gem_exec_suspend@basic-s3@smem: - fi-skl-6600u: [PASS][2] -> [FAIL][3] ([fdo#103375]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12402/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111086v1/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111086v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-apl-guc: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111086v1/fi-apl-guc/igt@gem_lmem_swapp...@basic.html - fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111086v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@i915_selftest@live@execlists: - fi-bsw-nick:[PASS][7] -> [INCOMPLETE][8] ([i915#7120]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12402/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111086v1/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gem_contexts: - fi-kbl-soraka: NOTRUN -> [INCOMPLETE][9] ([i915#7099]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111086v1/fi-kbl-soraka/igt@i915_selftest@live@gem_contexts.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][10] ([i915#5334]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111086v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html - fi-apl-guc: NOTRUN -> [DMESG-FAIL][11] ([i915#5334]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111086v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][12] ([i915#1886]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111086v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@mman: - fi-rkl-guc: [PASS][13] -> [TIMEOUT][14] ([i915#6794]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12402/fi-rkl-guc/igt@i915_selftest@l...@mman.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111086v1/fi-rkl-guc/igt@i915_selftest@l...@mman.html * igt@i915_suspend@basic-s3-without-i915: - fi-rkl-11600: [PASS][15] -> [INCOMPLETE][16] ([i915#4817]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12402/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111086v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-apl-guc: NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111086v1/fi-apl-guc/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-soraka: NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +7 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111086v1/fi-kbl-soraka/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size: - fi-bsw-kefka: [PASS][19] -> [FAIL][20] ([i915#6298]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12402/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html [20]:
Re: [Intel-gfx] [PATCH] drm/i915/gt: Manage uncore->lock while waiting on MCR register
On Fri, Nov 18, 2022 at 01:20:45PM -0800, Lucas De Marchi wrote:
> On Thu, Nov 17, 2022 at 09:33:58AM -0800, Matt Roper wrote:
> > The GT MCR code currently relies on uncore->lock to avoid race
> > conditions on the steering control register during MCR operations. The
> > *_fw() versions of MCR operations expect the caller to already hold
> > uncore->lock, while the non-fw variants manage the lock internally.
> > However the sole callsite of intel_gt_mcr_wait_for_reg_fw() does not
> > currently obtain the forcewake lock, allowing a potential race condition
> > (and triggering an assertion on lockdep builds). Furthermore, since
> > 'wait for register value' requests may not return immediately, it is
> > undesirable to hold a fundamental lock like uncore->lock for the entire
> > wait and block all other MMIO for the duration; rather the lock is only
> > needed around the MCR read operations and can be released during the
> > delays.
> >
> > Convert intel_gt_mcr_wait_for_reg_fw() to a non-fw variant that will
> > manage uncore->lock internally. This does have the side effect of
> > causing an unnecessary lookup in the forcewake table on each read
> > operation, but since the caller is still holding the relevant forcewake
> > domain, this will ultimately just incremenent the reference count and
> > won't actually cause any additional MMIO traffic.
> >
> > In the future we plan to switch to a dedicated MCR lock to protect the
> > steering critical section rather than using the overloaded and
> > high-traffic uncore->lock; on MTL and beyond the new lock can be
> > implemented on top of the hardware-provided synchonization mechanism for
> > steering.
> >
> > Fixes: 3068bec83eea ("drm/i915/gt: Add intel_gt_mcr_wait_for_reg_fw()")
> > Cc: Lucas De Marchi
> > Signed-off-by: Matt Roper
>
>
> Reviewed-by: Lucas De Marchi
Applied to drm-intel-gt-next. Thanks for the review.
Matt
>
> thanks
> Lucas De Marchi
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH v3] drm/i915/mtl: Enable Idle Messaging for GSC CS
On Fri, 18 Nov 2022 10:37:37 -0800, Vivi, Rodrigo wrote: > > On Sat, 2022-11-19 at 00:03 +0530, Badal Nilawar wrote: > > From: Vinay Belgaumkar > > > > By defaut idle messaging is disabled for GSC CS so to unblock RC6 > > entry on media tile idle messaging need to be enabled. > > > > v2: > > - Fix review comments (Vinay) > > - Set GSC idle hysteresis as per spec (Badal) > > v3: > > - Fix review comments (Rodrigo) > > > > Bspec: 71496 > > > > Cc: Daniele Ceraolo Spurio > > Signed-off-by: Vinay Belgaumkar > > Signed-off-by: Badal Nilawar > > Reviewed-by: Vinay Belgaumkar > > He is the author of the patch, no?! > or you can remove this or change the author to be you and keep his > reviewed-by... > > or I can just remove his rv-b while merging.. just let me know.. Not sure if that is the case here, but when multiple people contribute to a patch, the original author can review changes by others and add his Reviewed-by, no? Or are we saying it is redundant for the author to add his R-b? Similarly, are S-o-b and R-b by the same person ok? I add changes to someone's patch so add my S-o-b but also review other's changes so add my R-b? Sometimes finding a 3rd person to add a R-b is hard. But two poeple can contribute to a patch and review each other's changes so add both their S-o-b's and R-b's or no? :) Ashutosh
[Intel-gfx] [PULL] drm-intel-next
Hi Dave and Daniel, Here goes the final pull request from drm-intel-next targeting 6.2. Manly more display clean-ups and the removal of the force_probe protection on DG2. drm-intel-next-2022-11-18: GVT Changes: - gvt-next stuff mostly with refactor for the new MDEV interface. i915 Changes: - PSR fixes and improvements (Jouni) - DP DSC fixes (Vinod, Jouni) - More general display cleanups (Jani) - More display collor management cleanup targetting degamma (Ville) - remove circ_buf.h includes (Jiri) - wait power off delay at driver remove to optimize probe (Jani) - More audio cleanup targeting the ELD precompute readout (Ville) - Enable DC power states on all eDP ports (Imre) - RPL-P stepping info (Matt Atwood) - MTL enabling patches (RK) - Removal of DG2 force_probe (Matt) Thanks, Rodrigo. The following changes since commit c02f20d38fb90eba606277874581db124ace42c4: drm/nouveau/disp: fix incorrect/broken hdmi methods (2022-11-14 16:17:22 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-2022-11-18 for you to fetch changes up to d2eae8e98d5979aa4a767e1cbf53ab9f6a83a38e: drm/i915/dg2: Drop force_probe requirement (2022-11-18 15:38:33 -0500) GVT Changes: - gvt-next stuff mostly with refactor for the new MDEV interface. i915 Changes: - PSR fixes and improvements (Jouni) - DP DSC fixes (Vinod, Jouni) - More general display cleanups (Jani) - More display collor management cleanup targetting degamma (Ville) - remove circ_buf.h includes (Jiri) - wait power off delay at driver remove to optimize probe (Jani) - More audio cleanup targeting the ELD precompute readout (Ville) - Enable DC power states on all eDP ports (Imre) - RPL-P stepping info (Matt Atwood) - MTL enabling patches (RK) - Removal of DG2 force_probe (Matt) Colin Ian King (1): drm/i915/reg: Fix spelling mistake "Unsupport" -> "Unsupported" Imre Deak (9): drm/i915: Fix warn in intel_display_power_*_domain() functions drm/i915: Preallocate the debug power domain wakerefs array drm/i915: Move the POWER_DOMAIN_AUX_IO_A definition to its logical place drm/i915: Use the AUX_IO power domain only for eDP/PSR port drm/i915/tgl+: Enable display DC power states on all eDP ports drm/i915: Add missing AUX_IO_A power domain->well mappings drm/i915: Add missing DC_OFF power domain->well mappings drm/i915: Factor out function to get/put AUX_IO power for main link drm/i915/mtl+: Don't enable the AUX_IO power for non-eDP port main links Jani Nikula (21): drm/i915/gmbus: move GPIO enum to gmbus drm/i915: reduce includes in intel_connector.h drm/i915: reduce includes in intel_fifo_underrun.h drm/i915: un-inline icl_hdr_plane_mask() to simplify includes drm/i915/dpio: un-inline the vlv phy/channel mapping functions drm/i915/dpio: move dpio_channel and dpio_phy enums to intel_dpio_phy.h drm/i915: reduce includes in intel_display_power.h drm/i915/display: reduce the includes in intel_dvo_dev.h drm/i915/display: reduce includes in intel_hdmi.h drm/i915/display: reduce includes in g4x_dp.h includes drm/i915/irq: make gen2_irq_init()/gen2_irq_reset() static drm/i915/display: move struct intel_link_m_n to intel_display_types.h drm/i915/reg: move masked field helpers to i915_reg_defs.h drm/i915/reg: move pick even and pick to reg defs drm/i915: split out intel_display_reg_defs.h drm/i915: stop including i915_irq.h from i915_trace.h drm/i915/edp: wait power off delay at driver remove to optimize probe drm/i915/hti: abstract hti handling drm/i915/display: move hti under display sub-struct drm/i915/display: move global_obj_list under display sub-struct drm/i915/display: move restore state and ctx under display sub-struct Jiapeng Chong (4): drm/i915/gvt: Fix kernel-doc drm/i915/gvt: Fix kernel-doc drm/i915/gvt: Fix kernel-doc drm/i915/gvt: Remove the unused function get_pt_type() Jiri Slaby (SUSE) (1): drm/i915: remove circ_buf.h includes Jouni Högander (4): drm/i915/psr: Send update also on invalidate drm/i915/mtl: Fix PSR2_MAN_TRK_CTL bit getter functions for MTL drm/i915/psr: Ensure panel granularity aligns with DSC slice height drm/i915/psr: Remove inappropriate DSC slice alignment warning Julia Lawall (1): drm/i915/gvt: fix typo in comment Matt Atwood (1): drm/i915/rpl-p: Add stepping info Matt Roper (1): drm/i915/dg2: Drop force_probe requirement Mauro Carvalho Chehab (1): drm/i915: gvt: fix kernel-doc trivial warnings Paulo Miguel Almeida (1): i915/gvt: remove hardcoded value on crc32_start calculation Radhakrishna Sripada (2): drm/i915/mtl: Fix dram info readout drm/i915/mtl: Skip
Re: [Intel-gfx] [PATCH] drm/i915/gt: Manage uncore->lock while waiting on MCR register
On Thu, Nov 17, 2022 at 09:33:58AM -0800, Matt Roper wrote:
The GT MCR code currently relies on uncore->lock to avoid race
conditions on the steering control register during MCR operations. The
*_fw() versions of MCR operations expect the caller to already hold
uncore->lock, while the non-fw variants manage the lock internally.
However the sole callsite of intel_gt_mcr_wait_for_reg_fw() does not
currently obtain the forcewake lock, allowing a potential race condition
(and triggering an assertion on lockdep builds). Furthermore, since
'wait for register value' requests may not return immediately, it is
undesirable to hold a fundamental lock like uncore->lock for the entire
wait and block all other MMIO for the duration; rather the lock is only
needed around the MCR read operations and can be released during the
delays.
Convert intel_gt_mcr_wait_for_reg_fw() to a non-fw variant that will
manage uncore->lock internally. This does have the side effect of
causing an unnecessary lookup in the forcewake table on each read
operation, but since the caller is still holding the relevant forcewake
domain, this will ultimately just incremenent the reference count and
won't actually cause any additional MMIO traffic.
In the future we plan to switch to a dedicated MCR lock to protect the
steering critical section rather than using the overloaded and
high-traffic uncore->lock; on MTL and beyond the new lock can be
implemented on top of the hardware-provided synchonization mechanism for
steering.
Fixes: 3068bec83eea ("drm/i915/gt: Add intel_gt_mcr_wait_for_reg_fw()")
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Reviewed-by: Lucas De Marchi
thanks
Lucas De Marchi
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Enable Idle Messaging for GSC CS (rev2)
== Series Details == Series: drm/i915/mtl: Enable Idle Messaging for GSC CS (rev2) URL : https://patchwork.freedesktop.org/series/111011/ State : success == Summary == CI Bug Log - changes from CI_DRM_12401 -> Patchwork_111011v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v2/index.html Participating hosts (41 -> 41) -- Additional (4): fi-rkl-11600 fi-tgl-dsi fi-snb-2520m fi-pnv-d510 Missing(4): fi-ctg-p8600 fi-hsw-4770 fi-ilk-m540 fi-bdw-samus Known issues Here are the changes found in Patchwork_111011v2 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - fi-rkl-11600: NOTRUN -> [SKIP][1] ([i915#7456]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v2/fi-rkl-11600/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-rkl-11600: NOTRUN -> [SKIP][2] ([i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v2/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-rkl-11600: NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v2/fi-rkl-11600/igt@gem_lmem_swapp...@basic.html * igt@gem_tiled_pread_basic: - fi-rkl-11600: NOTRUN -> [SKIP][4] ([i915#3282]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v2/fi-rkl-11600/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - fi-rkl-11600: NOTRUN -> [SKIP][5] ([i915#7561]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v2/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@gt_heartbeat: - fi-bxt-dsi: [PASS][6] -> [DMESG-FAIL][7] ([i915#5334]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12401/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v2/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@mman: - fi-rkl-guc: [PASS][8] -> [TIMEOUT][9] ([i915#6794]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12401/fi-rkl-guc/igt@i915_selftest@l...@mman.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v2/fi-rkl-guc/igt@i915_selftest@l...@mman.html * igt@i915_suspend@basic-s3-without-i915: - fi-rkl-11600: NOTRUN -> [INCOMPLETE][10] ([i915#4817]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v2/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_chamelium@hdmi-crc-fast: - fi-snb-2520m: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v2/fi-snb-2520m/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_chamelium@hdmi-edid-read: - fi-rkl-11600: NOTRUN -> [SKIP][12] ([fdo#111827]) +7 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v2/fi-rkl-11600/igt@kms_chamel...@hdmi-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor: - fi-rkl-11600: NOTRUN -> [SKIP][13] ([i915#4103]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v2/fi-rkl-11600/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html * igt@kms_force_connector_basic@force-load-detect: - fi-rkl-11600: NOTRUN -> [SKIP][14] ([fdo#109285] / [i915#4098]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v2/fi-rkl-11600/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_psr@primary_page_flip: - fi-pnv-d510:NOTRUN -> [SKIP][15] ([fdo#109271]) +44 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v2/fi-pnv-d510/igt@kms_psr@primary_page_flip.html - fi-rkl-11600: NOTRUN -> [SKIP][16] ([i915#1072]) +3 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v2/fi-rkl-11600/igt@kms_psr@primary_page_flip.html * igt@kms_setmode@basic-clone-single-crtc: - fi-rkl-11600: NOTRUN -> [SKIP][17] ([i915#3555] / [i915#4098]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v2/fi-rkl-11600/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-flip: - fi-snb-2520m: NOTRUN -> [SKIP][18] ([fdo#109271]) +23 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v2/fi-snb-2520m/igt@prime_v...@basic-fence-flip.html * igt@prime_vgem@basic-read: - fi-rkl-11600: NOTRUN -> [SKIP][19] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111011v2/fi-rkl-11600/igt@prime_v...@basic-read.html * igt@prime_vgem@basic-userptr:
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Manage uncore->lock while waiting on MCR register
On Fri, Nov 18, 2022 at 09:19:45AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/gt: Manage uncore->lock while waiting on MCR register > URL : https://patchwork.freedesktop.org/series/111033/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_12396_full -> Patchwork_111033v1_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_111033v1_full absolutely need > to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_111033v1_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > Participating hosts (11 -> 11) > -- > > No changes in participating hosts > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_111033v1_full: > > ### IGT changes ### > > Possible regressions > > * igt@i915_selftest@live@gtt: > - shard-skl: NOTRUN -> [INCOMPLETE][1] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-skl4/igt@i915_selftest@l...@gtt.html Unexpected incomplete with no errors in the log. Possibly https://gitlab.freedesktop.org/drm/intel/-/issues/7319 from KBL? Matt > > > Known issues > > > Here are the changes found in Patchwork_111033v1_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_create@create-ext-cpu-access-sanity-check: > - shard-iclb: NOTRUN -> [SKIP][2] ([i915#6335]) >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-iclb6/igt@gem_cre...@create-ext-cpu-access-sanity-check.html > > * igt@gem_exec_balancer@parallel: > - shard-iclb: [PASS][3] -> [SKIP][4] ([i915#4525]) +1 similar > issue >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-iclb2/igt@gem_exec_balan...@parallel.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-iclb5/igt@gem_exec_balan...@parallel.html > > * igt@gem_exec_fair@basic-none-solo@rcs0: > - shard-apl: [PASS][5] -> [FAIL][6] ([i915#2842]) >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-apl6/igt@gem_exec_fair@basic-none-s...@rcs0.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html > > * igt@gem_lmem_swapping@heavy-verify-random: > - shard-apl: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +1 > similar issue >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-apl6/igt@gem_lmem_swapp...@heavy-verify-random.html > > * igt@gem_lmem_swapping@parallel-random-verify: > - shard-skl: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +2 > similar issues >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-skl1/igt@gem_lmem_swapp...@parallel-random-verify.html > > * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled: > - shard-skl: NOTRUN -> [SKIP][9] ([fdo#109271]) +203 similar > issues >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-skl1/igt@gem_render_c...@yf-tiled-mc-ccs-to-vebox-yf-tiled.html > > * igt@gem_tiled_wb: > - shard-skl: NOTRUN -> [TIMEOUT][10] ([i915#6990]) >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-skl4/igt@gem_tiled_wb.html > > * igt@gen9_exec_parse@allowed-single: > - shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#5566] / > [i915#716]) >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk1/igt@gen9_exec_pa...@allowed-single.html >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-glk5/igt@gen9_exec_pa...@allowed-single.html > > * igt@gen9_exec_parse@unaligned-jump: > - shard-iclb: NOTRUN -> [SKIP][13] ([i915#2856]) >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-iclb6/igt@gen9_exec_pa...@unaligned-jump.html > > * igt@i915_pipe_stress@stress-xrgb-ytiled: > - shard-skl: NOTRUN -> [FAIL][14] ([i915#7036]) +1 similar issue >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-skl9/igt@i915_pipe_str...@stress-xrgb-ytiled.html > > * igt@i915_pm_dc@dc6-dpms: > - shard-iclb: [PASS][15] -> [FAIL][16] ([i915#3989] / [i915#454]) >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-iclb2/igt@i915_pm...@dc6-dpms.html >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-iclb3/igt@i915_pm...@dc6-dpms.html > > * igt@i915_pm_dc@dc9-dpms: > - shard-iclb: [PASS][17] -> [INCOMPLETE][18]
Re: [Intel-gfx] [PATCH] drm/i915/dg2: Drop force_probe requirement
On Tue, Nov 08, 2022 at 04:13:28PM -0800, Matt Roper wrote:
> DG2 has been very usable for a while now, and all of the uapi changes
> related to fundamental platform usage have been finalized. Recent CI
> results have also been healthy, so we're ready to drop the force_probe
> requirement and enable the platform by default.
>
> Cc: Rodrigo Vivi
> Cc: Tvrtko Ursulin
> Cc: Joonas Lahtinen
> Cc: Jani Nikula
> Signed-off-by: Matt Roper
Acked-by: Rodrigo Vivi
I'm going to merge this soon. Thanks to everyone involved.
> ---
>
> There was some recent offline discussion questioning whether we'd fully
> identified the root cause of some historic CI failures, or whether it
> was possible we might still have a bug lurking somewhere causing
> sporadic failures. Let's use this patch to centralize discussion about
> any remaining concerns and make sure they're addressed before we apply
> this.
>
> drivers/gpu/drm/i915/i915_pci.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 211913be40ce..0866300243aa 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1078,7 +1078,6 @@ static const struct intel_device_info dg2_info = {
> XE_LPD_FEATURES,
> .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> - .require_force_probe = 1,
> };
>
> static const struct intel_device_info ats_m_info = {
> --
> 2.38.1
>
Re: [Intel-gfx] [PATCH] drm/i915/dg2: Drop force_probe requirement
On 09/11/2022 00:13, Matt Roper wrote:
DG2 has been very usable for a while now, and all of the uapi changes
related to fundamental platform usage have been finalized. Recent CI
results have also been healthy, so we're ready to drop the force_probe
requirement and enable the platform by default.
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
Cc: Jani Nikula
Signed-off-by: Matt Roper
---
There was some recent offline discussion questioning whether we'd fully
identified the root cause of some historic CI failures, or whether it
was possible we might still have a bug lurking somewhere causing
sporadic failures. Let's use this patch to centralize discussion about
any remaining concerns and make sure they're addressed before we apply
this.
The two main issues were analysed and I am satisfied that they are
either very sporadic and with impact limited to i915/DG2, or sporadic
with impact limited to a small subset of DG2 functionality. Furthermore,
there are already fixes for both which seem most probably will be merged
inside the 6.2 fixes window. Therefore I agree that we can proceed with
dropping the force_probe protection. I also understand our upstream
maintainer has acked the plan to finish up in the fixes window.
Acked-by: Tvrtko Ursulin
Regards,
Tvrtko
drivers/gpu/drm/i915/i915_pci.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 211913be40ce..0866300243aa 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1078,7 +1078,6 @@ static const struct intel_device_info dg2_info = {
XE_LPD_FEATURES,
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
- .require_force_probe = 1,
};
static const struct intel_device_info ats_m_info = {
Re: [Intel-gfx] [PATCH] drm/i915: Fix workarounds on Gen2-3
On Fri, Nov 18, 2022 at 11:52:49AM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> In 3653727560d0 ("drm/i915: Simplify internal helper function signature")
> I broke the old platforms by not noticing engine workaround init does not
> initialize the list on old platforms. Fix it by always initializing which
> already does the right thing by mostly not doing anything if there aren't
> any workarounds on the list.
Was going to give this a quick smoke test on my 865 but I can't even
reproduce the original issue on it.
Turns out the 64bit compiler is too smart:
:
0: 8b 77 20mov0x20(%rdi),%esi
3: 85 f6 test %esi,%esi
5: 75 01 jne8
7: c3 ret
8: 41 57 push %r15
a: 41 56 push %r14
c: 41 55 push %r13
e: 41 54 push %r12
10: 55 push %rbp
11: 53 push %rbx
12: 48 83 ec 10 sub$0x10,%rsp
16: 48 89 fdmov%rdi,%rbp
19: 4c 8b 2fmov(%rdi),%r13
So it has moved the wal->count check to be the very first thing,
even before even doing any stack setup.
The 32bit compiler is somewhat less smart:
:
0: 55 push %ebp
1: 89 e5 mov%esp,%ebp
3: 57 push %edi
4: 56 push %esi
5: 53 push %ebx
6: 83 ec 10sub$0x10,%esp
9: 89 45 f0mov%eax,-0x10(%ebp)
c: 8b 58 10mov0x10(%eax),%ebx
f: 8b 38 mov(%eax),%edi
11: 85 db test %ebx,%ebx
13: 89 7d e8mov%edi,-0x18(%ebp)
16: 8b 7f 0cmov0xc(%edi),%edi
19: 75 0d jne28
Not only does it do all that potentially pointless stack
setup, but then it has decided to do a bunch of stuff
with wal->gt before the jne.
That presumably explains why CI is still green despite blb/pnv.
Hmm. Now a different 32bit build also failed to hit this:
0003 :
3: 55 push %ebp
4: 89 e5 mov%esp,%ebp
6: 57 push %edi
7: 56 push %esi
8: 53 push %ebx
9: 83 ec 14sub$0x14,%esp
c: 89 45 f0mov%eax,-0x10(%ebp)
f: 8b 58 10mov0x10(%eax),%ebx
12: 85 db test %ebx,%ebx
14: 75 08 jne1e
So this time it moved the wal->gt stuff to some later point.
Same compiler, different .config. Not sure which knob is
causing the difference here.
>
> Signed-off-by: Tvrtko Ursulin
> Fixes: 3653727560d0 ("drm/i915: Simplify internal helper function signature")
> Reported-by: Ville Syrjälä
> Cc: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 213160f29ec3..4d7a01b45e09 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2991,7 +2991,7 @@ general_render_compute_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_li
> static void
> engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list
> *wal)
> {
> - if (I915_SELFTEST_ONLY(GRAPHICS_VER(engine->i915) < 4))
> + if (GRAPHICS_VER(engine->i915) < 4)
> return;
>
> engine_fake_wa_init(engine, wal);
> @@ -3016,9 +3016,6 @@ void intel_engine_init_workarounds(struct
> intel_engine_cs *engine)
> {
> struct i915_wa_list *wal = >wa_list;
>
> - if (GRAPHICS_VER(engine->i915) < 4)
> - return;
> -
> wa_init_start(wal, engine->gt, "engine", engine->name);
> engine_init_workarounds(engine, wal);
> wa_init_finish(wal);
> --
> 2.34.1
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Never return 0 if not all requests retired
On 11/18/2022 11:42 AM, Janusz Krzysztofik wrote:
Users of intel_gt_retire_requests_timeout() expect 0 return value on
success. However, we have no protection from passing back 0 potentially
returned by a call to dma_fence_wait_timeout() when it succedes right
after its timeout has expired.
Replace 0 with -ETIME before potentially using the timeout value as return
code, so -ETIME is returned if there are still some requests not retired
after timeout, 0 otherwise.
v2: Move the added lines down so flush_submission() is not affected.
Fixes: f33a8a51602c ("drm/i915: Merge wait_for_timelines with retire_request")
Signed-off-by: Janusz Krzysztofik
Cc: sta...@vger.kernel.org # v5.5+
---
drivers/gpu/drm/i915/gt/intel_gt_requests.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
index edb881d756309..3ac4603eeb4ee 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
@@ -199,6 +199,9 @@ out_active: spin_lock(>lock);
if (remaining_timeout)
*remaining_timeout = timeout;
+ if (!timeout)
+ timeout = -ETIME;
This will return error, -ETIME when 0 timeout is passed,
intel_gt_retire_requests().
We don't want that. I think you can use a separate variable to store
return val from the dma_fence_wait_timeout()
Regards,
Nirmoy
+
return active_count ? timeout : 0;
}
Re: [Intel-gfx] [PATCH] drm/i915/display: Add missing CDCLK Squash support for MTL
On Fri, Nov 18, 2022 at 11:00:08AM -0800, Anusha Srivatsa wrote:
MTL supports both squash and crawl.
Cc: Clint Taylor
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index cf3b28d71d2b..d82f118809e9 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1118,6 +1118,7 @@ static const struct intel_device_info pvc_info = {
XE_LPD_FEATURES,\
.__runtime.display.ip.ver = 14, \
.display.has_cdclk_crawl = 1, \
+ .display.has_cdclk_squash = 1, \
warning about inconsistent cdclk is now gone,
Reviewed-by: Lucas De Marchi
thanks,
Lucas De Marchi
.__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
static const struct intel_gt_definition xelpmp_extra_gt[] = {
--
2.25.1
[Intel-gfx] ✓ Fi.CI.IGT: success for Add module oriented dmesg output
== Series Details ==
Series: Add module oriented dmesg output
URL : https://patchwork.freedesktop.org/series/111050/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12397_full -> Patchwork_111050v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (11 -> 11)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_111050v1_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_mmap_write_crc@main:
- {shard-dg1}:NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-dg1-17/igt@kms_mmap_write_...@main.html
Known issues
Here are the changes found in Patchwork_111050v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [PASS][2] -> [SKIP][3] ([i915#4525]) +1 similar issue
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-iclb2/igt@gem_exec_balan...@parallel-bb-first.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-iclb5/igt@gem_exec_balan...@parallel-bb-first.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][4] -> [FAIL][5] ([i915#2842])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-tglb8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-tglb3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-skl: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +1
similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-skl10/igt@gem_lmem_swapp...@parallel-random-verify-ccs.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#5566] /
[i915#716])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-glk1/igt@gen9_exec_pa...@allowed-single.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-glk7/igt@gen9_exec_pa...@allowed-single.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][9] -> [FAIL][10] ([i915#3989] / [i915#454])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-iclb5/igt@i915_pm...@dc6-dpms.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-iclb3/igt@i915_pm...@dc6-dpms.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- shard-skl: [PASS][11] -> [WARN][12] ([i915#1804])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-skl9/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-skl4/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][13] ([i915#3763])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-skl10/igt@kms_big...@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#3886])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-skl10/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs:
- shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271]) +61 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-skl10/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs.html
* igt@kms_chamelium@hdmi-crc-multiple:
- shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +2
similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-skl10/igt@kms_chamel...@hdmi-crc-multiple.html
* igt@kms_chamelium@hdmi-crc-single:
- shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-apl6/igt@kms_chamel...@hdmi-crc-single.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][18] -> [FAIL][19] ([i915#79])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12397/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@bc-hdmi-a1-hdmi-a2.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111050v1/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
-
[Intel-gfx] [PATCH] drm/i915/display: Add missing CDCLK Squash support for MTL
MTL supports both squash and crawl.
Cc: Clint Taylor
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index cf3b28d71d2b..d82f118809e9 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1118,6 +1118,7 @@ static const struct intel_device_info pvc_info = {
XE_LPD_FEATURES,\
.__runtime.display.ip.ver = 14, \
.display.has_cdclk_crawl = 1, \
+ .display.has_cdclk_squash = 1, \
.__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
static const struct intel_gt_definition xelpmp_extra_gt[] = {
--
2.25.1
[Intel-gfx] [PATCH] drm/i915: Remove non-existent pipes from bigjoiner pipe mask
From: Ville Syrjälä
bigjoiner_pipes() doesn't consider that:
- RKL only has three pipes
- some pipes may be fused off
This means that intel_atomic_check_bigjoiner() won't reject
all configurations that would need a non-existent pipe.
Instead we just keep on rolling witout actually having
reserved the slave pipe we need.
It's possible that we don't outright explode anywhere due to
this since eg. for_each_intel_crtc_in_pipe_mask() will only
walk the crtcs we've registered even though the passed in
pipe_mask asks for more of them. But clearly the thing won't
do what is expected of it when the required pipes are not
present.
Fix the problem by consulting the device info pipe_mask already
in bigjoiner_pipes().
Cc: sta...@vger.kernel.org
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index b3e23708d194..6c2686ecb62a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3733,12 +3733,16 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
static u8 bigjoiner_pipes(struct drm_i915_private *i915)
{
+ u8 pipes;
+
if (DISPLAY_VER(i915) >= 12)
- return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
+ pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
else if (DISPLAY_VER(i915) >= 11)
- return BIT(PIPE_B) | BIT(PIPE_C);
+ pipes = BIT(PIPE_B) | BIT(PIPE_C);
else
- return 0;
+ pipes = 0;
+
+ return pipes & RUNTIME_INFO(i915)->pipe_mask;
}
static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
--
2.37.4
Re: [Intel-gfx] [PATCH v3 20/20] drm/i915: Do state check for color management changes
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Monday, November 14, 2022 9:08 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 20/20] drm/i915: Do state check for color
> management changes
>
> From: Ville Syrjälä
>
> In order to validate LUT programming more thoroughly let's do a state check
> for all
> color management updates as well.
>
> Not sure we really want this outside CI. It is rather heavy and color
> management
> updates could become rather common with all the HDR/etc. stuff happening.
> Maybe
> we should have an extra knob for this that we could enable in CI?
Yeah for now it maybe not be that heavily used, but in future usage may
increase.
I think we can have it enable via debugfs when we really need for testing and
keep it
disabled as default.
For now, looks good.
Reviewed-by: Uma Shankar
> v2: Skip for initial_commit to avoid FDI dotclock
> sanity checks/etc. tripping up
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_modeset_verify.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> index 842d70f0dfd2..9e4767e1b900 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> @@ -228,6 +228,8 @@ void intel_modeset_verify_crtc(struct intel_crtc *crtc,
> struct intel_crtc_state *new_crtc_state) {
> if (!intel_crtc_needs_modeset(new_crtc_state) &&
> + (!intel_crtc_needs_color_update(new_crtc_state) ||
> + new_crtc_state->inherited) &&
> !intel_crtc_needs_fastset(new_crtc_state))
> return;
>
> --
> 2.37.4
Re: [Intel-gfx] [PATCH v3] drm/i915/mtl: Enable Idle Messaging for GSC CS
On Sat, 2022-11-19 at 00:03 +0530, Badal Nilawar wrote:
> From: Vinay Belgaumkar
>
> By defaut idle messaging is disabled for GSC CS so to unblock RC6
> entry on media tile idle messaging need to be enabled.
>
> v2:
> - Fix review comments (Vinay)
> - Set GSC idle hysteresis as per spec (Badal)
> v3:
> - Fix review comments (Rodrigo)
>
> Bspec: 71496
>
> Cc: Daniele Ceraolo Spurio
> Signed-off-by: Vinay Belgaumkar
> Signed-off-by: Badal Nilawar
> Reviewed-by: Vinay Belgaumkar
He is the author of the patch, no?!
or you can remove this or change the author to be you and keep his
reviewed-by...
or I can just remove his rv-b while merging.. just let me know..
> Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gt/intel_engine_pm.c | 18 ++
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4
> 2 files changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> index b0a4a2dbe3ee..e971b153fda9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> @@ -15,6 +15,22 @@
> #include "intel_rc6.h"
> #include "intel_ring.h"
> #include "shmem_utils.h"
> +#include "intel_gt_regs.h"
> +
> +static void intel_gsc_idle_msg_enable(struct intel_engine_cs
> *engine)
> +{
> + struct drm_i915_private *i915 = engine->i915;
> +
> + if (IS_METEORLAKE(i915) && engine->id == GSC0) {
> + intel_uncore_write(engine->gt->uncore,
> + RC_PSMI_CTRL_GSCCS,
> +
> _MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));
> + /* hysteresis 0xA=5us as recommended in spec*/
> + intel_uncore_write(engine->gt->uncore,
> + PWRCTX_MAXCNT_GSCCS,
> + 0xA);
> + }
> +}
>
> static void dbg_poison_ce(struct intel_context *ce)
> {
> @@ -275,6 +291,8 @@ void intel_engine_init__pm(struct intel_engine_cs
> *engine)
>
> intel_wakeref_init(>wakeref, rpm, _ops);
> intel_engine_init_heartbeat(engine);
> +
> + intel_gsc_idle_msg_enable(engine);
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index c3cd92691795..80a979e6f6be 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -917,6 +917,10 @@
> #define MSG_IDLE_FW_MASK REG_GENMASK(13, 9)
> #define MSG_IDLE_FW_SHIFT 9
>
> +#defineRC_PSMI_CTRL_GSCCS _MMIO(0x11a050)
> +#define IDLE_MSG_DISABLE REG_BIT(0)
> +#definePWRCTX_MAXCNT_GSCCS _MMIO(0x11a054)
> +
> #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
> #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
>
Re: [Intel-gfx] [PATCH v3 18/20] drm/i915: Use gamma LUT for RGB limited range compression
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Monday, November 14, 2022 9:08 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 18/20] drm/i915: Use gamma LUT for RGB limited
> range compression
>
> From: Ville Syrjälä
>
> On ilk+ and glk class hardware we current make a mess of things when we have
> to
> both generate limited range output and use the hw gamma LUT. Since we do the
> range compression using the pipe CSC unit (which is situated before the gamma
> LUT
> in the pipe) we are in fact applying the gamma to the limited range data
> instead of
> the full range data as the user intended.
>
> We can work around this by applying the range compression via the gamma LUT
> instead of using the pipe CSC for it.
> Fairly easy to do now that we have the internal post_csc_lut attachment point
> where
> we can stick our new cooked LUT.
>
> On ilk+ this only needs to be dome when using the split gamma mode or when the
Nit: Typo in "done"
Looks Good to me.
Reviewed-by: Uma Shankar
> ctm is enabled since otherwise we can simply reorder the LUT vs. CSC. On glk
> we
> need to do this any time a gamma LUT is used since no reordering is possible.
> We do lose a bit of coverage in intel_color_assert_luts(), but so be it.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 133 +
> 1 file changed, 111 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index c336524d9225..dee0382015a5 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -249,17 +249,44 @@ static void icl_update_output_csc(struct intel_crtc
> *crtc,
> intel_de_write_fw(i915, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]);
> }
>
> +static bool ilk_limited_range(const struct intel_crtc_state
> +*crtc_state) {
> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> +
> + /* icl+ have dedicated output CSC */
> + if (DISPLAY_VER(i915) >= 11)
> + return false;
> +
> + /* pre-hsw have PIPECONF_COLOR_RANGE_SELECT */
> + if (DISPLAY_VER(i915) < 7 || IS_IVYBRIDGE(i915))
> + return false;
> +
> + return crtc_state->limited_color_range; }
> +
> +static bool ilk_lut_limited_range(const struct intel_crtc_state
> +*crtc_state) {
> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> +
> + if (!ilk_limited_range(crtc_state))
> + return false;
> +
> + if (crtc_state->c8_planes)
> + return false;
> +
> + if (DISPLAY_VER(i915) == 10)
> + return crtc_state->hw.gamma_lut;
> + else
> + return crtc_state->hw.gamma_lut &&
> + (crtc_state->hw.degamma_lut || crtc_state->hw.ctm); }
> +
> static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> + if (!ilk_limited_range(crtc_state))
> + return false;
>
> - /*
> - * FIXME if there's a gamma LUT after the CSC, we should
> - * do the range compression using the gamma LUT instead.
> - */
> - return crtc_state->limited_color_range &&
> - (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
> - IS_DISPLAY_VER(i915, 9, 10));
> + return !ilk_lut_limited_range(crtc_state);
> }
>
> static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
> @@ -
> 603,9 +630,18 @@ create_linear_lut(struct drm_i915_private *i915, int
> lut_size)
> return blob;
> }
>
> +static u16 lut_limited_range(unsigned int value) {
> + unsigned int min = 16 << 8;
> + unsigned int max = 235 << 8;
> +
> + return value * (max - min) / 0x + min; }
> +
> static struct drm_property_blob *
> create_resized_lut(struct drm_i915_private *i915,
> -const struct drm_property_blob *blob_in, int lut_out_size)
> +const struct drm_property_blob *blob_in, int lut_out_size,
> +bool limited_color_range)
> {
> int i, lut_in_size = drm_color_lut_size(blob_in);
> struct drm_property_blob *blob_out;
> @@ -621,8 +657,18 @@ create_resized_lut(struct drm_i915_private *i915,
> lut_in = blob_in->data;
> lut_out = blob_out->data;
>
> - for (i = 0; i < lut_out_size; i++)
> - lut_out[i] = lut_in[i * (lut_in_size - 1) / (lut_out_size - 1)];
> + for (i = 0; i < lut_out_size; i++) {
> + const struct drm_color_lut *entry =
> + _in[i * (lut_in_size - 1) / (lut_out_size - 1)];
> +
> + if (limited_color_range) {
> + lut_out[i].red = lut_limited_range(entry->red);
> + lut_out[i].green = lut_limited_range(entry->green);
> + lut_out[i].blue =
[Intel-gfx] [PATCH v3] drm/i915/mtl: Enable Idle Messaging for GSC CS
From: Vinay Belgaumkar
By defaut idle messaging is disabled for GSC CS so to unblock RC6
entry on media tile idle messaging need to be enabled.
v2:
- Fix review comments (Vinay)
- Set GSC idle hysteresis as per spec (Badal)
v3:
- Fix review comments (Rodrigo)
Bspec: 71496
Cc: Daniele Ceraolo Spurio
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Badal Nilawar
Reviewed-by: Vinay Belgaumkar
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 18 ++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index b0a4a2dbe3ee..e971b153fda9 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -15,6 +15,22 @@
#include "intel_rc6.h"
#include "intel_ring.h"
#include "shmem_utils.h"
+#include "intel_gt_regs.h"
+
+static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine)
+{
+ struct drm_i915_private *i915 = engine->i915;
+
+ if (IS_METEORLAKE(i915) && engine->id == GSC0) {
+ intel_uncore_write(engine->gt->uncore,
+ RC_PSMI_CTRL_GSCCS,
+ _MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));
+ /* hysteresis 0xA=5us as recommended in spec*/
+ intel_uncore_write(engine->gt->uncore,
+ PWRCTX_MAXCNT_GSCCS,
+ 0xA);
+ }
+}
static void dbg_poison_ce(struct intel_context *ce)
{
@@ -275,6 +291,8 @@ void intel_engine_init__pm(struct intel_engine_cs *engine)
intel_wakeref_init(>wakeref, rpm, _ops);
intel_engine_init_heartbeat(engine);
+
+ intel_gsc_idle_msg_enable(engine);
}
/**
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index c3cd92691795..80a979e6f6be 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -917,6 +917,10 @@
#define MSG_IDLE_FW_MASK REG_GENMASK(13, 9)
#define MSG_IDLE_FW_SHIFT 9
+#defineRC_PSMI_CTRL_GSCCS _MMIO(0x11a050)
+#define IDLE_MSG_DISABLE REG_BIT(0)
+#definePWRCTX_MAXCNT_GSCCS _MMIO(0x11a054)
+
#define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
#define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
--
2.25.1
Re: [Intel-gfx] [PATCH v3 17/20] drm/i915: Use hw degamma LUT for sw gamma on glk with YCbCr output
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Monday, November 14, 2022 9:07 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 17/20] drm/i915: Use hw degamma LUT for sw
> gamma on glk with YCbCr output
>
> From: Ville Syrjälä
>
> On glk we can no longer reorder the hw LUTS vs. pipe CSC like we could on
> eaerlier
Typo in "earlier"
> platforms, and neither do we have a separate output CSC like on icl+. That
> means if
> we use the pipe CSC for YCbCr output we are currently applying the gamma LUT
> after the RGB->YCbCr conversion, which is just wrong.
> The further we go from a linear curve the more distorted the resulting colors
> become.
>
> To work around this terrible limitation the best we can do is repurpose the hw
> degamma LUT as a poor man's gamma LUT. Now that we have the internal
> pre_csc_lut attachment point that is not particularly hard to do.
>
> What makes this less than ideal however is the fact that the hw degamma LUT
> and
> gamma LUTs have very different capabilities.
> The gamma LUT can operatie in direct color type modes, whereas the degamma LUT
> can't and just always operaters in interpolated mode. Additionally the
> degamma LUT
Typo in "operate"
> is just a single 1D LUT, whereas the gamma LUT is made of three separate 1D
> LUts
> (one for each channel).
> So in order to make this semi-sensible we must also verify the user supplied
> LUT
> more less matches the hw degamma LUT capabilities.
> We still end up losing most of the LUT entries though, so the results might
> be a bit
> crap.
>
> The other option of flat out rejecting the YCbCr+gamma LUT combo seems
> extremely likely to just cause a black screen for the user.
> Eg. pretty sure Xorg always applies some kind of gamma LUT, and if the user
> then
> plugs in a display that needs YCbCr output we're toast.
With the typos fixed, this looks good to me.
Reviewed-by: Uma Shankar
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 61 +++---
> 1 file changed, 54 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 8bb8983b490c..c336524d9225 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1362,13 +1362,13 @@ static int check_lut_size(const struct
> drm_property_blob *lut, int expected)
> return 0;
> }
>
> -static int check_luts(const struct intel_crtc_state *crtc_state)
> +static int _check_luts(const struct intel_crtc_state *crtc_state,
> +u32 degamma_tests, u32 gamma_tests)
> {
> struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> const struct drm_property_blob *degamma_lut = crtc_state-
> >hw.degamma_lut;
> int gamma_length, degamma_length;
> - u32 gamma_tests, degamma_tests;
>
> /* C8 relies on its palette being stored in the legacy LUT */
> if (crtc_state->c8_planes && !lut_is_legacy(crtc_state->hw.gamma_lut)) {
> @@ -1379,8 +1379,6 @@ static int check_luts(const struct intel_crtc_state
> *crtc_state)
>
> degamma_length = intel_degamma_lut_size(crtc_state);
> gamma_length = intel_gamma_lut_size(crtc_state);
> - degamma_tests = intel_degamma_lut_tests(crtc_state);
> - gamma_tests = intel_gamma_lut_tests(crtc_state);
>
> if (check_lut_size(degamma_lut, degamma_length) ||
> check_lut_size(gamma_lut, gamma_length)) @@ -1393,6 +1391,13 @@
> static int check_luts(const struct intel_crtc_state *crtc_state)
> return 0;
> }
>
> +static int check_luts(const struct intel_crtc_state *crtc_state) {
> + return _check_luts(crtc_state,
> +intel_degamma_lut_tests(crtc_state),
> +intel_gamma_lut_tests(crtc_state));
> +}
> +
> static u32 i9xx_gamma_mode(struct intel_crtc_state *crtc_state) {
> if (!crtc_state->gamma_enable ||
> @@ -1414,9 +1419,11 @@ void intel_color_assert_luts(const struct
> intel_crtc_state
> *crtc_state)
> crtc_state->post_csc_lut !=
> crtc_state->hw.gamma_lut);
> } else if (DISPLAY_VER(i915) == 10) {
> drm_WARN_ON(>drm,
> + crtc_state->post_csc_lut == crtc_state->hw.gamma_lut
> &&
> crtc_state->pre_csc_lut !=
> crtc_state->hw.degamma_lut
> &&
> crtc_state->pre_csc_lut != i915-
> >display.color.glk_linear_degamma_lut);
> drm_WARN_ON(>drm,
> + crtc_state->post_csc_lut != NULL &&
> crtc_state->post_csc_lut !=
> crtc_state->hw.gamma_lut);
> } else if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT) {
> drm_WARN_ON(>drm,
> @@ -1728,10 +1735,33 @@ static u32
Re: [Intel-gfx] [PATCH v3 16/20] drm/i915: Rework legacy LUT handling
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Monday, November 14, 2022 9:07 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 16/20] drm/i915: Rework legacy LUT handling
>
> From: Ville Syrjälä
>
> Currently crtc_state_is_legacy_gamma() has a very specific set of conditions,
> not all
> of which are actually necessary. Also Also when we detect those conditions
Nit: "Also" duplicated.
Looks Good to me.
Reviewed-by: Uma Shankar
> check_luts() just skips all the checks. That will no longer work for glk soon
> when we'll
> start to use the hw degamma LUT in place of the hw gamma LUT for YCbCr output.
> So let's rework the logic to only really consider whether the user provided
> gamma_lut is one that matches the hw legacy LUT capabilities or not.
>
> We'll need to reject C8+degamma on ivb+ since the presence of degamma_lut
> would
> either mean we have to really use the LUT for degamma as opposed to C8
> palette,
> or we have to enable split gamma mode which also can't work as the C8 palette.
>
> Otherwise this will now cause the legacy LUT to go through the regular lut
> checks as
> well. As a side effect we also start to allow the use of the legacy LUT with
> CTM, but
> that is perfectly fine as far a the hardware is concerned.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 82 +++---
> 1 file changed, 55 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index e2bcfbffb298..8bb8983b490c 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -154,15 +154,7 @@ static const u16 ilk_csc_postoff_rgb_to_ycbcr[3] = {
>
> static bool lut_is_legacy(const struct drm_property_blob *lut) {
> - return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH;
> -}
> -
> -static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state
> *crtc_state) -{
> - return !crtc_state->hw.degamma_lut &&
> - !crtc_state->hw.ctm &&
> - crtc_state->hw.gamma_lut &&
> - lut_is_legacy(crtc_state->hw.gamma_lut);
> + return lut && drm_color_lut_size(lut) == LEGACY_LUT_LENGTH;
> }
>
> /*
> @@ -1317,6 +1309,42 @@ intel_color_add_affected_planes(struct intel_crtc_state
> *new_crtc_state)
> return 0;
> }
>
> +static u32 intel_gamma_lut_tests(const struct intel_crtc_state
> +*crtc_state) {
> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> + const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> +
> + if (lut_is_legacy(gamma_lut))
> + return 0;
> +
> + return INTEL_INFO(i915)->display.color.gamma_lut_tests;
> +}
> +
> +static u32 intel_degamma_lut_tests(const struct intel_crtc_state
> +*crtc_state) {
> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> +
> + return INTEL_INFO(i915)->display.color.degamma_lut_tests;
> +}
> +
> +static int intel_gamma_lut_size(const struct intel_crtc_state
> +*crtc_state) {
> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> + const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> +
> + if (lut_is_legacy(gamma_lut))
> + return LEGACY_LUT_LENGTH;
> +
> + return INTEL_INFO(i915)->display.color.gamma_lut_size;
> +}
> +
> +static u32 intel_degamma_lut_size(const struct intel_crtc_state
> +*crtc_state) {
> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> +
> + return INTEL_INFO(i915)->display.color.degamma_lut_size;
> +}
> +
> static int check_lut_size(const struct drm_property_blob *lut, int expected)
> {
> int len;
> @@ -1342,21 +1370,17 @@ static int check_luts(const struct intel_crtc_state
> *crtc_state)
> int gamma_length, degamma_length;
> u32 gamma_tests, degamma_tests;
>
> - /* Always allow legacy gamma LUT with no further checking. */
> - if (crtc_state_is_legacy_gamma(crtc_state))
> - return 0;
> -
> /* C8 relies on its palette being stored in the legacy LUT */
> - if (crtc_state->c8_planes) {
> + if (crtc_state->c8_planes && !lut_is_legacy(crtc_state->hw.gamma_lut))
> +{
> drm_dbg_kms(>drm,
> "C8 pixelformat requires the legacy LUT\n");
> return -EINVAL;
> }
>
> - degamma_length = INTEL_INFO(i915)->display.color.degamma_lut_size;
> - gamma_length = INTEL_INFO(i915)->display.color.gamma_lut_size;
> - degamma_tests = INTEL_INFO(i915)->display.color.degamma_lut_tests;
> - gamma_tests = INTEL_INFO(i915)->display.color.gamma_lut_tests;
> + degamma_length = intel_degamma_lut_size(crtc_state);
> + gamma_length = intel_gamma_lut_size(crtc_state);
> + degamma_tests = intel_degamma_lut_tests(crtc_state);
> + gamma_tests =
Re: [Intel-gfx] [PATCH v3 15/20] drm/i915: Finish the LUT state checker
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Monday, November 14, 2022 9:07 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 15/20] drm/i915: Finish the LUT state checker
>
> From: Ville Syrjälä
>
> We have full readout now for all platforms (sans the icl+ multi-segment
> readout hw
> fail), so hook up the LUT state checker for everyone.
>
> We add a new vfunc for this since different platforms need to handle the
> details a bit
> differently.
>
> The implementation is rather repetitive in places. Probably we want to think
> of a
> more declarative approach for the LUT precision/etc. stuff in the future...
Yeah some places do look as if can be optimized as you already mentioned.
But no major concerns on this one.
Looks Good to me.
Reviewed-by: Uma Shankar
> Note that we're currently missing readout for c8_planes, so we'll have to
> skip the
> state check in that case.
>
> v2: Fix readout for C8 use cases
> v3: Skip C8 entirely due to lack of c8_planes readout
> Add ilk_has_pre_csc_lut() helper and use other such helpers
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 275 ++-
> drivers/gpu/drm/i915/display/intel_color.h | 8 +-
> drivers/gpu/drm/i915/display/intel_display.c | 29 +-
> 3 files changed, 225 insertions(+), 87 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index f0bb4227338c..e2bcfbffb298 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -53,7 +53,18 @@ struct intel_color_funcs {
>* involved with the same commit.
>*/
> void (*load_luts)(const struct intel_crtc_state *crtc_state);
> + /*
> + * Read out the LUTs from the hardware into the software state.
> + * Used by eg. the hardware state checker.
> + */
> void (*read_luts)(struct intel_crtc_state *crtc_state);
> + /*
> + * Compare the LUTs
> + */
> + bool (*lut_equal)(const struct intel_crtc_state *crtc_state,
> + const struct drm_property_blob *blob1,
> + const struct drm_property_blob *blob2,
> + bool is_pre_csc_lut);
> };
>
> #define CTM_COEFF_SIGN (1ULL << 63)
> @@ -1234,6 +1245,24 @@ void intel_color_get_config(struct intel_crtc_state
> *crtc_state)
> i915->display.funcs.color->read_luts(crtc_state);
> }
>
> +bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state,
> +const struct drm_property_blob *blob1,
> +const struct drm_property_blob *blob2,
> +bool is_pre_csc_lut)
> +{
> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> +
> + /*
> + * FIXME c8_planes readout missing thus
> + * .read_luts() doesn't read out post_csc_lut.
> + */
> + if (!is_pre_csc_lut && crtc_state->c8_planes)
> + return true;
> +
> + return i915->display.funcs.color->lut_equal(crtc_state, blob1, blob2,
> + is_pre_csc_lut);
> +}
> +
> static bool need_plane_update(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state) { @@
> -1814,6
> +1843,24 @@ static int i9xx_post_csc_lut_precision(const struct
> intel_crtc_state
> *crtc_state
> }
> }
>
> +static int i9xx_pre_csc_lut_precision(const struct intel_crtc_state
> +*crtc_state) {
> + return 0;
> +}
> +
> +static int ilk_gamma_mode_precision(u32 gamma_mode) {
> + switch (gamma_mode) {
> + case GAMMA_MODE_MODE_8BIT:
> + return 8;
> + case GAMMA_MODE_MODE_10BIT:
> + return 10;
> + default:
> + MISSING_CASE(gamma_mode);
> + return 0;
> + }
> +}
> +
> static bool ilk_has_post_csc_lut(const struct intel_crtc_state *crtc_state)
> {
> if (crtc_state->c8_planes)
> @@ -1823,28 +1870,60 @@ static bool ilk_has_post_csc_lut(const struct
> intel_crtc_state *crtc_state)
> (crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) != 0; }
>
> +static bool ilk_has_pre_csc_lut(const struct intel_crtc_state
> +*crtc_state) {
> + return crtc_state->gamma_enable &&
> + (crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0; }
> +
> static int ilk_post_csc_lut_precision(const struct intel_crtc_state
> *crtc_state) {
> if (!ilk_has_post_csc_lut(crtc_state))
> return 0;
>
> - switch (crtc_state->gamma_mode) {
> - case GAMMA_MODE_MODE_8BIT:
> - return 8;
> - case GAMMA_MODE_MODE_10BIT:
> - return 10;
> - default:
> - MISSING_CASE(crtc_state->gamma_mode);
> + return ilk_gamma_mode_precision(crtc_state->gamma_mode);
> +}
> +
> +static int ilk_pre_csc_lut_precision(const struct
Re: [Intel-gfx] [PATCH v3 14/20] drm/i915: Make .read_luts() mandatory
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Monday, November 14, 2022 9:07 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 14/20] drm/i915: Make .read_luts() mandatory
>
> From: Ville Syrjälä
>
> Every platform now implemnts .read_luts(). Make it mandatory.
Nit: Typo in implements
Looks Good to me.
Reviewed-by: Uma Shankar
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index ca01b3e6b585..f0bb4227338c 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1231,8 +1231,7 @@ void intel_color_get_config(struct intel_crtc_state
> *crtc_state) {
> struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>
> - if (i915->display.funcs.color->read_luts)
> - i915->display.funcs.color->read_luts(crtc_state);
> + i915->display.funcs.color->read_luts(crtc_state);
> }
>
> static bool need_plane_update(struct intel_plane *plane,
> --
> 2.37.4
Re: [Intel-gfx] [PATCH v3 13/20] drm/i915: Prep for C8 palette readout
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Monday, November 14, 2022 9:07 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 13/20] drm/i915: Prep for C8 palette readout
>
> From: Ville Syrjälä
>
> Add the approproate c8_planes checks to make the LUT code ready for C8 palette
> readout. Note we currently lack the actual c8_planes readout, so this won't
> work
> yet. But no harm in making the code somewhat more ready for the day when we do
> get c8_planes readout.
Looks Good to me.
Reviewed-by: Uma Shankar
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 22 ++
> 1 file changed, 14 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index ef171837ef45..ca01b3e6b585 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1801,7 +1801,7 @@ static int icl_color_check(struct intel_crtc_state
> *crtc_state)
>
> static int i9xx_post_csc_lut_precision(const struct intel_crtc_state
> *crtc_state) {
> - if (!crtc_state->gamma_enable)
> + if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
> return 0;
>
> switch (crtc_state->gamma_mode) {
> @@ -1817,6 +1817,9 @@ static int i9xx_post_csc_lut_precision(const struct
> intel_crtc_state *crtc_state
>
> static bool ilk_has_post_csc_lut(const struct intel_crtc_state *crtc_state)
> {
> + if (crtc_state->c8_planes)
> + return true;
> +
> return crtc_state->gamma_enable &&
> (crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) != 0; }
> @@ -1847,7 +1850,7 @@ static int chv_post_csc_lut_precision(const struct
> intel_crtc_state *crtc_state)
>
> static int glk_post_csc_lut_precision(const struct intel_crtc_state
> *crtc_state) {
> - if (!crtc_state->gamma_enable)
> + if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
> return 0;
>
> switch (crtc_state->gamma_mode) {
> @@ -1863,6 +1866,9 @@ static int glk_post_csc_lut_precision(const struct
> intel_crtc_state *crtc_state)
>
> static bool icl_has_post_csc_lut(const struct intel_crtc_state *crtc_state)
> {
> + if (crtc_state->c8_planes)
> + return true;
> +
> return crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE; }
>
> @@ -2009,7 +2015,7 @@ static void i9xx_read_luts(struct intel_crtc_state
> *crtc_state) {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> - if (!crtc_state->gamma_enable)
> + if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
> return;
>
> crtc_state->post_csc_lut = i9xx_read_lut_8(crtc); @@ -2049,7 +2055,7 @@
> static void i965_read_luts(struct intel_crtc_state *crtc_state) {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> - if (!crtc_state->gamma_enable)
> + if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
> return;
>
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) @@ -2180,7
> +2186,7 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state)
> ilk_has_post_csc_lut(crtc_state) ?
> _state->post_csc_lut : _state->pre_csc_lut;
>
> - if (!crtc_state->gamma_enable)
> + if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
> return;
>
> switch (crtc_state->gamma_mode) {
> @@ -2240,7 +2246,7 @@ static void ivb_read_luts(struct intel_crtc_state
> *crtc_state)
> ilk_has_post_csc_lut(crtc_state) ?
> _state->post_csc_lut : _state->pre_csc_lut;
>
> - if (!crtc_state->gamma_enable)
> + if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
> return;
>
> switch (crtc_state->gamma_mode) {
> @@ -2303,7 +2309,7 @@ static void bdw_read_luts(struct intel_crtc_state
> *crtc_state)
> ilk_has_post_csc_lut(crtc_state) ?
> _state->post_csc_lut : _state->pre_csc_lut;
>
> - if (!crtc_state->gamma_enable)
> + if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
> return;
>
> switch (crtc_state->gamma_mode) {
> @@ -2372,7 +2378,7 @@ static void glk_read_luts(struct intel_crtc_state
> *crtc_state)
> if (crtc_state->csc_enable)
> crtc_state->pre_csc_lut = glk_read_degamma_lut(crtc);
>
> - if (!crtc_state->gamma_enable)
> + if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
> return;
>
> switch (crtc_state->gamma_mode) {
> --
> 2.37.4
Re: [Intel-gfx] [PATCH] drm/i915: Fix workarounds on Gen2-3
On Fri, Nov 18, 2022 at 11:52:49AM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> In 3653727560d0 ("drm/i915: Simplify internal helper function signature")
> I broke the old platforms by not noticing engine workaround init does not
> initialize the list on old platforms. Fix it by always initializing which
> already does the right thing by mostly not doing anything if there aren't
> any workarounds on the list.
>
> Signed-off-by: Tvrtko Ursulin
> Fixes: 3653727560d0 ("drm/i915: Simplify internal helper function signature")
> Reported-by: Ville Syrjälä
> Cc: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 213160f29ec3..4d7a01b45e09 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2991,7 +2991,7 @@ general_render_compute_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_li
> static void
> engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list
> *wal)
> {
> - if (I915_SELFTEST_ONLY(GRAPHICS_VER(engine->i915) < 4))
> + if (GRAPHICS_VER(engine->i915) < 4)
> return;
Do we even need this early return at all? As far as I can see, letting
this function run its course doesn't wind up having any effect or cause
any problems (you still wind up with an empty list).
Regardless,
Reviewed-by: Matt Roper
>
> engine_fake_wa_init(engine, wal);
> @@ -3016,9 +3016,6 @@ void intel_engine_init_workarounds(struct
> intel_engine_cs *engine)
> {
> struct i915_wa_list *wal = >wa_list;
>
> - if (GRAPHICS_VER(engine->i915) < 4)
> - return;
> -
> wa_init_start(wal, engine->gt, "engine", engine->name);
> engine_init_workarounds(engine, wal);
> wa_init_finish(wal);
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915/display: Add missing checks for cdclk crawling
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Add missing checks for
cdclk crawling
URL : https://patchwork.freedesktop.org/series/111045/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12396_full -> Patchwork_111045v1_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_111045v1_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_111045v1_full, please notify your bug team to allow
them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 11)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_111045v1_full:
### IGT changes ###
Possible regressions
* igt@gem_exec_reloc@basic-write-wc:
- shard-glk: [PASS][1] -> [TIMEOUT][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk3/igt@gem_exec_re...@basic-write-wc.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v1/shard-glk5/igt@gem_exec_re...@basic-write-wc.html
* igt@i915_selftest@live@evict:
- shard-skl: NOTRUN -> [INCOMPLETE][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v1/shard-skl7/igt@i915_selftest@l...@evict.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling:
- shard-glk: NOTRUN -> [TIMEOUT][4] +1 similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v1/shard-glk5/igt@kms_flip_scaled_...@flip-64bpp-ytile-to-32bpp-ytile-upscaling.html
Warnings
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-glk: [SKIP][5] ([fdo#109271] / [i915#658]) -> [TIMEOUT][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk3/igt@i915_pm...@dc3co-vpb-simulation.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v1/shard-glk5/igt@i915_pm...@dc3co-vpb-simulation.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_gttfill@all:
- {shard-rkl}:[PASS][7] -> [INCOMPLETE][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-rkl-4/igt@gem_exec_gttf...@all.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111045v1/shard-rkl-2/igt@gem_exec_gttf...@all.html
New tests
-
New tests have been introduced between CI_DRM_12396_full and
Patchwork_111045v1_full:
### New IGT tests (2) ###
* igt@kms_ccs:
- Statuses :
- Exec time: [None] s
* igt@kms_plane_scaling:
- Statuses :
- Exec time: [None] s
Known issues
Here are the changes found in Patchwork_111045v1_full that come from known
issues:
### CI changes ###
Issues hit
* boot:
- shard-glk: ([PASS][9], [PASS][10], [PASS][11], [PASS][12],
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18],
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24],
[PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30],
[PASS][31], [PASS][32], [PASS][33]) -> ([PASS][34], [PASS][35], [PASS][36],
[PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42],
[PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48],
[PASS][49], [FAIL][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54],
[PASS][55], [PASS][56], [PASS][57], [PASS][58]) ([i915#4392])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk9/boot.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk9/boot.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk9/boot.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk9/boot.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk8/boot.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk8/boot.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk8/boot.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk7/boot.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk7/boot.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk7/boot.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk6/boot.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk6/boot.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk6/boot.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk5/boot.html
[23]:
[Intel-gfx] Coverity: intel_hti_uses_phy(): Integer handling issues
Hello!
This is an experimental semi-automated report about issues detected by
Coverity from a scan of next-20221118 as part of the linux-next scan project:
https://scan.coverity.com/projects/linux-next-weekly-scan
You're getting this email because you were associated with the identified
lines of code (noted below) that were touched by commits:
Thu Nov 17 16:12:56 2022 +0200
62749912540b ("drm/i915/display: move hti under display sub-struct")
Coverity reported the following:
*** CID 1527374: Integer handling issues (BAD_SHIFT)
drivers/gpu/drm/i915/display/intel_hti.c:24 in intel_hti_uses_phy()
18 if (INTEL_INFO(i915)->display.has_hti)
19 i915->display.hti.state = intel_de_read(i915, HDPORT_STATE);
20 }
21
22 bool intel_hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
23 {
vvv CID 1527374: Integer handling issues (BAD_SHIFT)
vvv In expression "1UL << 2 * phy + 1", shifting by a negative amount has
undefined behavior. The shift amount, "2 * phy + 1", is as little as -1.
24 return i915->display.hti.state & HDPORT_ENABLED &&
25 i915->display.hti.state & HDPORT_DDI_USED(phy);
26 }
27
28 u32 intel_hti_dpll_mask(struct drm_i915_private *i915)
29 {
If this is a false positive, please let us know so we can mark it as
such, or teach the Coverity rules to be smarter. If not, please make
sure fixes get into linux-next. :) For patches fixing this, please
include these lines (but double-check the "Fixes" first):
Reported-by: coverity-bot
Addresses-Coverity-ID: 1527374 ("Integer handling issues")
Fixes: 62749912540b ("drm/i915/display: move hti under display sub-struct")
This code appears to be safe currently (intel_hti_uses_phy() is never
called with PHY_NONE), but perhaps add an explicit check?
if (WARN_ON(phy == PHY_NONE))
return false;
Thanks for your attention!
--
Coverity-bot
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/rpl-p: Add stepping info
On Fri, Nov 18, 2022 at 02:34:42PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/rpl-p: Add stepping info
> URL : https://patchwork.freedesktop.org/series/111041/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_12396_full -> Patchwork_111041v1_full
>
>
> Summary
> ---
>
> **SUCCESS**
>
> No regressions found.
Applied to drm-intel-next. Thanks for the patch.
Matt
>
>
>
> Participating hosts (11 -> 11)
> --
>
> No changes in participating hosts
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_111041v1_full:
>
> ### IGT changes ###
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@kms_cursor_legacy@single-bo@all-pipes:
> - {shard-rkl}:[PASS][1] -> [INCOMPLETE][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-rkl-3/igt@kms_cursor_legacy@single...@all-pipes.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-rkl-3/igt@kms_cursor_legacy@single...@all-pipes.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_111041v1_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gem_ccs@ctrl-surf-copy-new-ctx:
> - shard-skl: NOTRUN -> [SKIP][3] ([fdo#109271]) +144 similar
> issues
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-skl4/igt@gem_...@ctrl-surf-copy-new-ctx.html
>
> * igt@gem_create@create-ext-cpu-access-sanity-check:
> - shard-iclb: NOTRUN -> [SKIP][4] ([i915#6335])
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-iclb3/igt@gem_cre...@create-ext-cpu-access-sanity-check.html
>
> * igt@gem_exec_balancer@parallel-balancer:
> - shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525])
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-iclb1/igt@gem_exec_balan...@parallel-balancer.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-iclb3/igt@gem_exec_balan...@parallel-balancer.html
>
> * igt@gem_exec_fair@basic-none-solo@rcs0:
> - shard-apl: [PASS][7] -> [FAIL][8] ([i915#2842])
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-apl6/igt@gem_exec_fair@basic-none-s...@rcs0.html
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-apl7/igt@gem_exec_fair@basic-none-s...@rcs0.html
>
> * igt@gem_exec_fair@basic-none@vcs0:
> - shard-glk: [PASS][9] -> [FAIL][10] ([i915#2842])
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk5/igt@gem_exec_fair@basic-n...@vcs0.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-glk3/igt@gem_exec_fair@basic-n...@vcs0.html
>
> * igt@gem_huc_copy@huc-copy:
> - shard-tglb: [PASS][11] -> [SKIP][12] ([i915#2190])
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-tglb5/igt@gem_huc_c...@huc-copy.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-tglb7/igt@gem_huc_c...@huc-copy.html
>
> * igt@gem_lmem_swapping@heavy-verify-random:
> - shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613])
> +1 similar issue
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-apl3/igt@gem_lmem_swapp...@heavy-verify-random.html
>
> * igt@gem_lmem_swapping@parallel-multi:
> - shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613])
> +1 similar issue
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-skl3/igt@gem_lmem_swapp...@parallel-multi.html
>
> * igt@gem_tiled_wb:
> - shard-skl: NOTRUN -> [TIMEOUT][15] ([i915#6990])
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-skl3/igt@gem_tiled_wb.html
>
> * igt@gen9_exec_parse@unaligned-jump:
> - shard-iclb: NOTRUN -> [SKIP][16] ([i915#2856])
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-iclb3/igt@gen9_exec_pa...@unaligned-jump.html
>
> * igt@i915_pipe_stress@stress-xrgb-ytiled:
> - shard-skl: NOTRUN -> [FAIL][17] ([i915#7036]) +1 similar issue
>[17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-skl1/igt@i915_pipe_str...@stress-xrgb-ytiled.html
>
> * igt@i915_pm_rpm@dpms-non-lpsp:
> - shard-iclb: NOTRUN -> [SKIP][18] ([fdo#110892])
>[18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-iclb3/igt@i915_pm_...@dpms-non-lpsp.html
>
> * igt@i915_query@query-topology-unsupported:
> - shard-iclb: NOTRUN -> [SKIP][19] ([fdo#109302])
[Intel-gfx] [PATCH i-g-t] tests/i915/gem_exec_balancer: exercise dmabuf import
With parallel submission it should be easy to get a fence array as the
output fence. Try importing this into dma-buf reservation object, to see
if anything explodes.
References: https://gitlab.freedesktop.org/drm/intel/-/issues/7532
Signed-off-by: Matthew Auld
Cc: Andrzej Hajda
Cc: Nirmoy Das
---
tests/i915/gem_exec_balancer.c | 39 ++
1 file changed, 39 insertions(+)
diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
index 4300dbd1..fdae8de5 100644
--- a/tests/i915/gem_exec_balancer.c
+++ b/tests/i915/gem_exec_balancer.c
@@ -37,6 +37,7 @@
#include "igt_sysfs.h"
#include "igt_types.h"
#include "sw_sync.h"
+#include
IGT_TEST_DESCRIPTION("Exercise in-kernel load-balancing");
@@ -2856,6 +2857,24 @@ static void logical_sort_siblings(int i915,
#define PARALLEL_SUBMIT_FENCE (0x1 << 3)
#define PARALLEL_CONTEXTS (0x1 << 4)
#define PARALLEL_VIRTUAL (0x1 << 5)
+#define PARALLEL_OUT_FENCE_DMABUF (0x1 << 6)
+
+struct igt_dma_buf_sync_file {
+__u32 flags;
+__s32 fd;
+};
+
+#define IGT_DMA_BUF_IOCTL_EXPORT_SYNC_FILE _IOWR(DMA_BUF_BASE, 2, struct
igt_dma_buf_sync_file)
+#define IGT_DMA_BUF_IOCTL_IMPORT_SYNC_FILE _IOW(DMA_BUF_BASE, 3, struct
igt_dma_buf_sync_file)
+
+static void dmabuf_import_sync_file(int dmabuf, uint32_t flags, int sync_fd)
+{
+struct igt_dma_buf_sync_file arg;
+
+arg.flags = flags;
+arg.fd = sync_fd;
+do_ioctl(dmabuf, IGT_DMA_BUF_IOCTL_IMPORT_SYNC_FILE, );
+}
static void parallel_thread(int i915, unsigned int flags,
struct i915_engine_class_instance *siblings,
@@ -2871,6 +2890,8 @@ static void parallel_thread(int i915, unsigned int flags,
uint32_t target_bo_idx = 0;
uint32_t first_bb_idx = 1;
intel_ctx_cfg_t cfg;
+ uint32_t dmabuf_handle;
+ int dmabuf;
igt_assert(bb_per_execbuf < 32);
@@ -2924,11 +2945,20 @@ static void parallel_thread(int i915, unsigned int
flags,
execbuf.buffers_ptr = to_user_pointer(obj);
execbuf.rsvd1 = ctx->id;
+ if (flags & PARALLEL_OUT_FENCE_DMABUF) {
+ dmabuf_handle = gem_create(i915, 4096);
+ dmabuf = prime_handle_to_fd(i915, dmabuf_handle);
+ }
+
for (n = 0; n < PARALLEL_BB_LOOP_COUNT; ++n) {
execbuf.flags &= ~0x3full;
gem_execbuf_wr(i915, );
if (flags & PARALLEL_OUT_FENCE) {
+ if (flags & PARALLEL_OUT_FENCE_DMABUF)
+ dmabuf_import_sync_file(dmabuf,
DMA_BUF_SYNC_WRITE,
+ execbuf.rsvd2 >> 32);
+
igt_assert_eq(sync_fence_wait(execbuf.rsvd2 >> 32,
1000), 0);
igt_assert_eq(sync_fence_status(execbuf.rsvd2 >> 32),
1);
@@ -2959,6 +2989,11 @@ static void parallel_thread(int i915, unsigned int flags,
if (fence)
close(fence);
+ if (flags & PARALLEL_OUT_FENCE_DMABUF) {
+ gem_close(i915, dmabuf_handle);
+ close(dmabuf);
+ }
+
check_bo(i915, obj[target_bo_idx].handle,
bb_per_execbuf * PARALLEL_BB_LOOP_COUNT, true);
@@ -3420,6 +3455,10 @@ igt_main
igt_subtest("parallel-out-fence")
parallel(i915, PARALLEL_OUT_FENCE);
+ igt_subtest("parallel-out-fence-import-dmabuf")
+ parallel(i915, PARALLEL_OUT_FENCE |
+PARALLEL_OUT_FENCE_DMABUF);
+
igt_subtest("parallel-keep-in-fence")
parallel(i915, PARALLEL_OUT_FENCE | PARALLEL_IN_FENCE);
--
2.38.1
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/2] drm/i915/dg2: Introduce Wa_18018764978
== Series Details == Series: series starting with [v2,1/2] drm/i915/dg2: Introduce Wa_18018764978 URL : https://patchwork.freedesktop.org/series/111042/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12396_full -> Patchwork_111042v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_111042v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_111042v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 11) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_111042v1_full: ### IGT changes ### Possible regressions * igt@i915_selftest@live@evict: - shard-skl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/shard-skl9/igt@i915_selftest@l...@evict.html Known issues Here are the changes found in Patchwork_111042v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ccs@ctrl-surf-copy-new-ctx: - shard-skl: NOTRUN -> [SKIP][2] ([fdo#109271]) +170 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/shard-skl2/igt@gem_...@ctrl-surf-copy-new-ctx.html * igt@gem_create@create-ext-cpu-access-sanity-check: - shard-iclb: NOTRUN -> [SKIP][3] ([i915#6335]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/shard-iclb2/igt@gem_cre...@create-ext-cpu-access-sanity-check.html * igt@gem_exec_balancer@parallel: - shard-iclb: [PASS][4] -> [SKIP][5] ([i915#4525]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-iclb2/igt@gem_exec_balan...@parallel.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/shard-iclb5/igt@gem_exec_balan...@parallel.html * igt@gem_exec_fair@basic-none@vcs0: - shard-glk: [PASS][6] -> [FAIL][7] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk5/igt@gem_exec_fair@basic-n...@vcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/shard-glk6/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][8] -> [SKIP][9] ([i915#2190]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-tglb5/igt@gem_huc_c...@huc-copy.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/shard-tglb6/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-apl: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/shard-apl2/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-skl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/shard-skl4/igt@gem_lmem_swapp...@parallel-random-verify.html * igt@gem_tiled_wb: - shard-skl: NOTRUN -> [TIMEOUT][12] ([i915#6990]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/shard-skl9/igt@gem_tiled_wb.html * igt@gen9_exec_parse@unaligned-jump: - shard-iclb: NOTRUN -> [SKIP][13] ([i915#2856]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/shard-iclb2/igt@gen9_exec_pa...@unaligned-jump.html * igt@i915_pipe_stress@stress-xrgb-ytiled: - shard-skl: NOTRUN -> [FAIL][14] ([i915#7036]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/shard-skl9/igt@i915_pipe_str...@stress-xrgb-ytiled.html * igt@i915_pm_rpm@dpms-non-lpsp: - shard-iclb: NOTRUN -> [SKIP][15] ([fdo#110892]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/shard-iclb2/igt@i915_pm_...@dpms-non-lpsp.html * igt@i915_query@query-topology-unsupported: - shard-iclb: NOTRUN -> [SKIP][16] ([fdo#109302]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/shard-iclb2/igt@i915_qu...@query-topology-unsupported.html * igt@i915_selftest@live@gt_pm: - shard-skl: NOTRUN -> [DMESG-FAIL][17] ([i915#1886]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111042v1/shard-skl9/igt@i915_selftest@live@gt_pm.html * igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-b-hdmi-a-2: - shard-glk: NOTRUN -> [INCOMPLETE][18] ([i915#5584]) [18]:
[Intel-gfx] call to __compiletime_assert_1441 declared with attribute error: FIELD_PREP: mask is not constant
Hi, I'm getting this on latest Linus master with gcc (SUSE Linux) 7.5.0: DESCEND objtool CALLscripts/checksyscalls.sh CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_submission.o In file included from :0:0: In function ‘__guc_context_policy_add_priority.isra.45’, inlined from ‘__guc_context_set_prio.isra.46’ at drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:3198:3, inlined from ‘guc_context_set_prio’ at drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:3226:2: ././include/linux/compiler_types.h:357:38: error: call to ‘__compiletime_assert_1441’ declared with attribute error: FIELD_PREP: mask is not constant _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) ^ ././include/linux/compiler_types.h:338:4: note: in definition of macro ‘__compiletime_assert’ prefix ## suffix();\ ^~ ././include/linux/compiler_types.h:357:2: note: in expansion of macro ‘_compiletime_assert’ _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) ^~~ ./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’ #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg) ^~ ./include/linux/bitfield.h:65:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’ BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \ ^~~~ ./include/linux/bitfield.h:114:3: note: in expansion of macro ‘__BF_FIELD_CHECK’ __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \ ^~~~ drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:2399:3: note: in expansion of macro ‘FIELD_PREP’ FIELD_PREP(GUC_KLV_0_KEY, GUC_CONTEXT_POLICIES_KLV_ID_##id) | \ ^~ drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:2407:1: note: in expansion of macro ‘MAKE_CONTEXT_POLICY_ADD’ MAKE_CONTEXT_POLICY_ADD(priority, SCHEDULING_PRIORITY) ^~~ In function ‘__guc_context_policy_add_priority.isra.45’, inlined from ‘__guc_add_request’ at drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:2437:2: ././include/linux/compiler_types.h:357:38: error: call to ‘__compiletime_assert_1441’ declared with attribute error: FIELD_PREP: mask is not constant _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) ^ ././include/linux/compiler_types.h:338:4: note: in definition of macro ‘__compiletime_assert’ prefix ## suffix();\ ^~ ././include/linux/compiler_types.h:357:2: note: in expansion of macro ‘_compiletime_assert’ _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) ^~~ ./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’ #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg) ^~ ./include/linux/bitfield.h:65:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’ BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \ ^~~~ ./include/linux/bitfield.h:114:3: note: in expansion of macro ‘__BF_FIELD_CHECK’ __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \ ^~~~ drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:2399:3: note: in expansion of macro ‘FIELD_PREP’ FIELD_PREP(GUC_KLV_0_KEY, GUC_CONTEXT_POLICIES_KLV_ID_##id) | \ ^~ drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:2407:1: note: in expansion of macro ‘MAKE_CONTEXT_POLICY_ADD’ MAKE_CONTEXT_POLICY_ADD(priority, SCHEDULING_PRIORITY) ^~~ In function ‘__guc_context_policy_add_priority.isra.45’, inlined from ‘register_context’ at drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:2437:2: ././include/linux/compiler_types.h:357:38: error: call to ‘__compiletime_assert_1441’ declared with attribute error: FIELD_PREP: mask is not constant _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) ^ ././include/linux/compiler_types.h:338:4: note: in definition of macro ‘__compiletime_assert’ prefix ## suffix();\ ^~ ././include/linux/compiler_types.h:357:2: note: in expansion of macro ‘_compiletime_assert’ _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) ^~~ ./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’ #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg) ^~ ./include/linux/bitfield.h:65:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’ BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \ ^~~~ ./include/linux/bitfield.h:114:3: note: in expansion of macro ‘__BF_FIELD_CHECK’ __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \ ^~~~ drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:2399:3: note: in expansion of macro ‘FIELD_PREP’
Re: [Intel-gfx] [PATCH] drm/i915: rename intel_gsc to intel_heci_gsc
>
>
> On 11/3/2022 3:41 AM, Winkler, Tomas wrote:
> >> Starting on MTL, the GSC FW is loaded at runtime and will be managed
> >> directly by i915. This means we now have a naming clash around the
> >> GSC, as we have 2 different aspects of it that we need to handle: the
> >> HECI interfaces we export pre-mtl and the new full FW loading and
> >> support we have to introduce starting from MTL. To avoid confusion,
> >> rename the existing intel_gsc structure to intel_heci_gsc, to make it
> >> clear it contains the data related to the HECI interfaces.
> >>
> > Are you sure you want to take this path, it will make backporting quite
> difficult.
>
> The diff is relatively small (< 50 lines), so it shouldn't be too bad.
> Otherwise, do you have any suggestion on how to avoid name clashing in a
> different way? I really want to avoid confusion around legacy heci gsc and
> new runtime-loaded gsc. My plan was to name them intel_heci_gsc and
> intel_gsc_uc respectively, to make it super clear which is which, but I'm open
> to alternatives.
I think if you use intel_gsc_uc and leave the old as it is (at least for few
kernel release cylces) it would good. There is always spike of issues with thew
new hardware that requires backports to stable kernels.
That's what I think.
Thanks
Tomas
>
> Daniele
>
> >
> >> Signed-off-by: Daniele Ceraolo Spurio
> >>
> >> Cc: Tomas Winkler
> >> Cc: Alexander Usyskin
> >> ---
> >> drivers/gpu/drm/i915/Makefile | 4 +-
> >> drivers/gpu/drm/i915/gt/intel_gt.c| 4 +-
> >> drivers/gpu/drm/i915/gt/intel_gt.h| 4 +-
> >> drivers/gpu/drm/i915/gt/intel_gt_irq.c| 2 +-
> >> drivers/gpu/drm/i915/gt/intel_gt_types.h | 4 +-
> >> .../i915/gt/{intel_gsc.c => intel_heci_gsc.c} | 43
> >> ++- .../i915/gt/{intel_gsc.h => intel_heci_gsc.h} | 22
> +-
> >> drivers/gpu/drm/i915/gt/uc/intel_huc.c| 10 ++---
> >> drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 2 +-
> >> 9 files changed, 48 insertions(+), 47 deletions(-) rename
> >> drivers/gpu/drm/i915/gt/{intel_gsc.c => intel_heci_gsc.c} (84%)
> >> rename drivers/gpu/drm/i915/gt/{intel_gsc.h => intel_heci_gsc.h}
> >> (52%)
> >>
> >> diff --git a/drivers/gpu/drm/i915/Makefile
> >> b/drivers/gpu/drm/i915/Makefile index 51704b54317c..2fa401dcf087
> >> 100644
> >> --- a/drivers/gpu/drm/i915/Makefile
> >> +++ b/drivers/gpu/drm/i915/Makefile
> >> @@ -206,8 +206,8 @@ i915-y += gt/uc/intel_uc.o \
> >> gt/uc/intel_huc_debugfs.o \
> >> gt/uc/intel_huc_fw.o
> >>
> >> -# graphics system controller (GSC) support -i915-y += gt/intel_gsc.o
> >> +# graphics system controller (GSC) HECI support i915-y +=
> >> +gt/intel_heci_gsc.o
> >>
> >> # graphics hardware monitoring (HWMON) support
> >> i915-$(CONFIG_HWMON) += i915_hwmon.o diff --git
> >> a/drivers/gpu/drm/i915/gt/intel_gt.c
> >> b/drivers/gpu/drm/i915/gt/intel_gt.c
> >> index 8e914c4066ed..6ca72479c943 100644
> >> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> >> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> >> @@ -454,7 +454,7 @@ void intel_gt_chipset_flush(struct intel_gt *gt)
> >>
> >> void intel_gt_driver_register(struct intel_gt *gt) {
> >> - intel_gsc_init(>gsc, gt->i915);
> >> + intel_heci_gsc_init(>heci_gsc, gt->i915);
> >>
> >>intel_rps_driver_register(>rps);
> >>
> >> @@ -785,7 +785,7 @@ void intel_gt_driver_unregister(struct intel_gt
> >> *gt)
> >>
> >>intel_gt_sysfs_unregister(gt);
> >>intel_rps_driver_unregister(>rps);
> >> - intel_gsc_fini(>gsc);
> >> + intel_heci_gsc_fini(>heci_gsc);
> >>
> >>intel_pxp_fini(>pxp);
> >>
> >> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
> >> b/drivers/gpu/drm/i915/gt/intel_gt.h
> >> index e0365d556248..43f73239a363 100644
> >> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> >> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> >> @@ -39,9 +39,9 @@ static inline struct intel_gt *huc_to_gt(struct
> >> intel_huc
> >> *huc)
> >>return container_of(huc, struct intel_gt, uc.huc); }
> >>
> >> -static inline struct intel_gt *gsc_to_gt(struct intel_gsc *gsc)
> >> +static inline struct intel_gt *heci_gsc_to_gt(struct intel_heci_gsc
> >> +*heci_gsc)
> >> {
> >> - return container_of(gsc, struct intel_gt, gsc);
> >> + return container_of(heci_gsc, struct intel_gt, heci_gsc);
> >> }
> >>
> >> void intel_gt_common_init_early(struct intel_gt *gt); diff --git
> >> a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> >> b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> >> index f26882fdc24c..3b4bd237659a 100644
> >> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> >> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> >> @@ -75,7 +75,7 @@ gen11_other_irq_handler(struct intel_gt *gt, const
> >> u8 instance,
> >>return intel_pxp_irq_handler(>pxp, iir);
> >>
> >>if (instance == OTHER_GSC_INSTANCE)
> >> - return intel_gsc_irq_handler(gt, iir);
> >> + return intel_heci_gsc_irq_handler(gt, iir);
> >>
> >>WARN_ONCE(1, "unhandled other
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/2] drm/i915/migrate: Account for the reserved_space
== Series Details == Series: series starting with [v2,1/2] drm/i915/migrate: Account for the reserved_space URL : https://patchwork.freedesktop.org/series/111076/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12398 -> Patchwork_111076v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_111076v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_111076v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111076v1/index.html Participating hosts (41 -> 27) -- Additional (1): fi-rkl-11600 Missing(15): fi-ilk-m540 bat-dg1-7 fi-bdw-samus bat-dg1-6 bat-dg2-8 bat-adlm-1 bat-dg2-9 bat-adlp-6 bat-adlp-4 fi-ctg-p8600 bat-adln-1 bat-rplp-1 bat-rpls-2 bat-dg2-11 bat-jsl-1 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_111076v1: ### IGT changes ### Possible regressions * igt@i915_selftest@live@migrate: - fi-bsw-nick:[PASS][1] -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/fi-bsw-nick/igt@i915_selftest@l...@migrate.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111076v1/fi-bsw-nick/igt@i915_selftest@l...@migrate.html - fi-bsw-kefka: [PASS][3] -> [TIMEOUT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/fi-bsw-kefka/igt@i915_selftest@l...@migrate.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111076v1/fi-bsw-kefka/igt@i915_selftest@l...@migrate.html Known issues Here are the changes found in Patchwork_111076v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - fi-rkl-11600: NOTRUN -> [SKIP][5] ([i915#7456]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111076v1/fi-rkl-11600/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-rkl-11600: NOTRUN -> [SKIP][6] ([i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111076v1/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-apl-guc: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111076v1/fi-apl-guc/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-rkl-11600: NOTRUN -> [SKIP][8] ([i915#4613]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111076v1/fi-rkl-11600/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_tiled_pread_basic: - fi-rkl-11600: NOTRUN -> [SKIP][9] ([i915#3282]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111076v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - fi-rkl-11600: NOTRUN -> [SKIP][10] ([i915#7561]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111076v1/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html * igt@i915_suspend@basic-s3-without-i915: - fi-rkl-11600: NOTRUN -> [INCOMPLETE][11] ([i915#4817]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111076v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-apl-guc: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111076v1/fi-apl-guc/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-rkl-11600: NOTRUN -> [SKIP][13] ([fdo#111827]) +7 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111076v1/fi-rkl-11600/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor: - fi-rkl-11600: NOTRUN -> [SKIP][14] ([i915#4103]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111076v1/fi-rkl-11600/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html * igt@kms_force_connector_basic@force-load-detect: - fi-rkl-11600: NOTRUN -> [SKIP][15] ([fdo#109285] / [i915#4098]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111076v1/fi-rkl-11600/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_psr@sprite_plane_onoff: - fi-rkl-11600: NOTRUN -> [SKIP][16] ([i915#1072]) +3 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111076v1/fi-rkl-11600/igt@kms_psr@sprite_plane_onoff.html * igt@kms_setmode@basic-clone-single-crtc: - fi-rkl-11600: NOTRUN -> [SKIP][17] ([i915#3555] / [i915#4098]) [17]:
Re: [Intel-gfx] [PATCH 1/1] drm/i915/mtl: Enable Idle Messaging for GSC CS
On Fri, Nov 18, 2022 at 09:32:37AM -0500, Rodrigo Vivi wrote:
> On Fri, Nov 18, 2022 at 09:35:41AM +0530, Nilawar, Badal wrote:
> >
> >
> > On 18-11-2022 03:44, Rodrigo Vivi wrote:
> > > On Tue, Nov 15, 2022 at 07:14:40PM +0530, Badal Nilawar wrote:
> > > > From: Vinay Belgaumkar
> > > >
> > > > By defaut idle mesaging is disabled for GSC CS so to unblock RC6
> > > > entry on media tile idle messaging need to be enabled.
> > > >
> > > > v2:
> > > > - Fix review comments (Vinay)
> > > > - Set GSC idle hysterisis to 5 us (Badal)
> > > >
> > > > Bspec: 71496
> > > >
> > > > Cc: Daniele Ceraolo Spurio
> > > > Signed-off-by: Vinay Belgaumkar
> > > > Signed-off-by: Badal Nilawar
> > > > ---
> > > > drivers/gpu/drm/i915/gt/intel_engine_pm.c | 18 ++
> > > > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4
> > > > 2 files changed, 22 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > > > b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > > > index b0a4a2dbe3ee..5522885b2db0 100644
> > > > --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > > > @@ -15,6 +15,22 @@
> > > > #include "intel_rc6.h"
> > > > #include "intel_ring.h"
> > > > #include "shmem_utils.h"
> > > > +#include "intel_gt_regs.h"
> > > > +
> > > > +static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine)
> > > > +{
> > > > + struct drm_i915_private *i915 = engine->i915;
> > > > +
> > > > + if (IS_METEORLAKE(i915) && engine->id == GSC0) {
> > > > + intel_uncore_write(engine->gt->uncore,
> > > > + RC_PSMI_CTRL_GSCCS,
> > > > +
> > > > _MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));
> > >
> > > disable the disable? shouldn't be enable the disable?
> > > 1 = disable, no?
>
> doh! the function here is enable so the disable of disable is the
> right thing for this bit... Sorry for that.
>
>
> > >
> > > > + /* 5 us hysterisis */
> > >
> > > could you please mention here in the comment that 0xA = 5 us per spec?
> > > I got confused again even though you had explained already...
> > Sure I will add the comment "0xA=5 us as per spec"
>
> Thank you
>
> > >
> > > BTW, how reliable that spec is? Because according to that same line
> > > we should be setting the bit 16, not the bit 0 in the previous reg!
> > Bit 16 is mask bit.
>
> Okay, and we need to clear the bit 0. It makes sense. However the spec
> seems to ask us to set the mask, but we are not. Should we?
>
> Also from the register page:
> "Must be set to modify corresponding bit in Bits 15:0. (All implemented bits)"
>
> So it looks to me that we do need to set the bit16 to ensure that the
> clear of the bit 0 is valid, otherwise this is a bogus call.
oh, I hate these macros hiding things up... bit 16 is there on that
_MASKED_BIT_DISABLED as you showed me offline...
So, with the comment to the 5usec added, feel free to use:
Reviewed-by: Rodrigo Vivi
>
> > Bit 0 need to be cleared to enable Idle messaging.
> > Bit[0] = 1 Disable Idle Messaging / 0 Enable Idle Messaging.
> >
> > Regards,
> > Badal
> > >
> > > > + intel_uncore_write(engine->gt->uncore,
> > > > + PWRCTX_MAXCNT_GSCCS,
> > > > + 0xA);
> > > > + }
> > > > +}
> > > > static void dbg_poison_ce(struct intel_context *ce)
> > > > {
> > > > @@ -275,6 +291,8 @@ void intel_engine_init__pm(struct intel_engine_cs
> > > > *engine)
> > > > intel_wakeref_init(>wakeref, rpm, _ops);
> > > > intel_engine_init_heartbeat(engine);
> > > > +
> > > > + intel_gsc_idle_msg_enable(engine);
> > > > }
> > > > /**
> > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > > > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > > > index 07031e03f80c..20472eb15364 100644
> > > > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > > > @@ -913,6 +913,10 @@
> > > > #define MSG_IDLE_FW_MASK REG_GENMASK(13, 9)
> > > > #define MSG_IDLE_FW_SHIFT9
> > > > +#defineRC_PSMI_CTRL_GSCCS _MMIO(0x11a050)
> > > > +#define IDLE_MSG_DISABLE BIT(0)
> > > > +#define PWRCTX_MAXCNT_GSCCS_MMIO(0x11a054)
> > > > +
> > > > #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
> > > > #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
> > > > --
> > > > 2.25.1
> > > >
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/dg2: Introduce Wa_18019271663
On Thu, Nov 17, 2022 at 02:24:47PM -0800, Matt Atwood wrote: > Wa_18019271663 applies to all DG2 steppings and skus. > > Bspec: 66622 > > Signed-off-by: Matt Atwood > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ > 2 files changed, 7 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 1711dbf9dd462..62a17baacf03e 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -429,9 +429,10 @@ > #define RC_OP_FLUSH_ENABLE (1 << 0) > #define HIZ_RAW_STALL_OPT_DISABLE (1 << 2) > #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ > -#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6) > -#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6) > -#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1) > +#define MSAA_OPTIMIZATION_REDUC_DISABLEREG_BIT(11) > +#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE REG_BIT(6) > +#define GEN8_4x4_STC_OPTIMIZATION_DISABLE REG_BIT(6) > +#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE REG_BIT(1) > > #define GEN7_GT_MODE _MMIO(0x7008) > #define GEN9_IZ_HASHING_MASK(slice)(0x3 << ((slice) * 2)) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 483fd2a83ca19..452e423233207 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -781,6 +781,9 @@ static void dg2_ctx_workarounds_init(struct > intel_engine_cs *engine, > > /* Wa_15010599737:dg2 */ > wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); > + > + /*Wa_18019271663:dg2 */ Nitpick: add a space after "/*". With that, Reviewed-by: Gustavo Sousa > + wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); > } > > static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, > -- > 2.38.1 >
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/rpl-p: Add stepping info
== Series Details ==
Series: drm/i915/rpl-p: Add stepping info
URL : https://patchwork.freedesktop.org/series/111041/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12396_full -> Patchwork_111041v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (11 -> 11)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_111041v1_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_cursor_legacy@single-bo@all-pipes:
- {shard-rkl}:[PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-rkl-3/igt@kms_cursor_legacy@single...@all-pipes.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-rkl-3/igt@kms_cursor_legacy@single...@all-pipes.html
Known issues
Here are the changes found in Patchwork_111041v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-skl: NOTRUN -> [SKIP][3] ([fdo#109271]) +144 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-skl4/igt@gem_...@ctrl-surf-copy-new-ctx.html
* igt@gem_create@create-ext-cpu-access-sanity-check:
- shard-iclb: NOTRUN -> [SKIP][4] ([i915#6335])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-iclb3/igt@gem_cre...@create-ext-cpu-access-sanity-check.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-iclb1/igt@gem_exec_balan...@parallel-balancer.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-iclb3/igt@gem_exec_balan...@parallel-balancer.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][7] -> [FAIL][8] ([i915#2842])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-apl6/igt@gem_exec_fair@basic-none-s...@rcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-apl7/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk5/igt@gem_exec_fair@basic-n...@vcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-glk3/igt@gem_exec_fair@basic-n...@vcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][11] -> [SKIP][12] ([i915#2190])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-tglb5/igt@gem_huc_c...@huc-copy.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-tglb7/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-apl3/igt@gem_lmem_swapp...@heavy-verify-random.html
* igt@gem_lmem_swapping@parallel-multi:
- shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +1
similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-skl3/igt@gem_lmem_swapp...@parallel-multi.html
* igt@gem_tiled_wb:
- shard-skl: NOTRUN -> [TIMEOUT][15] ([i915#6990])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-skl3/igt@gem_tiled_wb.html
* igt@gen9_exec_parse@unaligned-jump:
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#2856])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-iclb3/igt@gen9_exec_pa...@unaligned-jump.html
* igt@i915_pipe_stress@stress-xrgb-ytiled:
- shard-skl: NOTRUN -> [FAIL][17] ([i915#7036]) +1 similar issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-skl1/igt@i915_pipe_str...@stress-xrgb-ytiled.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- shard-iclb: NOTRUN -> [SKIP][18] ([fdo#110892])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-iclb3/igt@i915_pm_...@dpms-non-lpsp.html
* igt@i915_query@query-topology-unsupported:
- shard-iclb: NOTRUN -> [SKIP][19] ([fdo#109302])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111041v1/shard-iclb3/igt@i915_qu...@query-topology-unsupported.html
* igt@i915_selftest@live@hangcheck:
- shard-tglb: [PASS][20] -> [DMESG-WARN][21] ([i915#5591])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-tglb3/igt@i915_selftest@l...@hangcheck.html
[21]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/i915/migrate: Account for the reserved_space
== Series Details == Series: series starting with [v2,1/2] drm/i915/migrate: Account for the reserved_space URL : https://patchwork.freedesktop.org/series/111076/ State : warning == Summary == Error: dim checkpatch failed 4cce983fec4a drm/i915/migrate: Account for the reserved_space -:33: WARNING:LEADING_SPACE: please, no spaces at the start of a line #33: FILE: drivers/gpu/drm/i915/gt/intel_migrate.c:347: + struct intel_ring *ring = rq->ring;$ -:35: WARNING:LEADING_SPACE: please, no spaces at the start of a line #35: FILE: drivers/gpu/drm/i915/gt/intel_migrate.c:349: + pkt = min_t(int, pkt, (ring->space - rq->reserved_space) / sizeof(u32) + 5);$ -:36: WARNING:LEADING_SPACE: please, no spaces at the start of a line #36: FILE: drivers/gpu/drm/i915/gt/intel_migrate.c:350: + pkt = min_t(int, pkt, (ring->size - ring->emit) / sizeof(u32) + 5);$ -:38: WARNING:LEADING_SPACE: please, no spaces at the start of a line #38: FILE: drivers/gpu/drm/i915/gt/intel_migrate.c:352: + return pkt;$ total: 0 errors, 4 warnings, 0 checks, 34 lines checked 28ff1746d334 drm/i915/selftests: exercise emit_pte() with nearly full ring -:179: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst #179: FILE: drivers/gpu/drm/i915/gt/selftest_migrate.c:644: + msleep(10); /* start all threads before we kthread_stop() */ total: 0 errors, 1 warnings, 0 checks, 194 lines checked
Re: [Intel-gfx] [PATCH 1/1] drm/i915/mtl: Enable Idle Messaging for GSC CS
On Fri, Nov 18, 2022 at 09:35:41AM +0530, Nilawar, Badal wrote:
>
>
> On 18-11-2022 03:44, Rodrigo Vivi wrote:
> > On Tue, Nov 15, 2022 at 07:14:40PM +0530, Badal Nilawar wrote:
> > > From: Vinay Belgaumkar
> > >
> > > By defaut idle mesaging is disabled for GSC CS so to unblock RC6
> > > entry on media tile idle messaging need to be enabled.
> > >
> > > v2:
> > > - Fix review comments (Vinay)
> > > - Set GSC idle hysterisis to 5 us (Badal)
> > >
> > > Bspec: 71496
> > >
> > > Cc: Daniele Ceraolo Spurio
> > > Signed-off-by: Vinay Belgaumkar
> > > Signed-off-by: Badal Nilawar
> > > ---
> > > drivers/gpu/drm/i915/gt/intel_engine_pm.c | 18 ++
> > > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4
> > > 2 files changed, 22 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > > b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > > index b0a4a2dbe3ee..5522885b2db0 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > > @@ -15,6 +15,22 @@
> > > #include "intel_rc6.h"
> > > #include "intel_ring.h"
> > > #include "shmem_utils.h"
> > > +#include "intel_gt_regs.h"
> > > +
> > > +static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine)
> > > +{
> > > + struct drm_i915_private *i915 = engine->i915;
> > > +
> > > + if (IS_METEORLAKE(i915) && engine->id == GSC0) {
> > > + intel_uncore_write(engine->gt->uncore,
> > > +RC_PSMI_CTRL_GSCCS,
> > > +_MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));
> >
> > disable the disable? shouldn't be enable the disable?
> > 1 = disable, no?
doh! the function here is enable so the disable of disable is the
right thing for this bit... Sorry for that.
> >
> > > + /* 5 us hysterisis */
> >
> > could you please mention here in the comment that 0xA = 5 us per spec?
> > I got confused again even though you had explained already...
> Sure I will add the comment "0xA=5 us as per spec"
Thank you
> >
> > BTW, how reliable that spec is? Because according to that same line
> > we should be setting the bit 16, not the bit 0 in the previous reg!
> Bit 16 is mask bit.
Okay, and we need to clear the bit 0. It makes sense. However the spec
seems to ask us to set the mask, but we are not. Should we?
Also from the register page:
"Must be set to modify corresponding bit in Bits 15:0. (All implemented bits)"
So it looks to me that we do need to set the bit16 to ensure that the
clear of the bit 0 is valid, otherwise this is a bogus call.
> Bit 0 need to be cleared to enable Idle messaging.
> Bit[0] = 1 Disable Idle Messaging / 0 Enable Idle Messaging.
>
> Regards,
> Badal
> >
> > > + intel_uncore_write(engine->gt->uncore,
> > > +PWRCTX_MAXCNT_GSCCS,
> > > +0xA);
> > > + }
> > > +}
> > > static void dbg_poison_ce(struct intel_context *ce)
> > > {
> > > @@ -275,6 +291,8 @@ void intel_engine_init__pm(struct intel_engine_cs
> > > *engine)
> > > intel_wakeref_init(>wakeref, rpm, _ops);
> > > intel_engine_init_heartbeat(engine);
> > > +
> > > + intel_gsc_idle_msg_enable(engine);
> > > }
> > > /**
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > > index 07031e03f80c..20472eb15364 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > > @@ -913,6 +913,10 @@
> > > #define MSG_IDLE_FW_MASK REG_GENMASK(13, 9)
> > > #define MSG_IDLE_FW_SHIFT 9
> > > +#define RC_PSMI_CTRL_GSCCS _MMIO(0x11a050)
> > > +#defineIDLE_MSG_DISABLE BIT(0)
> > > +#define PWRCTX_MAXCNT_GSCCS _MMIO(0x11a054)
> > > +
> > > #define FORCEWAKE_MEDIA_GEN9_MMIO(0xa270)
> > > #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
> > > --
> > > 2.25.1
> > >
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/dg2: Introduce Wa_18018764978
On Thu, Nov 17, 2022 at 02:24:46PM -0800, Matt Atwood wrote: > Wa_18018764978 applies to specific steppings of DG2 (G10 C0+, > G11 and G12 A0+). > > Bspec: 66622 > > Signed-off-by: Matt Atwood > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 + > 2 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index c3cd926917957..1711dbf9dd462 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -457,6 +457,9 @@ > #define GEN8_L3CNTLREG _MMIO(0x7034) > #define GEN8_ERRDETBCTRL (1 << 9) > > +#define PSS_MODE2_MMIO(0x703c) > +#define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) > + > #define GEN7_SC_INSTDONE _MMIO(0x7100) > #define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104) > #define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 1bd8d63ad4f3f..483fd2a83ca19 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -774,6 +774,11 @@ static void dg2_ctx_workarounds_init(struct > intel_engine_cs *engine, > IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > wa_masked_field_set(wal, VF_PREEMPTION, > PREEMPTION_VERTEX_COUNT, 0x4000); > > + /* Wa_18018764978:dg2 */ > + if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) || > + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) With the fix to align this line match the open parenthesis, Reviewed-by: Gustavo Sousa > + wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); > + > /* Wa_15010599737:dg2 */ > wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); > } > -- > 2.38.1 >
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix timeout handling when retiring requests (rev2)
== Series Details == Series: drm/i915: Fix timeout handling when retiring requests (rev2) URL : https://patchwork.freedesktop.org/series/110964/ State : success == Summary == CI Bug Log - changes from CI_DRM_12398 -> Patchwork_110964v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/index.html Participating hosts (41 -> 39) -- Additional (1): fi-rkl-11600 Missing(3): fi-ctg-p8600 fi-ilk-m540 fi-bdw-samus Known issues Here are the changes found in Patchwork_110964v2 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - fi-rkl-11600: NOTRUN -> [SKIP][1] ([i915#7456]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-rkl-11600: NOTRUN -> [SKIP][2] ([i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-apl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-apl-guc/igt@gem_lmem_swapp...@basic.html - fi-rkl-11600: NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@gem_lmem_swapp...@basic.html * igt@gem_tiled_pread_basic: - fi-rkl-11600: NOTRUN -> [SKIP][5] ([i915#3282]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - fi-rkl-11600: NOTRUN -> [SKIP][6] ([i915#7561]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@gt_heartbeat: - fi-bxt-dsi: [PASS][7] -> [DMESG-FAIL][8] ([i915#5334]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_suspend@basic-s3-without-i915: - fi-rkl-11600: NOTRUN -> [INCOMPLETE][9] ([i915#4817]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-apl-guc: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-apl-guc/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-edid-read: - fi-rkl-11600: NOTRUN -> [SKIP][11] ([fdo#111827]) +7 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@kms_chamel...@hdmi-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor: - fi-rkl-11600: NOTRUN -> [SKIP][12] ([i915#4103]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html * igt@kms_force_connector_basic@force-load-detect: - fi-rkl-11600: NOTRUN -> [SKIP][13] ([fdo#109285] / [i915#4098]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_psr@primary_page_flip: - fi-rkl-11600: NOTRUN -> [SKIP][14] ([i915#1072]) +3 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@kms_psr@primary_page_flip.html * igt@kms_setmode@basic-clone-single-crtc: - fi-rkl-11600: NOTRUN -> [SKIP][15] ([i915#3555] / [i915#4098]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-read: - fi-rkl-11600: NOTRUN -> [SKIP][16] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@prime_v...@basic-read.html * igt@prime_vgem@basic-userptr: - fi-rkl-11600: NOTRUN -> [SKIP][17] ([fdo#109295] / [i915#3301] / [i915#3708]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@prime_v...@basic-userptr.html Possible fixes * igt@core_hotunplug@unbind-rebind: - fi-apl-guc: [INCOMPLETE][18] ([i915#7073]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html *
Re: [Intel-gfx] [PATCH 1/2] drm/i915/migrate: Account for the reserved_space
On 11/18/2022 1:48 PM, Matthew Auld wrote:
From: Chris Wilson
If the ring is nearly full when calling into emit_pte(), we might
incorrectly trample the reserved_space when constructing the packet to
emit the PTEs. This then triggers the GEM_BUG_ON(rq->reserved_space >
ring->space) when later submitting the request, since the request itself
doesn't have enough space left in the ring to emit things like
workarounds, breadcrumbs etc.
Testcase: igt@i915_selftests@live_emit_pte_full_ring
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7535
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6889
Fixes: cf586021642d ("drm/i915/gt: Pipelined page migration")
Signed-off-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Andrzej Hajda
Cc: Nirmoy Das
Tested this on ATS-M.
Tested-by: Nirmoy Das
Reviewed-by: Nirmoy Das
Cc: # v5.15+
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index b405a04135ca..48c3b5168558 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -342,6 +342,16 @@ static int emit_no_arbitration(struct i915_request *rq)
return 0;
}
+static int max_pte_pkt_size(struct i915_request *rq, int pkt)
+{
+ struct intel_ring *ring = rq->ring;
+
+ pkt = min_t(int, pkt, (ring->space - rq->reserved_space) / sizeof(u32)
+ 5);
+ pkt = min_t(int, pkt, (ring->size - ring->emit) / sizeof(u32) + 5);
+
+ return pkt;
+}
+
static int emit_pte(struct i915_request *rq,
struct sgt_dma *it,
enum i915_cache_level cache_level,
@@ -388,8 +398,7 @@ static int emit_pte(struct i915_request *rq,
return PTR_ERR(cs);
/* Pack as many PTE updates as possible into a single MI command */
- pkt = min_t(int, dword_length, ring->space / sizeof(u32) + 5);
- pkt = min_t(int, pkt, (ring->size - ring->emit) / sizeof(u32) + 5);
+ pkt = max_pte_pkt_size(rq, dword_length);
hdr = cs;
*cs++ = MI_STORE_DATA_IMM | REG_BIT(21); /* as qword elements */
@@ -422,8 +431,7 @@ static int emit_pte(struct i915_request *rq,
}
}
- pkt = min_t(int, dword_rem, ring->space / sizeof(u32) + 5);
- pkt = min_t(int, pkt, (ring->size - ring->emit) /
sizeof(u32) + 5);
+ pkt = max_pte_pkt_size(rq, dword_rem);
hdr = cs;
*cs++ = MI_STORE_DATA_IMM | REG_BIT(21);
[Intel-gfx] [PATCH v2 2/2] drm/i915/selftests: exercise emit_pte() with nearly full ring
Simple regression test to check that we don't trample the
rq->reserved_space when returning from emit_pte(), if the ring is nearly
full.
v2: make spinner_kill() static
References: https://gitlab.freedesktop.org/drm/intel/-/issues/7535
References: https://gitlab.freedesktop.org/drm/intel/-/issues/6889
Signed-off-by: Matthew Auld
Cc: Chris Wilson
Cc: Andrzej Hajda
Cc: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_migrate.c| 6 +-
drivers/gpu/drm/i915/gt/selftest_migrate.c | 152 +
2 files changed, 156 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 48c3b5168558..6df728b82a73 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -352,6 +352,8 @@ static int max_pte_pkt_size(struct i915_request *rq, int
pkt)
return pkt;
}
+#define I915_EMIT_PTE_NUM_DWORDS 6
+
static int emit_pte(struct i915_request *rq,
struct sgt_dma *it,
enum i915_cache_level cache_level,
@@ -393,7 +395,7 @@ static int emit_pte(struct i915_request *rq,
offset += (u64)rq->engine->instance << 32;
- cs = intel_ring_begin(rq, 6);
+ cs = intel_ring_begin(rq, I915_EMIT_PTE_NUM_DWORDS);
if (IS_ERR(cs))
return PTR_ERR(cs);
@@ -416,7 +418,7 @@ static int emit_pte(struct i915_request *rq,
intel_ring_advance(rq, cs);
intel_ring_update_space(ring);
- cs = intel_ring_begin(rq, 6);
+ cs = intel_ring_begin(rq, I915_EMIT_PTE_NUM_DWORDS);
if (IS_ERR(cs))
return PTR_ERR(cs);
diff --git a/drivers/gpu/drm/i915/gt/selftest_migrate.c
b/drivers/gpu/drm/i915/gt/selftest_migrate.c
index 0dc5309c90a4..edac9e4dec55 100644
--- a/drivers/gpu/drm/i915/gt/selftest_migrate.c
+++ b/drivers/gpu/drm/i915/gt/selftest_migrate.c
@@ -8,6 +8,7 @@
#include "gem/i915_gem_internal.h"
#include "gem/i915_gem_lmem.h"
+#include "selftests/igt_spinner.h"
#include "selftests/i915_random.h"
static const unsigned int sizes[] = {
@@ -527,6 +528,156 @@ static int live_migrate_clear(void *arg)
return 0;
}
+static int spinner_kill(void *arg)
+{
+ struct igt_spinner *spin = arg;
+
+ msleep(2000); /* Should be plenty */
+ igt_spinner_end(spin);
+ return 0;
+}
+
+static int live_emit_pte_full_ring(void *arg)
+{
+ struct intel_migrate *migrate = arg;
+ struct drm_i915_private *i915 = migrate->context->engine->i915;
+ struct drm_i915_gem_object *obj;
+ struct intel_context *ce;
+ struct i915_request *rq, *prev;
+ struct igt_spinner spin;
+ struct task_struct *tsk = NULL;
+ struct sgt_dma it;
+ int len, sz, err;
+ int status;
+ u32 *cs;
+
+ /*
+* Simple regression test to check that we don't trample the
+* rq->reserved_space when returning from emit_pte(), if the ring is
+* nearly full.
+*/
+
+ if (igt_spinner_init(, to_gt(i915)))
+ return -ENOMEM;
+
+ obj = i915_gem_object_create_internal(i915, 2 * PAGE_SIZE);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ goto out_spinner;
+ }
+
+ err = i915_gem_object_pin_pages_unlocked(obj);
+ if (err)
+ goto out_obj;
+
+ ce = intel_migrate_create_context(migrate);
+ if (IS_ERR(ce)) {
+ err = PTR_ERR(ce);
+ goto out_obj;
+ }
+
+ ce->ring_size = SZ_4K; /* Not too big */
+
+ err = intel_context_pin(ce);
+ if (err)
+ goto out_put;
+
+ rq = igt_spinner_create_request(, ce, MI_ARB_CHECK);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_unpin;
+ }
+
+ i915_request_add(rq);
+ if (!igt_wait_for_spinner(, rq)) {
+ err = -EIO;
+ goto out_unpin;
+ }
+
+ /*
+* Fill the ring leaving I915_EMIT_PTE_NUM_DWORDS + ring->reserved_space
+* at the end. To actually emit the PTEs we require slightly more than
+* I915_EMIT_PTE_NUM_DWORDS, since our object size is greater than
+* PAGE_SIZE. The correct behaviour is to wait for more ring space in
+* emit_pte(), otherwise we trample on the reserved_space resulting in
+* crashes when later submitting the rq.
+*/
+
+ prev = NULL;
+ do {
+ if (prev)
+ i915_request_add(rq);
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_unpin;
+ }
+
+ sz = (rq->ring->space - rq->reserved_space) / sizeof(u32) -
+ I915_EMIT_PTE_NUM_DWORDS;
+ sz = min_t(u32, sz, SZ_1K
[Intel-gfx] [PATCH v2 1/2] drm/i915/migrate: Account for the reserved_space
From: Chris Wilson
If the ring is nearly full when calling into emit_pte(), we might
incorrectly trample the reserved_space when constructing the packet to
emit the PTEs. This then triggers the GEM_BUG_ON(rq->reserved_space >
ring->space) when later submitting the request, since the request itself
doesn't have enough space left in the ring to emit things like
workarounds, breadcrumbs etc.
Testcase: igt@i915_selftests@live_emit_pte_full_ring
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7535
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6889
Fixes: cf586021642d ("drm/i915/gt: Pipelined page migration")
Signed-off-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Andrzej Hajda
Cc: Nirmoy Das
Cc: # v5.15+
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index b405a04135ca..48c3b5168558 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -342,6 +342,16 @@ static int emit_no_arbitration(struct i915_request *rq)
return 0;
}
+static int max_pte_pkt_size(struct i915_request *rq, int pkt)
+{
+ struct intel_ring *ring = rq->ring;
+
+ pkt = min_t(int, pkt, (ring->space - rq->reserved_space) / sizeof(u32)
+ 5);
+ pkt = min_t(int, pkt, (ring->size - ring->emit) / sizeof(u32) + 5);
+
+ return pkt;
+}
+
static int emit_pte(struct i915_request *rq,
struct sgt_dma *it,
enum i915_cache_level cache_level,
@@ -388,8 +398,7 @@ static int emit_pte(struct i915_request *rq,
return PTR_ERR(cs);
/* Pack as many PTE updates as possible into a single MI command */
- pkt = min_t(int, dword_length, ring->space / sizeof(u32) + 5);
- pkt = min_t(int, pkt, (ring->size - ring->emit) / sizeof(u32) + 5);
+ pkt = max_pte_pkt_size(rq, dword_length);
hdr = cs;
*cs++ = MI_STORE_DATA_IMM | REG_BIT(21); /* as qword elements */
@@ -422,8 +431,7 @@ static int emit_pte(struct i915_request *rq,
}
}
- pkt = min_t(int, dword_rem, ring->space / sizeof(u32) +
5);
- pkt = min_t(int, pkt, (ring->size - ring->emit) /
sizeof(u32) + 5);
+ pkt = max_pte_pkt_size(rq, dword_rem);
hdr = cs;
*cs++ = MI_STORE_DATA_IMM | REG_BIT(21);
--
2.38.1
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/2] drm/i915/mtl: Fix dram info readout
== Series Details == Series: series starting with [v2,1/2] drm/i915/mtl: Fix dram info readout URL : https://patchwork.freedesktop.org/series/111039/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12396_full -> Patchwork_111039v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_111039v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_111039v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 11) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_111039v1_full: ### IGT changes ### Possible regressions * igt@i915_selftest@live@evict: - shard-skl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/shard-skl10/igt@i915_selftest@l...@evict.html Known issues Here are the changes found in Patchwork_111039v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-ext-cpu-access-sanity-check: - shard-iclb: NOTRUN -> [SKIP][2] ([i915#6335]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/shard-iclb2/igt@gem_cre...@create-ext-cpu-access-sanity-check.html * igt@gem_eio@reset-stress: - shard-snb: [PASS][3] -> [TIMEOUT][4] ([i915#3063]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-snb7/igt@gem_...@reset-stress.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/shard-snb7/igt@gem_...@reset-stress.html * igt@gem_exec_balancer@parallel: - shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-iclb2/igt@gem_exec_balan...@parallel.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/shard-iclb3/igt@gem_exec_balan...@parallel.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-tglb1/igt@gem_exec_fair@basic-f...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/shard-tglb2/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-apl: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-apl6/igt@gem_exec_fair@basic-none-s...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/shard-apl8/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-apl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/shard-apl1/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-skl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +2 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/shard-skl6/igt@gem_lmem_swapp...@parallel-random-verify.html * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled: - shard-skl: NOTRUN -> [SKIP][13] ([fdo#109271]) +204 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/shard-skl7/igt@gem_render_c...@yf-tiled-mc-ccs-to-vebox-yf-tiled.html * igt@gem_tiled_wb: - shard-skl: NOTRUN -> [TIMEOUT][14] ([i915#6990]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/shard-skl10/igt@gem_tiled_wb.html * igt@gen9_exec_parse@unaligned-jump: - shard-iclb: NOTRUN -> [SKIP][15] ([i915#2856]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/shard-iclb2/igt@gen9_exec_pa...@unaligned-jump.html * igt@i915_pipe_stress@stress-xrgb-ytiled: - shard-skl: NOTRUN -> [FAIL][16] ([i915#7036]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/shard-skl4/igt@i915_pipe_str...@stress-xrgb-ytiled.html * igt@i915_pm_dc@dc9-dpms: - shard-iclb: [PASS][17] -> [SKIP][18] ([i915#4281]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-iclb7/igt@i915_pm...@dc9-dpms.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/shard-iclb3/igt@i915_pm...@dc9-dpms.html * igt@i915_pm_rpm@dpms-non-lpsp: - shard-iclb: NOTRUN -> [SKIP][19] ([fdo#110892]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111039v1/shard-iclb2/igt@i915_pm_...@dpms-non-lpsp.html * igt@i915_query@query-topology-unsupported: -
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915/migrate: Account for the reserved_space
== Series Details == Series: series starting with [1/2] drm/i915/migrate: Account for the reserved_space URL : https://patchwork.freedesktop.org/series/111072/ State : failure == Summary == Error: make failed CALLscripts/checksyscalls.sh DESCEND objtool CC [M] drivers/gpu/drm/i915/gt/intel_migrate.o In file included from drivers/gpu/drm/i915/gt/intel_migrate.c:1137: drivers/gpu/drm/i915/gt/selftest_migrate.c:531:5: error: no previous prototype for ‘spinner_kill’ [-Werror=missing-prototypes] int spinner_kill(void *arg) ^~~~ cc1: all warnings being treated as errors scripts/Makefile.build:250: recipe for target 'drivers/gpu/drm/i915/gt/intel_migrate.o' failed make[5]: *** [drivers/gpu/drm/i915/gt/intel_migrate.o] Error 1 scripts/Makefile.build:500: recipe for target 'drivers/gpu/drm/i915' failed make[4]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:500: recipe for target 'drivers/gpu/drm' failed make[3]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:500: recipe for target 'drivers/gpu' failed make[2]: *** [drivers/gpu] Error 2 scripts/Makefile.build:500: recipe for target 'drivers' failed make[1]: *** [drivers] Error 2 Makefile:1992: recipe for target '.' failed make: *** [.] Error 2
[Intel-gfx] [PATCH 1/2] drm/i915/migrate: Account for the reserved_space
From: Chris Wilson
If the ring is nearly full when calling into emit_pte(), we might
incorrectly trample the reserved_space when constructing the packet to
emit the PTEs. This then triggers the GEM_BUG_ON(rq->reserved_space >
ring->space) when later submitting the request, since the request itself
doesn't have enough space left in the ring to emit things like
workarounds, breadcrumbs etc.
Testcase: igt@i915_selftests@live_emit_pte_full_ring
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7535
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6889
Fixes: cf586021642d ("drm/i915/gt: Pipelined page migration")
Signed-off-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Andrzej Hajda
Cc: Nirmoy Das
Cc: # v5.15+
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index b405a04135ca..48c3b5168558 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -342,6 +342,16 @@ static int emit_no_arbitration(struct i915_request *rq)
return 0;
}
+static int max_pte_pkt_size(struct i915_request *rq, int pkt)
+{
+ struct intel_ring *ring = rq->ring;
+
+ pkt = min_t(int, pkt, (ring->space - rq->reserved_space) / sizeof(u32)
+ 5);
+ pkt = min_t(int, pkt, (ring->size - ring->emit) / sizeof(u32) + 5);
+
+ return pkt;
+}
+
static int emit_pte(struct i915_request *rq,
struct sgt_dma *it,
enum i915_cache_level cache_level,
@@ -388,8 +398,7 @@ static int emit_pte(struct i915_request *rq,
return PTR_ERR(cs);
/* Pack as many PTE updates as possible into a single MI command */
- pkt = min_t(int, dword_length, ring->space / sizeof(u32) + 5);
- pkt = min_t(int, pkt, (ring->size - ring->emit) / sizeof(u32) + 5);
+ pkt = max_pte_pkt_size(rq, dword_length);
hdr = cs;
*cs++ = MI_STORE_DATA_IMM | REG_BIT(21); /* as qword elements */
@@ -422,8 +431,7 @@ static int emit_pte(struct i915_request *rq,
}
}
- pkt = min_t(int, dword_rem, ring->space / sizeof(u32) +
5);
- pkt = min_t(int, pkt, (ring->size - ring->emit) /
sizeof(u32) + 5);
+ pkt = max_pte_pkt_size(rq, dword_rem);
hdr = cs;
*cs++ = MI_STORE_DATA_IMM | REG_BIT(21);
--
2.38.1
[Intel-gfx] [PATCH 2/2] drm/i915/selftests: exercise emit_pte() with nearly full ring
Simple regression test to check that we don't trample the
rq->reserved_space when returning from emit_pte(), if the ring is nearly
full.
References: https://gitlab.freedesktop.org/drm/intel/-/issues/7535
References: https://gitlab.freedesktop.org/drm/intel/-/issues/6889
Signed-off-by: Matthew Auld
Cc: Chris Wilson
Cc: Andrzej Hajda
Cc: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_migrate.c| 6 +-
drivers/gpu/drm/i915/gt/selftest_migrate.c | 153 +
2 files changed, 157 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 48c3b5168558..6df728b82a73 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -352,6 +352,8 @@ static int max_pte_pkt_size(struct i915_request *rq, int
pkt)
return pkt;
}
+#define I915_EMIT_PTE_NUM_DWORDS 6
+
static int emit_pte(struct i915_request *rq,
struct sgt_dma *it,
enum i915_cache_level cache_level,
@@ -393,7 +395,7 @@ static int emit_pte(struct i915_request *rq,
offset += (u64)rq->engine->instance << 32;
- cs = intel_ring_begin(rq, 6);
+ cs = intel_ring_begin(rq, I915_EMIT_PTE_NUM_DWORDS);
if (IS_ERR(cs))
return PTR_ERR(cs);
@@ -416,7 +418,7 @@ static int emit_pte(struct i915_request *rq,
intel_ring_advance(rq, cs);
intel_ring_update_space(ring);
- cs = intel_ring_begin(rq, 6);
+ cs = intel_ring_begin(rq, I915_EMIT_PTE_NUM_DWORDS);
if (IS_ERR(cs))
return PTR_ERR(cs);
diff --git a/drivers/gpu/drm/i915/gt/selftest_migrate.c
b/drivers/gpu/drm/i915/gt/selftest_migrate.c
index 0dc5309c90a4..fc469dbcbc41 100644
--- a/drivers/gpu/drm/i915/gt/selftest_migrate.c
+++ b/drivers/gpu/drm/i915/gt/selftest_migrate.c
@@ -8,6 +8,7 @@
#include "gem/i915_gem_internal.h"
#include "gem/i915_gem_lmem.h"
+#include "selftests/igt_spinner.h"
#include "selftests/i915_random.h"
static const unsigned int sizes[] = {
@@ -527,6 +528,157 @@ static int live_migrate_clear(void *arg)
return 0;
}
+int spinner_kill(void *arg)
+{
+ struct igt_spinner *spin = arg;
+
+ msleep(2000); /* Should be plenty */
+ igt_spinner_end(spin);
+ return 0;
+}
+
+static int live_emit_pte_full_ring(void *arg)
+{
+ struct intel_migrate *migrate = arg;
+ struct drm_i915_private *i915 = migrate->context->engine->i915;
+ struct drm_i915_gem_object *obj;
+ struct intel_context *ce;
+ struct i915_request *rq, *prev;
+ struct igt_spinner spin;
+ struct task_struct *tsk = NULL;
+ struct sgt_dma it;
+ int len, sz, err;
+ int status;
+ u32 *cs;
+
+ /*
+* Simple regression test to check that we don't trample the
+* rq->reserved_space when returning from emit_pte(), if the ring is
+* nearly full.
+*/
+
+ if (igt_spinner_init(, to_gt(i915)))
+ return -ENOMEM;
+
+ obj = i915_gem_object_create_internal(i915, 2 * PAGE_SIZE);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ goto out_spinner;
+ }
+
+ err = i915_gem_object_pin_pages_unlocked(obj);
+ if (err)
+ goto out_obj;
+
+ ce = intel_migrate_create_context(migrate);
+ if (IS_ERR(ce)) {
+ err = PTR_ERR(ce);
+ goto out_obj;
+ }
+
+ ce->ring_size = SZ_4K; /* Not too big */
+
+ err = intel_context_pin(ce);
+ if (err)
+ goto out_put;
+
+ rq = igt_spinner_create_request(, ce, MI_ARB_CHECK);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_unpin;
+ }
+
+ i915_request_add(rq);
+ if (!igt_wait_for_spinner(, rq)) {
+ GEM_TRACE("spinner failed to start\n");
+ err = -EIO;
+ goto out_unpin;
+ }
+
+ /*
+* Fill the ring leaving I915_EMIT_PTE_NUM_DWORDS + ring->reserved_space
+* at the end. To actually emit the PTEs we require slightly more than
+* I915_EMIT_PTE_NUM_DWORDS, since our object size is greater than
+* PAGE_SIZE. The correct behaviour is to wait for more ring space in
+* emit_pte(), otherwise we trample on the reserved_space resulting in
+* crashes when later submitting the rq.
+*/
+
+ prev = NULL;
+ do {
+ if (prev)
+ i915_request_add(rq);
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_unpin;
+ }
+
+ sz = (rq->ring->space - rq->reserved_space) / sizeof(u32) -
+ I915_EMIT_PTE_NUM_DWORDS;
+ sz =
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix workarounds on Gen2-3
== Series Details ==
Series: drm/i915: Fix workarounds on Gen2-3
URL : https://patchwork.freedesktop.org/series/111067/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12398 -> Patchwork_111067v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111067v1/index.html
Participating hosts (41 -> 38)
--
Additional (1): bat-rpls-1
Missing(4): fi-ctg-p8600 fi-ilk-m540 fi-bdw-samus bat-dg1-6
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_111067v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-2:
- {bat-rpls-1}: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111067v1/bat-rpls-1/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-dp-2.html
Known issues
Here are the changes found in Patchwork_111067v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3
similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111067v1/fi-apl-guc/igt@gem_lmem_swapp...@basic.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-apl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111067v1/fi-apl-guc/igt@kms_chamel...@common-hpd-after-suspend.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-apl-guc: [INCOMPLETE][4] ([i915#7073]) -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111067v1/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html
*
igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka: [FAIL][6] ([i915#6298]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111067v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#7073]: https://gitlab.freedesktop.org/drm/intel/issues/7073
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
Build changes
-
* Linux: CI_DRM_12398 -> Patchwork_111067v1
CI-20190529: 20190529
CI_DRM_12398: 6ff9396457d55a1915566b11121e8fe6f9068b1c @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7068: 5c0ec905b6bbecfb8df8b8f3315d0470539e6ae3 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111067v1: 6ff9396457d55a1915566b11121e8fe6f9068b1c @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
6d14a386ece3 drm/i915: Fix workarounds on Gen2-3
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111067v1/index.html
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915/mtl: limit second scaler vertical scaling in ver >= 14
== Series Details == Series: series starting with [1/2] drm/i915/mtl: limit second scaler vertical scaling in ver >= 14 URL : https://patchwork.freedesktop.org/series/111069/ State : failure == Summary == Error: make failed CALLscripts/checksyscalls.sh DESCEND objtool CC [M] drivers/gpu/drm/i915/display/intel_atomic_plane.o drivers/gpu/drm/i915/display/intel_atomic_plane.c: In function ‘intel_atomic_plane_check_clipping’: drivers/gpu/drm/i915/display/intel_atomic_plane.c:926:16: error: ‘DRM_PLANE_HELPER_NO_SCALING’ undeclared (first use in this function); did you mean ‘DRM_PLANE_NO_SCALING’? min_hscale = DRM_PLANE_HELPER_NO_SCALING; ^~~ DRM_PLANE_NO_SCALING drivers/gpu/drm/i915/display/intel_atomic_plane.c:926:16: note: each undeclared identifier is reported only once for each function it appears in scripts/Makefile.build:250: recipe for target 'drivers/gpu/drm/i915/display/intel_atomic_plane.o' failed make[5]: *** [drivers/gpu/drm/i915/display/intel_atomic_plane.o] Error 1 scripts/Makefile.build:500: recipe for target 'drivers/gpu/drm/i915' failed make[4]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:500: recipe for target 'drivers/gpu/drm' failed make[3]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:500: recipe for target 'drivers/gpu' failed make[2]: *** [drivers/gpu] Error 2 scripts/Makefile.build:500: recipe for target 'drivers' failed make[1]: *** [drivers] Error 2 Makefile:1992: recipe for target '.' failed make: *** [.] Error 2
[Intel-gfx] ✗ Fi.CI.IGT: failure for Fix live busy stats selftest failure (rev3)
== Series Details == Series: Fix live busy stats selftest failure (rev3) URL : https://patchwork.freedesktop.org/series/110557/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12396_full -> Patchwork_110557v3_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_110557v3_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_110557v3_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 11) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_110557v3_full: ### IGT changes ### Possible regressions * igt@i915_module_load@reload-with-fault-injection: - shard-snb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-snb6/igt@i915_module_l...@reload-with-fault-injection.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110557v3/shard-snb7/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_selftest@live@evict: - shard-skl: NOTRUN -> [INCOMPLETE][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110557v3/shard-skl4/igt@i915_selftest@l...@evict.html * igt@kms_cursor_crc@cursor-alpha-transparent@pipe-d-edp-1: - shard-tglb: [PASS][4] -> [INCOMPLETE][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-tglb8/igt@kms_cursor_crc@cursor-alpha-transpar...@pipe-d-edp-1.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110557v3/shard-tglb8/igt@kms_cursor_crc@cursor-alpha-transpar...@pipe-d-edp-1.html Known issues Here are the changes found in Patchwork_110557v3_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-glk: ([PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30]) -> ([PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [FAIL][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55]) ([i915#4392]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk1/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk9/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk8/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk8/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk8/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk7/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk7/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk7/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk6/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk6/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk6/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk5/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk5/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk5/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk3/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk3/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk3/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk2/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk2/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk2/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk1/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk1/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk9/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk9/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk9/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110557v3/shard-glk5/boot.html [32]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix workarounds on Gen2-3
== Series Details ==
Series: drm/i915: Fix workarounds on Gen2-3
URL : https://patchwork.freedesktop.org/series/111067/
State : warning
== Summary ==
Error: dim checkpatch failed
dc0ad34ead34 drm/i915: Fix workarounds on Gen2-3
-:9: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 3653727560d0 ("drm/i915:
Simplify internal helper function signature")'
#9:
In 3653727560d0 ("drm/i915: Simplify internal helper function signature")
total: 1 errors, 0 warnings, 0 checks, 17 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dvo: DVO init fixes/cleanps
== Series Details ==
Series: drm/i915/dvo: DVO init fixes/cleanps
URL : https://patchwork.freedesktop.org/series/111066/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12398 -> Patchwork_111066v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/index.html
Participating hosts (41 -> 40)
--
Additional (2): bat-rpls-1 fi-rkl-11600
Missing(3): fi-ctg-p8600 fi-ilk-m540 fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_111066v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-2:
- {bat-rpls-1}: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/bat-rpls-1/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-dp-2.html
Known issues
Here are the changes found in Patchwork_111066v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@basic-hwmon:
- fi-rkl-11600: NOTRUN -> [SKIP][2] ([i915#7456])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/fi-rkl-11600/igt@debugfs_t...@basic-hwmon.html
* igt@gem_huc_copy@huc-copy:
- fi-rkl-11600: NOTRUN -> [SKIP][3] ([i915#2190])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3
similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/fi-apl-guc/igt@gem_lmem_swapp...@basic.html
- fi-rkl-11600: NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/fi-rkl-11600/igt@gem_lmem_swapp...@basic.html
* igt@gem_tiled_pread_basic:
- fi-rkl-11600: NOTRUN -> [SKIP][6] ([i915#3282])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- fi-rkl-11600: NOTRUN -> [SKIP][7] ([i915#7561])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@mman:
- fi-rkl-guc: [PASS][8] -> [TIMEOUT][9] ([i915#6794])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/fi-rkl-guc/igt@i915_selftest@l...@mman.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/fi-rkl-guc/igt@i915_selftest@l...@mman.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: NOTRUN -> [INCOMPLETE][10] ([i915#4817])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-apl-guc: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/fi-apl-guc/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-rkl-11600: NOTRUN -> [SKIP][12] ([fdo#111827]) +7 similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/fi-rkl-11600/igt@kms_chamel...@hdmi-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-rkl-11600: NOTRUN -> [SKIP][13] ([i915#4103])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/fi-rkl-11600/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-rkl-11600: NOTRUN -> [SKIP][14] ([fdo#109285] / [i915#4098])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/fi-rkl-11600/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_psr@primary_page_flip:
- fi-rkl-11600: NOTRUN -> [SKIP][15] ([i915#1072]) +3 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/fi-rkl-11600/igt@kms_psr@primary_page_flip.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-rkl-11600: NOTRUN -> [SKIP][16] ([i915#3555] / [i915#4098])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/fi-rkl-11600/igt@kms_setm...@basic-clone-single-crtc.html
* igt@prime_vgem@basic-read:
- fi-rkl-11600: NOTRUN -> [SKIP][17] ([fdo#109295] / [i915#3291] /
[i915#3708]) +2 similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111066v1/fi-rkl-11600/igt@prime_v...@basic-read.html
* igt@prime_vgem@basic-userptr:
- fi-rkl-11600: NOTRUN -> [SKIP][18] ([fdo#109295] / [i915#3301] /
[i915#3708])
[18]:
[Intel-gfx] [PATCH 2/2] drm/i915/mtl: Limit scaler input to 4k in plane scaling
From: Animesh Manna
As part of die area reduction max input source modified to 4096
for MTL so modified range check logic of scaler.
Signed-off-by: José Roberto de Souza
Signed-off-by: Animesh Manna
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/display/skl_scaler.c | 31 +--
1 file changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c
b/drivers/gpu/drm/i915/display/skl_scaler.c
index d7390067b7d4..6baa07142b03 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -103,6 +103,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool
force_detach,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
const struct drm_display_mode *adjusted_mode =
_state->hw.adjusted_mode;
+ int min_src_w, min_src_h, min_dst_w, min_dst_h;
+ int max_src_w, max_src_h, max_dst_w, max_dst_h;
/*
* Src coordinates are already rotated by 270 degrees for
@@ -157,15 +159,28 @@ skl_update_scaler(struct intel_crtc_state *crtc_state,
bool force_detach,
return -EINVAL;
}
+ min_src_w = SKL_MIN_SRC_W;
+ min_src_h = SKL_MIN_SRC_H;
+ min_dst_w = SKL_MIN_DST_W;
+ min_dst_h = SKL_MIN_DST_H;
+
+ if (DISPLAY_VER(dev_priv) >= 11 && DISPLAY_VER(dev_priv) < 14) {
+ max_src_w = ICL_MAX_SRC_W;
+ max_src_h = ICL_MAX_SRC_H;
+ max_dst_w = ICL_MAX_DST_W;
+ max_dst_h = ICL_MAX_DST_H;
+ } else {
+ max_src_w = SKL_MAX_SRC_W;
+ max_src_h = SKL_MAX_SRC_H;
+ max_dst_w = SKL_MAX_DST_W;
+ max_dst_h = SKL_MAX_DST_H;
+ }
+
/* range checks */
- if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
- dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
- (DISPLAY_VER(dev_priv) >= 11 &&
-(src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
- dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
- (DISPLAY_VER(dev_priv) < 11 &&
-(src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
- dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
+ if (src_w < min_src_w || src_h < min_src_h ||
+ dst_w < min_dst_w || dst_h < min_dst_h ||
+ src_w > max_src_w || src_h > max_src_h ||
+ dst_w > max_dst_w || dst_h > max_dst_h) {
drm_dbg_kms(_priv->drm,
"scaler_user index %u.%u: src %ux%u dst %ux%u "
"size is out of scaler range\n",
--
2.37.2
[Intel-gfx] [PATCH 1/2] drm/i915/mtl: limit second scaler vertical scaling in ver >= 14
In newer hardware versions (i.e. display version >= 14), the second
scaler doesn't support vertical scaling.
The current implementation of the scaling limits is simplified and
only occurs when the planes are created, so we don't know which scaler
is being used.
In order to handle separate scaling limits for horizontal and vertical
scaling, and different limits per scaler, split the checks in two
phases. We first do a simple check during plane creation and use the
best-case scenario (because we don't know the scaler that may be used
at a later point) and then do a more specific check when the scalers
are actually being set up.
Signed-off-by: Luca Coelho
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 4 +-
drivers/gpu/drm/i915/display/intel_atomic.c | 47 +++
.../gpu/drm/i915/display/intel_atomic_plane.c | 39 +--
.../gpu/drm/i915/display/intel_atomic_plane.h | 2 +-
drivers/gpu/drm/i915/display/intel_cursor.c | 4 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 19 ++--
.../drm/i915/display/skl_universal_plane.c| 26 ++
7 files changed, 91 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index ecaeb7dc196b..390e96f0692b 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -326,9 +326,7 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
- DRM_PLANE_NO_SCALING,
- DRM_PLANE_NO_SCALING,
+ ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, false,
i9xx_plane_has_windowing(plane));
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 6621aa245caf..43b1c7a227f8 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -38,6 +38,7 @@
#include "intel_atomic.h"
#include "intel_cdclk.h"
#include "intel_display_types.h"
+#include "intel_fb.h"
#include "intel_global_state.h"
#include "intel_hdcp.h"
#include "intel_psr.h"
@@ -375,6 +376,52 @@ static void intel_atomic_setup_scaler(struct
intel_crtc_scaler_state *scaler_sta
mode = SKL_PS_SCALER_MODE_DYN;
}
+ if (plane_state && plane_state->hw.fb) {
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ struct drm_rect *src = _state->uapi.src;
+ struct drm_rect *dst = _state->uapi.dst;
+ int hscale, vscale, max_vscale, max_hscale;
+
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ /*
+* On versions 14 and up, only the first
+* scaler supports a vertical scaling factor
+* of more than 1.0, while a horizontal
+* scaling factor of 3.0 is supported.
+*/
+ max_hscale = 0x3 - 1;
+ if (*scaler_id == 0)
+ max_vscale = 0x3 - 1;
+ else
+ max_vscale = 0x1;
+
+ } else if (DISPLAY_VER(dev_priv) >= 10 ||
+ !intel_format_info_is_yuv_semiplanar(fb->format,
fb->modifier)) {
+ max_hscale = 0x3 - 1;
+ max_vscale = 0x3 - 1;
+ } else {
+ max_hscale = 0x2 - 1;
+ max_vscale = 0x2 - 1;
+ }
+
+ /* Check if required scaling is within limits */
+ hscale = drm_rect_calc_hscale(src, dst, 1, max_hscale);
+ vscale = drm_rect_calc_vscale(src, dst, 1, max_vscale);
+
+ if (hscale < 0 || vscale < 0) {
+ drm_dbg_kms(_priv->drm,
+ "Scaler %d doesn't support required plane
scaling\n",
+ *scaler_id);
+ drm_rect_debug_print("src: ", src, true);
+ drm_rect_debug_print("dst: ", dst, false);
+
+ scaler_state->scalers[*scaler_id].in_use = 0;
+ *scaler_id = -1;
+
+ return;
+ }
+ }
+
drm_dbg_kms(_priv->drm, "Attached scaler id %u.%u to %s:%d\n",
intel_crtc->pipe, *scaler_id, name, idx);
scaler_state->scalers[*scaler_id].mode = mode;
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 10e1fc9d0698..9f50e6c98918 100644
---
[Intel-gfx] [PATCH] drm/i915: Fix workarounds on Gen2-3
From: Tvrtko Ursulin
In 3653727560d0 ("drm/i915: Simplify internal helper function signature")
I broke the old platforms by not noticing engine workaround init does not
initialize the list on old platforms. Fix it by always initializing which
already does the right thing by mostly not doing anything if there aren't
any workarounds on the list.
Signed-off-by: Tvrtko Ursulin
Fixes: 3653727560d0 ("drm/i915: Simplify internal helper function signature")
Reported-by: Ville Syrjälä
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 213160f29ec3..4d7a01b45e09 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2991,7 +2991,7 @@ general_render_compute_wa_init(struct intel_engine_cs
*engine, struct i915_wa_li
static void
engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list
*wal)
{
- if (I915_SELFTEST_ONLY(GRAPHICS_VER(engine->i915) < 4))
+ if (GRAPHICS_VER(engine->i915) < 4)
return;
engine_fake_wa_init(engine, wal);
@@ -3016,9 +3016,6 @@ void intel_engine_init_workarounds(struct intel_engine_cs
*engine)
{
struct i915_wa_list *wal = >wa_list;
- if (GRAPHICS_VER(engine->i915) < 4)
- return;
-
wa_init_start(wal, engine->gt, "engine", engine->name);
engine_init_workarounds(engine, wal);
wa_init_finish(wal);
--
2.34.1
Re: [Intel-gfx] [PATCH v3] drm/i915/display: Don't disable DDI/Transcoder when setting phy test pattern
On Wed, 16 Nov 2022, Khaled Almahallawy wrote:
> Bspecs has updated recently to remove the restriction to disable
> DDI/Transcoder before setting PHY test pattern. This update is to
> address PHY compliance test failures observed on a port with LTTPR.
> The issue is that when Transc. is disabled, the main link signals fed
> to LTTPR will be dropped invalidating link training, which will affect
> the quality of the phy test pattern when the transcoder is enabled again.
>
> v2: Update commit message (Clint)
> v3: Add missing Signed-off in v2
Bspec 7555 for pre-gen12 still says "TRANS_CONF and TRANS_DDI_FUNC_CTL
must be disabled prior to enabling the test pattern."
All I have against that is your word [1], and it's not even recorded in
the commit message.
BR,
Jani.
[1]
https://lore.kernel.org/r/8f0e921300db2b6a36497773d4508892e1ea5a43.ca...@intel.com
>
> Bspec: 50482
> Cc: Imre Deak
> Cc: Clint Taylor
> CC: Jani Nikula
> Tested-by: Khaled Almahallawy
> Signed-off-by: Khaled Almahallawy
> Reviewed-by: Clint Taylor
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 59 -
> 1 file changed, 59 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 914161d7d122..16cf961b4d1a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3679,61 +3679,6 @@ static void intel_dp_phy_pattern_update(struct
> intel_dp *intel_dp,
> }
> }
>
> -static void
> -intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
> - const struct intel_crtc_state *crtc_state)
> -{
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - struct drm_device *dev = dig_port->base.base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
> - enum pipe pipe = crtc->pipe;
> - u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
> -
> - trans_ddi_func_ctl_value = intel_de_read(dev_priv,
> - TRANS_DDI_FUNC_CTL(pipe));
> - trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
> - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
> -
> - trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
> - TGL_TRANS_DDI_PORT_MASK);
> - trans_conf_value &= ~PIPECONF_ENABLE;
> - dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
> -
> - intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
> - intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
> -trans_ddi_func_ctl_value);
> - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
> -}
> -
> -static void
> -intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
> - const struct intel_crtc_state *crtc_state)
> -{
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - struct drm_device *dev = dig_port->base.base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - enum port port = dig_port->base.port;
> - struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
> - enum pipe pipe = crtc->pipe;
> - u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
> -
> - trans_ddi_func_ctl_value = intel_de_read(dev_priv,
> - TRANS_DDI_FUNC_CTL(pipe));
> - trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
> - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
> -
> - trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
> - TGL_TRANS_DDI_SELECT_PORT(port);
> - trans_conf_value |= PIPECONF_ENABLE;
> - dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
> -
> - intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
> - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
> - intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
> -trans_ddi_func_ctl_value);
> -}
> -
> static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
>const struct intel_crtc_state
> *crtc_state)
> {
> @@ -3752,14 +3697,10 @@ static void intel_dp_process_phy_request(struct
> intel_dp *intel_dp,
> intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
> link_status);
>
> - intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
> -
> intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
>
> intel_dp_phy_pattern_update(intel_dp, crtc_state);
>
> - intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
> -
> drm_dp_dpcd_write(_dp->aux, DP_TRAINING_LANE0_SET,
> intel_dp->train_set, crtc_state->lane_count);
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dvo: DVO init fixes/cleanps
== Series Details == Series: drm/i915/dvo: DVO init fixes/cleanps URL : https://patchwork.freedesktop.org/series/111066/ State : warning == Summary == Error: dim checkpatch failed 31ec571cb014 drm/i915/dvo: Remove unused panel_wants_dither c9da1e495ad7 drm/i915/dvo: Don't leak connector state on DVO init failure 59880e593787 drm/i915/dvo: Actually initialize the DVO encoder type 0625749326d5 drm/i915/dvo: Introduce intel_dvo_connector_type() 6c30df4f3b60 drm/i915/dvo: Eliminate useless 'port' variable a83da608cc24 drm/i915/dvo: Flatten intel_dvo_init() -:185: CHECK:CAMELCASE: Avoid CamelCase: #185: FILE: drivers/gpu/drm/i915/display/intel_dvo.c:555: + connector->display_info.subpixel_order = SubPixelHorizontalRGB; total: 0 errors, 0 warnings, 1 checks, 247 lines checked 8af7706c0d42 drm/i915/dvo: s/intel_encoder/encoder/ etc. -:182: CHECK:CAMELCASE: Avoid CamelCase: #182: FILE: drivers/gpu/drm/i915/display/intel_dvo.c:554: + connector->base.display_info.subpixel_order = SubPixelHorizontalRGB; total: 0 errors, 0 warnings, 1 checks, 177 lines checked f2d632893373 drm/i915/dvo: s/dev_priv/i915/ c103975f29ff drm/i915/dvo: Use per device debugs
Re: [Intel-gfx] [PATCH 0/9] drm/i915/dvo: DVO init fixes/cleanps
On Fri, 18 Nov 2022, Ville Syrjala wrote: > From: Ville Syrjälä > > The DVO encoder init code is meesy. Try to clean it > up a bit, and fix a few buglets while at it. On the series, Reviewed-by: Jani Nikula > > Ville Syrjälä (9): > drm/i915/dvo: Remove unused panel_wants_dither > drm/i915/dvo: Don't leak connector state on DVO init failure > drm/i915/dvo: Actually initialize the DVO encoder type > drm/i915/dvo: Introduce intel_dvo_connector_type() > drm/i915/dvo: Eliminate useless 'port' variable > drm/i915/dvo: Flatten intel_dvo_init() > drm/i915/dvo: s/intel_encoder/encoder/ etc. > drm/i915/dvo: s/dev_priv/i915/ > drm/i915/dvo: Use per device debugs > > drivers/gpu/drm/i915/display/intel_dvo.c | 375 --- > 1 file changed, 201 insertions(+), 174 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Fix timeout handling when retiring requests (rev2)
== Series Details == Series: drm/i915: Fix timeout handling when retiring requests (rev2) URL : https://patchwork.freedesktop.org/series/110964/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12398 -> Patchwork_110964v2 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_110964v2 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_110964v2, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/index.html Participating hosts (41 -> 39) -- Additional (1): fi-rkl-11600 Missing(3): fi-ctg-p8600 fi-ilk-m540 fi-bdw-samus Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_110964v2: ### IGT changes ### Possible regressions * igt@i915_pm_backlight@basic-brightness: - fi-rkl-11600: NOTRUN -> [SKIP][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html Known issues Here are the changes found in Patchwork_110964v2 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - fi-rkl-11600: NOTRUN -> [SKIP][2] ([i915#7456]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-rkl-11600: NOTRUN -> [SKIP][3] ([i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-apl-guc: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-apl-guc/igt@gem_lmem_swapp...@basic.html - fi-rkl-11600: NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@gem_lmem_swapp...@basic.html * igt@gem_tiled_pread_basic: - fi-rkl-11600: NOTRUN -> [SKIP][6] ([i915#3282]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@gem_tiled_pread_basic.html * igt@i915_selftest@live@gt_heartbeat: - fi-bxt-dsi: [PASS][7] -> [DMESG-FAIL][8] ([i915#5334]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12398/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_suspend@basic-s3-without-i915: - fi-rkl-11600: NOTRUN -> [INCOMPLETE][9] ([i915#4817]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-apl-guc: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-apl-guc/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-edid-read: - fi-rkl-11600: NOTRUN -> [SKIP][11] ([fdo#111827]) +7 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@kms_chamel...@hdmi-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor: - fi-rkl-11600: NOTRUN -> [SKIP][12] ([i915#4103]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html * igt@kms_force_connector_basic@force-load-detect: - fi-rkl-11600: NOTRUN -> [SKIP][13] ([fdo#109285] / [i915#4098]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_psr@primary_page_flip: - fi-rkl-11600: NOTRUN -> [SKIP][14] ([i915#1072]) +3 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@kms_psr@primary_page_flip.html * igt@kms_setmode@basic-clone-single-crtc: - fi-rkl-11600: NOTRUN -> [SKIP][15] ([i915#3555] / [i915#4098]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-read: - fi-rkl-11600: NOTRUN -> [SKIP][16] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110964v2/fi-rkl-11600/igt@prime_v...@basic-read.html * igt@prime_vgem@basic-userptr: - fi-rkl-11600: NOTRUN -> [SKIP][17] ([fdo#109295] / [i915#3301] / [i915#3708]) [17]:
[Intel-gfx] [PATCH 6/9] drm/i915/dvo: Flatten intel_dvo_init()
From: Ville Syrjälä
The loop over intel_dvo_devices[] makes intel_dvo_init()
an ugly mess. Pull the i2c device probe out to a separate
function so that we can get rid of the loop and flatten
the code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dvo.c | 229 ---
1 file changed, 123 insertions(+), 106 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c
b/drivers/gpu/drm/i915/display/intel_dvo.c
index 87ee913cf89b..bccbda50113c 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -415,12 +415,88 @@ static int intel_dvo_connector_type(const struct
intel_dvo_device *dvo)
}
}
+static bool intel_dvo_init_dev(struct drm_i915_private *dev_priv,
+ struct intel_dvo *intel_dvo,
+ const struct intel_dvo_device *dvo)
+{
+ struct i2c_adapter *i2c;
+ u32 dpll[I915_MAX_PIPES];
+ enum pipe pipe;
+ int gpio;
+ bool ret;
+
+ /*
+* Allow the I2C driver info to specify the GPIO to be used in
+* special cases, but otherwise default to what's defined
+* in the spec.
+*/
+ if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio))
+ gpio = dvo->gpio;
+ else if (dvo->type == INTEL_DVO_CHIP_LVDS)
+ gpio = GMBUS_PIN_SSC;
+ else
+ gpio = GMBUS_PIN_DPB;
+
+ /*
+* Set up the I2C bus necessary for the chip we're probing.
+* It appears that everything is on GPIOE except for panels
+* on i830 laptops, which are on GPIOB (DVOA).
+*/
+ i2c = intel_gmbus_get_adapter(dev_priv, gpio);
+
+ intel_dvo->dev = *dvo;
+
+ /*
+* GMBUS NAK handling seems to be unstable, hence let the
+* transmitter detection run in bit banging mode for now.
+*/
+ intel_gmbus_force_bit(i2c, true);
+
+ /*
+* ns2501 requires the DVO 2x clock before it will
+* respond to i2c accesses, so make sure we have
+* the clock enabled before we attempt to initialize
+* the device.
+*/
+ for_each_pipe(dev_priv, pipe) {
+ dpll[pipe] = intel_de_read(dev_priv, DPLL(pipe));
+ intel_de_write(dev_priv, DPLL(pipe),
+ dpll[pipe] | DPLL_DVO_2X_MODE);
+ }
+
+ ret = dvo->dev_ops->init(_dvo->dev, i2c);
+
+ /* restore the DVO 2x clock state to original */
+ for_each_pipe(dev_priv, pipe) {
+ intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]);
+ }
+
+ intel_gmbus_force_bit(i2c, false);
+
+ return ret;
+}
+
+static bool intel_dvo_probe(struct drm_i915_private *dev_priv,
+ struct intel_dvo *intel_dvo)
+{
+ int i;
+
+ /* Now, try to find a controller */
+ for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) {
+ if (intel_dvo_init_dev(dev_priv, intel_dvo,
+ _dvo_devices[i]))
+ return true;
+ }
+
+ return false;
+}
+
void intel_dvo_init(struct drm_i915_private *dev_priv)
{
struct intel_encoder *intel_encoder;
struct intel_dvo *intel_dvo;
struct intel_connector *intel_connector;
- int i;
+ struct drm_connector *connector;
intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL);
if (!intel_dvo)
@@ -432,6 +508,8 @@ void intel_dvo_init(struct drm_i915_private *dev_priv)
return;
}
+ connector = _connector->base;
+
intel_dvo->attached_connector = intel_connector;
intel_encoder = _dvo->base;
@@ -444,112 +522,51 @@ void intel_dvo_init(struct drm_i915_private *dev_priv)
intel_encoder->pre_enable = intel_dvo_pre_enable;
intel_connector->get_hw_state = intel_dvo_connector_get_hw_state;
- /* Now, try to find a controller */
- for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) {
- struct drm_connector *connector = _connector->base;
- const struct intel_dvo_device *dvo = _dvo_devices[i];
- struct i2c_adapter *i2c;
- int gpio;
- bool dvoinit;
- enum pipe pipe;
- u32 dpll[I915_MAX_PIPES];
-
- /*
-* Allow the I2C driver info to specify the GPIO to be used in
-* special cases, but otherwise default to what's defined
-* in the spec.
-*/
- if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio))
- gpio = dvo->gpio;
- else if (dvo->type == INTEL_DVO_CHIP_LVDS)
- gpio = GMBUS_PIN_SSC;
- else
- gpio = GMBUS_PIN_DPB;
-
- /*
-* Set up the I2C bus necessary for the chip we're probing.
-* It appears that
[Intel-gfx] [PATCH 4/9] drm/i915/dvo: Introduce intel_dvo_connector_type()
From: Ville Syrjälä
Introduce intel_dvo_connector_type() as a counterpart to
intel_dvo_encoder_type(), mainly to declutter intel_dvo_init()
a bit.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dvo.c | 32 ++--
1 file changed, 19 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c
b/drivers/gpu/drm/i915/display/intel_dvo.c
index fe61cb41d83b..9ce3b4ec6a4d 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -401,6 +401,20 @@ static int intel_dvo_encoder_type(const struct
intel_dvo_device *dvo)
}
}
+static int intel_dvo_connector_type(const struct intel_dvo_device *dvo)
+{
+ switch (dvo->type) {
+ case INTEL_DVO_CHIP_TMDS:
+ return DRM_MODE_CONNECTOR_DVII;
+ case INTEL_DVO_CHIP_LVDS_NO_FIXED:
+ case INTEL_DVO_CHIP_LVDS:
+ return DRM_MODE_CONNECTOR_LVDS;
+ default:
+ MISSING_CASE(dvo->type);
+ return DRM_MODE_CONNECTOR_Unknown;
+ }
+}
+
void intel_dvo_init(struct drm_i915_private *dev_priv)
{
struct intel_encoder *intel_encoder;
@@ -507,21 +521,13 @@ void intel_dvo_init(struct drm_i915_private *dev_priv)
intel_encoder->cloneable = BIT(INTEL_OUTPUT_ANALOG) |
BIT(INTEL_OUTPUT_DVO);
- switch (dvo->type) {
- case INTEL_DVO_CHIP_TMDS:
+ if (dvo->type == INTEL_DVO_CHIP_TMDS)
intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT |
DRM_CONNECTOR_POLL_DISCONNECT;
- drm_connector_init(_priv->drm, connector,
- _dvo_connector_funcs,
- DRM_MODE_CONNECTOR_DVII);
- break;
- case INTEL_DVO_CHIP_LVDS_NO_FIXED:
- case INTEL_DVO_CHIP_LVDS:
- drm_connector_init(_priv->drm, connector,
- _dvo_connector_funcs,
- DRM_MODE_CONNECTOR_LVDS);
- break;
- }
+
+ drm_connector_init(_priv->drm, connector,
+ _dvo_connector_funcs,
+ intel_dvo_connector_type(dvo));
drm_connector_helper_add(connector,
_dvo_connector_helper_funcs);
--
2.37.4
[Intel-gfx] [PATCH 5/9] drm/i915/dvo: Eliminate useless 'port' variable
From: Ville Syrjälä Reorder the drm_encoder_init() vs. encoder->port assignment so that we don't need the extra 'port' variable. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dvo.c | 14 ++ 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c index 9ce3b4ec6a4d..87ee913cf89b 100644 --- a/drivers/gpu/drm/i915/display/intel_dvo.c +++ b/drivers/gpu/drm/i915/display/intel_dvo.c @@ -453,7 +453,6 @@ void intel_dvo_init(struct drm_i915_private *dev_priv) bool dvoinit; enum pipe pipe; u32 dpll[I915_MAX_PIPES]; - enum port port; /* * Allow the I2C driver info to specify the GPIO to be used in @@ -506,21 +505,20 @@ void intel_dvo_init(struct drm_i915_private *dev_priv) if (!dvoinit) continue; - port = intel_dvo_port(dvo->dvo_reg); - drm_encoder_init(_priv->drm, _encoder->base, -_dvo_enc_funcs, -intel_dvo_encoder_type(dvo), -"DVO %c", port_name(port)); - intel_encoder->type = INTEL_OUTPUT_DVO; intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; - intel_encoder->port = port; + intel_encoder->port = intel_dvo_port(dvo->dvo_reg); intel_encoder->pipe_mask = ~0; if (dvo->type != INTEL_DVO_CHIP_LVDS) intel_encoder->cloneable = BIT(INTEL_OUTPUT_ANALOG) | BIT(INTEL_OUTPUT_DVO); + drm_encoder_init(_priv->drm, _encoder->base, +_dvo_enc_funcs, +intel_dvo_encoder_type(dvo), +"DVO %c", port_name(intel_encoder->port)); + if (dvo->type == INTEL_DVO_CHIP_TMDS) intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; -- 2.37.4
[Intel-gfx] [PATCH 3/9] drm/i915/dvo: Actually initialize the DVO encoder type
From: Ville Syrjälä
We call drm_encoder_init() before determining the correct
encoder type, thus we always end up with DRM_MODE_ENCODER_NONE.
Determine the correct encoder type earlier.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dvo.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c
b/drivers/gpu/drm/i915/display/intel_dvo.c
index 8859e400b860..fe61cb41d83b 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -387,13 +387,26 @@ static enum port intel_dvo_port(i915_reg_t dvo_reg)
return PORT_C;
}
+static int intel_dvo_encoder_type(const struct intel_dvo_device *dvo)
+{
+ switch (dvo->type) {
+ case INTEL_DVO_CHIP_TMDS:
+ return DRM_MODE_ENCODER_TMDS;
+ case INTEL_DVO_CHIP_LVDS_NO_FIXED:
+ case INTEL_DVO_CHIP_LVDS:
+ return DRM_MODE_ENCODER_LVDS;
+ default:
+ MISSING_CASE(dvo->type);
+ return DRM_MODE_ENCODER_NONE;
+ }
+}
+
void intel_dvo_init(struct drm_i915_private *dev_priv)
{
struct intel_encoder *intel_encoder;
struct intel_dvo *intel_dvo;
struct intel_connector *intel_connector;
int i;
- int encoder_type = DRM_MODE_ENCODER_NONE;
intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL);
if (!intel_dvo)
@@ -481,7 +494,8 @@ void intel_dvo_init(struct drm_i915_private *dev_priv)
port = intel_dvo_port(dvo->dvo_reg);
drm_encoder_init(_priv->drm, _encoder->base,
-_dvo_enc_funcs, encoder_type,
+_dvo_enc_funcs,
+intel_dvo_encoder_type(dvo),
"DVO %c", port_name(port));
intel_encoder->type = INTEL_OUTPUT_DVO;
@@ -500,14 +514,12 @@ void intel_dvo_init(struct drm_i915_private *dev_priv)
drm_connector_init(_priv->drm, connector,
_dvo_connector_funcs,
DRM_MODE_CONNECTOR_DVII);
- encoder_type = DRM_MODE_ENCODER_TMDS;
break;
case INTEL_DVO_CHIP_LVDS_NO_FIXED:
case INTEL_DVO_CHIP_LVDS:
drm_connector_init(_priv->drm, connector,
_dvo_connector_funcs,
DRM_MODE_CONNECTOR_LVDS);
- encoder_type = DRM_MODE_ENCODER_LVDS;
break;
}
--
2.37.4
[Intel-gfx] [PATCH 8/9] drm/i915/dvo: s/dev_priv/i915/
From: Ville Syrjälä
Follow the modern style and rename most 'dev_priv' variables
to 'i915'.
intel_dvo_init_dev() is the sole exception since it needs the
magic 'dev_priv' variable for the DPLL register macros.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dvo.c | 53
1 file changed, 26 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c
b/drivers/gpu/drm/i915/display/intel_dvo.c
index d078cf0d9765..9462b66e5fb4 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -132,12 +132,11 @@ static struct intel_dvo *intel_attached_dvo(struct
intel_connector *connector)
static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
{
- struct drm_device *dev = connector->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
u32 tmp;
- tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg);
+ tmp = intel_de_read(i915, intel_dvo->dev.dvo_reg);
if (!(tmp & DVO_ENABLE))
return false;
@@ -148,11 +147,11 @@ static bool intel_dvo_connector_get_hw_state(struct
intel_connector *connector)
static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
enum pipe *pipe)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
u32 tmp;
- tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg);
+ tmp = intel_de_read(i915, intel_dvo->dev.dvo_reg);
*pipe = (tmp & DVO_PIPE_SEL_MASK) >> DVO_PIPE_SEL_SHIFT;
@@ -162,13 +161,13 @@ static bool intel_dvo_get_hw_state(struct intel_encoder
*encoder,
static void intel_dvo_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
u32 tmp, flags = 0;
pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO);
- tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg);
+ tmp = intel_de_read(i915, intel_dvo->dev.dvo_reg);
if (tmp & DVO_HSYNC_ACTIVE_HIGH)
flags |= DRM_MODE_FLAG_PHSYNC;
else
@@ -188,14 +187,14 @@ static void intel_disable_dvo(struct intel_atomic_state
*state,
const struct intel_crtc_state *old_crtc_state,
const struct drm_connector_state *old_conn_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
- u32 temp = intel_de_read(dev_priv, dvo_reg);
+ u32 temp = intel_de_read(i915, dvo_reg);
intel_dvo->dev.dev_ops->dpms(_dvo->dev, false);
- intel_de_write(dev_priv, dvo_reg, temp & ~DVO_ENABLE);
- intel_de_read(dev_priv, dvo_reg);
+ intel_de_write(i915, dvo_reg, temp & ~DVO_ENABLE);
+ intel_de_read(i915, dvo_reg);
}
static void intel_enable_dvo(struct intel_atomic_state *state,
@@ -203,17 +202,17 @@ static void intel_enable_dvo(struct intel_atomic_state
*state,
const struct intel_crtc_state *pipe_config,
const struct drm_connector_state *conn_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
- u32 temp = intel_de_read(dev_priv, dvo_reg);
+ u32 temp = intel_de_read(i915, dvo_reg);
intel_dvo->dev.dev_ops->mode_set(_dvo->dev,
_config->hw.mode,
_config->hw.adjusted_mode);
- intel_de_write(dev_priv, dvo_reg, temp | DVO_ENABLE);
- intel_de_read(dev_priv, dvo_reg);
+ intel_de_write(i915, dvo_reg, temp | DVO_ENABLE);
+ intel_de_read(i915, dvo_reg);
intel_dvo->dev.dev_ops->dpms(_dvo->dev, true);
}
@@ -287,7 +286,7 @@ static void intel_dvo_pre_enable(struct intel_atomic_state
*state,
const struct intel_crtc_state *pipe_config,
const struct drm_connector_state *conn_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct
[Intel-gfx] [PATCH 9/9] drm/i915/dvo: Use per device debugs
From: Ville Syrjälä
Convert the lonely DRM_DEBUG_KMS() to the per-device variant.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dvo.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c
b/drivers/gpu/drm/i915/display/intel_dvo.c
index 9462b66e5fb4..575cb920bd43 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -320,8 +320,8 @@ intel_dvo_detect(struct drm_connector *_connector, bool
force)
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
- DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
- connector->base.base.id, connector->base.name);
+ drm_dbg_kms(>drm, "[CONNECTOR:%d:%s]\n",
+ connector->base.base.id, connector->base.name);
if (!INTEL_DISPLAY_ENABLED(i915))
return connector_status_disconnected;
--
2.37.4
[Intel-gfx] [PATCH 7/9] drm/i915/dvo: s/intel_encoder/encoder/ etc.
From: Ville Syrjälä
Remove the pointless intel_ namespace from our encoder/connector
variables.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dvo.c | 91
1 file changed, 45 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c
b/drivers/gpu/drm/i915/display/intel_dvo.c
index bccbda50113c..d078cf0d9765 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -219,14 +219,14 @@ static void intel_enable_dvo(struct intel_atomic_state
*state,
}
static enum drm_mode_status
-intel_dvo_mode_valid(struct drm_connector *connector,
+intel_dvo_mode_valid(struct drm_connector *_connector,
struct drm_display_mode *mode)
{
- struct intel_connector *intel_connector = to_intel_connector(connector);
- struct intel_dvo *intel_dvo = intel_attached_dvo(intel_connector);
+ struct intel_connector *connector = to_intel_connector(_connector);
+ struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
const struct drm_display_mode *fixed_mode =
- intel_panel_fixed_mode(intel_connector, mode);
- int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+ intel_panel_fixed_mode(connector, mode);
+ int max_dotclk = to_i915(connector->base.dev)->max_dotclk_freq;
int target_clock = mode->clock;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
@@ -237,7 +237,7 @@ intel_dvo_mode_valid(struct drm_connector *connector,
if (fixed_mode) {
enum drm_mode_status status;
- status = intel_panel_mode_valid(intel_connector, mode);
+ status = intel_panel_mode_valid(connector, mode);
if (status != MODE_OK)
return status;
@@ -315,13 +315,14 @@ static void intel_dvo_pre_enable(struct
intel_atomic_state *state,
}
static enum drm_connector_status
-intel_dvo_detect(struct drm_connector *connector, bool force)
+intel_dvo_detect(struct drm_connector *_connector, bool force)
{
- struct drm_i915_private *i915 = to_i915(connector->dev);
- struct intel_dvo *intel_dvo =
intel_attached_dvo(to_intel_connector(connector));
+ struct intel_connector *connector = to_intel_connector(_connector);
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
- connector->base.id, connector->name);
+ connector->base.base.id, connector->base.name);
if (!INTEL_DISPLAY_ENABLED(i915))
return connector_status_disconnected;
@@ -329,9 +330,10 @@ intel_dvo_detect(struct drm_connector *connector, bool
force)
return intel_dvo->dev.dev_ops->detect(_dvo->dev);
}
-static int intel_dvo_get_modes(struct drm_connector *connector)
+static int intel_dvo_get_modes(struct drm_connector *_connector)
{
- struct drm_i915_private *dev_priv = to_i915(connector->dev);
+ struct intel_connector *connector = to_intel_connector(_connector);
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
int num_modes;
/*
@@ -340,12 +342,12 @@ static int intel_dvo_get_modes(struct drm_connector
*connector)
* (TV-out, for example), but for now with just TMDS and LVDS,
* that's not the case.
*/
- num_modes = intel_ddc_get_modes(connector,
+ num_modes = intel_ddc_get_modes(>base,
intel_gmbus_get_adapter(dev_priv,
GMBUS_PIN_DPC));
if (num_modes)
return num_modes;
- return intel_panel_get_modes(to_intel_connector(connector));
+ return intel_panel_get_modes(connector);
}
static const struct drm_connector_funcs intel_dvo_connector_funcs = {
@@ -493,68 +495,66 @@ static bool intel_dvo_probe(struct drm_i915_private
*dev_priv,
void intel_dvo_init(struct drm_i915_private *dev_priv)
{
- struct intel_encoder *intel_encoder;
+ struct intel_connector *connector;
+ struct intel_encoder *encoder;
struct intel_dvo *intel_dvo;
- struct intel_connector *intel_connector;
- struct drm_connector *connector;
intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL);
if (!intel_dvo)
return;
- intel_connector = intel_connector_alloc();
- if (!intel_connector) {
+ connector = intel_connector_alloc();
+ if (!connector) {
kfree(intel_dvo);
return;
}
- connector = _connector->base;
+ intel_dvo->attached_connector = connector;
- intel_dvo->attached_connector = intel_connector;
+ encoder = _dvo->base;
- intel_encoder = _dvo->base;
-
- intel_encoder->disable = intel_disable_dvo;
- intel_encoder->enable = intel_enable_dvo;
-
[Intel-gfx] [PATCH 2/9] drm/i915/dvo: Don't leak connector state on DVO init failure
From: Ville Syrjälä If we can't initialize the DVO encoder also free the connector state allocated by intel_connector_alloc(). Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dvo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c index 94dcc43876c9..8859e400b860 100644 --- a/drivers/gpu/drm/i915/display/intel_dvo.c +++ b/drivers/gpu/drm/i915/display/intel_dvo.c @@ -535,5 +535,5 @@ void intel_dvo_init(struct drm_i915_private *dev_priv) } kfree(intel_dvo); - kfree(intel_connector); + intel_connector_free(intel_connector); } -- 2.37.4
[Intel-gfx] [PATCH 1/9] drm/i915/dvo: Remove unused panel_wants_dither
From: Ville Syrjälä
intel_dvo.panel_wants_dither is only set but never used.
We can't do dithering on the gmch side anyway since the
dithering logic is part of the integrated LVDS port and
not available for other output types.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dvo.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c
b/drivers/gpu/drm/i915/display/intel_dvo.c
index c86f9890754d..94dcc43876c9 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -118,8 +118,6 @@ struct intel_dvo {
struct intel_dvo_device dev;
struct intel_connector *attached_connector;
-
- bool panel_wants_dither;
};
static struct intel_dvo *enc_to_dvo(struct intel_encoder *encoder)
@@ -531,8 +529,6 @@ void intel_dvo_init(struct drm_i915_private *dev_priv)
intel_encoder);
intel_panel_init(intel_connector);
-
- intel_dvo->panel_wants_dither = true;
}
return;
--
2.37.4
[Intel-gfx] [PATCH 0/9] drm/i915/dvo: DVO init fixes/cleanps
From: Ville Syrjälä The DVO encoder init code is meesy. Try to clean it up a bit, and fix a few buglets while at it. Ville Syrjälä (9): drm/i915/dvo: Remove unused panel_wants_dither drm/i915/dvo: Don't leak connector state on DVO init failure drm/i915/dvo: Actually initialize the DVO encoder type drm/i915/dvo: Introduce intel_dvo_connector_type() drm/i915/dvo: Eliminate useless 'port' variable drm/i915/dvo: Flatten intel_dvo_init() drm/i915/dvo: s/intel_encoder/encoder/ etc. drm/i915/dvo: s/dev_priv/i915/ drm/i915/dvo: Use per device debugs drivers/gpu/drm/i915/display/intel_dvo.c | 375 --- 1 file changed, 201 insertions(+), 174 deletions(-) -- 2.37.4
Re: [Intel-gfx] [PATCH v2 0/5] Add module oriented dmesg output
On Thu, 17 Nov 2022, john.c.harri...@intel.com wrote: > From: John Harrison > > When trying to analyse bug reports from CI, customers, etc. it can be > difficult to work out exactly what is happening on which GT in a > multi-GT system. So add GT oriented debug/error message wrappers. If > used instead of the drm_ equivalents, you get the same output but with > a GT# prefix on it. > > It was also requested to extend this further to submodules in order to > factor out the repeated structure accessing constructs and common > string prefixes. So, add versions for GuC, HuC and GuC CTB as well. > > This patch set updates all the gt/uc files to use the new helpers as a > first step. The intention would be to convert all output messages that > have access to a GT structure. > > v2: Go back to using lower case names, add more wrapper sets (combined > review feedback). Also, wrap up probe injection and WARN entries. > > Signed-off-by: John Harrison For adding the wrappers in general, I'm going to disagree and commit. I'll leave it up to Tvrtko and Joonas. Regarding the placement of the macros, I insist you add individual header files for the wrappers and include them only where needed. We have a fairly serious problem with everything including everything in i915 that I've been slowly trying to tackle. Touch one thing, rebuild everything. About a third of our headers cause the rebuild of the entire driver when modified. We need to reduce the surface of things that cause rebuilds. For example, intel_gt.h is included by 97 files, intel_guc.h by 332 files, and intel_huc.h by 329 files (counting recursively). There's absolutely no reason any of the display code, for example, needs to have these logging macros in their build. Long term, the headers should be reorganized to reduce the interdependencies, and this is what I've been doing in i915_drv.h and display/ in general. But the least we can do is not make the problem worse. BR, Jani. > > > John Harrison (5): > drm/i915/gt: Start adding module oriented dmesg output > drm/i915/huc: Add HuC specific debug print wrappers > drm/i915/guc: Add GuC specific debug print wrappers > drm/i915/guc: Add GuC CT specific debug print wrappers > drm/i915/uc: Update the gt/uc code to use gt_err and friends > > drivers/gpu/drm/i915/gt/intel_gt.c| 96 > drivers/gpu/drm/i915/gt/intel_gt.h| 35 +++ > drivers/gpu/drm/i915/gt/uc/intel_guc.c| 32 +-- > drivers/gpu/drm/i915/gt/uc/intel_guc.h| 35 +++ > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 8 +- > .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 48 ++-- > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 222 +- > drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 19 +- > drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 37 ++- > drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 7 +- > drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 55 ++--- > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 62 +++-- > drivers/gpu/drm/i915/gt/uc/intel_huc.c| 31 +-- > drivers/gpu/drm/i915/gt/uc/intel_huc.h| 23 ++ > drivers/gpu/drm/i915/gt/uc/intel_uc.c | 108 - > drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 98 > drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 34 +-- > .../drm/i915/gt/uc/selftest_guc_hangcheck.c | 22 +- > .../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 10 +- > 19 files changed, 507 insertions(+), 475 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH v2 2/2] drm/i915: Never return 0 if not all requests retired
Users of intel_gt_retire_requests_timeout() expect 0 return value on
success. However, we have no protection from passing back 0 potentially
returned by a call to dma_fence_wait_timeout() when it succedes right
after its timeout has expired.
Replace 0 with -ETIME before potentially using the timeout value as return
code, so -ETIME is returned if there are still some requests not retired
after timeout, 0 otherwise.
v2: Move the added lines down so flush_submission() is not affected.
Fixes: f33a8a51602c ("drm/i915: Merge wait_for_timelines with retire_request")
Signed-off-by: Janusz Krzysztofik
Cc: sta...@vger.kernel.org # v5.5+
---
drivers/gpu/drm/i915/gt/intel_gt_requests.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
index edb881d756309..3ac4603eeb4ee 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
@@ -199,6 +199,9 @@ out_active: spin_lock(>lock);
if (remaining_timeout)
*remaining_timeout = timeout;
+ if (!timeout)
+ timeout = -ETIME;
+
return active_count ? timeout : 0;
}
--
2.25.1
[Intel-gfx] [PATCH v2 1/2] drm/i915: Fix negative value passed as remaining time
Commit b97060a99b01 ("drm/i915/guc: Update intel_gt_wait_for_idle to work
with GuC") extended the API of intel_gt_retire_requests_timeout() with an
extra argument 'remaining_timeout', intended for passing back unconsumed
portion of requested timeout when 0 (success) is returned. However, when
request retirement happens to succeed despite an error returned by a call
to dma_fence_wait_timeout(), that error code (a negative value) is passed
back instead of remaining time. If we then pass that negative value
forward as requested timeout to intel_uc_wait_for_idle(), an explicit BUG
will be triggered.
If request retirement succeeds but an error code other than -ETIME is
passed back via remaininig_timeout, we have no clue on how much of
the initial timeout might have been left for spending it on waiting for
GuC to become idle. Then, we have no choice other than fail in that case
-- do it. However, if -ETIME is returned via remaining_timeout then we
know that no more time has been left. Then, pass 0 timeout value to
intel_uc_wait_for_idle() to give it a chance to return success if GuC is
already idle.
v2: Fix the issue on the caller side, not the provider.
Fixes: b97060a99b01 ("drm/i915/guc: Update intel_gt_wait_for_idle to work with
GuC")
Signed-off-by: Janusz Krzysztofik
Cc: sta...@vger.kernel.org # v5.15+
---
drivers/gpu/drm/i915/gt/intel_gt.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 0325f071046ca..5d612ba547d23 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -677,8 +677,15 @@ int intel_gt_wait_for_idle(struct intel_gt *gt, long
timeout)
return -EINTR;
}
- return timeout ? timeout : intel_uc_wait_for_idle(>uc,
- remaining_timeout);
+ if (timeout)
+ return timeout;
+
+ if (remaining_timeout == -ETIME)
+ remaining_timeout = 0;
+ else if (remaining_timeout < 0)
+ return remaining_timeout;
+
+ return intel_uc_wait_for_idle(>uc, remaining_timeout);
}
int intel_gt_init(struct intel_gt *gt)
--
2.25.1
[Intel-gfx] [PATCH v2 0/2] drm/i915: Fix timeout handling when retiring requests
Fixes for issues discovered via code review while working on https://gitlab.freedesktop.org/drm/intel/issues/7349. v2: PATCH 1: fix the issue on the caller side, not the provider, reword commit message and description. PATCH 2: move the added lines down so flush_submission() is not affected, reword commit message and description. PATCH 3: drop -- controversial, not needed. Janusz Krzysztofik (2): drm/i915: Fix negative value passed as remaining time drm/i915: Never return 0 if not all requests retired drivers/gpu/drm/i915/gt/intel_gt.c | 11 +-- drivers/gpu/drm/i915/gt/intel_gt_requests.c | 3 +++ 2 files changed, 12 insertions(+), 2 deletions(-) -- 2.25.1
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/mtl: Skip doubling channel numbers for LPDDR4/LPDDDR5
== Series Details == Series: drm/i915/mtl: Skip doubling channel numbers for LPDDR4/LPDDDR5 URL : https://patchwork.freedesktop.org/series/111036/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12396_full -> Patchwork_111036v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_111036v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_111036v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 11) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_111036v1_full: ### IGT changes ### Possible regressions * igt@i915_selftest@live@late_gt_pm: - shard-snb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-snb5/igt@i915_selftest@live@late_gt_pm.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/shard-snb4/igt@i915_selftest@live@late_gt_pm.html Known issues Here are the changes found in Patchwork_111036v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-ext-cpu-access-sanity-check: - shard-iclb: NOTRUN -> [SKIP][3] ([i915#6335]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/shard-iclb8/igt@gem_cre...@create-ext-cpu-access-sanity-check.html * igt@gem_exec_balancer@parallel: - shard-iclb: [PASS][4] -> [SKIP][5] ([i915#4525]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-iclb2/igt@gem_exec_balan...@parallel.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/shard-iclb5/igt@gem_exec_balan...@parallel.html * igt@gem_exec_capture@pi@bcs0: - shard-iclb: [PASS][6] -> [INCOMPLETE][7] ([i915#3371]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-iclb3/igt@gem_exec_capture@p...@bcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/shard-iclb3/igt@gem_exec_capture@p...@bcs0.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-tglb1/igt@gem_exec_fair@basic-f...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/shard-tglb3/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-glk: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk5/igt@gem_exec_fair@basic-n...@vecs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/shard-glk8/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][12] -> [SKIP][13] ([i915#2190]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-tglb5/igt@gem_huc_c...@huc-copy.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/shard-tglb6/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-apl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/shard-apl7/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@gem_lmem_swapping@parallel-multi: - shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/shard-skl6/igt@gem_lmem_swapp...@parallel-multi.html * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled: - shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271]) +127 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/shard-skl2/igt@gem_render_c...@yf-tiled-mc-ccs-to-vebox-yf-tiled.html * igt@gem_tiled_wb: - shard-skl: NOTRUN -> [TIMEOUT][17] ([i915#6990]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/shard-skl6/igt@gem_tiled_wb.html * igt@gen9_exec_parse@unaligned-jump: - shard-iclb: NOTRUN -> [SKIP][18] ([i915#2856]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/shard-iclb8/igt@gen9_exec_pa...@unaligned-jump.html * igt@i915_pipe_stress@stress-xrgb-untiled: - shard-skl: NOTRUN -> [FAIL][19] ([i915#7036]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111036v1/shard-skl9/igt@i915_pipe_str...@stress-xrgb-untiled.html * igt@i915_pm_dc@dc5-psr: - shard-skl: [PASS][20] -> [FAIL][21] ([i915#6470]) [20]:
Re: [Intel-gfx] linux-next: manual merge of the drm-misc tree with the origin tree
On Thu, Nov 17, 2022 at 05:01:08PM -0700, Nathan Chancellor wrote: > On Fri, Nov 18, 2022 at 09:06:36AM +1100, Stephen Rothwell wrote: > > Hi Nathan, > > > > On Thu, 17 Nov 2022 10:29:33 -0700 Nathan Chancellor > > wrote: > > > > > > This resolution is not quite right, as pointed out by clang: > > > > > > drivers/gpu/drm/vc4/vc4_hdmi.c:351:14: error: variable 'vc4_hdmi' is > > > uninitialized when used here [-Werror,-Wuninitialized] > > > mutex_lock(_hdmi->mutex); > > > ^~~~ > > > ./include/linux/mutex.h:187:44: note: expanded from macro 'mutex_lock' > > > #define mutex_lock(lock) mutex_lock_nested(lock, 0) > > >^~~~ > > > drivers/gpu/drm/vc4/vc4_hdmi.c:322:27: note: initialize the variable > > > 'vc4_hdmi' to silence this warning > > > struct vc4_hdmi *vc4_hdmi; > > > ^ > > > = NULL > > > 1 error generated. > > > > > > Obviously, the assignment of vc4_hdmi should be before mutex_lock(). > > > > Thanks for pointing that out (silly me :-) ). I have fixed up the > > resolution for today. > > Great, thank you so much! One less warning to worry about :) I actually did the same conflict resolution in drm-tip. I've fixed it up too, thanks for your report :) Maxime signature.asc Description: PGP signature
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Manage uncore->lock while waiting on MCR register
== Series Details == Series: drm/i915/gt: Manage uncore->lock while waiting on MCR register URL : https://patchwork.freedesktop.org/series/111033/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12396_full -> Patchwork_111033v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_111033v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_111033v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 11) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_111033v1_full: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gtt: - shard-skl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-skl4/igt@i915_selftest@l...@gtt.html Known issues Here are the changes found in Patchwork_111033v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-ext-cpu-access-sanity-check: - shard-iclb: NOTRUN -> [SKIP][2] ([i915#6335]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-iclb6/igt@gem_cre...@create-ext-cpu-access-sanity-check.html * igt@gem_exec_balancer@parallel: - shard-iclb: [PASS][3] -> [SKIP][4] ([i915#4525]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-iclb2/igt@gem_exec_balan...@parallel.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-iclb5/igt@gem_exec_balan...@parallel.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-apl: [PASS][5] -> [FAIL][6] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-apl6/igt@gem_exec_fair@basic-none-s...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-apl: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-apl6/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-skl: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +2 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-skl1/igt@gem_lmem_swapp...@parallel-random-verify.html * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled: - shard-skl: NOTRUN -> [SKIP][9] ([fdo#109271]) +203 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-skl1/igt@gem_render_c...@yf-tiled-mc-ccs-to-vebox-yf-tiled.html * igt@gem_tiled_wb: - shard-skl: NOTRUN -> [TIMEOUT][10] ([i915#6990]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-skl4/igt@gem_tiled_wb.html * igt@gen9_exec_parse@allowed-single: - shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#5566] / [i915#716]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-glk1/igt@gen9_exec_pa...@allowed-single.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-glk5/igt@gen9_exec_pa...@allowed-single.html * igt@gen9_exec_parse@unaligned-jump: - shard-iclb: NOTRUN -> [SKIP][13] ([i915#2856]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-iclb6/igt@gen9_exec_pa...@unaligned-jump.html * igt@i915_pipe_stress@stress-xrgb-ytiled: - shard-skl: NOTRUN -> [FAIL][14] ([i915#7036]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-skl9/igt@i915_pipe_str...@stress-xrgb-ytiled.html * igt@i915_pm_dc@dc6-dpms: - shard-iclb: [PASS][15] -> [FAIL][16] ([i915#3989] / [i915#454]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-iclb2/igt@i915_pm...@dc6-dpms.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-iclb3/igt@i915_pm...@dc6-dpms.html * igt@i915_pm_dc@dc9-dpms: - shard-iclb: [PASS][17] -> [INCOMPLETE][18] ([i915#7475]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12396/shard-iclb7/igt@i915_pm...@dc9-dpms.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-iclb7/igt@i915_pm...@dc9-dpms.html * igt@i915_pm_rpm@dpms-non-lpsp: - shard-iclb: NOTRUN -> [SKIP][19] ([fdo#110892]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111033v1/shard-iclb6/igt@i915_pm_...@dpms-non-lpsp.html *
[Intel-gfx] [PULL] drm-intel-gt-next
Hi Dave & Daniel, Here goes the last drm-intel-gt-next feature pull req for v6.2. We have a couple of important fixes around memory management (TTM and userptr), then demoting GuC kernel contexts to normal priority and Meteorlake enabling. Beyond that it's smaller fixes to code structure and corner cases. Note the backmerge of drm-next to bring in v6.1-rc1 which had needed dependencies for which I gave heads-up in IRC. Regards, Joonas ** drm-intel-gt-next-2022-11-18: Core Changes: - Backmerge of drm-next Driver Changes: - Restore probe_range behaviour for userptr (Matt A) - Fix use-after-free on lmem_userfault_list (Matt A) - Never purge busy TTM objects (Matt A) - Meteorlake enabling (Daniele, Badal, Daniele, Stuart, Aravind, Alan) - Demote GuC kernel contexts to normal priority (John) - Use RC6 residency types as arguments to residency functions (Ashutosh, Rodrigo, Jani) - Convert some legacy DRM debugging macros to new ones (Tvrtko) - Don't deadlock GuC busyness stats vs reset (John) - Remove excessive line feeds in GuC state dumps (John) - Use i915_sg_dma_sizes() for all backends (Matt A) - Prefer REG_FIELD_GET in intel_rps_get_cagf (Ashutosh, Rodrigo) - Use GEN12_RPSTAT register for GT freq (Don, Badal, Ashutosh) - Remove unwanted TTM ghost obj check (Matt A) - Update workaround documentation (Lucas) - Coding style and static checker fixes and cleanups (Jani, Umesh, Tvrtko, Lucas, Andrzej) - Selftest improvements (Chris, Daniele, Riana, Andrzej) The following changes since commit 60ba8c5bd94e17ab4b024f5cecf8b48e2cf36412: Merge tag 'drm-intel-gt-next-2022-11-03' of git://anongit.freedesktop.org/drm/drm-intel into drm-next (2022-11-04 17:33:34 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-gt-next-2022-11-18 for you to fetch changes up to 4bb9ca7ee07455bec0a802ecf0aa5b09496888e2: drm/i915/mtl: C6 residency and C state type for MTL SAMedia (2022-11-17 10:47:12 -0500) Core Changes: - Backmerge of drm-next Driver Changes: - Restore probe_range behaviour for userptr (Matt A) - Fix use-after-free on lmem_userfault_list (Matt A) - Never purge busy TTM objects (Matt A) - Meteorlake enabling (Daniele, Badal, Daniele, Stuart, Aravind, Alan) - Demote GuC kernel contexts to normal priority (John) - Use RC6 residency types as arguments to residency functions (Ashutosh, Rodrigo, Jani) - Convert some legacy DRM debugging macros to new ones (Tvrtko) - Don't deadlock GuC busyness stats vs reset (John) - Remove excessive line feeds in GuC state dumps (John) - Use i915_sg_dma_sizes() for all backends (Matt A) - Prefer REG_FIELD_GET in intel_rps_get_cagf (Ashutosh, Rodrigo) - Use GEN12_RPSTAT register for GT freq (Don, Badal, Ashutosh) - Remove unwanted TTM ghost obj check (Matt A) - Update workaround documentation (Lucas) - Coding style and static checker fixes and cleanups (Jani, Umesh, Tvrtko, Lucas, Andrzej) - Selftest improvements (Chris, Daniele, Riana, Andrzej) Alan Previn (1): drm/i915/pxp: Separate PXP FW interface structures for both v42 and 43 Andrzej Hajda (2): drm/i915: call i915_request_await_object from _i915_vma_move_to_active drm/i915/selftests: add igt_vma_move_to_active_unlocked Aravind Iddamsetty (1): drm/i915/mtl: Handle wopcm per-GT and limit calculations. Ashutosh Dixit (2): drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf drm/i915/gt: Use RC6 residency types as arguments to residency functions Badal Nilawar (3): drm/i915/mtl: Add Wa_14017073508 for SAMedia drm/i915/mtl: Modify CAGF functions for MTL drm/i915/mtl: C6 residency and C state type for MTL SAMedia Chris Wilson (1): drm/i915/selftests: Reduce oversaturation of request smoketesting Daniele Ceraolo Spurio (12): drm/i915/mtl: add initial definitions for GSC CS drm/i915/mtl: pass the GSC CS info to the GuC drm/i915/mtl: add GSC CS interrupt support drm/i915/mtl: add GSC CS reset support drm/i915/mtl: don't expose GSC command streamer to the user drm/i915/guc: don't hardcode BCS0 in guc_hang selftest drm/i915/huc: only load HuC on GTs that have VCS engines drm/i915/uc: fetch uc firmwares for each GT drm/i915/uc: use different ggtt pin offsets for uc loads drm/i915/guc: define media GT GuC send regs drm/i915/guc: handle interrupts from media GuC drm/i915/guc: add the GSC CS to the GuC capture list Don Hiatt (1): drm/i915: Use GEN12_RPSTAT register for GT freq Jani Nikula (1): drm/i915/pxp: use <> instead of "" for headers in include/ John Harrison (3): drm/i915/guc: Remove excessive line feeds in state dumps drm/i915/guc: Properly initialise kernel contexts drm/i915/guc: Don't deadlock busyness stats vs reset Joonas Lahtinen (1):
Re: [Intel-gfx] [PATCH v3 07/20] drm/i915: s/gamma/post_csc_lut/
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Monday, November 14, 2022 9:07 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 07/20] drm/i915: s/gamma/post_csc_lut/
>
> From: Ville Syrjälä
>
> Rename a the LUT state check foo_gamma_precision() functions to
> foo_post_csc_lut_precision() to make it more clear what they really do.
Looks Good to me.
Reviewed-by: Uma Shankar
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 22 +++---
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 250e83f1f5ac..e1958a1b4dcc 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1792,7 +1792,7 @@ static int icl_color_check(struct intel_crtc_state
> *crtc_state)
> return 0;
> }
>
> -static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
> +static int i9xx_post_csc_lut_precision(const struct intel_crtc_state
> +*crtc_state)
> {
> if (!crtc_state->gamma_enable)
> return 0;
> @@ -1808,7 +1808,7 @@ static int i9xx_gamma_precision(const struct
> intel_crtc_state *crtc_state)
> }
> }
>
> -static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
> +static int ilk_post_csc_lut_precision(const struct intel_crtc_state
> +*crtc_state)
> {
> if (!crtc_state->gamma_enable)
> return 0;
> @@ -1827,15 +1827,15 @@ static int ilk_gamma_precision(const struct
> intel_crtc_state *crtc_state)
> }
> }
>
> -static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
> +static int chv_post_csc_lut_precision(const struct intel_crtc_state
> +*crtc_state)
> {
> if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
> return 10;
> else
> - return i9xx_gamma_precision(crtc_state);
> + return i9xx_post_csc_lut_precision(crtc_state);
> }
>
> -static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
> +static int glk_post_csc_lut_precision(const struct intel_crtc_state
> +*crtc_state)
> {
> if (!crtc_state->gamma_enable)
> return 0;
> @@ -1851,7 +1851,7 @@ static int glk_gamma_precision(const struct
> intel_crtc_state *crtc_state)
> }
> }
>
> -static int icl_gamma_precision(const struct intel_crtc_state *crtc_state)
> +static int icl_post_csc_lut_precision(const struct intel_crtc_state
> +*crtc_state)
> {
> if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
> return 0;
> @@ -1876,16 +1876,16 @@ int intel_color_get_gamma_bit_precision(const struct
> intel_crtc_state *crtc_stat
>
> if (HAS_GMCH(i915)) {
> if (IS_CHERRYVIEW(i915))
> - return chv_gamma_precision(crtc_state);
> + return chv_post_csc_lut_precision(crtc_state);
> else
> - return i9xx_gamma_precision(crtc_state);
> + return i9xx_post_csc_lut_precision(crtc_state);
> } else {
> if (DISPLAY_VER(i915) >= 11)
> - return icl_gamma_precision(crtc_state);
> + return icl_post_csc_lut_precision(crtc_state);
> else if (DISPLAY_VER(i915) == 10)
> - return glk_gamma_precision(crtc_state);
> + return glk_post_csc_lut_precision(crtc_state);
> else if (IS_IRONLAKE(i915))
> - return ilk_gamma_precision(crtc_state);
> + return ilk_post_csc_lut_precision(crtc_state);
> }
>
> return 0;
> --
> 2.37.4
Re: [Intel-gfx] [PATCH v3 06/20] drm/i915: Fix adl+ degamma LUT size
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Monday, November 14, 2022 9:07 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 06/20] drm/i915: Fix adl+ degamma LUT size
>
> From: Ville Syrjälä
>
> The degamma LUT is interpolated so we need the 128th (==1.0) entry to
> represent
> the full < 1.0 input range. Only the 129th and 130th entries are strictly for
> the >=1.0
> extended range inputs.
Looks Good to me.
Reviewed-by: Uma Shankar
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_pci.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c
> b/drivers/gpu/drm/i915/i915_pci.c index
> 211913be40ce..c50841e36c61 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -948,7 +948,7 @@ static const struct intel_device_info adl_s_info = {
> #define
> XE_LPD_FEATURES \
> .display.abox_mask = GENMASK(1, 0),
> \
> .display.color = {
> \
> - .degamma_lut_size = 128, .gamma_lut_size = 1024,
> \
> + .degamma_lut_size = 129, .gamma_lut_size = 1024,
> \
> .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |
> \
>DRM_COLOR_LUT_EQUAL_CHANNELS,
> \
> },
> \
> --
> 2.37.4
