[Intel-gfx] ✗ Fi.CI.BAT: failure for add guard padding around i915_vma (rev3)
== Series Details == Series: add guard padding around i915_vma (rev3) URL : https://patchwork.freedesktop.org/series/110720/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12435 -> Patchwork_110720v3 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_110720v3 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_110720v3, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110720v3/index.html Participating hosts (36 -> 36) -- Additional (2): fi-adl-ddr5 fi-tgl-dsi Missing(2): fi-ctg-p8600 bat-dg1-6 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_110720v3: ### IGT changes ### Possible regressions * igt@i915_selftest@live@hangcheck: - fi-rkl-guc: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12435/fi-rkl-guc/igt@i915_selftest@l...@hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110720v3/fi-rkl-guc/igt@i915_selftest@l...@hangcheck.html Known issues Here are the changes found in Patchwork_110720v3 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - fi-adl-ddr5:NOTRUN -> [SKIP][3] ([i915#7456]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110720v3/fi-adl-ddr5/igt@debugfs_t...@basic-hwmon.html * igt@gem_exec_gttfill@basic: - fi-pnv-d510:[PASS][4] -> [FAIL][5] ([i915#7229]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12435/fi-pnv-d510/igt@gem_exec_gttf...@basic.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110720v3/fi-pnv-d510/igt@gem_exec_gttf...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-adl-ddr5:NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110720v3/fi-adl-ddr5/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_tiled_blits@basic: - fi-pnv-d510:[PASS][7] -> [SKIP][8] ([fdo#109271]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12435/fi-pnv-d510/igt@gem_tiled_bl...@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110720v3/fi-pnv-d510/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - fi-adl-ddr5:NOTRUN -> [SKIP][9] ([i915#3282]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110720v3/fi-adl-ddr5/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - fi-adl-ddr5:NOTRUN -> [SKIP][10] ([i915#7561]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110720v3/fi-adl-ddr5/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@hangcheck: - fi-adl-ddr5:NOTRUN -> [DMESG-WARN][11] ([i915#5591]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110720v3/fi-adl-ddr5/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@dp-edid-read: - fi-adl-ddr5:NOTRUN -> [SKIP][12] ([fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110720v3/fi-adl-ddr5/igt@kms_chamel...@dp-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor: - fi-adl-ddr5:NOTRUN -> [SKIP][13] ([i915#4103]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110720v3/fi-adl-ddr5/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html * igt@kms_force_connector_basic@force-load-detect: - fi-adl-ddr5:NOTRUN -> [SKIP][14] ([fdo#109285]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110720v3/fi-adl-ddr5/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_psr@cursor_plane_move: - fi-adl-ddr5:NOTRUN -> [SKIP][15] ([i915#1072]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110720v3/fi-adl-ddr5/igt@kms_psr@cursor_plane_move.html * igt@kms_setmode@basic-clone-single-crtc: - fi-adl-ddr5:NOTRUN -> [SKIP][16] ([i915#3555]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110720v3/fi-adl-ddr5/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-userptr: - fi-adl-ddr5:NOTRUN -> [SKIP][17] ([fdo#109295] / [i915#3301]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110720v3/fi-adl-ddr5/igt@prime_v...@basic-userptr.html * igt@prime_vgem@basic-write: - fi-adl-ddr5:NOTRUN -> [SKIP][18] ([fdo#109295] / [i915#3291]) +2 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110720v3/fi-adl-ddr5/igt@prime_v...@basic-write.html Possible
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for add guard padding around i915_vma (rev3)
== Series Details == Series: add guard padding around i915_vma (rev3) URL : https://patchwork.freedesktop.org/series/110720/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for add guard padding around i915_vma (rev3)
== Series Details == Series: add guard padding around i915_vma (rev3) URL : https://patchwork.freedesktop.org/series/110720/ State : warning == Summary == Error: dim checkpatch failed f7daace394f7 drm/i915: Wrap all access to i915_vma.node.start|size -:264: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #264: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c:475: + GEM_BUG_ON(i915_vma_offset(vma) != addr); -:356: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #356: FILE: drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c:65: + GEM_BUG_ON(offset + (count - 1) * PAGE_SIZE > i915_vma_size(vma)); -:393: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #393: FILE: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c:223: + GEM_BUG_ON(vma->fence_size > i915_vma_size(vma)); -:787: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #787: FILE: drivers/gpu/drm/i915/i915_vma.c:450: + GEM_BUG_ON(vma->size > i915_vma_size(vma)); -:870: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #870: FILE: drivers/gpu/drm/i915/i915_vma.h:146: + GEM_BUG_ON(!drm_mm_node_allocated(>node)); -:892: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #892: FILE: drivers/gpu/drm/i915/i915_vma.h:168: + GEM_BUG_ON(!drm_mm_node_allocated(>node)); -:903: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #903: FILE: drivers/gpu/drm/i915/i915_vma.h:176: + GEM_BUG_ON(upper_32_bits(i915_vma_offset(vma))); -:904: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #904: FILE: drivers/gpu/drm/i915/i915_vma.h:177: + GEM_BUG_ON(upper_32_bits(i915_vma_offset(vma) + total: 0 errors, 8 warnings, 0 checks, 805 lines checked 36a1d1d017ee drm/i915: Introduce guard pages to i915_vma -:118: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #118: FILE: drivers/gpu/drm/i915/i915_vma.c:762: + GEM_BUG_ON(hweight64(flags & (PIN_OFFSET_GUARD | PIN_OFFSET_FIXED | PIN_OFFSET_BIAS)) > 1); -:132: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #132: FILE: drivers/gpu/drm/i915/i915_vma.c:778: + GEM_BUG_ON(overflows_type(flags & PIN_OFFSET_MASK, u32)); -:227: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_node' - possible side-effects? #227: FILE: drivers/gpu/drm/i915/i915_vma_resource.c:37: +#define VMA_RES_START(_node) ((_node)->start - (_node)->guard) -:228: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_node' - possible side-effects? #228: FILE: drivers/gpu/drm/i915/i915_vma_resource.c:38: +#define VMA_RES_LAST(_node) ((_node)->start + (_node)->node_size + (_node)->guard - 1) total: 0 errors, 2 warnings, 2 checks, 207 lines checked 2ad1adab85d0 drm/i915: Refine VT-d scanout workaround 35ea638e279e Revert "drm/i915: Improve on suspend / resume time with VT-d enabled" 385c05fb3340 drm/i915: Limit the display memory alignment to 32 bit instead of 64
[Intel-gfx] [PATCH v3 5/5] drm/i915: Limit the display memory alignment to 32 bit instead of 64
Chris commit "drm/i915: Introduce guard pages to i915_vma" was
"cunningly" changing display_alignment to u32 from u64. The
reason is that the display GGTT is and will be limited o 4GB.
Put it in a separate patch and use "max(...)" instead of
"max_t(64, ...)" when asigning the value. We can safely use max
as we know beforehand that the comparison is between two u32
variables.
Signed-off-by: Chris Wilson
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/display/intel_fb_pin.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 2 +-
drivers/gpu/drm/i915/i915_vma_types.h | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c
b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index 6900acbb1381c..1aca7552a85d0 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -91,7 +91,7 @@ intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
goto err;
}
- vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
+ vma->display_alignment = max(vma->display_alignment, alignment);
i915_gem_object_flush_if_display(obj);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 882b91519f92b..9969e687ad857 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -457,7 +457,7 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
if (IS_ERR(vma))
return vma;
- vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
+ vma->display_alignment = max(vma->display_alignment, alignment);
i915_vma_mark_scanout(vma);
i915_gem_object_flush_if_display_locked(obj);
diff --git a/drivers/gpu/drm/i915/i915_vma_types.h
b/drivers/gpu/drm/i915/i915_vma_types.h
index 46f5ce19d4a0a..77fda2244d161 100644
--- a/drivers/gpu/drm/i915/i915_vma_types.h
+++ b/drivers/gpu/drm/i915/i915_vma_types.h
@@ -197,7 +197,6 @@ struct i915_vma {
struct i915_fence_reg *fence;
u64 size;
- u64 display_alignment;
struct i915_page_sizes page_sizes;
/* mmap-offset associated with fencing for this vma */
@@ -206,6 +205,7 @@ struct i915_vma {
u32 guard; /* padding allocated around vma->pages within the node */
u32 fence_size;
u32 fence_alignment;
+ u32 display_alignment;
/**
* Count of the number of times this vma has been opened by different
--
2.38.1
[Intel-gfx] [PATCH v3 3/5] drm/i915: Refine VT-d scanout workaround
From: Chris Wilson
VT-d may cause overfetch of the scanout PTE, both before and after the
vma (depending on the scanout orientation). bspec recommends that we
provide a tile-row in either directions, and suggests using 168 PTE,
warning that the accesses will wrap around the ends of the GGTT.
Currently, we fill the entire GGTT with scratch pages when using VT-d to
always ensure there are valid entries around every vma, including
scanout. However, writing every PTE is slow as on recent devices we
perform 8MiB of uncached writes, incurring an extra 100ms during resume.
If instead we focus on only putting guard pages around scanout, we can
avoid touching the whole GGTT. To avoid having to introduce extra nodes
around each scanout vma, we adjust the scanout drm_mm_node to be smaller
than the allocated space, and fixup the extra PTE during dma binding.
Signed-off-by: Chris Wilson
Signed-off-by: Tejas Upadhyay
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 13 +++
drivers/gpu/drm/i915/gt/intel_ggtt.c | 25 +-
2 files changed, 14 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index d44a152ce6800..882b91519f92b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -17,6 +17,8 @@
#include "i915_gem_object.h"
#include "i915_vma.h"
+#define VTD_GUARD (168u * I915_GTT_PAGE_SIZE) /* 168 or tile-row PTE padding */
+
static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
@@ -424,6 +426,17 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
if (ret)
return ERR_PTR(ret);
+ /* VT-d may overfetch before/after the vma, so pad with scratch */
+ if (intel_scanout_needs_vtd_wa(i915)) {
+ unsigned int guard = VTD_GUARD;
+
+ if (i915_gem_object_is_tiled(obj))
+ guard = max(guard,
+ i915_gem_object_get_tile_row_size(obj));
+
+ flags |= PIN_OFFSET_GUARD | guard;
+ }
+
/*
* As the user may map the buffer once pinned in the display plane
* (e.g. libkms for the bootup splash), we have to ensure that we
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 133710258eae6..5ccec5c9206d2 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -367,27 +367,6 @@ static void nop_clear_range(struct i915_address_space *vm,
{
}
-static void gen8_ggtt_clear_range(struct i915_address_space *vm,
- u64 start, u64 length)
-{
- struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
- unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
- unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
- const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
- gen8_pte_t __iomem *gtt_base =
- (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
- const int max_entries = ggtt_total_entries(ggtt) - first_entry;
- int i;
-
- if (WARN(num_entries > max_entries,
-"First entry = %d; Num entries = %d (max=%d)\n",
-first_entry, num_entries, max_entries))
- num_entries = max_entries;
-
- for (i = 0; i < num_entries; i++)
- gen8_set_pte(_base[i], scratch_pte);
-}
-
static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
{
/*
@@ -959,8 +938,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.cleanup = gen6_gmch_remove;
ggtt->vm.insert_page = gen8_ggtt_insert_page;
ggtt->vm.clear_range = nop_clear_range;
- if (intel_scanout_needs_vtd_wa(i915))
- ggtt->vm.clear_range = gen8_ggtt_clear_range;
ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
@@ -1121,7 +1098,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
ggtt->vm.clear_range = nop_clear_range;
- if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915))
+ if (!HAS_FULL_PPGTT(i915))
ggtt->vm.clear_range = gen6_ggtt_clear_range;
ggtt->vm.insert_page = gen6_ggtt_insert_page;
ggtt->vm.insert_entries = gen6_ggtt_insert_entries;
--
2.38.1
[Intel-gfx] [PATCH v3 4/5] Revert "drm/i915: Improve on suspend / resume time with VT-d enabled"
This reverts commit 2ef6efa79fecd5e3457b324155d35524d95f2b6b.
Checking the presence if the IRST (Intel Rapid Start Technology)
through the ACPI to decide whether to rebuild or not the GGTT
puts us at the mercy of the boot firmware and we need to
unnecessarily rely on third parties.
Because now we avoid adding scratch pages to the entire GGTT we
don't need this hack anymore.
Signed-off-by: Andi Shyti
Cc: Thomas Hellström
Cc: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 69 ++--
drivers/gpu/drm/i915/gt/intel_gtt.h | 24 --
drivers/gpu/drm/i915/i915_driver.c | 16 ---
3 files changed, 13 insertions(+), 96 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 5ccec5c9206d2..9d76a573255f6 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -26,13 +26,6 @@
#include "intel_gtt.h"
#include "gen8_ppgtt.h"
-static inline bool suspend_retains_ptes(struct i915_address_space *vm)
-{
- return GRAPHICS_VER(vm->i915) >= 8 &&
- !HAS_LMEM(vm->i915) &&
- vm->is_ggtt;
-}
-
static void i915_ggtt_color_adjust(const struct drm_mm_node *node,
unsigned long color,
u64 *start,
@@ -104,23 +97,6 @@ int i915_ggtt_init_hw(struct drm_i915_private *i915)
return 0;
}
-/*
- * Return the value of the last GGTT pte cast to an u64, if
- * the system is supposed to retain ptes across resume. 0 otherwise.
- */
-static u64 read_last_pte(struct i915_address_space *vm)
-{
- struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
- gen8_pte_t __iomem *ptep;
-
- if (!suspend_retains_ptes(vm))
- return 0;
-
- GEM_BUG_ON(GRAPHICS_VER(vm->i915) < 8);
- ptep = (typeof(ptep))ggtt->gsm + (ggtt_total_entries(ggtt) - 1);
- return readq(ptep);
-}
-
/**
* i915_ggtt_suspend_vm - Suspend the memory mappings for a GGTT or DPT VM
* @vm: The VM to suspend the mappings for
@@ -184,10 +160,7 @@ void i915_ggtt_suspend_vm(struct i915_address_space *vm)
i915_gem_object_unlock(obj);
}
- if (!suspend_retains_ptes(vm))
- vm->clear_range(vm, 0, vm->total);
- else
- i915_vm_to_ggtt(vm)->probed_pte = read_last_pte(vm);
+ vm->clear_range(vm, 0, vm->total);
vm->skip_pte_rewrite = save_skip_rewrite;
@@ -536,8 +509,6 @@ static int init_ggtt(struct i915_ggtt *ggtt)
struct drm_mm_node *entry;
int ret;
- ggtt->pte_lost = true;
-
/*
* GuC requires all resources that we're sharing with it to be placed in
* non-WOPCM memory. If GuC is not present or not in use we still need a
@@ -1236,20 +1207,11 @@ bool i915_ggtt_resume_vm(struct i915_address_space *vm)
{
struct i915_vma *vma;
bool write_domain_objs = false;
- bool retained_ptes;
drm_WARN_ON(>i915->drm, !vm->is_ggtt && !vm->is_dpt);
- /*
-* First fill our portion of the GTT with scratch pages if
-* they were not retained across suspend.
-*/
- retained_ptes = suspend_retains_ptes(vm) &&
- !i915_vm_to_ggtt(vm)->pte_lost &&
- !GEM_WARN_ON(i915_vm_to_ggtt(vm)->probed_pte !=
read_last_pte(vm));
-
- if (!retained_ptes)
- vm->clear_range(vm, 0, vm->total);
+ /* First fill our portion of the GTT with scratch pages */
+ vm->clear_range(vm, 0, vm->total);
/* clflush objects bound into the GGTT and rebind them. */
list_for_each_entry(vma, >bound_list, vm_link) {
@@ -1258,16 +1220,16 @@ bool i915_ggtt_resume_vm(struct i915_address_space *vm)
atomic_read(>flags) & I915_VMA_BIND_MASK;
GEM_BUG_ON(!was_bound);
- if (!retained_ptes) {
- /*
-* Clear the bound flags of the vma resource to allow
-* ptes to be repopulated.
-*/
- vma->resource->bound_flags = 0;
- vma->ops->bind_vma(vm, NULL, vma->resource,
- obj ? obj->cache_level : 0,
- was_bound);
- }
+
+ /*
+* Clear the bound flags of the vma resource to allow
+* ptes to be repopulated.
+*/
+ vma->resource->bound_flags = 0;
+ vma->ops->bind_vma(vm, NULL, vma->resource,
+ obj ? obj->cache_level : 0,
+ was_bound);
+
if (obj) { /* only used during resume => exclusive access */
write_domain_objs |= fetch_and_zero(>write_domain);
obj->read_domains |= I915_GEM_DOMAIN_GTT;
@@ -1295,8 +1257,3 @@
[Intel-gfx] [PATCH v3 1/5] drm/i915: Wrap all access to i915_vma.node.start|size
From: Chris Wilson
We already wrap i915_vma.node.start for use with the GGTT, as there we
can perform additional sanity checks that the node belongs to the GGTT
and fits within the 32b registers. In the next couple of patches, we
will introduce guard pages around the objects _inside_ the drm_mm_node
allocation. That is we will offset the vma->pages so that the first page
is at drm_mm_node.start + vma->guard (not 0 as is currently the case).
All users must then not use i915_vma.node.start directly, but compute
the guard offset, thus all users are converted to use a
i915_vma_offset() wrapper.
The notable exceptions are the selftests that are testing exact
behaviour of i915_vma_pin/i915_vma_insert.
Signed-off-by: Chris Wilson
Signed-off-by: Tejas Upadhyay
Co-developed-by: Thomas Hellström
Signed-off-by: Thomas Hellström
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Andi Shyti
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/display/intel_fbdev.c| 2 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 33 ++--
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_tiling.c| 4 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
.../i915/gem/selftests/i915_gem_client_blt.c | 23 +
.../drm/i915/gem/selftests/i915_gem_context.c | 15 +++---
.../drm/i915/gem/selftests/i915_gem_mman.c| 2 +-
.../drm/i915/gem/selftests/igt_gem_utils.c| 7 +--
drivers/gpu/drm/i915/gt/gen7_renderclear.c| 2 +-
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 3 +-
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 8 +--
drivers/gpu/drm/i915/gt/selftest_execlists.c | 18 +++
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 15 +++---
drivers/gpu/drm/i915/gt/selftest_lrc.c| 16 +++---
.../drm/i915/gt/selftest_ring_submission.c| 2 +-
drivers/gpu/drm/i915/gt/selftest_rps.c| 12 ++---
.../gpu/drm/i915/gt/selftest_workarounds.c| 8 +--
drivers/gpu/drm/i915/i915_cmd_parser.c| 4 +-
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 25 -
drivers/gpu/drm/i915/i915_vma.h | 51 +--
drivers/gpu/drm/i915/i915_vma_resource.h | 10 ++--
drivers/gpu/drm/i915/selftests/i915_request.c | 20
drivers/gpu/drm/i915/selftests/igt_spinner.c | 8 +--
29 files changed, 180 insertions(+), 122 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 5575d7abdc092..03ed4607a46d2 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -286,7 +286,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
/* Our framebuffer is the entirety of fbdev's system memory */
info->fix.smem_start =
- (unsigned long)(ggtt->gmadr.start + vma->node.start);
+ (unsigned long)(ggtt->gmadr.start +
i915_ggtt_offset(vma));
info->fix.smem_len = vma->size;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 29e9e8d5b6fec..86956b902c978 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -379,22 +379,25 @@ eb_vma_misplaced(const struct drm_i915_gem_exec_object2
*entry,
const struct i915_vma *vma,
unsigned int flags)
{
- if (vma->node.size < entry->pad_to_size)
+ const u64 start = i915_vma_offset(vma);
+ const u64 size = i915_vma_size(vma);
+
+ if (size < entry->pad_to_size)
return true;
- if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
+ if (entry->alignment && !IS_ALIGNED(start, entry->alignment))
return true;
if (flags & EXEC_OBJECT_PINNED &&
- vma->node.start != entry->offset)
+ start != entry->offset)
return true;
if (flags & __EXEC_OBJECT_NEEDS_BIAS &&
- vma->node.start < BATCH_OFFSET_BIAS)
+ start < BATCH_OFFSET_BIAS)
return true;
if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
- (vma->node.start + vma->node.size + 4095) >> 32)
+ (start + size + 4095) >> 32)
return true;
if (flags & __EXEC_OBJECT_NEEDS_MAP &&
@@ -440,7 +443,7 @@ eb_pin_vma(struct i915_execbuffer *eb,
int err;
if (vma->node.size)
- pin_flags = vma->node.start;
+ pin_flags = __i915_vma_offset(vma);
else
pin_flags = entry->offset & PIN_OFFSET_MASK;
@@ -663,8 +666,8 @@
[Intel-gfx] [PATCH v3 2/5] drm/i915: Introduce guard pages to i915_vma
From: Chris Wilson Introduce the concept of padding the i915_vma with guard pages before and after. The major consequence is that all ordinary uses of i915_vma must use i915_vma_offset/i915_vma_size and not i915_vma.node.start/size directly, as the drm_mm_node will include the guard pages that surround our object. The biggest connundrum is how exactly to mix requesting a fixed address with guard pages, particularly through the existing uABI. The user does not know about guard pages, so such must be transparent to the user, and so the execobj.offset must be that of the object itself excluding the guard. So a PIN_OFFSET_FIXED must then be exclusive of the guard pages. The caveat is that some placements will be impossible with guard pages, as wrap arounds need to be avoided, and the vma itself will require a larger node. We must not report EINVAL but ENOSPC as these are unavailable locations within the GTT rather than conflicting user requirements. In the next patch, we start using guard pages for scanout objects. While these are limited to GGTT vma, on a few platforms these vma (or at least an alias of the vma) is shared with userspace, so we may leak the existence of such guards if we are not careful to ensure that the execobj.offset is transparent and excludes the guards. (On such platforms like ivb, without full-ppgtt, userspace has to use relocations so the presence of more untouchable regions within its GTT such be of no further issue.) Signed-off-by: Chris Wilson Signed-off-by: Tejas Upadhyay Signed-off-by: Tvrtko Ursulin Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_ggtt.c | 14 +--- drivers/gpu/drm/i915/i915_gem_gtt.h | 3 +- drivers/gpu/drm/i915/i915_vma.c | 43 drivers/gpu/drm/i915/i915_vma.h | 5 +-- drivers/gpu/drm/i915/i915_vma_resource.c | 4 +-- drivers/gpu/drm/i915/i915_vma_resource.h | 7 +++- drivers/gpu/drm/i915/i915_vma_types.h| 1 + 7 files changed, 60 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 8145851ad23d5..133710258eae6 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -287,8 +287,11 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm, */ gte = (gen8_pte_t __iomem *)ggtt->gsm; - gte += vma_res->start / I915_GTT_PAGE_SIZE; - end = gte + vma_res->node_size / I915_GTT_PAGE_SIZE; + gte += (vma_res->start - vma_res->guard) / I915_GTT_PAGE_SIZE; + end = gte + vma_res->guard / I915_GTT_PAGE_SIZE; + while (gte < end) + gen8_set_pte(gte++, vm->scratch[0]->encode); + end += (vma_res->node_size + vma_res->guard) / I915_GTT_PAGE_SIZE; for_each_sgt_daddr(addr, iter, vma_res->bi.pages) gen8_set_pte(gte++, pte_encode | addr); @@ -338,9 +341,12 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm, dma_addr_t addr; gte = (gen6_pte_t __iomem *)ggtt->gsm; - gte += vma_res->start / I915_GTT_PAGE_SIZE; - end = gte + vma_res->node_size / I915_GTT_PAGE_SIZE; + gte += (vma_res->start - vma_res->guard) / I915_GTT_PAGE_SIZE; + end = gte + vma_res->guard / I915_GTT_PAGE_SIZE; + while (gte < end) + iowrite32(vm->scratch[0]->encode, gte++); + end += (vma_res->node_size + vma_res->guard) / I915_GTT_PAGE_SIZE; for_each_sgt_daddr(addr, iter, vma_res->bi.pages) iowrite32(vm->pte_encode(addr, level, flags), gte++); GEM_BUG_ON(gte > end); diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 8c2f57eb5ddaa..2434197830523 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -44,7 +44,8 @@ int i915_gem_gtt_insert(struct i915_address_space *vm, #define PIN_HIGH BIT_ULL(5) #define PIN_OFFSET_BIASBIT_ULL(6) #define PIN_OFFSET_FIXED BIT_ULL(7) -#define PIN_VALIDATE BIT_ULL(8) /* validate placement only, no need to call unpin() */ +#define PIN_OFFSET_GUARD BIT_ULL(8) +#define PIN_VALIDATE BIT_ULL(9) /* validate placement only, no need to call unpin() */ #define PIN_GLOBAL BIT_ULL(10) /* I915_VMA_GLOBAL_BIND */ #define PIN_USER BIT_ULL(11) /* I915_VMA_LOCAL_BIND */ diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index 2232118babeb3..709a37f1c144b 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -419,7 +419,7 @@ i915_vma_resource_init_from_vma(struct i915_vma_resource *vma_res, obj->mm.rsgt, i915_gem_object_is_readonly(obj), i915_gem_object_is_lmem(obj), obj->mm.region, vma->ops, vma->private, __i915_vma_offset(vma), -
[Intel-gfx] [PATCH v3 0/5] Add guard padding around i915_vma
Hi,
This series adds guards around vma's but setting a pages at the
beginning and at the end that work as padding.
The first user of the vma guard are scanout objects which don't
need anymore to add scratch to all the unused ggtt's and speeding
up up considerably the boot and resume by several hundreds of
milliseconds up to over a full second in slower machines.
Because of this we don't need anymore 2ef6efa79fec ("drm/i915:
Improve on suspend / resume time with VT-d enabled") which gets
reverted.
Thanks Tvrtko for the review.
Andi
Changelog
=
v2 -> v3:
- fix Tvrtko's comments: explain in a comment why the guard is
is alligned as the vma and remove a GEM_BUG_ON() in case the
the total padding was exceeding the size of the va.
- the display_alignment is declared as u32 instead of a u64 in
a separate patch.
v1 -> v2:
- Revert 2ef6efa79fec ("drm/i915: Improve on suspend / resume
time with VT-d enabled")
Andi Shyti (2):
Revert "drm/i915: Improve on suspend / resume time with VT-d enabled"
drm/i915: Limit the display memory alignment to 32 bit instead of 64
Chris Wilson (3):
drm/i915: Wrap all access to i915_vma.node.start|size
drm/i915: Introduce guard pages to i915_vma
drm/i915: Refine VT-d scanout workaround
drivers/gpu/drm/i915/display/intel_fb_pin.c | 2 +-
drivers/gpu/drm/i915/display/intel_fbdev.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_domain.c| 15 ++-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 33 +++---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_tiling.c| 4 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
.../i915/gem/selftests/i915_gem_client_blt.c | 23 ++--
.../drm/i915/gem/selftests/i915_gem_context.c | 15 ++-
.../drm/i915/gem/selftests/i915_gem_mman.c| 2 +-
.../drm/i915/gem/selftests/igt_gem_utils.c| 7 +-
drivers/gpu/drm/i915/gt/gen7_renderclear.c| 2 +-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 108 --
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 3 +-
drivers/gpu/drm/i915/gt/intel_gtt.h | 24
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 8 +-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 18 +--
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 15 +--
drivers/gpu/drm/i915/gt/selftest_lrc.c| 16 +--
.../drm/i915/gt/selftest_ring_submission.c| 2 +-
drivers/gpu/drm/i915/gt/selftest_rps.c| 12 +-
.../gpu/drm/i915/gt/selftest_workarounds.c| 8 +-
drivers/gpu/drm/i915/i915_cmd_parser.c| 4 +-
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_driver.c| 16 ---
drivers/gpu/drm/i915/i915_gem_gtt.h | 3 +-
drivers/gpu/drm/i915/i915_perf.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 66 ---
drivers/gpu/drm/i915/i915_vma.h | 52 -
drivers/gpu/drm/i915/i915_vma_resource.c | 4 +-
drivers/gpu/drm/i915/i915_vma_resource.h | 17 ++-
drivers/gpu/drm/i915/i915_vma_types.h | 3 +-
drivers/gpu/drm/i915/selftests/i915_request.c | 20 ++--
drivers/gpu/drm/i915/selftests/igt_spinner.c | 8 +-
37 files changed, 267 insertions(+), 259 deletions(-)
--
2.38.1
Re: [Intel-gfx] [PATCH 1/9] drm/amdgpu: generally allow over-commit during BO allocation
On Fri, Nov 25, 2022 at 5:21 AM Christian König
wrote:
>
> We already fallback to a dummy BO with no backing store when we
> allocate GDS,GWS and OA resources and to GTT when we allocate VRAM.
>
> Drop all those workarounds and generalize this for GTT as well. This
> fixes ENOMEM issues with runaway applications which try to allocate/free
> GTT in a loop and are otherwise only limited by the CPU speed.
>
> The CS will wait for the cleanup of freed up BOs to satisfy the
> various domain specific limits and so effectively throttle those
> buggy applications down to a sane allocation behavior again.
>
> Signed-off-by: Christian König
This looks like a good bug fix and unrelated to the rest of this series.
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 16 +++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 6 +-
> 2 files changed, 4 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> index a0780a4e3e61..62e98f1ad770 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> @@ -113,7 +113,7 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev,
> unsigned long size,
> bp.resv = resv;
> bp.preferred_domain = initial_domain;
> bp.flags = flags;
> - bp.domain = initial_domain;
> + bp.domain = initial_domain | AMDGPU_GEM_DOMAIN_CPU;
> bp.bo_ptr_size = sizeof(struct amdgpu_bo);
>
> r = amdgpu_bo_create_user(adev, , );
> @@ -332,20 +332,10 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev,
> void *data,
> }
>
> initial_domain = (u32)(0x & args->in.domains);
> -retry:
> r = amdgpu_gem_object_create(adev, size, args->in.alignment,
> -initial_domain,
> -flags, ttm_bo_type_device, resv, );
> +initial_domain, flags,
> ttm_bo_type_device,
> +resv, );
> if (r && r != -ERESTARTSYS) {
> - if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
> - flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
> - goto retry;
> - }
> -
> - if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
> - initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
> - goto retry;
> - }
> DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu,
> %d)\n",
> size, initial_domain, args->in.alignment, r);
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 974e85d8b6cc..919bbea2e3ac 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -581,11 +581,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
> bo->flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
>
> bo->tbo.bdev = >mman.bdev;
> - if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA |
> - AMDGPU_GEM_DOMAIN_GDS))
> - amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
> - else
> - amdgpu_bo_placement_from_domain(bo, bp->domain);
> + amdgpu_bo_placement_from_domain(bo, bp->domain);
> if (bp->type == ttm_bo_type_kernel)
> bo->tbo.priority = 1;
>
> --
> 2.34.1
>
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Fake dual eDP VBT fixes (rev2)
== Series Details == Series: drm/i915: Fake dual eDP VBT fixes (rev2) URL : https://patchwork.freedesktop.org/series/110693/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12434 -> Patchwork_110693v2 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_110693v2 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_110693v2, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v2/index.html Participating hosts (36 -> 34) -- Additional (3): fi-bdw-gvtdvm fi-cfl-guc bat-dg1-6 Missing(5): fi-cfl-8700k bat-adlp-4 fi-ctg-p8600 fi-kbl-x1275 bat-rpls-2 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_110693v2: ### IGT changes ### Possible regressions * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@toggle: - fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12434/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@toggle.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v2/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@toggle.html Known issues Here are the changes found in Patchwork_110693v2 that come from known issues: ### IGT changes ### Issues hit * igt@gem_lmem_swapping@verify-random: - fi-cfl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v2/fi-cfl-guc/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-dg1-6: NOTRUN -> [SKIP][4] ([i915#4083]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v2/bat-dg1-6/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][5] ([i915#4079]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v2/bat-dg1-6/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][6] ([i915#4077]) +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v2/bat-dg1-6/igt@gem_tiled_fence_bl...@basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg1-6: NOTRUN -> [SKIP][7] ([i915#7561]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v2/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rps@basic-api: - bat-dg1-6: NOTRUN -> [SKIP][8] ([i915#6621]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v2/bat-dg1-6/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_heartbeat: - fi-apl-guc: [PASS][9] -> [DMESG-FAIL][10] ([i915#5334]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12434/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v2/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_suspend@basic-s2idle-without-i915: - fi-bdw-gvtdvm: NOTRUN -> [INCOMPLETE][11] ([i915#146]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v2/fi-bdw-gvtdvm/igt@i915_susp...@basic-s2idle-without-i915.html * igt@i915_suspend@basic-s3-without-i915: - fi-rkl-11600: [PASS][12] -> [INCOMPLETE][13] ([i915#4817]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12434/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v2/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg1-6: NOTRUN -> [SKIP][14] ([i915#4215]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v2/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_addfb_basic@tile-pitch-mismatch: - bat-dg1-6: NOTRUN -> [SKIP][15] ([i915#4212]) +7 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v2/bat-dg1-6/igt@kms_addfb_ba...@tile-pitch-mismatch.html * igt@kms_chamelium@dp-crc-fast: - fi-cfl-guc: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +8 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v2/fi-cfl-guc/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@hdmi-crc-fast: - bat-dg1-6: NOTRUN -> [SKIP][17] ([fdo#111827]) +8 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110693v2/bat-dg1-6/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-bdw-gvtdvm:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fake dual eDP VBT fixes (rev2)
== Series Details == Series: drm/i915: Fake dual eDP VBT fixes (rev2) URL : https://patchwork.freedesktop.org/series/110693/ State : warning == Summary == Error: dim checkpatch failed 511c04a85e13 drm/i915: Introduce intel_panel_init_alloc() a4be5e4ce2c8 drm/i915: Do panel VBT init early if the VBT declares an explicit panel type 9d9ac5b9e9fc drm/i915: Generalize the PPS vlv_pipe_check() stuff 019ac31fe0fb drm/i915: Try to use the correct power sequencer intiially on bxt/glk a793e11f3eb7 drm/i915: Extend dual PPS handlind for ICP+ 4623ab0d30ec drm/i915: Reject unusablee power sequencers b1be98eb02a0 drm/i915: Print the PPS registers using consistent format 91b6e552079c drm/i915: Fix whitespace -:23: WARNING:LONG_LINE: line length of 110 exceeds 100 columns #23: FILE: drivers/gpu/drm/i915/display/intel_pps.c:538: +#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) total: 0 errors, 1 warnings, 0 checks, 8 lines checked b9ab0185fcf8 drm/i915: Improve PPS debugs
[Intel-gfx] [PATCH v2 3/9] drm/i915: Generalize the PPS vlv_pipe_check() stuff
From: Ville Syrjälä
Restate the vlv_pipe_check() stuff in terms of PPS index
(rather than pipe, which it is on VLV/CHV) so that we can
reuse this same mechanim on other platforms as well.
Cc: Animesh Manna
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_pps.c | 27 ++--
1 file changed, 11 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 9bbf41a076f7..41ab12fcce0e 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -234,31 +234,26 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
return backlight_controller;
}
-typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
- enum pipe pipe);
+typedef bool (*pps_check)(struct drm_i915_private *dev_priv, int pps_idx);
-static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
- enum pipe pipe)
+static bool pps_has_pp_on(struct drm_i915_private *dev_priv, int pps_idx)
{
- return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON;
+ return intel_de_read(dev_priv, PP_STATUS(pps_idx)) & PP_ON;
}
-static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
- enum pipe pipe)
+static bool pps_has_vdd_on(struct drm_i915_private *dev_priv, int pps_idx)
{
- return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD;
+ return intel_de_read(dev_priv, PP_CONTROL(pps_idx)) & EDP_FORCE_VDD;
}
-static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
-enum pipe pipe)
+static bool pps_any(struct drm_i915_private *dev_priv, int pps_idx)
{
return true;
}
static enum pipe
vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
-enum port port,
-vlv_pipe_check pipe_check)
+enum port port, pps_check check)
{
enum pipe pipe;
@@ -269,7 +264,7 @@ vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
if (port_sel != PANEL_PORT_SELECT_VLV(port))
continue;
- if (!pipe_check(dev_priv, pipe))
+ if (!check(dev_priv, pipe))
continue;
return pipe;
@@ -290,15 +285,15 @@ vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp)
/* try to find a pipe with this port selected */
/* first pick one where the panel is on */
intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
- vlv_pipe_has_pp_on);
+ pps_has_pp_on);
/* didn't find one? pick one where vdd is on */
if (intel_dp->pps.pps_pipe == INVALID_PIPE)
intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
-
vlv_pipe_has_vdd_on);
+ pps_has_vdd_on);
/* didn't find one? pick one with just the correct port */
if (intel_dp->pps.pps_pipe == INVALID_PIPE)
intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
- vlv_pipe_any);
+ pps_any);
/* didn't find one? just let vlv_power_sequencer_pipe() pick one when
needed */
if (intel_dp->pps.pps_pipe == INVALID_PIPE) {
--
2.37.4
[Intel-gfx] [PATCH v2 6/9] drm/i915: Reject unusablee power sequencers
From: Ville Syrjälä
On ICP-ADP the pins used by the second PPS can be alternatively
muxed to some other function. In that case the second power
sequencer is unusable.
Unfortunately (on my ADL Thinkpad T14 gen3 at least) the
BIOS still likes to enable the VDD on the second PPS (due
to the VBT declaring the second bogus eDP panel) even when
not correctly muxed, so we need to deal with it somehow.
For now let's just initialize the PPS as normal, and then
use the normal eDP probe failure VDD off path to turn it off
(and release the wakeref the PPS init grabbed). The
alternative of just declaring that the platform has a single
PPS doesn't really work since it would cause the second eDP
probe to also try to use the first PPS and thus clobber the
state for the first (real) eDP panel.
Cc: Animesh Manna
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 12 -
drivers/gpu/drm/i915/display/intel_pps.c | 34 +---
drivers/gpu/drm/i915/display/intel_pps.h | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 1 +
4 files changed, 38 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index c1bebe77ed8e..9deaa5e3632a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5283,7 +5283,17 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
intel_bios_init_panel_early(dev_priv, _connector->panel,
encoder->devdata);
- intel_pps_init(intel_dp);
+ if (!intel_pps_init(intel_dp)) {
+ drm_info(_priv->drm,
+"[ENCODER:%d:%s] unusable PPS, disabling eDP\n",
+encoder->base.base.id, encoder->base.name);
+ /*
+* The BIOS may have still enabled VDD on the PPS even
+* though it's unusable. Make sure we turn it back off
+* and to release the power domain references/etc.
+*/
+ goto out_vdd_off;
+ }
/* Cache DPCD and EDID for edp. */
has_dpcd = intel_edp_init_dpcd(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 77b0a4f27abc..d18c1c58dfcf 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -327,6 +327,18 @@ static int intel_num_pps(struct drm_i915_private *i915)
return 1;
}
+static bool intel_pps_is_valid(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+ if (intel_dp->pps.pps_idx == 1 &&
+ INTEL_PCH_TYPE(i915) >= PCH_ICP &&
+ INTEL_PCH_TYPE(i915) < PCH_MTP)
+ return intel_de_read(i915, SOUTH_CHICKEN1) &
ICP_SECOND_PPS_IO_SELECT;
+
+ return true;
+}
+
static int
bxt_initial_pps_idx(struct drm_i915_private *i915, pps_check check)
{
@@ -340,7 +352,7 @@ bxt_initial_pps_idx(struct drm_i915_private *i915,
pps_check check)
return -1;
}
-static void
+static bool
pps_initial_setup(struct intel_dp *intel_dp)
{
struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
@@ -351,7 +363,7 @@ pps_initial_setup(struct intel_dp *intel_dp)
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
vlv_initial_power_sequencer_setup(intel_dp);
- return;
+ return true;
}
/* first ask the VBT */
@@ -377,13 +389,14 @@ pps_initial_setup(struct intel_dp *intel_dp)
"[ENCODER:%d:%s] no initial power sequencer,
assuming %d\n",
encoder->base.base.id, encoder->base.name,
intel_dp->pps.pps_idx);
- return;
+ } else {
+ drm_dbg_kms(>drm,
+ "[ENCODER:%d:%s] initial power sequencer: %d\n",
+ encoder->base.base.id, encoder->base.name,
+ intel_dp->pps.pps_idx);
}
- drm_dbg_kms(>drm,
- "[ENCODER:%d:%s] initial power sequencer: %d\n",
- encoder->base.base.id, encoder->base.name,
- intel_dp->pps.pps_idx);
+ return intel_pps_is_valid(intel_dp);
}
void intel_pps_reset_all(struct drm_i915_private *dev_priv)
@@ -1504,9 +1517,10 @@ void intel_pps_encoder_reset(struct intel_dp *intel_dp)
}
}
-void intel_pps_init(struct intel_dp *intel_dp)
+bool intel_pps_init(struct intel_dp *intel_dp)
{
intel_wakeref_t wakeref;
+ bool ret;
intel_dp->pps.initializing = true;
INIT_DELAYED_WORK(_dp->pps.panel_vdd_work, edp_panel_vdd_work);
@@ -1514,12 +1528,14 @@ void intel_pps_init(struct intel_dp *intel_dp)
pps_init_timestamps(intel_dp);
with_intel_pps_lock(intel_dp, wakeref) {
- pps_initial_setup(intel_dp);
+
[Intel-gfx] [PATCH v2 9/9] drm/i915: Improve PPS debugs
From: Ville Syrjälä
Always include both the encoder and PPS instance information
in the debug prints so that we know what piece of hardware
we're actually dealing with.
Cc: Animesh Manna
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_pps.c | 184 +++
1 file changed, 121 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 880c530d5832..98ae7836c8ab 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -22,6 +22,36 @@ static void vlv_steal_power_sequencer(struct
drm_i915_private *dev_priv,
static void pps_init_delays(struct intel_dp *intel_dp);
static void pps_init_registers(struct intel_dp *intel_dp, bool
force_disable_vdd);
+static const char *pps_name(struct drm_i915_private *i915,
+ struct intel_pps *pps)
+{
+ if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
+ switch (pps->pps_pipe) {
+ case PIPE_A:
+ return "PPS A";
+ case PIPE_B:
+ return "PPS B";
+ case PIPE_C:
+ return "PPS C";
+ default:
+ MISSING_CASE(pps->pps_pipe);
+ break;
+ }
+ } else {
+ switch (pps->pps_idx) {
+ case 0:
+ return "PPS 0";
+ case 1:
+ return "PPS 1";
+ default:
+ MISSING_CASE(pps->pps_idx);
+ break;
+ }
+ }
+
+ return "PPS ";
+}
+
intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -60,15 +90,15 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
if (drm_WARN(_priv->drm,
intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
-"skipping pipe %c power sequencer kick due to
[ENCODER:%d:%s] being active\n",
-pipe_name(pipe), dig_port->base.base.base.id,
-dig_port->base.base.name))
+"skipping %s kick due to [ENCODER:%d:%s] being active\n",
+pps_name(dev_priv, _dp->pps),
+dig_port->base.base.base.id, dig_port->base.base.name))
return;
drm_dbg_kms(_priv->drm,
- "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
- pipe_name(pipe), dig_port->base.base.base.id,
- dig_port->base.base.name);
+ "kicking %s for [ENCODER:%d:%s]\n",
+ pps_name(dev_priv, _dp->pps),
+ dig_port->base.base.base.id, dig_port->base.base.name);
/* Preserve the BIOS-computed detected bit. This is
* supposed to be read-only.
@@ -95,7 +125,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(dev_priv))) {
drm_err(_priv->drm,
- "Failed to force on pll for pipe %c!\n",
+ "Failed to force on PLL for pipe %c!\n",
pipe_name(pipe));
return;
}
@@ -190,10 +220,9 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
intel_dp->pps.pps_pipe = pipe;
drm_dbg_kms(_priv->drm,
- "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
- pipe_name(intel_dp->pps.pps_pipe),
- dig_port->base.base.base.id,
- dig_port->base.base.name);
+ "picked %s for [ENCODER:%d:%s]\n",
+ pps_name(dev_priv, _dp->pps),
+ dig_port->base.base.base.id, dig_port->base.base.name);
/* init power sequencer on this pipe and port */
pps_init_delays(intel_dp);
@@ -297,17 +326,15 @@ vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp)
/* didn't find one? just let vlv_power_sequencer_pipe() pick one when
needed */
if (intel_dp->pps.pps_pipe == INVALID_PIPE) {
drm_dbg_kms(_priv->drm,
- "no initial power sequencer for [ENCODER:%d:%s]\n",
- dig_port->base.base.base.id,
- dig_port->base.base.name);
+ "[ENCODER:%d:%s] no initial power sequencer\n",
+ dig_port->base.base.base.id,
dig_port->base.base.name);
return;
}
drm_dbg_kms(_priv->drm,
- "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
- dig_port->base.base.base.id,
- dig_port->base.base.name,
- pipe_name(intel_dp->pps.pps_pipe));
+
[Intel-gfx] [PATCH v2 7/9] drm/i915: Print the PPS registers using consistent format
From: Ville Syrjälä
Use the consistent format when dumping out the PPS control/status
registers. Helps with pattern matching.
Cc: Animesh Manna
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_pps.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index d18c1c58dfcf..f6bc896338de 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -527,7 +527,8 @@ void intel_pps_check_power_unlocked(struct intel_dp
*intel_dp)
if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
drm_WARN(_priv->drm, 1,
"eDP powered off while attempting aux channel
communication.\n");
- drm_dbg_kms(_priv->drm, "Status 0x%08x Control 0x%08x\n",
+ drm_dbg_kms(_priv->drm,
+ "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
}
@@ -559,7 +560,7 @@ static void wait_panel_status(struct intel_dp *intel_dp,
pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
drm_dbg_kms(_priv->drm,
- "mask %08x value %08x status %08x control %08x\n",
+ "mask: 0x%08x value: 0x%08x PP_STATUS: 0x%08x PP_CONTROL:
0x%08x\n",
mask, value,
intel_de_read(dev_priv, pp_stat_reg),
intel_de_read(dev_priv, pp_ctrl_reg));
@@ -567,7 +568,7 @@ static void wait_panel_status(struct intel_dp *intel_dp,
if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
mask, value, 5000))
drm_err(_priv->drm,
- "Panel status timeout: status %08x control %08x\n",
+ "Panel status timeout: PP_STATUS: 0x%08x PP_CONTROL:
0x%08x\n",
intel_de_read(dev_priv, pp_stat_reg),
intel_de_read(dev_priv, pp_ctrl_reg));
--
2.37.4
[Intel-gfx] [PATCH v2 8/9] drm/i915: Fix whitespace
From: Ville Syrjälä Stray spaces have snuck in where everything else uses tabs. Cc: Animesh Manna Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_pps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index f6bc896338de..880c530d5832 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -535,7 +535,7 @@ void intel_pps_check_power_unlocked(struct intel_dp *intel_dp) } #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) -#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) +#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) -- 2.37.4
[Intel-gfx] [PATCH v2 5/9] drm/i915: Extend dual PPS handlind for ICP+
From: Ville Syrjälä
On the PCH side the second PPS was introduced in ICP. Let's
make sure we examine both power sequencer on ICP+ as well.
Note that DG1/2 south block only has the single PPS, so need
to exclude the fake DG1/2 PCHs.
Cc: Animesh Manna
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_pps.c | 44 +---
1 file changed, 32 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index d8d2f22f3e0c..77b0a4f27abc 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -310,10 +310,27 @@ vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp)
pipe_name(intel_dp->pps.pps_pipe));
}
+static int intel_num_pps(struct drm_i915_private *i915)
+{
+ if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ return 2;
+
+ if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
+ return 2;
+
+ if (INTEL_PCH_TYPE(i915) >= PCH_DG1)
+ return 1;
+
+ if (INTEL_PCH_TYPE(i915) >= PCH_ICP)
+ return 2;
+
+ return 1;
+}
+
static int
bxt_initial_pps_idx(struct drm_i915_private *i915, pps_check check)
{
- int pps_idx, pps_num = 2;
+ int pps_idx, pps_num = intel_num_pps(i915);
for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
if (check(i915, pps_idx))
@@ -337,12 +354,13 @@ pps_initial_setup(struct intel_dp *intel_dp)
return;
}
- if (!IS_GEMINILAKE(i915) && !IS_BROXTON(i915))
- return;
-
/* first ask the VBT */
- intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller;
- if (drm_WARN_ON(>drm, intel_dp->pps.pps_idx >= 2))
+ if (intel_num_pps(i915) > 1)
+ intel_dp->pps.pps_idx =
connector->panel.vbt.backlight.controller;
+ else
+ intel_dp->pps.pps_idx = 0;
+
+ if (drm_WARN_ON(>drm, intel_dp->pps.pps_idx >=
intel_num_pps(i915)))
intel_dp->pps.pps_idx = -1;
/* VBT wasn't parsed yet? pick one where the panel is on */
@@ -416,7 +434,7 @@ static void intel_pps_get_registers(struct intel_dp
*intel_dp,
struct pps_registers *regs)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- int pps_idx = 0;
+ int pps_idx;
memset(regs, 0, sizeof(*regs));
@@ -424,6 +442,8 @@ static void intel_pps_get_registers(struct intel_dp
*intel_dp,
pps_idx = vlv_power_sequencer_pipe(intel_dp);
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
pps_idx = bxt_power_sequencer_idx(intel_dp);
+ else
+ pps_idx = intel_dp->pps.pps_idx;
regs->pp_ctrl = PP_CONTROL(pps_idx);
regs->pp_stat = PP_STATUS(pps_idx);
@@ -1508,7 +1528,10 @@ static void pps_init_late(struct intel_dp *intel_dp)
struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
struct intel_connector *connector = intel_dp->attached_connector;
- if (!IS_GEMINILAKE(i915) && !IS_BROXTON(i915))
+ if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ return;
+
+ if (intel_num_pps(i915) < 2)
return;
drm_WARN(>drm, connector->panel.vbt.backlight.controller >= 0 &&
@@ -1551,10 +1574,7 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private
*dev_priv)
* This w/a is needed at least on CPT/PPT, but to be sure apply it
* everywhere where registers can be write protected.
*/
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- pps_num = 2;
- else
- pps_num = 1;
+ pps_num = intel_num_pps(dev_priv);
for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx));
--
2.37.4
[Intel-gfx] [PATCH v2 4/9] drm/i915: Try to use the correct power sequencer intiially on bxt/glk
From: Ville Syrjälä
Currently on bxt/glk we just grab the power sequencer index from
the VBT data even though it may not have been parsed yet. That
could lead us to using the incorrect power sequencer during the
initial panel probe.
To avoid that let's try to read out the current state of the
power sequencer from the hardware. Unfortunately the power
sequencer no longer has anything in its registers to associate
it with the port, so the best we can do is just iterate through
the power sequencers and pick the first one. This should be
sufficient for single panel cases.
For the dual panel cases we probably need to go back to
parsing the VBT before the panel probe (and hope that
panel_type=0xff is never a thing in those cases). To that
end the code always prefers the VBT panel sequencer, if
available.
v2: Restructure a bit for upcoming icp+ dual PPS support
Cc: Animesh Manna
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_types.h| 22 +++--
drivers/gpu/drm/i915/display/intel_panel.c| 1 +
drivers/gpu/drm/i915/display/intel_pps.c | 96 +--
3 files changed, 102 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index cc64e787e401..32e8b2fc3cc6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -330,7 +330,7 @@ struct intel_vbt_panel_data {
bool present;
bool active_low_pwm;
u8 min_brightness; /* min_brightness/255 of max */
- u8 controller; /* brightness controller number */
+ s8 controller; /* brightness controller number */
enum intel_backlight_type type;
} backlight;
@@ -1570,11 +1570,19 @@ struct intel_pps {
ktime_t panel_power_off_time;
intel_wakeref_t vdd_wakeref;
- /*
-* Pipe whose power sequencer is currently locked into
-* this port. Only relevant on VLV/CHV.
-*/
- enum pipe pps_pipe;
+ union {
+ /*
+* Pipe whose power sequencer is currently locked into
+* this port. Only relevant on VLV/CHV.
+*/
+ enum pipe pps_pipe;
+
+ /*
+* Power sequencer index. Only relevant on BXT+.
+*/
+ int pps_idx;
+ };
+
/*
* Pipe currently driving the port. Used for preventing
* the use of the PPS for any pipe currentrly driving
@@ -1583,7 +1591,7 @@ struct intel_pps {
enum pipe active_pipe;
/*
* Set if the sequencer may be reset due to a power transition,
-* requiring a reinitialization. Only relevant on BXT.
+* requiring a reinitialization. Only relevant on BXT+.
*/
bool pps_reset;
struct edp_power_seq pps_delays;
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
b/drivers/gpu/drm/i915/display/intel_panel.c
index 609fcdbd7d58..3b1004b019a8 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -666,6 +666,7 @@ void intel_panel_init_alloc(struct intel_connector
*connector)
struct intel_panel *panel = >panel;
connector->panel.vbt.panel_type = -1;
+ connector->panel.vbt.backlight.controller = -1;
INIT_LIST_HEAD(>fixed_modes);
}
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
b/drivers/gpu/drm/i915/display/intel_pps.c
index 41ab12fcce0e..d8d2f22f3e0c 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -212,8 +212,7 @@ static int
bxt_power_sequencer_idx(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_connector *connector = intel_dp->attached_connector;
- int backlight_controller = connector->panel.vbt.backlight.controller;
+ int pps_idx = intel_dp->pps.pps_idx;
lockdep_assert_held(_priv->display.pps.mutex);
@@ -221,7 +220,7 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
drm_WARN_ON(_priv->drm, !intel_dp_is_edp(intel_dp));
if (!intel_dp->pps.pps_reset)
- return backlight_controller;
+ return pps_idx;
intel_dp->pps.pps_reset = false;
@@ -231,7 +230,7 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
*/
pps_init_registers(intel_dp, false);
- return backlight_controller;
+ return pps_idx;
}
typedef bool (*pps_check)(struct drm_i915_private *dev_priv, int pps_idx);
@@ -311,6 +310,64 @@ vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp)
pipe_name(intel_dp->pps.pps_pipe));
}
+static int
+bxt_initial_pps_idx(struct drm_i915_private *i915, pps_check check)
+{
+ int pps_idx, pps_num = 2;
+
+ for (pps_idx =
[Intel-gfx] [PATCH v2 1/9] drm/i915: Introduce intel_panel_init_alloc()
From: Ville Syrjälä
Introduce a place where we can initialize connector->panel
after it's been allocated. We already have a intel_panel_init()
so had to get creative with the name and came up with
intel_panel_init_alloc().
Cc: Animesh Manna
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_connector.c | 2 +-
drivers/gpu/drm/i915/display/intel_panel.c | 7 +++
drivers/gpu/drm/i915/display/intel_panel.h | 1 +
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_connector.c
b/drivers/gpu/drm/i915/display/intel_connector.c
index 6205ddd3ded0..562da3b741e2 100644
--- a/drivers/gpu/drm/i915/display/intel_connector.c
+++ b/drivers/gpu/drm/i915/display/intel_connector.c
@@ -54,7 +54,7 @@ int intel_connector_init(struct intel_connector *connector)
__drm_atomic_helper_connector_reset(>base,
_state->base);
- INIT_LIST_HEAD(>panel.fixed_modes);
+ intel_panel_init_alloc(connector);
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
b/drivers/gpu/drm/i915/display/intel_panel.c
index 1640726bfbf6..b49228eb79e7 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -661,6 +661,13 @@ intel_panel_mode_valid(struct intel_connector *connector,
return MODE_OK;
}
+void intel_panel_init_alloc(struct intel_connector *connector)
+{
+ struct intel_panel *panel = >panel;
+
+ INIT_LIST_HEAD(>fixed_modes);
+}
+
int intel_panel_init(struct intel_connector *connector)
{
struct intel_panel *panel = >panel;
diff --git a/drivers/gpu/drm/i915/display/intel_panel.h
b/drivers/gpu/drm/i915/display/intel_panel.h
index 5c5b5b7f95b6..4b51e1c51da6 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.h
+++ b/drivers/gpu/drm/i915/display/intel_panel.h
@@ -18,6 +18,7 @@ struct intel_connector;
struct intel_crtc_state;
struct intel_encoder;
+void intel_panel_init_alloc(struct intel_connector *connector);
int intel_panel_init(struct intel_connector *connector);
void intel_panel_fini(struct intel_connector *connector);
enum drm_connector_status
--
2.37.4
[Intel-gfx] [PATCH v2 2/9] drm/i915: Do panel VBT init early if the VBT declares an explicit panel type
From: Ville Syrjälä
Lots of ADL machines out there with bogus VBTs that declare
two eDP child devices. In order for those to work we need to
figure out which power sequencer to use before we try the EDID
read. So let's do the panel VBT init early if we can, falling
back to the post-EDID init otherwise.
The post-EDID init panel_type=0xff approach of assuming the
power sequencer should already be enabled doesn't really work
with multiple eDP panels, and currently we just end up using
the same power sequencer for both eDP ports, which at least
confuses the wakeref tracking, and potentially also causes us
to toggle the VDD for the panel when we should not.
Cc: Animesh Manna
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c| 2 +-
drivers/gpu/drm/i915/display/intel_bios.c | 56 ++-
drivers/gpu/drm/i915/display/intel_bios.h | 11 ++--
.../drm/i915/display/intel_display_types.h| 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 7 ++-
drivers/gpu/drm/i915/display/intel_lvds.c | 4 +-
drivers/gpu/drm/i915/display/intel_panel.c| 1 +
drivers/gpu/drm/i915/display/intel_sdvo.c | 2 +-
drivers/gpu/drm/i915/display/vlv_dsi.c| 2 +-
9 files changed, 61 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index d16b30a2dded..ae14c794c4bc 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -2043,7 +2043,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
/* attach connector to encoder */
intel_connector_attach_encoder(intel_connector, encoder);
- intel_bios_init_panel(dev_priv, _connector->panel, NULL, NULL);
+ intel_bios_init_panel_late(dev_priv, _connector->panel, NULL,
NULL);
mutex_lock(_priv->drm.mode_config.mutex);
intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index c2987f2c2b2e..64f927f6479d 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -620,14 +620,14 @@ static void dump_pnp_id(struct drm_i915_private *i915,
static int opregion_get_panel_type(struct drm_i915_private *i915,
const struct intel_bios_encoder_data
*devdata,
- const struct edid *edid)
+ const struct edid *edid, bool use_fallback)
{
return intel_opregion_get_panel_type(i915);
}
static int vbt_get_panel_type(struct drm_i915_private *i915,
const struct intel_bios_encoder_data *devdata,
- const struct edid *edid)
+ const struct edid *edid, bool use_fallback)
{
const struct bdb_lvds_options *lvds_options;
@@ -652,7 +652,7 @@ static int vbt_get_panel_type(struct drm_i915_private *i915,
static int pnpid_get_panel_type(struct drm_i915_private *i915,
const struct intel_bios_encoder_data *devdata,
- const struct edid *edid)
+ const struct edid *edid, bool use_fallback)
{
const struct bdb_lvds_lfp_data *data;
const struct bdb_lvds_lfp_data_ptrs *ptrs;
@@ -701,9 +701,9 @@ static int pnpid_get_panel_type(struct drm_i915_private
*i915,
static int fallback_get_panel_type(struct drm_i915_private *i915,
const struct intel_bios_encoder_data
*devdata,
- const struct edid *edid)
+ const struct edid *edid, bool use_fallback)
{
- return 0;
+ return use_fallback ? 0 : -1;
}
enum panel_type {
@@ -715,13 +715,13 @@ enum panel_type {
static int get_panel_type(struct drm_i915_private *i915,
const struct intel_bios_encoder_data *devdata,
- const struct edid *edid)
+ const struct edid *edid, bool use_fallback)
{
struct {
const char *name;
int (*get_panel_type)(struct drm_i915_private *i915,
const struct intel_bios_encoder_data
*devdata,
- const struct edid *edid);
+ const struct edid *edid, bool
use_fallback);
int panel_type;
} panel_types[] = {
[PANEL_TYPE_OPREGION] = {
@@ -744,7 +744,8 @@ static int get_panel_type(struct drm_i915_private *i915,
int i;
for (i = 0; i < ARRAY_SIZE(panel_types); i++) {
- panel_types[i].panel_type = panel_types[i].get_panel_type(i915,
devdata, edid);
+ panel_types[i].panel_type = panel_types[i].get_panel_type(i915,
devdata,
+
[Intel-gfx] [PATCH v2 0/9] drm/i915: Fake dual eDP VBT fixes
From: Ville Syrjälä Here's my take on fixing *some* of the issues around the dual eDP VBTs floating around atm. I have now such a machine. Main changes in v2: - deal with the ICP-ADP second PPS pin muxing - Improve debugs all over With this my T14 gen3 now boots without WARNs, and we also remember to turn off the bogus second PPS that BIOS turned on. The one thing that doesn't work is HDMI port B that aliases with the second bogus eDP in the VBT, but fixing that mess is going to take a lot more work. Ville Syrjälä (9): drm/i915: Introduce intel_panel_init_alloc() drm/i915: Do panel VBT init early if the VBT declares an explicit panel type drm/i915: Generalize the PPS vlv_pipe_check() stuff drm/i915: Try to use the correct power sequencer intiially on bxt/glk drm/i915: Extend dual PPS handlind for ICP+ drm/i915: Reject unusablee power sequencers drm/i915: Print the PPS registers using consistent format drm/i915: Fix whitespace drm/i915: Improve PPS debugs drivers/gpu/drm/i915/display/icl_dsi.c| 2 +- drivers/gpu/drm/i915/display/intel_bios.c | 56 ++- drivers/gpu/drm/i915/display/intel_bios.h | 11 +- .../gpu/drm/i915/display/intel_connector.c| 2 +- .../drm/i915/display/intel_display_types.h| 24 +- drivers/gpu/drm/i915/display/intel_dp.c | 19 +- drivers/gpu/drm/i915/display/intel_lvds.c | 4 +- drivers/gpu/drm/i915/display/intel_panel.c| 9 + drivers/gpu/drm/i915/display/intel_panel.h| 1 + drivers/gpu/drm/i915/display/intel_pps.c | 350 +- drivers/gpu/drm/i915/display/intel_pps.h | 2 +- drivers/gpu/drm/i915/display/intel_sdvo.c | 2 +- drivers/gpu/drm/i915/display/vlv_dsi.c| 2 +- drivers/gpu/drm/i915/i915_reg.h | 1 + 14 files changed, 357 insertions(+), 128 deletions(-) -- 2.37.4
Re: [Intel-gfx] [PATCH] drm/i915/dp: wait on timeout before retry include sw delay
On Thu, Nov 24, 2022 at 12:39:25PM +0530, Arun R Murthy wrote:
> AUX HW timeout is being set to max(4000ms), consider AUX SW timeout to
^ 4ms
> be 200ms more to avoid AUX boundary read//write.
The HSD mentions a 200us extension.
> HSDES: 1409498780
>
> Signed-off-by: Arun R Murthy
> ---
> drivers/gpu/drm/i915/display/intel_dp_aux.c | 11 +--
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> index 664bebdecea7..6c1c9602518b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> @@ -293,14 +293,13 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> DP_AUX_CH_CTL_RECEIVE_ERROR);
>
> /*
> - * DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
> - * 400us delay required for errors and timeouts
> - * Timeout errors from the HW already meet this
> - * requirement so skip to next iteration
I think keeping the above still makes sense to explain why the 400us
explicit delay described in the CTS is not needed.
> + * Once the hw timeouts, before next try
> + * need to add a sw timeout of 200usec(HSD: 1409498780).
The HSD is for ICL, I can't see the bspec entry for it at bspec/33450.
WAs should have a "Wa_:" tag.
>*/
> - if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
> + if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
> + usleep_range(200, 300);
The HSD ticket implies that the WA is to increase the timeout when
polling for the BUSY flag to clear from 600us to 800us for the non-LTTPR
case and from 4ms to 4.2ms in the LTTPR case (regardless of why the BUSY
flag is cleared). This seems to match what the Windows driver does now.
i915 waits for the same condition for 10ms, so to me it looks like the
waiting here already complies with the change described by the HSD.
One difference I see is that Windows just polls for the BUSY flag
without enabling the interrupt-on-done for this, not sure if this could
cause a problem.
> continue;
> -
> + }
> if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
> usleep_range(400, 500);
> continue;
> --
> 2.25.1
>
Re: [Intel-gfx] [RFC 0/2] drm/connector: connector iterator with filtering
On 10/5/22 06:51, Jani Nikula wrote: > Currently i915 assumes all drm_connectors it encounters are embedded in > intel_connectors that i915 allocated. The drm_writeback_connector forces > a design where this is not the case; we can't provide our own connector, > and writeback embeds the drm_connector it initializes itself. > > To use drm writeback, none of the i915 connector iteration could assume > the drm connector is embedded in intel_connector. Checking this is > tedious, and would require an intermediate step with > drm_connector. Here's an idea I came up with; filtering at the drm > connector iterator level with a caller supplied function. Not too much > code, and could be used for other things as well. > We've been trying to hook up drm_writeback_connector in amdgpu and this would be really helpful. I've had to do liberal sprinkling of "!= DRM_MODE_CONNECTOR_WRITEBACK" all over the place. > Mind you, we'd still much rather modify drm writeback to allow passing > the connector i915 allocated, instead of the current midlayer design > that forces drivers to a certain model. Working around this is a bunch > of error prone and tedious code that we really could do without. > I think this would be even better but also be much more work and impact every driver that implements writeback. FWIW, there was no way for me to add writeback connector handling without KASAN. Interpreting the connector wrong in one place leads to memory corruption and undefined behavior and is almost impossible to spot without KASAN. This series is Acked-by: Harry Wentland Harry > > BR, > Jani. > > > Cc: Arun R Murthy > Cc: Dave Airlie > Cc: Laurent Pinchart > Cc: Suraj Kandpal > Cc: Ville Syrjälä > > Jani Nikula (2): > drm/connector: add connector list iteration with filtering > drm/i915: iterate intel_connectors only > > drivers/gpu/drm/drm_connector.c | 57 +++ > drivers/gpu/drm/i915/display/intel_display.c | 3 +- > .../drm/i915/display/intel_display_types.h| 7 +++ > drivers/gpu/drm/i915/display/intel_dp.c | 6 +- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +- > drivers/gpu/drm/i915/display/intel_hdcp.c | 3 +- > drivers/gpu/drm/i915/display/intel_hotplug.c | 12 ++-- > .../drm/i915/display/intel_modeset_setup.c| 6 +- > drivers/gpu/drm/i915/display/intel_opregion.c | 9 ++- > include/drm/drm_connector.h | 9 +++ > 10 files changed, 89 insertions(+), 26 deletions(-) >
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Use continuous full frame update instead of single
== Series Details == Series: drm/i915/psr: Use continuous full frame update instead of single URL : https://patchwork.freedesktop.org/series/111350/ State : success == Summary == CI Bug Log - changes from CI_DRM_12434 -> Patchwork_111350v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111350v1/index.html Participating hosts (36 -> 37) -- Additional (3): fi-bdw-gvtdvm fi-cfl-guc bat-dg1-6 Missing(2): fi-ctg-p8600 bat-adlp-4 Known issues Here are the changes found in Patchwork_111350v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_lmem_swapping@verify-random: - fi-cfl-guc: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#4613]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111350v1/fi-cfl-guc/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-dg1-6: NOTRUN -> [SKIP][2] ([i915#4083]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111350v1/bat-dg1-6/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][3] ([i915#4079]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111350v1/bat-dg1-6/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][4] ([i915#4077]) +2 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111350v1/bat-dg1-6/igt@gem_tiled_fence_bl...@basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg1-6: NOTRUN -> [SKIP][5] ([i915#7561]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111350v1/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rps@basic-api: - bat-dg1-6: NOTRUN -> [SKIP][6] ([i915#6621]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111350v1/bat-dg1-6/igt@i915_pm_...@basic-api.html * igt@i915_suspend@basic-s2idle-without-i915: - fi-bdw-gvtdvm: NOTRUN -> [INCOMPLETE][7] ([i915#146]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111350v1/fi-bdw-gvtdvm/igt@i915_susp...@basic-s2idle-without-i915.html * igt@i915_suspend@basic-s3-without-i915: - fi-rkl-11600: [PASS][8] -> [INCOMPLETE][9] ([i915#4817]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12434/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111350v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg1-6: NOTRUN -> [SKIP][10] ([i915#4215]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111350v1/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_addfb_basic@tile-pitch-mismatch: - bat-dg1-6: NOTRUN -> [SKIP][11] ([i915#4212]) +7 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111350v1/bat-dg1-6/igt@kms_addfb_ba...@tile-pitch-mismatch.html * igt@kms_chamelium@dp-crc-fast: - fi-cfl-guc: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111350v1/fi-cfl-guc/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@hdmi-crc-fast: - bat-dg1-6: NOTRUN -> [SKIP][13] ([fdo#111827]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111350v1/bat-dg1-6/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-bdw-gvtdvm: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +7 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111350v1/fi-bdw-gvtdvm/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor: - bat-dg1-6: NOTRUN -> [SKIP][15] ([i915#4103] / [i915#4213]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111350v1/bat-dg1-6/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html * igt@kms_flip@basic-plain-flip: - fi-bdw-gvtdvm: NOTRUN -> [SKIP][16] ([fdo#109271]) +38 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111350v1/fi-bdw-gvtdvm/igt@kms_f...@basic-plain-flip.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg1-6: NOTRUN -> [SKIP][17] ([fdo#109285]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111350v1/bat-dg1-6/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_psr@sprite_plane_onoff: - bat-dg1-6: NOTRUN -> [SKIP][18] ([i915#1072] / [i915#4078]) +3 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111350v1/bat-dg1-6/igt@kms_psr@sprite_plane_onoff.html * igt@kms_setmode@basic-clone-single-crtc: - bat-dg1-6:
Re: [Intel-gfx] [PATCH] drm/i915/huc: fix leak of debug object in huc load fence on driver unload
On Thu, Nov 10, 2022 at 04:56:51PM -0800, Daniele Ceraolo Spurio wrote:
> The fence is always initialized in huc_init_early, but the cleanup in
> huc_fini is only being run if HuC is enabled. This causes a leaking of
> the debug object when HuC is disabled/not supported, which can in turn
> trigger a warning if we try to register a new debug offset at the same
> address on driver reload.
>
> To fix the issue, make sure to always run the cleanup code.
This oopsing in ci now. Somehow the patchwork run did not
hit that oops.
>
> Reported-by: Tvrtko Ursulin
> Reported-by: Brian Norris
> Fixes: 27536e03271d ("drm/i915/huc: track delayed HuC load with a fence")
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Tvrtko Ursulin
> Cc: Brian Norris
> Cc: Alan Previn
> Cc: John Harrison
> ---
>
> Note: I didn't manage to repro the reported warning, but I did confirm
> that we weren't correctly calling i915_sw_fence_fini and that this patch
> fixes that.
>
> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 12 +++-
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 1 +
> 2 files changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> index fbc8bae14f76..83735a1528fe 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> @@ -300,13 +300,15 @@ int intel_huc_init(struct intel_huc *huc)
>
> void intel_huc_fini(struct intel_huc *huc)
> {
> - if (!intel_uc_fw_is_loadable(>fw))
> - return;
> -
> + /*
> + * the fence is initialized in init_early, so we need to clean it up
> + * even if HuC loading is off.
> + */
> delayed_huc_load_complete(huc);
> -
> i915_sw_fence_fini(>delayed_load.fence);
> - intel_uc_fw_fini(>fw);
> +
> + if (intel_uc_fw_is_loadable(>fw))
> + intel_uc_fw_fini(>fw);
> }
>
> void intel_huc_suspend(struct intel_huc *huc)
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index dbd048b77e19..41f08b55790e 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -718,6 +718,7 @@ int intel_uc_runtime_resume(struct intel_uc *uc)
>
> static const struct intel_uc_ops uc_ops_off = {
> .init_hw = __uc_check_hw,
> + .fini = __uc_fini, /* to clean-up the init_early initialization */
> };
>
> static const struct intel_uc_ops uc_ops_on = {
> --
> 2.37.3
--
Ville Syrjälä
Intel
[Intel-gfx] [PATCH] drm/i915/psr: Use continuous full frame update instead of single
Currently we are observing occasionally display flickering or complete
freeze. This is narrowed down to be caused by single full frame update
(SFF).
SFF bit after it's written gets cleared by HW in subsequent vblank
i.e. when the update is sent to the panel. SFF bit is required to be
written together with partial frame update (PFU) bit. After the bit
gets cleared by the HW psr2 man trk ctl register still contains PFU
bit. If there is subsequent update for any reason we will end up
having selective update/fetch configuration where start line is 0 and
end line is 0. Also selective fetch configuration for the planes is
not properly performed. This seems to be causing problems with some
panels.
Fix this by using continuous full frame update instead and switch to
partial frame update only when selective update area is properly
calculated and configured.
This is also workaround for HSD 14014971508
Cc: Ville Syrjälä
Cc: José Roberto de Souza
Cc: Mika Kahola
Reported-by: Lee Shawn C
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 21 ++---
1 file changed, 2 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 5b678916e6db..41b0718eb3a1 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1480,13 +1480,6 @@ static u32 man_trk_ctl_enable_bit_get(struct
drm_i915_private *dev_priv)
PSR2_MAN_TRK_CTL_ENABLE;
}
-static u32 man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private
*dev_priv)
-{
- return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ?
- ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME :
- PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
-}
-
static u32 man_trk_ctl_partial_frame_bit_get(struct drm_i915_private *dev_priv)
{
return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ?
@@ -1510,7 +1503,7 @@ static void psr_force_hw_tracking_exit(struct intel_dp
*intel_dp)
PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
man_trk_ctl_enable_bit_get(dev_priv) |
man_trk_ctl_partial_frame_bit_get(dev_priv) |
- man_trk_ctl_single_full_frame_bit_get(dev_priv));
+ man_trk_ctl_continuos_full_frame(dev_priv));
/*
* Display WA #0884: skl+
@@ -1624,11 +1617,7 @@ static void psr2_man_trk_ctl_calc(struct
intel_crtc_state *crtc_state,
val |= man_trk_ctl_partial_frame_bit_get(dev_priv);
if (full_update) {
- /*
-* Not applying Wa_14014971508:adlp as we do not support the
-* feature that requires this workaround.
-*/
- val |= man_trk_ctl_single_full_frame_bit_get(dev_priv);
+ val |= man_trk_ctl_continuos_full_frame(dev_priv);
goto exit;
}
@@ -2306,16 +2295,10 @@ static void _psr_flush_handle(struct intel_dp *intel_dp)
if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
/* can we turn CFF off? */
if (intel_dp->psr.busy_frontbuffer_bits == 0) {
- u32 val = man_trk_ctl_enable_bit_get(dev_priv) |
-
man_trk_ctl_partial_frame_bit_get(dev_priv) |
-
man_trk_ctl_single_full_frame_bit_get(dev_priv);
-
/*
* turn continuous full frame off and do a
single
* full frame
*/
- intel_de_write(dev_priv,
PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
- val);
intel_de_write(dev_priv,
CURSURFLIVE(intel_dp->psr.pipe), 0);
intel_dp->psr.psr2_sel_fetch_cff_enabled =
false;
}
--
2.34.1
Re: [Intel-gfx] [PATCH 7/9] drm/i915: stop using ttm_bo_wait
Am 25.11.22 um 12:14 schrieb Tvrtko Ursulin:
+ Matt
On 25/11/2022 10:21, Christian König wrote:
TTM is just wrapping core DMA functionality here, remove the mid-layer.
No functional change.
Signed-off-by: Christian König
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 5247d88b3c13..d409a77449a3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -599,13 +599,16 @@ i915_ttm_resource_get_st(struct
drm_i915_gem_object *obj,
static int i915_ttm_truncate(struct drm_i915_gem_object *obj)
{
struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
- int err;
+ long err;
WARN_ON_ONCE(obj->mm.madv == I915_MADV_WILLNEED);
- err = ttm_bo_wait(bo, true, false);
- if (err)
+ err = dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP,
+ true, 15 * HZ);
This 15 second stuck out a bit for me and then on a slightly deeper
look it seems this timeout will "leak" into a few of i915 code paths.
If we look at the difference between the legacy shmem and ttm backend
I am not sure if the legacy one is blocking or not - but if it can
block I don't think it would have an arbitrary timeout like this. Matt
your thoughts?
That's exactly the reason why I try to remove the ttm_bo_wait() as mid
layer here. It hides the fact that we don't wait forever for BOs to
become idle.
This is functional identical to the old code. If you want some other
behavior feel free to note what's desired and I will implement it.
Regards,
Christian.
Regards,
Tvrtko
+ if (err < 0)
return err;
+ if (err == 0)
+ return -EBUSY;
err = i915_ttm_move_notify(bo);
if (err)
Re: [Intel-gfx] [RFC 0/2] drm/connector: connector iterator with filtering
On Wed, 05 Oct 2022, Jani Nikula wrote: > Currently i915 assumes all drm_connectors it encounters are embedded in > intel_connectors that i915 allocated. The drm_writeback_connector forces > a design where this is not the case; we can't provide our own connector, > and writeback embeds the drm_connector it initializes itself. > > To use drm writeback, none of the i915 connector iteration could assume > the drm connector is embedded in intel_connector. Checking this is > tedious, and would require an intermediate step with > drm_connector. Here's an idea I came up with; filtering at the drm > connector iterator level with a caller supplied function. Not too much > code, and could be used for other things as well. > > Mind you, we'd still much rather modify drm writeback to allow passing > the connector i915 allocated, instead of the current midlayer design > that forces drivers to a certain model. Working around this is a bunch > of error prone and tedious code that we really could do without. Any feedback on this one? BR, Jani. > > > BR, > Jani. > > > Cc: Arun R Murthy > Cc: Dave Airlie > Cc: Laurent Pinchart > Cc: Suraj Kandpal > Cc: Ville Syrjälä > > Jani Nikula (2): > drm/connector: add connector list iteration with filtering > drm/i915: iterate intel_connectors only > > drivers/gpu/drm/drm_connector.c | 57 +++ > drivers/gpu/drm/i915/display/intel_display.c | 3 +- > .../drm/i915/display/intel_display_types.h| 7 +++ > drivers/gpu/drm/i915/display/intel_dp.c | 6 +- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +- > drivers/gpu/drm/i915/display/intel_hdcp.c | 3 +- > drivers/gpu/drm/i915/display/intel_hotplug.c | 12 ++-- > .../drm/i915/display/intel_modeset_setup.c| 6 +- > drivers/gpu/drm/i915/display/intel_opregion.c | 9 ++- > include/drm/drm_connector.h | 9 +++ > 10 files changed, 89 insertions(+), 26 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/9] drm/amdgpu: generally allow over-commit during BO allocation
== Series Details == Series: series starting with [1/9] drm/amdgpu: generally allow over-commit during BO allocation URL : https://patchwork.freedesktop.org/series/111337/ State : success == Summary == CI Bug Log - changes from CI_DRM_12434 -> Patchwork_111337v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111337v1/index.html Participating hosts (36 -> 39) -- Additional (4): fi-cml-u2 fi-bdw-gvtdvm fi-cfl-guc bat-dg1-6 Missing(1): fi-ctg-p8600 Known issues Here are the changes found in Patchwork_111337v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - fi-cml-u2: NOTRUN -> [SKIP][1] ([i915#7456]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111337v1/fi-cml-u2/igt@debugfs_t...@basic-hwmon.html * igt@gem_exec_suspend@basic-s3@smem: - fi-rkl-11600: [PASS][2] -> [FAIL][3] ([fdo#103375]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12434/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111337v1/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - fi-cml-u2: NOTRUN -> [SKIP][4] ([i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111337v1/fi-cml-u2/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@verify-random: - fi-cfl-guc: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111337v1/fi-cfl-guc/igt@gem_lmem_swapp...@verify-random.html - fi-cml-u2: NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111337v1/fi-cml-u2/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-dg1-6: NOTRUN -> [SKIP][7] ([i915#4083]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111337v1/bat-dg1-6/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][8] ([i915#4079]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111337v1/bat-dg1-6/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][9] ([i915#4077]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111337v1/bat-dg1-6/igt@gem_tiled_fence_bl...@basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg1-6: NOTRUN -> [SKIP][10] ([i915#7561]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111337v1/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rps@basic-api: - bat-dg1-6: NOTRUN -> [SKIP][11] ([i915#6621]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111337v1/bat-dg1-6/igt@i915_pm_...@basic-api.html * igt@i915_suspend@basic-s2idle-without-i915: - fi-bdw-gvtdvm: NOTRUN -> [INCOMPLETE][12] ([i915#146]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111337v1/fi-bdw-gvtdvm/igt@i915_susp...@basic-s2idle-without-i915.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg1-6: NOTRUN -> [SKIP][13] ([i915#4215]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111337v1/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_addfb_basic@tile-pitch-mismatch: - bat-dg1-6: NOTRUN -> [SKIP][14] ([i915#4212]) +7 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111337v1/bat-dg1-6/igt@kms_addfb_ba...@tile-pitch-mismatch.html * igt@kms_chamelium@common-hpd-after-suspend: - bat-adlp-4: NOTRUN -> [SKIP][15] ([fdo#111827]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111337v1/bat-adlp-4/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@dp-crc-fast: - fi-cfl-guc: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +8 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111337v1/fi-cfl-guc/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@hdmi-crc-fast: - bat-dg1-6: NOTRUN -> [SKIP][17] ([fdo#111827]) +8 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111337v1/bat-dg1-6/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-bdw-gvtdvm: NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +7 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111337v1/fi-bdw-gvtdvm/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_chamelium@vga-hpd-fast: - fi-cml-u2: NOTRUN -> [SKIP][19] ([fdo#109284] / [fdo#111827]) +8 similar issues [19]:
[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/9] drm/amdgpu: generally allow over-commit during BO allocation
== Series Details == Series: series starting with [1/9] drm/amdgpu: generally allow over-commit during BO allocation URL : https://patchwork.freedesktop.org/series/111337/ State : warning == Summary == Error: make htmldocs had i915 warnings ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/9] drm/amdgpu: generally allow over-commit during BO allocation
== Series Details == Series: series starting with [1/9] drm/amdgpu: generally allow over-commit during BO allocation URL : https://patchwork.freedesktop.org/series/111337/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/9] drm/amdgpu: generally allow over-commit during BO allocation
== Series Details == Series: series starting with [1/9] drm/amdgpu: generally allow over-commit during BO allocation URL : https://patchwork.freedesktop.org/series/111337/ State : warning == Summary == Error: dim checkpatch failed e90cbfda09c3 drm/amdgpu: generally allow over-commit during BO allocation -:74: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: "Christian König" ' != 'Signed-off-by: Christian König ' total: 0 errors, 1 warnings, 0 checks, 42 lines checked 709a97d8ed9c drm/ttm: remove ttm_bo_(un)lock_delayed_workqueue -:168: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: "Christian König" ' != 'Signed-off-by: Christian König ' total: 0 errors, 1 warnings, 0 checks, 119 lines checked 015bfda0abf6 drm/ttm: use per BO cleanup workers -:301: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #301: FILE: include/drm/ttm/ttm_bo_api.h:137: + unsigned priority; -:302: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #302: FILE: include/drm/ttm/ttm_bo_api.h:138: + unsigned pin_count; -:355: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: "Christian König" ' != 'Signed-off-by: Christian König ' total: 0 errors, 3 warnings, 0 checks, 290 lines checked e3a743aadfe8 drm/ttm: merge ttm_bo_api.h and ttm_bo_driver.h -:11: WARNING:TYPO_SPELLING: 'unecessary' may be misspelled - perhaps 'unnecessary'? #11: drop unecessary includes from the header. ^^ -:1050: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #1050: rename from include/drm/ttm/ttm_bo_api.h -:1166: ERROR:CODE_INDENT: code indent should use tabs where possible #1166: FILE: include/drm/ttm/ttm_bo.h:135: +struct sg_table *sg;$ -:1166: WARNING:LEADING_SPACE: please, no spaces at the start of a line #1166: FILE: include/drm/ttm/ttm_bo.h:135: +struct sg_table *sg;$ -:1225: WARNING:LINE_SPACING: Missing a blank line after declarations #1225: FILE: include/drm/ttm/ttm_bo.h:246: + bool success; + if (WARN_ON(ticket)) -:1389: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u32' over 'uint32_t' #1389: FILE: include/drm/ttm/ttm_bo.h:364: +uint32_t alignment, struct ttm_operation_ctx *ctx, -:1391: WARNING:SPACING: Unnecessary space before function pointer arguments #1391: FILE: include/drm/ttm/ttm_bo.h:366: +void (*destroy) (struct ttm_buffer_object *)); -:1394: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u32' over 'uint32_t' #1394: FILE: include/drm/ttm/ttm_bo.h:369: +uint32_t alignment, bool interruptible, -:1396: WARNING:SPACING: Unnecessary space before function pointer arguments #1396: FILE: include/drm/ttm/ttm_bo.h:371: +void (*destroy) (struct ttm_buffer_object *)); -:1515: ERROR:CODE_INDENT: code indent should use tabs where possible #1515: FILE: include/drm/ttm/ttm_bo.h:413: + u32 num_pages,$ -:1515: WARNING:LEADING_SPACE: please, no spaces at the start of a line #1515: FILE: include/drm/ttm/ttm_bo.h:413: + u32 num_pages,$ -:1516: ERROR:CODE_INDENT: code indent should use tabs where possible #1516: FILE: include/drm/ttm/ttm_bo.h:414: + struct ttm_kmap_iter *dst_iter,$ -:1516: WARNING:LEADING_SPACE: please, no spaces at the start of a line #1516: FILE: include/drm/ttm/ttm_bo.h:414: + struct ttm_kmap_iter *dst_iter,$ -:1517: ERROR:CODE_INDENT: code indent should use tabs where possible #1517: FILE: include/drm/ttm/ttm_bo.h:415: + struct ttm_kmap_iter *src_iter);$ -:1517: WARNING:LEADING_SPACE: please, no spaces at the start of a line #1517: FILE: include/drm/ttm/ttm_bo.h:415: + struct ttm_kmap_iter *src_iter);$ -:1856: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: "Christian König" ' != 'Signed-off-by: Christian König ' total: 4 errors, 10 warnings, 2 checks, 1234 lines checked 7ef9eceb4636 drm/nouveau: stop using ttm_bo_wait -:67: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: "Christian König" ' != 'Signed-off-by: Christian König ' total: 0 errors, 1 warnings, 0 checks, 42 lines checked 3e3fc83b8053 drm/qxl: stop using ttm_bo_wait -:47: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: "Christian König" ' != 'Signed-off-by: Christian König ' total: 0 errors, 1 warnings, 0 checks, 28 lines checked 98ec1b67a785 drm/i915: stop using ttm_bo_wait -:37: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: "Christian König" ' != 'Signed-off-by: Christian König ' total: 0 errors, 1 warnings, 0 checks, 19 lines checked 2b6141fc5caa drm/ttm: use ttm_bo_wait_ctx instead of ttm_bo_wait -:34:
Re: [Intel-gfx] [PATCH 7/9] drm/i915: stop using ttm_bo_wait
+ Matt
On 25/11/2022 10:21, Christian König wrote:
TTM is just wrapping core DMA functionality here, remove the mid-layer.
No functional change.
Signed-off-by: Christian König
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 5247d88b3c13..d409a77449a3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -599,13 +599,16 @@ i915_ttm_resource_get_st(struct drm_i915_gem_object *obj,
static int i915_ttm_truncate(struct drm_i915_gem_object *obj)
{
struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
- int err;
+ long err;
WARN_ON_ONCE(obj->mm.madv == I915_MADV_WILLNEED);
- err = ttm_bo_wait(bo, true, false);
- if (err)
+ err = dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP,
+ true, 15 * HZ);
This 15 second stuck out a bit for me and then on a slightly deeper look
it seems this timeout will "leak" into a few of i915 code paths. If we
look at the difference between the legacy shmem and ttm backend I am not
sure if the legacy one is blocking or not - but if it can block I don't
think it would have an arbitrary timeout like this. Matt your thoughts?
Regards,
Tvrtko
+ if (err < 0)
return err;
+ if (err == 0)
+ return -EBUSY;
err = i915_ttm_move_notify(bo);
if (err)
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: add intel_display_limits.h for key enums
== Series Details == Series: drm/i915/display: add intel_display_limits.h for key enums URL : https://patchwork.freedesktop.org/series/111334/ State : success == Summary == CI Bug Log - changes from CI_DRM_12434 -> Patchwork_111334v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111334v1/index.html Participating hosts (36 -> 37) -- Additional (3): fi-bdw-gvtdvm fi-cfl-guc bat-dg1-6 Missing(2): fi-ctg-p8600 bat-rpls-2 Known issues Here are the changes found in Patchwork_111334v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_lmem_swapping@verify-random: - fi-cfl-guc: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#4613]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111334v1/fi-cfl-guc/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-dg1-6: NOTRUN -> [SKIP][2] ([i915#4083]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111334v1/bat-dg1-6/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][3] ([i915#4079]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111334v1/bat-dg1-6/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - fi-pnv-d510:[PASS][4] -> [SKIP][5] ([fdo#109271]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12434/fi-pnv-d510/igt@gem_tiled_bl...@basic.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111334v1/fi-pnv-d510/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][6] ([i915#4077]) +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111334v1/bat-dg1-6/igt@gem_tiled_fence_bl...@basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg1-6: NOTRUN -> [SKIP][7] ([i915#7561]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111334v1/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rps@basic-api: - bat-dg1-6: NOTRUN -> [SKIP][8] ([i915#6621]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111334v1/bat-dg1-6/igt@i915_pm_...@basic-api.html * igt@i915_suspend@basic-s2idle-without-i915: - fi-bdw-gvtdvm: NOTRUN -> [INCOMPLETE][9] ([i915#146]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111334v1/fi-bdw-gvtdvm/igt@i915_susp...@basic-s2idle-without-i915.html * igt@i915_suspend@basic-s3-without-i915: - fi-rkl-11600: [PASS][10] -> [FAIL][11] ([fdo#103375]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12434/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111334v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg1-6: NOTRUN -> [SKIP][12] ([i915#4215]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111334v1/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_addfb_basic@tile-pitch-mismatch: - bat-dg1-6: NOTRUN -> [SKIP][13] ([i915#4212]) +7 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111334v1/bat-dg1-6/igt@kms_addfb_ba...@tile-pitch-mismatch.html * igt@kms_chamelium@dp-crc-fast: - fi-cfl-guc: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111334v1/fi-cfl-guc/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@hdmi-crc-fast: - bat-dg1-6: NOTRUN -> [SKIP][15] ([fdo#111827]) +8 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111334v1/bat-dg1-6/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-bdw-gvtdvm: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +7 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111334v1/fi-bdw-gvtdvm/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor: - bat-dg1-6: NOTRUN -> [SKIP][17] ([i915#4103] / [i915#4213]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111334v1/bat-dg1-6/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html * igt@kms_flip@basic-plain-flip: - fi-bdw-gvtdvm: NOTRUN -> [SKIP][18] ([fdo#109271]) +38 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111334v1/fi-bdw-gvtdvm/igt@kms_f...@basic-plain-flip.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg1-6: NOTRUN -> [SKIP][19] ([fdo#109285]) [19]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: add intel_display_limits.h for key enums
== Series Details == Series: drm/i915/display: add intel_display_limits.h for key enums URL : https://patchwork.freedesktop.org/series/111334/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: add intel_display_limits.h for key enums
== Series Details == Series: drm/i915/display: add intel_display_limits.h for key enums URL : https://patchwork.freedesktop.org/series/111334/ State : warning == Summary == Error: dim checkpatch failed 721cfeb5e38c drm/i915/display: add intel_display_limits.h for key enums Traceback (most recent call last): File "scripts/spdxcheck.py", line 11, in import git ModuleNotFoundError: No module named 'git' -:222: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #222: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 442 lines checked
Re: [Intel-gfx] [PATCH 12/12] drm/i915/fbc: switch to intel_de_* register accessors in display code
On Thu, 24 Nov 2022, Ville Syrjälä wrote:
> On Wed, Nov 23, 2022 at 11:18:25PM +0200, Jani Nikula wrote:
>> Avoid direct uncore use in display code. Use the new
>> intel_de_rewrite_fw().
>>
>> Cc: Maarten Lankhorst
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/display/intel_fbc.c | 10 ++
>> 1 file changed, 2 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
>> b/drivers/gpu/drm/i915/display/intel_fbc.c
>> index b5ee5ea0d010..6066ac412e6f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>> @@ -323,10 +323,7 @@ static void i8xx_fbc_nuke(struct intel_fbc *fbc)
>> enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
>> struct drm_i915_private *dev_priv = fbc->i915;
>>
>> -spin_lock_irq(_priv->uncore.lock);
>> -intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
>> - intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane)));
>> -spin_unlock_irq(_priv->uncore.lock);
>> +intel_de_rewrite_fw(dev_priv, DSPADDR(i9xx_plane));
>
> intel_de_rewrite_fw() seems to imply some kind of atomicicity guarantee
> here. But that entirely depends on whether the other writers of this
> register also protect it with unore.lock. So just a misleading illusion.
>
> That said, this locking stuff shouldn't even be needed since
> commit de5bd083d247 ("drm/i915/fbc: Skip nuke when flip is pending")
> commit 7cfd1a18c5f9 ("drm/i915: Remove remaining locks from i9xx plane
> udpates")
So instead just drop the whole intel_de_rewrite_fw() thing and the
locking around the rewrite here?
BR,
Jani.
>
>> }
>>
>> static void i8xx_fbc_program_cfb(struct intel_fbc *fbc)
>> @@ -359,10 +356,7 @@ static void i965_fbc_nuke(struct intel_fbc *fbc)
>> enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
>> struct drm_i915_private *dev_priv = fbc->i915;
>>
>> -spin_lock_irq(_priv->uncore.lock);
>> -intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
>> - intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane)));
>> -spin_unlock_irq(_priv->uncore.lock);
>> +intel_de_rewrite_fw(dev_priv, DSPSURF(i9xx_plane));
>> }
>>
>> static const struct intel_fbc_funcs i965_fbc_funcs = {
>> --
>> 2.34.1
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH i-g-t] tests/i915/gem_exec_balancer: exercise dmabuf import
Hi Matthew,
one more nit, see below.
On 2022-11-18 at 15:53:35 +, Matthew Auld wrote:
> With parallel submission it should be easy to get a fence array as the
> output fence. Try importing this into dma-buf reservation object, to see
> if anything explodes.
>
> References: https://gitlab.freedesktop.org/drm/intel/-/issues/7532
> Signed-off-by: Matthew Auld
> Cc: Andrzej Hajda
> Cc: Nirmoy Das
> ---
> tests/i915/gem_exec_balancer.c | 39 ++
> 1 file changed, 39 insertions(+)
>
> diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
> index 4300dbd1..fdae8de5 100644
> --- a/tests/i915/gem_exec_balancer.c
> +++ b/tests/i915/gem_exec_balancer.c
> @@ -37,6 +37,7 @@
> #include "igt_sysfs.h"
> #include "igt_types.h"
> #include "sw_sync.h"
> +#include
- ^^
This should be above with other . Also it is linux
specific, so please put it with
#ifdef __linux__
#include
#endif
Regards,
Kamil
>
> IGT_TEST_DESCRIPTION("Exercise in-kernel load-balancing");
>
> @@ -2856,6 +2857,24 @@ static void logical_sort_siblings(int i915,
> #define PARALLEL_SUBMIT_FENCE(0x1 << 3)
> #define PARALLEL_CONTEXTS(0x1 << 4)
> #define PARALLEL_VIRTUAL (0x1 << 5)
> +#define PARALLEL_OUT_FENCE_DMABUF(0x1 << 6)
> +
> +struct igt_dma_buf_sync_file {
> +__u32 flags;
> +__s32 fd;
> +};
> +
> +#define IGT_DMA_BUF_IOCTL_EXPORT_SYNC_FILE _IOWR(DMA_BUF_BASE, 2, struct
> igt_dma_buf_sync_file)
> +#define IGT_DMA_BUF_IOCTL_IMPORT_SYNC_FILE _IOW(DMA_BUF_BASE, 3, struct
> igt_dma_buf_sync_file)
> +
> +static void dmabuf_import_sync_file(int dmabuf, uint32_t flags, int sync_fd)
> +{
> +struct igt_dma_buf_sync_file arg;
> +
> +arg.flags = flags;
> +arg.fd = sync_fd;
> +do_ioctl(dmabuf, IGT_DMA_BUF_IOCTL_IMPORT_SYNC_FILE, );
> +}
>
> static void parallel_thread(int i915, unsigned int flags,
> struct i915_engine_class_instance *siblings,
> @@ -2871,6 +2890,8 @@ static void parallel_thread(int i915, unsigned int
> flags,
> uint32_t target_bo_idx = 0;
> uint32_t first_bb_idx = 1;
> intel_ctx_cfg_t cfg;
> + uint32_t dmabuf_handle;
> + int dmabuf;
>
> igt_assert(bb_per_execbuf < 32);
>
> @@ -2924,11 +2945,20 @@ static void parallel_thread(int i915, unsigned int
> flags,
> execbuf.buffers_ptr = to_user_pointer(obj);
> execbuf.rsvd1 = ctx->id;
>
> + if (flags & PARALLEL_OUT_FENCE_DMABUF) {
> + dmabuf_handle = gem_create(i915, 4096);
> + dmabuf = prime_handle_to_fd(i915, dmabuf_handle);
> + }
> +
> for (n = 0; n < PARALLEL_BB_LOOP_COUNT; ++n) {
> execbuf.flags &= ~0x3full;
> gem_execbuf_wr(i915, );
>
> if (flags & PARALLEL_OUT_FENCE) {
> + if (flags & PARALLEL_OUT_FENCE_DMABUF)
> + dmabuf_import_sync_file(dmabuf,
> DMA_BUF_SYNC_WRITE,
> + execbuf.rsvd2 >> 32);
> +
> igt_assert_eq(sync_fence_wait(execbuf.rsvd2 >> 32,
> 1000), 0);
> igt_assert_eq(sync_fence_status(execbuf.rsvd2 >> 32),
> 1);
> @@ -2959,6 +2989,11 @@ static void parallel_thread(int i915, unsigned int
> flags,
> if (fence)
> close(fence);
>
> + if (flags & PARALLEL_OUT_FENCE_DMABUF) {
> + gem_close(i915, dmabuf_handle);
> + close(dmabuf);
> + }
> +
> check_bo(i915, obj[target_bo_idx].handle,
>bb_per_execbuf * PARALLEL_BB_LOOP_COUNT, true);
>
> @@ -3420,6 +3455,10 @@ igt_main
> igt_subtest("parallel-out-fence")
> parallel(i915, PARALLEL_OUT_FENCE);
>
> + igt_subtest("parallel-out-fence-import-dmabuf")
> + parallel(i915, PARALLEL_OUT_FENCE |
> + PARALLEL_OUT_FENCE_DMABUF);
> +
> igt_subtest("parallel-keep-in-fence")
> parallel(i915, PARALLEL_OUT_FENCE | PARALLEL_IN_FENCE);
>
> --
> 2.38.1
>
[Intel-gfx] [PATCH 4/9] drm/ttm: merge ttm_bo_api.h and ttm_bo_driver.h
Merge and cleanup the two headers into a single description of the
object API. Also move all the documentation to the implementation and
drop unecessary includes from the header.
No functional change.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +-
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c| 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.h| 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.h| 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h| 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 1 +
drivers/gpu/drm/drm_gem_ttm_helper.c | 2 +
drivers/gpu/drm/drm_gem_vram_helper.c | 1 +
.../gpu/drm/i915/gem/i915_gem_object_types.h | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 2 +-
drivers/gpu/drm/i915/i915_deps.c | 2 +-
drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 2 +-
drivers/gpu/drm/i915/intel_region_ttm.c | 1 -
drivers/gpu/drm/nouveau/nouveau_bo.c | 1 +
drivers/gpu/drm/nouveau/nouveau_bo.h | 3 +-
drivers/gpu/drm/nouveau/nouveau_drv.h | 3 +-
drivers/gpu/drm/nouveau/nouveau_mem.c | 3 +-
drivers/gpu/drm/nouveau/nouveau_mem.h | 2 +-
drivers/gpu/drm/nouveau/nouveau_prime.c | 1 +
drivers/gpu/drm/nouveau/nouveau_sgdma.c | 1 +
drivers/gpu/drm/qxl/qxl_drv.h | 3 +-
drivers/gpu/drm/qxl/qxl_ttm.c | 4 +-
drivers/gpu/drm/radeon/radeon.h | 3 +-
drivers/gpu/drm/radeon/radeon_prime.c | 2 +
drivers/gpu/drm/radeon/radeon_ttm.c | 4 +-
drivers/gpu/drm/ttm/ttm_bo.c | 81 +++-
drivers/gpu/drm/ttm/ttm_bo_util.c | 110 +-
drivers/gpu/drm/ttm/ttm_bo_vm.c | 19 +-
drivers/gpu/drm/ttm/ttm_device.c | 2 +-
drivers/gpu/drm/ttm/ttm_execbuf_util.c| 6 +-
drivers/gpu/drm/ttm/ttm_pool.c| 3 +-
drivers/gpu/drm/ttm/ttm_range_manager.c | 2 +-
drivers/gpu/drm/ttm/ttm_resource.c| 3 +-
drivers/gpu/drm/ttm/ttm_tt.c | 3 +-
drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c| 2 +-
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 1 -
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h | 4 +-
drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | 2 +-
drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c | 1 -
drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c | 1 -
.../gpu/drm/vmwgfx/vmwgfx_system_manager.c| 1 -
drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c| 1 -
include/drm/drm_gem_ttm_helper.h | 3 +-
include/drm/drm_gem_vram_helper.h | 4 +-
include/drm/ttm/{ttm_bo_api.h => ttm_bo.h}| 345 +-
include/drm/ttm/ttm_bo_driver.h | 303 ---
include/drm/ttm/ttm_execbuf_util.h| 4 +-
55 files changed, 410 insertions(+), 557 deletions(-)
rename include/drm/ttm/{ttm_bo_api.h => ttm_bo.h} (67%)
delete mode 100644 include/drm/ttm/ttm_bo_driver.h
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 6b74df446694..2644cd991210 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -52,8 +52,7 @@
#include
#include
-#include
-#include
+#include
#include
#include
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 3a763916a5a1..ab450f12c445 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include "amdgpu_object.h"
#include "amdgpu_gem.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
index e4d78491bcc7..ededdc01ca28 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
@@ -28,6 +28,8 @@
struct hmm_range;
+struct drm_file;
+
struct amdgpu_device;
struct amdgpu_bo;
struct amdgpu_bo_va;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 8516c814bc9b..8b7a09b392ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -32,6 +32,8 @@
#include
#include
+#include
+
#include "amdgpu_cs.h"
#include "amdgpu.h"
#include "amdgpu_trace.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.h
[Intel-gfx] [PATCH 9/9] drm/ttm: move ttm_bo_wait into VMWGFX
Not used anymore by other drivers or TTM itself.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c| 44 +++--
drivers/gpu/drm/ttm/ttm_bo_util.c | 19 -
drivers/gpu/drm/vmwgfx/ttm_object.h | 11
include/drm/ttm/ttm_bo.h| 1 -
4 files changed, 39 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index cd266a067773..326a3d13a829 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -1087,47 +1087,35 @@ void ttm_bo_unmap_virtual(struct ttm_buffer_object *bo)
EXPORT_SYMBOL(ttm_bo_unmap_virtual);
/**
- * ttm_bo_wait - wait for buffer idle.
+ * ttm_bo_wait_ctx - wait for buffer idle.
*
* @bo: The buffer object.
- * @interruptible: Use interruptible wait.
- * @no_wait: Return immediately if buffer is busy.
+ * @ctx: defines how to wait
*
- * This function must be called with the bo::mutex held, and makes
- * sure any previous rendering to the buffer is completed.
- * Note: It might be necessary to block validations before the
- * wait by reserving the buffer.
- * Returns -EBUSY if no_wait is true and the buffer is busy.
- * Returns -ERESTARTSYS if interrupted by a signal.
+ * Waits for the buffer to be idle. Used timeout depends on the context.
+ * Returns -EBUSY if wait timed outt, -ERESTARTSYS if interrupted by a signal
or
+ * zero on success.
*/
-int ttm_bo_wait(struct ttm_buffer_object *bo,
- bool interruptible, bool no_wait)
+int ttm_bo_wait_ctx(struct ttm_buffer_object *bo, struct ttm_operation_ctx
*ctx)
{
- long timeout = 15 * HZ;
+ long ret;
- if (no_wait) {
- if (dma_resv_test_signaled(bo->base.resv,
DMA_RESV_USAGE_BOOKKEEP))
+ if (ctx->no_wait_gpu) {
+ if (dma_resv_test_signaled(bo->base.resv,
+ DMA_RESV_USAGE_BOOKKEEP))
return 0;
else
return -EBUSY;
}
- timeout = dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP,
- interruptible, timeout);
- if (timeout < 0)
- return timeout;
-
- if (timeout == 0)
+ ret = dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP,
+ ctx->interruptible, 15 * HZ);
+ if (unlikely(ret < 0))
+ return ret;
+ if (unlikely(ret == 0))
return -EBUSY;
-
return 0;
}
-EXPORT_SYMBOL(ttm_bo_wait);
-
-int ttm_bo_wait_ctx(struct ttm_buffer_object *bo, struct ttm_operation_ctx
*ctx)
-{
- return ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
-}
EXPORT_SYMBOL(ttm_bo_wait_ctx);
int ttm_bo_swapout(struct ttm_buffer_object *bo, struct ttm_operation_ctx *ctx,
@@ -1135,7 +1123,7 @@ int ttm_bo_swapout(struct ttm_buffer_object *bo, struct
ttm_operation_ctx *ctx,
{
struct ttm_place place;
bool locked;
- int ret;
+ long ret;
/*
* While the bo may already reside in SYSTEM placement, set
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index fee7c20775c0..ed2b28734541 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -547,9 +547,13 @@ EXPORT_SYMBOL(ttm_bo_vunmap);
static int ttm_bo_wait_free_node(struct ttm_buffer_object *bo,
bool dst_use_tt)
{
- int ret;
- ret = ttm_bo_wait(bo, false, false);
- if (ret)
+ long ret;
+
+ ret = dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP,
+ false, 15 * HZ);
+ if (ret == 0)
+ return -EBUSY;
+ if (ret < 0)
return ret;
if (!dst_use_tt)
@@ -710,8 +714,7 @@ int ttm_bo_pipeline_gutting(struct ttm_buffer_object *bo)
return ret;
/* If already idle, no need for ghost object dance. */
- ret = ttm_bo_wait(bo, false, true);
- if (ret != -EBUSY) {
+ if (dma_resv_test_signaled(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP)) {
if (!bo->ttm) {
/* See comment below about clearing. */
ret = ttm_tt_create(bo, true);
@@ -748,8 +751,10 @@ int ttm_bo_pipeline_gutting(struct ttm_buffer_object *bo)
ret = dma_resv_copy_fences(>base._resv, bo->base.resv);
/* Last resort, wait for the BO to be idle when we are OOM */
- if (ret)
- ttm_bo_wait(bo, false, false);
+ if (ret) {
+ dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP,
+ false, MAX_SCHEDULE_TIMEOUT);
+ }
dma_resv_unlock(>base._resv);
ttm_bo_put(ghost);
diff --git a/drivers/gpu/drm/vmwgfx/ttm_object.h
b/drivers/gpu/drm/vmwgfx/ttm_object.h
index f0ebbe340ad6..95a9679f9d39
[Intel-gfx] [PATCH 2/9] drm/ttm: remove ttm_bo_(un)lock_delayed_workqueue
Those functions never worked correctly since it is still perfectly
possible that a buffer object is released and the background worker
restarted even after calling them.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +---
drivers/gpu/drm/radeon/radeon_device.c | 5 -
drivers/gpu/drm/radeon/radeon_pm.c | 4 +---
drivers/gpu/drm/ttm/ttm_bo.c| 14 --
include/drm/ttm/ttm_bo_api.h| 16
6 files changed, 3 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 0f16d3c09309..f60753f97ac5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1717,7 +1717,7 @@ static void amdgpu_ib_preempt_mark_partial_job(struct
amdgpu_ring *ring)
static int amdgpu_debugfs_ib_preempt(void *data, u64 val)
{
- int r, resched, length;
+ int r, length;
struct amdgpu_ring *ring;
struct dma_fence **fences = NULL;
struct amdgpu_device *adev = (struct amdgpu_device *)data;
@@ -1747,8 +1747,6 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val)
/* stop the scheduler */
kthread_park(ring->sched.thread);
- resched = ttm_bo_lock_delayed_workqueue(>mman.bdev);
-
/* preempt the IB */
r = amdgpu_ring_preempt_ib(ring);
if (r) {
@@ -1785,8 +1783,6 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val)
up_read(>reset_domain->sem);
- ttm_bo_unlock_delayed_workqueue(>mman.bdev, resched);
-
pro_end:
kfree(fences);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b2b1c66bfe39..2b1db37e25c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3983,10 +3983,8 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)
}
amdgpu_fence_driver_hw_fini(adev);
- if (adev->mman.initialized) {
+ if (adev->mman.initialized)
flush_delayed_work(>mman.bdev.wq);
- ttm_bo_lock_delayed_workqueue(>mman.bdev);
- }
if (adev->pm_sysfs_en)
amdgpu_pm_sysfs_fini(adev);
diff --git a/drivers/gpu/drm/radeon/radeon_device.c
b/drivers/gpu/drm/radeon/radeon_device.c
index 6344454a7721..9a556f505685 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1772,7 +1772,6 @@ int radeon_gpu_reset(struct radeon_device *rdev)
bool saved = false;
int i, r;
- int resched;
down_write(>exclusive_lock);
@@ -1784,8 +1783,6 @@ int radeon_gpu_reset(struct radeon_device *rdev)
atomic_inc(>gpu_reset_counter);
radeon_save_bios_scratch_regs(rdev);
- /* block TTM */
- resched = ttm_bo_lock_delayed_workqueue(>mman.bdev);
radeon_suspend(rdev);
radeon_hpd_fini(rdev);
@@ -1844,8 +1841,6 @@ int radeon_gpu_reset(struct radeon_device *rdev)
/* reset hpd state */
radeon_hpd_init(rdev);
- ttm_bo_unlock_delayed_workqueue(>mman.bdev, resched);
-
rdev->in_reset = true;
rdev->needs_reset = false;
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c
b/drivers/gpu/drm/radeon/radeon_pm.c
index 04c693ca419a..cbc554928bcc 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -1853,11 +1853,10 @@ static bool radeon_pm_debug_check_in_vbl(struct
radeon_device *rdev, bool finish
static void radeon_dynpm_idle_work_handler(struct work_struct *work)
{
struct radeon_device *rdev;
- int resched;
+
rdev = container_of(work, struct radeon_device,
pm.dynpm_idle_work.work);
- resched = ttm_bo_lock_delayed_workqueue(>mman.bdev);
mutex_lock(>pm.mutex);
if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
int not_processed = 0;
@@ -1908,7 +1907,6 @@ static void radeon_dynpm_idle_work_handler(struct
work_struct *work)
msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
}
mutex_unlock(>pm.mutex);
- ttm_bo_unlock_delayed_workqueue(>mman.bdev, resched);
}
/*
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index c3f4b33136e5..b77262a623e0 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -418,20 +418,6 @@ void ttm_bo_put(struct ttm_buffer_object *bo)
}
EXPORT_SYMBOL(ttm_bo_put);
-int ttm_bo_lock_delayed_workqueue(struct ttm_device *bdev)
-{
- return cancel_delayed_work_sync(>wq);
-}
-EXPORT_SYMBOL(ttm_bo_lock_delayed_workqueue);
-
-void ttm_bo_unlock_delayed_workqueue(struct ttm_device *bdev, int resched)
-{
- if (resched)
- schedule_delayed_work(>wq,
-
[Intel-gfx] [PATCH 3/9] drm/ttm: use per BO cleanup workers
Instead of a single worker going over the list of delete BOs in regular
intervals use a per BO worker which blocks for the resv object and
locking of the BO.
This not only simplifies the handling massively, but also results in
much better response time when cleaning up buffers.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c| 2 +-
drivers/gpu/drm/i915/intel_region_ttm.c| 2 +-
drivers/gpu/drm/ttm/ttm_bo.c | 112 -
drivers/gpu/drm/ttm/ttm_bo_util.c | 1 -
drivers/gpu/drm/ttm/ttm_device.c | 24 ++---
include/drm/ttm/ttm_bo_api.h | 18 +---
include/drm/ttm/ttm_device.h | 7 +-
8 files changed, 57 insertions(+), 111 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2b1db37e25c1..74ccbd566777 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3984,7 +3984,7 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)
amdgpu_fence_driver_hw_fini(adev);
if (adev->mman.initialized)
- flush_delayed_work(>mman.bdev.wq);
+ drain_workqueue(adev->mman.bdev.wq);
if (adev->pm_sysfs_en)
amdgpu_pm_sysfs_fini(adev);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8468ca9885fd..c38306f156d6 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1099,7 +1099,7 @@ void i915_gem_drain_freed_objects(struct drm_i915_private
*i915)
{
while (atomic_read(>mm.free_count)) {
flush_work(>mm.free_work);
- flush_delayed_work(>bdev.wq);
+ drain_workqueue(i915->bdev.wq);
rcu_barrier();
}
}
diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c
b/drivers/gpu/drm/i915/intel_region_ttm.c
index cf89d0c2a2d9..657bbc16a48a 100644
--- a/drivers/gpu/drm/i915/intel_region_ttm.c
+++ b/drivers/gpu/drm/i915/intel_region_ttm.c
@@ -132,7 +132,7 @@ int intel_region_ttm_fini(struct intel_memory_region *mem)
break;
msleep(20);
- flush_delayed_work(>i915->bdev.wq);
+ drain_workqueue(mem->i915->bdev.wq);
}
/* If we leaked objects, Don't free the region causing use after free */
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index b77262a623e0..4749b65bedc4 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -280,14 +280,13 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object
*bo,
ret = 0;
}
- if (ret || unlikely(list_empty(>ddestroy))) {
+ if (ret) {
if (unlock_resv)
dma_resv_unlock(bo->base.resv);
spin_unlock(>bdev->lru_lock);
return ret;
}
- list_del_init(>ddestroy);
spin_unlock(>bdev->lru_lock);
ttm_bo_cleanup_memtype_use(bo);
@@ -300,47 +299,21 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object
*bo,
}
/*
- * Traverse the delayed list, and call ttm_bo_cleanup_refs on all
- * encountered buffers.
+ * Block for the dma_resv object to become idle, lock the buffer and clean up
+ * the resource and tt object.
*/
-bool ttm_bo_delayed_delete(struct ttm_device *bdev, bool remove_all)
+static void ttm_bo_delayed_delete(struct work_struct *work)
{
- struct list_head removed;
- bool empty;
-
- INIT_LIST_HEAD();
-
- spin_lock(>lru_lock);
- while (!list_empty(>ddestroy)) {
- struct ttm_buffer_object *bo;
-
- bo = list_first_entry(>ddestroy, struct ttm_buffer_object,
- ddestroy);
- list_move_tail(>ddestroy, );
- if (!ttm_bo_get_unless_zero(bo))
- continue;
-
- if (remove_all || bo->base.resv != >base._resv) {
- spin_unlock(>lru_lock);
- dma_resv_lock(bo->base.resv, NULL);
-
- spin_lock(>lru_lock);
- ttm_bo_cleanup_refs(bo, false, !remove_all, true);
-
- } else if (dma_resv_trylock(bo->base.resv)) {
- ttm_bo_cleanup_refs(bo, false, !remove_all, true);
- } else {
- spin_unlock(>lru_lock);
- }
+ struct ttm_buffer_object *bo;
- ttm_bo_put(bo);
- spin_lock(>lru_lock);
- }
- list_splice_tail(, >ddestroy);
- empty = list_empty(>ddestroy);
- spin_unlock(>lru_lock);
+ bo = container_of(work, typeof(*bo), delayed_delete);
- return empty;
+ dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP, false,
+
[Intel-gfx] [PATCH 7/9] drm/i915: stop using ttm_bo_wait
TTM is just wrapping core DMA functionality here, remove the mid-layer.
No functional change.
Signed-off-by: Christian König
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 5247d88b3c13..d409a77449a3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -599,13 +599,16 @@ i915_ttm_resource_get_st(struct drm_i915_gem_object *obj,
static int i915_ttm_truncate(struct drm_i915_gem_object *obj)
{
struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
- int err;
+ long err;
WARN_ON_ONCE(obj->mm.madv == I915_MADV_WILLNEED);
- err = ttm_bo_wait(bo, true, false);
- if (err)
+ err = dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP,
+ true, 15 * HZ);
+ if (err < 0)
return err;
+ if (err == 0)
+ return -EBUSY;
err = i915_ttm_move_notify(bo);
if (err)
--
2.34.1
[Intel-gfx] [PATCH 8/9] drm/ttm: use ttm_bo_wait_ctx instead of ttm_bo_wait
Make sure that we use the correct settings from the context.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index f9d9fd2d865d..cd266a067773 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -439,7 +439,7 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo,
bdev->funcs->evict_flags(bo, );
if (!placement.num_placement && !placement.num_busy_placement) {
- ret = ttm_bo_wait(bo, true, false);
+ ret = ttm_bo_wait_ctx(bo, ctx);
if (ret)
return ret;
@@ -1190,7 +1190,7 @@ int ttm_bo_swapout(struct ttm_buffer_object *bo, struct
ttm_operation_ctx *ctx,
/*
* Make sure BO is idle.
*/
- ret = ttm_bo_wait(bo, false, false);
+ ret = ttm_bo_wait_ctx(bo, ctx);
if (unlikely(ret != 0))
goto out;
--
2.34.1
[Intel-gfx] [PATCH 5/9] drm/nouveau: stop using ttm_bo_wait
TTM is just wrapping core DMA functionality here, remove the mid-layer.
No functional change.
Signed-off-by: Christian König
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 6 +-
drivers/gpu/drm/nouveau/nouveau_gem.c | 11 ---
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c
b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 335fa91ca4ad..288eebc70a67 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -922,6 +922,7 @@ static void nouveau_bo_move_ntfy(struct ttm_buffer_object
*bo,
struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
struct nouveau_bo *nvbo = nouveau_bo(bo);
struct nouveau_vma *vma;
+ long ret;
/* ttm can now (stupidly) pass the driver bos it didn't create... */
if (bo->destroy != nouveau_bo_del_ttm)
@@ -936,7 +937,10 @@ static void nouveau_bo_move_ntfy(struct ttm_buffer_object
*bo,
}
} else {
list_for_each_entry(vma, >vma_list, head) {
- WARN_ON(ttm_bo_wait(bo, false, false));
+ ret = dma_resv_wait_timeout(bo->base.resv,
+ DMA_RESV_USAGE_BOOKKEEP,
+ false, 15 * HZ);
+ WARN_ON(ret <= 0);
nouveau_vma_unmap(vma);
}
}
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c
b/drivers/gpu/drm/nouveau/nouveau_gem.c
index ac5793c96957..f77e44958037 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -645,7 +645,7 @@ nouveau_gem_pushbuf_reloc_apply(struct nouveau_cli *cli,
struct drm_nouveau_gem_pushbuf_reloc *reloc,
struct drm_nouveau_gem_pushbuf_bo *bo)
{
- int ret = 0;
+ long ret = 0;
unsigned i;
for (i = 0; i < req->nr_relocs; i++) {
@@ -703,9 +703,14 @@ nouveau_gem_pushbuf_reloc_apply(struct nouveau_cli *cli,
data |= r->vor;
}
- ret = ttm_bo_wait(>bo, false, false);
+ ret = dma_resv_wait_timeout(nvbo->bo.base.resv,
+ DMA_RESV_USAGE_BOOKKEEP,
+ false, 15 * HZ);
+ if (ret == 0)
+ ret = -EBUSY;
if (ret) {
- NV_PRINTK(err, cli, "reloc wait_idle failed: %d\n",
ret);
+ NV_PRINTK(err, cli, "reloc wait_idle failed: %ld\n",
+ ret);
break;
}
--
2.34.1
[Intel-gfx] [PATCH 6/9] drm/qxl: stop using ttm_bo_wait
TTM is just wrapping core DMA functionality here, remove the mid-layer.
No functional change.
Signed-off-by: Christian König
---
drivers/gpu/drm/qxl/qxl_cmd.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/qxl/qxl_cmd.c b/drivers/gpu/drm/qxl/qxl_cmd.c
index 63aa96a69752..281edab518cd 100644
--- a/drivers/gpu/drm/qxl/qxl_cmd.c
+++ b/drivers/gpu/drm/qxl/qxl_cmd.c
@@ -579,7 +579,7 @@ void qxl_surface_evict(struct qxl_device *qdev, struct
qxl_bo *surf, bool do_upd
static int qxl_reap_surf(struct qxl_device *qdev, struct qxl_bo *surf, bool
stall)
{
- int ret;
+ long ret;
ret = qxl_bo_reserve(surf);
if (ret)
@@ -588,7 +588,19 @@ static int qxl_reap_surf(struct qxl_device *qdev, struct
qxl_bo *surf, bool stal
if (stall)
mutex_unlock(>surf_evict_mutex);
- ret = ttm_bo_wait(>tbo, true, !stall);
+ if (stall) {
+ ret = dma_resv_wait_timeout(surf->tbo.base.resv,
+ DMA_RESV_USAGE_BOOKKEEP, true,
+ 15 * HZ);
+ if (ret > 0)
+ ret = 0;
+ else if (ret == 0)
+ ret = -EBUSY;
+ } else {
+ ret = dma_resv_test_signaled(surf->tbo.base.resv,
+DMA_RESV_USAGE_BOOKKEEP);
+ ret = ret ? -EBUSY : 0;
+ }
if (stall)
mutex_lock(>surf_evict_mutex);
--
2.34.1
[Intel-gfx] [PATCH 1/9] drm/amdgpu: generally allow over-commit during BO allocation
We already fallback to a dummy BO with no backing store when we
allocate GDS,GWS and OA resources and to GTT when we allocate VRAM.
Drop all those workarounds and generalize this for GTT as well. This
fixes ENOMEM issues with runaway applications which try to allocate/free
GTT in a loop and are otherwise only limited by the CPU speed.
The CS will wait for the cleanup of freed up BOs to satisfy the
various domain specific limits and so effectively throttle those
buggy applications down to a sane allocation behavior again.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 16 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 6 +-
2 files changed, 4 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index a0780a4e3e61..62e98f1ad770 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -113,7 +113,7 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev,
unsigned long size,
bp.resv = resv;
bp.preferred_domain = initial_domain;
bp.flags = flags;
- bp.domain = initial_domain;
+ bp.domain = initial_domain | AMDGPU_GEM_DOMAIN_CPU;
bp.bo_ptr_size = sizeof(struct amdgpu_bo);
r = amdgpu_bo_create_user(adev, , );
@@ -332,20 +332,10 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void
*data,
}
initial_domain = (u32)(0x & args->in.domains);
-retry:
r = amdgpu_gem_object_create(adev, size, args->in.alignment,
-initial_domain,
-flags, ttm_bo_type_device, resv, );
+initial_domain, flags, ttm_bo_type_device,
+resv, );
if (r && r != -ERESTARTSYS) {
- if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
- flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
- goto retry;
- }
-
- if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
- initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
- goto retry;
- }
DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu,
%d)\n",
size, initial_domain, args->in.alignment, r);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 974e85d8b6cc..919bbea2e3ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -581,11 +581,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
bo->flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
bo->tbo.bdev = >mman.bdev;
- if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA |
- AMDGPU_GEM_DOMAIN_GDS))
- amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
- else
- amdgpu_bo_placement_from_domain(bo, bp->domain);
+ amdgpu_bo_placement_from_domain(bo, bp->domain);
if (bp->type == ttm_bo_type_kernel)
bo->tbo.priority = 1;
--
2.34.1
[Intel-gfx] [RFC] drm/i915/display: add intel_display_limits.h for key enums
Move a handful of key enums to a new file intel_display_limits.h. These
are the enum types, and the MAX/NUM enumerations within them, that are
used in other headers. Otherwise, there's no common theme between them.
Replace intel_display.h include with intel_display_limit.h where
relevant, and add the intel_display.h include directly in the .c files
where needed.
Since intel_display.h is used almost everywhere in display/, include it
from intel_display_types.h to avoid massive changes across the
board. There are very few files that would need intel_display_types.h
but not intel_display.h so this is neglible, and further cleanup between
these headers can be left for the future.
Overall this change drops the direct and indirect dependencies on
intel_display.h from about 300 to about 100 compilation units.
Signed-off-by: Jani Nikula
---
N.b. intel_display_limits.h is not a great name. I was hoping it was
only needed for the MAX/NUM enumerations such as I915_MAX_PIPES but
there are a number of headers that use the types for struct members as
well. intel_display_enums.h sounds too generic too. Suggestions?
---
drivers/gpu/drm/i915/display/intel_bw.h | 2 +-
drivers/gpu/drm/i915/display/intel_cdclk.h| 2 +-
drivers/gpu/drm/i915/display/intel_display.h | 115 +---
.../gpu/drm/i915/display/intel_display_core.h | 2 +-
.../drm/i915/display/intel_display_limits.h | 124 ++
.../i915/display/intel_display_power_map.c| 1 +
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_dvo_dev.h | 2 +-
drivers/gpu/drm/i915/display/skl_watermark.h | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_create.c| 1 +
drivers/gpu/drm/i915/gt/intel_ggtt.c | 1 +
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 1 +
drivers/gpu/drm/i915/gt/intel_rps.c | 1 +
drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 +
drivers/gpu/drm/i915/gvt/display.c| 1 +
drivers/gpu/drm/i915/gvt/fb_decoder.h | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_vma.c | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 2 +-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
drivers/gpu/drm/i915/intel_pm.c | 1 +
drivers/gpu/drm/i915/intel_pm_types.h | 2 +-
drivers/gpu/drm/i915/vlv_sideband.c | 1 +
25 files changed, 148 insertions(+), 123 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_display_limits.h
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
b/drivers/gpu/drm/i915/display/intel_bw.h
index cb7ee3a24a58..f20292143745 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -8,7 +8,7 @@
#include
-#include "intel_display.h"
+#include "intel_display_limits.h"
#include "intel_display_power.h"
#include "intel_global_state.h"
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
b/drivers/gpu/drm/i915/display/intel_cdclk.h
index c674879a84a5..51e2f6a11ce4 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -8,7 +8,7 @@
#include
-#include "intel_display.h"
+#include "intel_display_limits.h"
#include "intel_global_state.h"
struct drm_i915_private;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 714030136b7f..057445da54e2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -28,6 +28,7 @@
#include
#include "i915_reg_defs.h"
+#include "intel_display_limits.h"
enum drm_scaling_filter;
struct dpll;
@@ -62,51 +63,9 @@ struct intel_remapped_info;
struct intel_rotation_info;
struct pci_dev;
-/*
- * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
- * rest have consecutive values and match the enum values of transcoders
- * with a 1:1 transcoder -> pipe mapping.
- */
-enum pipe {
- INVALID_PIPE = -1,
-
- PIPE_A = 0,
- PIPE_B,
- PIPE_C,
- PIPE_D,
- _PIPE_EDP,
-
- I915_MAX_PIPES = _PIPE_EDP
-};
#define pipe_name(p) ((p) + 'A')
-enum transcoder {
- INVALID_TRANSCODER = -1,
- /*
-* The following transcoders have a 1:1 transcoder -> pipe mapping,
-* keep their values fixed: the code assumes that TRANSCODER_A=0, the
-* rest have consecutive values and match the enum values of the pipes
-* they map to.
-*/
- TRANSCODER_A = PIPE_A,
- TRANSCODER_B = PIPE_B,
- TRANSCODER_C = PIPE_C,
- TRANSCODER_D = PIPE_D,
-
- /*
-* The following transcoders can map to any pipe, their enum value
-* doesn't need to stay fixed.
-*/
- TRANSCODER_EDP,
- TRANSCODER_DSI_0,
-
Re: [Intel-gfx] [PATCH i-g-t] tests/i915/gem_exec_balancer: exercise dmabuf import
Hi Matthew,
few nits, see below.
On 2022-11-18 at 15:53:35 +, Matthew Auld wrote:
> With parallel submission it should be easy to get a fence array as the
> output fence. Try importing this into dma-buf reservation object, to see
> if anything explodes.
>
> References: https://gitlab.freedesktop.org/drm/intel/-/issues/7532
> Signed-off-by: Matthew Auld
> Cc: Andrzej Hajda
> Cc: Nirmoy Das
> ---
> tests/i915/gem_exec_balancer.c | 39 ++
> 1 file changed, 39 insertions(+)
>
> diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
> index 4300dbd1..fdae8de5 100644
> --- a/tests/i915/gem_exec_balancer.c
> +++ b/tests/i915/gem_exec_balancer.c
> @@ -37,6 +37,7 @@
> #include "igt_sysfs.h"
> #include "igt_types.h"
> #include "sw_sync.h"
> +#include
>
> IGT_TEST_DESCRIPTION("Exercise in-kernel load-balancing");
>
> @@ -2856,6 +2857,24 @@ static void logical_sort_siblings(int i915,
> #define PARALLEL_SUBMIT_FENCE(0x1 << 3)
> #define PARALLEL_CONTEXTS(0x1 << 4)
> #define PARALLEL_VIRTUAL (0x1 << 5)
> +#define PARALLEL_OUT_FENCE_DMABUF(0x1 << 6)
> +
> +struct igt_dma_buf_sync_file {
> +__u32 flags;
> +__s32 fd;
> +};
> +
> +#define IGT_DMA_BUF_IOCTL_EXPORT_SYNC_FILE _IOWR(DMA_BUF_BASE, 2, struct
> igt_dma_buf_sync_file)
> +#define IGT_DMA_BUF_IOCTL_IMPORT_SYNC_FILE _IOW(DMA_BUF_BASE, 3, struct
> igt_dma_buf_sync_file)
> +
> +static void dmabuf_import_sync_file(int dmabuf, uint32_t flags, int sync_fd)
> +{
> +struct igt_dma_buf_sync_file arg;
> +
> +arg.flags = flags;
> +arg.fd = sync_fd;
> +do_ioctl(dmabuf, IGT_DMA_BUF_IOCTL_IMPORT_SYNC_FILE, );
> +}
You did not check for error here, so either add assert
do_ioctl ... == 0 or change function name, add __ before like:
static int __dmabuf_import_sync_file(int dmabuf, uint32_t flags, int sync_fd)
>
> static void parallel_thread(int i915, unsigned int flags,
> struct i915_engine_class_instance *siblings,
> @@ -2871,6 +2890,8 @@ static void parallel_thread(int i915, unsigned int
> flags,
> uint32_t target_bo_idx = 0;
> uint32_t first_bb_idx = 1;
> intel_ctx_cfg_t cfg;
> + uint32_t dmabuf_handle;
> + int dmabuf;
>
> igt_assert(bb_per_execbuf < 32);
>
> @@ -2924,11 +2945,20 @@ static void parallel_thread(int i915, unsigned int
> flags,
> execbuf.buffers_ptr = to_user_pointer(obj);
> execbuf.rsvd1 = ctx->id;
>
> + if (flags & PARALLEL_OUT_FENCE_DMABUF) {
> + dmabuf_handle = gem_create(i915, 4096);
> + dmabuf = prime_handle_to_fd(i915, dmabuf_handle);
> + }
> +
> for (n = 0; n < PARALLEL_BB_LOOP_COUNT; ++n) {
> execbuf.flags &= ~0x3full;
> gem_execbuf_wr(i915, );
>
> if (flags & PARALLEL_OUT_FENCE) {
> + if (flags & PARALLEL_OUT_FENCE_DMABUF)
> + dmabuf_import_sync_file(dmabuf,
> DMA_BUF_SYNC_WRITE,
> + execbuf.rsvd2 >> 32);
> +
> igt_assert_eq(sync_fence_wait(execbuf.rsvd2 >> 32,
> 1000), 0);
> igt_assert_eq(sync_fence_status(execbuf.rsvd2 >> 32),
> 1);
> @@ -2959,6 +2989,11 @@ static void parallel_thread(int i915, unsigned int
> flags,
> if (fence)
> close(fence);
>
> + if (flags & PARALLEL_OUT_FENCE_DMABUF) {
> + gem_close(i915, dmabuf_handle);
> + close(dmabuf);
> + }
> +
> check_bo(i915, obj[target_bo_idx].handle,
>bb_per_execbuf * PARALLEL_BB_LOOP_COUNT, true);
>
> @@ -3420,6 +3455,10 @@ igt_main
> igt_subtest("parallel-out-fence")
> parallel(i915, PARALLEL_OUT_FENCE);
>
Please put description here.
Regards,
Kamil
> + igt_subtest("parallel-out-fence-import-dmabuf")
> + parallel(i915, PARALLEL_OUT_FENCE |
> + PARALLEL_OUT_FENCE_DMABUF);
> +
> igt_subtest("parallel-keep-in-fence")
> parallel(i915, PARALLEL_OUT_FENCE | PARALLEL_IN_FENCE);
>
> --
> 2.38.1
>
Re: [Intel-gfx] [PATCH] drm/i915/bios: fix a memory leak in generate_lfp_data_ptrs
On Fri, 25 Nov 2022, Xia Fukun wrote:
> When (size != 0 || ptrs->lvds_ entries != 3), the program tries to
> free() the ptrs. However, the ptrs is not created by calling kzmalloc(),
> but is obtained by pointer offset operation.
> This may lead to memory leaks or undefined behavior.
Yeah probably worse things will happen than just leak.
>
> Fix this by replacing the arguments of kfree() with ptrs_block.
>
> Fixes: a87d0a847607 ("drm/i915/bios: Generate LFP data table pointers if the
> VBT lacks them")
> Signed-off-by: Xia Fukun
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 28bdb936cd1f..edbdb949b6ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -414,7 +414,7 @@ static void *generate_lfp_data_ptrs(struct
> drm_i915_private *i915,
> ptrs->lvds_entries++;
>
> if (size != 0 || ptrs->lvds_entries != 3) {
> - kfree(ptrs);
> + kfree(ptrs_block);
> return NULL;
> }
--
Jani Nikula, Intel Open Source Graphics Center
