[Intel-gfx] [PATCH] drm/i915/psr: Add continuous full frame bit together with single
Currently we are observing occasionally display flickering or complete
freeze. This is narrowed down to be caused by single full frame update
(SFF).
SFF bit after it's written gets cleared by HW in subsequent vblank
i.e. when the update is sent to the panel. SFF bit is required to be
written together with partial frame update (PFU) bit. After the SFF
bit gets cleared by the HW psr2 man trk ctl register still contains
PFU bit. If there is subsequent update for any reason we will end up
having selective update/fetch configuration where start line is 0 and
end line is 0. Also selective fetch configuration for the planes is
not properly performed. This seems to be causing problems with some
panels.
Using CFF without SFF doesn't work either because it may happen that
psr2 man track ctl register is overwritten by next update before
vblank triggers sending the update. This is causing problems to
psr_invalidate/flush. Using CFF and SFF together solves the problems
as SFF is cleared only by HW in subsequent vblank.
Fix the flickering/freeze issue by adding continuous full frame with
single full frame update and switch to partial frame update only when
selective update area is properly calculated and configured.
This is also workaround for HSD 14014971508
Cc: Ville Syrjälä
Cc: José Roberto de Souza
Cc: Mika Kahola
Reported-by: Lee Shawn C
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 5b678916e6db..88388201684e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1510,7 +1510,8 @@ static void psr_force_hw_tracking_exit(struct intel_dp
*intel_dp)
PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
man_trk_ctl_enable_bit_get(dev_priv) |
man_trk_ctl_partial_frame_bit_get(dev_priv) |
- man_trk_ctl_single_full_frame_bit_get(dev_priv));
+ man_trk_ctl_single_full_frame_bit_get(dev_priv) |
+ man_trk_ctl_continuos_full_frame(dev_priv));
/*
* Display WA #0884: skl+
@@ -1624,11 +1625,8 @@ static void psr2_man_trk_ctl_calc(struct
intel_crtc_state *crtc_state,
val |= man_trk_ctl_partial_frame_bit_get(dev_priv);
if (full_update) {
- /*
-* Not applying Wa_14014971508:adlp as we do not support the
-* feature that requires this workaround.
-*/
val |= man_trk_ctl_single_full_frame_bit_get(dev_priv);
+ val |= man_trk_ctl_continuos_full_frame(dev_priv);
goto exit;
}
@@ -2307,12 +2305,15 @@ static void _psr_flush_handle(struct intel_dp *intel_dp)
/* can we turn CFF off? */
if (intel_dp->psr.busy_frontbuffer_bits == 0) {
u32 val = man_trk_ctl_enable_bit_get(dev_priv) |
-
man_trk_ctl_partial_frame_bit_get(dev_priv) |
-
man_trk_ctl_single_full_frame_bit_get(dev_priv);
+
man_trk_ctl_partial_frame_bit_get(dev_priv) |
+
man_trk_ctl_single_full_frame_bit_get(dev_priv) |
+
man_trk_ctl_continuos_full_frame(dev_priv);
/*
-* turn continuous full frame off and do a
single
-* full frame
+* turn continuous full frame off and do a
single full frame. Still
+* keep cff bit enabled as we don't have proper
SU configuration in
+* case update is sent for any reason after sff
bit gets cleared by
+* the HW on next vblank.
*/
intel_de_write(dev_priv,
PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
val);
--
2.34.1
[Intel-gfx] [PATCH v8 13/22] drm/i915/vm_bind: Update i915_vma_verify_bind_complete()
Ensure i915_vma_verify_bind_complete() handles case where bind
is not initiated. Also make it non static, add documentation
and move it out of CONFIG_DRM_I915_DEBUG_GEM.
v2: Fix fence leak
Reviewed-by: Matthew Auld
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/i915_vma.c | 22 --
drivers/gpu/drm/i915/i915_vma.h | 1 +
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index c29e22b1cfea..e382c8a6cac4 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -441,12 +441,25 @@ int i915_vma_sync(struct i915_vma *vma)
return i915_vm_sync(vma->vm);
}
-#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
-static int i915_vma_verify_bind_complete(struct i915_vma *vma)
+/**
+ * i915_vma_verify_bind_complete() - Check for the bind completion of the vma
+ * @vma: vma to check for bind completion
+ *
+ * As the fence reference is obtained under RCU, no locking is required by
+ * the caller.
+ *
+ * Returns: 0 if the vma bind is completed. Error code otherwise.
+ */
+int i915_vma_verify_bind_complete(struct i915_vma *vma)
{
- struct dma_fence *fence = i915_active_fence_get(>active.excl);
+ struct dma_fence *fence;
int err;
+ /* Ensure vma bind is initiated */
+ if (!i915_vma_is_bound(vma, I915_VMA_BIND_MASK))
+ return -EINVAL;
+
+ fence = i915_active_fence_get(>active.excl);
if (!fence)
return 0;
@@ -459,9 +472,6 @@ static int i915_vma_verify_bind_complete(struct i915_vma
*vma)
return err;
}
-#else
-#define i915_vma_verify_bind_complete(_vma) 0
-#endif
I915_SELFTEST_EXPORT void
i915_vma_resource_init_from_vma(struct i915_vma_resource *vma_res,
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 25e4aa69cd89..9a411a79badd 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -441,6 +441,7 @@ void i915_vma_make_purgeable(struct i915_vma *vma);
int i915_vma_wait_for_bind(struct i915_vma *vma);
int i915_vma_sync(struct i915_vma *vma);
+int i915_vma_verify_bind_complete(struct i915_vma *vma);
/**
* i915_vma_get_current_resource - Get the current resource of the vma
--
2.21.0.rc0.32.g243a4c7e27
[Intel-gfx] [PATCH v8 16/22] drm/i915/vm_bind: userptr dma-resv changes
For persistent (vm_bind) vmas of userptr BOs, handle the user
page pinning by using the i915_gem_object_userptr_submit_init()
/done() functions
v2: Do not double add vma to vm->userptr_invalidated_list
v3: Initialize vma->userptr_invalidated_link
Reviewed-by: Matthew Auld
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Andi Shyti
---
.../gpu/drm/i915/gem/i915_gem_execbuffer3.c | 84 ++-
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 19 +
.../drm/i915/gem/i915_gem_vm_bind_object.c| 15
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +
drivers/gpu/drm/i915/gt/intel_gtt.h | 4 +
drivers/gpu/drm/i915/i915_vma.c | 1 +
drivers/gpu/drm/i915/i915_vma_types.h | 2 +
7 files changed, 125 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
index 913b1f8bda9f..a1aee477e2df 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
@@ -20,6 +20,7 @@
#include "i915_gem_vm_bind.h"
#include "i915_trace.h"
+#define __EXEC3_USERPTR_USED BIT_ULL(34)
#define __EXEC3_HAS_PINBIT_ULL(33)
#define __EXEC3_ENGINE_PINNED BIT_ULL(32)
#define __EXEC3_INTERNAL_FLAGS (~0ull << 32)
@@ -144,7 +145,22 @@ static void eb_scoop_unbound_vma_all(struct
i915_address_space *vm)
{
struct i915_vma *vma, *vn;
- /**
+#ifdef CONFIG_MMU_NOTIFIER
+ /*
+* Move all invalidated userptr vmas back into vm_bind_list so that
+* they are looked up and revalidated.
+*/
+ spin_lock(>userptr_invalidated_lock);
+ list_for_each_entry_safe(vma, vn, >userptr_invalidated_list,
+userptr_invalidated_link) {
+ list_del_init(>userptr_invalidated_link);
+ if (!list_empty(>vm_bind_link))
+ list_move_tail(>vm_bind_link, >vm_bind_list);
+ }
+ spin_unlock(>userptr_invalidated_lock);
+#endif
+
+ /*
* Move all unbound vmas back into vm_bind_list so that they are
* revalidated.
*/
@@ -157,10 +173,47 @@ static void eb_scoop_unbound_vma_all(struct
i915_address_space *vm)
spin_unlock(>vm_rebind_lock);
}
+static int eb_lookup_persistent_userptr_vmas(struct i915_execbuffer *eb)
+{
+ struct i915_address_space *vm = eb->context->vm;
+ struct i915_vma *last_vma = NULL;
+ struct i915_vma *vma;
+ int err;
+
+ lockdep_assert_held(>vm_bind_lock);
+
+ list_for_each_entry(vma, >vm_bind_list, vm_bind_link) {
+ if (!i915_gem_object_is_userptr(vma->obj))
+ continue;
+
+ err = i915_gem_object_userptr_submit_init(vma->obj);
+ if (err)
+ return err;
+
+ /*
+* The above submit_init() call does the object unbind and
+* hence adds vma into vm_rebind_list. Remove it from that
+* list as it is already scooped for revalidation.
+*/
+ spin_lock(>vm_rebind_lock);
+ if (!list_empty(>vm_rebind_link))
+ list_del_init(>vm_rebind_link);
+ spin_unlock(>vm_rebind_lock);
+
+ last_vma = vma;
+ }
+
+ if (last_vma)
+ eb->args->flags |= __EXEC3_USERPTR_USED;
+
+ return 0;
+}
+
static int eb_lookup_vma_all(struct i915_execbuffer *eb)
{
struct i915_vma *vma;
unsigned int i;
+ int err = 0;
for (i = 0; i < eb->num_batches; i++) {
vma = eb_find_vma(eb->context->vm, eb->batch_addresses[i]);
@@ -172,6 +225,10 @@ static int eb_lookup_vma_all(struct i915_execbuffer *eb)
eb_scoop_unbound_vma_all(eb->context->vm);
+ err = eb_lookup_persistent_userptr_vmas(eb);
+ if (err)
+ return err;
+
return 0;
}
@@ -344,6 +401,29 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
}
}
+#ifdef CONFIG_MMU_NOTIFIER
+ /* Check for further userptr invalidations */
+ spin_lock(>userptr_invalidated_lock);
+ if (!list_empty(>userptr_invalidated_list))
+ err = -EAGAIN;
+ spin_unlock(>userptr_invalidated_lock);
+
+ if (!err && (eb->args->flags & __EXEC3_USERPTR_USED)) {
+ read_lock(>i915->mm.notifier_lock);
+ list_for_each_entry(vma, >vm_bind_list, vm_bind_link) {
+ if (!i915_gem_object_is_userptr(vma->obj))
+ continue;
+
+ err = i915_gem_object_userptr_submit_done(vma->obj);
+ if (err)
+ break;
+ }
+ read_unlock(>i915->mm.notifier_lock);
+ }
+#endif
+ if (unlikely(err))
+ goto err_skip;
+
[Intel-gfx] [PATCH v8 17/22] drm/i915/vm_bind: Limit vm_bind mode to non-recoverable contexts
Only support vm_bind mode with non-recoverable contexts.
With new vm_bind mode with eb3 submission path, we need not
support older recoverable contexts.
Reviewed-by: Matthew Auld
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 7d3366975e6d..a048bf463916 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1617,6 +1617,12 @@ i915_gem_create_context(struct drm_i915_private *i915,
INIT_LIST_HEAD(>stale.engines);
if (pc->vm) {
+ /* Only non-recoverable contexts are allowed in vm_bind mode */
+ if (i915_gem_vm_is_vm_bind_mode(pc->vm) &&
+ (pc->user_flags & BIT(UCONTEXT_RECOVERABLE))) {
+ err = -EINVAL;
+ goto err_ctx;
+ }
vm = i915_vm_get(pc->vm);
} else if (HAS_FULL_PPGTT(i915)) {
struct i915_ppgtt *ppgtt;
--
2.21.0.rc0.32.g243a4c7e27
[Intel-gfx] [PATCH v8 07/22] drm/i915/vm_bind: Add support to handle object evictions
Support eviction by maintaining a list of evicted persistent vmas
for rebinding during next submission. Ensure the list do not
include persistent vmas that are being purged.
v2: Remove unused I915_VMA_PURGED definition.
v3: Properly handle __i915_vma_unbind_async() case.
Reviewed-by: Matthew Auld
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Andi Shyti
---
.../drm/i915/gem/i915_gem_vm_bind_object.c| 6
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 ++
drivers/gpu/drm/i915/gt/intel_gtt.h | 4 +++
drivers/gpu/drm/i915/i915_vma.c | 31 +--
drivers/gpu/drm/i915/i915_vma.h | 10 ++
drivers/gpu/drm/i915/i915_vma_types.h | 8 +
6 files changed, 59 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
index 4f9df4b756d2..dc738677466b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
@@ -86,6 +86,12 @@ static void i915_gem_vm_bind_remove(struct i915_vma *vma,
bool release_obj)
{
lockdep_assert_held(>vm->vm_bind_lock);
+ spin_lock(>vm->vm_rebind_lock);
+ if (!list_empty(>vm_rebind_link))
+ list_del_init(>vm_rebind_link);
+ i915_vma_set_purged(vma);
+ spin_unlock(>vm->vm_rebind_lock);
+
list_del_init(>vm_bind_link);
list_del_init(>non_priv_vm_bind_link);
i915_vm_bind_it_remove(vma, >vm->va);
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 542c0f85bf6f..401075776a83 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -291,6 +291,8 @@ void i915_address_space_init(struct i915_address_space *vm,
int subclass)
INIT_LIST_HEAD(>vm_bound_list);
mutex_init(>vm_bind_lock);
INIT_LIST_HEAD(>non_priv_vm_bind_list);
+ INIT_LIST_HEAD(>vm_rebind_list);
+ spin_lock_init(>vm_rebind_lock);
}
void *__px_vaddr(struct drm_i915_gem_object *p)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 8c1b81d2a56c..fc1b2622c66f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -266,6 +266,10 @@ struct i915_address_space {
struct list_head vm_bind_list;
/** @vm_bound_list: List of vm_binding completed */
struct list_head vm_bound_list;
+ /** @vm_rebind_list: list of vmas to be rebinded */
+ struct list_head vm_rebind_list;
+ /** @vm_rebind_lock: protects vm_rebound_list */
+ spinlock_t vm_rebind_lock;
/** @va: tree of persistent vmas */
struct rb_root_cached va;
/** @non_priv_vm_bind_list: list of non-private object mappings */
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 92dea99cc735..8de9f7a5b306 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -243,6 +243,7 @@ vma_create(struct drm_i915_gem_object *obj,
INIT_LIST_HEAD(>vm_bind_link);
INIT_LIST_HEAD(>non_priv_vm_bind_link);
+ INIT_LIST_HEAD(>vm_rebind_link);
return vma;
err_unlock:
@@ -1686,6 +1687,14 @@ static void force_unbind(struct i915_vma *vma)
if (!drm_mm_node_allocated(>node))
return;
+ /*
+* Persistent vma should have been purged by now.
+* If not, issue a warning and purge it.
+*/
+ if (GEM_WARN_ON(i915_vma_is_persistent(vma) &&
+ !i915_vma_is_purged(vma)))
+ i915_vma_set_purged(vma);
+
atomic_and(~I915_VMA_PIN_MASK, >flags);
WARN_ON(__i915_vma_unbind(vma));
GEM_BUG_ON(drm_mm_node_allocated(>node));
@@ -2052,6 +2061,16 @@ int __i915_vma_unbind(struct i915_vma *vma)
__i915_vma_evict(vma, false);
drm_mm_remove_node(>node); /* pairs with i915_vma_release() */
+
+ if (i915_vma_is_persistent(vma)) {
+ spin_lock(>vm->vm_rebind_lock);
+ if (list_empty(>vm_rebind_link) &&
+ !i915_vma_is_purged(vma))
+ list_add_tail(>vm_rebind_link,
+ >vm->vm_rebind_list);
+ spin_unlock(>vm->vm_rebind_lock);
+ }
+
return 0;
}
@@ -2064,8 +2083,7 @@ static struct dma_fence *__i915_vma_unbind_async(struct
i915_vma *vma)
if (!drm_mm_node_allocated(>node))
return NULL;
- if (i915_vma_is_pinned(vma) ||
- >obj->mm.rsgt->table != vma->resource->bi.pages)
+ if (i915_vma_is_pinned(vma))
return ERR_PTR(-EAGAIN);
/*
@@ -2087,6 +2105,15 @@ static struct dma_fence *__i915_vma_unbind_async(struct
i915_vma *vma)
drm_mm_remove_node(>node); /* pairs with i915_vma_release() */
+ if (i915_vma_is_persistent(vma)) {
+
[Intel-gfx] [PATCH v8 10/22] drm/i915/vm_bind: Abstract out common execbuf functions
The new execbuf3 ioctl path and the legacy execbuf ioctl
paths have many common functionalities.
Abstract out the common execbuf functionalities into a
separate file where possible, thus allowing code sharing.
v2: Use drm_dbg instead of DRM_DEBUG
Reviewed-by: Andi Shyti
Reviewed-by: Matthew Auld
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/gem/i915_gem_execbuffer_common.c | 671 ++
.../drm/i915/gem/i915_gem_execbuffer_common.h | 76 ++
3 files changed, 748 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 71d5c992..81ce17f4406b 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -150,6 +150,7 @@ gem-y += \
gem/i915_gem_create.o \
gem/i915_gem_dmabuf.o \
gem/i915_gem_domain.o \
+ gem/i915_gem_execbuffer_common.o \
gem/i915_gem_execbuffer.o \
gem/i915_gem_internal.o \
gem/i915_gem_object.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c
new file mode 100644
index ..fb1364f08a61
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c
@@ -0,0 +1,671 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include
+
+#include
+
+#include "gt/intel_context.h"
+#include "gt/intel_gt.h"
+#include "gt/intel_gt_pm.h"
+#include "gt/intel_ring.h"
+
+#include "i915_drv.h"
+#include "i915_gem_execbuffer_common.h"
+
+#define __EXEC_COMMON_FENCE_WAIT BIT(0)
+#define __EXEC_COMMON_FENCE_SIGNAL BIT(1)
+
+static struct i915_request *eb_throttle(struct intel_context *ce)
+{
+ struct intel_ring *ring = ce->ring;
+ struct intel_timeline *tl = ce->timeline;
+ struct i915_request *rq;
+
+ /*
+* Completely unscientific finger-in-the-air estimates for suitable
+* maximum user request size (to avoid blocking) and then backoff.
+*/
+ if (intel_ring_update_space(ring) >= PAGE_SIZE)
+ return NULL;
+
+ /*
+* Find a request that after waiting upon, there will be at least half
+* the ring available. The hysteresis allows us to compete for the
+* shared ring and should mean that we sleep less often prior to
+* claiming our resources, but not so long that the ring completely
+* drains before we can submit our next request.
+*/
+ list_for_each_entry(rq, >requests, link) {
+ if (rq->ring != ring)
+ continue;
+
+ if (__intel_ring_space(rq->postfix,
+ ring->emit, ring->size) > ring->size / 2)
+ break;
+ }
+ if (>link == >requests)
+ return NULL; /* weird, we will check again later for real */
+
+ return i915_request_get(rq);
+}
+
+static int eb_pin_timeline(struct intel_context *ce, bool throttle,
+ bool nonblock)
+{
+ struct intel_timeline *tl;
+ struct i915_request *rq = NULL;
+
+ /*
+* Take a local wakeref for preparing to dispatch the execbuf as
+* we expect to access the hardware fairly frequently in the
+* process, and require the engine to be kept awake between accesses.
+* Upon dispatch, we acquire another prolonged wakeref that we hold
+* until the timeline is idle, which in turn releases the wakeref
+* taken on the engine, and the parent device.
+*/
+ tl = intel_context_timeline_lock(ce);
+ if (IS_ERR(tl))
+ return PTR_ERR(tl);
+
+ intel_context_enter(ce);
+ if (throttle)
+ rq = eb_throttle(ce);
+ intel_context_timeline_unlock(tl);
+
+ if (rq) {
+ long timeout = nonblock ? 0 : MAX_SCHEDULE_TIMEOUT;
+
+ if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE,
+ timeout) < 0) {
+ i915_request_put(rq);
+
+ /*
+* Error path, cannot use intel_context_timeline_lock as
+* that is user interruptable and this clean up step
+* must be done.
+*/
+ mutex_lock(>timeline->mutex);
+ intel_context_exit(ce);
+ mutex_unlock(>timeline->mutex);
+
+ if (nonblock)
+ return -EWOULDBLOCK;
+ else
+ return -EINTR;
+ }
+ i915_request_put(rq);
+ }
+
+ return 0;
+}
+
+/**
+ * i915_eb_pin_engine() - Pin the engine
+ * @ce:
[Intel-gfx] [PATCH v8 21/22] drm/i915/vm_bind: Properly build persistent map sg table
Properly build the sg table for persistent mapping which can
be partial map of the underlying object. Ensure the sg pages
are properly set for page backed regions. The dump capture
support requires this for page backed regions.
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/drm/i915/i915_vma.c | 120 +++-
1 file changed, 119 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 1b9033865768..68a9ac77b4f2 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -1298,6 +1298,120 @@ intel_partial_pages(const struct i915_gtt_view *view,
return ERR_PTR(ret);
}
+static unsigned int
+intel_copy_dma_sg(struct sg_table *src_st, struct sg_table *dst_st,
+ u64 offset, u64 length, bool dry_run)
+{
+ struct scatterlist *dst_sg, *src_sg;
+ unsigned int i, len, nents = 0;
+
+ dst_sg = dst_st->sgl;
+ for_each_sgtable_dma_sg(src_st, src_sg, i) {
+ if (sg_dma_len(src_sg) <= offset) {
+ offset -= sg_dma_len(src_sg);
+ continue;
+ }
+
+ nents++;
+ len = min(sg_dma_len(src_sg) - offset, length);
+ if (!dry_run) {
+ sg_dma_address(dst_sg) = sg_dma_address(src_sg) +
offset;
+ sg_dma_len(dst_sg) = len;
+ dst_sg = sg_next(dst_sg);
+ }
+
+ length -= len;
+ offset = 0;
+ if (!length)
+ break;
+ }
+ WARN_ON_ONCE(length);
+
+ return nents;
+}
+
+static unsigned int
+intel_copy_sg(struct sg_table *src_st, struct sg_table *dst_st,
+ u64 offset, u64 length, bool dry_run)
+{
+ struct scatterlist *dst_sg, *src_sg;
+ unsigned int i, len, nents = 0;
+
+ dst_sg = dst_st->sgl;
+ for_each_sgtable_sg(src_st, src_sg, i) {
+ if (src_sg->length <= offset) {
+ offset -= src_sg->length;
+ continue;
+ }
+
+ nents++;
+ len = min(src_sg->length - offset, length);
+ if (!dry_run) {
+ unsigned long pfn;
+
+ pfn = page_to_pfn(sg_page(src_sg)) + offset / PAGE_SIZE;
+ sg_set_page(dst_sg, pfn_to_page(pfn), len, 0);
+ dst_sg = sg_next(dst_sg);
+ }
+
+ length -= len;
+ offset = 0;
+ if (!length)
+ break;
+ }
+ WARN_ON_ONCE(length);
+
+ return nents;
+}
+
+static noinline struct sg_table *
+intel_persistent_partial_pages(const struct i915_gtt_view *view,
+ struct drm_i915_gem_object *obj)
+{
+ u64 offset = view->partial.offset << PAGE_SHIFT;
+ struct sg_table *st, *obj_st = obj->mm.pages;
+ u64 length = view->partial.size << PAGE_SHIFT;
+ struct scatterlist *sg;
+ unsigned int nents;
+ int ret = -ENOMEM;
+
+ st = kmalloc(sizeof(*st), GFP_KERNEL);
+ if (!st)
+ goto err_st_alloc;
+
+ /* Get required sg_table size */
+ nents = intel_copy_dma_sg(obj_st, st, offset, length, true);
+ if (i915_gem_object_has_struct_page(obj)) {
+ unsigned int pg_nents;
+
+ pg_nents = intel_copy_sg(obj_st, st, offset, length, true);
+ if (nents < pg_nents)
+ nents = pg_nents;
+ }
+
+ ret = sg_alloc_table(st, nents, GFP_KERNEL);
+ if (ret)
+ goto err_sg_alloc;
+
+ /* Build sg_table for specified section */
+ intel_copy_dma_sg(obj_st, st, offset, length, false);
+ if (i915_gem_object_has_struct_page(obj))
+ intel_copy_sg(obj_st, st, offset, length, false);
+
+ /* Mark last sg */
+ sg = st->sgl;
+ while (sg_next(sg))
+ sg = sg_next(sg);
+ sg_mark_end(sg);
+
+ return st;
+
+err_sg_alloc:
+ kfree(st);
+err_st_alloc:
+ return ERR_PTR(ret);
+}
+
static int
__i915_vma_get_pages(struct i915_vma *vma)
{
@@ -1330,7 +1444,11 @@ __i915_vma_get_pages(struct i915_vma *vma)
break;
case I915_GTT_VIEW_PARTIAL:
- pages = intel_partial_pages(>gtt_view, vma->obj);
+ if (i915_vma_is_persistent(vma))
+ pages = intel_persistent_partial_pages(>gtt_view,
+ vma->obj);
+ else
+ pages = intel_partial_pages(>gtt_view, vma->obj);
break;
}
--
2.21.0.rc0.32.g243a4c7e27
[Intel-gfx] [PATCH v8 08/22] drm/i915/vm_bind: Support persistent vma activeness tracking
Do not use i915_vma activeness tracking for persistent vmas.
As persistent vmas are part of working set for each execbuf
submission on that address space (VM), a persistent vma is
active if the VM active. As vm->root_obj->base.resv will be
updated for each submission on that VM, it correctly
represent whether the VM is active or not.
Add i915_vm_is_active() and i915_vm_sync() functions based
on vm->root_obj->base.resv with DMA_RESV_USAGE_BOOKKEEP
usage. dma-resv fence list will be updated with this usage
during each submission with this VM in the new execbuf3
ioctl path.
Update i915_vma_is_active(), i915_vma_sync() and the
__i915_vma_unbind_async() functions to properly handle
persistent vmas.
v2: Ensure lvalue of dma_resv_wait_timeout() call is long.
Reviewed-by: Andi Shyti
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 39 +
drivers/gpu/drm/i915/i915_gem_gtt.h | 3 +++
drivers/gpu/drm/i915/i915_vma.c | 28 +
drivers/gpu/drm/i915/i915_vma.h | 25 +-
4 files changed, 83 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7bd1861ddbdf..1d8506548d4a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -25,6 +25,45 @@
#include "i915_trace.h"
#include "i915_vgpu.h"
+/**
+ * i915_vm_sync() - Wait until address space is not in use
+ * @vm: address space
+ *
+ * Waits until all requests using the address space are complete.
+ *
+ * Returns: 0 if success, -ve err code upon failure
+ */
+int i915_vm_sync(struct i915_address_space *vm)
+{
+ long ret;
+
+ /* Wait for all requests under this vm to finish */
+ ret = dma_resv_wait_timeout(vm->root_obj->base.resv,
+ DMA_RESV_USAGE_BOOKKEEP, false,
+ MAX_SCHEDULE_TIMEOUT);
+ if (ret < 0)
+ return ret;
+ else if (ret > 0)
+ return 0;
+ else
+ return -ETIMEDOUT;
+}
+
+/**
+ * i915_vm_is_active() - Check if address space is being used
+ * @vm: address space
+ *
+ * Check if any request using the specified address space is
+ * active.
+ *
+ * Returns: true if address space is active, false otherwise.
+ */
+bool i915_vm_is_active(const struct i915_address_space *vm)
+{
+ return !dma_resv_test_signaled(vm->root_obj->base.resv,
+ DMA_RESV_USAGE_BOOKKEEP);
+}
+
int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj,
struct sg_table *pages)
{
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 8c2f57eb5dda..a5bbdc59d9df 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -51,4 +51,7 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
#define PIN_OFFSET_MASKI915_GTT_PAGE_MASK
+int i915_vm_sync(struct i915_address_space *vm);
+bool i915_vm_is_active(const struct i915_address_space *vm);
+
#endif
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 8de9f7a5b306..9f284c3c6339 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -422,6 +422,24 @@ int i915_vma_wait_for_bind(struct i915_vma *vma)
return err;
}
+/**
+ * i915_vma_sync() - Wait for the vma to be idle
+ * @vma: vma to be tested
+ *
+ * Returns 0 on success and error code on failure
+ */
+int i915_vma_sync(struct i915_vma *vma)
+{
+ int ret;
+
+ /* Wait for the asynchronous bindings and pending GPU reads */
+ ret = i915_active_wait(>active);
+ if (ret || !i915_vma_is_persistent(vma) || i915_vma_is_purged(vma))
+ return ret;
+
+ return i915_vm_sync(vma->vm);
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
static int i915_vma_verify_bind_complete(struct i915_vma *vma)
{
@@ -1887,6 +1905,8 @@ int _i915_vma_move_to_active(struct i915_vma *vma,
int err;
assert_object_held(obj);
+ if (i915_vma_is_persistent(vma))
+ return -EINVAL;
GEM_BUG_ON(!vma->pages);
@@ -2101,6 +2121,14 @@ static struct dma_fence *__i915_vma_unbind_async(struct
i915_vma *vma)
return ERR_PTR(-EBUSY);
}
+ if (i915_vma_is_persistent(vma) &&
+ __i915_sw_fence_await_reservation(>resource->chain,
+ vma->vm->root_obj->base.resv,
+ DMA_RESV_USAGE_BOOKKEEP,
+ i915_fence_timeout(vma->vm->i915),
+ GFP_NOWAIT | __GFP_NOWARN) < 0)
+ return ERR_PTR(-EBUSY);
+
fence = __i915_vma_evict(vma, true);
drm_mm_remove_node(>node); /* pairs with i915_vma_release() */
diff --git
[Intel-gfx] [PATCH v8 06/22] drm/i915/vm_bind: Support for VM private BOs
Each VM creates a root_obj and shares it with all of its private objects
to use it as dma_resv object. This has a performance advantage as it
requires a single dma_resv object update for all private BOs vs list of
dma_resv objects update for shared BOs, in the execbuf path.
VM private BOs can be only mapped on specified VM and cannot be dmabuf
exported. Also, they are supported only in vm_bind mode.
v2: Pad struct drm_i915_gem_create_ext_vm_private for 64bit alignment,
add input validity checks.
v3: Create root_obj only for ppgtt.
v4: Fix releasing of obj->priv_root. Do not create vm->root_obj yet.
Allow vm private object creation only in vm_bind mode.
Replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode().
Reviewed-by: Matthew Auld
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 1 +
drivers/gpu/drm/i915/gem/i915_gem_create.c| 54 ++-
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c| 6 +++
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 4 ++
drivers/gpu/drm/i915/gem/i915_gem_object.c| 3 ++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 6 +++
.../drm/i915/gem/i915_gem_vm_bind_object.c| 9
drivers/gpu/drm/i915/gt/intel_gtt.c | 1 +
drivers/gpu/drm/i915/gt/intel_gtt.h | 4 ++
drivers/gpu/drm/i915/i915_vma.c | 1 +
drivers/gpu/drm/i915/i915_vma_types.h | 2 +
include/uapi/drm/i915_drm.h | 33
12 files changed, 122 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 3a696f61af92..7d3366975e6d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -83,6 +83,7 @@
#include "i915_file_private.h"
#include "i915_gem_context.h"
+#include "i915_gem_internal.h"
#include "i915_trace.h"
#include "i915_user_extensions.h"
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index 5c6e396ab74d..62648341780b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -11,6 +11,7 @@
#include "pxp/intel_pxp.h"
#include "i915_drv.h"
+#include "i915_gem_context.h"
#include "i915_gem_create.h"
#include "i915_trace.h"
#include "i915_user_extensions.h"
@@ -251,6 +252,7 @@ struct create_ext {
unsigned int n_placements;
unsigned int placement_mask;
unsigned long flags;
+ u32 vm_id;
};
static void repr_placements(char *buf, size_t size,
@@ -400,9 +402,32 @@ static int ext_set_protected(struct i915_user_extension
__user *base, void *data
return 0;
}
+static int ext_set_vm_private(struct i915_user_extension __user *base,
+ void *data)
+{
+ struct drm_i915_gem_create_ext_vm_private ext;
+ struct create_ext *ext_data = data;
+
+ if (copy_from_user(, base, sizeof(ext)))
+ return -EFAULT;
+
+ /* Reserved fields must be 0 */
+ if (ext.rsvd)
+ return -EINVAL;
+
+ /* vm_id 0 is reserved */
+ if (!ext.vm_id)
+ return -ENOENT;
+
+ ext_data->vm_id = ext.vm_id;
+
+ return 0;
+}
+
static const i915_user_extension_fn create_extensions[] = {
[I915_GEM_CREATE_EXT_MEMORY_REGIONS] = ext_set_placements,
[I915_GEM_CREATE_EXT_PROTECTED_CONTENT] = ext_set_protected,
+ [I915_GEM_CREATE_EXT_VM_PRIVATE] = ext_set_vm_private,
};
/**
@@ -418,6 +443,7 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void
*data,
struct drm_i915_private *i915 = to_i915(dev);
struct drm_i915_gem_create_ext *args = data;
struct create_ext ext_data = { .i915 = i915 };
+ struct i915_address_space *vm = NULL;
struct drm_i915_gem_object *obj;
int ret;
@@ -431,6 +457,17 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void
*data,
if (ret)
return ret;
+ if (ext_data.vm_id) {
+ vm = i915_gem_vm_lookup(file->driver_priv, ext_data.vm_id);
+ if (unlikely(!vm))
+ return -ENOENT;
+
+ if (!i915_gem_vm_is_vm_bind_mode(vm)) {
+ ret = -EINVAL;
+ goto vm_put;
+ }
+ }
+
if (!ext_data.n_placements) {
ext_data.placements[0] =
intel_memory_region_by_type(i915, INTEL_MEMORY_SYSTEM);
@@ -457,8 +494,21 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void
*data,
ext_data.placements,
ext_data.n_placements,
ext_data.flags);
- if (IS_ERR(obj))
- return PTR_ERR(obj);
+ if (IS_ERR(obj)) {
+ ret =
[Intel-gfx] [PATCH v8 02/22] drm/i915/vm_bind: Add __i915_sw_fence_await_reservation()
Add function __i915_sw_fence_await_reservation() for
asynchronous wait on a dma-resv object with specified
dma_resv_usage. This is required for async vma unbind
with vm_bind.
Reviewed-by: Matthew Auld
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/drm/i915/i915_sw_fence.c | 28 +---
drivers/gpu/drm/i915/i915_sw_fence.h | 23 +--
2 files changed, 38 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c
b/drivers/gpu/drm/i915/i915_sw_fence.c
index cc2a8821d22a..ae06d35db056 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence.c
@@ -7,7 +7,6 @@
#include
#include
#include
-#include
#include "i915_sw_fence.h"
#include "i915_selftest.h"
@@ -569,11 +568,26 @@ int __i915_sw_fence_await_dma_fence(struct i915_sw_fence
*fence,
return ret;
}
-int i915_sw_fence_await_reservation(struct i915_sw_fence *fence,
- struct dma_resv *resv,
- bool write,
- unsigned long timeout,
- gfp_t gfp)
+/**
+ * __i915_sw_fence_await_reservation() - Setup a fence to wait on a dma-resv
+ * object with specified usage.
+ * @fence: the fence that needs to wait
+ * @resv: dma-resv object
+ * @usage: dma_resv_usage (See enum dma_resv_usage)
+ * @timeout: how long to wait in jiffies
+ * @gfp: allocation mode
+ *
+ * Setup the @fence to asynchronously wait on dma-resv object @resv for
+ * @usage to complete before signaling.
+ *
+ * Returns 0 if there is nothing to wait on, -ve error code upon error
+ * and >0 upon successfully setting up the wait.
+ */
+int __i915_sw_fence_await_reservation(struct i915_sw_fence *fence,
+ struct dma_resv *resv,
+ enum dma_resv_usage usage,
+ unsigned long timeout,
+ gfp_t gfp)
{
struct dma_resv_iter cursor;
struct dma_fence *f;
@@ -582,7 +596,7 @@ int i915_sw_fence_await_reservation(struct i915_sw_fence
*fence,
debug_fence_assert(fence);
might_sleep_if(gfpflags_allow_blocking(gfp));
- dma_resv_iter_begin(, resv, dma_resv_usage_rw(write));
+ dma_resv_iter_begin(, resv, usage);
dma_resv_for_each_fence_unlocked(, f) {
pending = i915_sw_fence_await_dma_fence(fence, f, timeout,
gfp);
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.h
b/drivers/gpu/drm/i915/i915_sw_fence.h
index f752bfc7c6e1..9c4859dc4c0d 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.h
+++ b/drivers/gpu/drm/i915/i915_sw_fence.h
@@ -10,13 +10,13 @@
#define _I915_SW_FENCE_H_
#include
+#include
#include
#include
#include /* for NOTIFY_DONE */
#include
struct completion;
-struct dma_resv;
struct i915_sw_fence;
enum i915_sw_fence_notify {
@@ -89,11 +89,22 @@ int i915_sw_fence_await_dma_fence(struct i915_sw_fence
*fence,
unsigned long timeout,
gfp_t gfp);
-int i915_sw_fence_await_reservation(struct i915_sw_fence *fence,
- struct dma_resv *resv,
- bool write,
- unsigned long timeout,
- gfp_t gfp);
+int __i915_sw_fence_await_reservation(struct i915_sw_fence *fence,
+ struct dma_resv *resv,
+ enum dma_resv_usage usage,
+ unsigned long timeout,
+ gfp_t gfp);
+
+static inline int i915_sw_fence_await_reservation(struct i915_sw_fence *fence,
+ struct dma_resv *resv,
+ bool write,
+ unsigned long timeout,
+ gfp_t gfp)
+{
+ return __i915_sw_fence_await_reservation(fence, resv,
+dma_resv_usage_rw(write),
+timeout, gfp);
+}
bool i915_sw_fence_await(struct i915_sw_fence *fence);
void i915_sw_fence_complete(struct i915_sw_fence *fence);
--
2.21.0.rc0.32.g243a4c7e27
[Intel-gfx] [PATCH v8 04/22] drm/i915/vm_bind: Add support to create persistent vma
Add i915_vma_instance_persistent() to create persistent vmas.
Persistent vmas will use i915_gtt_view to support partial binding.
vma_lookup is tied to segment of the object instead of section
of VA space. Hence, it do not support aliasing. ie., multiple
mappings (at different VA) point to the same gtt_view of object.
Skip vma_lookup for persistent vmas to support aliasing.
v2: Remove unused I915_VMA_PERSISTENT definition,
update validity check in i915_vma_compare(),
remove unwanted is_persistent check in release_references().
Reviewed-by: Matthew Auld
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/i915_vma.c | 36 +--
drivers/gpu/drm/i915/i915_vma.h | 17 -
drivers/gpu/drm/i915/i915_vma_types.h | 6 +
3 files changed, 56 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 726705b10637..9462a29764eb 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -111,7 +111,8 @@ static void __i915_vma_retire(struct i915_active *ref)
static struct i915_vma *
vma_create(struct drm_i915_gem_object *obj,
struct i915_address_space *vm,
- const struct i915_gtt_view *view)
+ const struct i915_gtt_view *view,
+ bool skip_lookup_cache)
{
struct i915_vma *pos = ERR_PTR(-E2BIG);
struct i915_vma *vma;
@@ -198,6 +199,9 @@ vma_create(struct drm_i915_gem_object *obj,
__set_bit(I915_VMA_GGTT_BIT, __i915_vma_flags(vma));
}
+ if (skip_lookup_cache)
+ goto skip_rb_insert;
+
rb = NULL;
p = >vma.tree.rb_node;
while (*p) {
@@ -222,6 +226,7 @@ vma_create(struct drm_i915_gem_object *obj,
rb_link_node(>obj_node, rb, p);
rb_insert_color(>obj_node, >vma.tree);
+skip_rb_insert:
if (i915_vma_is_ggtt(vma))
/*
* We put the GGTT vma at the start of the vma-list, followed
@@ -301,7 +306,34 @@ i915_vma_instance(struct drm_i915_gem_object *obj,
/* vma_create() will resolve the race if another creates the vma */
if (unlikely(!vma))
- vma = vma_create(obj, vm, view);
+ vma = vma_create(obj, vm, view, false);
+
+ GEM_BUG_ON(!IS_ERR(vma) && i915_vma_compare(vma, vm, view));
+ return vma;
+}
+
+/**
+ * i915_vma_create_persistent - create a persistent VMA
+ * @obj: parent drm_i915_gem_object to be mapped
+ * @vm: address space in which the mapping is located
+ * @view: additional mapping requirements
+ *
+ * Creates a persistent vma.
+ *
+ * Returns the vma, or an error pointer.
+ */
+struct i915_vma *
+i915_vma_create_persistent(struct drm_i915_gem_object *obj,
+ struct i915_address_space *vm,
+ const struct i915_gtt_view *view)
+{
+ struct i915_vma *vma;
+
+ GEM_BUG_ON(!kref_read(>ref));
+
+ vma = vma_create(obj, vm, view, true);
+ if (!IS_ERR(vma))
+ i915_vma_set_persistent(vma);
GEM_BUG_ON(!IS_ERR(vma) && i915_vma_compare(vma, vm, view));
return vma;
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 0757977a489b..0a4662fbe6c3 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -44,6 +44,10 @@ struct i915_vma *
i915_vma_instance(struct drm_i915_gem_object *obj,
struct i915_address_space *vm,
const struct i915_gtt_view *view);
+struct i915_vma *
+i915_vma_create_persistent(struct drm_i915_gem_object *obj,
+ struct i915_address_space *vm,
+ const struct i915_gtt_view *view);
void i915_vma_unpin_and_release(struct i915_vma **p_vma, unsigned int flags);
#define I915_VMA_RELEASE_MAP BIT(0)
@@ -139,6 +143,16 @@ static inline u32 i915_ggtt_pin_bias(struct i915_vma *vma)
return i915_vm_to_ggtt(vma->vm)->pin_bias;
}
+static inline bool i915_vma_is_persistent(const struct i915_vma *vma)
+{
+ return test_bit(I915_VMA_PERSISTENT_BIT, __i915_vma_flags(vma));
+}
+
+static inline void i915_vma_set_persistent(struct i915_vma *vma)
+{
+ set_bit(I915_VMA_PERSISTENT_BIT, __i915_vma_flags(vma));
+}
+
static inline struct i915_vma *i915_vma_get(struct i915_vma *vma)
{
i915_gem_object_get(vma->obj);
@@ -165,7 +179,8 @@ i915_vma_compare(struct i915_vma *vma,
{
ptrdiff_t cmp;
- GEM_BUG_ON(view && !i915_is_ggtt_or_dpt(vm));
+ GEM_BUG_ON(view && !(i915_is_ggtt_or_dpt(vm) ||
+i915_vma_is_persistent(vma)));
cmp = ptrdiff(vma->vm, vm);
if (cmp)
diff --git a/drivers/gpu/drm/i915/i915_vma_types.h
b/drivers/gpu/drm/i915/i915_vma_types.h
index ec0f6c9f57d0..3144d71a0c3e 100644
--- a/drivers/gpu/drm/i915/i915_vma_types.h
+++ b/drivers/gpu/drm/i915/i915_vma_types.h
@@ -264,6
[Intel-gfx] [PATCH v8 05/22] drm/i915/vm_bind: Implement bind and unbind of object
Add uapi and implement support for bind and unbind of an
object at the specified GPU virtual addresses.
The vm_bind mode is not supported in legacy execbuf2 ioctl.
It will be supported only in the newer execbuf3 ioctl.
v2: On older platforms ctx->vm is not set, check for it.
In vm_bind call, add vma to vm_bind_list.
Add more input validity checks.
Update some documentation.
v3: In vm_bind call, add vma to vm_bound_list as user can
request a fence and pass to execbuf3 as input fence.
Remove short term pinning with PIN_VALIDATE flag.
v4: Replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode().
v5: Ensure all reserved fields are 0, use PIN_NOEVICT.
v6: Add reserved fields to drm_i915_gem_vm_bind.
Reviewed-by: Matthew Auld
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Prathap Kumar Valsan
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_context.h | 15 +
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 5 +
drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h | 26 ++
.../drm/i915/gem/i915_gem_vm_bind_object.c| 330 ++
drivers/gpu/drm/i915/gt/intel_gtt.c | 10 +
drivers/gpu/drm/i915/gt/intel_gtt.h | 9 +
drivers/gpu/drm/i915/i915_driver.c| 3 +
drivers/gpu/drm/i915/i915_vma.c | 1 +
drivers/gpu/drm/i915/i915_vma_types.h | 14 +
include/uapi/drm/i915_drm.h | 105 ++
11 files changed, 519 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 01974b82d205..71d5c992 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -168,6 +168,7 @@ gem-y += \
gem/i915_gem_ttm_move.o \
gem/i915_gem_ttm_pm.o \
gem/i915_gem_userptr.o \
+ gem/i915_gem_vm_bind_object.o \
gem/i915_gem_wait.o \
gem/i915_gemfs.o
i915-y += \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index 899fa8f1e0fe..e8b41aa8f8c4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -139,6 +139,21 @@ int i915_gem_context_setparam_ioctl(struct drm_device
*dev, void *data,
int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
+/**
+ * i915_gem_vm_is_vm_bind_mode() - Check if address space is in vm_bind mode
+ * @vm: the address space
+ *
+ * Returns:
+ * true: @vm is in vm_bind mode; allows only vm_bind method of binding.
+ * false: @vm is not in vm_bind mode; allows only legacy execbuff method
+ *of binding.
+ */
+static inline bool i915_gem_vm_is_vm_bind_mode(struct i915_address_space *vm)
+{
+ /* No support to enable vm_bind mode yet */
+ return false;
+}
+
struct i915_address_space *
i915_gem_vm_lookup(struct drm_i915_file_private *file_priv, u32 id);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 29e9e8d5b6fe..6fdb7ce09afc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -782,6 +782,11 @@ static int eb_select_context(struct i915_execbuffer *eb)
if (unlikely(IS_ERR(ctx)))
return PTR_ERR(ctx);
+ if (ctx->vm && i915_gem_vm_is_vm_bind_mode(ctx->vm)) {
+ i915_gem_context_put(ctx);
+ return -EOPNOTSUPP;
+ }
+
eb->gem_context = ctx;
if (i915_gem_context_has_full_ppgtt(ctx))
eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
new file mode 100644
index ..36262a6357b5
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __I915_GEM_VM_BIND_H
+#define __I915_GEM_VM_BIND_H
+
+#include
+
+struct drm_device;
+struct drm_file;
+struct i915_address_space;
+struct i915_vma;
+
+struct i915_vma *
+i915_gem_vm_bind_lookup_vma(struct i915_address_space *vm, u64 va);
+
+int i915_gem_vm_bind_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file);
+int i915_gem_vm_unbind_ioctl(struct drm_device *dev, void *data,
+struct drm_file *file);
+
+void i915_gem_vm_unbind_all(struct i915_address_space *vm);
+
+#endif /* __I915_GEM_VM_BIND_H */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
new file mode 100644
index ..5064aba9ab87
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
[Intel-gfx] [PATCH v8 20/22] drm/i915/vm_bind: Async vm_unbind support
Asynchronously unbind the vma upon vm_unbind call.
Fall back to synchronous unbind if backend doesn't support
async unbind or if async unbind fails.
No need for vm_unbind out fence support as i915 will internally
handle all sequencing and user need not try to sequence any
operation with the unbind completion.
v2: use i915_vma_destroy_async in vm_unbind ioctl
v3: Add force_unbind function variants
Reviewed-by: Matthew Auld
Reviewed-by: Andi Shyti
Signed-off-by: Niranjana Vishwanathapura
---
.../drm/i915/gem/i915_gem_vm_bind_object.c| 2 +-
drivers/gpu/drm/i915/i915_vma.c | 49 ++-
drivers/gpu/drm/i915/i915_vma.h | 1 +
include/uapi/drm/i915_drm.h | 3 +-
4 files changed, 51 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
index 1cc0b8a4e0e7..78e7c0642c5f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
@@ -210,7 +210,7 @@ static int i915_gem_vm_unbind_vma(struct i915_address_space
*vm,
*/
obj = vma->obj;
i915_gem_object_lock(obj, NULL);
- i915_vma_destroy(vma);
+ i915_vma_destroy_async(vma);
i915_gem_object_unlock(obj);
i915_gem_object_put(obj);
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 5240463d5b48..1b9033865768 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -42,6 +42,8 @@
#include "i915_vma.h"
#include "i915_vma_resource.h"
+static struct dma_fence *__i915_vma_unbind_async(struct i915_vma *vma);
+
static inline void assert_vma_held_evict(const struct i915_vma *vma)
{
/*
@@ -1716,7 +1718,7 @@ void i915_vma_reopen(struct i915_vma *vma)
spin_unlock_irq(>closed_lock);
}
-static void force_unbind(struct i915_vma *vma)
+static void __force_unbind(struct i915_vma *vma, bool async)
{
if (!drm_mm_node_allocated(>node))
return;
@@ -1730,10 +1732,26 @@ static void force_unbind(struct i915_vma *vma)
i915_vma_set_purged(vma);
atomic_and(~I915_VMA_PIN_MASK, >flags);
- WARN_ON(__i915_vma_unbind(vma));
+ if (async) {
+ struct dma_fence *fence;
+
+ fence = __i915_vma_unbind_async(vma);
+ if (IS_ERR_OR_NULL(fence)) {
+ async = false;
+ } else {
+ dma_resv_add_fence(vma->obj->base.resv, fence,
+ DMA_RESV_USAGE_READ);
+ dma_fence_put(fence);
+ }
+ }
+
+ if (!async)
+ WARN_ON(__i915_vma_unbind(vma));
GEM_BUG_ON(drm_mm_node_allocated(>node));
}
+#define force_unbind(vma) __force_unbind((vma), false)
+
static void release_references(struct i915_vma *vma, struct intel_gt *gt,
bool vm_ddestroy)
{
@@ -1812,6 +1830,33 @@ void i915_vma_destroy(struct i915_vma *vma)
release_references(vma, gt, vm_ddestroy);
}
+void i915_vma_destroy_async(struct i915_vma *vma)
+{
+ bool vm_ddestroy, async = vma->obj->mm.rsgt;
+ struct intel_gt *gt;
+
+ if (dma_resv_reserve_fences(vma->obj->base.resv, 1))
+ async = false;
+
+ mutex_lock(>vm->mutex);
+ /*
+* Ensure any asynchronous binding is complete while using
+* async unbind as we will be releasing the vma here.
+*/
+ if (async && i915_active_wait(>active))
+ async = false;
+
+ __force_unbind(vma, async);
+ list_del_init(>vm_link);
+ vm_ddestroy = vma->vm_ddestroy;
+ vma->vm_ddestroy = false;
+
+ /* vma->vm may be freed when releasing vma->vm->mutex. */
+ gt = vma->vm->gt;
+ mutex_unlock(>vm->mutex);
+ release_references(vma, gt, vm_ddestroy);
+}
+
void i915_vma_parked(struct intel_gt *gt)
{
struct i915_vma *vma, *next;
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 1ecc71cf2698..5f783ce21e06 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -273,6 +273,7 @@ void i915_vma_reopen(struct i915_vma *vma);
void i915_vma_destroy_locked(struct i915_vma *vma);
void i915_vma_destroy(struct i915_vma *vma);
+void i915_vma_destroy_async(struct i915_vma *vma);
#define assert_vma_held(vma) dma_resv_assert_held((vma)->obj->base.resv)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 3f27001a2c8d..b9167f950327 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -3970,7 +3970,8 @@ struct drm_i915_gem_vm_bind {
* any error.
*
* VM_BIND/UNBIND ioctl calls executed on different CPU threads concurrently
- * are not ordered.
+ * are not ordered. Furthermore, parts of the VM_UNBIND operation can be done
+ *
[Intel-gfx] [PATCH v8 19/22] drm/i915/vm_bind: Render VM_BIND documentation
Update i915 documentation to include VM_BIND changes and render all VM_BIND related documentation. Reviewed-by: Matthew Auld Signed-off-by: Niranjana Vishwanathapura --- Documentation/gpu/i915.rst | 78 -- 1 file changed, 59 insertions(+), 19 deletions(-) diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 60ea21734902..01429a8f0d6c 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -283,15 +283,18 @@ An Intel GPU has multiple engines. There are several engine types. The Intel GPU family is a family of integrated GPU's using Unified Memory Access. For having the GPU "do work", user space will feed the -GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2` -or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will -instruct the GPU to perform work (for example rendering) and that work -needs memory from which to read and memory to which to write. All memory -is encapsulated within GEM buffer objects (usually created with the ioctl -`DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU -to create will also list all GEM buffer objects that the batchbuffer reads -and/or writes. For implementation details of memory management see -`GEM BO Management Implementation Details`_. +GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2`, +`DRM_IOCTL_I915_GEM_EXECBUFFER2_WR` or `DRM_IOCTL_I915_GEM_EXECBUFFER3`. +Most such batchbuffers will instruct the GPU to perform work (for example +rendering) and that work needs memory from which to read and memory to +which to write. All memory is encapsulated within GEM buffer objects +(usually created with the ioctl `DRM_IOCTL_I915_GEM_CREATE`). In vm_bind mode +(see `VM_BIND mode`_), the batch buffer and all the GEM buffer objects that +it reads and/or writes should be bound with vm_bind ioctl before submitting +the batch buffer to GPU. In legacy (non-VM_BIND) mode, an ioctl providing a +batchbuffer for the GPU to create will also list all GEM buffer objects that +the batchbuffer reads and/or writes. For implementation details of memory +management see `GEM BO Management Implementation Details`_. The i915 driver allows user space to create a context via the ioctl `DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit @@ -309,8 +312,9 @@ In addition to the ordering guarantees, the kernel will restore GPU state via HW context when commands are issued to a context, this saves user space the need to restore (most of atleast) the GPU state at the start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer -work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1) -to identify what context to use with the command. +work can pass that ID (drm_i915_gem_execbuffer3::ctx_id, or in the lower +bits of drm_i915_gem_execbuffer2::rsvd1) to identify what context to use +with the command. The GPU has its own memory management and address space. The kernel driver maintains the memory translation table for the GPU. For older @@ -318,14 +322,14 @@ GPUs (i.e. those before Gen8), there is a single global such translation table, a global Graphics Translation Table (GTT). For newer generation GPUs each context has its own translation table, called Per-Process Graphics Translation Table (PPGTT). Of important note, is that although -PPGTT is named per-process it is actually per context. When user space -submits a batchbuffer, the kernel walks the list of GEM buffer objects -used by the batchbuffer and guarantees that not only is the memory of -each such GEM buffer object resident but it is also present in the -(PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT, -then it is given an address. Two consequences of this are: the kernel -needs to edit the batchbuffer submitted to write the correct value of -the GPU address when a GEM BO is assigned a GPU address and the kernel +PPGTT is named per-process it is actually per context. In legacy +(non-vm_bind) mode, when user space submits a batchbuffer, the kernel walks +the list of GEM buffer objects used by the batchbuffer and guarantees that +not only is the memory of each such GEM buffer object resident but it is +also present in the (PP)GTT. If the GEM buffer object is not yet placed in +the (PP)GTT, then it is given an address. Two consequences of this are: the +kernel needs to edit the batchbuffer submitted to write the correct value +of the GPU address when a GEM BO is assigned a GPU address and the kernel might evict a different GEM BO from the (PP)GTT to make address room for another GEM BO. Consequently, the ioctls submitting a batchbuffer for execution also include a list of all locations within buffers that @@ -407,6 +411,15 @@ objects, which has the goal to make space in gpu virtual address spaces. .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_shrinker.c :internal: +VM_BIND mode + +
[Intel-gfx] [PATCH v8 11/22] drm/i915/vm_bind: Use common execbuf functions in execbuf path
Update the execbuf path to use common execbuf functions to
reduce code duplication with the newer execbuf3 path.
Reviewed-by: Matthew Auld
Signed-off-by: Niranjana Vishwanathapura
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 513 ++
1 file changed, 39 insertions(+), 474 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index aeb591d38a20..d8fa37acfba1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -28,6 +28,7 @@
#include "i915_file_private.h"
#include "i915_gem_clflush.h"
#include "i915_gem_context.h"
+#include "i915_gem_execbuffer_common.h"
#include "i915_gem_evict.h"
#include "i915_gem_ioctls.h"
#include "i915_reg.h"
@@ -236,13 +237,6 @@ enum {
* the batchbuffer in trusted mode, otherwise the ioctl is rejected.
*/
-struct eb_fence {
- struct drm_syncobj *syncobj; /* Use with ptr_mask_bits() */
- struct dma_fence *dma_fence;
- u64 value;
- struct dma_fence_chain *chain_fence;
-};
-
struct i915_execbuffer {
struct drm_i915_private *i915; /** i915 backpointer */
struct drm_file *file; /** per-file lookup tables and limits */
@@ -2449,164 +2443,29 @@ static const enum intel_engine_id user_ring_map[] = {
[I915_EXEC_VEBOX] = VECS0
};
-static struct i915_request *eb_throttle(struct i915_execbuffer *eb, struct
intel_context *ce)
-{
- struct intel_ring *ring = ce->ring;
- struct intel_timeline *tl = ce->timeline;
- struct i915_request *rq;
-
- /*
-* Completely unscientific finger-in-the-air estimates for suitable
-* maximum user request size (to avoid blocking) and then backoff.
-*/
- if (intel_ring_update_space(ring) >= PAGE_SIZE)
- return NULL;
-
- /*
-* Find a request that after waiting upon, there will be at least half
-* the ring available. The hysteresis allows us to compete for the
-* shared ring and should mean that we sleep less often prior to
-* claiming our resources, but not so long that the ring completely
-* drains before we can submit our next request.
-*/
- list_for_each_entry(rq, >requests, link) {
- if (rq->ring != ring)
- continue;
-
- if (__intel_ring_space(rq->postfix,
- ring->emit, ring->size) > ring->size / 2)
- break;
- }
- if (>link == >requests)
- return NULL; /* weird, we will check again later for real */
-
- return i915_request_get(rq);
-}
-
-static int eb_pin_timeline(struct i915_execbuffer *eb, struct intel_context
*ce,
- bool throttle)
-{
- struct intel_timeline *tl;
- struct i915_request *rq = NULL;
-
- /*
-* Take a local wakeref for preparing to dispatch the execbuf as
-* we expect to access the hardware fairly frequently in the
-* process, and require the engine to be kept awake between accesses.
-* Upon dispatch, we acquire another prolonged wakeref that we hold
-* until the timeline is idle, which in turn releases the wakeref
-* taken on the engine, and the parent device.
-*/
- tl = intel_context_timeline_lock(ce);
- if (IS_ERR(tl))
- return PTR_ERR(tl);
-
- intel_context_enter(ce);
- if (throttle)
- rq = eb_throttle(eb, ce);
- intel_context_timeline_unlock(tl);
-
- if (rq) {
- bool nonblock = eb->file->filp->f_flags & O_NONBLOCK;
- long timeout = nonblock ? 0 : MAX_SCHEDULE_TIMEOUT;
-
- if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE,
- timeout) < 0) {
- i915_request_put(rq);
-
- /*
-* Error path, cannot use intel_context_timeline_lock as
-* that is user interruptable and this clean up step
-* must be done.
-*/
- mutex_lock(>timeline->mutex);
- intel_context_exit(ce);
- mutex_unlock(>timeline->mutex);
-
- if (nonblock)
- return -EWOULDBLOCK;
- else
- return -EINTR;
- }
- i915_request_put(rq);
- }
-
- return 0;
-}
-
static int eb_pin_engine(struct i915_execbuffer *eb, bool throttle)
{
- struct intel_context *ce = eb->context, *child;
int err;
- int i = 0, j = 0;
GEM_BUG_ON(eb->args->flags & __EXEC_ENGINE_PINNED);
- if (unlikely(intel_context_is_banned(ce)))
- return -EIO;
-
- /*
-* Pinning the contexts may generate requests in
[Intel-gfx] [PATCH v8 22/22] drm/i915/vm_bind: Support capture of persistent mappings
Support dump capture of persistent mappings upon user request.
Signed-off-by: Brian Welty
Signed-off-by: Niranjana Vishwanathapura
---
.../drm/i915/gem/i915_gem_vm_bind_object.c| 11 +++
drivers/gpu/drm/i915/gt/intel_gtt.c | 3 +++
drivers/gpu/drm/i915/gt/intel_gtt.h | 5 +
drivers/gpu/drm/i915/i915_gpu_error.c | 19 +++
drivers/gpu/drm/i915/i915_vma.c | 1 +
drivers/gpu/drm/i915/i915_vma_types.h | 2 ++
include/uapi/drm/i915_drm.h | 3 ++-
7 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
index 78e7c0642c5f..50969613daf6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
@@ -88,6 +88,11 @@ static void i915_gem_vm_bind_remove(struct i915_vma *vma,
bool release_obj)
{
lockdep_assert_held(>vm->vm_bind_lock);
+ spin_lock(>vm->vm_capture_lock);
+ if (!list_empty(>vm_capture_link))
+ list_del_init(>vm_capture_link);
+ spin_unlock(>vm->vm_capture_lock);
+
spin_lock(>vm->vm_rebind_lock);
if (!list_empty(>vm_rebind_link))
list_del_init(>vm_rebind_link);
@@ -357,6 +362,12 @@ static int i915_gem_vm_bind_obj(struct i915_address_space
*vm,
continue;
}
+ if (va->flags & I915_GEM_VM_BIND_CAPTURE) {
+ spin_lock(>vm_capture_lock);
+ list_add_tail(>vm_capture_link,
>vm_capture_list);
+ spin_unlock(>vm_capture_lock);
+ }
+
list_add_tail(>vm_bind_link, >vm_bound_list);
i915_vm_bind_it_insert(vma, >va);
if (!obj->priv_root)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index ebf6830574a0..bdabe13fc30e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -297,6 +297,9 @@ void i915_address_space_init(struct i915_address_space *vm,
int subclass)
spin_lock_init(>vm_rebind_lock);
spin_lock_init(>userptr_invalidated_lock);
INIT_LIST_HEAD(>userptr_invalidated_list);
+
+ INIT_LIST_HEAD(>vm_capture_list);
+ spin_lock_init(>vm_capture_lock);
}
void *__px_vaddr(struct drm_i915_gem_object *p)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 87e5b6568a00..8e4ddd073348 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -281,6 +281,11 @@ struct i915_address_space {
/** @root_obj: root object for dma-resv sharing by private objects */
struct drm_i915_gem_object *root_obj;
+ /* @vm_capture_list: list of vm captures */
+ struct list_head vm_capture_list;
+ /* @vm_capture_lock: protects vm_capture_list */
+ spinlock_t vm_capture_lock;
+
/* Global GTT */
bool is_ggtt:1;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 9d5d5a397b64..3b2b12a739f7 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1460,6 +1460,22 @@ capture_vma(struct intel_engine_capture_vma *next,
return next;
}
+static struct intel_engine_capture_vma *
+capture_user_vm(struct intel_engine_capture_vma *capture,
+ struct i915_address_space *vm, gfp_t gfp)
+{
+ struct i915_vma *vma;
+
+ spin_lock(>vm_capture_lock);
+ /* vma->resource must be valid here as persistent vmas are bound */
+ list_for_each_entry(vma, >vm_capture_list, vm_capture_link)
+ capture = capture_vma_snapshot(capture, vma->resource,
+ gfp, "user");
+ spin_unlock(>vm_capture_lock);
+
+ return capture;
+}
+
static struct intel_engine_capture_vma *
capture_user(struct intel_engine_capture_vma *capture,
const struct i915_request *rq,
@@ -1471,6 +1487,9 @@ capture_user(struct intel_engine_capture_vma *capture,
capture = capture_vma_snapshot(capture, c->vma_res, gfp,
"user");
+ capture = capture_user_vm(capture, rq->context->vm,
+ GFP_NOWAIT | __GFP_NOWARN);
+
return capture;
}
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 68a9ac77b4f2..0244864e94f7 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -248,6 +248,7 @@ vma_create(struct drm_i915_gem_object *obj,
INIT_LIST_HEAD(>non_priv_vm_bind_link);
INIT_LIST_HEAD(>vm_rebind_link);
INIT_LIST_HEAD(>userptr_invalidated_link);
+ INIT_LIST_HEAD(>vm_capture_link);
return vma;
err_unlock:
diff --git
[Intel-gfx] [PATCH v8 12/22] drm/i915/vm_bind: Implement I915_GEM_EXECBUFFER3 ioctl
Implement new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only
works in vm_bind mode. The vm_bind mode only works with
this new execbuf3 ioctl.
The new execbuf3 ioctl will not have any list of objects to validate
bind as all required objects binding would have been requested by the
userspace before submitting the execbuf3.
Legacy features like relocations etc are not supported by execbuf3.
v2: Add more input validity checks.
v3: batch_address is a VA (not an array) if num_batches=1,
minor cleanup
v4: replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode()
v5: Remove unwanted krealloc() and address other review comments.
Reviewed-by: Matthew Auld
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/Makefile | 1 +
.../gpu/drm/i915/gem/i915_gem_execbuffer3.c | 579 ++
drivers/gpu/drm/i915/gem/i915_gem_ioctls.h| 2 +
drivers/gpu/drm/i915/i915_driver.c| 1 +
include/uapi/drm/i915_drm.h | 61 ++
5 files changed, 644 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 81ce17f4406b..e5a4cf20839b 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -152,6 +152,7 @@ gem-y += \
gem/i915_gem_domain.o \
gem/i915_gem_execbuffer_common.o \
gem/i915_gem_execbuffer.o \
+ gem/i915_gem_execbuffer3.o \
gem/i915_gem_internal.o \
gem/i915_gem_object.o \
gem/i915_gem_lmem.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
new file mode 100644
index ..49045858a3e9
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
@@ -0,0 +1,579 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include
+#include
+
+#include
+
+#include "gt/intel_context.h"
+#include "gt/intel_gpu_commands.h"
+#include "gt/intel_gt.h"
+
+#include "i915_drv.h"
+#include "i915_gem_context.h"
+#include "i915_gem_execbuffer_common.h"
+#include "i915_gem_ioctls.h"
+#include "i915_gem_vm_bind.h"
+#include "i915_trace.h"
+
+#define __EXEC3_ENGINE_PINNED BIT_ULL(32)
+#define __EXEC3_INTERNAL_FLAGS (~0ull << 32)
+
+/* Catch emission of unexpected errors for CI! */
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
+#undef EINVAL
+#define EINVAL ({ \
+ DRM_DEBUG_DRIVER("EINVAL at %s:%d\n", __func__, __LINE__); \
+ 22; \
+})
+#endif
+
+/**
+ * DOC: User command execution in vm_bind mode
+ *
+ * A VM in VM_BIND mode will not support older execbuf mode of binding.
+ * The execbuf ioctl handling in VM_BIND mode differs significantly from the
+ * older execbuf2 ioctl (See struct drm_i915_gem_execbuffer2).
+ * Hence, a new execbuf3 ioctl has been added to support VM_BIND mode. (See
+ * struct drm_i915_gem_execbuffer3). The execbuf3 ioctl will not accept any
+ * execlist. Hence, no support for implicit sync.
+ *
+ * The new execbuf3 ioctl only works in VM_BIND mode and the VM_BIND mode only
+ * works with execbuf3 ioctl for submission.
+ *
+ * The execbuf3 ioctl directly specifies the batch addresses instead of as
+ * object handles as in execbuf2 ioctl. The execbuf3 ioctl will also not
+ * support many of the older features like in/out/submit fences, fence array,
+ * default gem context etc. (See struct drm_i915_gem_execbuffer3).
+ *
+ * In VM_BIND mode, VA allocation is completely managed by the user instead of
+ * the i915 driver. Hence all VA assignment, eviction are not applicable in
+ * VM_BIND mode. Also, for determining object activeness, VM_BIND mode will not
+ * be using the i915_vma active reference tracking. It will instead check the
+ * dma-resv object's fence list for that.
+ *
+ * So, a lot of code supporting execbuf2 ioctl, like relocations, VA evictions,
+ * vma lookup table, implicit sync, vma active reference tracking etc., are not
+ * applicable for execbuf3 ioctl.
+ */
+
+/**
+ * struct i915_execbuffer - execbuf struct for execbuf3
+ * @i915: reference to the i915 instance we run on
+ * @file: drm file reference
+ * @args: execbuf3 ioctl structure
+ * @gt: reference to the gt instance ioctl submitted for
+ * @context: logical state for the request
+ * @gem_context: callers context
+ * @requests: requests to be build
+ * @composite_fence: used for excl fence in dma_resv objects when > 1 BB
submitted
+ * @ww: i915_gem_ww_ctx instance
+ * @num_batches: number of batches submitted
+ * @batch_addresses: addresses corresponds to the submitted batches
+ * @batches: references to the i915_vmas corresponding to the batches
+ * @fences: array of execbuf fences (See struct eb_fence)
+ * @num_fences: number of fences in @fences array
+ */
+struct i915_execbuffer {
+ struct drm_i915_private *i915;
+ struct drm_file *file;
+ struct drm_i915_gem_execbuffer3 *args;
+
+
[Intel-gfx] [PATCH v8 15/22] drm/i915/vm_bind: Handle persistent vmas in execbuf3
Handle persistent (VM_BIND) mappings during the request submission
in the execbuf3 path.
v2: Ensure requests wait for bindings to complete.
v3: Remove short term pinning with PIN_VALIDATE flag.
Individualize fences before adding to dma_resv obj.
v4: Fix bind completion check, use PIN_NOEVICT,
use proper lock while checking if vm_rebind_list is empty.
Reviewed-by: Matthew Auld
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Andi Shyti
---
.../gpu/drm/i915/gem/i915_gem_execbuffer3.c | 215 +-
1 file changed, 214 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
index 49045858a3e9..913b1f8bda9f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
@@ -3,6 +3,7 @@
* Copyright © 2022 Intel Corporation
*/
+#include
#include
#include
@@ -19,6 +20,7 @@
#include "i915_gem_vm_bind.h"
#include "i915_trace.h"
+#define __EXEC3_HAS_PINBIT_ULL(33)
#define __EXEC3_ENGINE_PINNED BIT_ULL(32)
#define __EXEC3_INTERNAL_FLAGS (~0ull << 32)
@@ -42,7 +44,9 @@
* execlist. Hence, no support for implicit sync.
*
* The new execbuf3 ioctl only works in VM_BIND mode and the VM_BIND mode only
- * works with execbuf3 ioctl for submission.
+ * works with execbuf3 ioctl for submission. All BOs mapped on that VM (through
+ * VM_BIND call) at the time of execbuf3 call are deemed required for that
+ * submission.
*
* The execbuf3 ioctl directly specifies the batch addresses instead of as
* object handles as in execbuf2 ioctl. The execbuf3 ioctl will also not
@@ -58,6 +62,13 @@
* So, a lot of code supporting execbuf2 ioctl, like relocations, VA evictions,
* vma lookup table, implicit sync, vma active reference tracking etc., are not
* applicable for execbuf3 ioctl.
+ *
+ * During each execbuf submission, request fence is added to all VM_BIND mapped
+ * objects with DMA_RESV_USAGE_BOOKKEEP. The DMA_RESV_USAGE_BOOKKEEP usage will
+ * prevent over sync (See enum dma_resv_usage). Note that DRM_I915_GEM_WAIT and
+ * DRM_I915_GEM_BUSY ioctls do not check for DMA_RESV_USAGE_BOOKKEEP usage and
+ * hence should not be used for end of batch check. Instead, the execbuf3
+ * timeline out fence should be used for end of batch check.
*/
/**
@@ -129,6 +140,23 @@ eb_find_vma(struct i915_address_space *vm, u64 addr)
return i915_gem_vm_bind_lookup_vma(vm, va);
}
+static void eb_scoop_unbound_vma_all(struct i915_address_space *vm)
+{
+ struct i915_vma *vma, *vn;
+
+ /**
+* Move all unbound vmas back into vm_bind_list so that they are
+* revalidated.
+*/
+ spin_lock(>vm_rebind_lock);
+ list_for_each_entry_safe(vma, vn, >vm_rebind_list, vm_rebind_link) {
+ list_del_init(>vm_rebind_link);
+ if (!list_empty(>vm_bind_link))
+ list_move_tail(>vm_bind_link, >vm_bind_list);
+ }
+ spin_unlock(>vm_rebind_lock);
+}
+
static int eb_lookup_vma_all(struct i915_execbuffer *eb)
{
struct i915_vma *vma;
@@ -142,14 +170,108 @@ static int eb_lookup_vma_all(struct i915_execbuffer *eb)
eb->batches[i] = vma;
}
+ eb_scoop_unbound_vma_all(eb->context->vm);
+
+ return 0;
+}
+
+static int eb_lock_vma_all(struct i915_execbuffer *eb)
+{
+ struct i915_address_space *vm = eb->context->vm;
+ struct i915_vma *vma;
+ int err;
+
+ err = i915_gem_object_lock(eb->context->vm->root_obj, >ww);
+ if (err)
+ return err;
+
+ list_for_each_entry(vma, >non_priv_vm_bind_list,
+ non_priv_vm_bind_link) {
+ err = i915_gem_object_lock(vma->obj, >ww);
+ if (err)
+ return err;
+ }
+
return 0;
}
+static void eb_release_persistent_vma_all(struct i915_execbuffer *eb)
+{
+ struct i915_address_space *vm = eb->context->vm;
+ struct i915_vma *vma, *vn;
+
+ lockdep_assert_held(>vm_bind_lock);
+
+ if (!(eb->args->flags & __EXEC3_HAS_PIN))
+ return;
+
+ assert_object_held(vm->root_obj);
+
+ list_for_each_entry_safe(vma, vn, >vm_bind_list, vm_bind_link)
+ if (!i915_vma_verify_bind_complete(vma))
+ list_move_tail(>vm_bind_link, >vm_bound_list);
+
+ eb->args->flags &= ~__EXEC3_HAS_PIN;
+}
+
static void eb_release_vma_all(struct i915_execbuffer *eb)
{
+ eb_release_persistent_vma_all(eb);
eb_unpin_engine(eb);
}
+static int eb_reserve_fence_for_persistent_vma_all(struct i915_execbuffer *eb)
+{
+ struct i915_address_space *vm = eb->context->vm;
+ u64 num_fences = 1;
+ struct i915_vma *vma;
+ int ret;
+
+ /* Reserve enough slots to accommodate composite fences */
+ if
[Intel-gfx] [PATCH v8 09/22] drm/i915/vm_bind: Add out fence support
Add support for handling out fence for vm_bind call.
v2: Reset vma->vm_bind_fence.syncobj to NULL at the end
of vm_bind call.
v3: Remove vm_unbind out fence uapi which is not supported yet.
v4: Return error if I915_TIMELINE_FENCE_WAIT fence flag is set.
Wait for bind to complete iff I915_TIMELINE_FENCE_SIGNAL is
not specified.
v5: Ensure __I915_TIMELINE_FENCE_UNKNOWN_FLAGS are not set.
Reviewed-by: Matthew Auld
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h | 4 +
.../drm/i915/gem/i915_gem_vm_bind_object.c| 98 ++-
drivers/gpu/drm/i915/i915_vma.c | 7 +-
drivers/gpu/drm/i915/i915_vma_types.h | 7 ++
include/uapi/drm/i915_drm.h | 58 ++-
5 files changed, 165 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
index 36262a6357b5..b70e900e35ab 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
@@ -8,6 +8,7 @@
#include
+struct dma_fence;
struct drm_device;
struct drm_file;
struct i915_address_space;
@@ -23,4 +24,7 @@ int i915_gem_vm_unbind_ioctl(struct drm_device *dev, void
*data,
void i915_gem_vm_unbind_all(struct i915_address_space *vm);
+void i915_vm_bind_signal_fence(struct i915_vma *vma,
+ struct dma_fence * const fence);
+
#endif /* __I915_GEM_VM_BIND_H */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
index dc738677466b..fd1d82ce99e6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
@@ -7,6 +7,8 @@
#include
+#include
+
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_vm_bind.h"
@@ -101,6 +103,77 @@ static void i915_gem_vm_bind_remove(struct i915_vma *vma,
bool release_obj)
i915_gem_object_put(vma->obj);
}
+static int i915_vm_bind_add_fence(struct drm_file *file, struct i915_vma *vma,
+ u32 handle, u64 point)
+{
+ struct drm_syncobj *syncobj;
+
+ syncobj = drm_syncobj_find(file, handle);
+ if (!syncobj) {
+ drm_dbg(>vm->i915->drm,
+ "Invalid syncobj handle provided\n");
+ return -ENOENT;
+ }
+
+ /*
+* For timeline syncobjs we need to preallocate chains for
+* later signaling.
+*/
+ if (point) {
+ vma->vm_bind_fence.chain_fence = dma_fence_chain_alloc();
+ if (!vma->vm_bind_fence.chain_fence) {
+ drm_syncobj_put(syncobj);
+ return -ENOMEM;
+ }
+ } else {
+ vma->vm_bind_fence.chain_fence = NULL;
+ }
+ vma->vm_bind_fence.syncobj = syncobj;
+ vma->vm_bind_fence.value = point;
+
+ return 0;
+}
+
+static void i915_vm_bind_put_fence(struct i915_vma *vma)
+{
+ if (!vma->vm_bind_fence.syncobj)
+ return;
+
+ drm_syncobj_put(vma->vm_bind_fence.syncobj);
+ dma_fence_chain_free(vma->vm_bind_fence.chain_fence);
+ vma->vm_bind_fence.syncobj = NULL;
+}
+
+/**
+ * i915_vm_bind_signal_fence() - Add fence to vm_bind syncobj
+ * @vma: vma mapping requiring signaling
+ * @fence: fence to be added
+ *
+ * Associate specified @fence with the @vma's syncobj to be
+ * signaled after the @fence work completes.
+ */
+void i915_vm_bind_signal_fence(struct i915_vma *vma,
+ struct dma_fence * const fence)
+{
+ struct drm_syncobj *syncobj = vma->vm_bind_fence.syncobj;
+
+ if (!syncobj)
+ return;
+
+ if (vma->vm_bind_fence.chain_fence) {
+ drm_syncobj_add_point(syncobj,
+ vma->vm_bind_fence.chain_fence,
+ fence, vma->vm_bind_fence.value);
+ /*
+* The chain's ownership is transferred to the
+* timeline.
+*/
+ vma->vm_bind_fence.chain_fence = NULL;
+ } else {
+ drm_syncobj_replace_fence(syncobj, fence);
+ }
+}
+
static int i915_gem_vm_unbind_vma(struct i915_address_space *vm,
struct drm_i915_gem_vm_unbind *va)
{
@@ -206,6 +279,11 @@ static int i915_gem_vm_bind_obj(struct i915_address_space
*vm,
if (!va->length || !IS_ALIGNED(va->start, I915_GTT_PAGE_SIZE))
ret = -EINVAL;
+ /* In fences are not supported */
+ if ((va->fence.flags & I915_TIMELINE_FENCE_WAIT) ||
+ (va->fence.flags & __I915_TIMELINE_FENCE_UNKNOWN_FLAGS))
+ ret = -EINVAL;
+
obj = i915_gem_object_lookup(file, va->handle);
if (!obj)
return -ENOENT;
@@ -238,6 +316,13 @@ static int
[Intel-gfx] [PATCH v8 03/22] drm/i915/vm_bind: Expose i915_gem_object_max_page_size()
Expose i915_gem_object_max_page_size() function non-static
which will be used by the vm_bind feature.
Reviewed-by: Matthew Auld
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 18 +-
drivers/gpu/drm/i915/gem/i915_gem_object.h | 2 ++
2 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index 33673fe7ee0a..5c6e396ab74d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -15,10 +15,18 @@
#include "i915_trace.h"
#include "i915_user_extensions.h"
-static u32 object_max_page_size(struct intel_memory_region **placements,
- unsigned int n_placements)
+/**
+ * i915_gem_object_max_page_size() - max of min_page_size of the regions
+ * @placements: list of regions
+ * @n_placements: number of the placements
+ *
+ * Returns the largest of min_page_size of the @placements,
+ * or I915_GTT_PAGE_SIZE_4K if @n_placements is 0.
+ */
+u32 i915_gem_object_max_page_size(struct intel_memory_region **placements,
+ unsigned int n_placements)
{
- u32 max_page_size = 0;
+ u32 max_page_size = I915_GTT_PAGE_SIZE_4K;
int i;
for (i = 0; i < n_placements; i++) {
@@ -28,7 +36,6 @@ static u32 object_max_page_size(struct intel_memory_region
**placements,
max_page_size = max_t(u32, max_page_size, mr->min_page_size);
}
- GEM_BUG_ON(!max_page_size);
return max_page_size;
}
@@ -99,7 +106,8 @@ __i915_gem_object_create_user_ext(struct drm_i915_private
*i915, u64 size,
i915_gem_flush_free_objects(i915);
- size = round_up(size, object_max_page_size(placements, n_placements));
+ size = round_up(size, i915_gem_object_max_page_size(placements,
+ n_placements));
if (size == 0)
return ERR_PTR(-EINVAL);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 3db53769864c..5455ca0eabe9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -47,6 +47,8 @@ static inline bool i915_gem_object_size_2big(u64 size)
}
void i915_gem_init__objects(struct drm_i915_private *i915);
+u32 i915_gem_object_max_page_size(struct intel_memory_region **placements,
+ unsigned int n_placements);
void i915_objects_module_exit(void);
int i915_objects_module_init(void);
--
2.21.0.rc0.32.g243a4c7e27
[Intel-gfx] [PATCH v8 18/22] drm/i915/vm_bind: Add uapi for user to enable vm_bind_mode
Add getparam support for VM_BIND capability version.
Add VM creation time flag to enable vm_bind_mode for the VM.
v2: update kernel-doc
v3: create vm->root_obj only upon I915_VM_CREATE_FLAGS_USE_VM_BIND
v4: replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode()
Reviewed-by: Matthew Auld
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 25 ++--
drivers/gpu/drm/i915/gem/i915_gem_context.h | 3 +--
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_getparam.c| 3 +++
include/uapi/drm/i915_drm.h | 26 -
6 files changed, 56 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index a048bf463916..a85f4febaafe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1809,9 +1809,13 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev,
void *data,
if (!HAS_FULL_PPGTT(i915))
return -ENODEV;
- if (args->flags)
+ if (args->flags & I915_VM_CREATE_FLAGS_UNKNOWN)
return -EINVAL;
+ if ((args->flags & I915_VM_CREATE_FLAGS_USE_VM_BIND) &&
+ !HAS_VM_BIND(i915))
+ return -EOPNOTSUPP;
+
ppgtt = i915_ppgtt_create(to_gt(i915), 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
@@ -1824,15 +1828,32 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev,
void *data,
goto err_put;
}
+ if (args->flags & I915_VM_CREATE_FLAGS_USE_VM_BIND) {
+ struct drm_i915_gem_object *obj;
+
+ obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ goto err_put;
+ }
+
+ ppgtt->vm.root_obj = obj;
+ }
+
err = xa_alloc(_priv->vm_xa, , >vm,
xa_limit_32b, GFP_KERNEL);
if (err)
- goto err_put;
+ goto err_root_obj_put;
GEM_BUG_ON(id == 0); /* reserved for invalid/unassigned ppgtt */
args->vm_id = id;
return 0;
+err_root_obj_put:
+ if (ppgtt->vm.root_obj) {
+ i915_gem_object_put(ppgtt->vm.root_obj);
+ ppgtt->vm.root_obj = NULL;
+ }
err_put:
i915_vm_put(>vm);
return err;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index e8b41aa8f8c4..b53aef2853cb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -150,8 +150,7 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev, void *data,
*/
static inline bool i915_gem_vm_is_vm_bind_mode(struct i915_address_space *vm)
{
- /* No support to enable vm_bind mode yet */
- return false;
+ return !!vm->root_obj;
}
struct i915_address_space *
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 0573b72ae678..ebf6830574a0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -179,6 +179,8 @@ int i915_vm_lock_objects(struct i915_address_space *vm,
void i915_address_space_fini(struct i915_address_space *vm)
{
drm_mm_takedown(>mm);
+ if (vm->root_obj)
+ i915_gem_object_put(vm->root_obj);
GEM_BUG_ON(!RB_EMPTY_ROOT(>va.rb_root));
mutex_destroy(>vm_bind_lock);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a380db36d52c..53653ad3ffa5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -967,6 +967,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
GRAPHICS_VER_FULL(i915) >= IP_VER(12,
70))
+#define HAS_VM_BIND(i915) (GRAPHICS_VER(i915) >= 12)
+
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_getparam.c
b/drivers/gpu/drm/i915/i915_getparam.c
index 61ef2d9cfa62..20c1bf904a65 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -178,6 +178,9 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
case I915_PARAM_OA_TIMESTAMP_FREQUENCY:
value = i915_perf_oa_timestamp_frequency(i915);
break;
+ case I915_PARAM_VM_BIND_VERSION:
+ value = HAS_VM_BIND(i915);
+ break;
default:
drm_dbg(>drm, "Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/include/uapi/drm/i915_drm.h
[Intel-gfx] [PATCH v8 01/22] drm/i915/vm_bind: Expose vm lookup function
Make i915_gem_vm_lookup() function non-static as it will be
used by the vm_bind feature.
Reviewed-by: Matthew Auld
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 11 ++-
drivers/gpu/drm/i915/gem/i915_gem_context.h | 3 +++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 7f2831efc798..3a696f61af92 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -346,7 +346,16 @@ static int proto_context_register(struct
drm_i915_file_private *fpriv,
return ret;
}
-static struct i915_address_space *
+/**
+ * i915_gem_vm_lookup() - looks up for the VM reference given the vm id
+ * @file_priv: the private data associated with the user's file
+ * @id: the VM id
+ *
+ * Finds the VM reference associated to a specific id.
+ *
+ * Returns the VM pointer on success, NULL in case of failure.
+ */
+struct i915_address_space *
i915_gem_vm_lookup(struct drm_i915_file_private *file_priv, u32 id)
{
struct i915_address_space *vm;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index e5b0f66ea1fe..899fa8f1e0fe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -139,6 +139,9 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev,
void *data,
int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
+struct i915_address_space *
+i915_gem_vm_lookup(struct drm_i915_file_private *file_priv, u32 id);
+
struct i915_gem_context *
i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id);
--
2.21.0.rc0.32.g243a4c7e27
[Intel-gfx] [PATCH v8 14/22] drm/i915/vm_bind: Expose i915_request_await_bind()
Rename __i915_request_await_bind() as i915_request_await_bind()
and make it non-static as it will be used in execbuf3 ioctl path.
v2: add documentation
Reviewed-by: Matthew Auld
Reviewed-by: Andi Shyti
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/drm/i915/i915_vma.c | 8 +---
drivers/gpu/drm/i915/i915_vma.h | 16
2 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index e382c8a6cac4..931277dfe706 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -1893,18 +1893,12 @@ void i915_vma_revoke_mmap(struct i915_vma *vma)
list_del(>obj->userfault_link);
}
-static int
-__i915_request_await_bind(struct i915_request *rq, struct i915_vma *vma)
-{
- return __i915_request_await_exclusive(rq, >active);
-}
-
static int __i915_vma_move_to_active(struct i915_vma *vma, struct i915_request
*rq)
{
int err;
/* Wait for the vma to be bound before we start! */
- err = __i915_request_await_bind(rq, vma);
+ err = i915_request_await_bind(rq, vma);
if (err)
return err;
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 9a411a79badd..1ecc71cf2698 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -55,6 +55,22 @@ void i915_vma_unpin_and_release(struct i915_vma **p_vma,
unsigned int flags);
#define __EXEC_OBJECT_NO_RESERVE BIT(31)
#define __EXEC_OBJECT_NO_REQUEST_AWAIT BIT(30)
+/**
+ * i915_request_await_bind() - Setup request to wait for a vma bind completion
+ * @rq: the request which should wait
+ * @vma: vma whose binding @rq should wait to complete
+ *
+ * Setup the request @rq to asynchronously wait for @vma bind to complete
+ * before starting execution.
+ *
+ * Returns 0 on success, error code on failure.
+ */
+static inline int
+i915_request_await_bind(struct i915_request *rq, struct i915_vma *vma)
+{
+ return __i915_request_await_exclusive(rq, >active);
+}
+
int __must_check _i915_vma_move_to_active(struct i915_vma *vma,
struct i915_request *rq,
struct dma_fence *fence,
--
2.21.0.rc0.32.g243a4c7e27
[Intel-gfx] [PATCH v8 00/22] drm/i915/vm_bind: Add VM_BIND functionality
DRM_I915_GEM_VM_BIND/UNBIND ioctls allows UMD to bind/unbind GEM buffer objects (BOs) or sections of a BOs at specified GPU virtual addresses on a specified address space (VM). Multiple mappings can map to the same physical pages of an object (aliasing). These mappings (also referred to as persistent mappings) will be persistent across multiple GPU submissions (execbuf calls) issued by the UMD, without user having to provide a list of all required mappings during each submission (as required by older execbuf mode). This patch series support VM_BIND version 1, as described by the param I915_PARAM_VM_BIND_VERSION. Add new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only works in vm_bind mode. The vm_bind mode only works with this new execbuf3 ioctl. The new execbuf3 ioctl will not have any execlist support and all the legacy support like relocations etc., are removed. NOTEs: * It is based on below VM_BIND design+uapi rfc. Documentation/gpu/rfc/i915_vm_bind.rst * The IGT RFC series is posted as, [PATCH i-g-t v8 0/14] vm_bind: Add VM_BIND validation support v2: Address various review comments v3: Address review comments and other fixes v4: Remove vm_unbind out fence uapi which is not supported yet, replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode() v5: Render kernel-doc, use PIN_NOEVICT, limit vm_bind support to non-recoverable faults v6: Rebased, minor fixes, add reserved fields to drm_i915_gem_vm_bind, add new patch for async vm_unbind support v7: Rebased, minor cleanups as per review feedback v8: Rebased, add capture support Test-with: 20221129072355.769-1-niranjana.vishwanathap...@intel.com Signed-off-by: Niranjana Vishwanathapura Niranjana Vishwanathapura (22): drm/i915/vm_bind: Expose vm lookup function drm/i915/vm_bind: Add __i915_sw_fence_await_reservation() drm/i915/vm_bind: Expose i915_gem_object_max_page_size() drm/i915/vm_bind: Add support to create persistent vma drm/i915/vm_bind: Implement bind and unbind of object drm/i915/vm_bind: Support for VM private BOs drm/i915/vm_bind: Add support to handle object evictions drm/i915/vm_bind: Support persistent vma activeness tracking drm/i915/vm_bind: Add out fence support drm/i915/vm_bind: Abstract out common execbuf functions drm/i915/vm_bind: Use common execbuf functions in execbuf path drm/i915/vm_bind: Implement I915_GEM_EXECBUFFER3 ioctl drm/i915/vm_bind: Update i915_vma_verify_bind_complete() drm/i915/vm_bind: Expose i915_request_await_bind() drm/i915/vm_bind: Handle persistent vmas in execbuf3 drm/i915/vm_bind: userptr dma-resv changes drm/i915/vm_bind: Limit vm_bind mode to non-recoverable contexts drm/i915/vm_bind: Add uapi for user to enable vm_bind_mode drm/i915/vm_bind: Render VM_BIND documentation drm/i915/vm_bind: Async vm_unbind support drm/i915/vm_bind: Properly build persistent map sg table drm/i915/vm_bind: Support capture of persistent mappings Documentation/gpu/i915.rst| 78 +- drivers/gpu/drm/i915/Makefile | 3 + drivers/gpu/drm/i915/gem/i915_gem_context.c | 43 +- drivers/gpu/drm/i915/gem/i915_gem_context.h | 17 + drivers/gpu/drm/i915/gem/i915_gem_create.c| 72 +- drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c| 6 + .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 522 +-- .../gpu/drm/i915/gem/i915_gem_execbuffer3.c | 872 ++ .../drm/i915/gem/i915_gem_execbuffer_common.c | 671 ++ .../drm/i915/gem/i915_gem_execbuffer_common.h | 76 ++ drivers/gpu/drm/i915/gem/i915_gem_ioctls.h| 2 + drivers/gpu/drm/i915/gem/i915_gem_object.c| 3 + drivers/gpu/drm/i915/gem/i915_gem_object.h| 2 + .../gpu/drm/i915/gem/i915_gem_object_types.h | 6 + drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 19 + drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h | 30 + .../drm/i915/gem/i915_gem_vm_bind_object.c| 461 + drivers/gpu/drm/i915/gt/intel_gtt.c | 20 + drivers/gpu/drm/i915/gt/intel_gtt.h | 26 + drivers/gpu/drm/i915/i915_driver.c| 4 + drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_gem_gtt.c | 39 + drivers/gpu/drm/i915/i915_gem_gtt.h | 3 + drivers/gpu/drm/i915/i915_getparam.c | 3 + drivers/gpu/drm/i915/i915_gpu_error.c | 19 + drivers/gpu/drm/i915/i915_sw_fence.c | 28 +- drivers/gpu/drm/i915/i915_sw_fence.h | 23 +- drivers/gpu/drm/i915/i915_vma.c | 305 +- drivers/gpu/drm/i915/i915_vma.h | 70 +- drivers/gpu/drm/i915/i915_vma_types.h | 41 + include/uapi/drm/i915_drm.h | 277 +- 31 files changed, 3192 insertions(+), 551 deletions(-) create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.h
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/perf: Do not parse context image for HSW (rev4)
== Series Details == Series: drm/i915/perf: Do not parse context image for HSW (rev4) URL : https://patchwork.freedesktop.org/series/111231/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12440_full -> Patchwork_111231v4_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_111231v4_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_111231v4_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_111231v4_full: ### IGT changes ### Possible regressions * igt@gem_mmap_offset@open-flood: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl9/igt@gem_mmap_off...@open-flood.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/shard-skl7/igt@gem_mmap_off...@open-flood.html Known issues Here are the changes found in Patchwork_111231v4_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-skl: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [FAIL][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46]) ([i915#5032]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl10/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl9/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl7/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl7/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl7/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl7/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl6/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl6/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl4/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl4/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl4/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl4/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl3/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl3/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl1/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl1/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl1/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl1/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl10/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl10/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl9/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl9/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-skl9/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/shard-skl9/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/shard-skl9/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/shard-skl9/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/shard-skl7/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/shard-skl7/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/shard-skl7/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/shard-skl6/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/shard-skl6/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/shard-skl6/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/shard-skl4/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/shard-skl4/boot.html [37]:
Re: [Intel-gfx] [PATCH] drm/i915/mtl: Add support for 32 bit OAG formats in MTL
On Mon, Nov 28, 2022 at 05:21:46PM -0800, Umesh Nerlige Ramappa wrote:
As part of OA support for MTL,
- Enable 32 bit OAG formats for MTL.
- 0x200c is repurposed on MTL. Use a separate mux table to verify oa
configs passed by user.
- Similar to ACM, OA/CS timestamp is mismatched on MTL. Add MTL to the
WA.
- On MTL, gt->scratch was using stolen lmem. An MI_SRM to stolen lmem is
hanging. Add a page in noa_wait BO to save/restore GPR registers for
the noa_wait logic.
why are all these changes squashed in a single patch?
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 6 ---
drivers/gpu/drm/i915/i915_perf.c | 49 ++--
2 files changed, 38 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index c1d9cd255e06..13dffe0a3d20 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -296,12 +296,6 @@ enum intel_gt_scratch_field {
/* 8 bytes */
INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
-
- /* 6 * 8 bytes */
- INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR = 2048,
-
- /* 4 bytes */
- INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 = 2096,
};
#endif /* __INTEL_GT_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 00e09bb18b13..a735b9540113 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1842,8 +1842,7 @@ static u32 *save_restore_register(struct i915_perf_stream
*stream, u32 *cs,
for (d = 0; d < dword_count; d++) {
*cs++ = cmd;
*cs++ = i915_mmio_reg_offset(reg) + 4 * d;
- *cs++ = intel_gt_scratch_offset(stream->engine->gt,
- offset) + 4 * d;
+ *cs++ = i915_ggtt_offset(stream->noa_wait) + offset + 4 * d;
*cs++ = 0;
}
@@ -1876,7 +1875,13 @@ static int alloc_noa_wait(struct i915_perf_stream
*stream)
MI_PREDICATE_RESULT_2_ENGINE(base) :
MI_PREDICATE_RESULT_1(RENDER_RING_BASE);
- bo = i915_gem_object_create_internal(i915, 4096);
+ /*
+* gt->scratch was being used to save/restore the GPR registers, but on
+* MTL the scratch uses stolen lmem. An MI_SRM to this memory region
+* causes an engine hang. Instead allocate an additional page here to
humn.. is it because of the pte being wrong? "stolen lmem" in mtl is
still system memory... do we know why we'd need this change?
Lucas De Marchi
+* save/restore GPR registers
+*/
+ bo = i915_gem_object_create_internal(i915, 8192);
if (IS_ERR(bo)) {
drm_err(>drm,
"Failed to allocate NOA wait batchbuffer\n");
@@ -1910,14 +1915,19 @@ static int alloc_noa_wait(struct i915_perf_stream
*stream)
goto err_unpin;
}
+ stream->noa_wait = vma;
+
+#define GPR_SAVE_OFFSET 4096
+#define PREDICATE_SAVE_OFFSET 4160
+
/* Save registers. */
for (i = 0; i < N_CS_GPR; i++)
cs = save_restore_register(
stream, cs, true /* save */, CS_GPR(i),
- INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
+ GPR_SAVE_OFFSET + 8 * i, 2);
cs = save_restore_register(
stream, cs, true /* save */, mi_predicate_result,
- INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
+ PREDICATE_SAVE_OFFSET, 1);
/* First timestamp snapshot location. */
ts0 = cs;
@@ -2033,10 +2043,10 @@ static int alloc_noa_wait(struct i915_perf_stream
*stream)
for (i = 0; i < N_CS_GPR; i++)
cs = save_restore_register(
stream, cs, false /* restore */, CS_GPR(i),
- INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
+ GPR_SAVE_OFFSET + 8 * i, 2);
cs = save_restore_register(
stream, cs, false /* restore */, mi_predicate_result,
- INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
+ PREDICATE_SAVE_OFFSET, 1);
/* And return to the ring. */
*cs++ = MI_BATCH_BUFFER_END;
@@ -2046,7 +2056,6 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
i915_gem_object_flush_map(bo);
__i915_gem_object_release_map(bo);
- stream->noa_wait = vma;
goto out_ww;
err_unpin:
@@ -3127,8 +3136,11 @@ get_sseu_config(struct intel_sseu *out_sseu,
*/
u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)
{
- /* Wa_18013179988:dg2 */
- if (IS_DG2(i915)) {
+ /*
+* Wa_18013179988:dg2
+* Wa_14015846243:mtl
+*/
+ if (IS_DG2(i915) || IS_METEORLAKE(i915)) {
intel_wakeref_t
Re: [Intel-gfx] [PATCH 2/3] drm/i915/mtl: Define new PTE encode for MTL
On Tue, Nov 29, 2022 at 09:58:03AM +0530, Iddamsetty, Aravind wrote:
On 29-11-2022 01:57, Lucas De Marchi wrote:
On Mon, Nov 28, 2022 at 03:43:51PM +0530, Aravind Iddamsetty wrote:
Add a separate PTE encode function for MTL. The number of PAT registers
have increased to 16 on MTL. All 16 PAT registers are available for
PPGTT mapped pages, but only the lower 4 are available for GGTT mapped
pages.
this would be easier to review with a preparatory patch, replacing
direct calls to gen8_pte_encode() and gen8_ggtt_pte_encode() with the
indirect ones through vm.
Well I did this together because it would be easy to justify the change
as I'm adding new definitions but if you insist on separating it out I
can do that too.
as long as they are in the same patch series, it should be fine: the
justification is already there and the commit message can simply say new
platforms will use a different encode function.
Lucas De Marchi
Thanks,
Aravind.
Then the patch on top adding MTL would be the definition of the new
encoding (mtl_pte_encode/mtl_ggtt_pte_encode) and assigning the function
pointer.
Lucas De Marchi
BSPEC: 63884
Cc: Lucas De Marchi
Cc: Matt Roper
Co-developed-by: Fei Yang
Signed-off-by: Fei Yang
Signed-off-by: Aravind Iddamsetty
---
drivers/gpu/drm/i915/display/intel_dpt.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 43
drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 4 +++
drivers/gpu/drm/i915/gt/intel_ggtt.c | 36 ++--
drivers/gpu/drm/i915/gt/intel_gtt.h | 13 +--
5 files changed, 86 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
b/drivers/gpu/drm/i915/display/intel_dpt.c
index ad1a37b515fb..cb8ed9bfb240 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -298,7 +298,7 @@ intel_dpt_create(struct intel_framebuffer *fb)
vm->vma_ops.bind_vma = dpt_bind_vma;
vm->vma_ops.unbind_vma = dpt_unbind_vma;
- vm->pte_encode = gen8_ggtt_pte_encode;
+ vm->pte_encode = vm->gt->ggtt->vm.pte_encode;
dpt->obj = dpt_obj;
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 4daaa6f55668..4197b43150cc 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -55,6 +55,34 @@ static u64 gen8_pte_encode(dma_addr_t addr,
return pte;
}
+static u64 mtl_pte_encode(dma_addr_t addr,
+ enum i915_cache_level level,
+ u32 flags)
+{
+ gen8_pte_t pte = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
+
+ if (unlikely(flags & PTE_READ_ONLY))
+ pte &= ~GEN8_PAGE_RW;
+
+ if (flags & PTE_LM)
+ pte |= GEN12_PPGTT_PTE_LM | GEN12_PPGTT_PTE_NC;
+
+ switch (level) {
+ case I915_CACHE_NONE:
+ pte |= GEN12_PPGTT_PTE_PAT1;
+ break;
+ case I915_CACHE_LLC:
+ case I915_CACHE_L3_LLC:
+ pte |= GEN12_PPGTT_PTE_PAT0 | GEN12_PPGTT_PTE_PAT1;
+ break;
+ case I915_CACHE_WT:
+ pte |= GEN12_PPGTT_PTE_PAT0;
+ break;
+ }
+
+ return pte;
+}
+
static void gen8_ppgtt_notify_vgt(struct i915_ppgtt *ppgtt, bool create)
{
struct drm_i915_private *i915 = ppgtt->vm.i915;
@@ -427,7 +455,7 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
u32 flags)
{
struct i915_page_directory *pd;
- const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level,
flags);
+ const gen8_pte_t pte_encode = ppgtt->vm.pte_encode(0,
cache_level, flags);
gen8_pte_t *vaddr;
pd = i915_pd_entry(pdp, gen8_pd_index(idx, 2));
@@ -580,7 +608,7 @@ static void gen8_ppgtt_insert_huge(struct
i915_address_space *vm,
enum i915_cache_level cache_level,
u32 flags)
{
- const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level,
flags);
+ const gen8_pte_t pte_encode = vm->pte_encode(0, cache_level, flags);
unsigned int rem = sg_dma_len(iter->sg);
u64 start = vma_res->start;
@@ -743,7 +771,7 @@ static void gen8_ppgtt_insert_entry(struct
i915_address_space *vm,
GEM_BUG_ON(pt->is_compact);
vaddr = px_vaddr(pt);
- vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
+ vaddr[gen8_pd_index(idx, 0)] = vm->pte_encode(addr, level, flags);
drm_clflush_virt_range([gen8_pd_index(idx, 0)],
sizeof(*vaddr));
}
@@ -773,7 +801,7 @@ static void __xehpsdv_ppgtt_insert_entry_lm(struct
i915_address_space *vm,
}
vaddr = px_vaddr(pt);
- vaddr[gen8_pd_index(idx, 0) / 16] = gen8_pte_encode(addr, level,
flags);
+ vaddr[gen8_pd_index(idx, 0) / 16] = vm->pte_encode(addr, level,
flags);
}
static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm,
@@ -820,7 +848,7 @@ static int gen8_init_scratch(struct
i915_address_space *vm)
pte_flags |= PTE_LM;
vm->scratch[0]->encode =
- gen8_pte_encode(px_dma(vm->scratch[0]),
+ vm->pte_encode(px_dma(vm->scratch[0]),
I915_CACHE_NONE,
Re: [Intel-gfx] [PATCH v4] drm/i915/mtl: Media GT and Render GT share common GGTT
On Tue, Nov 29, 2022 at 11:33:15AM +0530, Iddamsetty, Aravind wrote:
On 29-11-2022 11:24, Lucas De Marchi wrote:
On Wed, Nov 23, 2022 at 09:47:03AM +0530, Iddamsetty, Aravind wrote:
On 23-11-2022 05:29, Matt Roper wrote:
On Tue, Nov 22, 2022 at 12:31:26PM +0530, Aravind Iddamsetty wrote:
On XE_LPM+ platforms the media engines are carved out into a separate
GT but have a common GGTMMADR address range which essentially makes
the GGTT address space to be shared between media and render GT. As a
result any updates in GGTT shall invalidate TLB of GTs sharing it and
similarly any operation on GGTT requiring an action on a GT will
have to
involve all GTs sharing it. setup_private_pat was being done on a per
GGTT based as that doesn't touch any GGTT structures moved it to per GT
based.
BSPEC: 63834
v2:
1. Add details to commit msg
2. includes fix for failure to add item to ggtt->gt_list, as suggested
by Lucas
3. as ggtt_flush() is used only for ggtt drop i915_is_ggtt check within
it.
4. setup_private_pat moved out of intel_gt_tiles_init
v3:
1. Move out for_each_gt from i915_driver.c (Jani Nikula)
v4: drop using RCU primitives on ggtt->gt_list as it is not an RCU list
(Matt Roper)
Cc: Matt Roper
Signed-off-by: Aravind Iddamsetty
Reviewed-by: Matt Roper
Thanks Matt, could you also help with merging the change.
Regards,
Aravind.
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 54 +--
drivers/gpu/drm/i915/gt/intel_gt.c | 13 +-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
drivers/gpu/drm/i915/gt/intel_gtt.h | 4 ++
drivers/gpu/drm/i915/i915_driver.c | 12 ++---
drivers/gpu/drm/i915/i915_gem.c | 2 +
drivers/gpu/drm/i915/i915_gem_evict.c | 51 +++--
drivers/gpu/drm/i915/i915_vma.c | 5 ++-
drivers/gpu/drm/i915/selftests/i915_gem.c | 2 +
9 files changed, 111 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 8145851ad23d..7644738b9cdb 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -8,6 +8,7 @@
#include
#include
+#include
#include
#include
@@ -196,10 +197,13 @@ void i915_ggtt_suspend_vm(struct
i915_address_space *vm)
void i915_ggtt_suspend(struct i915_ggtt *ggtt)
{
+ struct intel_gt *gt;
+
i915_ggtt_suspend_vm(>vm);
ggtt->invalidate(ggtt);
- intel_gt_check_and_clear_faults(ggtt->vm.gt);
+ list_for_each_entry(gt, >gt_list, ggtt_link)
+ intel_gt_check_and_clear_faults(gt);
}
void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
@@ -225,16 +229,21 @@ static void gen8_ggtt_invalidate(struct
i915_ggtt *ggtt)
static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
{
- struct intel_uncore *uncore = ggtt->vm.gt->uncore;
struct drm_i915_private *i915 = ggtt->vm.i915;
gen8_ggtt_invalidate(ggtt);
- if (GRAPHICS_VER(i915) >= 12)
- intel_uncore_write_fw(uncore, GEN12_GUC_TLB_INV_CR,
- GEN12_GUC_TLB_INV_CR_INVALIDATE);
- else
- intel_uncore_write_fw(uncore, GEN8_GTCR,
GEN8_GTCR_INVALIDATE);
+ if (GRAPHICS_VER(i915) >= 12) {
+ struct intel_gt *gt;
+
+ list_for_each_entry(gt, >gt_list, ggtt_link)
+ intel_uncore_write_fw(gt->uncore,
+ GEN12_GUC_TLB_INV_CR,
+ GEN12_GUC_TLB_INV_CR_INVALIDATE);
+ } else {
+ intel_uncore_write_fw(ggtt->vm.gt->uncore,
+ GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+ }
}
u64 gen8_ggtt_pte_encode(dma_addr_t addr,
@@ -986,8 +995,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.pte_encode = gen8_ggtt_pte_encode;
- setup_private_pat(ggtt->vm.gt);
-
return ggtt_probe_common(ggtt, size);
}
@@ -1196,7 +1203,14 @@ static int ggtt_probe_hw(struct i915_ggtt
*ggtt, struct intel_gt *gt)
*/
int i915_ggtt_probe_hw(struct drm_i915_private *i915)
{
- int ret;
+ struct intel_gt *gt;
+ int ret, i;
+
+ for_each_gt(gt, i915, i) {
+ ret = intel_gt_assign_ggtt(gt);
in v3 the intel_gt_assign_ggtt() call is not in i915_driver.c anymore but
rather moved here. We could make i915_ggtt_create() static, doing the
allocation here and intel_gt_assign_ggtt() would be in charge of just
assigning the ggtt. Not very important though and can be done later.
well we call intel_gt_assign_ggtt in i915_gem_gtt_mock_selftests but not
i915_ggtt_probe_hw.
makes sense, let's leave it as is.
Lucas De Marchi
[Intel-gfx] ✗ Fi.CI.IGT: failure for i915: dedicated MCR locking and hardware semaphore (rev2)
== Series Details == Series: i915: dedicated MCR locking and hardware semaphore (rev2) URL : https://patchwork.freedesktop.org/series/111220/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12440_full -> Patchwork_111220v2_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_111220v2_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_111220v2_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_111220v2_full: ### IGT changes ### Possible regressions * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-tglb3/igt@gem_ctx_isolation@preservation...@bcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/shard-tglb8/igt@gem_ctx_isolation@preservation...@bcs0.html Known issues Here are the changes found in Patchwork_111220v2_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@smoketest: - shard-iclb: [PASS][3] -> [FAIL][4] ([i915#5099]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-iclb3/igt@gem_ctx_persiste...@smoketest.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/shard-iclb5/igt@gem_ctx_persiste...@smoketest.html * igt@gem_exec_balancer@parallel: - shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-iclb2/igt@gem_exec_balan...@parallel.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/shard-iclb8/igt@gem_exec_balan...@parallel.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][7] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_params@secure-non-root: - shard-iclb: NOTRUN -> [SKIP][8] ([fdo#112283]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/shard-iclb8/igt@gem_exec_par...@secure-non-root.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#2190]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/shard-apl7/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-apl: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/shard-apl1/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-skl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/shard-skl10/igt@gem_lmem_swapp...@parallel-random-verify.html * igt@gem_lmem_swapping@verify-random-ccs: - shard-tglb: NOTRUN -> [SKIP][12] ([i915#4613]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/shard-tglb6/igt@gem_lmem_swapp...@verify-random-ccs.html * igt@gem_pxp@create-protected-buffer: - shard-iclb: NOTRUN -> [SKIP][13] ([i915#4270]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/shard-iclb8/igt@gem_...@create-protected-buffer.html * igt@gem_render_copy@x-tiled-to-vebox-y-tiled: - shard-iclb: NOTRUN -> [SKIP][14] ([i915#768]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/shard-iclb8/igt@gem_render_c...@x-tiled-to-vebox-y-tiled.html * igt@gem_userptr_blits@coherency-unsync: - shard-iclb: NOTRUN -> [SKIP][15] ([i915#3297]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/shard-iclb8/igt@gem_userptr_bl...@coherency-unsync.html * igt@gem_userptr_blits@input-checking: - shard-skl: NOTRUN -> [DMESG-WARN][16] ([i915#4991]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/shard-skl9/igt@gem_userptr_bl...@input-checking.html * igt@gen9_exec_parse@bb-start-far: - shard-iclb: NOTRUN -> [SKIP][17] ([i915#2856]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/shard-iclb8/igt@gen9_exec_pa...@bb-start-far.html * igt@i915_pm_dc@dc6-dpms: - shard-skl: NOTRUN -> [FAIL][18] ([i915#3989] / [i915#454]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/shard-skl9/igt@i915_pm...@dc6-dpms.html *
Re: [Intel-gfx] [PATCH v4] drm/i915/mtl: Media GT and Render GT share common GGTT
On 29-11-2022 11:24, Lucas De Marchi wrote:
> On Wed, Nov 23, 2022 at 09:47:03AM +0530, Iddamsetty, Aravind wrote:
>>
>>
>> On 23-11-2022 05:29, Matt Roper wrote:
>>> On Tue, Nov 22, 2022 at 12:31:26PM +0530, Aravind Iddamsetty wrote:
On XE_LPM+ platforms the media engines are carved out into a separate
GT but have a common GGTMMADR address range which essentially makes
the GGTT address space to be shared between media and render GT. As a
result any updates in GGTT shall invalidate TLB of GTs sharing it and
similarly any operation on GGTT requiring an action on a GT will
have to
involve all GTs sharing it. setup_private_pat was being done on a per
GGTT based as that doesn't touch any GGTT structures moved it to per GT
based.
BSPEC: 63834
v2:
1. Add details to commit msg
2. includes fix for failure to add item to ggtt->gt_list, as suggested
by Lucas
3. as ggtt_flush() is used only for ggtt drop i915_is_ggtt check within
it.
4. setup_private_pat moved out of intel_gt_tiles_init
v3:
1. Move out for_each_gt from i915_driver.c (Jani Nikula)
v4: drop using RCU primitives on ggtt->gt_list as it is not an RCU list
(Matt Roper)
Cc: Matt Roper
Signed-off-by: Aravind Iddamsetty
>>>
>>> Reviewed-by: Matt Roper
>>
>> Thanks Matt, could you also help with merging the change.
>>
>> Regards,
>> Aravind.
>>>
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 54 +--
drivers/gpu/drm/i915/gt/intel_gt.c | 13 +-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
drivers/gpu/drm/i915/gt/intel_gtt.h | 4 ++
drivers/gpu/drm/i915/i915_driver.c | 12 ++---
drivers/gpu/drm/i915/i915_gem.c | 2 +
drivers/gpu/drm/i915/i915_gem_evict.c | 51 +++--
drivers/gpu/drm/i915/i915_vma.c | 5 ++-
drivers/gpu/drm/i915/selftests/i915_gem.c | 2 +
9 files changed, 111 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 8145851ad23d..7644738b9cdb 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -8,6 +8,7 @@
#include
#include
+#include
#include
#include
@@ -196,10 +197,13 @@ void i915_ggtt_suspend_vm(struct
i915_address_space *vm)
void i915_ggtt_suspend(struct i915_ggtt *ggtt)
{
+ struct intel_gt *gt;
+
i915_ggtt_suspend_vm(>vm);
ggtt->invalidate(ggtt);
- intel_gt_check_and_clear_faults(ggtt->vm.gt);
+ list_for_each_entry(gt, >gt_list, ggtt_link)
+ intel_gt_check_and_clear_faults(gt);
}
void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
@@ -225,16 +229,21 @@ static void gen8_ggtt_invalidate(struct
i915_ggtt *ggtt)
static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
{
- struct intel_uncore *uncore = ggtt->vm.gt->uncore;
struct drm_i915_private *i915 = ggtt->vm.i915;
gen8_ggtt_invalidate(ggtt);
- if (GRAPHICS_VER(i915) >= 12)
- intel_uncore_write_fw(uncore, GEN12_GUC_TLB_INV_CR,
- GEN12_GUC_TLB_INV_CR_INVALIDATE);
- else
- intel_uncore_write_fw(uncore, GEN8_GTCR,
GEN8_GTCR_INVALIDATE);
+ if (GRAPHICS_VER(i915) >= 12) {
+ struct intel_gt *gt;
+
+ list_for_each_entry(gt, >gt_list, ggtt_link)
+ intel_uncore_write_fw(gt->uncore,
+ GEN12_GUC_TLB_INV_CR,
+ GEN12_GUC_TLB_INV_CR_INVALIDATE);
+ } else {
+ intel_uncore_write_fw(ggtt->vm.gt->uncore,
+ GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+ }
}
u64 gen8_ggtt_pte_encode(dma_addr_t addr,
@@ -986,8 +995,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.pte_encode = gen8_ggtt_pte_encode;
- setup_private_pat(ggtt->vm.gt);
-
return ggtt_probe_common(ggtt, size);
}
@@ -1196,7 +1203,14 @@ static int ggtt_probe_hw(struct i915_ggtt
*ggtt, struct intel_gt *gt)
*/
int i915_ggtt_probe_hw(struct drm_i915_private *i915)
{
- int ret;
+ struct intel_gt *gt;
+ int ret, i;
+
+ for_each_gt(gt, i915, i) {
+ ret = intel_gt_assign_ggtt(gt);
>
> in v3 the intel_gt_assign_ggtt() call is not in i915_driver.c anymore but
> rather moved here. We could make i915_ggtt_create() static, doing the
> allocation here and intel_gt_assign_ggtt() would be in charge of just
> assigning the ggtt. Not very important though and can be done later.
well we call intel_gt_assign_ggtt in
Re: [Intel-gfx] [PATCH v4] drm/i915/mtl: Media GT and Render GT share common GGTT
On Wed, Nov 23, 2022 at 09:47:03AM +0530, Iddamsetty, Aravind wrote:
On 23-11-2022 05:29, Matt Roper wrote:
On Tue, Nov 22, 2022 at 12:31:26PM +0530, Aravind Iddamsetty wrote:
On XE_LPM+ platforms the media engines are carved out into a separate
GT but have a common GGTMMADR address range which essentially makes
the GGTT address space to be shared between media and render GT. As a
result any updates in GGTT shall invalidate TLB of GTs sharing it and
similarly any operation on GGTT requiring an action on a GT will have to
involve all GTs sharing it. setup_private_pat was being done on a per
GGTT based as that doesn't touch any GGTT structures moved it to per GT
based.
BSPEC: 63834
v2:
1. Add details to commit msg
2. includes fix for failure to add item to ggtt->gt_list, as suggested
by Lucas
3. as ggtt_flush() is used only for ggtt drop i915_is_ggtt check within
it.
4. setup_private_pat moved out of intel_gt_tiles_init
v3:
1. Move out for_each_gt from i915_driver.c (Jani Nikula)
v4: drop using RCU primitives on ggtt->gt_list as it is not an RCU list
(Matt Roper)
Cc: Matt Roper
Signed-off-by: Aravind Iddamsetty
Reviewed-by: Matt Roper
Thanks Matt, could you also help with merging the change.
Regards,
Aravind.
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 54 +--
drivers/gpu/drm/i915/gt/intel_gt.c| 13 +-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
drivers/gpu/drm/i915/gt/intel_gtt.h | 4 ++
drivers/gpu/drm/i915/i915_driver.c| 12 ++---
drivers/gpu/drm/i915/i915_gem.c | 2 +
drivers/gpu/drm/i915/i915_gem_evict.c | 51 +++--
drivers/gpu/drm/i915/i915_vma.c | 5 ++-
drivers/gpu/drm/i915/selftests/i915_gem.c | 2 +
9 files changed, 111 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 8145851ad23d..7644738b9cdb 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -8,6 +8,7 @@
#include
#include
+#include
#include
#include
@@ -196,10 +197,13 @@ void i915_ggtt_suspend_vm(struct i915_address_space *vm)
void i915_ggtt_suspend(struct i915_ggtt *ggtt)
{
+ struct intel_gt *gt;
+
i915_ggtt_suspend_vm(>vm);
ggtt->invalidate(ggtt);
- intel_gt_check_and_clear_faults(ggtt->vm.gt);
+ list_for_each_entry(gt, >gt_list, ggtt_link)
+ intel_gt_check_and_clear_faults(gt);
}
void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
@@ -225,16 +229,21 @@ static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
{
- struct intel_uncore *uncore = ggtt->vm.gt->uncore;
struct drm_i915_private *i915 = ggtt->vm.i915;
gen8_ggtt_invalidate(ggtt);
- if (GRAPHICS_VER(i915) >= 12)
- intel_uncore_write_fw(uncore, GEN12_GUC_TLB_INV_CR,
- GEN12_GUC_TLB_INV_CR_INVALIDATE);
- else
- intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+ if (GRAPHICS_VER(i915) >= 12) {
+ struct intel_gt *gt;
+
+ list_for_each_entry(gt, >gt_list, ggtt_link)
+ intel_uncore_write_fw(gt->uncore,
+ GEN12_GUC_TLB_INV_CR,
+ GEN12_GUC_TLB_INV_CR_INVALIDATE);
+ } else {
+ intel_uncore_write_fw(ggtt->vm.gt->uncore,
+ GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+ }
}
u64 gen8_ggtt_pte_encode(dma_addr_t addr,
@@ -986,8 +995,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.pte_encode = gen8_ggtt_pte_encode;
- setup_private_pat(ggtt->vm.gt);
-
return ggtt_probe_common(ggtt, size);
}
@@ -1196,7 +1203,14 @@ static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct
intel_gt *gt)
*/
int i915_ggtt_probe_hw(struct drm_i915_private *i915)
{
- int ret;
+ struct intel_gt *gt;
+ int ret, i;
+
+ for_each_gt(gt, i915, i) {
+ ret = intel_gt_assign_ggtt(gt);
in v3 the intel_gt_assign_ggtt() call is not in i915_driver.c anymore but
rather moved here. We could make i915_ggtt_create() static, doing the
allocation here and intel_gt_assign_ggtt() would be in charge of just
assigning the ggtt. Not very important though and can be done later.
pushed, thanks
Lucas De Marchi
+ if (ret)
+ return ret;
+ }
ret = ggtt_probe_hw(to_gt(i915)->ggtt, to_gt(i915));
if (ret)
@@ -1208,6 +1222,19 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
return 0;
}
+struct i915_ggtt *i915_ggtt_create(struct drm_i915_private *i915)
+{
+ struct i915_ggtt *ggtt;
+
+ ggtt = drmm_kzalloc(>drm, sizeof(*ggtt), GFP_KERNEL);
+ if (!ggtt)
+ return ERR_PTR(-ENOMEM);
+
+
Re: [Intel-gfx] [PATCH 3/3] drm/i915/mtl/UAPI: Disable SET_CACHING IOCTL for MTL+
On 29-11-2022 01:49, Lucas De Marchi wrote:
> On Mon, Nov 28, 2022 at 03:43:52PM +0530, Aravind Iddamsetty wrote:
>> From: Pallavi Mishra
>>
>> Caching mode for an object shall be selected via upcoming VM_BIND
>> interface.
>
> last I've heard there was no plan to support this through VM_BIND. Did
> anything change? Otherwise this needs a better explanation recorded in
> the cover letter.
@Niranjana, We do plan to support this via VM_BIND in future is it not?
Thanks,
Aravind.
>
> According to e7737b67ab46 ("drm/i915/uapi: reject caching ioctls for
> discrete")
> it seems it was already planned to extend this to all platforms.
>
> +Daniel, +Matt Auld
>
>>
>> Cc: Lucas De Marchi
>> Cc: Matt Roper
>> Cc: Joonas Lahtinen
>>
>> Signed-off-by: Pallavi Mishra
>> Signed-off-by: Aravind Iddamsetty
>> ---
>> drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
>> b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
>> index d44a152ce680..aebbfe186143 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
>> @@ -332,6 +332,9 @@ int i915_gem_set_caching_ioctl(struct drm_device
>> *dev, void *data,
>> if (IS_DGFX(i915))
>> return -ENODEV;
>>
>> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
>> + return -EOPNOTSUPP;
>
> Why a different return? Should this be treated similar to the IS_DGFX()
> case above? It seems we are also missing an equivalent change in
> i915_gem_get_caching_ioctl().
>
> include/uapi/drm/i915_drm.h also needs to be updated with documentation
> about this behavior. See the commit mentioned above.
>
> Lucas De Marchi
>
>
>
>> +
>> switch (args->caching) {
>> case I915_CACHING_NONE:
>> level = I915_CACHE_NONE;
>> --
>> 2.25.1
>>
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/huc: always init the delayed load fence (rev2)
== Series Details ==
Series: drm/i915/huc: always init the delayed load fence (rev2)
URL : https://patchwork.freedesktop.org/series/111288/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12440_full -> Patchwork_111288v2_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (10 -> 10)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_111288v2_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_flip@plain-flip-fb-recreate@d-hdmi-a4:
- {shard-dg1}:[PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-dg1-18/igt@kms_flip@plain-flip-fb-recre...@d-hdmi-a4.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v2/shard-dg1-15/igt@kms_flip@plain-flip-fb-recre...@d-hdmi-a4.html
New tests
-
New tests have been introduced between CI_DRM_12440_full and
Patchwork_111288v2_full:
### New IGT tests (1) ###
* igt@kms_atomic_transition:
- Statuses :
- Exec time: [None] s
Known issues
Here are the changes found in Patchwork_111288v2_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_balancer@parallel:
- shard-iclb: [PASS][3] -> [SKIP][4] ([i915#4525]) +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-iclb2/igt@gem_exec_balan...@parallel.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v2/shard-iclb8/igt@gem_exec_balan...@parallel.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][5] -> [FAIL][6] ([i915#2842])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-apl3/igt@gem_exec_fair@basic-none-s...@rcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v2/shard-apl7/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_params@secure-non-root:
- shard-iclb: NOTRUN -> [SKIP][7] ([fdo#112283]) +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v2/shard-iclb5/igt@gem_exec_par...@secure-non-root.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v2/shard-apl1/igt@gem_huc_c...@huc-copy.html
- shard-tglb: [PASS][9] -> [SKIP][10] ([i915#2190])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-tglb3/igt@gem_huc_c...@huc-copy.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v2/shard-tglb7/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-apl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v2/shard-apl3/igt@gem_lmem_swapp...@heavy-verify-random.html
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-skl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v2/shard-skl7/igt@gem_lmem_swapp...@parallel-random-verify.html
* igt@gem_lmem_swapping@verify-random-ccs:
- shard-tglb: NOTRUN -> [SKIP][13] ([i915#4613])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v2/shard-tglb2/igt@gem_lmem_swapp...@verify-random-ccs.html
* igt@gem_pxp@create-protected-buffer:
- shard-iclb: NOTRUN -> [SKIP][14] ([i915#4270])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v2/shard-iclb5/igt@gem_...@create-protected-buffer.html
* igt@gem_render_copy@x-tiled-to-vebox-y-tiled:
- shard-iclb: NOTRUN -> [SKIP][15] ([i915#768])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v2/shard-iclb5/igt@gem_render_c...@x-tiled-to-vebox-y-tiled.html
* igt@gem_softpin@evict-single-offset:
- shard-tglb: [PASS][16] -> [FAIL][17] ([i915#4171])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/shard-tglb7/igt@gem_soft...@evict-single-offset.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v2/shard-tglb3/igt@gem_soft...@evict-single-offset.html
* igt@gem_userptr_blits@coherency-sync:
- shard-iclb: NOTRUN -> [SKIP][18] ([fdo#109290])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v2/shard-iclb6/igt@gem_userptr_bl...@coherency-sync.html
- shard-tglb: NOTRUN -> [SKIP][19] ([fdo#110542])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v2/shard-tglb2/igt@gem_userptr_bl...@coherency-sync.html
* igt@gem_userptr_blits@coherency-unsync:
- shard-iclb: NOTRUN -> [SKIP][20]
Re: [Intel-gfx] [PATCH 2/3] drm/i915/mtl: Define new PTE encode for MTL
On 29-11-2022 01:57, Lucas De Marchi wrote:
> On Mon, Nov 28, 2022 at 03:43:51PM +0530, Aravind Iddamsetty wrote:
>> Add a separate PTE encode function for MTL. The number of PAT registers
>> have increased to 16 on MTL. All 16 PAT registers are available for
>> PPGTT mapped pages, but only the lower 4 are available for GGTT mapped
>> pages.
>
> this would be easier to review with a preparatory patch, replacing
> direct calls to gen8_pte_encode() and gen8_ggtt_pte_encode() with the
> indirect ones through vm.
Well I did this together because it would be easy to justify the change
as I'm adding new definitions but if you insist on separating it out I
can do that too.
Thanks,
Aravind.
>
> Then the patch on top adding MTL would be the definition of the new
> encoding (mtl_pte_encode/mtl_ggtt_pte_encode) and assigning the function
> pointer.
>
>
> Lucas De Marchi
>
>>
>> BSPEC: 63884
>>
>> Cc: Lucas De Marchi
>> Cc: Matt Roper
>> Co-developed-by: Fei Yang
>> Signed-off-by: Fei Yang
>> Signed-off-by: Aravind Iddamsetty
>> ---
>> drivers/gpu/drm/i915/display/intel_dpt.c | 2 +-
>> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 43
>> drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 4 +++
>> drivers/gpu/drm/i915/gt/intel_ggtt.c | 36 ++--
>> drivers/gpu/drm/i915/gt/intel_gtt.h | 13 +--
>> 5 files changed, 86 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
>> b/drivers/gpu/drm/i915/display/intel_dpt.c
>> index ad1a37b515fb..cb8ed9bfb240 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dpt.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dpt.c
>> @@ -298,7 +298,7 @@ intel_dpt_create(struct intel_framebuffer *fb)
>> vm->vma_ops.bind_vma = dpt_bind_vma;
>> vm->vma_ops.unbind_vma = dpt_unbind_vma;
>>
>> - vm->pte_encode = gen8_ggtt_pte_encode;
>> + vm->pte_encode = vm->gt->ggtt->vm.pte_encode;
>>
>> dpt->obj = dpt_obj;
>>
>> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> index 4daaa6f55668..4197b43150cc 100644
>> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> @@ -55,6 +55,34 @@ static u64 gen8_pte_encode(dma_addr_t addr,
>> return pte;
>> }
>>
>> +static u64 mtl_pte_encode(dma_addr_t addr,
>> + enum i915_cache_level level,
>> + u32 flags)
>> +{
>> + gen8_pte_t pte = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
>> +
>> + if (unlikely(flags & PTE_READ_ONLY))
>> + pte &= ~GEN8_PAGE_RW;
>> +
>> + if (flags & PTE_LM)
>> + pte |= GEN12_PPGTT_PTE_LM | GEN12_PPGTT_PTE_NC;
>> +
>> + switch (level) {
>> + case I915_CACHE_NONE:
>> + pte |= GEN12_PPGTT_PTE_PAT1;
>> + break;
>> + case I915_CACHE_LLC:
>> + case I915_CACHE_L3_LLC:
>> + pte |= GEN12_PPGTT_PTE_PAT0 | GEN12_PPGTT_PTE_PAT1;
>> + break;
>> + case I915_CACHE_WT:
>> + pte |= GEN12_PPGTT_PTE_PAT0;
>> + break;
>> + }
>> +
>> + return pte;
>> +}
>> +
>> static void gen8_ppgtt_notify_vgt(struct i915_ppgtt *ppgtt, bool create)
>> {
>> struct drm_i915_private *i915 = ppgtt->vm.i915;
>> @@ -427,7 +455,7 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
>> u32 flags)
>> {
>> struct i915_page_directory *pd;
>> - const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level,
>> flags);
>> + const gen8_pte_t pte_encode = ppgtt->vm.pte_encode(0,
>> cache_level, flags);
>> gen8_pte_t *vaddr;
>>
>> pd = i915_pd_entry(pdp, gen8_pd_index(idx, 2));
>> @@ -580,7 +608,7 @@ static void gen8_ppgtt_insert_huge(struct
>> i915_address_space *vm,
>> enum i915_cache_level cache_level,
>> u32 flags)
>> {
>> - const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level,
>> flags);
>> + const gen8_pte_t pte_encode = vm->pte_encode(0, cache_level, flags);
>> unsigned int rem = sg_dma_len(iter->sg);
>> u64 start = vma_res->start;
>>
>> @@ -743,7 +771,7 @@ static void gen8_ppgtt_insert_entry(struct
>> i915_address_space *vm,
>> GEM_BUG_ON(pt->is_compact);
>>
>> vaddr = px_vaddr(pt);
>> - vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
>> + vaddr[gen8_pd_index(idx, 0)] = vm->pte_encode(addr, level, flags);
>> drm_clflush_virt_range([gen8_pd_index(idx, 0)],
>> sizeof(*vaddr));
>> }
>>
>> @@ -773,7 +801,7 @@ static void __xehpsdv_ppgtt_insert_entry_lm(struct
>> i915_address_space *vm,
>> }
>>
>> vaddr = px_vaddr(pt);
>> - vaddr[gen8_pd_index(idx, 0) / 16] = gen8_pte_encode(addr, level,
>> flags);
>> + vaddr[gen8_pd_index(idx, 0) / 16] = vm->pte_encode(addr, level,
>> flags);
>> }
>>
>> static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm,
>> @@ -820,7 +848,7 @@ static int gen8_init_scratch(struct
>> i915_address_space *vm)
>> pte_flags |= PTE_LM;
>>
>> vm->scratch[0]->encode =
>> -
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/mtl: Add support for 32 bit OAG formats in MTL
== Series Details ==
Series: drm/i915/mtl: Add support for 32 bit OAG formats in MTL
URL : https://patchwork.freedesktop.org/series/111411/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12440 -> Patchwork_111411v1
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_111411v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_111411v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111411v1/index.html
Participating hosts (34 -> 31)
--
Missing(3): bat-kbl-2 bat-adlp-4 bat-jsl-3
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_111411v1:
### CI changes ###
Possible regressions
* boot:
- fi-ilk-650: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/fi-ilk-650/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111411v1/fi-ilk-650/boot.html
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rpls-1}: NOTRUN -> [DMESG-WARN][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111411v1/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
Known issues
Here are the changes found in Patchwork_111411v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-apl-guc: [PASS][4] -> [INCOMPLETE][5] ([i915#7073])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111411v1/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html
Possible fixes
* igt@gem_tiled_blits@basic:
- fi-pnv-d510:[SKIP][6] ([fdo#109271]) -> [PASS][7] +1 similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/fi-pnv-d510/igt@gem_tiled_bl...@basic.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111411v1/fi-pnv-d510/igt@gem_tiled_bl...@basic.html
* igt@i915_module_load@reload:
- {bat-rpls-2}: [INCOMPLETE][8] ([i915#6434]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/bat-rpls-2/igt@i915_module_l...@reload.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111411v1/bat-rpls-2/igt@i915_module_l...@reload.html
* igt@i915_selftest@live@reset:
- {bat-rpls-1}: [DMESG-FAIL][10] ([i915#4983]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/bat-rpls-1/igt@i915_selftest@l...@reset.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111411v1/bat-rpls-1/igt@i915_selftest@l...@reset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
[i915#6559]: https://gitlab.freedesktop.org/drm/intel/issues/6559
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7073]: https://gitlab.freedesktop.org/drm/intel/issues/7073
[i915#7077]: https://gitlab.freedesktop.org/drm/intel/issues/7077
[i915#7346]: https://gitlab.freedesktop.org/drm/intel/issues/7346
Build changes
-
* Linux: CI_DRM_12440 -> Patchwork_111411v1
CI-20190529: 20190529
CI_DRM_12440: d21d6474a37e5d43075a24668807ea40a7ee9fc1 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7073: d021d66e389f4a759dc749b5f74f278ecd2e6cbf @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111411v1: d21d6474a37e5d43075a24668807ea40a7ee9fc1 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
1127d659634b drm/i915/mtl: Add support for 32 bit OAG formats in MTL
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111411v1/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: Add support for 32 bit OAG formats in MTL
== Series Details == Series: drm/i915/mtl: Add support for 32 bit OAG formats in MTL URL : https://patchwork.freedesktop.org/series/111411/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pxp: Add missing cleanup steps for PXP global-teardown
== Series Details == Series: drm/i915/pxp: Add missing cleanup steps for PXP global-teardown URL : https://patchwork.freedesktop.org/series/111409/ State : success == Summary == CI Bug Log - changes from CI_DRM_12440 -> Patchwork_111409v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111409v1/index.html Participating hosts (34 -> 35) -- Additional (1): bat-dg1-5 Known issues Here are the changes found in Patchwork_111409v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_mmap@basic: - bat-dg1-5: NOTRUN -> [SKIP][1] ([i915#4083]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111409v1/bat-dg1-5/igt@gem_m...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-5: NOTRUN -> [SKIP][2] ([i915#4077]) +2 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111409v1/bat-dg1-5/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-dg1-5: NOTRUN -> [SKIP][3] ([i915#4079]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111409v1/bat-dg1-5/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg1-5: NOTRUN -> [SKIP][4] ([i915#7561]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111409v1/bat-dg1-5/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rps@basic-api: - bat-dg1-5: NOTRUN -> [SKIP][5] ([i915#6621]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111409v1/bat-dg1-5/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@migrate: - bat-adlp-4: [PASS][6] -> [INCOMPLETE][7] ([i915#7308] / [i915#7348]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/bat-adlp-4/igt@i915_selftest@l...@migrate.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111409v1/bat-adlp-4/igt@i915_selftest@l...@migrate.html * igt@kms_addfb_basic@basic-x-tiled-legacy: - bat-dg1-5: NOTRUN -> [SKIP][8] ([i915#4212]) +7 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111409v1/bat-dg1-5/igt@kms_addfb_ba...@basic-x-tiled-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg1-5: NOTRUN -> [SKIP][9] ([i915#4215]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111409v1/bat-dg1-5/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_chamelium@hdmi-hpd-fast: - bat-dg1-5: NOTRUN -> [SKIP][10] ([fdo#111827]) +8 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111409v1/bat-dg1-5/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor: - bat-dg1-5: NOTRUN -> [SKIP][11] ([i915#4103] / [i915#4213]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111409v1/bat-dg1-5/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions: - fi-bsw-kefka: [PASS][12] -> [FAIL][13] ([i915#6298]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111409v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg1-5: NOTRUN -> [SKIP][14] ([fdo#109285]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111409v1/bat-dg1-5/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_psr@sprite_plane_onoff: - bat-dg1-5: NOTRUN -> [SKIP][15] ([i915#1072] / [i915#4078]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111409v1/bat-dg1-5/igt@kms_psr@sprite_plane_onoff.html * igt@kms_setmode@basic-clone-single-crtc: - bat-dg1-5: NOTRUN -> [SKIP][16] ([i915#3555]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111409v1/bat-dg1-5/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-read: - bat-dg1-5: NOTRUN -> [SKIP][17] ([i915#3708]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111409v1/bat-dg1-5/igt@prime_v...@basic-fence-read.html * igt@prime_vgem@basic-gtt: - bat-dg1-5: NOTRUN -> [SKIP][18] ([i915#3708] / [i915#4077]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111409v1/bat-dg1-5/igt@prime_v...@basic-gtt.html * igt@prime_vgem@basic-userptr: - bat-dg1-5: NOTRUN -> [SKIP][19] ([i915#3708] / [i915#4873]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111409v1/bat-dg1-5/igt@prime_v...@basic-userptr.html * igt@runner@aborted: -
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/pxp: Add missing cleanup steps for PXP global-teardown
== Series Details == Series: drm/i915/pxp: Add missing cleanup steps for PXP global-teardown URL : https://patchwork.freedesktop.org/series/111409/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/perf: Do not parse context image for HSW (rev4)
== Series Details ==
Series: drm/i915/perf: Do not parse context image for HSW (rev4)
URL : https://patchwork.freedesktop.org/series/111231/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12440 -> Patchwork_111231v4
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/index.html
Participating hosts (34 -> 33)
--
Additional (1): bat-dg1-5
Missing(2): fi-apl-guc fi-pnv-d510
Known issues
Here are the changes found in Patchwork_111231v4 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap@basic:
- bat-dg1-5: NOTRUN -> [SKIP][1] ([i915#4083])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/bat-dg1-5/igt@gem_m...@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg1-5: NOTRUN -> [SKIP][2] ([i915#4077]) +2 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/bat-dg1-5/igt@gem_tiled_fence_bl...@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg1-5: NOTRUN -> [SKIP][3] ([i915#4079]) +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/bat-dg1-5/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-dg1-5: NOTRUN -> [SKIP][4] ([i915#7561])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/bat-dg1-5/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_pm_rps@basic-api:
- bat-dg1-5: NOTRUN -> [SKIP][5] ([i915#6621])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/bat-dg1-5/igt@i915_pm_...@basic-api.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- bat-dg1-5: NOTRUN -> [SKIP][6] ([i915#4212]) +7 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/bat-dg1-5/igt@kms_addfb_ba...@basic-x-tiled-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-5: NOTRUN -> [SKIP][7] ([i915#4215])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/bat-dg1-5/igt@kms_addfb_ba...@basic-y-tiled-legacy.html
* igt@kms_chamelium@hdmi-hpd-fast:
- bat-dg1-5: NOTRUN -> [SKIP][8] ([fdo#111827]) +8 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/bat-dg1-5/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- bat-dg1-5: NOTRUN -> [SKIP][9] ([i915#4103] / [i915#4213])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/bat-dg1-5/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg1-5: NOTRUN -> [SKIP][10] ([fdo#109285])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/bat-dg1-5/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_psr@sprite_plane_onoff:
- bat-dg1-5: NOTRUN -> [SKIP][11] ([i915#1072] / [i915#4078]) +3
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/bat-dg1-5/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-dg1-5: NOTRUN -> [SKIP][12] ([i915#3555])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/bat-dg1-5/igt@kms_setm...@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-read:
- bat-dg1-5: NOTRUN -> [SKIP][13] ([i915#3708]) +3 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/bat-dg1-5/igt@prime_v...@basic-fence-read.html
* igt@prime_vgem@basic-gtt:
- bat-dg1-5: NOTRUN -> [SKIP][14] ([i915#3708] / [i915#4077]) +1
similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/bat-dg1-5/igt@prime_v...@basic-gtt.html
* igt@prime_vgem@basic-userptr:
- bat-dg1-5: NOTRUN -> [SKIP][15] ([i915#3708] / [i915#4873])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/bat-dg1-5/igt@prime_v...@basic-userptr.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]:
[Intel-gfx] [PATCH] drm/i915/mtl: Add support for 32 bit OAG formats in MTL
As part of OA support for MTL,
- Enable 32 bit OAG formats for MTL.
- 0x200c is repurposed on MTL. Use a separate mux table to verify oa
configs passed by user.
- Similar to ACM, OA/CS timestamp is mismatched on MTL. Add MTL to the
WA.
- On MTL, gt->scratch was using stolen lmem. An MI_SRM to stolen lmem is
hanging. Add a page in noa_wait BO to save/restore GPR registers for
the noa_wait logic.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 6 ---
drivers/gpu/drm/i915/i915_perf.c | 49 ++--
2 files changed, 38 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index c1d9cd255e06..13dffe0a3d20 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -296,12 +296,6 @@ enum intel_gt_scratch_field {
/* 8 bytes */
INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
-
- /* 6 * 8 bytes */
- INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR = 2048,
-
- /* 4 bytes */
- INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 = 2096,
};
#endif /* __INTEL_GT_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 00e09bb18b13..a735b9540113 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1842,8 +1842,7 @@ static u32 *save_restore_register(struct i915_perf_stream
*stream, u32 *cs,
for (d = 0; d < dword_count; d++) {
*cs++ = cmd;
*cs++ = i915_mmio_reg_offset(reg) + 4 * d;
- *cs++ = intel_gt_scratch_offset(stream->engine->gt,
- offset) + 4 * d;
+ *cs++ = i915_ggtt_offset(stream->noa_wait) + offset + 4 * d;
*cs++ = 0;
}
@@ -1876,7 +1875,13 @@ static int alloc_noa_wait(struct i915_perf_stream
*stream)
MI_PREDICATE_RESULT_2_ENGINE(base) :
MI_PREDICATE_RESULT_1(RENDER_RING_BASE);
- bo = i915_gem_object_create_internal(i915, 4096);
+ /*
+* gt->scratch was being used to save/restore the GPR registers, but on
+* MTL the scratch uses stolen lmem. An MI_SRM to this memory region
+* causes an engine hang. Instead allocate an additional page here to
+* save/restore GPR registers
+*/
+ bo = i915_gem_object_create_internal(i915, 8192);
if (IS_ERR(bo)) {
drm_err(>drm,
"Failed to allocate NOA wait batchbuffer\n");
@@ -1910,14 +1915,19 @@ static int alloc_noa_wait(struct i915_perf_stream
*stream)
goto err_unpin;
}
+ stream->noa_wait = vma;
+
+#define GPR_SAVE_OFFSET 4096
+#define PREDICATE_SAVE_OFFSET 4160
+
/* Save registers. */
for (i = 0; i < N_CS_GPR; i++)
cs = save_restore_register(
stream, cs, true /* save */, CS_GPR(i),
- INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
+ GPR_SAVE_OFFSET + 8 * i, 2);
cs = save_restore_register(
stream, cs, true /* save */, mi_predicate_result,
- INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
+ PREDICATE_SAVE_OFFSET, 1);
/* First timestamp snapshot location. */
ts0 = cs;
@@ -2033,10 +2043,10 @@ static int alloc_noa_wait(struct i915_perf_stream
*stream)
for (i = 0; i < N_CS_GPR; i++)
cs = save_restore_register(
stream, cs, false /* restore */, CS_GPR(i),
- INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
+ GPR_SAVE_OFFSET + 8 * i, 2);
cs = save_restore_register(
stream, cs, false /* restore */, mi_predicate_result,
- INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
+ PREDICATE_SAVE_OFFSET, 1);
/* And return to the ring. */
*cs++ = MI_BATCH_BUFFER_END;
@@ -2046,7 +2056,6 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
i915_gem_object_flush_map(bo);
__i915_gem_object_release_map(bo);
- stream->noa_wait = vma;
goto out_ww;
err_unpin:
@@ -3127,8 +3136,11 @@ get_sseu_config(struct intel_sseu *out_sseu,
*/
u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)
{
- /* Wa_18013179988:dg2 */
- if (IS_DG2(i915)) {
+ /*
+* Wa_18013179988:dg2
+* Wa_14015846243:mtl
+*/
+ if (IS_DG2(i915) || IS_METEORLAKE(i915)) {
intel_wakeref_t wakeref;
u32 reg, shift;
@@ -4306,6 +4318,17 @@ static const struct i915_range gen12_oa_mux_regs[] = {
{}
};
+/*
+ * Ref: 14010536224:
+ * 0x20cc is repurposed on MTL, so use a separate array for MTL.
+ */
+static const struct i915_range
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/pxp: Prepare intel_pxp entry points for MTL
== Series Details == Series: drm/i915/pxp: Prepare intel_pxp entry points for MTL URL : https://patchwork.freedesktop.org/series/111408/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12440 -> Patchwork_111408v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_111408v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_111408v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111408v1/index.html Participating hosts (34 -> 38) -- Additional (4): bat-atsm-1 bat-adls-5 fi-tgl-dsi bat-dg1-5 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_111408v1: ### IGT changes ### Possible regressions * igt@core_hotunplug@unbind-rebind: - fi-bsw-kefka: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/fi-bsw-kefka/igt@core_hotunp...@unbind-rebind.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111408v1/fi-bsw-kefka/igt@core_hotunp...@unbind-rebind.html - fi-adl-ddr5:[PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/fi-adl-ddr5/igt@core_hotunp...@unbind-rebind.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111408v1/fi-adl-ddr5/igt@core_hotunp...@unbind-rebind.html - fi-cfl-guc: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111408v1/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html - fi-cfl-8700k: [PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/fi-cfl-8700k/igt@core_hotunp...@unbind-rebind.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111408v1/fi-cfl-8700k/igt@core_hotunp...@unbind-rebind.html - fi-rkl-11600: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/fi-rkl-11600/igt@core_hotunp...@unbind-rebind.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111408v1/fi-rkl-11600/igt@core_hotunp...@unbind-rebind.html - fi-icl-u2: [PASS][11] -> [INCOMPLETE][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111408v1/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html - bat-dg1-5: NOTRUN -> [INCOMPLETE][13] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111408v1/bat-dg1-5/igt@core_hotunp...@unbind-rebind.html - fi-bdw-gvtdvm: [PASS][14] -> [INCOMPLETE][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/fi-bdw-gvtdvm/igt@core_hotunp...@unbind-rebind.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111408v1/fi-bdw-gvtdvm/igt@core_hotunp...@unbind-rebind.html - fi-rkl-guc: [PASS][16] -> [INCOMPLETE][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/fi-rkl-guc/igt@core_hotunp...@unbind-rebind.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111408v1/fi-rkl-guc/igt@core_hotunp...@unbind-rebind.html - fi-skl-guc: [PASS][18] -> [INCOMPLETE][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/fi-skl-guc/igt@core_hotunp...@unbind-rebind.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111408v1/fi-skl-guc/igt@core_hotunp...@unbind-rebind.html - bat-dg1-6: [PASS][20] -> [INCOMPLETE][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/bat-dg1-6/igt@core_hotunp...@unbind-rebind.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111408v1/bat-dg1-6/igt@core_hotunp...@unbind-rebind.html - fi-skl-6700k2: [PASS][22] -> [INCOMPLETE][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/fi-skl-6700k2/igt@core_hotunp...@unbind-rebind.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111408v1/fi-skl-6700k2/igt@core_hotunp...@unbind-rebind.html - fi-cfl-8109u: [PASS][24] -> [INCOMPLETE][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/fi-cfl-8109u/igt@core_hotunp...@unbind-rebind.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111408v1/fi-cfl-8109u/igt@core_hotunp...@unbind-rebind.html - bat-adlp-4: [PASS][26] -> [INCOMPLETE][27] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/bat-adlp-4/igt@core_hotunp...@unbind-rebind.html [27]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/pxp: Prepare intel_pxp entry points for MTL
== Series Details == Series: drm/i915/pxp: Prepare intel_pxp entry points for MTL URL : https://patchwork.freedesktop.org/series/111408/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [PATCH v5 0/1] drm/i915/pxp: Prepare intel_pxp entry points for MTL
(++tagging Rodrigo) This series is a replacement for https://patchwork.freedesktop.org/series/109429/. Patchwork bestowed a new URL as the series is significantly different now with the new design approach direction from Rodrigo. ...alan On Mon, 2022-11-28 at 16:31 -0800, Alan Previn wrote: > MTL has two tiles that is represented by the intel_gt structure in the i915 > code. The PXP feature has a control-structure that currently hangs off the > intel_gt structure. In MTL, the standalone media tile (i.e. not the root > tile) contains the VDBOX and KCR engine which are among several assets > that PXP relies on for establishing and tearing down the PXP session. > > However PXP is a global feature as other engines on other tiles can reference > the PXP session in an object's info within batch buffer instructions. That > coherrency is handled implicitly by the HW. In fact, for the forseeable > future, > we are expecting this link whereby only one of the tiles will be the > control-gt > for the PXP subsystem. > > Keeping the intel_pxp structure within the intel_gt structure makes some > internal functionalities more straight forward but adds code complexity to > code readibility and maintainibility to many external-to-pxp subsystems > which may need to pick the correct intel_gt structure. An example of this > would be the intel_pxp_is_active or intel_pxp_is_enabled functionality which > should be viewed as a global level inquiry, not a per-gt inquiry. > > That said, this series promotes the intel_pxp structure into the > drm_i915_private structure making it a top-level subsystem and the PXP > subsystem will select the control gt internally and keep a pointer to > it for internal reference. > > Changes from prior revs: >v4: - Instead of maintaining intel_pxp as an intel_gt structure member and > creating a number of convoluted helpers that takes in i915 as input > and redirects to the correct intel_gt or takes any intel_gt and > internally > replaces with the correct intel_gt, promote it to be a top-level i915 > structure. >v3: - Rename gt level helper functions to "intel_pxp_is_enabled/supported/ > active_on_gt" (Daniele) >- Upgrade _gt_supports_pxp to replace what was intel_gtpxp_is_supported > as the new intel_pxp_is_supported_on_gt to check for PXP feature > support vs the tee support for huc authentication. Fix pxp-debugfs- > registration to use only the former to decide support. (Daniele) >- Couple minor optimizations. >v2: - Avoid introduction of new device info or gt variables and use > existing checks / macros to differentiate the correct GT->PXP > control ownership (Daniele Ceraolo Spurio) >- Don't reuse the updated global-checkers for per-GT callers (such > as other files within PXP) to avoid unnecessary GT-reparsing, > expose a replacement helper like the prior ones. (Daniele). >v1: Add one more patch to the series for the intel_pxp suspend/resume >for similiar refactoring > > Alan Previn (1): > drm/i915/pxp: Promote pxp subsystem to top-level of i915 > > .../drm/i915/display/skl_universal_plane.c| 2 +- > drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 +- > drivers/gpu/drm/i915/gem/i915_gem_create.c| 2 +- > .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 +- > drivers/gpu/drm/i915/gt/intel_gt.c| 5 -- > drivers/gpu/drm/i915/gt/intel_gt_debugfs.c| 1 - > drivers/gpu/drm/i915/gt/intel_gt_irq.c| 2 +- > drivers/gpu/drm/i915/gt/intel_gt_pm.c | 8 --- > drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 - > drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 2 +- > drivers/gpu/drm/i915/i915_driver.c| 20 ++ > drivers/gpu/drm/i915/i915_drv.h | 3 + > drivers/gpu/drm/i915/pxp/intel_pxp.c | 72 ++- > drivers/gpu/drm/i915/pxp/intel_pxp.h | 6 +- > drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 8 ++- > drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 41 +++ > drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.h | 4 +- > drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 10 ++- > drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 4 +- > drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 8 ++- > drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 11 +++ > 21 files changed, 150 insertions(+), 70 deletions(-) > > > base-commit: d21d6474a37e5d43075a24668807ea40a7ee9fc1 > -- > 2.34.1 >
[Intel-gfx] [PATCH v2 0/3] drm/i915/pxp: Add missing cleanup steps for PXP global-teardown
A customer issue was recently discovered and in the process a gap in i915's PXP interaction with HW+FW architecure was also realized. This series adds those missing pieces. The patches explain the details. Changes from prior revs: v1: - Dont need to teardown non arbitration sessions (Juston). - Fix builds when PXP is enabled in config (Alan/CI-build) - Fix the broken pm-suspend-resume symmetry when we do this pxp-session-teardown during i915s pm_suspend_prepare by ensuring the init is done during i915s pm_resume_complete. Alan Previn (3): drm/i915/pxp: Invalidate all PXP fw sessions during teardown drm/i915/pxp: Trigger the global teardown for before suspending drm/i915/pxp: Pxp hw init should be in resume_complete drivers/gpu/drm/i915/gem/i915_gem_pm.c| 11 drivers/gpu/drm/i915/gem/i915_gem_pm.h| 2 + drivers/gpu/drm/i915/gt/intel_gt_pm.c | 7 ++- drivers/gpu/drm/i915/gt/intel_gt_pm.h | 2 + drivers/gpu/drm/i915/i915_driver.c| 16 + drivers/gpu/drm/i915/pxp/intel_pxp.c | 60 --- drivers/gpu/drm/i915/pxp/intel_pxp.h | 2 + .../drm/i915/pxp/intel_pxp_cmd_interface_42.h | 15 + .../i915/pxp/intel_pxp_cmd_interface_cmn.h| 3 + drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 4 +- drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 6 +- drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 14 - drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 5 ++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 35 +++ drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 2 + 15 files changed, 165 insertions(+), 19 deletions(-) base-commit: d21d6474a37e5d43075a24668807ea40a7ee9fc1 -- 2.34.1
[Intel-gfx] [PATCH v2 3/3] drm/i915/pxp: Pxp hw init should be in resume_complete
During suspend flow, i915 currently achors' on the pm_suspend_prepare
callback as the location where we quiesce the entire GPU and perform
all necessary cleanup in order to go into suspend. PXP is also called
during this time to perform the arbitration session teardown (with
the assurance no additional GEM IOCTLs will come after that could
restart the session).
However, if other devices or drivers fail their suspend_prepare, the
system will not go into suspend and i915 will be expected to resume
operation. In this case, we need to re-initialize the PXP hardware
and this really should be done within the pm_resume_complete callback
which is the correct opposing function in the resume sequence to
match pm_suspend_prepare of the suspend sequence.
Because this callback is the last thing at the end of resuming
we expect little to no impact to the rest of the i915 resume sequence
with this change.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 11 +++
drivers/gpu/drm/i915/gem/i915_gem_pm.h | 2 ++
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 7 +--
drivers/gpu/drm/i915/gt/intel_gt_pm.h | 2 ++
drivers/gpu/drm/i915/i915_driver.c | 16
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 2 +-
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 6 +++---
7 files changed, 40 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 0d812f4d787d..774a3fcd192a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -87,6 +87,17 @@ static void lmem_recover(struct drm_i915_private *i915)
i915_ttm_recover_region(mr);
}
+void i915_gem_resume_complete(struct drm_i915_private *i915)
+{
+ struct intel_gt *gt;
+ unsigned int i;
+
+ GEM_TRACE("%s\n", dev_name(i915->drm.dev));
+
+ for_each_gt(gt, i915, i)
+ intel_gt_resume_complete(gt);
+}
+
int i915_gem_backup_suspend(struct drm_i915_private *i915)
{
int ret;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.h
b/drivers/gpu/drm/i915/gem/i915_gem_pm.h
index bedf1e95941a..8e791a06392a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.h
@@ -20,6 +20,8 @@ void i915_gem_suspend(struct drm_i915_private *i915);
void i915_gem_suspend_late(struct drm_i915_private *i915);
int i915_gem_backup_suspend(struct drm_i915_private *i915);
+void i915_gem_resume_complete(struct drm_i915_private *i915);
+
int i915_gem_freeze(struct drm_i915_private *i915);
int i915_gem_freeze_late(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 16db85fab0b1..e1941bd36336 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -304,8 +304,6 @@ int intel_gt_resume(struct intel_gt *gt)
intel_uc_resume(>uc);
- intel_pxp_resume(>pxp);
-
user_forcewake(gt, false);
out_fw:
@@ -335,6 +333,11 @@ static void wait_for_suspend(struct intel_gt *gt)
intel_gt_pm_wait_for_idle(gt);
}
+void intel_gt_resume_complete(struct intel_gt *gt)
+{
+ intel_pxp_resume_complete(>pxp);
+}
+
void intel_gt_suspend_prepare(struct intel_gt *gt)
{
user_forcewake(gt, true);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index 6c9a46452364..f23388805332 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
@@ -77,7 +77,9 @@ void intel_gt_pm_fini(struct intel_gt *gt);
void intel_gt_suspend_prepare(struct intel_gt *gt);
void intel_gt_suspend_late(struct intel_gt *gt);
+
int intel_gt_resume(struct intel_gt *gt);
+void intel_gt_resume_complete(struct intel_gt *gt);
void intel_gt_runtime_suspend(struct intel_gt *gt);
int intel_gt_runtime_resume(struct intel_gt *gt);
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index 69103ae37779..e0b736bd0b06 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1168,6 +1168,11 @@ static bool suspend_to_idle(struct drm_i915_private
*dev_priv)
return false;
}
+static void i915_drm_complete(struct drm_device *dev)
+{
+ i915_gem_resume_complete(to_i915(dev));
+}
+
static int i915_drm_prepare(struct drm_device *dev)
{
struct drm_i915_private *i915 = to_i915(dev);
@@ -1470,6 +1475,16 @@ int i915_driver_resume_switcheroo(struct
drm_i915_private *i915)
return i915_drm_resume(>drm);
}
+static void i915_pm_complete(struct device *kdev)
+{
+ struct drm_i915_private *i915 = kdev_to_i915(kdev);
+
+ if (!i915)
+ dev_err(kdev, "DRM not initialized, aborting suspend.\n");
+
+ i915_drm_complete(>drm);
+}
+
static int i915_pm_prepare(struct device *kdev)
{
struct drm_i915_private *i915 = kdev_to_i915(kdev);
@@ -1774,6
[Intel-gfx] [PATCH v2 1/3] drm/i915/pxp: Invalidate all PXP fw sessions during teardown
A gap was recently discovered where if an application did not
invalidate all of the stream keys (intentionally or not), and the
driver did a full PXP global teardown on the GT subsystem, we
find that future session creation would fail on the security
firmware's side of the equation. i915 is the entity that needs
ensure the sessions' state across both iGT and security firmware
are at a known clean point when performing a full global teardown.
Architecturally speaking, i915 should inspect all active sessions
and submit the invalidate-stream-key PXP command to the security
firmware for each of them. However, for the upstream i915 driver
we only support the arbitration session that can be created
so that will be the only session we will cleanup.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/pxp/intel_pxp.h | 1 +
.../drm/i915/pxp/intel_pxp_cmd_interface_42.h | 15
.../i915/pxp/intel_pxp_cmd_interface_cmn.h| 3 ++
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 5 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 35 +++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 2 ++
6 files changed, 61 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 2da309088c6d..bbeb8ed8e211 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -23,6 +23,7 @@ void intel_pxp_init_hw(struct intel_pxp *pxp);
void intel_pxp_fini_hw(struct intel_pxp *pxp);
void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp);
+void intel_pxp_tee_end_arb_fw_session(struct intel_pxp *pxp, u32
arb_session_id);
int intel_pxp_start(struct intel_pxp *pxp);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_42.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_42.h
index 739f9072fa5f..26f7d9f01bf3 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_42.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_42.h
@@ -12,6 +12,9 @@
/* PXP-Opcode for Init Session */
#define PXP42_CMDID_INIT_SESSION 0x1e
+/* PXP-Opcode for Invalidate Stream Key */
+#define PXP42_CMDID_INVALIDATE_STREAM_KEY 0x0007
+
/* PXP-Input-Packet: Init Session (Arb-Session) */
struct pxp42_create_arb_in {
struct pxp_cmd_header header;
@@ -25,4 +28,16 @@ struct pxp42_create_arb_out {
struct pxp_cmd_header header;
} __packed;
+/* PXP-Input-Packet: Invalidate Stream Key */
+struct pxp42_inv_stream_key_in {
+ struct pxp_cmd_header header;
+ u32 rsvd[3];
+} __packed;
+
+/* PXP-Output-Packet: Invalidate Stream Key */
+struct pxp42_inv_stream_key_out {
+ struct pxp_cmd_header header;
+ u32 rsvd;
+} __packed;
+
#endif /* __INTEL_PXP_FW_INTERFACE_42_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h
index c2f23394f9b8..69e34ec49e78 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h
@@ -27,6 +27,9 @@ struct pxp_cmd_header {
union {
u32 status; /* out */
u32 stream_id; /* in */
+#define PXP_CMDHDR_EXTDATA_SESSION_VALID GENMASK(0, 0)
+#define PXP_CMDHDR_EXTDATA_APP_TYPE GENMASK(1, 1)
+#define PXP_CMDHDR_EXTDATA_SESSION_ID GENMASK(17, 2)
};
/* Length of the message (excluding the header) */
u32 buffer_len;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
index 85572360c71a..8eb886d3f2a0 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
@@ -91,10 +91,13 @@ static int pxp_terminate_arb_session_and_global(struct
intel_pxp *pxp)
{
int ret;
struct intel_gt *gt = pxp_to_gt(pxp);
+ u32 active_sip_slots;
/* must mark termination in progress calling this function */
GEM_WARN_ON(pxp->arb_is_valid);
+ active_sip_slots = intel_uncore_read(gt->uncore, GEN12_KCR_SIP);
+
/* terminate the hw sessions */
ret = intel_pxp_terminate_session(pxp, ARB_SESSION);
if (ret) {
@@ -110,6 +113,8 @@ static int pxp_terminate_arb_session_and_global(struct
intel_pxp *pxp)
intel_uncore_write(gt->uncore, PXP_GLOBAL_TERMINATE, 1);
+ intel_pxp_tee_end_arb_fw_session(pxp, ARB_SESSION);
+
return ret;
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index b0c9170b1395..202ea01cbb88 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -309,3 +309,38 @@ int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp
*pxp,
return ret;
}
+
+void intel_pxp_tee_end_arb_fw_session(struct intel_pxp *pxp, u32 session_id)
+{
+ struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
+ struct pxp42_inv_stream_key_in msg_in = {0};
+ struct
[Intel-gfx] [PATCH v2 2/3] drm/i915/pxp: Trigger the global teardown for before suspending
A driver bug was recently discovered where the security firmware was
receiving internal HW signals indicating that session key expirations
had occurred. Architecturally, the firmware was expecting a response
from the GuC to acknowledge the event with the firmware side.
However the OS was in a suspended state and GuC had been reset.
Internal specifications actually required the driver to ensure
that all active sessions be properly cleaned up in such cases where
the system is suspended and the GuC potentially unable to respond.
This patch adds the global teardown code in i915's suspend_prepare
code path.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 60 +---
drivers/gpu/drm/i915/pxp/intel_pxp.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 2 +-
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 9 ++-
drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 5 ++
5 files changed, 64 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 5efe61f67546..659410ae1b89 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -198,6 +198,55 @@ static bool pxp_component_bound(struct intel_pxp *pxp)
return bound;
}
+static int __pxp_global_teardown_locked(struct intel_pxp *pxp, bool
terminate_for_cleanup)
+{
+ if (terminate_for_cleanup) {
+ if (!pxp->arb_is_valid)
+ return 0;
+ /*
+* To ensure synchronous and coherent session teardown
completion
+* in response to suspend or shutdown triggers, don't user a
worker.
+*/
+ intel_pxp_mark_termination_in_progress(pxp);
+ intel_pxp_terminate(pxp, false);
+ } else {
+ if (pxp->arb_is_valid)
+ return 0;
+ /*
+* If we are not in final termination, and the arb-session is
currently
+* inactive, we are doing a reset and restart due to some
runtime event.
+* Use the worker that was designed for this.
+*/
+ pxp_queue_termination(pxp);
+ }
+
+ if (!wait_for_completion_timeout(>termination,
msecs_to_jiffies(250)))
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+void intel_pxp_end(struct intel_pxp *pxp)
+{
+ struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
+ intel_wakeref_t wakeref;
+
+ if (!intel_pxp_is_enabled(pxp))
+ return;
+
+ wakeref = intel_runtime_pm_get(>runtime_pm);
+
+ mutex_lock(>arb_mutex);
+
+ if (__pxp_global_teardown_locked(pxp, true))
+ drm_dbg(&(pxp_to_gt(pxp))->i915->drm, "PXP end timed out\n");
+
+ mutex_unlock(>arb_mutex);
+
+ intel_pxp_fini_hw(pxp);
+ intel_runtime_pm_put(>runtime_pm, wakeref);
+}
+
/*
* the arb session is restarted from the irq work when we receive the
* termination completion interrupt
@@ -214,16 +263,9 @@ int intel_pxp_start(struct intel_pxp *pxp)
mutex_lock(>arb_mutex);
- if (pxp->arb_is_valid)
- goto unlock;
-
- pxp_queue_termination(pxp);
-
- if (!wait_for_completion_timeout(>termination,
- msecs_to_jiffies(250))) {
- ret = -ETIMEDOUT;
+ ret = __pxp_global_teardown_locked(pxp, false);
+ if (ret)
goto unlock;
- }
/* make sure the compiler doesn't optimize the double access */
barrier();
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index bbeb8ed8e211..a06b65850246 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -26,6 +26,7 @@ void intel_pxp_mark_termination_in_progress(struct intel_pxp
*pxp);
void intel_pxp_tee_end_arb_fw_session(struct intel_pxp *pxp, u32
arb_session_id);
int intel_pxp_start(struct intel_pxp *pxp);
+void intel_pxp_end(struct intel_pxp *pxp);
int intel_pxp_key_check(struct intel_pxp *pxp,
struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
index 6a7d4e2ee138..36af52c28e63 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -14,7 +14,7 @@ void intel_pxp_suspend_prepare(struct intel_pxp *pxp)
if (!intel_pxp_is_enabled(pxp))
return;
- pxp->arb_is_valid = false;
+ intel_pxp_end(pxp);
intel_pxp_invalidate(pxp);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
index 8eb886d3f2a0..794ccdd00bb9 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
@@ -118,11 +118,14 @@ static int
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: fix exiting context timeout calculation
== Series Details == Series: drm/i915: fix exiting context timeout calculation URL : https://patchwork.freedesktop.org/series/111402/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12439_full -> Patchwork_111402v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_111402v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_111402v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_111402v1_full: ### IGT changes ### Possible regressions * igt@gem_exec_capture@pi@vecs0: - shard-skl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/shard-skl4/igt@gem_exec_capture@p...@vecs0.html Known issues Here are the changes found in Patchwork_111402v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@parallel-contexts: - shard-iclb: NOTRUN -> [SKIP][2] ([i915#4525]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/shard-iclb5/igt@gem_exec_balan...@parallel-contexts.html * igt@gem_exec_balancer@parallel-keep-in-fence: - shard-iclb: [PASS][3] -> [SKIP][4] ([i915#4525]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12439/shard-iclb1/igt@gem_exec_balan...@parallel-keep-in-fence.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/shard-iclb5/igt@gem_exec_balan...@parallel-keep-in-fence.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2842]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12439/shard-tglb1/igt@gem_exec_fair@basic-f...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/shard-tglb2/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-apl: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12439/shard-apl3/igt@gem_exec_fair@basic-pace-s...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/shard-apl1/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_lmem_swapping@heavy-random: - shard-skl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/shard-skl4/igt@gem_lmem_swapp...@heavy-random.html * igt@gem_pxp@fail-invalid-protected-context: - shard-iclb: NOTRUN -> [SKIP][10] ([i915#4270]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/shard-iclb5/igt@gem_...@fail-invalid-protected-context.html * igt@gem_userptr_blits@unsync-overlap: - shard-skl: NOTRUN -> [SKIP][11] ([fdo#109271]) +195 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/shard-skl7/igt@gem_userptr_bl...@unsync-overlap.html * igt@gen9_exec_parse@allowed-single: - shard-apl: [PASS][12] -> [DMESG-WARN][13] ([i915#5566] / [i915#716]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12439/shard-apl7/igt@gen9_exec_pa...@allowed-single.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/shard-apl6/igt@gen9_exec_pa...@allowed-single.html * igt@gen9_exec_parse@bb-start-cmd: - shard-iclb: NOTRUN -> [SKIP][14] ([i915#2856]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/shard-iclb5/igt@gen9_exec_pa...@bb-start-cmd.html * igt@kms_big_fb@4-tiled-8bpp-rotate-90: - shard-iclb: NOTRUN -> [SKIP][15] ([i915#5286]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/shard-iclb5/igt@kms_big...@4-tiled-8bpp-rotate-90.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip: - shard-iclb: [PASS][16] -> [DMESG-FAIL][17] ([i915#5138]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12439/shard-iclb2/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/shard-iclb1/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip: - shard-skl: NOTRUN -> [FAIL][18] ([i915#3763]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/shard-skl4/igt@kms_big...@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs: - shard-iclb:
[Intel-gfx] [PATCH v5 0/1] drm/i915/pxp: Prepare intel_pxp entry points for MTL
MTL has two tiles that is represented by the intel_gt structure in the i915 code. The PXP feature has a control-structure that currently hangs off the intel_gt structure. In MTL, the standalone media tile (i.e. not the root tile) contains the VDBOX and KCR engine which are among several assets that PXP relies on for establishing and tearing down the PXP session. However PXP is a global feature as other engines on other tiles can reference the PXP session in an object's info within batch buffer instructions. That coherrency is handled implicitly by the HW. In fact, for the forseeable future, we are expecting this link whereby only one of the tiles will be the control-gt for the PXP subsystem. Keeping the intel_pxp structure within the intel_gt structure makes some internal functionalities more straight forward but adds code complexity to code readibility and maintainibility to many external-to-pxp subsystems which may need to pick the correct intel_gt structure. An example of this would be the intel_pxp_is_active or intel_pxp_is_enabled functionality which should be viewed as a global level inquiry, not a per-gt inquiry. That said, this series promotes the intel_pxp structure into the drm_i915_private structure making it a top-level subsystem and the PXP subsystem will select the control gt internally and keep a pointer to it for internal reference. Changes from prior revs: v4: - Instead of maintaining intel_pxp as an intel_gt structure member and creating a number of convoluted helpers that takes in i915 as input and redirects to the correct intel_gt or takes any intel_gt and internally replaces with the correct intel_gt, promote it to be a top-level i915 structure. v3: - Rename gt level helper functions to "intel_pxp_is_enabled/supported/ active_on_gt" (Daniele) - Upgrade _gt_supports_pxp to replace what was intel_gtpxp_is_supported as the new intel_pxp_is_supported_on_gt to check for PXP feature support vs the tee support for huc authentication. Fix pxp-debugfs- registration to use only the former to decide support. (Daniele) - Couple minor optimizations. v2: - Avoid introduction of new device info or gt variables and use existing checks / macros to differentiate the correct GT->PXP control ownership (Daniele Ceraolo Spurio) - Don't reuse the updated global-checkers for per-GT callers (such as other files within PXP) to avoid unnecessary GT-reparsing, expose a replacement helper like the prior ones. (Daniele). v1: Add one more patch to the series for the intel_pxp suspend/resume for similiar refactoring Alan Previn (1): drm/i915/pxp: Promote pxp subsystem to top-level of i915 .../drm/i915/display/skl_universal_plane.c| 2 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 +- drivers/gpu/drm/i915/gem/i915_gem_create.c| 2 +- .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 +- drivers/gpu/drm/i915/gt/intel_gt.c| 5 -- drivers/gpu/drm/i915/gt/intel_gt_debugfs.c| 1 - drivers/gpu/drm/i915/gt/intel_gt_irq.c| 2 +- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 8 --- drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 - drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 2 +- drivers/gpu/drm/i915/i915_driver.c| 20 ++ drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/pxp/intel_pxp.c | 72 ++- drivers/gpu/drm/i915/pxp/intel_pxp.h | 6 +- drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 8 ++- drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 41 +++ drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.h | 4 +- drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 10 ++- drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 4 +- drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 8 ++- drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 11 +++ 21 files changed, 150 insertions(+), 70 deletions(-) base-commit: d21d6474a37e5d43075a24668807ea40a7ee9fc1 -- 2.34.1
[Intel-gfx] [PATCH v5 1/1] drm/i915/pxp: Promote pxp subsystem to top-level of i915
Starting with MTL, there will be two GT-tiles, a render and media
tile. PXP as a service for supporting workloads with protected
contexts and protected buffers can be subscribed by process
workloads on any tile. However, depending on the platform,
only one of the tiles is used for control events pertaining to PXP
operation (such as creating the arbitration session and session
tear-down). In the case of MTL, this is the media-tile.
Signed-off-by: Alan Previn
---
.../drm/i915/display/skl_universal_plane.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 +-
drivers/gpu/drm/i915/gem/i915_gem_create.c| 2 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 5 --
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c| 1 -
drivers/gpu/drm/i915/gt/intel_gt_irq.c| 2 +-
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 8 ---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 -
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 2 +-
drivers/gpu/drm/i915/i915_driver.c| 20 ++
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 72 ++-
drivers/gpu/drm/i915/pxp/intel_pxp.h | 6 +-
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 8 ++-
drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 41 +++
drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.h | 4 +-
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 10 ++-
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 4 +-
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 8 ++-
drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 11 +++
21 files changed, 150 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 76490cc59d8f..4b79c2d2d617 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1848,7 +1848,7 @@ static bool bo_has_valid_encryption(struct
drm_i915_gem_object *obj)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- return intel_pxp_key_check(_gt(i915)->pxp, obj, false) == 0;
+ return intel_pxp_key_check(i915->pxp, obj, false) == 0;
}
static bool pxp_is_borked(struct drm_i915_gem_object *obj)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 7f2831efc798..46e71f62fcec 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -257,7 +257,7 @@ static int proto_context_set_protected(struct
drm_i915_private *i915,
if (!protected) {
pc->uses_protected_content = false;
- } else if (!intel_pxp_is_enabled(_gt(i915)->pxp)) {
+ } else if (!intel_pxp_is_enabled(i915->pxp)) {
ret = -ENODEV;
} else if ((pc->user_flags & BIT(UCONTEXT_RECOVERABLE)) ||
!(pc->user_flags & BIT(UCONTEXT_BANNABLE))) {
@@ -271,8 +271,8 @@ static int proto_context_set_protected(struct
drm_i915_private *i915,
*/
pc->pxp_wakeref = intel_runtime_pm_get(>runtime_pm);
- if (!intel_pxp_is_active(_gt(i915)->pxp))
- ret = intel_pxp_start(_gt(i915)->pxp);
+ if (!intel_pxp_is_active(i915->pxp))
+ ret = intel_pxp_start(i915->pxp);
}
return ret;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index 33673fe7ee0a..005a7f842784 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -384,7 +384,7 @@ static int ext_set_protected(struct i915_user_extension
__user *base, void *data
if (ext.flags)
return -EINVAL;
- if (!intel_pxp_is_enabled(_gt(ext_data->i915)->pxp))
+ if (!intel_pxp_is_enabled(ext_data->i915->pxp))
return -ENODEV;
ext_data->flags |= I915_BO_PROTECTED;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 29e9e8d5b6fe..ed74d173a092 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -869,7 +869,7 @@ static struct i915_vma *eb_lookup_vma(struct
i915_execbuffer *eb, u32 handle)
*/
if (i915_gem_context_uses_protected_content(eb->gem_context) &&
i915_gem_object_is_protected(obj)) {
- err = intel_pxp_key_check(>gt->pxp, obj, true);
+ err = intel_pxp_key_check(vm->gt->i915->pxp, obj, true);
if (err) {
i915_gem_object_put(obj);
return ERR_PTR(err);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index
Re: [Intel-gfx] [PATCH 01/20] drm/i915/mtl: Initial DDI port setup
> -Original Message-
> From: Kahola, Mika
> Sent: Friday, October 14, 2022 5:47 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kahola, Mika ; Taylor, Clinton A
> ; Sripada, Radhakrishna
>
> Subject: [PATCH 01/20] drm/i915/mtl: Initial DDI port setup
>
> From: Clint Taylor
>
> Initialize c10 combo phy ports. TODO Type-C ports.
>
> Cc: Radhakrishna Sripada
>
Shouldn't this be moved after C10 phy patches. Apart from that.
Reviewed-by: Radhakrishna Sripada
> Signed-off-by: Clint Taylor
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index c52da2a21896..6a8937a7d2d9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7900,7 +7900,11 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv))
> return;
>
> - if (IS_DG2(dev_priv)) {
> + if (IS_METEORLAKE(dev_priv)) {
> + /* TODO: initialize TC ports as well */
> + intel_ddi_init(dev_priv, PORT_A);
> + intel_ddi_init(dev_priv, PORT_B);
> + } else if (IS_DG2(dev_priv)) {
> intel_ddi_init(dev_priv, PORT_A);
> intel_ddi_init(dev_priv, PORT_B);
> intel_ddi_init(dev_priv, PORT_C);
> --
> 2.34.1
[Intel-gfx] ✓ Fi.CI.BAT: success for i915: dedicated MCR locking and hardware semaphore (rev2)
== Series Details ==
Series: i915: dedicated MCR locking and hardware semaphore (rev2)
URL : https://patchwork.freedesktop.org/series/111220/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12440 -> Patchwork_111220v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/index.html
Participating hosts (34 -> 35)
--
Additional (1): bat-dg1-5
Known issues
Here are the changes found in Patchwork_111220v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap@basic:
- bat-dg1-5: NOTRUN -> [SKIP][1] ([i915#4083])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/bat-dg1-5/igt@gem_m...@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg1-5: NOTRUN -> [SKIP][2] ([i915#4077]) +2 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/bat-dg1-5/igt@gem_tiled_fence_bl...@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg1-5: NOTRUN -> [SKIP][3] ([i915#4079]) +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/bat-dg1-5/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-dg1-5: NOTRUN -> [SKIP][4] ([i915#7561])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/bat-dg1-5/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_pm_rps@basic-api:
- bat-dg1-5: NOTRUN -> [SKIP][5] ([i915#6621])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/bat-dg1-5/igt@i915_pm_...@basic-api.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- bat-dg1-5: NOTRUN -> [SKIP][6] ([i915#4212]) +7 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/bat-dg1-5/igt@kms_addfb_ba...@basic-x-tiled-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-5: NOTRUN -> [SKIP][7] ([i915#4215])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/bat-dg1-5/igt@kms_addfb_ba...@basic-y-tiled-legacy.html
* igt@kms_chamelium@hdmi-hpd-fast:
- bat-dg1-5: NOTRUN -> [SKIP][8] ([fdo#111827]) +8 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/bat-dg1-5/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- bat-dg1-5: NOTRUN -> [SKIP][9] ([i915#4103] / [i915#4213])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/bat-dg1-5/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg1-5: NOTRUN -> [SKIP][10] ([fdo#109285])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/bat-dg1-5/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_psr@sprite_plane_onoff:
- bat-dg1-5: NOTRUN -> [SKIP][11] ([i915#1072] / [i915#4078]) +3
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/bat-dg1-5/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-dg1-5: NOTRUN -> [SKIP][12] ([i915#3555])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/bat-dg1-5/igt@kms_setm...@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-read:
- bat-dg1-5: NOTRUN -> [SKIP][13] ([i915#3708]) +3 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/bat-dg1-5/igt@prime_v...@basic-fence-read.html
* igt@prime_vgem@basic-gtt:
- bat-dg1-5: NOTRUN -> [SKIP][14] ([i915#3708] / [i915#4077]) +1
similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/bat-dg1-5/igt@prime_v...@basic-gtt.html
* igt@prime_vgem@basic-userptr:
- bat-dg1-5: NOTRUN -> [SKIP][15] ([i915#3708] / [i915#4873])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/bat-dg1-5/igt@prime_v...@basic-userptr.html
Possible fixes
* igt@gem_tiled_blits@basic:
- fi-pnv-d510:[SKIP][16] ([fdo#109271]) -> [PASS][17] +1 similar
issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/fi-pnv-d510/igt@gem_tiled_bl...@basic.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/fi-pnv-d510/igt@gem_tiled_bl...@basic.html
* igt@i915_module_load@reload:
- {bat-rpls-2}: [INCOMPLETE][18] ([i915#6434]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/bat-rpls-2/igt@i915_module_l...@reload.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111220v2/bat-rpls-2/igt@i915_module_l...@reload.html
* igt@i915_selftest@live@reset:
- {bat-rpls-1}: [DMESG-FAIL][20] ([i915#4983]) -> [PASS][21]
[20]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: dedicated MCR locking and hardware semaphore (rev2)
== Series Details == Series: i915: dedicated MCR locking and hardware semaphore (rev2) URL : https://patchwork.freedesktop.org/series/111220/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [PATCH 2/3] drm/i915/mtl: Define new PTE encode for MTL
On 29-11-2022 01:22, Yang, Fei wrote:
>> From: Iddamsetty, Aravind
>> Sent: Monday, November 28, 2022 2:14 AM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: De Marchi, Lucas ; Roper, Matthew D
>> ; Yang, Fei
>> Subject: [PATCH 2/3] drm/i915/mtl: Define new PTE encode for MTL
>>
>> Add a separate PTE encode function for MTL. The number of PAT
>> registers have increased to 16 on MTL. All 16 PAT registers are
>> available for PPGTT mapped pages, but only the lower 4 are
>> available for GGTT mapped pages.
>>
>> BSPEC: 63884
>>
>> Cc: Lucas De Marchi
>> Cc: Matt Roper
>> Co-developed-by: Fei Yang
>> Signed-off-by: Fei Yang
>> Signed-off-by: Aravind Iddamsetty
>> ---
>> drivers/gpu/drm/i915/display/intel_dpt.c | 2 +-
>> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 43
>> drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 4 +++
>> drivers/gpu/drm/i915/gt/intel_ggtt.c | 36 ++--
>> drivers/gpu/drm/i915/gt/intel_gtt.h | 13 +--
>> 5 files changed, 86 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
>> b/drivers/gpu/drm/i915/display/intel_dpt.c
>> index ad1a37b515fb..cb8ed9bfb240 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dpt.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dpt.c
>> @@ -298,7 +298,7 @@ intel_dpt_create(struct intel_framebuffer *fb)
>> vm->vma_ops.bind_vma= dpt_bind_vma;
>> vm->vma_ops.unbind_vma = dpt_unbind_vma;
>>
>> - vm->pte_encode = gen8_ggtt_pte_encode;
>> + vm->pte_encode = vm->gt->ggtt->vm.pte_encode;
>>
>> dpt->obj = dpt_obj;
>>
>> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> index 4daaa6f55668..4197b43150cc 100644
>> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> @@ -55,6 +55,34 @@ static u64 gen8_pte_encode(dma_addr_t addr,
>> return pte;
>> }
>>
>> +static u64 mtl_pte_encode(dma_addr_t addr,
>> + enum i915_cache_level level,
>> + u32 flags)
>> +{
>> + gen8_pte_t pte = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
>> +
>> + if (unlikely(flags & PTE_READ_ONLY))
>> + pte &= ~GEN8_PAGE_RW;
>> +
>> + if (flags & PTE_LM)
>> + pte |= GEN12_PPGTT_PTE_LM | GEN12_PPGTT_PTE_NC;
>> +
>> + switch (level) {
>> + case I915_CACHE_NONE:
>> + pte |= GEN12_PPGTT_PTE_PAT1;
>> + break;
>> + case I915_CACHE_LLC:
>> + case I915_CACHE_L3_LLC:
>> + pte |= GEN12_PPGTT_PTE_PAT0 | GEN12_PPGTT_PTE_PAT1;
>> + break;
>> + case I915_CACHE_WT:
>> + pte |= GEN12_PPGTT_PTE_PAT0;
>> + break;
>> + }
>
> How are the PAT indices greater then 3 being handled for ppgtt?
The default cachelevels we have will use upto 3 indices only, and also
presently we do not have way to select PAT index, when in future we
support setting PAT Index via VM_BIND we shall extend this as well.
>
>> +
>> + return pte;
>> +}
>> +
>> static void gen8_ppgtt_notify_vgt(struct i915_ppgtt *ppgtt, bool create) {
>> struct drm_i915_private *i915 = ppgtt->vm.i915; @@ -427,7 +455,7 @@
>> gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
>> u32 flags)
>> {
>> struct i915_page_directory *pd;
>> - const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
>> + const gen8_pte_t pte_encode = ppgtt->vm.pte_encode(0, cache_level,
>> +flags);
>> gen8_pte_t *vaddr;
>>
>> pd = i915_pd_entry(pdp, gen8_pd_index(idx, 2)); @@ -580,7 +608,7 @@
>> static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
>> enum i915_cache_level cache_level,
>> u32 flags)
>> {
>> - const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
>> + const gen8_pte_t pte_encode = vm->pte_encode(0, cache_level, flags);
>> unsigned int rem = sg_dma_len(iter->sg);
>> u64 start = vma_res->start;
>>
>> @@ -743,7 +771,7 @@ static void gen8_ppgtt_insert_entry(struct
>> i915_address_space *vm,
>> GEM_BUG_ON(pt->is_compact);
>>
>> vaddr = px_vaddr(pt);
>> - vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
>> + vaddr[gen8_pd_index(idx, 0)] = vm->pte_encode(addr, level, flags);
>> drm_clflush_virt_range([gen8_pd_index(idx, 0)], sizeof(*vaddr));
>> }
>>
>> @@ -773,7 +801,7 @@ static void __xehpsdv_ppgtt_insert_entry_lm(struct
>> i915_address_space *vm,
>> }
>>
>> vaddr = px_vaddr(pt);
>> - vaddr[gen8_pd_index(idx, 0) / 16] = gen8_pte_encode(addr, level,
>> flags);
>> + vaddr[gen8_pd_index(idx, 0) / 16] = vm->pte_encode(addr, level,
>> +flags);
>> }
>>
>> static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm, @@
>> -820,7 +848,7 @@ static int gen8_init_scratch(struct i915_address_space *vm)
>> pte_flags |= PTE_LM;
>>
>>
[Intel-gfx] [PATCH v2 1/5] drm/i915/gt: Correct kerneldoc for intel_gt_mcr_wait_for_reg()
The kerneldoc function name was not updated when this function was
converted to a non-fw form.
Fixes: 192bb40f030a ("drm/i915/gt: Manage uncore->lock while waiting on MCR
register")
Reported-by: kernel test robot
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index d9a8ff9e5e57..ea86c1ab5dc5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -702,7 +702,7 @@ void intel_gt_mcr_get_ss_steering(struct intel_gt *gt,
unsigned int dss,
}
/**
- * intel_gt_mcr_wait_for_reg_fw - wait until MCR register matches expected
state
+ * intel_gt_mcr_wait_for_reg - wait until MCR register matches expected state
* @gt: GT structure
* @reg: the register to read
* @mask: mask to apply to register value
--
2.38.1
[Intel-gfx] [PATCH v2 5/5] drm/i915/mtl: Hold forcewake and MCR lock over PPAT setup
PPAT setup involves a series of multicast writes. This can be optimized
slightly be acquiring forcewake and the steering lock just once for the
entire sequence.
Suggested-by: Balasubramani Vivekanandan
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gtt.c | 27 +++
1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 2ba3983984b9..288d9f118ee9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -482,14 +482,25 @@ static void tgl_setup_private_ppat(struct intel_uncore
*uncore)
static void xehp_setup_private_ppat(struct intel_gt *gt)
{
- intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(0), GEN8_PPAT_WB);
- intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(1), GEN8_PPAT_WC);
- intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(2), GEN8_PPAT_WT);
- intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(3), GEN8_PPAT_UC);
- intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(4), GEN8_PPAT_WB);
- intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(5), GEN8_PPAT_WB);
- intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(6), GEN8_PPAT_WB);
- intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(7), GEN8_PPAT_WB);
+ enum forcewake_domains fw;
+ unsigned long flags;
+
+ fw = intel_uncore_forcewake_for_reg(gt->uncore,
_MMIO(XEHP_PAT_INDEX(0).reg),
+ FW_REG_READ);
+ intel_uncore_forcewake_get(gt->uncore, fw);
+
+ intel_gt_mcr_lock(gt, );
+ intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(0), GEN8_PPAT_WB);
+ intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(1), GEN8_PPAT_WC);
+ intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(2), GEN8_PPAT_WT);
+ intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(3), GEN8_PPAT_UC);
+ intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(4), GEN8_PPAT_WB);
+ intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(5), GEN8_PPAT_WB);
+ intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(6), GEN8_PPAT_WB);
+ intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(7), GEN8_PPAT_WB);
+ intel_gt_mcr_unlock(gt, flags);
+
+ intel_uncore_forcewake_put(gt->uncore, fw);
}
static void icl_setup_private_ppat(struct intel_uncore *uncore)
--
2.38.1
[Intel-gfx] [PATCH v2 4/5] drm/i915/mtl: Add hardware-level lock for steering
Starting with MTL, the driver needs to not only protect the steering
control register from simultaneous software accesses, but also protect
against races with hardware/firmware agents. The hardware provides a
dedicated locking mechanism to support this via the MTL_STEER_SEMAPHORE
register. Reading the register acts as a 'trylock' operation; the read
will return 0x1 if the lock is acquired or 0x0 if something else is
already holding the lock; once acquired, writing 0x1 to the register
will release the lock.
We'll continue to grab the software lock as well, just so lockdep can
track our locking; assuming the hardware lock is behaving properly,
there should never be any contention on the software lock in this case.
v2:
- Extend hardware semaphore timeout and add a taint for CI if it ever
happens (this would imply misbehaving hardware/firmware). (Mika)
- Add "MTL_" prefix to new steering semaphore register. (Mika)
Cc: Mika Kuoppala
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 38 ++---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
2 files changed, 35 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index aa070ae57f11..087e4ac5b68d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -347,10 +347,9 @@ static u32 rw_with_mcr_steering(struct intel_gt *gt,
* @flags: storage to save IRQ flags to
*
* Performs locking to protect the steering for the duration of an MCR
- * operation. Depending on the platform, this may be a software lock
- * (gt->mcr_lock) or a hardware lock (i.e., a register that synchronizes
- * access not only for the driver, but also for external hardware and
- * firmware agents).
+ * operation. On MTL and beyond, a hardware lock will also be taken to
+ * serialize access not only for the driver, but also for external hardware and
+ * firmware agents.
*
* Context: Takes gt->mcr_lock. uncore->lock should *not* be held when this
* function is called, although it may be acquired after this
@@ -359,12 +358,40 @@ static u32 rw_with_mcr_steering(struct intel_gt *gt,
void intel_gt_mcr_lock(struct intel_gt *gt, unsigned long *flags)
{
unsigned long __flags;
+ int err = 0;
lockdep_assert_not_held(>uncore->lock);
+ /*
+* Starting with MTL, we need to coordinate not only with other
+* driver threads, but also with hardware/firmware agents. A dedicated
+* locking register is used.
+*/
+ if (GRAPHICS_VER(gt->i915) >= IP_VER(12, 70))
+ err = wait_for(intel_uncore_read_fw(gt->uncore,
+ MTL_STEER_SEMAPHORE) ==
0x1, 100);
+
+ /*
+* Even on platforms with a hardware lock, we'll continue to grab
+* a software spinlock too for lockdep purposes. If the hardware lock
+* was already acquired, there should never be contention on the
+* software lock.
+*/
spin_lock_irqsave(>mcr_lock, __flags);
*flags = __flags;
+
+ /*
+* In theory we should never fail to acquire the HW semaphore; this
+* would indicate some hardware/firmware is misbehaving and not
+* releasing it properly.
+*/
+ if (err == -ETIMEDOUT) {
+ drm_err_ratelimited(>i915->drm,
+ "GT%u hardware MCR steering semaphore timed
out",
+ gt->info.id);
+ add_taint_for_CI(gt->i915, TAINT_WARN); /* CI is now
unreliable */
+ }
}
/**
@@ -379,6 +406,9 @@ void intel_gt_mcr_lock(struct intel_gt *gt, unsigned long
*flags)
void intel_gt_mcr_unlock(struct intel_gt *gt, unsigned long flags)
{
spin_unlock_irqrestore(>mcr_lock, flags);
+
+ if (GRAPHICS_VER(gt->i915) >= IP_VER(12, 70))
+ intel_uncore_write_fw(gt->uncore, MTL_STEER_SEMAPHORE, 0x1);
}
/**
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 784152548472..1618d46cb8c7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -67,6 +67,7 @@
#define GMD_ID_MEDIA _MMIO(MTL_MEDIA_GSI_BASE +
0xd8c)
#define MCFG_MCR_SELECTOR _MMIO(0xfd0)
+#define MTL_STEER_SEMAPHORE_MMIO(0xfd0)
#define MTL_MCR_SELECTOR _MMIO(0xfd4)
#define SF_MCR_SELECTOR_MMIO(0xfd8)
#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
--
2.38.1
[Intel-gfx] [PATCH v2 2/5] drm/i915/gt: Pass gt rather than uncore to lowest-level reads/writes
Passing the GT rather than uncore to the lowest level MCR read and write
functions will make it easier to introduce dedicated MCR locking in a
following patch.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index ea86c1ab5dc5..f4484bb18ec9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -221,7 +221,7 @@ static i915_reg_t mcr_reg_cast(const i915_mcr_reg_t mcr)
/*
* rw_with_mcr_steering_fw - Access a register with specific MCR steering
- * @uncore: pointer to struct intel_uncore
+ * @gt: GT to read register from
* @reg: register being accessed
* @rw_flag: FW_REG_READ for read access or FW_REG_WRITE for write access
* @group: group number (documented as "sliceid" on older platforms)
@@ -232,10 +232,11 @@ static i915_reg_t mcr_reg_cast(const i915_mcr_reg_t mcr)
*
* Caller needs to make sure the relevant forcewake wells are up.
*/
-static u32 rw_with_mcr_steering_fw(struct intel_uncore *uncore,
+static u32 rw_with_mcr_steering_fw(struct intel_gt *gt,
i915_mcr_reg_t reg, u8 rw_flag,
int group, int instance, u32 value)
{
+ struct intel_uncore *uncore = gt->uncore;
u32 mcr_mask, mcr_ss, mcr, old_mcr, val = 0;
lockdep_assert_held(>lock);
@@ -308,11 +309,12 @@ static u32 rw_with_mcr_steering_fw(struct intel_uncore
*uncore,
return val;
}
-static u32 rw_with_mcr_steering(struct intel_uncore *uncore,
+static u32 rw_with_mcr_steering(struct intel_gt *gt,
i915_mcr_reg_t reg, u8 rw_flag,
int group, int instance,
u32 value)
{
+ struct intel_uncore *uncore = gt->uncore;
enum forcewake_domains fw_domains;
u32 val;
@@ -325,7 +327,7 @@ static u32 rw_with_mcr_steering(struct intel_uncore *uncore,
spin_lock_irq(>lock);
intel_uncore_forcewake_get__locked(uncore, fw_domains);
- val = rw_with_mcr_steering_fw(uncore, reg, rw_flag, group, instance,
value);
+ val = rw_with_mcr_steering_fw(gt, reg, rw_flag, group, instance, value);
intel_uncore_forcewake_put__locked(uncore, fw_domains);
spin_unlock_irq(>lock);
@@ -347,7 +349,7 @@ u32 intel_gt_mcr_read(struct intel_gt *gt,
i915_mcr_reg_t reg,
int group, int instance)
{
- return rw_with_mcr_steering(gt->uncore, reg, FW_REG_READ, group,
instance, 0);
+ return rw_with_mcr_steering(gt, reg, FW_REG_READ, group, instance, 0);
}
/**
@@ -364,7 +366,7 @@ u32 intel_gt_mcr_read(struct intel_gt *gt,
void intel_gt_mcr_unicast_write(struct intel_gt *gt, i915_mcr_reg_t reg, u32
value,
int group, int instance)
{
- rw_with_mcr_steering(gt->uncore, reg, FW_REG_WRITE, group, instance,
value);
+ rw_with_mcr_steering(gt, reg, FW_REG_WRITE, group, instance, value);
}
/**
@@ -588,7 +590,7 @@ u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt,
i915_mcr_reg_t reg)
for (type = 0; type < NUM_STEERING_TYPES; type++) {
if (reg_needs_read_steering(gt, reg, type)) {
get_nonterminated_steering(gt, type, , );
- return rw_with_mcr_steering_fw(gt->uncore, reg,
+ return rw_with_mcr_steering_fw(gt, reg,
FW_REG_READ,
group, instance, 0);
}
@@ -615,7 +617,7 @@ u32 intel_gt_mcr_read_any(struct intel_gt *gt,
i915_mcr_reg_t reg)
for (type = 0; type < NUM_STEERING_TYPES; type++) {
if (reg_needs_read_steering(gt, reg, type)) {
get_nonterminated_steering(gt, type, , );
- return rw_with_mcr_steering(gt->uncore, reg,
+ return rw_with_mcr_steering(gt, reg,
FW_REG_READ,
group, instance, 0);
}
--
2.38.1
[Intel-gfx] [PATCH v2 3/5] drm/i915/gt: Add dedicated MCR lock
We've been overloading uncore->lock to protect access to the MCR
steering register. That's not really what uncore->lock is intended for,
and it would be better if we didn't need to hold such a high-traffic
spinlock for the whole sequence of (apply steering, access MCR register,
restore steering). Let's create a dedicated MCR lock to protect the
steering control register over this critical section and stop relying on
the high-traffic uncore->lock.
For now the new lock is a software lock. However some platforms (MTL
and beyond) have a hardware-provided locking mechanism that can be used
to serialize not only software accesses, but also hardware/firmware
accesses as well; support for that hardware level lock will be added in
a future patch.
v2:
- Use irqsave/irqrestore spinlock calls; platforms using execlist
submission rather than GuC submission can perform MCR accesses in
interrupt context because reset -> errordump happens in a tasklet.
Cc: Chris Wilson
Cc: Mika Kuoppala
Cc: Balasubramani Vivekanandan
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 7 +-
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 79 +++--
drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 2 +
drivers/gpu/drm/i915/gt/intel_gt_types.h| 8 +++
drivers/gpu/drm/i915/gt/intel_mocs.c| 3 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 ++--
6 files changed, 101 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 7ef0edb2e37c..6847f3bd2b03 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1079,6 +1079,7 @@ static void mmio_invalidate_full(struct intel_gt *gt)
enum intel_engine_id id;
const i915_reg_t *regs;
unsigned int num = 0;
+ unsigned long flags;
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
regs = NULL;
@@ -1099,7 +1100,8 @@ static void mmio_invalidate_full(struct intel_gt *gt)
intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
- spin_lock_irq(>lock); /* serialise invalidate with GT reset */
+ intel_gt_mcr_lock(gt, );
+ spin_lock(>lock); /* serialise invalidate with GT reset */
awake = 0;
for_each_engine(engine, gt, id) {
@@ -1133,7 +1135,8 @@ static void mmio_invalidate_full(struct intel_gt *gt)
IS_ALDERLAKE_P(i915)))
intel_uncore_write_fw(uncore, GEN12_OA_TLB_INV_CR, 1);
- spin_unlock_irq(>lock);
+ spin_unlock(>lock);
+ intel_gt_mcr_unlock(gt, flags);
for_each_engine_masked(engine, gt, awake, tmp) {
struct reg_and_bit rb;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index f4484bb18ec9..aa070ae57f11 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -143,6 +143,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
unsigned long fuse;
int i;
+ spin_lock_init(>mcr_lock);
+
/*
* An mslice is unavailable only if both the meml3 for the slice is
* disabled *and* all of the DSS in the slice (quadrant) are disabled.
@@ -228,6 +230,7 @@ static i915_reg_t mcr_reg_cast(const i915_mcr_reg_t mcr)
* @instance: instance number (documented as "subsliceid" on older platforms)
* @value: register value to be written (ignored for read)
*
+ * Context: The caller must hold the MCR lock
* Return: 0 for write access. register value for read access.
*
* Caller needs to make sure the relevant forcewake wells are up.
@@ -239,7 +242,7 @@ static u32 rw_with_mcr_steering_fw(struct intel_gt *gt,
struct intel_uncore *uncore = gt->uncore;
u32 mcr_mask, mcr_ss, mcr, old_mcr, val = 0;
- lockdep_assert_held(>lock);
+ lockdep_assert_held(>mcr_lock);
if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 70)) {
/*
@@ -316,6 +319,7 @@ static u32 rw_with_mcr_steering(struct intel_gt *gt,
{
struct intel_uncore *uncore = gt->uncore;
enum forcewake_domains fw_domains;
+ unsigned long flags;
u32 val;
fw_domains = intel_uncore_forcewake_for_reg(uncore, mcr_reg_cast(reg),
@@ -324,17 +328,59 @@ static u32 rw_with_mcr_steering(struct intel_gt *gt,
GEN8_MCR_SELECTOR,
FW_REG_READ |
FW_REG_WRITE);
- spin_lock_irq(>lock);
+ intel_gt_mcr_lock(gt, );
+ spin_lock(>lock);
intel_uncore_forcewake_get__locked(uncore, fw_domains);
val = rw_with_mcr_steering_fw(gt, reg, rw_flag, group, instance, value);
intel_uncore_forcewake_put__locked(uncore, fw_domains);
- spin_unlock_irq(>lock);
+ spin_unlock(>lock);
+ intel_gt_mcr_unlock(gt, flags);
return val;
}
+/**
+ * intel_gt_mcr_lock - Acquire MCR steering
[Intel-gfx] [PATCH v2 0/5] i915: dedicated MCR locking and hardware semaphore
We've been overloading uncore->lock to protect access to the MCR steering register. That's not really what uncore->lock is intended for, and it would be better if we didn't need to hold such a high-traffic spinlock for the whole sequence of (apply steering, access MCR register, restore steering). Switch to a dedicated MCR lock to protect the steering control register over this critical section and stop relying on the high-traffic uncore->lock. On pre-MTL platforms the dedicated MCR lock is just another software lock, but on MTL and beyond we also utilize the hardware-provided STEER_SEMAPHORE that allows us to synchronize with external hardware and firmware agents. v2: - Use irqsave/irqrestore locking; on platforms that use execlist submission instead of GuC, MCR accesses can happen in interrupt context (tasklet) during reset -> error dump. - Extend timeout for hardware semaphore and CI taint if we ever encounter it (this implies a hardware/firmware problem). (Mika) - Add an extra patch optimizing xehp_setup_private_ppat by holding forcewake & mcr lock over the sequence of register writes. (Bala) Cc: Mika Kuoppala Cc: Balasubramani Vivekanandan Matt Roper (5): drm/i915/gt: Correct kerneldoc for intel_gt_mcr_wait_for_reg() drm/i915/gt: Pass gt rather than uncore to lowest-level reads/writes drm/i915/gt: Add dedicated MCR lock drm/i915/mtl: Add hardware-level lock for steering drm/i915/mtl: Hold forcewake and MCR lock over PPAT setup drivers/gpu/drm/i915/gt/intel_gt.c | 7 +- drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 129 ++-- drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 2 + drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_gt_types.h| 8 ++ drivers/gpu/drm/i915/gt/intel_gtt.c | 27 ++-- drivers/gpu/drm/i915/gt/intel_mocs.c| 3 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 +- 8 files changed, 162 insertions(+), 27 deletions(-) -- 2.38.1
[Intel-gfx] ✓ Fi.CI.IGT: success for Align DDI_BUF_CTL Active timeouts with Bspec updates (rev2)
== Series Details == Series: Align DDI_BUF_CTL Active timeouts with Bspec updates (rev2) URL : https://patchwork.freedesktop.org/series/111373/ State : success == Summary == CI Bug Log - changes from CI_DRM_12439_full -> Patchwork_111373v2_full Summary --- **SUCCESS** No regressions found. Participating hosts (10 -> 10) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_111373v2_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@vecs0: - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([i915#4793]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12439/shard-skl9/igt@gem_ctx_isolation@preservation...@vecs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/shard-skl10/igt@gem_ctx_isolation@preservation...@vecs0.html * igt@gem_exec_balancer@parallel-contexts: - shard-iclb: NOTRUN -> [SKIP][3] ([i915#4525]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/shard-iclb5/igt@gem_exec_balan...@parallel-contexts.html * igt@gem_exec_balancer@parallel-keep-in-fence: - shard-iclb: [PASS][4] -> [SKIP][5] ([i915#4525]) +2 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12439/shard-iclb1/igt@gem_exec_balan...@parallel-keep-in-fence.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/shard-iclb3/igt@gem_exec_balan...@parallel-keep-in-fence.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2842]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12439/shard-tglb1/igt@gem_exec_fair@basic-f...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/shard-tglb1/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-apl: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12439/shard-apl3/igt@gem_exec_fair@basic-pace-s...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/shard-apl7/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_lmem_swapping@heavy-random: - shard-skl: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +2 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/shard-skl3/igt@gem_lmem_swapp...@heavy-random.html * igt@gem_pxp@fail-invalid-protected-context: - shard-iclb: NOTRUN -> [SKIP][11] ([i915#4270]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/shard-iclb5/igt@gem_...@fail-invalid-protected-context.html * igt@gem_spin_batch@spin-each: - shard-skl: [PASS][12] -> [FAIL][13] ([i915#2898]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12439/shard-skl4/igt@gem_spin_ba...@spin-each.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/shard-skl3/igt@gem_spin_ba...@spin-each.html * igt@gem_userptr_blits@unsync-overlap: - shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271]) +167 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/shard-skl1/igt@gem_userptr_bl...@unsync-overlap.html * igt@gen9_exec_parse@bb-start-cmd: - shard-iclb: NOTRUN -> [SKIP][15] ([i915#2856]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/shard-iclb5/igt@gen9_exec_pa...@bb-start-cmd.html * igt@kms_big_fb@4-tiled-8bpp-rotate-90: - shard-iclb: NOTRUN -> [SKIP][16] ([i915#5286]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/shard-iclb5/igt@kms_big...@4-tiled-8bpp-rotate-90.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip: - shard-iclb: [PASS][17] -> [DMESG-FAIL][18] ([i915#5138]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12439/shard-iclb2/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/shard-iclb5/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip: - shard-skl: NOTRUN -> [FAIL][19] ([i915#3763]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/shard-skl3/igt@kms_big...@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs: - shard-iclb: NOTRUN -> [SKIP][20] ([fdo#109278]) +5 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/shard-iclb5/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs.html * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs: - shard-skl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#3886]) +7 similar issues
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/huc: always init the delayed load fence (rev2)
== Series Details ==
Series: drm/i915/huc: always init the delayed load fence (rev2)
URL : https://patchwork.freedesktop.org/series/111288/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12440 -> Patchwork_111288v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v2/index.html
Participating hosts (34 -> 31)
--
Missing(3): bat-kbl-2 bat-adlp-4 bat-jsl-3
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_111288v2:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_suspend@basic-s3-without-i915:
- {bat-rpls-1}: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v2/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-2:
- {bat-dg2-11}: [PASS][2] -> [FAIL][3] +1 similar issue
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-...@pipe-a-dp-2.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v2/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-...@pipe-a-dp-2.html
Known issues
Here are the changes found in Patchwork_111288v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_linear_blits@basic:
- fi-pnv-d510:[PASS][4] -> [SKIP][5] ([fdo#109271])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/fi-pnv-d510/igt@gem_linear_bl...@basic.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v2/fi-pnv-d510/igt@gem_linear_bl...@basic.html
* igt@gem_lmem_swapping@basic:
- fi-pnv-d510:NOTRUN -> [SKIP][6] ([fdo#109271]) +5 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v2/fi-pnv-d510/igt@gem_lmem_swapp...@basic.html
* igt@i915_pm_rpm@module-reload:
- fi-blb-e6850: NOTRUN -> [SKIP][7] ([fdo#109271]) +5 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v2/fi-blb-e6850/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live@hangcheck:
- fi-rkl-guc: [PASS][8] -> [INCOMPLETE][9] ([i915#4983])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/fi-rkl-guc/igt@i915_selftest@l...@hangcheck.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v2/fi-rkl-guc/igt@i915_selftest@l...@hangcheck.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-blb-e6850: [INCOMPLETE][10] ([i915#7605]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v2/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html
- fi-pnv-d510:[INCOMPLETE][12] ([i915#7605]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12440/fi-pnv-d510/igt@core_hotunp...@unbind-rebind.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111288v2/fi-pnv-d510/igt@core_hotunp...@unbind-rebind.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
[i915#6559]: https://gitlab.freedesktop.org/drm/intel/issues/6559
[i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
[i915#6818]: https://gitlab.freedesktop.org/drm/intel/issues/6818
[i915#7348]: https://gitlab.freedesktop.org/drm/intel/issues/7348
[i915#7605]: https://gitlab.freedesktop.org/drm/intel/issues/7605
Build changes
-
* Linux: CI_DRM_12440 -> Patchwork_111288v2
CI-20190529: 20190529
CI_DRM_12440: d21d6474a37e5d43075a24668807ea40a7ee9fc1 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7073: d021d66e389f4a759dc749b5f74f278ecd2e6cbf @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111288v2: d21d6474a37e5d43075a24668807ea40a7ee9fc1 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
1d52f400e75d drm/i915/huc: always init the delayed
Re: [Intel-gfx] [PATCH] drm/i915/gt: remove some limited use register access wrappers
On 23.11.2022 17:49, Jani Nikula wrote:
Remove rmw_set(), rmw_clear(), clear_register(), rmw_set_fw(), and
rmw_clear_fw(). They're just one too many levels of abstraction for
register access, for very specific purposes.
clear_register() seems like a micro-optimization bypassing the write
when the register is already clear, but that trick has ceased to work
since commit 06b975d58fd6 ("drm/i915: make intel_uncore_rmw() write
unconditionally"). Just clear the register in the most obvious way.
Signed-off-by: Jani Nikula
Reviewed-by: Andrzej Hajda
Regards
Andrzej
Re: [Intel-gfx] [PATCH 2/3] drm/i915/mtl: Define new PTE encode for MTL
On Mon, Nov 28, 2022 at 03:43:51PM +0530, Aravind Iddamsetty wrote:
Add a separate PTE encode function for MTL. The number of PAT registers
have increased to 16 on MTL. All 16 PAT registers are available for
PPGTT mapped pages, but only the lower 4 are available for GGTT mapped
pages.
this would be easier to review with a preparatory patch, replacing
direct calls to gen8_pte_encode() and gen8_ggtt_pte_encode() with the
indirect ones through vm.
Then the patch on top adding MTL would be the definition of the new
encoding (mtl_pte_encode/mtl_ggtt_pte_encode) and assigning the function
pointer.
Lucas De Marchi
BSPEC: 63884
Cc: Lucas De Marchi
Cc: Matt Roper
Co-developed-by: Fei Yang
Signed-off-by: Fei Yang
Signed-off-by: Aravind Iddamsetty
---
drivers/gpu/drm/i915/display/intel_dpt.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 43
drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 4 +++
drivers/gpu/drm/i915/gt/intel_ggtt.c | 36 ++--
drivers/gpu/drm/i915/gt/intel_gtt.h | 13 +--
5 files changed, 86 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
b/drivers/gpu/drm/i915/display/intel_dpt.c
index ad1a37b515fb..cb8ed9bfb240 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -298,7 +298,7 @@ intel_dpt_create(struct intel_framebuffer *fb)
vm->vma_ops.bind_vma= dpt_bind_vma;
vm->vma_ops.unbind_vma = dpt_unbind_vma;
- vm->pte_encode = gen8_ggtt_pte_encode;
+ vm->pte_encode = vm->gt->ggtt->vm.pte_encode;
dpt->obj = dpt_obj;
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 4daaa6f55668..4197b43150cc 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -55,6 +55,34 @@ static u64 gen8_pte_encode(dma_addr_t addr,
return pte;
}
+static u64 mtl_pte_encode(dma_addr_t addr,
+ enum i915_cache_level level,
+ u32 flags)
+{
+ gen8_pte_t pte = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
+
+ if (unlikely(flags & PTE_READ_ONLY))
+ pte &= ~GEN8_PAGE_RW;
+
+ if (flags & PTE_LM)
+ pte |= GEN12_PPGTT_PTE_LM | GEN12_PPGTT_PTE_NC;
+
+ switch (level) {
+ case I915_CACHE_NONE:
+ pte |= GEN12_PPGTT_PTE_PAT1;
+ break;
+ case I915_CACHE_LLC:
+ case I915_CACHE_L3_LLC:
+ pte |= GEN12_PPGTT_PTE_PAT0 | GEN12_PPGTT_PTE_PAT1;
+ break;
+ case I915_CACHE_WT:
+ pte |= GEN12_PPGTT_PTE_PAT0;
+ break;
+ }
+
+ return pte;
+}
+
static void gen8_ppgtt_notify_vgt(struct i915_ppgtt *ppgtt, bool create)
{
struct drm_i915_private *i915 = ppgtt->vm.i915;
@@ -427,7 +455,7 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
u32 flags)
{
struct i915_page_directory *pd;
- const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
+ const gen8_pte_t pte_encode = ppgtt->vm.pte_encode(0, cache_level,
flags);
gen8_pte_t *vaddr;
pd = i915_pd_entry(pdp, gen8_pd_index(idx, 2));
@@ -580,7 +608,7 @@ static void gen8_ppgtt_insert_huge(struct
i915_address_space *vm,
enum i915_cache_level cache_level,
u32 flags)
{
- const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
+ const gen8_pte_t pte_encode = vm->pte_encode(0, cache_level, flags);
unsigned int rem = sg_dma_len(iter->sg);
u64 start = vma_res->start;
@@ -743,7 +771,7 @@ static void gen8_ppgtt_insert_entry(struct
i915_address_space *vm,
GEM_BUG_ON(pt->is_compact);
vaddr = px_vaddr(pt);
- vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
+ vaddr[gen8_pd_index(idx, 0)] = vm->pte_encode(addr, level, flags);
drm_clflush_virt_range([gen8_pd_index(idx, 0)], sizeof(*vaddr));
}
@@ -773,7 +801,7 @@ static void __xehpsdv_ppgtt_insert_entry_lm(struct
i915_address_space *vm,
}
vaddr = px_vaddr(pt);
- vaddr[gen8_pd_index(idx, 0) / 16] = gen8_pte_encode(addr, level, flags);
+ vaddr[gen8_pd_index(idx, 0) / 16] = vm->pte_encode(addr, level, flags);
}
static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm,
@@ -820,7 +848,7 @@ static int gen8_init_scratch(struct i915_address_space *vm)
pte_flags |= PTE_LM;
vm->scratch[0]->encode =
- gen8_pte_encode(px_dma(vm->scratch[0]),
+ vm->pte_encode(px_dma(vm->scratch[0]),
I915_CACHE_NONE, pte_flags);
for (i = 1; i <= vm->top; i++) {
@@ -963,7 +991,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
*/
ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
- ppgtt->vm.pte_encode =
Re: [Intel-gfx] [PATCH 3/3] drm/i915/mtl/UAPI: Disable SET_CACHING IOCTL for MTL+
On Mon, Nov 28, 2022 at 03:43:52PM +0530, Aravind Iddamsetty wrote:
From: Pallavi Mishra
Caching mode for an object shall be selected via upcoming VM_BIND
interface.
last I've heard there was no plan to support this through VM_BIND. Did
anything change? Otherwise this needs a better explanation recorded in
the cover letter.
According to e7737b67ab46 ("drm/i915/uapi: reject caching ioctls for discrete")
it seems it was already planned to extend this to all platforms.
+Daniel, +Matt Auld
Cc: Lucas De Marchi
Cc: Matt Roper
Cc: Joonas Lahtinen
Signed-off-by: Pallavi Mishra
Signed-off-by: Aravind Iddamsetty
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index d44a152ce680..aebbfe186143 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -332,6 +332,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void
*data,
if (IS_DGFX(i915))
return -ENODEV;
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+ return -EOPNOTSUPP;
Why a different return? Should this be treated similar to the IS_DGFX()
case above? It seems we are also missing an equivalent change in
i915_gem_get_caching_ioctl().
include/uapi/drm/i915_drm.h also needs to be updated with documentation
about this behavior. See the commit mentioned above.
Lucas De Marchi
+
switch (args->caching) {
case I915_CACHING_NONE:
level = I915_CACHE_NONE;
--
2.25.1
Re: [Intel-gfx] [PATCH 2/3] drm/i915/mtl: Define new PTE encode for MTL
> From: Iddamsetty, Aravind
> Sent: Monday, November 28, 2022 2:14 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas ; Roper, Matthew D
> ; Yang, Fei
> Subject: [PATCH 2/3] drm/i915/mtl: Define new PTE encode for MTL
>
> Add a separate PTE encode function for MTL. The number of PAT
> registers have increased to 16 on MTL. All 16 PAT registers are
> available for PPGTT mapped pages, but only the lower 4 are
> available for GGTT mapped pages.
>
> BSPEC: 63884
>
> Cc: Lucas De Marchi
> Cc: Matt Roper
> Co-developed-by: Fei Yang
> Signed-off-by: Fei Yang
> Signed-off-by: Aravind Iddamsetty
> ---
> drivers/gpu/drm/i915/display/intel_dpt.c | 2 +-
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 43
> drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 4 +++
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 36 ++--
> drivers/gpu/drm/i915/gt/intel_gtt.h | 13 +--
> 5 files changed, 86 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
> b/drivers/gpu/drm/i915/display/intel_dpt.c
> index ad1a37b515fb..cb8ed9bfb240 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpt.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpt.c
> @@ -298,7 +298,7 @@ intel_dpt_create(struct intel_framebuffer *fb)
> vm->vma_ops.bind_vma= dpt_bind_vma;
> vm->vma_ops.unbind_vma = dpt_unbind_vma;
>
> - vm->pte_encode = gen8_ggtt_pte_encode;
> + vm->pte_encode = vm->gt->ggtt->vm.pte_encode;
>
> dpt->obj = dpt_obj;
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> index 4daaa6f55668..4197b43150cc 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> @@ -55,6 +55,34 @@ static u64 gen8_pte_encode(dma_addr_t addr,
> return pte;
> }
>
> +static u64 mtl_pte_encode(dma_addr_t addr,
> + enum i915_cache_level level,
> + u32 flags)
> +{
> + gen8_pte_t pte = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
> +
> + if (unlikely(flags & PTE_READ_ONLY))
> + pte &= ~GEN8_PAGE_RW;
> +
> + if (flags & PTE_LM)
> + pte |= GEN12_PPGTT_PTE_LM | GEN12_PPGTT_PTE_NC;
> +
> + switch (level) {
> + case I915_CACHE_NONE:
> + pte |= GEN12_PPGTT_PTE_PAT1;
> + break;
> + case I915_CACHE_LLC:
> + case I915_CACHE_L3_LLC:
> + pte |= GEN12_PPGTT_PTE_PAT0 | GEN12_PPGTT_PTE_PAT1;
> + break;
> + case I915_CACHE_WT:
> + pte |= GEN12_PPGTT_PTE_PAT0;
> + break;
> + }
How are the PAT indices greater then 3 being handled for ppgtt?
> +
> + return pte;
> +}
> +
> static void gen8_ppgtt_notify_vgt(struct i915_ppgtt *ppgtt, bool create) {
> struct drm_i915_private *i915 = ppgtt->vm.i915; @@ -427,7 +455,7 @@
> gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
> u32 flags)
> {
> struct i915_page_directory *pd;
> - const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
> + const gen8_pte_t pte_encode = ppgtt->vm.pte_encode(0, cache_level,
> +flags);
> gen8_pte_t *vaddr;
>
> pd = i915_pd_entry(pdp, gen8_pd_index(idx, 2)); @@ -580,7 +608,7 @@
> static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
> enum i915_cache_level cache_level,
> u32 flags)
> {
> - const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
> + const gen8_pte_t pte_encode = vm->pte_encode(0, cache_level, flags);
> unsigned int rem = sg_dma_len(iter->sg);
> u64 start = vma_res->start;
>
> @@ -743,7 +771,7 @@ static void gen8_ppgtt_insert_entry(struct
> i915_address_space *vm,
> GEM_BUG_ON(pt->is_compact);
>
> vaddr = px_vaddr(pt);
> - vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
> + vaddr[gen8_pd_index(idx, 0)] = vm->pte_encode(addr, level, flags);
> drm_clflush_virt_range([gen8_pd_index(idx, 0)], sizeof(*vaddr));
> }
>
> @@ -773,7 +801,7 @@ static void __xehpsdv_ppgtt_insert_entry_lm(struct
> i915_address_space *vm,
> }
>
> vaddr = px_vaddr(pt);
> - vaddr[gen8_pd_index(idx, 0) / 16] = gen8_pte_encode(addr, level, flags);
> + vaddr[gen8_pd_index(idx, 0) / 16] = vm->pte_encode(addr, level,
> +flags);
> }
>
> static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm, @@
> -820,7 +848,7 @@ static int gen8_init_scratch(struct i915_address_space *vm)
> pte_flags |= PTE_LM;
>
> vm->scratch[0]->encode =
> - gen8_pte_encode(px_dma(vm->scratch[0]),
> + vm->pte_encode(px_dma(vm->scratch[0]),
> I915_CACHE_NONE, pte_flags);
>
> for (i = 1; i <= vm->top; i++) {
> @@ -963,7 +991,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
>*/
> ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
Re: [Intel-gfx] [RFC 11/13] cgroup/drm: Introduce weight based drm cgroup control
Hello, On Thu, Nov 24, 2022 at 02:32:25PM +, Tvrtko Ursulin wrote: > > Soft limits is a bit of misnomer and can be confused with best-effort limits > > such as memory.high. Prolly best to not use the term. > > Are you suggesting "best effort limits" or "best effort "? It > would sounds good to me if we found the right . Best effort > budget perhaps? A more conventional name would be hierarchical weighted distribution. > Also, when you mention scalability you are concerned about multiple tree > walks I have per iteration? I wasn't so much worried about that, definitely > not for the RFC, but even in general due relatively low frequency of > scanning and a good amount of less trivial cost being outside the actual > tree walks (drm client walks, GPU utilisation calculations, maybe more). But > perhaps I don't have the right idea on how big cgroups hierarchies can be > compared to number of drm clients etc. It's just a better way doing this kind of weight based scheduling. It's simpler, more scalable and easier to understand how things are working. The basic idea is pretty simple - each schedulable entity gets assigned a timestamp and whenever it consumes the target resource, its time is wound forward by the consumption amount divided by its absolute share - e.g. if cgroup A deserves 25% of the entire thing and it ran for 1s, its time is wound forward by 1s / 0.25 == 4s. There's a rbtree keyed by these timestamps and anything wanting to consume gets put on that tree and whatever is at the head of the tree is the next thing to run. Thanks. -- tejun
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dsi: fix VBT send packet port selection for dual link DSI (rev2)
== Series Details ==
Series: drm/i915/dsi: fix VBT send packet port selection for dual link DSI
(rev2)
URL : https://patchwork.freedesktop.org/series/111366/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12438_full -> Patchwork_111366v2_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (8 -> 10)
--
Additional (2): shard-rkl shard-dg1
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_111366v2_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_color@ctm-blue-to-red@pipe-a-hdmi-a-4:
- {shard-dg1}:NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/shard-dg1-17/igt@kms_color@ctm-blue-to-...@pipe-a-hdmi-a-4.html
* igt@kms_vblank@pipe-b-wait-forked-hang:
- {shard-dg1}:NOTRUN -> [SKIP][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/shard-dg1-17/igt@kms_vbl...@pipe-b-wait-forked-hang.html
Known issues
Here are the changes found in Patchwork_111366v2_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#4793])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-skl9/igt@gem_ctx_isolation@preservation...@bcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/shard-skl10/igt@gem_ctx_isolation@preservation...@bcs0.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2842])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-tglb6/igt@gem_exec_fair@basic-f...@rcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/shard-tglb3/igt@gem_exec_fair@basic-f...@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-skl: NOTRUN -> [SKIP][7] ([fdo#109271]) +104 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/shard-skl10/igt@gem_exec_fair@basic-p...@vecs0.html
* igt@gem_lmem_swapping@random-engines:
- shard-skl: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +2
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/shard-skl6/igt@gem_lmem_swapp...@random-engines.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [PASS][9] -> [SKIP][10] ([i915#4281])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-iclb8/igt@i915_pm...@dc9-dpms.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/shard-iclb3/igt@i915_pm...@dc9-dpms.html
* igt@i915_selftest@live@gt_pm:
- shard-skl: NOTRUN -> [DMESG-FAIL][11] ([i915#1886])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/shard-skl4/igt@i915_selftest@live@gt_pm.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1:
- shard-skl: NOTRUN -> [FAIL][12] ([i915#2521])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/shard-skl10/igt@kms_async_flips@alternate-sync-async-f...@pipe-c-edp-1.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-iclb: [PASS][13] -> [DMESG-FAIL][14] ([i915#5138])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-iclb5/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/shard-iclb6/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#3886]) +3
similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/shard-skl4/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_color_chamelium@ctm-limited-range:
- shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +5
similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/shard-skl10/igt@kms_color_chamel...@ctm-limited-range.html
* igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1:
- shard-skl: [PASS][17] -> [INCOMPLETE][18] ([i915#6951])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-skl4/igt@kms_cursor_crc@cursor-susp...@pipe-b-edp-1.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/shard-skl4/igt@kms_cursor_crc@cursor-susp...@pipe-b-edp-1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
- shard-skl: NOTRUN -> [FAIL][19] ([i915#2122])
[19]:
Re: [Intel-gfx] [PATCH] drm/i915/huc: always init the delayed load fence
On 11/23/2022 15:54, Daniele Ceraolo Spurio wrote:
The fence is only tracking if the HuC load is in progress or not and
doesn't distinguish between already loaded, not supported or disabled,
so we can always initialize it to completed, no matter the actual
support. We already do that for most platforms, but we skip it on
GTs that lack VCS engines (i.e. MTL root GT), so fix that. Note that the
i.e. -> e.g., there is more than just MTL root GT.
cleanup is already unconditional.
While at it, move the init/fini to helper functions.
Fixes: 02224691cb0f ("drm/i915/huc: fix leak of debug object in huc load fence on
driver unload")
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
Cc: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 47 +++---
1 file changed, 34 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 0976e9101346..5f393f8e8b2e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -211,6 +211,30 @@ void intel_huc_unregister_gsc_notifier(struct intel_huc
*huc, struct bus_type *b
huc->delayed_load.nb.notifier_call = NULL;
}
+static void delayed_huc_load_init(struct intel_huc *huc)
+{
+ /*
+* Initialize fence to be complete as this is expected to be complete
+* unless there is a delayed HuC reload in progress.
reload -> load?
+*/
+ i915_sw_fence_init(>delayed_load.fence,
+ sw_fence_dummy_notify);
+ i915_sw_fence_commit(>delayed_load.fence);
+
+ hrtimer_init(>delayed_load.timer, CLOCK_MONOTONIC,
HRTIMER_MODE_REL);
+ huc->delayed_load.timer.function = huc_delayed_load_timer_callback;
+}
+
+static void delayed_huc_load_fini(struct intel_huc *huc)
+{
+ /*
+* the fence is initialized in init_early, so we need to clean it up
+* even if HuC loading is off.
+*/
+ delayed_huc_load_complete(huc);
+ i915_sw_fence_fini(>delayed_load.fence);
+}
+
static bool vcs_supported(struct intel_gt *gt)
{
intel_engine_mask_t mask = gt->info.engine_mask;
@@ -241,6 +265,15 @@ void intel_huc_init_early(struct intel_huc *huc)
intel_uc_fw_init_early(>fw, INTEL_UC_FW_TYPE_HUC);
+ /*
+* we always init the fence as already completed, even if HuC is not
+* supported. This way we don't have to distinguish between HuC not
+* supported/disabled or already loaded, band can focus on if the load
band -> and
Looks good otherwise. So with the typos fixed:
Reviewed-by: John Harrison
+* is currently in progress (fence not complete) or not, which is what
+* we care about for stalling userspace submissions.
+*/
+ delayed_huc_load_init(huc);
+
if (!vcs_supported(gt)) {
intel_uc_fw_change_status(>fw,
INTEL_UC_FIRMWARE_NOT_SUPPORTED);
return;
@@ -255,17 +288,6 @@ void intel_huc_init_early(struct intel_huc *huc)
huc->status.mask = HUC_FW_VERIFIED;
huc->status.value = HUC_FW_VERIFIED;
}
-
- /*
-* Initialize fence to be complete as this is expected to be complete
-* unless there is a delayed HuC reload in progress.
-*/
- i915_sw_fence_init(>delayed_load.fence,
- sw_fence_dummy_notify);
- i915_sw_fence_commit(>delayed_load.fence);
-
- hrtimer_init(>delayed_load.timer, CLOCK_MONOTONIC,
HRTIMER_MODE_REL);
- huc->delayed_load.timer.function = huc_delayed_load_timer_callback;
}
#define HUC_LOAD_MODE_STRING(x) (x ? "GSC" : "legacy")
@@ -333,8 +355,7 @@ void intel_huc_fini(struct intel_huc *huc)
* the fence is initialized in init_early, so we need to clean it up
* even if HuC loading is off.
*/
- delayed_huc_load_complete(huc);
- i915_sw_fence_fini(>delayed_load.fence);
+ delayed_huc_load_fini(huc);
if (intel_uc_fw_is_loadable(>fw))
intel_uc_fw_fini(>fw);
Re: [Intel-gfx] [PATCH] drm/i915/gt: remove some limited use register access wrappers
On Wed, Nov 23, 2022 at 06:49:16PM +0200, Jani Nikula wrote:
> Remove rmw_set(), rmw_clear(), clear_register(), rmw_set_fw(), and
> rmw_clear_fw(). They're just one too many levels of abstraction for
> register access, for very specific purposes.
>
> clear_register() seems like a micro-optimization bypassing the write
> when the register is already clear, but that trick has ceased to work
> since commit 06b975d58fd6 ("drm/i915: make intel_uncore_rmw() write
> unconditionally"). Just clear the register in the most obvious way.
>
> Signed-off-by: Jani Nikula
There's also set() in intel_rc6.c that could be dropped as a follow-up.
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c| 29 +++
> drivers/gpu/drm/i915/gt/intel_reset.c | 18 -
> 2 files changed, 11 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index b5ad9caa5537..efd9d722d77f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -210,21 +210,6 @@ int intel_gt_init_hw(struct intel_gt *gt)
> return ret;
> }
>
> -static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
> -{
> - intel_uncore_rmw(uncore, reg, 0, set);
> -}
> -
> -static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
> -{
> - intel_uncore_rmw(uncore, reg, clr, 0);
> -}
> -
> -static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
> -{
> - intel_uncore_rmw(uncore, reg, 0, 0);
> -}
> -
> static void gen6_clear_engine_error_register(struct intel_engine_cs *engine)
> {
> GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
> @@ -250,14 +235,14 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
> u32 eir;
>
> if (GRAPHICS_VER(i915) != 2)
> - clear_register(uncore, PGTBL_ER);
> + intel_uncore_write(uncore, PGTBL_ER, 0);
>
> if (GRAPHICS_VER(i915) < 4)
> - clear_register(uncore, IPEIR(RENDER_RING_BASE));
> + intel_uncore_write(uncore, IPEIR(RENDER_RING_BASE), 0);
> else
> - clear_register(uncore, IPEIR_I965);
> + intel_uncore_write(uncore, IPEIR_I965, 0);
>
> - clear_register(uncore, EIR);
> + intel_uncore_write(uncore, EIR, 0);
> eir = intel_uncore_read(uncore, EIR);
> if (eir) {
> /*
> @@ -265,7 +250,7 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
>* mask them.
>*/
> drm_dbg(>i915->drm, "EIR stuck: 0x%08x, masking\n", eir);
> - rmw_set(uncore, EMR, eir);
> + intel_uncore_rmw(uncore, EMR, 0, eir);
> intel_uncore_write(uncore, GEN2_IIR,
> I915_MASTER_ERROR_INTERRUPT);
> }
> @@ -275,10 +260,10 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
> RING_FAULT_VALID, 0);
> intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG);
> } else if (GRAPHICS_VER(i915) >= 12) {
> - rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
> + intel_uncore_rmw(uncore, GEN12_RING_FAULT_REG,
> RING_FAULT_VALID, 0);
> intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
> } else if (GRAPHICS_VER(i915) >= 8) {
> - rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
> + intel_uncore_rmw(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID,
> 0);
> intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
> } else if (GRAPHICS_VER(i915) >= 6) {
> struct intel_engine_cs *engine;
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
> b/drivers/gpu/drm/i915/gt/intel_reset.c
> index 24736ebee17c..ffde89c5835a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -35,16 +35,6 @@
> /* XXX How to handle concurrent GGTT updates using tiling registers? */
> #define RESET_UNDER_STOP_MACHINE 0
>
> -static void rmw_set_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
> -{
> - intel_uncore_rmw_fw(uncore, reg, 0, set);
> -}
> -
> -static void rmw_clear_fw(struct intel_uncore *uncore, i915_reg_t reg, u32
> clr)
> -{
> - intel_uncore_rmw_fw(uncore, reg, clr, 0);
> -}
> -
> static void client_mark_guilty(struct i915_gem_context *ctx, bool banned)
> {
> struct drm_i915_file_private *file_priv = ctx->file_priv;
> @@ -212,7 +202,7 @@ static int g4x_do_reset(struct intel_gt *gt,
> int ret;
>
> /* WaVcpClkGateDisableForMediaReset:ctg,elk */
> - rmw_set_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE);
> + intel_uncore_rmw_fw(uncore, VDECCLK_GATE_D, 0,
> VCP_UNIT_CLOCK_GATE_DISABLE);
> intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
>
> pci_write_config_byte(pdev, I915_GDRST,
> @@ -234,7 +224,7 @@ static int
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: fix exiting context timeout calculation
== Series Details ==
Series: drm/i915: fix exiting context timeout calculation
URL : https://patchwork.freedesktop.org/series/111402/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12439 -> Patchwork_111402v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/index.html
Participating hosts (31 -> 35)
--
Additional (4): fi-ilk-650 fi-jsl-1 fi-cfl-8700k bat-dg1-6
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_111402v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-2:
- {bat-dg2-11}: [PASS][1] -> [FAIL][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12439/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-...@pipe-a-dp-2.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-...@pipe-a-dp-2.html
Known issues
Here are the changes found in Patchwork_111402v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-cfl-8700k: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/fi-cfl-8700k/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-cfl-8700k: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3
similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/fi-cfl-8700k/igt@gem_lmem_swapp...@basic.html
* igt@gem_mmap@basic:
- bat-dg1-6: NOTRUN -> [SKIP][5] ([i915#4083])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/bat-dg1-6/igt@gem_m...@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][6] ([i915#4079]) +1 similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/bat-dg1-6/igt@gem_render_tiled_bl...@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][7] ([i915#4077]) +2 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/bat-dg1-6/igt@gem_tiled_fence_bl...@basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-dg1-6: NOTRUN -> [SKIP][8] ([i915#7561])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-ilk-650: NOTRUN -> [SKIP][9] ([fdo#109271]) +20 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/fi-ilk-650/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rps@basic-api:
- bat-dg1-6: NOTRUN -> [SKIP][10] ([i915#6621])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/bat-dg1-6/igt@i915_pm_...@basic-api.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-6: NOTRUN -> [SKIP][11] ([i915#4215])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg1-6: NOTRUN -> [SKIP][12] ([i915#4212]) +7 similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/bat-dg1-6/igt@kms_addfb_ba...@tile-pitch-mismatch.html
* igt@kms_chamelium@dp-edid-read:
- fi-cfl-8700k: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/fi-cfl-8700k/igt@kms_chamel...@dp-edid-read.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-ilk-650: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8
similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/fi-ilk-650/igt@kms_chamel...@dp-hpd-fast.html
* igt@kms_chamelium@hdmi-crc-fast:
- bat-dg1-6: NOTRUN -> [SKIP][15] ([fdo#111827]) +8 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/bat-dg1-6/igt@kms_chamel...@hdmi-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-cfl-8700k: NOTRUN -> [SKIP][16] ([fdo#109271]) +9 similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/fi-cfl-8700k/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html
- bat-dg1-6: NOTRUN -> [SKIP][17] ([i915#4103] / [i915#4213])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111402v1/bat-dg1-6/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg1-6: NOTRUN -> [SKIP][18]
Re: [Intel-gfx] signal: break out of wait loops on kthread_stop()
Hi Eric, On Mon, Nov 28, 2022 at 7:22 PM Eric W. Biederman wrote: > > Tvrtko Ursulin writes: > > > On 19/10/2022 21:19, Jason A. Donenfeld wrote: > >> On Wed, Oct 19, 2022 at 09:09:28PM +0100, Tvrtko Ursulin wrote: > >>> Hm why is kthread_stop() after kthread_run() abuse? I don't see it in > >>> kerneldoc that it must not be used for stopping threads. > >> Because you don't want it to stop. You want to wait until it's done. If > >> you call stop right after run, it will even stop it before it even > >> begins to run. That's why you wind up sprinkling your msleeps > >> everywhere, indicating that clearly this is not meant to work that way. > > Not after kthread_run which wakes it up already. If the kerneldoc for > > kthread_stop() is correct at least... In which case I really do think > > that the yields are pointless/red herring. Perhaps they predate kthread_run > > and > > then they were even wrong. > > > >>> Yep the yields and sleeps are horrible and will go. But they are also > >>> not relevant for the topic at hand. > >> Except they very much are. The reason you need these is because you're > >> using kthread_stop() for something it's not meant to do. > > > > It is supposed to assert kthread_should_stop() which thread can look at as > > when > > to exit. Except that now it can fail to get to that controlled exit > > point. Granted that argument is moot since it implies incomplete error > > handling > > in the thread anyway. > > > > Btw there are actually two use cases in our code base. One is thread > > controls > > the exit, second is caller controls the exit. Anyway... > > > >>> Never mind, I was not looking for anything more than a suggestion on how > >>> to maybe work around it in piece as someone is dealing with the affected > >>> call sites. > >> Sultan's kthread_work idea is probably the right direction. This would > >> seem to have what you need. > > > > ... yes, it can be converted. Even though for one of the two use cases we > > need > > explicit signalling. There now isn't anything which would assert > > kthread_should_stop() without also asserting the signal, right?. Neither > > I found that the thread work API can do it. > > > > Fingers crossed we were the only "abusers" of the API. There's a quite a > > number > > of kthread_stop callers and it would be a large job to audit them all. > > > I have been out and am coming to this late. Did this get resolved? > > > I really don't expect this affected much of anything else as the code > sat in linux-next for an entire development cycle before being merged. > > But I would like to make certain problems with this change were resolved. I just checked drm-next, and it looks like the i915 people resolved their issue, and also got rid of those pesky yield()s in the process: https://cgit.freedesktop.org/drm/drm/commit/?id=6407cf533217e09dfd895e64984c3f1ee3802373 Jason
Re: [Intel-gfx] [PATCH v4 1/2] drm/i915/dg2: Introduce Wa_18018764978
On Wed, Nov 23, 2022 at 04:45:25PM -0300, Gustavo Sousa wrote: > On Wed, Nov 23, 2022 at 10:36:47AM -0800, Matt Atwood wrote: > > Wa_18018764978 applies to specific steppings of DG2 (G10 C0+, > > G11 and G12 A0+). Clean up style in function at the same time. > > > > Bspec: 66622 > > > > Signed-off-by: Matt Atwood > > Reviewed-by: Gustavo Sousa Both patches applied to drm-intel-gt-next. Thanks for the patches and review. Matt > > > --- > > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 ++- > > 2 files changed, 9 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > index 80a979e6f6be..74379d3c5a4d 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > @@ -457,6 +457,9 @@ > > #define GEN8_L3CNTLREG _MMIO(0x7034) > > #define GEN8_ERRDETBCTRL (1 << 9) > > > > +#define PSS_MODE2 _MMIO(0x703c) > > +#define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) > > + > > #define GEN7_SC_INSTDONE _MMIO(0x7100) > > #define GEN12_SC_INSTDONE_EXTRA_MMIO(0x7104) > > #define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > index 2afb4f80a954..870db5a202dd 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > @@ -771,9 +771,14 @@ static void dg2_ctx_workarounds_init(struct > > intel_engine_cs *engine, > > > > /* Wa_14014947963:dg2 */ > > if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || > > - IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > > + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > > wa_masked_field_set(wal, VF_PREEMPTION, > > PREEMPTION_VERTEX_COUNT, 0x4000); > > > > + /* Wa_18018764978:dg2 */ > > + if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) || > > + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > > + wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); > > + > > /* Wa_15010599737:dg2 */ > > wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); > > } > > -- > > 2.38.1 > > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/bios: fix a memory leak in generate_lfp_data_ptrs
== Series Details ==
Series: drm/i915/bios: fix a memory leak in generate_lfp_data_ptrs
URL : https://patchwork.freedesktop.org/series/111392/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12438_full -> Patchwork_111392v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (8 -> 10)
--
Additional (2): shard-rkl shard-dg1
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_111392v1_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_vblank@pipe-b-wait-forked-hang:
- {shard-dg1}:NOTRUN -> [SKIP][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/shard-dg1-15/igt@kms_vbl...@pipe-b-wait-forked-hang.html
Known issues
Here are the changes found in Patchwork_111392v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_eio@in-flight-suspend:
- shard-skl: [PASS][2] -> [INCOMPLETE][3] ([i915#7112])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-skl4/igt@gem_...@in-flight-suspend.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/shard-skl3/igt@gem_...@in-flight-suspend.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [PASS][4] -> [FAIL][5] ([i915#2842])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-apl2/igt@gem_exec_fair@basic-pace-s...@rcs0.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/shard-apl6/igt@gem_exec_fair@basic-pace-s...@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-skl: NOTRUN -> [SKIP][6] ([fdo#109271]) +107 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/shard-skl9/igt@gem_exec_fair@basic-p...@vecs0.html
* igt@gem_lmem_swapping@random-engines:
- shard-skl: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +2
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/shard-skl9/igt@gem_lmem_swapp...@random-engines.html
* igt@i915_pm_rps@engine-order:
- shard-apl: [PASS][8] -> [FAIL][9] ([i915#6537])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-apl6/igt@i915_pm_...@engine-order.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/shard-apl3/igt@i915_pm_...@engine-order.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-skl: NOTRUN -> [DMESG-FAIL][10] ([i915#5334])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/shard-skl1/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_pm:
- shard-skl: NOTRUN -> [DMESG-FAIL][11] ([i915#1886])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/shard-skl1/igt@i915_selftest@live@gt_pm.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1:
- shard-skl: NOTRUN -> [FAIL][12] ([i915#2521])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/shard-skl9/igt@kms_async_flips@alternate-sync-async-f...@pipe-b-edp-1.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-iclb: [PASS][13] -> [DMESG-FAIL][14] ([i915#5138])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-iclb5/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/shard-iclb7/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#3886]) +3
similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/shard-skl1/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_color_chamelium@ctm-limited-range:
- shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +5
similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/shard-skl9/igt@kms_color_chamel...@ctm-limited-range.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#180])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-apl2/igt@kms_flip@flip-vs-suspend-interrupti...@c-dp1.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/shard-apl8/igt@kms_flip@flip-vs-suspend-interrupti...@c-dp1.html
*
igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#3555]) +1 similar issue
[19]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: fix exiting context timeout calculation
== Series Details ==
Series: drm/i915: fix exiting context timeout calculation
URL : https://patchwork.freedesktop.org/series/111402/
State : warning
== Summary ==
Error: dim checkpatch failed
a049dd461775 drm/i915: fix exiting context timeout calculation
-:10: WARNING:BAD_FIXES_TAG: Please use correct Fixes: style 'Fixes: <12 chars
of sha1> ("")' - ie: 'Fixes: d7a8680ec9fb ("drm/i915: Improve long
running compute w/a for GuC submission")'
#10:
Fixes: d7a8680ec9fb21 ("drm/i915: Improve long running compute w/a for GuC
submission")
total: 0 errors, 1 warnings, 0 checks, 10 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for Align DDI_BUF_CTL Active timeouts with Bspec updates (rev2)
== Series Details ==
Series: Align DDI_BUF_CTL Active timeouts with Bspec updates (rev2)
URL : https://patchwork.freedesktop.org/series/111373/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12439 -> Patchwork_111373v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/index.html
Participating hosts (31 -> 36)
--
Additional (5): fi-jsl-1 fi-cml-u2 bat-dg1-6 fi-cfl-8700k fi-ilk-650
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_111373v2:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_lrc:
- {bat-rpls-2}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12439/bat-rpls-2/igt@i915_selftest@live@gt_lrc.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/bat-rpls-2/igt@i915_selftest@live@gt_lrc.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-2:
- {bat-dg2-11}: [PASS][3] -> [FAIL][4] +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12439/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-...@pipe-a-dp-2.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-...@pipe-a-dp-2.html
Known issues
Here are the changes found in Patchwork_111373v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@basic-hwmon:
- fi-cml-u2: NOTRUN -> [SKIP][5] ([i915#7456])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/fi-cml-u2/igt@debugfs_t...@basic-hwmon.html
* igt@gem_huc_copy@huc-copy:
- fi-cfl-8700k: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/fi-cfl-8700k/igt@gem_huc_c...@huc-copy.html
- fi-cml-u2: NOTRUN -> [SKIP][7] ([i915#2190])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/fi-cml-u2/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-cfl-8700k: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/fi-cfl-8700k/igt@gem_lmem_swapp...@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-cml-u2: NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/fi-cml-u2/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@gem_mmap@basic:
- bat-dg1-6: NOTRUN -> [SKIP][10] ([i915#4083])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/bat-dg1-6/igt@gem_m...@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][11] ([i915#4079]) +1 similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/bat-dg1-6/igt@gem_render_tiled_bl...@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][12] ([i915#4077]) +2 similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/bat-dg1-6/igt@gem_tiled_fence_bl...@basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-dg1-6: NOTRUN -> [SKIP][13] ([i915#7561])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-ilk-650: NOTRUN -> [SKIP][14] ([fdo#109271]) +20 similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/fi-ilk-650/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rps@basic-api:
- bat-dg1-6: NOTRUN -> [SKIP][15] ([i915#6621])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/bat-dg1-6/igt@i915_pm_...@basic-api.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-ilk-650: NOTRUN -> [DMESG-WARN][16] ([i915#164])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/fi-ilk-650/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-6: NOTRUN -> [SKIP][17] ([i915#4215])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg1-6: NOTRUN -> [SKIP][18] ([i915#4212]) +7 similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111373v2/bat-dg1-6/igt@kms_addfb_ba...@tile-pitch-mismatch.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-rkl-11600: NOTRUN -> [SKIP][19] ([fdo#111827])
Re: [Intel-gfx] [PATCH] drm/i915/psr: Use continuous full frame update instead of single
I found issue with this patch:
There is a time window between psr_invalidate/flush and next vblank
where atomic commit with selective update will cause full frame update
being lost due to overwriting the configuration.
I will send a new version.
On Fri, 2022-11-25 at 15:43 +0200, Jouni Högander wrote:
> Currently we are observing occasionally display flickering or
> complete
> freeze. This is narrowed down to be caused by single full frame
> update
> (SFF).
>
> SFF bit after it's written gets cleared by HW in subsequent vblank
> i.e. when the update is sent to the panel. SFF bit is required to be
> written together with partial frame update (PFU) bit. After the bit
> gets cleared by the HW psr2 man trk ctl register still contains PFU
> bit. If there is subsequent update for any reason we will end up
> having selective update/fetch configuration where start line is 0 and
> end line is 0. Also selective fetch configuration for the planes is
> not properly performed. This seems to be causing problems with some
> panels.
>
> Fix this by using continuous full frame update instead and switch to
> partial frame update only when selective update area is properly
> calculated and configured.
>
> This is also workaround for HSD 14014971508
>
> Cc: Ville Syrjälä
> Cc: José Roberto de Souza
> Cc: Mika Kahola
>
> Reported-by: Lee Shawn C
> Signed-off-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 21 ++---
> 1 file changed, 2 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 5b678916e6db..41b0718eb3a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1480,13 +1480,6 @@ static u32 man_trk_ctl_enable_bit_get(struct
> drm_i915_private *dev_priv)
> PSR2_MAN_TRK_CTL_ENABLE;
> }
>
> -static u32 man_trk_ctl_single_full_frame_bit_get(struct
> drm_i915_private *dev_priv)
> -{
> - return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >=
> 14 ?
> - ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME :
> - PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> -}
> -
> static u32 man_trk_ctl_partial_frame_bit_get(struct drm_i915_private
> *dev_priv)
> {
> return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >=
> 14 ?
> @@ -1510,7 +1503,7 @@ static void psr_force_hw_tracking_exit(struct
> intel_dp *intel_dp)
> PSR2_MAN_TRK_CTL(intel_dp-
> >psr.transcoder),
> man_trk_ctl_enable_bit_get(dev_priv) |
>
> man_trk_ctl_partial_frame_bit_get(dev_priv) |
> -
> man_trk_ctl_single_full_frame_bit_get(dev_priv));
> +
> man_trk_ctl_continuos_full_frame(dev_priv));
>
> /*
> * Display WA #0884: skl+
> @@ -1624,11 +1617,7 @@ static void psr2_man_trk_ctl_calc(struct
> intel_crtc_state *crtc_state,
> val |= man_trk_ctl_partial_frame_bit_get(dev_priv);
>
> if (full_update) {
> - /*
> - * Not applying Wa_14014971508:adlp as we do not
> support the
> - * feature that requires this workaround.
> - */
> - val |=
> man_trk_ctl_single_full_frame_bit_get(dev_priv);
> + val |= man_trk_ctl_continuos_full_frame(dev_priv);
> goto exit;
> }
>
> @@ -2306,16 +2295,10 @@ static void _psr_flush_handle(struct intel_dp
> *intel_dp)
> if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
> /* can we turn CFF off? */
> if (intel_dp->psr.busy_frontbuffer_bits == 0)
> {
> - u32 val =
> man_trk_ctl_enable_bit_get(dev_priv) |
> -
> man_trk_ctl_partial_frame_bit_get(dev_priv) |
> -
> man_trk_ctl_single_full_frame_bit_get(dev_priv);
> -
> /*
> * turn continuous full frame off and
> do a single
> * full frame
> */
> - intel_de_write(dev_priv,
> PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
> - val);
> intel_de_write(dev_priv,
> CURSURFLIVE(intel_dp->psr.pipe), 0);
> intel_dp-
> >psr.psr2_sel_fetch_cff_enabled = false;
> }
[Intel-gfx] ✓ Fi.CI.IGT: success for Add DSC fractional bpp support
== Series Details == Series: Add DSC fractional bpp support URL : https://patchwork.freedesktop.org/series/111391/ State : success == Summary == CI Bug Log - changes from CI_DRM_12438_full -> Patchwork_111391v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (8 -> 9) -- Additional (1): shard-rkl Known issues Here are the changes found in Patchwork_111391v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_fair@basic-pace@vecs0: - shard-skl: NOTRUN -> [SKIP][1] ([fdo#109271]) +105 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/shard-skl6/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][2] -> [SKIP][3] ([i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-tglb5/igt@gem_huc_c...@huc-copy.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/shard-tglb7/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@random-engines: - shard-skl: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +2 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/shard-skl6/igt@gem_lmem_swapp...@random-engines.html * igt@gen9_exec_parse@allowed-all: - shard-skl: [PASS][5] -> [DMESG-WARN][6] ([i915#5566] / [i915#716]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-skl10/igt@gen9_exec_pa...@allowed-all.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/shard-skl10/igt@gen9_exec_pa...@allowed-all.html * igt@i915_selftest@live@gt_pm: - shard-skl: NOTRUN -> [DMESG-FAIL][7] ([i915#1886]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/shard-skl1/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@hangcheck: - shard-tglb: [PASS][8] -> [DMESG-WARN][9] ([i915#5591]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-tglb1/igt@i915_selftest@l...@hangcheck.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/shard-tglb5/igt@i915_selftest@l...@hangcheck.html * igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1: - shard-skl: NOTRUN -> [FAIL][10] ([i915#2521]) +2 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/shard-skl6/igt@kms_async_flips@alternate-sync-async-f...@pipe-b-edp-1.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip: - shard-iclb: [PASS][11] -> [DMESG-FAIL][12] ([i915#5138]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-iclb5/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/shard-iclb5/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs: - shard-skl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#3886]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/shard-skl1/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html * igt@kms_color_chamelium@ctm-limited-range: - shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +5 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/shard-skl6/igt@kms_color_chamel...@ctm-limited-range.html * igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([i915#6951]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-skl4/igt@kms_cursor_crc@cursor-susp...@pipe-b-edp-1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/shard-skl1/igt@kms_cursor_crc@cursor-susp...@pipe-b-edp-1.html * igt@kms_cursor_legacy@cursor-vs-flip@legacy: - shard-iclb: [PASS][17] -> [FAIL][18] ([i915#5072]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-iclb7/igt@kms_cursor_legacy@cursor-vs-f...@legacy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/shard-iclb7/igt@kms_cursor_legacy@cursor-vs-f...@legacy.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#79]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-edp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-edp1.html * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1: - shard-skl: NOTRUN -> [FAIL][21] ([i915#2122]) [21]:
[Intel-gfx] [PATCH] drm/i915: fix exiting context timeout calculation
In case context is exiting preempt_timeout_ms is used for timeout,
but since introduction of DRM_I915_PREEMPT_TIMEOUT_COMPUTE it increases
to 7.5 seconds. Heartbeat occurs earlier but it is still 2.5s.
Fixes: d7a8680ec9fb21 ("drm/i915: Improve long running compute w/a for GuC
submission")
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2410
Signed-off-by: Andrzej Hajda
---
Hi all,
I am not sure what is expected solution here, and if my patch does not
actually reverts intentions of patch d7a8680ec9fb21. Feel free to propose
something better.
Other alternative would be to increase t/o in IGT tests, but I am not sure
if this is good direction.
Regards
Andrzej
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 49a8f10d76c77b..cd9e00f947 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1248,6 +1248,10 @@ static unsigned long active_preempt_timeout(struct
intel_engine_cs *engine,
/* Force a fast reset for terminated contexts (ignoring sysfs!) */
if (unlikely(intel_context_is_banned(rq->context) || bad_request(rq)))
return INTEL_CONTEXT_BANNED_PREEMPT_TIMEOUT_MS;
+ else if (unlikely(intel_context_is_exiting(rq->context)))
+ return min_t(typeof(unsigned long),
+READ_ONCE(engine->props.preempt_timeout_ms),
+CONFIG_DRM_I915_PREEMPT_TIMEOUT);
return READ_ONCE(engine->props.preempt_timeout_ms);
}
--
2.34.1
Re: [Intel-gfx] [PATCH] drm/i915/huc: fix leak of debug object in huc load fence on driver unload
On 11/28/2022 5:08 AM, Ville Syrjälä wrote: On Mon, Nov 28, 2022 at 01:10:58AM -0800, Ceraolo Spurio, Daniele wrote: On 11/25/2022 5:54 AM, Ville Syrjälä wrote: On Thu, Nov 10, 2022 at 04:56:51PM -0800, Daniele Ceraolo Spurio wrote: The fence is always initialized in huc_init_early, but the cleanup in huc_fini is only being run if HuC is enabled. This causes a leaking of the debug object when HuC is disabled/not supported, which can in turn trigger a warning if we try to register a new debug offset at the same address on driver reload. To fix the issue, make sure to always run the cleanup code. This oopsing in ci now. Somehow the patchwork run did not hit that oops. Can you point me to the oops log? I opened a few recent runs at random but I wasn't able to find it. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html Thanks, it's indeed the same issue (and I've just confirmed that the pre-merge result for the fix do mention that this test is moving from incomplete to pass). From just a visual inspection I thought the problem would only affect MTL, which does have HuC but only on one of the 2 GTs, but it looks like this impacts also platforms without HuC at all (as long as they also have no VCS engines). I'll try to get the fix reviewed and merged ASAP. Thanks, Daniele
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/mtl: Define MOCS and PAT tables for MTL
== Series Details == Series: series starting with [1/3] drm/i915/mtl: Define MOCS and PAT tables for MTL URL : https://patchwork.freedesktop.org/series/111390/ State : success == Summary == CI Bug Log - changes from CI_DRM_12438_full -> Patchwork_111390v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (8 -> 8) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_111390v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@parallel: - shard-iclb: [PASS][1] -> [SKIP][2] ([i915#4525]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-iclb1/igt@gem_exec_balan...@parallel.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/shard-iclb8/igt@gem_exec_balan...@parallel.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][3] -> [FAIL][4] ([i915#2842]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-tglb8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/shard-tglb7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-skl: NOTRUN -> [SKIP][5] ([fdo#109271]) +106 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/shard-skl10/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_lmem_swapping@random-engines: - shard-skl: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/shard-skl7/igt@gem_lmem_swapp...@random-engines.html * igt@gen9_exec_parse@allowed-single: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#5566] / [i915#716]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-apl1/igt@gen9_exec_pa...@allowed-single.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/shard-apl7/igt@gen9_exec_pa...@allowed-single.html * igt@i915_selftest@live@gt_pm: - shard-skl: NOTRUN -> [DMESG-FAIL][9] ([i915#1886]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/shard-skl6/igt@i915_selftest@live@gt_pm.html * igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1: - shard-skl: NOTRUN -> [FAIL][10] ([i915#2521]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/shard-skl10/igt@kms_async_flips@alternate-sync-async-f...@pipe-c-edp-1.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip: - shard-iclb: [PASS][11] -> [DMESG-FAIL][12] ([i915#5138]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-iclb5/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/shard-iclb7/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs: - shard-skl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#3886]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/shard-skl6/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html * igt@kms_color_chamelium@ctm-limited-range: - shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +5 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/shard-skl10/igt@kms_color_chamel...@ctm-limited-range.html * igt@kms_cursor_legacy@flip-vs-cursor@varying-size: - shard-iclb: [PASS][15] -> [FAIL][16] ([i915#2346]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-iclb6/igt@kms_cursor_legacy@flip-vs-cur...@varying-size.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cur...@varying-size.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#79]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-edp1.html * igt@kms_flip@flip-vs-suspend@b-edp1: - shard-skl: [PASS][19] -> [INCOMPLETE][20] ([i915#4839]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/shard-skl10/igt@kms_flip@flip-vs-susp...@b-edp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/shard-skl3/igt@kms_flip@flip-vs-susp...@b-edp1.html * igt@kms_flip@plain-flip-fb-recreate@c-edp1: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#2122]) +1 similar issue [21]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsi: fix VBT send packet port selection for dual link DSI (rev2)
== Series Details ==
Series: drm/i915/dsi: fix VBT send packet port selection for dual link DSI
(rev2)
URL : https://patchwork.freedesktop.org/series/111366/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12438 -> Patchwork_111366v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/index.html
Participating hosts (31 -> 32)
--
Additional (2): fi-ivb-3770 fi-pnv-d510
Missing(1): bat-adls-5
Known issues
Here are the changes found in Patchwork_111366v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-pnv-d510:NOTRUN -> [INCOMPLETE][1] ([i915#7605])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/fi-pnv-d510/igt@core_hotunp...@unbind-rebind.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [PASS][2] -> [INCOMPLETE][3] ([i915#4817])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-ivb-3770:NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +8
similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/fi-ivb-3770/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_psr@cursor_plane_move:
- fi-ivb-3770:NOTRUN -> [SKIP][5] ([fdo#109271]) +18 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/fi-ivb-3770/igt@kms_psr@cursor_plane_move.html
* igt@kms_psr@primary_page_flip:
- fi-pnv-d510:NOTRUN -> [SKIP][6] ([fdo#109271]) +38 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/fi-pnv-d510/igt@kms_psr@primary_page_flip.html
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][7] ([i915#4312])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/fi-pnv-d510/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}: [DMESG-WARN][8] ([i915#2867]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@hugepages:
- {bat-rpls-2}: [DMESG-WARN][10] ([i915#5278]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/bat-rpls-2/igt@i915_selftest@l...@hugepages.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/bat-rpls-2/igt@i915_selftest@l...@hugepages.html
* igt@i915_selftest@live@mman:
- fi-rkl-guc: [TIMEOUT][12] ([i915#6794]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/fi-rkl-guc/igt@i915_selftest@l...@mman.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/fi-rkl-guc/igt@i915_selftest@l...@mman.html
* igt@i915_selftest@live@workarounds:
- {bat-rpls-2}: [DMESG-FAIL][14] -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/bat-rpls-2/igt@i915_selftest@l...@workarounds.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/bat-rpls-2/igt@i915_selftest@l...@workarounds.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka: [FAIL][16] ([i915#6298]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-3:
- {bat-dg2-9}:[FAIL][18] ([fdo#103375]) -> [PASS][19] +1 similar
issue
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-dp-3.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111366v2/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-dp-3.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/bios: fix a memory leak in generate_lfp_data_ptrs
== Series Details ==
Series: drm/i915/bios: fix a memory leak in generate_lfp_data_ptrs
URL : https://patchwork.freedesktop.org/series/111392/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12438 -> Patchwork_111392v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/index.html
Participating hosts (31 -> 31)
--
Additional (1): fi-pnv-d510
Missing(1): bat-adls-5
Known issues
Here are the changes found in Patchwork_111392v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-pnv-d510:NOTRUN -> [INCOMPLETE][1] ([i915#7605])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/fi-pnv-d510/igt@core_hotunp...@unbind-rebind.html
* igt@kms_psr@primary_page_flip:
- fi-pnv-d510:NOTRUN -> [SKIP][2] ([fdo#109271]) +38 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/fi-pnv-d510/igt@kms_psr@primary_page_flip.html
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][3] ([i915#4312])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/fi-pnv-d510/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}: [DMESG-WARN][4] ([i915#2867]) -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@hugepages:
- {bat-rpls-2}: [DMESG-WARN][6] ([i915#5278]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/bat-rpls-2/igt@i915_selftest@l...@hugepages.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/bat-rpls-2/igt@i915_selftest@l...@hugepages.html
* igt@i915_selftest@live@mman:
- fi-rkl-guc: [TIMEOUT][8] ([i915#6794]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/fi-rkl-guc/igt@i915_selftest@l...@mman.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/fi-rkl-guc/igt@i915_selftest@l...@mman.html
* igt@i915_selftest@live@slpc:
- {bat-adln-1}: [DMESG-FAIL][10] ([i915#6997]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/bat-adln-1/igt@i915_selftest@l...@slpc.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/bat-adln-1/igt@i915_selftest@l...@slpc.html
* igt@i915_selftest@live@workarounds:
- {bat-rpls-2}: [DMESG-FAIL][12] -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/bat-rpls-2/igt@i915_selftest@l...@workarounds.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/bat-rpls-2/igt@i915_selftest@l...@workarounds.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka: [FAIL][14] ([i915#6298]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-3:
- {bat-dg2-9}:[FAIL][16] ([fdo#103375]) -> [PASS][17] +1 similar
issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-dp-3.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111392v1/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-dp-3.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5278]: https://gitlab.freedesktop.org/drm/intel/issues/5278
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
[i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7346]: https://gitlab.freedesktop.org/drm/intel/issues/7346
[i915#7554]: https://gitlab.freedesktop.org/drm/intel/issues/7554
[i915#7605]: https://gitlab.freedesktop.org/drm/intel/issues/7605
Build changes
-
* Linux:
Re: [Intel-gfx] [PATCH] drm/i915/huc: fix leak of debug object in huc load fence on driver unload
On Mon, Nov 28, 2022 at 01:10:58AM -0800, Ceraolo Spurio, Daniele wrote: > > > On 11/25/2022 5:54 AM, Ville Syrjälä wrote: > > On Thu, Nov 10, 2022 at 04:56:51PM -0800, Daniele Ceraolo Spurio wrote: > >> The fence is always initialized in huc_init_early, but the cleanup in > >> huc_fini is only being run if HuC is enabled. This causes a leaking of > >> the debug object when HuC is disabled/not supported, which can in turn > >> trigger a warning if we try to register a new debug offset at the same > >> address on driver reload. > >> > >> To fix the issue, make sure to always run the cleanup code. > > This oopsing in ci now. Somehow the patchwork run did not > > hit that oops. > > Can you point me to the oops log? I opened a few recent runs at random > but I wasn't able to find it. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12425/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html -- Ville Syrjälä Intel
[Intel-gfx] ✓ Fi.CI.BAT: success for Add DSC fractional bpp support
== Series Details ==
Series: Add DSC fractional bpp support
URL : https://patchwork.freedesktop.org/series/111391/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12438 -> Patchwork_111391v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/index.html
Participating hosts (31 -> 30)
--
Additional (1): fi-pnv-d510
Missing(2): bat-adls-5 bat-dg1-6
Known issues
Here are the changes found in Patchwork_111391v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-pnv-d510:NOTRUN -> [INCOMPLETE][1] ([i915#7605])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/fi-pnv-d510/igt@core_hotunp...@unbind-rebind.html
* igt@i915_selftest@live@gt_mocs:
- fi-rkl-guc: [PASS][2] -> [INCOMPLETE][3] ([i915#4983])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/fi-rkl-guc/igt@i915_selftest@live@gt_mocs.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/fi-rkl-guc/igt@i915_selftest@live@gt_mocs.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [PASS][4] -> [INCOMPLETE][5] ([i915#4817])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_psr@primary_page_flip:
- fi-pnv-d510:NOTRUN -> [SKIP][6] ([fdo#109271]) +38 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/fi-pnv-d510/igt@kms_psr@primary_page_flip.html
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][7] ([i915#4312])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/fi-pnv-d510/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}: [DMESG-WARN][8] ([i915#2867]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@hugepages:
- {bat-rpls-2}: [DMESG-WARN][10] ([i915#5278]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/bat-rpls-2/igt@i915_selftest@l...@hugepages.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/bat-rpls-2/igt@i915_selftest@l...@hugepages.html
* igt@i915_selftest@live@slpc:
- {bat-rpls-1}: [DMESG-FAIL][12] ([i915#6367]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/bat-rpls-1/igt@i915_selftest@l...@slpc.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html
* igt@i915_selftest@live@workarounds:
- {bat-rpls-2}: [DMESG-FAIL][14] -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/bat-rpls-2/igt@i915_selftest@l...@workarounds.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/bat-rpls-2/igt@i915_selftest@l...@workarounds.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka: [FAIL][16] ([i915#6298]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-3:
- {bat-dg2-9}:[FAIL][18] ([fdo#103375]) -> [PASS][19] +1 similar
issue
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-dp-3.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v1/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-dp-3.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]:
[Intel-gfx] ✗ Fi.CI.DOCS: warning for Add DSC fractional bpp support
== Series Details == Series: Add DSC fractional bpp support URL : https://patchwork.freedesktop.org/series/111391/ State : warning == Summary == Error: make htmldocs had i915 warnings ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead ./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC fractional bpp support
== Series Details == Series: Add DSC fractional bpp support URL : https://patchwork.freedesktop.org/series/111391/ State : warning == Summary == Error: dim checkpatch failed d0e4e48ec58b drm/i915/dp: Check if force dsc bpc <= max requested bpc 22a420e3ce87 drm/display/dp: Add helper function to get DSC bpp prescision 3fc2ad9da8a7 drm/i915/dp: Rename helpers to get DSC max pipe bpp and max output bpp 39f231091e2e drm/i915/dp: Get optimal link config to have best compressed bpp 20e1583a0404 drm/i915/display: Store compressed bpp in U6.4 format -:180: WARNING:LONG_LINE: line length of 113 exceeds 100 columns #180: FILE: drivers/gpu/drm/i915/display/intel_dp.c:1849: + dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp)), total: 0 errors, 1 warnings, 0 checks, 160 lines checked b22eb684f80e drm/i915/display: Consider fractional vdsc bpp while computing m_n values 5ef5ed8b2b9b drm/i915/audio : Consider fractional vdsc bpp while computing tu_data 32179ab95935 drm/i915/dsc/mtl: Add support for fractional bpp 97ef0109f0b1 drm/i915/dp: Iterate over output bpp with fractional step size d0e95b095118 drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp 315f64374095 drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/mtl: Define MOCS and PAT tables for MTL
== Series Details ==
Series: series starting with [1/3] drm/i915/mtl: Define MOCS and PAT tables for
MTL
URL : https://patchwork.freedesktop.org/series/111390/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12438 -> Patchwork_111390v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/index.html
Participating hosts (31 -> 31)
--
Additional (1): fi-pnv-d510
Missing(1): bat-adls-5
Known issues
Here are the changes found in Patchwork_111390v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-pnv-d510:NOTRUN -> [INCOMPLETE][1] ([i915#7605])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/fi-pnv-d510/igt@core_hotunp...@unbind-rebind.html
* igt@i915_selftest@live@requests:
- bat-adlp-4: [PASS][2] -> [INCOMPLETE][3] ([i915#4983] /
[i915#6257])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/bat-adlp-4/igt@i915_selftest@l...@requests.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/bat-adlp-4/igt@i915_selftest@l...@requests.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [PASS][4] -> [INCOMPLETE][5] ([i915#4817])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_psr@primary_page_flip:
- fi-pnv-d510:NOTRUN -> [SKIP][6] ([fdo#109271]) +38 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/fi-pnv-d510/igt@kms_psr@primary_page_flip.html
* igt@runner@aborted:
- bat-adlp-4: NOTRUN -> [FAIL][7] ([i915#4312])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/bat-adlp-4/igt@run...@aborted.html
- fi-pnv-d510:NOTRUN -> [FAIL][8] ([i915#4312])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/fi-pnv-d510/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@mman:
- fi-rkl-guc: [TIMEOUT][9] ([i915#6794]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/fi-rkl-guc/igt@i915_selftest@l...@mman.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/fi-rkl-guc/igt@i915_selftest@l...@mman.html
* igt@i915_selftest@live@workarounds:
- {bat-rpls-2}: [DMESG-FAIL][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/bat-rpls-2/igt@i915_selftest@l...@workarounds.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/bat-rpls-2/igt@i915_selftest@l...@workarounds.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka: [FAIL][13] ([i915#6298]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-3:
- {bat-dg2-9}:[FAIL][15] ([fdo#103375]) -> [PASS][16] +1 similar
issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12438/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-dp-3.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111390v1/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-dp-3.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
[i915#7077]: https://gitlab.freedesktop.org/drm/intel/issues/7077
[i915#7605]: https://gitlab.freedesktop.org/drm/intel/issues/7605
Build changes
-
* Linux: CI_DRM_12438 -> Patchwork_111390v1
CI-20190529: 20190529
CI_DRM_12438: 26363b95074fe20d6a4e723ae24cf566f6878751 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7072: 69ba7163475925cdc69aebbdfa0e87453ae165c7 @
Re: [Intel-gfx] [PATCH 2/2] drm/i915/ddi: Add missing wait-for-active for HDMI aligning with bspec updates
On Sun, Nov 27, 2022 at 10:52:32AM +0530, Ankit Nautiyal wrote: > After enabling DDI_BUF_CTL, wait for DDI_BUF_CTL to be active. > Bspec:4232,53339,49191,54145 > > Signed-off-by: Ankit Nautiyal Looks ok to me. On the series: Reviewed-by: Imre Deak > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index 9e16db920bf2..13bf0142627b 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -2944,6 +2944,8 @@ static void intel_enable_ddi_hdmi(struct > intel_atomic_state *state, > } > intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); > > + intel_wait_ddi_buf_active(dev_priv, port); > + > intel_audio_codec_enable(encoder, crtc_state, conn_state); > } > > -- > 2.25.1 >
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/mtl: Define MOCS and PAT tables for MTL
== Series Details == Series: series starting with [1/3] drm/i915/mtl: Define MOCS and PAT tables for MTL URL : https://patchwork.freedesktop.org/series/111390/ State : warning == Summary == Error: dim checkpatch failed 3a4cce54c504 drm/i915/mtl: Define MOCS and PAT tables for MTL 42fb2a23d315 drm/i915/mtl: Define new PTE encode for MTL -:155: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #155: FILE: drivers/gpu/drm/i915/gt/intel_ggtt.c:246: + GEM_BUG_ON(addr & ~GEN12_GGTT_PTE_ADDR_MASK); total: 0 errors, 1 warnings, 0 checks, 182 lines checked 4135cd8c532d drm/i915/mtl/UAPI: Disable SET_CACHING IOCTL for MTL+
Re: [Intel-gfx] [PATCH v3 3/3] drm/i915/selftests: Add hwmon support in libpower for dgfx
On 11/22/2022 8:10 AM, Dixit, Ashutosh wrote:
On Sun, 20 Nov 2022 23:29:46 -0800, Riana Tauro wrote:
diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c
b/drivers/gpu/drm/i915/gt/selftest_rc6.c
index 15b84c428f66..845058ed83ed 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
@@ -61,9 +61,9 @@ int live_rc6_manual(void *arg)
res[0] = rc6_residency(rc6);
dt = ktime_get();
- rc0_power = libpower_get_energy_uJ();
+ rc0_power = libpower_get_energy_uJ(gt->i915);
msleep(250);
- rc0_power = libpower_get_energy_uJ() - rc0_power;
+ rc0_power = libpower_get_energy_uJ(gt->i915) - rc0_power;
dt = ktime_sub(ktime_get(), dt);
res[1] = rc6_residency(rc6);
if ((res[1] - res[0]) >> 10) {
@@ -89,9 +89,9 @@ int live_rc6_manual(void *arg)
res[0] = rc6_residency(rc6);
intel_uncore_forcewake_flush(rc6_to_uncore(rc6), FORCEWAKE_ALL);
dt = ktime_get();
- rc6_power = libpower_get_energy_uJ();
+ rc6_power = libpower_get_energy_uJ(gt->i915);
msleep(100);
- rc6_power = libpower_get_energy_uJ() - rc6_power;
+ rc6_power = libpower_get_energy_uJ(gt->i915) - rc6_power;
So:
* arg for live_rps_power and live_rc6_manual is gt
* freq's are per gt
* rc6 residency is per gt
But the power/energy we are using is per device (gt->i915)? And we expect
device level power to be low when only one gt might be in rc6?
Shouldn't all these functions be per gt? Specially when we might have
multiple gt's soon.
Or if per gt functions don't make in all cases have both device and gt
level functions?
i915 hwmon provides both gt and device/package/card level energy but iGFX
till now reads a MSR which does not need gt or i915. So per gt I think
should work for now.
Will modify to return per-gt values if present else
the default device level energy.
dt = ktime_sub(ktime_get(), dt);
res[1] = rc6_residency(rc6);
if (res[1] == res[0]) {
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c
b/drivers/gpu/drm/i915/gt/selftest_rps.c
index b8b0b0c7617e..6732aa7d4792 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -1090,38 +1090,38 @@ int live_rps_interrupt(void *arg)
return err;
}
-static u64 __measure_power(int duration_ms)
+static u64 __measure_power(struct intel_gt *gt, int duration_ms)
{
u64 dE, dt;
dt = ktime_get();
- dE = libpower_get_energy_uJ();
+ dE = libpower_get_energy_uJ(gt->i915);
usleep_range(1000 * duration_ms, 2000 * duration_ms);
- dE = libpower_get_energy_uJ() - dE;
+ dE = libpower_get_energy_uJ(gt->i915) - dE;
dt = ktime_get() - dt;
return div64_u64(1000 * 1000 * dE, dt);
}
-static u64 measure_power(struct intel_rps *rps, int *freq)
+static u64 measure_power(struct intel_gt *gt, int *freq)
{
u64 x[5];
int i;
for (i = 0; i < 5; i++)
- x[i] = __measure_power(5);
+ x[i] = __measure_power(gt, 5);
- *freq = (*freq + intel_rps_read_actual_frequency(rps)) / 2;
+ *freq = (*freq + intel_rps_read_actual_frequency(>rps)) / 2;
/* A simple triangle filter for better result stability */
sort(x, 5, sizeof(*x), cmp_u64, NULL);
return div_u64(x[1] + 2 * x[2] + x[3], 4);
}
-static u64 measure_power_at(struct intel_rps *rps, int *freq)
+static u64 measure_power_at(struct intel_gt *gt, int *freq)
{
- *freq = rps_set_check(rps, *freq);
- return measure_power(rps, freq);
+ *freq = rps_set_check(>rps, *freq);
Hmm looks like this whole live_rps_power stuff is only for host turbo, not
slpc. Anyway that's a future patch.
live_slpc_power is present in selftest_slpc.c.
+ return measure_power(gt, freq);
}
int live_rps_power(void *arg)
@@ -1187,10 +1187,10 @@ int live_rps_power(void *arg)
}
max.freq = rps->max_freq;
- max.power = measure_power_at(rps, );
+ max.power = measure_power_at(gt, );
min.freq = rps->min_freq;
- min.power = measure_power_at(rps, );
+ min.power = measure_power_at(gt, );
igt_spinner_end();
st_engine_heartbeat_enable(engine);
diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c
b/drivers/gpu/drm/i915/gt/selftest_slpc.c
index fc1cdda82ec6..c4b14f2b268c 100644
--- a/drivers/gpu/drm/i915/gt/selftest_slpc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_slpc.c
@@ -78,7 +78,7 @@ static u64 measure_power_at_freq(struct intel_gt *gt, int
*freq, u64 *power)
if (err)
return err;
*freq = intel_rps_read_actual_frequency(>rps);
- *power = measure_power(>rps, freq);
+ *power = measure_power(gt, freq);
return err;
}
Changes for slpc present here.
diff --git a/drivers/gpu/drm/i915/selftests/libpower.c
[Intel-gfx] [PATCH] drm/i915/dsi: fix VBT send packet port selection for dual link DSI
intel_dsi->ports contains bitmask of enabled ports and correspondingly
logic for selecting port for VBT packet sending must use port specific
bitmask when deciding appropriate port.
Fixes: 08c59dde71b7 ("drm/i915/dsi: fix VBT send packet port selection for
ICL+")
Cc: sta...@vger.kernel.org
Signed-off-by: Mikko Kovanen
---
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index 75e8cc4337c9..fce69fa446d5 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -137,9 +137,9 @@ static enum port intel_dsi_seq_port_to_port(struct
intel_dsi *intel_dsi,
return ffs(intel_dsi->ports) - 1;
if (seq_port) {
- if (intel_dsi->ports & PORT_B)
+ if (intel_dsi->ports & BIT(PORT_B))
return PORT_B;
- else if (intel_dsi->ports & PORT_C)
+ else if (intel_dsi->ports & BIT(PORT_C))
return PORT_C;
}
--
2.34.1
[Intel-gfx] [PATCH] drm/i915/bios: fix a memory leak in generate_lfp_data_ptrs
When (size != 0 || ptrs->lvds_ entries != 3), the program tries to
free() the ptrs. However, the ptrs is not created by calling kzmalloc(),
but is obtained by pointer offset operation.
This may lead to memory leaks or undefined behavior.
Fix this by replacing the arguments of kfree() with ptrs_block.
Fixes: a87d0a847607 ("drm/i915/bios: Generate LFP data table pointers if the
VBT lacks them")
Signed-off-by: Xia Fukun
---
drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 28bdb936cd1f..edbdb949b6ce 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -414,7 +414,7 @@ static void *generate_lfp_data_ptrs(struct drm_i915_private
*i915,
ptrs->lvds_entries++;
if (size != 0 || ptrs->lvds_entries != 3) {
- kfree(ptrs);
+ kfree(ptrs_block);
return NULL;
}
--
2.17.1
[Intel-gfx] [PATCH 11/11] drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs
From: Swati Sharma
If force_dsc_fractional_bpp_en is set through debugfs allow DSC iff
compressed bpp is fractional. Continue if we computed compressed bpp is
computed as integer.
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 379dd683be0a..5ed7471247ad 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1591,6 +1591,9 @@ static int dsc_compute_compressed_bpp(struct intel_dp
*intel_dp,
for (compressed_bppx16 = dsc_max_bppx16;
compressed_bppx16 >= dsc_min_bppx16;
compressed_bppx16 -= bppx16_step) {
+ if (intel_dp->force_dsc_fractional_bpp_en &&
+ (compressed_bppx16 % 16 == 0))
+ continue;
ret = dsc_compute_link_config(intel_dp,
pipe_config,
limits,
@@ -1709,6 +1712,9 @@ static int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
} else {
u8 dsc_dp_slice_count;
+ if (intel_dp->force_dsc_fractional_bpp_en)
+ drm_dbg_kms(_priv->drm,
+ "Forcing DSC fractional bpp\n");
if (intel_dp->force_dsc_bpc &&
intel_dp->force_dsc_bpc <= conn_state->max_requested_bpc)
ret = dsc_compute_compressed_bpp(intel_dp, pipe_config,
--
2.25.1
[Intel-gfx] [PATCH 08/11] drm/i915/dsc/mtl: Add support for fractional bpp
From: Vandita Kulkarni
Consider the fractional bpp while reading the qp values.
Signed-off-by: Vandita Kulkarni
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_qp_tables.c | 3 ---
drivers/gpu/drm/i915/display/intel_vdsc.c | 12 +---
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c
b/drivers/gpu/drm/i915/display/intel_qp_tables.c
index 6f8e4ec5c0fb..a0094287dc81 100644
--- a/drivers/gpu/drm/i915/display/intel_qp_tables.c
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c
@@ -21,9 +21,6 @@
* These qp tables are as per the C model
* and it has the rows pointing to bpps which increment
* in steps of 0.5
- * We do not support fractional bpps as of today,
- * hence we would skip the fractional bpps during
- * our references for qp calclulations.
*/
static const u8
rc_range_minqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 73f9ea266533..d24ca8828a1d 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -381,6 +381,7 @@ calculate_rc_params(struct rc_parameters *rc,
{
int bpc = vdsc_cfg->bits_per_component;
int bpp = vdsc_cfg->bits_per_pixel >> 4;
+ int fractional_bits = vdsc_cfg->bits_per_pixel & 0xf;
static const s8 ofs_und6[] = {
0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
};
@@ -421,7 +422,13 @@ calculate_rc_params(struct rc_parameters *rc,
rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
- bpp_i = (2 * (bpp - 6));
+ /*
+* QP table rows have values in increment of 0.5.
+* So 6.0 bpp to 6.4375 will have index 0, 6.5 to 6.9375 will have
index 1,
+* and so on.
+* 0.5 represented as 0x8 in U6.4 format.
+*/
+ bpp_i = ((bpp - 6) + (fractional_bits < 0x8 ? 0 : 1));
for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
/* Read range_minqp and range_max_qp from qp tables */
rc->rc_range_params[buf_i].range_min_qp =
@@ -469,8 +476,7 @@ int intel_dsc_compute_params(struct intel_crtc_state
*pipe_config)
/* Gen 11 does not support VBR */
vdsc_cfg->vbr_enable = false;
- /* Gen 11 only supports integral values of bpp */
- vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
+ vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp;
vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
--
2.25.1
[Intel-gfx] [PATCH 09/11] drm/i915/dp: Iterate over output bpp with fractional step size
This patch adds support to iterate over compressed output bpp as per the
fractional step, supported by DP sink.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 45 +++--
1 file changed, 27 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 7ad39ddadae6..379dd683be0a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1461,10 +1461,11 @@ static int intel_dp_dsc_compute_params(struct
intel_encoder *encoder,
return drm_dsc_compute_rc_parameters(vdsc_cfg);
}
-static bool is_dsc_bw_sufficient(int link_rate, int lane_count, int
compressed_bpp,
+static bool is_dsc_bw_sufficient(int link_rate, int lane_count, int
compressed_bppx16,
const struct drm_display_mode *adjusted_mode)
{
- int mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
compressed_bpp);
+ int mode_rate =
DIV_ROUND_UP(intel_dp_link_required(adjusted_mode->crtc_clock,
+ compressed_bppx16),
16);
int link_avail = intel_dp_max_data_rate(link_rate, lane_count);
return mode_rate <= link_avail;
@@ -1474,7 +1475,7 @@ static int dsc_compute_link_config(struct intel_dp
*intel_dp,
struct intel_crtc_state *pipe_config,
struct link_config_limits *limits,
int pipe_bpp,
- u16 compressed_bpp)
+ u16 compressed_bppx16)
{
const struct drm_display_mode *adjusted_mode =
_config->hw.adjusted_mode;
@@ -1498,11 +1499,11 @@ static int dsc_compute_link_config(struct intel_dp
*intel_dp,
adjusted_mode->crtc_hdisplay,
pipe_config->bigjoiner_pipes,
pipe_bpp);
- if (compressed_bpp > dsc_max_bpp)
+ if (compressed_bppx16 > dsc_max_bpp << 16)
continue;
if (!is_dsc_bw_sufficient(link_rate, lane_count,
- compressed_bpp,
adjusted_mode))
+ compressed_bppx16,
adjusted_mode))
continue;
pipe_config->lane_count = lane_count;
@@ -1565,30 +1566,38 @@ static int dsc_compute_compressed_bpp(struct intel_dp
*intel_dp,
int pipe_bpp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u16 compressed_bpp;
- int dsc_min_bpp, dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
+ u16 compressed_bppx16;
+ int dsc_min_bppx16, dsc_src_max_bppx16, dsc_sink_max_bppx16,
dsc_max_bppx16;
+ u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd);
+ u8 bppx16_step;
int ret;
- dsc_min_bpp = max(dsc_min_compressed_bppx16(pipe_config) >> 4, 8);
+ if (DISPLAY_VER(dev_priv) < 14 || bppx16_incr <= 1)
+ bppx16_step = 16;
+ else
+ bppx16_step = 16 / bppx16_incr;
+
+ dsc_min_bppx16 = max((int)dsc_min_compressed_bppx16(pipe_config), 8 <<
4);
if (DISPLAY_VER(dev_priv) <= 12)
- dsc_src_max_bpp = 23;
+ dsc_src_max_bppx16 = 23 << 4;
else
- dsc_src_max_bpp = 27;
- dsc_sink_max_bpp = dsc_max_sink_compressed_bppx16(intel_dp->dsc_dpcd,
- pipe_config, pipe_bpp
/ 3) >> 4;
+ dsc_src_max_bppx16 = 27 << 4;
+ dsc_sink_max_bppx16 = dsc_max_sink_compressed_bppx16(intel_dp->dsc_dpcd,
+pipe_config,
pipe_bpp / 3);
- dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp)
: dsc_src_max_bpp;
+ dsc_max_bppx16 = dsc_sink_max_bppx16 ?
+ min(dsc_sink_max_bppx16, dsc_src_max_bppx16) :
dsc_src_max_bppx16;
- for (compressed_bpp = dsc_max_bpp;
-compressed_bpp >= dsc_min_bpp;
-compressed_bpp--) {
+ for (compressed_bppx16 = dsc_max_bppx16;
+compressed_bppx16 >= dsc_min_bppx16;
+compressed_bppx16 -= bppx16_step) {
ret = dsc_compute_link_config(intel_dp,
pipe_config,
limits,
pipe_bpp,
- compressed_bpp);
+ compressed_bppx16);
if (ret == 0) {
-
[Intel-gfx] [PATCH 10/11] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
From: Swati Sharma
DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
to depict sink's precision.
Also, new debugfs entry is created to enforce fractional bpp.
If Force_DSC_Fractional_BPP_en is set then while iterating over
output bpp with fractional step size we will continue if output_bpp is
computed as integer. With this approach, we will be able to validate
DSC with fractional bpp.
Signed-off-by: Swati Sharma
Signed-off-by: Ankit Nautiyal
---
.../drm/i915/display/intel_display_debugfs.c | 84 +++
.../drm/i915/display/intel_display_types.h| 1 +
2 files changed, 85 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 7bcd90384a46..2b36ec812293 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1772,6 +1772,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m,
void *data)
str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
seq_printf(m, "Force_DSC_Enable: %s\n",
str_yes_no(intel_dp->force_dsc_en));
+ seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
+ drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
if (!intel_dp_is_edp(intel_dp))
seq_printf(m, "FEC_Sink_Support: %s\n",
str_yes_no(drm_dp_sink_supports_fec(intel_dp->fec_capable)));
@@ -1895,6 +1897,85 @@ static const struct file_operations i915_dsc_bpc_fops = {
.write = i915_dsc_bpc_write
};
+static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
+{
+ struct drm_connector *connector = m->private;
+ struct drm_device *dev = connector->dev;
+ struct drm_crtc *crtc;
+ struct intel_dp *intel_dp;
+ struct intel_crtc_state *crtc_state;
+ struct intel_encoder *encoder =
intel_attached_encoder(to_intel_connector(connector));
+ int ret;
+
+ if (!encoder)
+ return -ENODEV;
+
+ ret =
drm_modeset_lock_single_interruptible(>mode_config.connection_mutex);
+ if (ret)
+ return ret;
+
+ crtc = connector->state->crtc;
+ if (connector->status != connector_status_connected || !crtc) {
+ ret = -ENODEV;
+ goto out;
+ }
+
+ intel_dp = intel_attached_dp(to_intel_connector(connector));
+ crtc_state = to_intel_crtc_state(crtc->state);
+ seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
+ str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
+
+out: drm_modeset_unlock(>mode_config.connection_mutex);
+
+ return ret;
+}
+
+static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
+const char __user *ubuf,
+size_t len, loff_t *offp)
+{
+ struct drm_connector *connector =
+ ((struct seq_file *)file->private_data)->private;
+ struct intel_encoder *encoder =
intel_attached_encoder(to_intel_connector(connector));
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ bool dsc_fractional_bpp_enable = false;
+ int ret;
+
+ if (len == 0)
+ return 0;
+
+ drm_dbg(>drm,
+ "Copied %zu bytes from user to force fractional bpp for DSC\n",
len);
+
+ ret = kstrtobool_from_user(ubuf, len, _fractional_bpp_enable);
+ if (ret < 0)
+ return ret;
+
+ drm_dbg(>drm, "Got %s for DSC Fractional BPP Enable\n",
+ (dsc_fractional_bpp_enable) ? "true" : "false");
+ intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
+
+ *offp += len;
+
+ return len;
+}
+
+static int i915_dsc_fractional_bpp_open(struct inode *inode,
+ struct file *file)
+{
+ return single_open(file, i915_dsc_fractional_bpp_show,
inode->i_private);
+}
+
+static const struct file_operations i915_dsc_fractional_bpp_fops = {
+ .owner = THIS_MODULE,
+ .open = i915_dsc_fractional_bpp_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+ .write = i915_dsc_fractional_bpp_write
+};
+
/*
* Returns the Current CRTC's bpc.
* Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
@@ -1966,6 +2047,9 @@ void intel_connector_debugfs_add(struct intel_connector
*intel_connector)
debugfs_create_file("i915_dsc_bpc", 0644, root,
connector, _dsc_bpc_fops);
+
+ debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
+ connector, _dsc_fractional_bpp_fops);
}
if (connector->connector_type ==
[Intel-gfx] [PATCH 07/11] drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
MTL+ supports fractional compressed bits_per_pixel, with precision of 1/16. This compressed bpp is stored in U6.4 format. Accommodate the precision during calculation of transfer unit data for hblank_early calculation. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_audio.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index f63d5824aca2..4797040a6362 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -510,14 +510,14 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, unsigned int link_clks_available, link_clks_required; unsigned int tu_data, tu_line, link_clks_active; unsigned int h_active, h_total, hblank_delta, pixel_clk; - unsigned int fec_coeff, cdclk, vdsc_bpp; + unsigned int fec_coeff, cdclk, vdsc_bppx16; unsigned int link_clk, lanes; unsigned int hblank_rise; h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay; h_total = crtc_state->hw.adjusted_mode.crtc_htotal; pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; - vdsc_bpp = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp); + vdsc_bppx16 = crtc_state->dsc.compressed_bpp; cdclk = i915->display.cdclk.hw.cdclk; /* fec= 0.972261, using rounding multiplier of 100 */ fec_coeff = 972261; @@ -525,10 +525,10 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, lanes = crtc_state->lane_count; drm_dbg_kms(>drm, "h_active = %u link_clk = %u :" - "lanes = %u vdsc_bpp = %u cdclk = %u\n", - h_active, link_clk, lanes, vdsc_bpp, cdclk); + "lanes = %u vdsc_bppx16 = %u cdclk = %u\n", + h_active, link_clk, lanes, vdsc_bppx16, cdclk); - if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk)) + if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk)) return 0; link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; @@ -540,7 +540,7 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), mul_u32_u32(link_clk, cdclk)); - tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8, 100), + tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 16 * 100), mul_u32_u32(link_clk * lanes, fec_coeff)); tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff), mul_u32_u32(64 * pixel_clk, 100)); -- 2.25.1
[Intel-gfx] [PATCH 06/11] drm/i915/display: Consider fractional vdsc bpp while computing m_n values
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate this precision while computing m_n values.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 7 ---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 ++-
drivers/gpu/drm/i915/display/intel_fdi.c | 2 +-
5 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index b3e23708d194..5a7703af166d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2753,10 +2753,14 @@ void
intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
- bool fec_enable)
+ bool fec_enable,
+ bool is_dsc_fractional_bpp)
{
u32 data_clock = bits_per_pixel * pixel_clock;
+ if (is_dsc_fractional_bpp)
+ data_clock = DIV_ROUND_UP(bits_per_pixel * pixel_clock, 16);
+
if (fec_enable)
data_clock = intel_dp_mode_to_fec_clock(data_clock);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 714030136b7f..f3d32de9fa2c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -506,7 +506,7 @@ u8 intel_calc_active_pipes(struct intel_atomic_state *state,
void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
- bool fec_enable);
+ bool fec_enable, bool is_dsc_fractional_bpp);
u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier);
enum drm_mode_status
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 5f61abb8a0e2..7ad39ddadae6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2132,7 +2132,7 @@ intel_dp_drrs_compute_config(struct intel_connector
*connector,
intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
pipe_config->port_clock, _config->dp_m2_n2,
- pipe_config->fec_enable);
+ pipe_config->fec_enable, false);
/* FIXME: abstract this better */
if (pipe_config->splitter.enable)
@@ -2255,7 +2255,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_dp_limited_color_range(pipe_config, conn_state);
if (pipe_config->dsc.compression_enable)
- output_bpp =
dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp);
+ output_bpp = pipe_config->dsc.compressed_bpp;
else
output_bpp = intel_dp_output_bpp(pipe_config->output_format,
pipe_config->pipe_bpp);
@@ -2285,7 +2285,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
adjusted_mode->crtc_clock,
pipe_config->port_clock,
_config->dp_m_n,
- pipe_config->fec_enable);
+ pipe_config->fec_enable,
+ pipe_config->dsc.compression_enable);
/* FIXME: abstract this better */
if (pipe_config->splitter.enable)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 4077a979a924..4f8010285ebf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -100,7 +100,8 @@ static int intel_dp_mst_compute_link_config(struct
intel_encoder *encoder,
adjusted_mode->crtc_clock,
crtc_state->port_clock,
_state->dp_m_n,
- crtc_state->fec_enable);
+ crtc_state->fec_enable,
+ false);
crtc_state->dp_m_n.tu = slots;
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
b/drivers/gpu/drm/i915/display/intel_fdi.c
index 063f1da4f229..5ab6c2e983d5 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -257,7 +257,7 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
pipe_config->fdi_lanes = lane;
intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
-
[Intel-gfx] [PATCH 04/11] drm/i915/dp: Get optimal link config to have best compressed bpp
Currently, we take the max lane, rate and pipe bpp, to get the maximum
compressed bpp possible. We then set the output bpp to this value.
This patch provides support to have max bpp, min rate and min lanes,
that can support the min compressed bpp.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 223 +---
1 file changed, 200 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 8ddbbada22ab..10f9292e1e0d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1461,6 +1461,187 @@ static int intel_dp_dsc_compute_params(struct
intel_encoder *encoder,
return drm_dsc_compute_rc_parameters(vdsc_cfg);
}
+static bool is_dsc_bw_sufficient(int link_rate, int lane_count, int
compressed_bpp,
+const struct drm_display_mode *adjusted_mode)
+{
+ int mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
compressed_bpp);
+ int link_avail = intel_dp_max_data_rate(link_rate, lane_count);
+
+ return mode_rate <= link_avail;
+}
+
+static int dsc_compute_link_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct link_config_limits *limits,
+ int pipe_bpp,
+ u16 compressed_bpp)
+{
+ const struct drm_display_mode *adjusted_mode =
+ _config->hw.adjusted_mode;
+ int link_rate, lane_count;
+ int dsc_max_bpp;
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ int i;
+
+ for (i = 0; i < intel_dp->num_common_rates; i++) {
+ link_rate = intel_dp_common_rate(intel_dp, i);
+ if (link_rate < limits->min_rate || link_rate >
limits->max_rate)
+ continue;
+
+ for (lane_count = limits->min_lane_count;
+lane_count <= limits->max_lane_count;
+lane_count <<= 1) {
+ dsc_max_bpp = intel_dp_dsc_get_output_bpp_max(dev_priv,
+ link_rate,
+
lane_count,
+
adjusted_mode->crtc_clock,
+
adjusted_mode->crtc_hdisplay,
+
pipe_config->bigjoiner_pipes,
+ pipe_bpp);
+ if (compressed_bpp > dsc_max_bpp)
+ continue;
+
+ if (!is_dsc_bw_sufficient(link_rate, lane_count,
+ compressed_bpp,
adjusted_mode))
+ continue;
+
+ pipe_config->lane_count = lane_count;
+ pipe_config->port_clock = link_rate;
+
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static u16 dsc_max_sink_compressed_bppx16(const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
+ struct intel_crtc_state *pipe_config,
+ int bpc)
+{
+ u16 max_bpp = dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
+(dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
+ DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK <<
DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT);
+
+ if (max_bpp)
+ return max_bpp;
+ /*
+* If support not given in DPCD 67h, 68h use the Maximum Allowed bit
rate
+* values as given in spec Table 2-157 DP v2.0
+*/
+ switch (pipe_config->output_format) {
+ case INTEL_OUTPUT_FORMAT_RGB:
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ return (3 * bpc) << 4;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ return (3 * (bpc / 2)) << 4;
+ default:
+ MISSING_CASE(pipe_config->output_format);
+ break;
+ }
+
+ return 0;
+}
+
+static u16 dsc_min_compressed_bppx16(struct intel_crtc_state *pipe_config)
+{
+ switch (pipe_config->output_format) {
+ case INTEL_OUTPUT_FORMAT_RGB:
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ return 8 << 4;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ return 6 << 4;
+ default:
+ MISSING_CASE(pipe_config->output_format);
+ break;
+ }
+
+ return 0;
+}
+
+static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct
