On 12/3/2022 3:42 AM, Dixit, Ashutosh wrote:
On Tue, 29 Nov 2022 21:34:26 -0800, Riana Tauro wrote:
Hi Riana,
Mostly looks good but I have a little nit below.
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c
b/drivers/gpu/drm/i915/i915_hwmon.c
index c588a17f97e9..57d4e96d5c72 100644
---
On Mon, Nov 28, 2022 at 03:49:18PM +0530, Ankit Nautiyal wrote:
> MTL+ supports fractional compressed bits_per_pixel, with precision of
> 1/16. This compressed bpp is stored in U6.4 format.
> Accommodate the precision during calculation of transfer unit data
> for hblank_early calculation.
>
>
== Series Details ==
Series: Align DDI_BUF_CTL Active timeouts with Bspec updates (rev4)
URL : https://patchwork.freedesktop.org/series/111373/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12465_full -> Patchwork_111373v4_full
On Mon, Nov 28, 2022 at 03:49:15PM +0530, Ankit Nautiyal wrote:
> Currently, we take the max lane, rate and pipe bpp, to get the maximum
> compressed bpp possible. We then set the output bpp to this value.
> This patch provides support to have max bpp, min rate and min lanes,
> that can support
From: Anshuman Gupta
Change the include/drm/i915_mei_hdcp_interface.h to
include/drm/i915_cp_fw_hdcp_interface.h
Cc: Tomas Winkler
Cc: Rodrigo Vivi
Cc: Uma Shankar
Cc: Ankit Nautiyal
Signed-off-by: Anshuman Gupta
Signed-off-by: Suraj Kandpal
---
From: Anshuman Gupta
As now we have more then one type of content protection
secrity firmware. Let change the i915_cp_fw_hdcp_interface.h
header naming convention to suit generic f/w type.
%s/MEI_/FW_
%s/mei_fw/cp_fw
%s/mei_dev/fw_dev
As interface to CP FW can be either a non i915 component or
HDCP and PXP will require a common function to allow it to
submit commands to the gsc cs. Also adding the gsc mtl header
that needs to be added on to the existing payloads of HDCP
and PXP.
Cc: Daniele Ceraolo Spurio
Cc: Alan Previn
Signed-off-by: Suraj Kandpal
---
From: Jonathan Cavitt
The GSC CS is only used for communicating with the GSC FW, so no need to
initialize it if we're not going to use the FW. If we're not using
neither the engine nor the microcontoller, then we can also disable the
power well.
IMPORTANT: lack of GSC FW breaks media C6 due to
From: Daniele Ceraolo Spurio
Now that we have the GSC FW support code as a user to the GSC CS, we
can add the relevant flag to the engine mask. Note that the engine will
still be disabled until we define the GSC FW binary file.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Matt Roper
Cc: Rodrigo
From: Daniele Ceraolo Spurio
If the GSC was loaded, the only way to stop it during the driver unload
flow is to do a driver-FLR.
The driver-FLR is not the same as PCI config space FLR in that
it doesn't reset the SGUnit and doesn't modify the PCI config
space. Thus, it doesn't require a
From: Daniele Ceraolo Spurio
GSC FW is loaded by submitting a dedicated command via the GSC engine.
The memory area used for loading the FW is then re-purposed as local
memory for the GSC itself, so we use a separate allocation instead of
using the one where we keep the firmware stored for
From: Daniele Ceraolo Spurio
The current exectation from the FW side is that the driver will query
the GSC FW version after the FW is loaded, similarly to what the mei
driver does on DG2. However, we're discussing with the FW team if there
is a way to extract the version from the bin file before
From: Daniele Ceraolo Spurio
On MTL the GSC FW needs to be loaded on the media GT by the graphics
driver. We're going to treat it like a new uc_fw, so add the initial
defs and init/fini functions for it.
Similarly to the other FWs, the GSC FW path can be overriden via
modparam. The modparam can
Starting from MTL HDCP will be enabled via the GSC CS route
rather than going through the usual MEI route as it did before
>From now on GSC will be the mei client and all HDCP has to do is
add on a gsc header along with its normal payload and send messages to
GSC CS who will take care of the rest
== Series Details ==
Series: Align DDI_BUF_CTL Active timeouts with Bspec updates (rev4)
URL : https://patchwork.freedesktop.org/series/111373/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12465 -> Patchwork_111373v4
> -Original Message-
> From: Dixit, Ashutosh
> Sent: Monday, December 5, 2022 7:10 AM
> To: Gupta, Anshuman
> Cc: intel-gfx@lists.freedesktop.org; Nilawar, Badal
> ; Vivi, Rodrigo
> Subject: Re: [PATCH] drm/i915/hwmon: Silence "mailbox access failed"
> warning in snb_pcode_read
>
>
> -Original Message-
> From: Ville Syrjälä
> Sent: Friday, October 28, 2022 12:01 PM
> To: Murthy, Arun R
> Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville
> Subject: Re: [Intel-gfx] [PATCHv3] drm/i915: Support Async Flip on Linear
> buffers
>
> On Fri, Oct 28, 2022 at 03:23:02AM
On Sat, 03 Dec 2022 01:47:06 -0800, Gupta, Anshuman wrote:
>
Hi Anshuman,
> > > hwm_pcode_read_i1 is called during i915 load. This results in the
> > > following warning from snb_pcode_read because
> > > POWER_SETUP_SUBCOMMAND_READ_I1 is unsupported on DG1/DG2.
> > >
> > > [drm:snb_pcode_read
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