[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/mtl: Apply Wa_14017073508 for MTL Media Step (rev2)
== Series Details == Series: drm/i915/mtl: Apply Wa_14017073508 for MTL Media Step (rev2) URL : https://patchwork.freedesktop.org/series/114508/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12800 -> Patchwork_114508v2 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_114508v2 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_114508v2, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v2/index.html Participating hosts (38 -> 2) -- ERROR: It appears as if the changes made in Patchwork_114508v2 prevented too many machines from booting. Additional (1): bat-atsm-1 Missing(37): fi-rkl-11600 bat-adls-5 bat-dg1-6 bat-dg1-5 bat-adlp-6 fi-apl-guc fi-snb-2520m bat-rpls-1 fi-blb-e6850 bat-rpls-2 fi-skl-6600u fi-bsw-n3050 bat-dg2-8 bat-adlm-1 bat-dg2-9 fi-ilk-650 fi-hsw-4770 bat-adln-1 fi-ivb-3770 bat-jsl-3 bat-rplp-1 fi-elk-e7500 bat-dg2-11 fi-bsw-nick fi-kbl-7567u bat-dg1-7 bat-kbl-2 bat-adlp-9 fi-skl-guc fi-cfl-8700k fi-glk-j4005 bat-jsl-1 fi-tgl-1115g4 fi-cfl-guc fi-kbl-guc fi-kbl-x1275 fi-cfl-8109u Known issues Here are the changes found in Patchwork_114508v2 that come from known issues: ### IGT changes ### Issues hit * igt@fbdev@eof: - bat-atsm-1: NOTRUN -> [SKIP][1] ([i915#2582]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v2/bat-atsm-1/igt@fb...@eof.html * igt@gem_mmap@basic: - bat-atsm-1: NOTRUN -> [SKIP][2] ([i915#4083]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v2/bat-atsm-1/igt@gem_m...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-atsm-1: NOTRUN -> [SKIP][3] ([i915#4077]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v2/bat-atsm-1/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-atsm-1: NOTRUN -> [SKIP][4] ([i915#4079]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v2/bat-atsm-1/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-atsm-1: NOTRUN -> [SKIP][5] ([i915#6621]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v2/bat-atsm-1/igt@i915_pm_...@basic-api.html * igt@i915_suspend@basic-s3-without-i915: - bat-atsm-1: NOTRUN -> [SKIP][6] ([i915#6645]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v2/bat-atsm-1/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_addfb_basic@size-max: - bat-atsm-1: NOTRUN -> [SKIP][7] ([i915#6077]) +36 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v2/bat-atsm-1/igt@kms_addfb_ba...@size-max.html * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic: - bat-atsm-1: NOTRUN -> [SKIP][8] ([i915#6078]) +19 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v2/bat-atsm-1/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html * igt@kms_flip@basic-plain-flip: - bat-atsm-1: NOTRUN -> [SKIP][9] ([i915#6166]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v2/bat-atsm-1/igt@kms_f...@basic-plain-flip.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-atsm-1: NOTRUN -> [SKIP][10] ([i915#6093]) +3 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v2/bat-atsm-1/igt@kms_force_connector_ba...@prune-stale-modes.html * igt@kms_pipe_crc_basic@hang-read-crc: - bat-atsm-1: NOTRUN -> [SKIP][11] ([i915#1836]) +6 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v2/bat-atsm-1/igt@kms_pipe_crc_ba...@hang-read-crc.html * igt@kms_prop_blob@basic: - bat-atsm-1: NOTRUN -> [SKIP][12] ([i915#7357]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v2/bat-atsm-1/igt@kms_prop_b...@basic.html * igt@kms_psr@sprite_plane_onoff: - bat-atsm-1: NOTRUN -> [SKIP][13] ([i915#1072]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v2/bat-atsm-1/igt@kms_psr@sprite_plane_onoff.html * igt@kms_setmode@basic-clone-single-crtc: - bat-atsm-1: NOTRUN -> [SKIP][14] ([i915#6094]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v2/bat-atsm-1/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-flip: - bat-atsm-1: NOTRUN -> [SKIP][15] ([fdo#109295] / [i915#6078]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v2/bat-atsm-1/igt@prime_v...@basic-fence-flip.html *
Re: [Intel-gfx] [PATCH v5 09/19] vfio/pci: Allow passing zero-length fd array in VFIO_DEVICE_PCI_HOT_RESET
> From: Liu, Yi L
> Sent: Monday, February 27, 2023 7:11 PM
[...]
> @@ -2392,13 +2416,25 @@ static int
> vfio_pci_dev_set_pm_runtime_get(struct vfio_device_set *dev_set)
> return ret;
> }
>
> +static bool vfio_dev_in_iommufd_ctx(struct vfio_pci_core_device *vdev,
> + struct iommufd_ctx *iommufd_ctx)
> +{
> + struct iommufd_ctx *iommufd = vfio_device_iommufd(
> >vdev);
> +
> + if (!iommufd)
> + return false;
> +
> + return iommufd == iommufd_ctx;
> +}
> +
> /*
> * We need to get memory_lock for each device, but devices can share
> mmap_lock,
> * therefore we need to zap and hold the vma_lock for each device, and
> only then
> * get each memory_lock.
> */
> static int vfio_pci_dev_set_hot_reset(struct vfio_device_set *dev_set,
> - struct vfio_pci_group_info *groups)
> + struct vfio_pci_group_info *groups,
> + struct iommufd_ctx *iommufd_ctx)
> {
> struct vfio_pci_core_device *cur_mem;
> struct vfio_pci_core_device *cur_vma;
> @@ -2429,10 +2465,27 @@ static int vfio_pci_dev_set_hot_reset(struct
> vfio_device_set *dev_set,
>
> list_for_each_entry(cur_vma, _set->device_list,
> vdev.dev_set_list) {
> /*
> - * Test whether all the affected devices are contained by
> the
> - * set of groups provided by the user.
> + * Test whether all the affected devices can be reset by the
> + * user. The affected devices may already been opened or
> not
> + * yet.
> + *
> + * For the devices not opened yet, user can reset them. The
> + * reason is that the hot reset is done under the protection
> + * of the dev_set->lock, and device open is also under this
> + * lock. During the hot reset, such devices can not be
> opened
> + * by other users.
> + *
> + * For the devices that have been opened, needs to check
> the
> + * ownership. If the user provides a set of group fds, the
> + * ownership check is done by checking if all the opened
> + * devices are contained by the groups. If the user provides
> + * a zero-length fd array, the ownerhsip check is done by
> + * checking if all the opened devices are bound to the same
> + * iommufd_ctx.
>*/
> - if (!vfio_dev_in_groups(cur_vma, groups)) {
> + if (cur_vma->vdev.open_count &&
> + !vfio_dev_in_groups(cur_vma, groups) &&
> + !vfio_dev_in_iommufd_ctx(cur_vma, iommufd_ctx)) {
Hi Alex, Jason,
There is one concern on this approach which is related to the
cdev noiommu mode. As patch 16 of this series, cdev path
supports noiommu mode by passing a negative iommufd to
kernel. In such case, the vfio_device is not bound to a valid
iommufd. Then the check in vfio_dev_in_iommufd_ctx() is
to be broken.
An idea is to add a cdev_noiommu flag in vfio_device, when
checking the iommufd_ictx, also check this flag. If all the opened
devices in the dev_set have vfio_device->cdev_noiommu==true,
then the reset is considered to be doable. But there is a special
case. If devices in this dev_set are opened by two applications
that operates in cdev noiommu mode, then this logic is not able
to differentiate them. In that case, should we allow the reset?
It seems to ok to allow reset since noiommu mode itself means
no security between the applications that use it. thoughts?
> ret = -EINVAL;
> goto err_undo;
> }
> diff --git a/drivers/vfio/vfio.h b/drivers/vfio/vfio.h
> index 2e3cb284711d..64e862a02dad 100644
> --- a/drivers/vfio/vfio.h
> +++ b/drivers/vfio/vfio.h
> @@ -225,6 +225,11 @@ static inline void vfio_container_cleanup(void)
> #if IS_ENABLED(CONFIG_IOMMUFD)
> int vfio_iommufd_bind(struct vfio_device *device, struct iommufd_ctx
> *ictx);
> void vfio_iommufd_unbind(struct vfio_device *device);
> +static inline struct iommufd_ctx *
> +vfio_device_iommufd(struct vfio_device *device)
> +{
> + return device->iommufd_ictx;
> +}
> #else
Regards,
Yi Liu
Re: [Intel-gfx] [PATCH v5 16/19] vfio: Add VFIO_DEVICE_BIND_IOMMUFD
> From: Jason Gunthorpe
> Sent: Thursday, March 2, 2023 1:47 AM
>
> On Wed, Mar 01, 2023 at 09:19:07AM +, Liu, Yi L wrote:
> > > From: Liu, Yi L
> > > Sent: Monday, February 27, 2023 7:12 PM
> > [...]
> > > +long vfio_device_ioctl_bind_iommufd(struct vfio_device_file *df,
> > > + unsigned long arg)
> > > +{
> > > + struct vfio_device *device = df->device;
> > > + struct vfio_device_bind_iommufd bind;
> > > + struct iommufd_ctx *iommufd = NULL;
> > > + unsigned long minsz;
> > > + int ret;
> > > +
> > > + minsz = offsetofend(struct vfio_device_bind_iommufd, out_devid);
> > > +
> > > + if (copy_from_user(, (void __user *)arg, minsz))
> > > + return -EFAULT;
> > > +
> > > + if (bind.argsz < minsz || bind.flags)
> > > + return -EINVAL;
> > > +
> > > + if (!device->ops->bind_iommufd)
> > > + return -ENODEV;
> >
> > Hi Jason,
> >
> > Per the comment in vfio_iommufd_bind(), such device driver
> > won't provide .bind_iommufd(). So shall we allow this ioctl
> > to go longer to call .open_device() instead of failing it here?
> > I think we need to allow it to go further. E.g. leave the check
> > to be in vfio_iommufd_bind(). Otherwise, user may not able
> > to use such devices. Is it?
>
> You are thinking about the crazy mdev samples?
Yes. we don't have real devices which don't do DMA. Is it?
> We should probably just change them to provide a 'no dma' set of ops.
Yes. at least generate iommufd_device I suppose.
> > > +struct vfio_device_bind_iommufd {
> > > + __u32 argsz;
> > > + __u32 flags;
> > > + __aligned_u64 dev_cookie;
> > > + __s32 iommufd;
> > > + __u32 out_devid;
> >
> > As above, for the devices that do not do DMA, there is no .bind_iommufd
> > op, hence no iommufd_device generated. This means no good value
> > can be filled in this out_devid field. So this field is optional. Only
> > for the devices which do DMA, should this out_devid field return a
> > valid ID otherwise an invalid ID would be filled (e.g. value #0 is an
> > invalid value in the iommufd object id pool). Userspace needs to
> > check if the out_devid is valid or not before use. This ID can be further
> > used in iommufd uAPIs like IOMMU_HWPT_ALLOC,
> IOMMU_DEVICE_GET_INFO
> > and etc.
>
> I would say create an access and harmonize the no-DMA devices with the
> emulated devices.
In this case, iommufd_access would be created instead of iommufd_device.
> What should we return here anyhow if an access was created?
It depends on what can be done with this id and whether this field is mandatory.
For iommufd_device ID, the user could further use it to query iommu device info
and
alloc hwpt. Do we have a similar usage for iommufd_access? And if we define this
field as optional, then we may return iommufd_access object Id in future if it
is
needed.
Regards,
Yi Liu
Re: [Intel-gfx] [PATCH v5 17/19] vfio: Add VFIO_DEVICE_AT[DE]TACH_IOMMUFD_PT
> From: Jason Gunthorpe
> Sent: Thursday, March 2, 2023 1:49 AM
>
> On Wed, Mar 01, 2023 at 02:04:00PM +, Liu, Yi L wrote:
> > diff --git a/drivers/vfio/group.c b/drivers/vfio/group.c
> > index 2a13442add43..ed3ffe7ceb3f 100644
> > --- a/drivers/vfio/group.c
> > +++ b/drivers/vfio/group.c
> > @@ -777,6 +777,11 @@ void vfio_device_group_unregister(struct
> vfio_device *device)
> > mutex_unlock(>group->device_lock);
> > }
> >
> > +bool vfio_device_group_uses_container(struct vfio_device *device)
> > +{
> > + return READ_ONCE(device->group->container);
> > +}
>
> As I said this should take in the vfio_device_file because as long as
> a vfio_device_file exists then group->contianer is required to be stable.
Ok, let me store vfio_group in vfio_devcie_file instead of reach
it by df->device->group.
btw. With vfio_group stored in vfio_device_file, it looks like
the is_cdev_device flag (introduced in patch 14) is not necessary
now, we can always define the group pointer in vfio_device_file
even group code is compiled out, then we can use this group
pointer to check if the vfio_device_file is used in the group path
or the cdev path. Is it?
> > diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
> > index 121a75fadceb..4b5b17e8aaa1 100644
> > --- a/drivers/vfio/vfio_main.c
> > +++ b/drivers/vfio/vfio_main.c
> > @@ -422,9 +422,22 @@ static int vfio_device_first_open(struct
> vfio_device_file *df)
> > if (!try_module_get(device->dev->driver->owner))
> > return -ENODEV;
> >
> > + /*
> > +* The handling here depends on what the user is using.
> > +*
> > +* If user uses iommufd in the group compat mode or the
> > +* cdev path, call vfio_iommufd_bind().
> > +*
> > +* If user uses container in the group legacy mode, call
> > +* vfio_device_group_use_iommu().
> > +*
> > +* If user doesn't use iommufd nor container, this is
> > +* the noiommufd mode in the cdev path, nothing needs
> > +* to be done here just go ahead to open device.
> > +*/
> > if (iommufd)
> > ret = vfio_iommufd_bind(device, iommufd);
> > - else
> > + else if (vfio_device_group_uses_container(device))
> > ret = vfio_device_group_use_iommu(device);
>
> But yes, this makes alot more sense..
>
> Jason
Regards,
Yi Liu
Re: [Intel-gfx] [PATCH v2] drm/i915/active: Fix misuse of non-idle barriers as fence trackers
Hi Janusz,
On Sat, Feb 25, 2023 at 11:12:18PM +0100, Janusz Krzysztofik wrote:
> Users reported oopses on list corruptions when using i915 perf with a
> number of concurrently running graphics applications. Root cause analysis
> pointed at an issue in barrier processing code -- a race among perf open /
> close replacing active barriers with perf requests on kernel context and
> concurrent barrier preallocate / acquire operations performed during user
> context first pin / last unpin.
>
> When adding a request to a composite tracker, we try to reuse an existing
> fence tracker, already allocated and registered with that composite. The
> tracker we obtain may already track another fence, may be an idle barrier,
> or an active barrier.
>
> If the tracker we get occurs a non-idle barrier then we try to delete that
> barrier from a list of barrier tasks it belongs to. However, while doing
> that we don't respect return value from a function that performs the
> barrier deletion. Should the deletion ever failed, we would end up
> reusing the tracker still registered as a barrier task. Since the same
> structure field is reused with both fence callback lists and barrier
> tasks list, list corruptions would likely occur.
>
> Barriers are now deleted from a barrier tasks list by temporarily removing
> the list content, traversing that content with skip over the node to be
> deleted, then populating the list back with the modified content. Should
> that intentionally racy concurrent deletion attempts be not serialized,
> one or more of those may fail because of the list being temporary empty.
>
> Related code that ignores the results of barrier deletion was initially
> introduced in v5.4 by commit d8af05ff38ae ("drm/i915: Allow sharing the
> idle-barrier from other kernel requests"). However, all users of the
> barrier deletion routine were apparently serialized at that time, then the
> issue didn't exhibit itself. Results of git bisect with help of a newly
> developed igt@gem_barrier_race@remote-request IGT test indicate that list
> corruptions might start to appear after commit 311770173fac ("drm/i915/gt:
> Schedule request retirement when timeline idles"), introduced in v5.5.
>
> Respect results of barrier deletion attempts -- mark the barrier as idle
> only if successfully deleted from the list. Then, before proceeding with
> setting our fence as the one currently tracked, make sure that the tracker
> we've got is not a non-idle barrier. If that check fails then don't use
> that tracker but go back and try to acquire a new, usable one.
>
> v2: no code changes,
> - blame commit 311770173fac ("drm/i915/gt: Schedule request retirement
> when timeline idles"), v5.5, not commit d8af05ff38ae ("drm/i915: Allow
> sharing the idle-barrier from other kernel requests"), v5.4,
> - reword commit description.
That's a very good explanation and very much needed for such a
catch. Thanks!
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6333
> Fixes: 311770173fac ("drm/i915/gt: Schedule request retirement when timeline
> idles")
> Cc: Chris Wilson
> Cc: sta...@vger.kernel.org # v5.5
> Signed-off-by: Janusz Krzysztofik
> ---
> drivers/gpu/drm/i915/i915_active.c | 25 ++---
> 1 file changed, 14 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_active.c
> b/drivers/gpu/drm/i915/i915_active.c
> index 7412abf166a8c..f9282b8c87c1c 100644
> --- a/drivers/gpu/drm/i915/i915_active.c
> +++ b/drivers/gpu/drm/i915/i915_active.c
> @@ -422,12 +422,12 @@ replace_barrier(struct i915_active *ref, struct
> i915_active_fence *active)
>* we can use it to substitute for the pending idle-barrer
>* request that we want to emit on the kernel_context.
>*/
> - __active_del_barrier(ref, node_from_active(active));
> - return true;
> + return __active_del_barrier(ref, node_from_active(active));
In general, I support the idea of always checking the return
value, even if we expect a certain outcome. In these cases, the
likely/unlikely macros can be helpful. Given this change, I
believe the patch deserves an ack.
That being said, I was curious whether using an explicit lock
and a normal list of active barriers, rather than a lockless
list, could have solved the problem. It seems like using a
lockless list and iterating over it could be overkill, unless
there are specific scenarios where the lockless properties are
necessary.
Of course, this may be something to consider in a future cleanup,
as it may be outside the scope of this particular patch.
> }
>
> int i915_active_add_request(struct i915_active *ref, struct i915_request *rq)
> {
> + u64 idx = i915_request_timeline(rq)->fence_context;
> struct dma_fence *fence = >fence;
> struct i915_active_fence *active;
> int err;
> @@ -437,16 +437,19 @@ int i915_active_add_request(struct i915_active *ref,
> struct i915_request *rq)
> if (err)
>
Re: [Intel-gfx] [PATCH v3 4/9] drm/i915/perf: Group engines into respective OA groups
On Mon, 27 Feb 2023 18:23:24 -0800, Umesh Nerlige Ramappa wrote:
>
> @@ -3378,12 +3376,13 @@ void i915_oa_init_reg_state(const struct
> intel_context *ce,
> const struct intel_engine_cs *engine)
> {
> struct i915_perf_stream *stream;
> + struct i915_perf_group *g = engine->oa_group;
>
> - if (!engine_supports_oa(engine))
> + if (!g)
Maybe leave the engine_supports_oa check here since the NULL oa_group check
is now implemented there.
Rest looks good to be overall so this is:
Reviewed-by: Ashutosh Dixit
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/sseu: fix max_subslices array-index-out-of-bounds access (rev4)
On Wed, Mar 01, 2023 at 01:38:52AM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/sseu: fix max_subslices array-index-out-of-bounds access
> (rev4)
> URL : https://patchwork.freedesktop.org/series/114199/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_12794_full -> Patchwork_114199v4_full
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_114199v4_full absolutely need
> to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_114199v4_full, please notify your bug team to allow
> them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Participating hosts (11 -> 11)
> --
>
> No changes in participating hosts
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_114199v4_full:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
> - shard-apl: [PASS][1] -> [ABORT][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12794/shard-apl6/igt@kms_flip@flip-vs-suspend-interrupti...@a-dp1.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114199v4/shard-apl3/igt@kms_flip@flip-vs-suspend-interrupti...@a-dp1.html
The errors in the log here are display warnings, likely related to
https://gitlab.freedesktop.org/drm/intel/-/issues/180 . They are not
caused by the GT patch under test.
Applied to drm-intel-gt-next. Thanks for the patch.
Matt
>
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@i915_suspend@sysfs-reader:
> - {shard-tglu}: [PASS][3] -> [DMESG-WARN][4]
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12794/shard-tglu-3/igt@i915_susp...@sysfs-reader.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114199v4/shard-tglu-3/igt@i915_susp...@sysfs-reader.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_114199v4_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@device_reset@cold-reset-bound:
> - shard-tglu-9: NOTRUN -> [SKIP][5] ([i915#7701])
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114199v4/shard-tglu-9/igt@device_re...@cold-reset-bound.html
>
> * igt@feature_discovery@chamelium:
> - shard-tglu-10: NOTRUN -> [SKIP][6] ([fdo#111827]) +2 similar issues
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114199v4/shard-tglu-10/igt@feature_discov...@chamelium.html
>
> * igt@gem_ccs@ctrl-surf-copy:
> - shard-tglu-9: NOTRUN -> [SKIP][7] ([i915#3555] / [i915#5325])
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114199v4/shard-tglu-9/igt@gem_...@ctrl-surf-copy.html
>
> * igt@gem_ccs@suspend-resume:
> - shard-tglu-10: NOTRUN -> [SKIP][8] ([i915#5325])
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114199v4/shard-tglu-10/igt@gem_...@suspend-resume.html
>
> * igt@gem_close_race@multigpu-basic-process:
> - shard-tglu-9: NOTRUN -> [SKIP][9] ([i915#7697]) +1 similar issue
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114199v4/shard-tglu-9/igt@gem_close_r...@multigpu-basic-process.html
>
> * igt@gem_ctx_persistence@processes:
> - shard-snb: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#1099])
> +4 similar issues
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114199v4/shard-snb4/igt@gem_ctx_persiste...@processes.html
>
> * igt@gem_ctx_sseu@invalid-sseu:
> - shard-tglu-9: NOTRUN -> [SKIP][11] ([i915#280]) +1 similar issue
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114199v4/shard-tglu-9/igt@gem_ctx_s...@invalid-sseu.html
>
> * igt@gem_exec_balancer@parallel-ordering:
> - shard-tglu-9: NOTRUN -> [FAIL][12] ([i915#6117])
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114199v4/shard-tglu-9/igt@gem_exec_balan...@parallel-ordering.html
>
> * igt@gem_exec_params@rsvd2-dirt:
> - shard-tglu-9: NOTRUN -> [SKIP][13] ([fdo#109283])
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114199v4/shard-tglu-9/igt@gem_exec_par...@rsvd2-dirt.html
>
> * igt@gem_huc_copy@huc-copy:
> - shard-tglu-9: NOTRUN -> [SKIP][14] ([i915#2190])
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114199v4/shard-tglu-9/igt@gem_huc_c...@huc-copy.html
>
> * igt@gem_lmem_swapping@heavy-verify-random:
> - shard-tglu-9: NOTRUN -> [SKIP][15] ([i915#4613])
>[15]:
>
[Intel-gfx] ✓ Fi.CI.BAT: success for Misc Meteorlake patches (rev3)
== Series Details == Series: Misc Meteorlake patches (rev3) URL : https://patchwork.freedesktop.org/series/112700/ State : success == Summary == CI Bug Log - changes from CI_DRM_12799 -> Patchwork_112700v3 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/index.html Participating hosts (40 -> 39) -- Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_112700v3 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_gttfill@basic: - fi-pnv-d510:[PASS][1] -> [FAIL][2] ([i915#7229]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/fi-pnv-d510/igt@gem_exec_gttf...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/fi-pnv-d510/igt@gem_exec_gttf...@basic.html * igt@i915_selftest@live@requests: - bat-rpls-1: [PASS][3] -> [ABORT][4] ([i915#7694] / [i915#7911]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-1/igt@i915_selftest@l...@requests.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-rpls-1/igt@i915_selftest@l...@requests.html Possible fixes * igt@i915_pm_rps@basic-api: - bat-rpls-2: [SKIP][5] ([i915#6621]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-2/igt@i915_pm_...@basic-api.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-rpls-2/igt@i915_pm_...@basic-api.html - bat-dg1-6: [SKIP][7] ([i915#6621]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-dg1-6/igt@i915_pm_...@basic-api.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-dg1-6/igt@i915_pm_...@basic-api.html - bat-adlp-6: [SKIP][9] ([i915#6621]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-adlp-6/igt@i915_pm_...@basic-api.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-adlp-6/igt@i915_pm_...@basic-api.html - bat-atsm-1: [SKIP][11] ([i915#6621]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-atsm-1/igt@i915_pm_...@basic-api.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-atsm-1/igt@i915_pm_...@basic-api.html - bat-dg2-11: [SKIP][13] ([i915#6621]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-dg2-11/igt@i915_pm_...@basic-api.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-dg2-11/igt@i915_pm_...@basic-api.html - bat-dg2-8: [SKIP][15] ([i915#6621]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-dg2-8/igt@i915_pm_...@basic-api.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-dg2-8/igt@i915_pm_...@basic-api.html - bat-adlm-1: [SKIP][17] ([i915#6621]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-adlm-1/igt@i915_pm_...@basic-api.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-adlm-1/igt@i915_pm_...@basic-api.html - bat-rpls-1: [SKIP][19] ([i915#6621]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-1/igt@i915_pm_...@basic-api.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-rpls-1/igt@i915_pm_...@basic-api.html - bat-dg1-7: [SKIP][21] ([i915#6621]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-dg1-7/igt@i915_pm_...@basic-api.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-dg1-7/igt@i915_pm_...@basic-api.html - bat-adlp-9: [SKIP][23] ([i915#6621]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-adlp-9/igt@i915_pm_...@basic-api.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-adlp-9/igt@i915_pm_...@basic-api.html - bat-rplp-1: [SKIP][25] ([i915#6621]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rplp-1/igt@i915_pm_...@basic-api.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-rplp-1/igt@i915_pm_...@basic-api.html - bat-dg1-5: [SKIP][27] ([i915#6621]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-dg1-5/igt@i915_pm_...@basic-api.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-dg1-5/igt@i915_pm_...@basic-api.html - bat-dg2-9: [SKIP][29] ([i915#6621]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-dg2-9/igt@i915_pm_...@basic-api.html [30]:
Re: [Intel-gfx] [RFC PATCH 00/20] Initial Xe driver submission
On Fri, Feb 17, 2023 at 09:51:37PM +0100, Daniel Vetter wrote: > Hi all, > > [I thought I've sent this out earlier this week, but alas got stuck, kinda > bad timing now since I'm out next week but oh well] > > So xe is a quite substantial thing, and I think we need a clear plan how to > land > this or it will take forever, and managers will panic. Also I'm not a big fan > of > "Dave/me reviews everything", we defacto had that for amd's dc/dal and it was > not fun. The idea here is how to get everything reviewed without having two > people end up somewhat arbitrary as deciders. Thank you so much for taking time to write it down. We need to get alignment on the critical topics to see how we can move this forward. > > I've compiled a bunch of topics on what I think the important areas are, first > code that should be consistent about new-style render drivers that are aimed > for > vk/compute userspace as the primary feature driver: > > - figure out consensus solution for fw scheduler and drm/sched frontend among > interested driver parties (probably xe, amdgpu, nouveau, new panfrost) Yeap. We do need to figure this out. But just to ensure that we are in the same page here. What I had in mind was that Matt would upstream the 5 or 6 drm_sched related patches that we have underneath Xe patches on drm-misc with addressing the community feedback, then we would merge Xe with the current schedule solution (or modifications based on the modifications of these mentioned patches) and then we would continue to work with the other drivers to improve the drm sched frontend while we are already in tree. Possible? or do you want to see fundamental changes before we can even consider to get in? Like the ones below? > > - for the interface itself it might be good to have the drm_gpu_scheduler as > the > single per-hw-engine driver api object (but internally a new structure), > while > renaming the current drm_gpu_scheduler to drm_gpu_sched_internal. That way I > think we can address the main critique of the current xe scheduler plan > - keep the drm_gpu_sched_internal : drm_sched_entity 1:1 relationship for fw > scheduler > - keep the driver api relationship of drm_gpu_scheduler : drm_sched_entity > 1:n, the api functions simply iterate over a mutex protect list of > internal > schedulers. this should also help drivers with locking mistakes around > setup/teardown and gpu reset. > - drivers select with a flag or something between the current mode (where > the > drm_gpu_sched_internal is attached to the drm_gpu_scheduler api object) or > the new fw scheduler mode (where drm_gpu_sched_internal is attached to the > drm_sched_entity) > - overall still no fundamental changes (like the current patches) to > drm/sched > data structures and algorithms. But unlike the current patches we keep the > possibility open for eventual refactoring without having to again refactor > all the drivers. Even better, we can delay such refactoring until we have > a > handful of real-word drivers test-driving this all so we know we actually > do > the right thing. This should allow us to address all the > fairness/efficiency/whatever concerns that have been floating around > without > having to fix them all up upfront, before we actually know what needs to > be > fixed. do you believe this has to be decided and moved towards one of this before we get merged? > > - the generic scheduler code should also including the handling of endless > compute contexts, with the minimal scaffolding for preempt-ctx fences > (probably on the drm_sched_entity) and making sure drm/sched can cope with > the > lack of job completion fence. This is very minimal amounts of code, but it > helps a lot for cross-driver review if this works the same (with the same > locking and all that) for everyone. Ideally this gets extracted from amdkfd, > but as long as it's going to be used by all drivers supporting > endless/compute context going forward it's good enough. On this one I'm a bit clueless to be honest. I thought the biggest problem with the long running context or even endless were due to the hangcheck premption or migrations that would end in some pagefaults. But yeap, it looks that there are opens to get these kind of workloads properly supported. But with this in mind do you see any real blocker on Xe? or any must-have thing? > > - I'm assuming this also means Matt Brost will include a patch to add himself > as > drm/sched reviewer in MAINTAINERS, or at least something like that +1 on this idea! This enforces our engagement and commitment with the drm_sched imho. > > - adopt the gem_exec/vma helpers. again we probably want consensus here among > the same driver projects. I don't care whether these helpers specify the > ioctl > structs or not, but they absolutely need to enforce the overall locking > scheme > for all major structs and list
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Misc Meteorlake patches (rev3)
== Series Details == Series: Misc Meteorlake patches (rev3) URL : https://patchwork.freedesktop.org/series/112700/ State : warning == Summary == Error: dim checkpatch failed f2efa48f76b8 drm/i915/mtl: Fix Wa_16015201720 implementation 3d4b9acde185 drm/i915/gt: generate per tile debugfs files 300a16a2c511 drm/i915/mtl: make IRQ reset and postinstall multi-gt aware 1af00da0945d drm/i915/fbdev: lock the fbdev obj before vma pin -:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #9: <7>[ 93.563308] i915 :00:02.0: [drm:intelfb_create [i915]] no BIOS fb, allocating a new one -:51: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #51: FILE: drivers/gpu/drm/i915/display/intel_fbdev.c:296: + "Failed to remap framebuffer into virtual memory (%pe)\n", vaddr); -:51: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #51: FILE: drivers/gpu/drm/i915/display/intel_fbdev.c:296: + drm_err(_priv->drm, + "Failed to remap framebuffer into virtual memory (%pe)\n", vaddr); total: 0 errors, 2 warnings, 1 checks, 37 lines checked 4be18c15f3ba drm/i915/display/mtl: Program latch to phy reset
Re: [Intel-gfx] [PATCH v4 07/22] drm/i915/mtl: Add support for PM DEMAND
Hi Mika,
> -Original Message-
> From: Kahola, Mika
> Sent: Friday, February 24, 2023 2:14 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kahola, Mika ; Atwood, Matthew S
> ; Roper, Matthew D
> ; De Marchi, Lucas ;
> Sousa, Gustavo ; Souza, Jose
> ; Sripada, Radhakrishna
>
> Subject: [PATCH v4 07/22] drm/i915/mtl: Add support for PM DEMAND
>
> Display14 introduces a new way to instruct the PUnit with
> power and bandwidth requirements of DE. Add the functionality
> to program the registers and handle waits using interrupts.
> The current wait time for timeouts is programmed for 10 msecs to
> factor in the worst case scenarios. Changes made to use REG_BIT
> for a register that we touched(GEN8_DE_MISC_IER _MMIO).
>
> v2:
> - Removed repeated definition of dbuf, which has been moved to struct
> intel_display. (Gustavo)
> - s/dev_priv->dbuf/dev_priv->display.dbuf/ (Gustavo)
>
> Bspec: 66451, 64636, 64602, 64603
> Cc: Matt Atwood
> Cc: Matt Roper
> Cc: Lucas De Marchi
> Cc: Gustavo Sousa
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Radhakrishna Sripada
> Link:
> https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-8-
> mika.kah...@intel.com
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 4 +-
> drivers/gpu/drm/i915/display/intel_bw.h | 2 +
> drivers/gpu/drm/i915/display/intel_display.c | 14 +
> .../drm/i915/display/intel_display_power.c| 8 +
> drivers/gpu/drm/i915/i915_drv.h | 6 +
> drivers/gpu/drm/i915/i915_irq.c | 22 +-
> drivers/gpu/drm/i915/i915_reg.h | 33 +-
> drivers/gpu/drm/i915/intel_pm.c | 286 ++
> drivers/gpu/drm/i915/intel_pm.h | 35 +++
> 9 files changed, 405 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 202321ffbe2a..87c20bf52123 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -746,8 +746,8 @@ static unsigned int intel_bw_num_active_planes(struct
> drm_i915_private *dev_priv
> return num_active_planes;
> }
>
> -static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> -const struct intel_bw_state *bw_state)
> +unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> + const struct intel_bw_state *bw_state)
> {
> unsigned int data_rate = 0;
> enum pipe pipe;
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
> b/drivers/gpu/drm/i915/display/intel_bw.h
> index f20292143745..17fc0b61db04 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -62,6 +62,8 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
> int intel_bw_atomic_check(struct intel_atomic_state *state);
> void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> const struct intel_crtc_state *crtc_state);
> +unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> + const struct intel_bw_state *bw_state);
> int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> u32 points_mask);
> int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 8030968e7008..676bf512b9ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -959,6 +959,9 @@ intel_get_crtc_new_encoder(const struct
> intel_atomic_state *state,
> num_encoders++;
> }
>
> + if (!encoder)
> + return NULL;
> +
> drm_WARN(encoder->base.dev, num_encoders != 1,
>"%d encoders for pipe %c\n",
>num_encoders, pipe_name(master_crtc->pipe));
> @@ -6823,6 +6826,10 @@ int intel_atomic_check(struct drm_device *dev,
> ret = intel_modeset_calc_cdclk(state);
> if (ret)
> return ret;
> +
> + ret = intel_pmdemand_atomic_check(state);
> + if (ret)
> + goto fail;
> }
>
> ret = intel_atomic_check_crtcs(state);
> @@ -7439,6 +7446,7 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> }
>
> intel_sagv_pre_plane_update(state);
> + intel_pmdemand_pre_plane_update(state);
>
> /* Complete the events for pipes that have now been disabled */
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> @@ -7551,6 +7559,7 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> intel_verify_planes(state);
>
> intel_sagv_post_plane_update(state);
> + intel_pmdemand_post_plane_update(state);
>
>
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: vblank stuff (rev3)
== Series Details == Series: drm/i915: vblank stuff (rev3) URL : https://patchwork.freedesktop.org/series/112170/ State : success == Summary == CI Bug Log - changes from CI_DRM_12799 -> Patchwork_112170v3 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112170v3/index.html Participating hosts (40 -> 40) -- Additional (1): fi-kbl-soraka Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_112170v3 that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112170v3/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112170v3/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][3] ([i915#5334] / [i915#7872]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112170v3/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][4] ([i915#1886]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112170v3/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@hangcheck: - fi-kbl-soraka: NOTRUN -> [INCOMPLETE][5] ([i915#7913]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112170v3/fi-kbl-soraka/igt@i915_selftest@l...@hangcheck.html * igt@i915_selftest@live@reset: - bat-rpls-2: [PASS][6] -> [ABORT][7] ([i915#4983] / [i915#7913]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-2/igt@i915_selftest@l...@reset.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112170v3/bat-rpls-2/igt@i915_selftest@l...@reset.html * igt@i915_selftest@live@slpc: - bat-rpls-1: NOTRUN -> [DMESG-FAIL][8] ([i915#6367] / [i915#7996]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112170v3/bat-rpls-1/igt@i915_selftest@l...@slpc.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-rpls-1: NOTRUN -> [SKIP][9] ([i915#7828]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112170v3/bat-rpls-1/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271]) +16 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112170v3/fi-kbl-soraka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_pipe_crc_basic@suspend-read-crc: - bat-rpls-1: NOTRUN -> [SKIP][11] ([i915#1845]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112170v3/bat-rpls-1/igt@kms_pipe_crc_ba...@suspend-read-crc.html Possible fixes * igt@i915_selftest@live@migrate: - bat-atsm-1: [DMESG-FAIL][12] ([i915#7699]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-atsm-1/igt@i915_selftest@l...@migrate.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112170v3/bat-atsm-1/igt@i915_selftest@l...@migrate.html * igt@i915_selftest@live@reset: - bat-rpls-1: [ABORT][14] ([i915#4983]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-1/igt@i915_selftest@l...@reset.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112170v3/bat-rpls-1/igt@i915_selftest@l...@reset.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996 Build changes - * Linux: CI_DRM_12799 -> Patchwork_112170v3 CI-20190529: 20190529 CI_DRM_12799: 5f6631c00a7f226c990aecc643bc9fa70da1599a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7178:
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/gt: Create per-tile debugfs files
> I am not sure if Tiles is appropriate usage here. Since MTL does not have the
> concept of tiles.
> Shouldn't we be using gt instead of tile in our usage?
>
> With s/tile/gt/g,
> Reviewed-by: Radhakrishna Sripada
yes, GT is preferred to tile, generally. Thanks for the review, I
will change the commit log according to your comment.
Thanks!
Andi
> > -Original Message-
> > From: dri-devel On Behalf Of Andi
> > Shyti
> > Sent: Wednesday, March 1, 2023 3:03 AM
> > To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> > Cc: Tvrtko Ursulin ; Andi Shyti
> > ; Patelczyk, Maciej ; Andi
> > Shyti ; Wajdeczko, Michal
> >
> > Subject: [PATCH v2 1/2] drm/i915/gt: Create per-tile debugfs files
> >
> > To support multi-GT configurations, we need to generate
> > independent debug files for each GT.
> >
> > To achieve this create a separate directory for each GT under the
> > debugfs directory. For instance, in a system with two tiles, the
> > debugfs structure would look like this:
> >
> > /sys/kernel/debug/dri
> > └── 0
> > ├── gt0
> > │ ├── drpc
> > │ ├── engines
> > │ ├── forcewake
> > │ ├── frequency
> > │ └── rps_boost
> > └── gt1
> > : ├── drpc
> > : ├── engines
> > : ├── forcewake
> > ├── frequency
> > └── rps_boost
> >
> > Signed-off-by: Andi Shyti
> > Cc: Tvrtko Ursulin
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_debugfs.c| 4 +++-
> > drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 ++
> > drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 5 -
> > drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c | 2 ++
> > 4 files changed, 11 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> > b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> > index 5fc2df01aa0df..4dc23b8d3aa2d 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> > @@ -83,11 +83,13 @@ static void gt_debugfs_register(struct intel_gt *gt,
> > struct dentry *root)
> > void intel_gt_debugfs_register(struct intel_gt *gt)
> > {
> > struct dentry *root;
> > + char gtname[4];
> >
> > if (!gt->i915->drm.primary->debugfs_root)
> > return;
> >
> > - root = debugfs_create_dir("gt", gt->i915->drm.primary->debugfs_root);
> > + snprintf(gtname, sizeof(gtname), "gt%u", gt->info.id);
> > + root = debugfs_create_dir(gtname, gt->i915->drm.primary-
> > >debugfs_root);
> > if (IS_ERR(root))
> > return;
> >
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > index bb4dfe707a7d0..e46aac1a41e6d 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > @@ -42,6 +42,8 @@ struct intel_guc {
> > /** @capture: the error-state-capture module's data and objects */
> > struct intel_guc_state_capture *capture;
> >
> > + struct dentry *dbgfs_node;
> > +
> > /** @sched_engine: Global engine used to submit requests to GuC */
> > struct i915_sched_engine *sched_engine;
> > /**
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> > index 195db8c9d4200..55bc8b55fbc05 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> > @@ -542,8 +542,11 @@ static int guc_log_relay_create(struct intel_guc_log
> > *log)
> > */
> > n_subbufs = 8;
> >
> > + if (!guc->dbgfs_node)
> > + return -ENOENT;
> > +
> > guc_log_relay_chan = relay_open("guc_log",
> > - i915->drm.primary->debugfs_root,
> > + guc->dbgfs_node,
> > subbuf_size, n_subbufs,
> > _callbacks, i915);
> > if (!guc_log_relay_chan) {
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
> > b/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
> > index 284d6fbc2d08c..2f93cc4e408a8 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
> > @@ -54,6 +54,8 @@ void intel_uc_debugfs_register(struct intel_uc *uc, struct
> > dentry *gt_root)
> > if (IS_ERR(root))
> > return;
> >
> > + uc->guc.dbgfs_node = root;
> > +
> > intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), uc);
> >
> > intel_guc_debugfs_register(>guc, root);
> > --
> > 2.39.1
>
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: split out DSC and DSS registers
== Series Details == Series: drm/i915/display: split out DSC and DSS registers URL : https://patchwork.freedesktop.org/series/114523/ State : success == Summary == CI Bug Log - changes from CI_DRM_12799 -> Patchwork_114523v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/index.html Participating hosts (40 -> 38) -- Missing(2): fi-snb-2520m fi-pnv-d510 Known issues Here are the changes found in Patchwork_114523v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3@smem: - bat-rpls-1: NOTRUN -> [ABORT][1] ([i915#6687] / [i915#7978]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html * igt@i915_selftest@live@gt_heartbeat: - bat-jsl-1: [PASS][2] -> [DMESG-FAIL][3] ([i915#5334]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-jsl-1/igt@i915_selftest@live@gt_heartbeat.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/bat-jsl-1/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@slpc: - bat-rpls-1: NOTRUN -> [DMESG-FAIL][4] ([i915#6367]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html Possible fixes * igt@i915_selftest@live@migrate: - bat-atsm-1: [DMESG-FAIL][5] ([i915#7699]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-atsm-1/igt@i915_selftest@l...@migrate.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/bat-atsm-1/igt@i915_selftest@l...@migrate.html * igt@i915_selftest@live@reset: - bat-rpls-1: [ABORT][7] ([i915#4983]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-1/igt@i915_selftest@l...@reset.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/bat-rpls-1/igt@i915_selftest@l...@reset.html Warnings * igt@i915_selftest@live@slpc: - bat-rpls-2: [DMESG-FAIL][9] ([i915#6997] / [i915#7913]) -> [DMESG-FAIL][10] ([i915#6367] / [i915#7913]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-2/igt@i915_selftest@l...@slpc.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687 [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997 [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978 Build changes - * Linux: CI_DRM_12799 -> Patchwork_114523v1 CI-20190529: 20190529 CI_DRM_12799: 5f6631c00a7f226c990aecc643bc9fa70da1599a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7178: ffe3f6670b91ab975f90799ab3fd0941b6eae019 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_114523v1: 5f6631c00a7f226c990aecc643bc9fa70da1599a @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 0e112008e261 drm/i915/display: split out DSC and DSS registers == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/index.html
Re: [Intel-gfx] [PATCH v3 8/9] drm/i915/perf: Add engine class instance parameters to perf
On Mon, 27 Feb 2023 18:23:28 -0800, Umesh Nerlige Ramappa wrote:
>
Hi Umesh,
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 8df261c5ab9b..8ce20004a9dd 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -2758,6 +2758,28 @@ enum drm_i915_perf_property_id {
>*/
> DRM_I915_PERF_PROP_POLL_OA_PERIOD,
>
> + /**
> + * In platforms with multiple OA buffers, the engine class instance must
I'd say "one engine class instance".
> + * be passed to open a stream to a OA unit corresponding to the engine.
> + * Multiple engines may be mapped to the same OA unit.
Maybe (at the risk of over-stating) something like "Multiple engines may be
mapped to the same OA unit. The OA unit is identified by class:instance of
any engine mapped to it".
But it's ok to not change anything here.
> + *
> + * In addition to the class:instance, if a gem context is also passed,
> then
> + * 1) the report headers of OA reports from any contexts that do not
> + *match this specific engine context are squashed.
This one I don't understand: we seem to be mixing gem contexts and engine
context here. Also, afais there are no changes related to this in this
series. This context squashing has always been happening, so why add this
comment to DRM_I915_PERF_PROP_OA_ENGINE_CLASS (or to this patch)? If we
want to clarify something maybe this comment should be added to
DRM_I915_PERF_PROP_CTX_HANDLE? But otherwise I think we should just drop
this comment, at least from this patch?
> + * 2) if the engine supports MI_REPORT_PERF_COUNT, this specific engine
> + *context is configured for this command.
> + *
> + * This property is available in perf revision 6.
> + */
> + DRM_I915_PERF_PROP_OA_ENGINE_CLASS,
> +
> + /**
> + * This parameter specifies the engine instance.
> + *
> + * This property is available in perf revision 6.
> + */
> + DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE,
> +
> DRM_I915_PERF_PROP_MAX /* non-ABI */
> };
Thanks.
--
Ashutosh
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Separate wakeref tracking
On 27.02.2023 12:50, Jani Nikula wrote:
On Fri, 24 Feb 2023, Andrzej Hajda wrote:
From: Chris Wilson
Extract the callstack tracking of intel_runtime_pm.c into its own
utility so that that we can reuse it for other online debugging of
scoped wakerefs.
Signed-off-by: Chris Wilson
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/i915/Kconfig.debug | 9 +
drivers/gpu/drm/i915/Makefile| 4 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 244 +++
drivers/gpu/drm/i915/intel_runtime_pm.h | 10 +-
drivers/gpu/drm/i915/intel_wakeref.h | 6 +-
drivers/gpu/drm/i915/intel_wakeref_tracker.c | 234 +
drivers/gpu/drm/i915/intel_wakeref_tracker.h | 76 +
7 files changed, 355 insertions(+), 228 deletions(-)
diff --git a/drivers/gpu/drm/i915/Kconfig.debug
b/drivers/gpu/drm/i915/Kconfig.debug
index 93dfb7ed970547..5fde52107e3b44 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -25,6 +25,7 @@ config DRM_I915_DEBUG
select PREEMPT_COUNT
select I2C_CHARDEV
select STACKDEPOT
+ select STACKTRACE
select DRM_DP_AUX_CHARDEV
select X86_MSR # used by igt/pm_rpm
select DRM_VGEM # used by igt/prime_vgem (dmabuf interop checks)
@@ -37,6 +38,7 @@ config DRM_I915_DEBUG
select DRM_I915_DEBUG_GEM
select DRM_I915_DEBUG_GEM_ONCE
select DRM_I915_DEBUG_MMIO
+ select DRM_I915_TRACK_WAKEREF
select DRM_I915_DEBUG_RUNTIME_PM
select DRM_I915_SW_FENCE_DEBUG_OBJECTS
select DRM_I915_SELFTEST
@@ -227,11 +229,18 @@ config DRM_I915_DEBUG_VBLANK_EVADE
If in doubt, say "N".
+config DRM_I915_TRACK_WAKEREF
+ depends on STACKDEPOT
+ depends on STACKTRACE
+ bool
+
config DRM_I915_DEBUG_RUNTIME_PM
bool "Enable extra state checking for runtime PM"
depends on DRM_I915
default n
select STACKDEPOT
+ select STACKTRACE
+ select DRM_I915_TRACK_WAKEREF
help
Choose this option to turn on extra state checking for the
runtime PM functionality. This may introduce overhead during
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index b2f91a1f826858..42daff6d575a82 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -81,6 +81,10 @@ i915-$(CONFIG_DEBUG_FS) += \
i915_debugfs_params.o \
display/intel_display_debugfs.o \
display/intel_pipe_crc.o
+
+i915-$(CONFIG_DRM_I915_TRACK_WAKEREF) += \
+ intel_wakeref_tracker.o
+
i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
# "Graphics Technology" (aka we talk to the gpu)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 129746713d072f..72887e2bb03c21 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -52,182 +52,37 @@
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
-#include
-
-#define STACKDEPTH 8
-
-static noinline depot_stack_handle_t __save_depot_stack(void)
-{
- unsigned long entries[STACKDEPTH];
- unsigned int n;
-
- n = stack_trace_save(entries, ARRAY_SIZE(entries), 1);
- return stack_depot_save(entries, n, GFP_NOWAIT | __GFP_NOWARN);
-}
-
static void init_intel_runtime_pm_wakeref(struct intel_runtime_pm *rpm)
{
- spin_lock_init(>debug.lock);
- stack_depot_init();
+ intel_wakeref_tracker_init(>debug);
}
-static noinline depot_stack_handle_t
+static intel_wakeref_t
track_intel_runtime_pm_wakeref(struct intel_runtime_pm *rpm)
{
- depot_stack_handle_t stack, *stacks;
- unsigned long flags;
-
- if (rpm->no_wakeref_tracking)
- return -1;
-
- stack = __save_depot_stack();
- if (!stack)
+ if (!rpm->available)
return -1;
- spin_lock_irqsave(>debug.lock, flags);
-
- if (!rpm->debug.count)
- rpm->debug.last_acquire = stack;
-
- stacks = krealloc(rpm->debug.owners,
- (rpm->debug.count + 1) * sizeof(*stacks),
- GFP_NOWAIT | __GFP_NOWARN);
- if (stacks) {
- stacks[rpm->debug.count++] = stack;
- rpm->debug.owners = stacks;
- } else {
- stack = -1;
- }
-
- spin_unlock_irqrestore(>debug.lock, flags);
-
- return stack;
+ return intel_wakeref_tracker_add(>debug);
}
static void untrack_intel_runtime_pm_wakeref(struct intel_runtime_pm *rpm,
-depot_stack_handle_t stack)
+intel_wakeref_t wakeref)
{
- struct drm_i915_private *i915 = container_of(rpm,
-struct drm_i915_private,
-runtime_pm);
- unsigned
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/gt: Create per-tile debugfs files
I am not sure if Tiles is appropriate usage here. Since MTL does not have the
concept of tiles.
Shouldn't we be using gt instead of tile in our usage?
With s/tile/gt/g,
Reviewed-by: Radhakrishna Sripada
> -Original Message-
> From: dri-devel On Behalf Of Andi
> Shyti
> Sent: Wednesday, March 1, 2023 3:03 AM
> To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Cc: Tvrtko Ursulin ; Andi Shyti
> ; Patelczyk, Maciej ; Andi
> Shyti ; Wajdeczko, Michal
>
> Subject: [PATCH v2 1/2] drm/i915/gt: Create per-tile debugfs files
>
> To support multi-GT configurations, we need to generate
> independent debug files for each GT.
>
> To achieve this create a separate directory for each GT under the
> debugfs directory. For instance, in a system with two tiles, the
> debugfs structure would look like this:
>
> /sys/kernel/debug/dri
> └── 0
> ├── gt0
> │ ├── drpc
> │ ├── engines
> │ ├── forcewake
> │ ├── frequency
> │ └── rps_boost
> └── gt1
> : ├── drpc
> : ├── engines
> : ├── forcewake
> ├── frequency
> └── rps_boost
>
> Signed-off-by: Andi Shyti
> Cc: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/gt/intel_gt_debugfs.c| 4 +++-
> drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 ++
> drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 5 -
> drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c | 2 ++
> 4 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> index 5fc2df01aa0df..4dc23b8d3aa2d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> @@ -83,11 +83,13 @@ static void gt_debugfs_register(struct intel_gt *gt,
> struct dentry *root)
> void intel_gt_debugfs_register(struct intel_gt *gt)
> {
> struct dentry *root;
> + char gtname[4];
>
> if (!gt->i915->drm.primary->debugfs_root)
> return;
>
> - root = debugfs_create_dir("gt", gt->i915->drm.primary->debugfs_root);
> + snprintf(gtname, sizeof(gtname), "gt%u", gt->info.id);
> + root = debugfs_create_dir(gtname, gt->i915->drm.primary-
> >debugfs_root);
> if (IS_ERR(root))
> return;
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index bb4dfe707a7d0..e46aac1a41e6d 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -42,6 +42,8 @@ struct intel_guc {
> /** @capture: the error-state-capture module's data and objects */
> struct intel_guc_state_capture *capture;
>
> + struct dentry *dbgfs_node;
> +
> /** @sched_engine: Global engine used to submit requests to GuC */
> struct i915_sched_engine *sched_engine;
> /**
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> index 195db8c9d4200..55bc8b55fbc05 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> @@ -542,8 +542,11 @@ static int guc_log_relay_create(struct intel_guc_log
> *log)
>*/
> n_subbufs = 8;
>
> + if (!guc->dbgfs_node)
> + return -ENOENT;
> +
> guc_log_relay_chan = relay_open("guc_log",
> - i915->drm.primary->debugfs_root,
> + guc->dbgfs_node,
> subbuf_size, n_subbufs,
> _callbacks, i915);
> if (!guc_log_relay_chan) {
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
> index 284d6fbc2d08c..2f93cc4e408a8 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
> @@ -54,6 +54,8 @@ void intel_uc_debugfs_register(struct intel_uc *uc, struct
> dentry *gt_root)
> if (IS_ERR(root))
> return;
>
> + uc->guc.dbgfs_node = root;
> +
> intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), uc);
>
> intel_guc_debugfs_register(>guc, root);
> --
> 2.39.1
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/gt: Create per-tile debugfs files
> -Original Message-
> From: dri-devel On Behalf Of Andi
> Shyti
> Sent: Wednesday, March 1, 2023 3:03 AM
> To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Cc: Tvrtko Ursulin ; Andi Shyti
> ; Patelczyk, Maciej ; Andi
> Shyti ; Wajdeczko, Michal
>
> Subject: [PATCH v2 1/2] drm/i915/gt: Create per-tile debugfs files
>
> To support multi-GT configurations, we need to generate
> independent debug files for each GT.
>
> To achieve this create a separate directory for each GT under the
> debugfs directory. For instance, in a system with two tiles, the
> debugfs structure would look like this:
>
> /sys/kernel/debug/dri
> └── 0
> ├── gt0
> │ ├── drpc
> │ ├── engines
> │ ├── forcewake
> │ ├── frequency
> │ └── rps_boost
> └── gt1
> : ├── drpc
> : ├── engines
> : ├── forcewake
> ├── frequency
> └── rps_boost
>
> Signed-off-by: Andi Shyti
> Cc: Tvrtko Ursulin
LGTM,
Reviewed-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/gt/intel_gt_debugfs.c| 4 +++-
> drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 ++
> drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 5 -
> drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c | 2 ++
> 4 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> index 5fc2df01aa0df..4dc23b8d3aa2d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> @@ -83,11 +83,13 @@ static void gt_debugfs_register(struct intel_gt *gt,
> struct dentry *root)
> void intel_gt_debugfs_register(struct intel_gt *gt)
> {
> struct dentry *root;
> + char gtname[4];
>
> if (!gt->i915->drm.primary->debugfs_root)
> return;
>
> - root = debugfs_create_dir("gt", gt->i915->drm.primary->debugfs_root);
> + snprintf(gtname, sizeof(gtname), "gt%u", gt->info.id);
> + root = debugfs_create_dir(gtname, gt->i915->drm.primary-
> >debugfs_root);
> if (IS_ERR(root))
> return;
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index bb4dfe707a7d0..e46aac1a41e6d 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -42,6 +42,8 @@ struct intel_guc {
> /** @capture: the error-state-capture module's data and objects */
> struct intel_guc_state_capture *capture;
>
> + struct dentry *dbgfs_node;
> +
> /** @sched_engine: Global engine used to submit requests to GuC */
> struct i915_sched_engine *sched_engine;
> /**
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> index 195db8c9d4200..55bc8b55fbc05 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> @@ -542,8 +542,11 @@ static int guc_log_relay_create(struct intel_guc_log
> *log)
>*/
> n_subbufs = 8;
>
> + if (!guc->dbgfs_node)
> + return -ENOENT;
> +
> guc_log_relay_chan = relay_open("guc_log",
> - i915->drm.primary->debugfs_root,
> + guc->dbgfs_node,
> subbuf_size, n_subbufs,
> _callbacks, i915);
> if (!guc_log_relay_chan) {
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
> index 284d6fbc2d08c..2f93cc4e408a8 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
> @@ -54,6 +54,8 @@ void intel_uc_debugfs_register(struct intel_uc *uc, struct
> dentry *gt_root)
> if (IS_ERR(root))
> return;
>
> + uc->guc.dbgfs_node = root;
> +
> intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), uc);
>
> intel_guc_debugfs_register(>guc, root);
> --
> 2.39.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsi: fix DSS CTL register offsets for TGL+
== Series Details == Series: drm/i915/dsi: fix DSS CTL register offsets for TGL+ URL : https://patchwork.freedesktop.org/series/114522/ State : success == Summary == CI Bug Log - changes from CI_DRM_12799 -> Patchwork_114522v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114522v1/index.html Participating hosts (40 -> 39) -- Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_114522v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3@smem: - bat-rpls-1: NOTRUN -> [ABORT][1] ([i915#6687] / [i915#7978]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114522v1/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html * igt@i915_selftest@live@requests: - bat-rpls-2: [PASS][2] -> [ABORT][3] ([i915#4983] / [i915#7694] / [i915#7913] / [i915#7981]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-2/igt@i915_selftest@l...@requests.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114522v1/bat-rpls-2/igt@i915_selftest@l...@requests.html * igt@i915_selftest@live@slpc: - bat-rpls-1: NOTRUN -> [DMESG-FAIL][4] ([i915#6367] / [i915#7996]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114522v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html Possible fixes * igt@i915_selftest@live@migrate: - bat-atsm-1: [DMESG-FAIL][5] ([i915#7699]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-atsm-1/igt@i915_selftest@l...@migrate.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114522v1/bat-atsm-1/igt@i915_selftest@l...@migrate.html * igt@i915_selftest@live@reset: - bat-rpls-1: [ABORT][7] ([i915#4983]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-1/igt@i915_selftest@l...@reset.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114522v1/bat-rpls-1/igt@i915_selftest@l...@reset.html [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687 [i915#7694]: https://gitlab.freedesktop.org/drm/intel/issues/7694 [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978 [i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981 [i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996 Build changes - * Linux: CI_DRM_12799 -> Patchwork_114522v1 CI-20190529: 20190529 CI_DRM_12799: 5f6631c00a7f226c990aecc643bc9fa70da1599a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7178: ffe3f6670b91ab975f90799ab3fd0941b6eae019 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_114522v1: 5f6631c00a7f226c990aecc643bc9fa70da1599a @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 3f1fc1c43734 drm/i915/dsi: fix DSS CTL register offsets for TGL+ == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114522v1/index.html
Re: [Intel-gfx] [PATCH v3 2/5] drm/i915/gt: generate per tile debugfs files
This patch can be ignored. As the original Author submitted the series here
https://patchwork.freedesktop.org/series/114510/
- Radhakrishna(RK) Sripada
> -Original Message-
> From: Sripada, Radhakrishna
> Sent: Wednesday, March 1, 2023 12:11 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Shyti, Andi ; Ursulin, Tvrtko
> ; Sripada, Radhakrishna
>
> Subject: [PATCH v3 2/5] drm/i915/gt: generate per tile debugfs files
>
> From: Andi Shyti
>
> In the view of multi-gt we want independent per gt debug files.
>
> In debugfs create gt0/ gt1/ ... gtN/ for tile related files. In 4
> tiles, the debugfs would be structured as follows:
>
> /sys/kernel/debug/dri
> └── 0
> ├── gt0
> │ ├── drpc
> │ ├── engines
> │ ├── forcewake
> │ ├── frequency
> │ └── rps_boost
> ├── gt1
> │ ├── drpc
> │ ├── engines
> │ ├── forcewake
> │ ├── frequency
> │ └── rps_boost
> ├── gt2
> │ ├── drpc
> │ ├── engines
> │ ├── forcewake
> │ ├── frequency
> │ └── rps_boost
> └─- gt3
> : ├── drpc
> : ├── engines
> : ├── forcewake
> ├── frequency
> └── rps_boost
>
> v2: Fix the missed assignment dbgfs_node
>
> Cc: Tvrtko Ursulin
> Signed-off-by: Andi Shyti
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/gt/intel_gt_debugfs.c| 4 +++-
> drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 ++
> drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 5 -
> drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c | 2 ++
> 4 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> index 5fc2df01aa0d..4dc23b8d3aa2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> @@ -83,11 +83,13 @@ static void gt_debugfs_register(struct intel_gt *gt,
> struct dentry *root)
> void intel_gt_debugfs_register(struct intel_gt *gt)
> {
> struct dentry *root;
> + char gtname[4];
>
> if (!gt->i915->drm.primary->debugfs_root)
> return;
>
> - root = debugfs_create_dir("gt", gt->i915->drm.primary->debugfs_root);
> + snprintf(gtname, sizeof(gtname), "gt%u", gt->info.id);
> + root = debugfs_create_dir(gtname, gt->i915->drm.primary-
> >debugfs_root);
> if (IS_ERR(root))
> return;
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index bb4dfe707a7d..e46aac1a41e6 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -42,6 +42,8 @@ struct intel_guc {
> /** @capture: the error-state-capture module's data and objects */
> struct intel_guc_state_capture *capture;
>
> + struct dentry *dbgfs_node;
> +
> /** @sched_engine: Global engine used to submit requests to GuC */
> struct i915_sched_engine *sched_engine;
> /**
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> index 195db8c9d420..55bc8b55fbc0 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> @@ -542,8 +542,11 @@ static int guc_log_relay_create(struct intel_guc_log
> *log)
>*/
> n_subbufs = 8;
>
> + if (!guc->dbgfs_node)
> + return -ENOENT;
> +
> guc_log_relay_chan = relay_open("guc_log",
> - i915->drm.primary->debugfs_root,
> + guc->dbgfs_node,
> subbuf_size, n_subbufs,
> _callbacks, i915);
> if (!guc_log_relay_chan) {
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
> index 284d6fbc2d08..2f93cc4e408a 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
> @@ -54,6 +54,8 @@ void intel_uc_debugfs_register(struct intel_uc *uc, struct
> dentry *gt_root)
> if (IS_ERR(root))
> return;
>
> + uc->guc.dbgfs_node = root;
> +
> intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), uc);
>
> intel_guc_debugfs_register(>guc, root);
> --
> 2.34.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: pm cleanups, rename to clock gating
== Series Details == Series: drm/i915: pm cleanups, rename to clock gating URL : https://patchwork.freedesktop.org/series/114519/ State : success == Summary == CI Bug Log - changes from CI_DRM_12799 -> Patchwork_114519v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/index.html Participating hosts (40 -> 40) -- Additional (1): fi-kbl-soraka Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_114519v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3@smem: - bat-rpls-1: NOTRUN -> [ABORT][1] ([i915#6687] / [i915#7978]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@i915_selftest@live@execlists: - fi-kbl-soraka: NOTRUN -> [INCOMPLETE][4] ([i915#7156] / [i915#7913]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gt_heartbeat: - fi-apl-guc: [PASS][5] -> [DMESG-FAIL][6] ([i915#5334]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][7] ([i915#1886]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@hangcheck: - fi-skl-guc: [PASS][8] -> [DMESG-WARN][9] ([i915#8073]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271]) +16 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/fi-kbl-soraka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html Possible fixes * igt@i915_selftest@live@migrate: - bat-atsm-1: [DMESG-FAIL][11] ([i915#7699]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-atsm-1/igt@i915_selftest@l...@migrate.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/bat-atsm-1/igt@i915_selftest@l...@migrate.html * igt@i915_selftest@live@reset: - bat-rpls-1: [ABORT][13] ([i915#4983]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-1/igt@i915_selftest@l...@reset.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/bat-rpls-1/igt@i915_selftest@l...@reset.html Warnings * igt@i915_selftest@live@slpc: - bat-rpls-2: [DMESG-FAIL][15] ([i915#6997] / [i915#7913]) -> [DMESG-FAIL][16] ([i915#6367] / [i915#7913] / [i915#7996]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-2/igt@i915_selftest@l...@slpc.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687 [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997 [i915#7156]: https://gitlab.freedesktop.org/drm/intel/issues/7156 [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978 [i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996 [i915#8073]: https://gitlab.freedesktop.org/drm/intel/issues/8073 Build changes
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Add vfio_device cdev for iommufd support (rev6)
== Series Details == Series: Add vfio_device cdev for iommufd support (rev6) URL : https://patchwork.freedesktop.org/series/113696/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/113696/revisions/6/mbox/ not applied Applying: vfio: Allocate per device file structure Using index info to reconstruct a base tree... M drivers/vfio/group.c M drivers/vfio/vfio.h M drivers/vfio/vfio_main.c Falling back to patching base and 3-way merge... Auto-merging drivers/vfio/vfio_main.c Auto-merging drivers/vfio/vfio.h Auto-merging drivers/vfio/group.c Applying: vfio: Refine vfio file kAPIs for KVM Using index info to reconstruct a base tree... M drivers/vfio/group.c M drivers/vfio/vfio.h M drivers/vfio/vfio_main.c M include/linux/vfio.h Falling back to patching base and 3-way merge... Auto-merging include/linux/vfio.h Auto-merging drivers/vfio/vfio_main.c Auto-merging drivers/vfio/vfio.h Auto-merging drivers/vfio/group.c CONFLICT (content): Merge conflict in drivers/vfio/group.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0002 vfio: Refine vfio file kAPIs for KVM When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: pm cleanups, rename to clock gating
== Series Details ==
Series: drm/i915: pm cleanups, rename to clock gating
URL : https://patchwork.freedesktop.org/series/114519/
State : warning
== Summary ==
Error: dim checkpatch failed
b692b7687640 drm/i915/wm: remove display/ prefix from include
3c139b502a1f drm/i915/pm: drop intel_pm_setup()
107a5af9ab14 drm/i915/pm: drop intel_suspend_hw()
b19705e1c09f drm/i915: remove unnecessary intel_pm.h includes
f361dedf95d4 drm/i915: rename intel_pm.[ch] to intel_clock_gating.[ch]
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:147: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#147:
rename from drivers/gpu/drm/i915/intel_pm.c
total: 0 errors, 1 warnings, 0 checks, 168 lines checked
66cba8ee1b7c drm/i915/clock: mass rename dev_priv to i915
-:1032: CHECK:BRACES: braces {} should be used on all arms of this statement
#1032: FILE: drivers/gpu/drm/i915/intel_clock_gating.c:834:
+ if (IS_METEORLAKE(i915))
[...]
+ else if (IS_PONTEVECCHIO(i915))
[...]
+ else if (IS_DG2(i915))
[...]
+ else if (IS_XEHPSDV(i915))
[...]
+ else if (IS_ALDERLAKE_P(i915))
[...]
+ else if (GRAPHICS_VER(i915) == 12)
[...]
+ else if (GRAPHICS_VER(i915) == 11)
[...]
+ else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
[...]
+ else if (IS_SKYLAKE(i915))
[...]
+ else if (IS_KABYLAKE(i915))
[...]
+ else if (IS_BROXTON(i915))
[...]
+ else if (IS_GEMINILAKE(i915))
[...]
+ else if (IS_BROADWELL(i915))
[...]
+ else if (IS_CHERRYVIEW(i915))
[...]
+ else if (IS_HASWELL(i915))
[...]
+ else if (IS_IVYBRIDGE(i915))
[...]
+ else if (IS_VALLEYVIEW(i915))
[...]
+ else if (GRAPHICS_VER(i915) == 6)
[...]
+ else if (GRAPHICS_VER(i915) == 5)
[...]
+ else if (IS_G4X(i915))
[...]
+ else if (IS_I965GM(i915))
[...]
+ else if (IS_I965G(i915))
[...]
+ else if (GRAPHICS_VER(i915) == 3)
[...]
+ else if (IS_I85X(i915) || IS_I865G(i915))
[...]
+ else if (GRAPHICS_VER(i915) == 2)
[...]
else {
[...]
total: 0 errors, 0 warnings, 1 checks, 1056 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/5] drm/i915/power: move dc state members to struct i915_power_domains
== Series Details == Series: series starting with [v4,1/5] drm/i915/power: move dc state members to struct i915_power_domains URL : https://patchwork.freedesktop.org/series/114515/ State : success == Summary == CI Bug Log - changes from CI_DRM_12799 -> Patchwork_114515v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114515v1/index.html Participating hosts (40 -> 39) -- Additional (1): fi-kbl-soraka Missing(2): fi-snb-2520m fi-pnv-d510 Known issues Here are the changes found in Patchwork_114515v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3@smem: - bat-rpls-1: NOTRUN -> [ABORT][1] ([i915#6687] / [i915#7978]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114515v1/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114515v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114515v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@i915_selftest@live@execlists: - fi-kbl-soraka: NOTRUN -> [INCOMPLETE][4] ([i915#7913]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114515v1/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gt_heartbeat: - fi-apl-guc: [PASS][5] -> [DMESG-FAIL][6] ([i915#5334]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114515v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][7] ([i915#1886]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114515v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@reset: - bat-rpls-2: [PASS][8] -> [ABORT][9] ([i915#4983] / [i915#7913]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-2/igt@i915_selftest@l...@reset.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114515v1/bat-rpls-2/igt@i915_selftest@l...@reset.html * igt@i915_selftest@live@workarounds: - bat-adlm-1: [PASS][10] -> [INCOMPLETE][11] ([i915#4983] / [i915#7677]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-adlm-1/igt@i915_selftest@l...@workarounds.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114515v1/bat-adlm-1/igt@i915_selftest@l...@workarounds.html * igt@i915_suspend@basic-s2idle-without-i915: - fi-kbl-x1275: [PASS][12] -> [ABORT][13] ([i915#8213]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/fi-kbl-x1275/igt@i915_susp...@basic-s2idle-without-i915.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114515v1/fi-kbl-x1275/igt@i915_susp...@basic-s2idle-without-i915.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-kbl-soraka: NOTRUN -> [SKIP][14] ([fdo#109271]) +16 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114515v1/fi-kbl-soraka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_pipe_crc_basic@read-crc-frame-sequence: - bat-adlp-9: NOTRUN -> [SKIP][15] ([i915#3546]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114515v1/bat-adlp-9/igt@kms_pipe_crc_ba...@read-crc-frame-sequence.html Possible fixes * igt@i915_selftest@live@migrate: - bat-atsm-1: [DMESG-FAIL][16] ([i915#7699]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-atsm-1/igt@i915_selftest@l...@migrate.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114515v1/bat-atsm-1/igt@i915_selftest@l...@migrate.html * igt@i915_selftest@live@reset: - bat-rpls-1: [ABORT][18] ([i915#4983]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-1/igt@i915_selftest@l...@reset.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114515v1/bat-rpls-1/igt@i915_selftest@l...@reset.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[Intel-gfx] [PATCH v3 3/5] drm/i915/mtl: make IRQ reset and postinstall multi-gt aware
Irq reset and post install are to be made multi-gt aware for the
interrupts to work for the media tile on Meteorlake. Iterate through
all the gts to process irq reset for each gt.
Based on original version by Paulo and Tvrtko
Cc: Paulo Zanoni
Cc: Tvrtko Ursulin
Reviewed-by: Lucas De Marchi
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/i915_irq.c | 30 ++
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 417c981e4968..9377f59c1ac2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2759,16 +2759,19 @@ static void gen11_irq_reset(struct drm_i915_private
*dev_priv)
static void dg1_irq_reset(struct drm_i915_private *dev_priv)
{
- struct intel_gt *gt = to_gt(dev_priv);
- struct intel_uncore *uncore = gt->uncore;
+ struct intel_gt *gt;
+ unsigned int i;
dg1_master_intr_disable(dev_priv->uncore.regs);
- gen11_gt_irq_reset(gt);
- gen11_display_irq_reset(dev_priv);
+ for_each_gt(gt, dev_priv, i) {
+ gen11_gt_irq_reset(gt);
- GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
- GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+ GEN3_IRQ_RESET(gt->uncore, GEN11_GU_MISC_);
+ GEN3_IRQ_RESET(gt->uncore, GEN8_PCU_);
+ }
+
+ gen11_display_irq_reset(dev_priv);
}
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
@@ -3422,13 +3425,16 @@ static void gen11_irq_postinstall(struct
drm_i915_private *dev_priv)
static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
{
- struct intel_gt *gt = to_gt(dev_priv);
- struct intel_uncore *uncore = gt->uncore;
u32 gu_misc_masked = GEN11_GU_MISC_GSE;
+ struct intel_gt *gt;
+ unsigned int i;
- gen11_gt_irq_postinstall(gt);
+ for_each_gt(gt, dev_priv, i) {
+ gen11_gt_irq_postinstall(gt);
- GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
+ GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_, ~gu_misc_masked,
+ gu_misc_masked);
+ }
if (HAS_DISPLAY(dev_priv)) {
icp_irq_postinstall(dev_priv);
@@ -3437,8 +3443,8 @@ static void dg1_irq_postinstall(struct drm_i915_private
*dev_priv)
GEN11_DISPLAY_IRQ_ENABLE);
}
- dg1_master_intr_enable(uncore->regs);
- intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
+ dg1_master_intr_enable(to_gt(dev_priv)->uncore->regs);
+ intel_uncore_posting_read(to_gt(dev_priv)->uncore, DG1_MSTR_TILE_INTR);
}
static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
--
2.34.1
[Intel-gfx] [PATCH v3 2/5] drm/i915/gt: generate per tile debugfs files
From: Andi Shyti
In the view of multi-gt we want independent per gt debug files.
In debugfs create gt0/ gt1/ ... gtN/ for tile related files. In 4
tiles, the debugfs would be structured as follows:
/sys/kernel/debug/dri
└── 0
├── gt0
│ ├── drpc
│ ├── engines
│ ├── forcewake
│ ├── frequency
│ └── rps_boost
├── gt1
│ ├── drpc
│ ├── engines
│ ├── forcewake
│ ├── frequency
│ └── rps_boost
├── gt2
│ ├── drpc
│ ├── engines
│ ├── forcewake
│ ├── frequency
│ └── rps_boost
└─- gt3
: ├── drpc
: ├── engines
: ├── forcewake
├── frequency
└── rps_boost
v2: Fix the missed assignment dbgfs_node
Cc: Tvrtko Ursulin
Signed-off-by: Andi Shyti
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c| 4 +++-
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 5 -
drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c | 2 ++
4 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
index 5fc2df01aa0d..4dc23b8d3aa2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
@@ -83,11 +83,13 @@ static void gt_debugfs_register(struct intel_gt *gt, struct
dentry *root)
void intel_gt_debugfs_register(struct intel_gt *gt)
{
struct dentry *root;
+ char gtname[4];
if (!gt->i915->drm.primary->debugfs_root)
return;
- root = debugfs_create_dir("gt", gt->i915->drm.primary->debugfs_root);
+ snprintf(gtname, sizeof(gtname), "gt%u", gt->info.id);
+ root = debugfs_create_dir(gtname, gt->i915->drm.primary->debugfs_root);
if (IS_ERR(root))
return;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index bb4dfe707a7d..e46aac1a41e6 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -42,6 +42,8 @@ struct intel_guc {
/** @capture: the error-state-capture module's data and objects */
struct intel_guc_state_capture *capture;
+ struct dentry *dbgfs_node;
+
/** @sched_engine: Global engine used to submit requests to GuC */
struct i915_sched_engine *sched_engine;
/**
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 195db8c9d420..55bc8b55fbc0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -542,8 +542,11 @@ static int guc_log_relay_create(struct intel_guc_log *log)
*/
n_subbufs = 8;
+ if (!guc->dbgfs_node)
+ return -ENOENT;
+
guc_log_relay_chan = relay_open("guc_log",
- i915->drm.primary->debugfs_root,
+ guc->dbgfs_node,
subbuf_size, n_subbufs,
_callbacks, i915);
if (!guc_log_relay_chan) {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
index 284d6fbc2d08..2f93cc4e408a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
@@ -54,6 +54,8 @@ void intel_uc_debugfs_register(struct intel_uc *uc, struct
dentry *gt_root)
if (IS_ERR(root))
return;
+ uc->guc.dbgfs_node = root;
+
intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), uc);
intel_guc_debugfs_register(>guc, root);
--
2.34.1
[Intel-gfx] [PATCH v3 4/5] drm/i915/fbdev: lock the fbdev obj before vma pin
From: Tejas Upadhyay
lock the fbdev obj before calling into
i915_vma_pin_iomap(). This helps to solve below :
<7>[ 93.563308] i915 :00:02.0: [drm:intelfb_create [i915]] no BIOS fb,
allocating a new one
<4>[ 93.581844] [ cut here ]
<4>[ 93.581855] WARNING: CPU: 12 PID: 625 at
drivers/gpu/drm/i915/gem/i915_gem_pages.c:424
i915_gem_object_pin_map+0x152/0x1c0 [i915]
Fixes: f0b6b01b3efe ("drm/i915: Add ww context to intel_dpt_pin, v2.")
Cc: Chris Wilson
Cc: Matthew Auld
Cc: Maarten Lankhorst
Signed-off-by: Tejas Upadhyay
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 24 --
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 3659350061a7..2766d7ef0128 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -210,6 +210,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
bool prealloc = false;
void __iomem *vaddr;
struct drm_i915_gem_object *obj;
+ struct i915_gem_ww_ctx ww;
int ret;
mutex_lock(>hpd_lock);
@@ -283,13 +284,24 @@ static int intelfb_create(struct drm_fb_helper *helper,
info->fix.smem_len = vma->size;
}
- vaddr = i915_vma_pin_iomap(vma);
- if (IS_ERR(vaddr)) {
- drm_err(_priv->drm,
- "Failed to remap framebuffer into virtual memory
(%pe)\n", vaddr);
- ret = PTR_ERR(vaddr);
- goto out_unpin;
+ for_i915_gem_ww(, ret, false) {
+ ret = i915_gem_object_lock(vma->obj, );
+
+ if (ret)
+ continue;
+
+ vaddr = i915_vma_pin_iomap(vma);
+ if (IS_ERR(vaddr)) {
+ drm_err(_priv->drm,
+ "Failed to remap framebuffer into
virtual memory (%pe)\n", vaddr);
+ ret = PTR_ERR(vaddr);
+ continue;
+ }
}
+
+ if (ret)
+ goto out_unpin;
+
info->screen_base = vaddr;
info->screen_size = vma->size;
--
2.34.1
[Intel-gfx] [PATCH v3 5/5] drm/i915/display/mtl: Program latch to phy reset
From: José Roberto de Souza
Latch reset of phys during DC9 and when driver is unloaded to avoid
phy reset.
Specification ask us to program it closer to the step that enables
DC9 in DC_STATE_EN but doing this way allow us to sanitize the phy
latch during driver load.
BSpec: 49197
Reviewed-by: Matt Roper
Signed-off-by: José Roberto de Souza
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/display/intel_display_power.c | 8
drivers/gpu/drm/i915/i915_reg.h| 2 ++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 743b919bb2cf..50098c77e3be 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1624,6 +1624,10 @@ static void icl_display_core_init(struct
drm_i915_private *dev_priv,
intel_power_well_enable(dev_priv, well);
mutex_unlock(_domains->lock);
+ if (DISPLAY_VER(dev_priv) == 14)
+ intel_de_rmw(dev_priv, DC_STATE_EN,
+HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH, 0);
+
/* 4. Enable CDCLK. */
intel_cdclk_init_hw(dev_priv);
@@ -1677,6 +1681,10 @@ static void icl_display_core_uninit(struct
drm_i915_private *dev_priv)
/* 3. Disable CD clock */
intel_cdclk_uninit_hw(dev_priv);
+ if (DISPLAY_VER(dev_priv) == 14)
+ intel_de_rmw(dev_priv, DC_STATE_EN, 0,
+HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH);
+
/*
* 4. Disable Power Well 1 (PG1).
*The AUX IO power wells are toggled on demand, so they are already
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7c9ac5b43831..fa1905cc5a99 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7360,6 +7360,8 @@ enum skl_power_gate {
#define DC_STATE_DISABLE 0
#define DC_STATE_EN_DC3CO REG_BIT(30)
#define DC_STATE_DC3CO_STATUS REG_BIT(29)
+#define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21)
+#define HOLD_PHY_PG1_LATCHREG_BIT(20)
#define DC_STATE_EN_UPTO_DC5 (1 << 0)
#define DC_STATE_EN_DC9 (1 << 3)
#define DC_STATE_EN_UPTO_DC6 (2 << 0)
--
2.34.1
[Intel-gfx] [PATCH v3 0/5] Misc Meteorlake patches
This series adds misc MTL patches. This is a new rev of earlier series with dropped CCS patches. Review feedback for other patches included. Andi Shyti (1): drm/i915/gt: generate per tile debugfs files José Roberto de Souza (1): drm/i915/display/mtl: Program latch to phy reset Radhakrishna Sripada (2): drm/i915/mtl: Fix Wa_16015201720 implementation drm/i915/mtl: make IRQ reset and postinstall multi-gt aware Tejas Upadhyay (1): drm/i915/fbdev: lock the fbdev obj before vma pin .../drm/i915/display/intel_display_power.c| 8 + drivers/gpu/drm/i915/display/intel_dmc.c | 26 drivers/gpu/drm/i915/display/intel_fbdev.c| 24 +++ drivers/gpu/drm/i915/gt/intel_gt_debugfs.c| 4 ++- drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 ++ drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 5 +++- drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c | 2 ++ drivers/gpu/drm/i915/i915_irq.c | 30 +++ drivers/gpu/drm/i915/i915_reg.h | 12 ++-- 9 files changed, 85 insertions(+), 28 deletions(-) -- 2.34.1
[Intel-gfx] [PATCH v3 1/5] drm/i915/mtl: Fix Wa_16015201720 implementation
The commit 2357f2b271ad ("drm/i915/mtl: Initial display workarounds")
extended the workaround Wa_16015201720 to MTL. However the registers
that the original WA implemented moved for MTL.
Implement the workaround with the correct register.
v3: Skip clock gating for pipe C, D DMC's and fix the title
Fixes: 2357f2b271ad ("drm/i915/mtl: Initial display workarounds")
Cc: Matt Atwood
Cc: Lucas De Marchi
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/display/intel_dmc.c | 26 +++-
drivers/gpu/drm/i915/i915_reg.h | 10 ++---
2 files changed, 28 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index f70ada2357dc..b4283cf319f2 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -389,15 +389,12 @@ static void disable_all_event_handlers(struct
drm_i915_private *i915)
}
}
-static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
+static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool
enable)
{
enum pipe pipe;
- if (DISPLAY_VER(i915) < 13)
- return;
-
/*
-* Wa_16015201720:adl-p,dg2, mtl
+* Wa_16015201720:adl-p,dg2
* The WA requires clock gating to be disabled all the time
* for pipe A and B.
* For pipe C and D clock gating needs to be disabled only
@@ -413,6 +410,25 @@ static void pipedmc_clock_gating_wa(struct
drm_i915_private *i915, bool enable)
PIPEDMC_GATING_DIS, 0);
}
+static void mtl_pipedmc_clock_gating_wa(struct drm_i915_private *i915)
+{
+ /*
+* Wa_16015201720
+* The WA requires clock gating to be disabled all the time
+* for pipe A and B.
+*/
+ intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0,
+MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B);
+}
+
+static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
+{
+ if (DISPLAY_VER(i915) >= 14 && enable)
+ return mtl_pipedmc_clock_gating_wa(i915);
+ else if (DISPLAY_VER(i915) == 13)
+ return adlp_pipedmc_clock_gating_wa(i915, enable);
+}
+
void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe)
{
enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1efa655fb68..7c9ac5b43831 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1794,9 +1794,13 @@
* GEN9 clock gating regs
*/
#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
-#define DARBF_GATING_DIS (1 << 27)
-#define PWM2_GATING_DIS (1 << 14)
-#define PWM1_GATING_DIS (1 << 13)
+#define DARBF_GATING_DIS REG_BIT(27)
+#define MTL_PIPEDMC_GATING_DIS_A REG_BIT(15)
+#define MTL_PIPEDMC_GATING_DIS_B REG_BIT(14)
+#define PWM2_GATING_DIS REG_BIT(14)
+#define MTL_PIPEDMC_GATING_DIS_C REG_BIT(13)
+#define PWM1_GATING_DIS REG_BIT(13)
+#define MTL_PIPEDMC_GATING_DIS_D REG_BIT(12)
#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
#define TGL_VRH_GATING_DIS REG_BIT(31)
--
2.34.1
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4,1/5] drm/i915/power: move dc state members to struct i915_power_domains
== Series Details == Series: series starting with [v4,1/5] drm/i915/power: move dc state members to struct i915_power_domains URL : https://patchwork.freedesktop.org/series/114515/ State : warning == Summary == Error: dim checkpatch failed 873ffa5c0eff drm/i915/power: move dc state members to struct i915_power_domains b963889cc295 drm/i915/dmc: use has_dmc_id_fw() instead of poking dmc->dmc_info directly 20363d3a692a drm/i915/dmc: add i915_to_dmc() and dmc->i915 and use them -:66: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #66: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:529: + !intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)), total: 0 errors, 1 warnings, 0 checks, 272 lines checked 96d43b5f4dc6 drm/i915/dmc: allocate dmc structure dynamically b10c49af6653 drm/i915/dmc: mass rename dev_priv to i915
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/active: Fix misuse of non-idle barriers as fence trackers (rev6)
== Series Details == Series: drm/i915/active: Fix misuse of non-idle barriers as fence trackers (rev6) URL : https://patchwork.freedesktop.org/series/113950/ State : success == Summary == CI Bug Log - changes from CI_DRM_12799 -> Patchwork_113950v6 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113950v6/index.html Participating hosts (40 -> 40) -- Additional (1): fi-kbl-soraka Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_113950v6 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s0@smem: - bat-rplp-1: [PASS][1] -> [DMESG-WARN][2] ([i915#2867]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113950v6/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html * igt@gem_exec_suspend@basic-s3@smem: - bat-adlm-1: [PASS][3] -> [DMESG-WARN][4] ([i915#2867]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113950v6/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113950v6/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113950v6/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@i915_pm_rpm@basic-rte: - bat-adlp-6: [PASS][7] -> [ABORT][8] ([i915#7977]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-adlp-6/igt@i915_pm_...@basic-rte.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113950v6/bat-adlp-6/igt@i915_pm_...@basic-rte.html * igt@i915_selftest@live@client: - fi-kbl-soraka: NOTRUN -> [INCOMPLETE][9] ([i915#7913]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113950v6/fi-kbl-soraka/igt@i915_selftest@l...@client.html * igt@i915_selftest@live@execlists: - fi-bsw-nick:[PASS][10] -> [ABORT][11] ([i915#7913]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113950v6/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][12] ([i915#1886]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113950v6/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@requests: - bat-rpls-1: [PASS][13] -> [ABORT][14] ([i915#7694] / [i915#7911] / [i915#7982]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-1/igt@i915_selftest@l...@requests.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113950v6/bat-rpls-1/igt@i915_selftest@l...@requests.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-kbl-soraka: NOTRUN -> [SKIP][15] ([fdo#109271]) +16 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113950v6/fi-kbl-soraka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html Possible fixes * igt@i915_selftest@live@migrate: - bat-atsm-1: [DMESG-FAIL][16] ([i915#7699]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-atsm-1/igt@i915_selftest@l...@migrate.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113950v6/bat-atsm-1/igt@i915_selftest@l...@migrate.html Warnings * igt@i915_selftest@live@slpc: - bat-rpls-2: [DMESG-FAIL][18] ([i915#6997] / [i915#7913]) -> [DMESG-FAIL][19] ([i915#6367] / [i915#7913]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-2/igt@i915_selftest@l...@slpc.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113950v6/bat-rpls-2/igt@i915_selftest@l...@slpc.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997 [i915#7694]: https://gitlab.freedesktop.org/drm/intel/issues/7694 [i915#7699]:
Re: [Intel-gfx] [PATCH v2] drm/i915/mtl: Apply Wa_14017073508 for MTL Media Step
On Wed, Mar 01, 2023 at 03:42:51PM +0530, Badal Nilawar wrote:
> Apply Wa_14017073508 for MTL Media step instead of graphics step.
>
> v2: Use Media stepping instead of SoC die stepping (Matt)
>
> Bspec: 66623
>
> Fixes: 8f70f1ec587d ("drm/i915/mtl: Add Wa_14017073508 for SAMedia")
> Signed-off-by: Badal Nilawar
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++--
> drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> index cef3d6f5c34e..a14f23b3355a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> @@ -29,7 +29,7 @@
> static void mtl_media_busy(struct intel_gt *gt)
> {
> /* Wa_14017073508: mtl */
> - if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) &&
> + if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
> gt->type == GT_MEDIA)
> snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE,
> PCODE_MBOX_GT_STATE_MEDIA_BUSY,
> @@ -39,7 +39,7 @@ static void mtl_media_busy(struct intel_gt *gt)
> static void mtl_media_idle(struct intel_gt *gt)
> {
> /* Wa_14017073508: mtl */
> - if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) &&
> + if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
> gt->type == GT_MEDIA)
> snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE,
> PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY,
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
> index fcf51614f9a4..a53a995c3950 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
> @@ -19,7 +19,7 @@ static bool __guc_rc_supported(struct intel_guc *guc)
>* Do not enable gucrc to avoid additional interrupts which
>* may disrupt pcode wa.
>*/
> - if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) &&
> + if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
> gt->type == GT_MEDIA)
> return false;
>
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
[Intel-gfx] ✓ Fi.CI.BAT: success for Some debugfs refactoring and improvements
== Series Details == Series: Some debugfs refactoring and improvements URL : https://patchwork.freedesktop.org/series/114510/ State : success == Summary == CI Bug Log - changes from CI_DRM_12799 -> Patchwork_114510v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114510v1/index.html Participating hosts (40 -> 39) -- Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_114510v1 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@gt_heartbeat: - fi-apl-guc: [PASS][1] -> [DMESG-FAIL][2] ([i915#5334]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114510v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_pm: - bat-adln-1: [PASS][3] -> [DMESG-FAIL][4] ([i915#4258]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-adln-1/igt@i915_selftest@live@gt_pm.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114510v1/bat-adln-1/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@guc: - bat-rpls-2: [PASS][5] -> [DMESG-WARN][6] ([i915#7852]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-2/igt@i915_selftest@l...@guc.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114510v1/bat-rpls-2/igt@i915_selftest@l...@guc.html * igt@i915_selftest@live@requests: - bat-rpls-1: [PASS][7] -> [ABORT][8] ([i915#7694] / [i915#7911] / [i915#7982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-1/igt@i915_selftest@l...@requests.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114510v1/bat-rpls-1/igt@i915_selftest@l...@requests.html Possible fixes * igt@i915_pm_rps@basic-api: - bat-rpls-2: [SKIP][9] ([i915#6621]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-2/igt@i915_pm_...@basic-api.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114510v1/bat-rpls-2/igt@i915_pm_...@basic-api.html - bat-dg1-6: [SKIP][11] ([i915#6621]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-dg1-6/igt@i915_pm_...@basic-api.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114510v1/bat-dg1-6/igt@i915_pm_...@basic-api.html - bat-adlp-6: [SKIP][13] ([i915#6621]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-adlp-6/igt@i915_pm_...@basic-api.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114510v1/bat-adlp-6/igt@i915_pm_...@basic-api.html - bat-atsm-1: [SKIP][15] ([i915#6621]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-atsm-1/igt@i915_pm_...@basic-api.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114510v1/bat-atsm-1/igt@i915_pm_...@basic-api.html - bat-dg2-11: [SKIP][17] ([i915#6621]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-dg2-11/igt@i915_pm_...@basic-api.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114510v1/bat-dg2-11/igt@i915_pm_...@basic-api.html - bat-dg2-8: [SKIP][19] ([i915#6621]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-dg2-8/igt@i915_pm_...@basic-api.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114510v1/bat-dg2-8/igt@i915_pm_...@basic-api.html - bat-adlm-1: [SKIP][21] ([i915#6621]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-adlm-1/igt@i915_pm_...@basic-api.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114510v1/bat-adlm-1/igt@i915_pm_...@basic-api.html - bat-rpls-1: [SKIP][23] ([i915#6621]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-1/igt@i915_pm_...@basic-api.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114510v1/bat-rpls-1/igt@i915_pm_...@basic-api.html - bat-dg1-7: [SKIP][25] ([i915#6621]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-dg1-7/igt@i915_pm_...@basic-api.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114510v1/bat-dg1-7/igt@i915_pm_...@basic-api.html - bat-adlp-9: [SKIP][27] ([i915#6621]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-adlp-9/igt@i915_pm_...@basic-api.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114510v1/bat-adlp-9/igt@i915_pm_...@basic-api.html - bat-rplp-1: [SKIP][29] ([i915#6621]) -> [PASS][30] [29]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Some debugfs refactoring and improvements
== Series Details == Series: Some debugfs refactoring and improvements URL : https://patchwork.freedesktop.org/series/114510/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [PATCH v5 17/19] vfio: Add VFIO_DEVICE_AT[DE]TACH_IOMMUFD_PT
On Wed, Mar 01, 2023 at 02:04:00PM +, Liu, Yi L wrote:
> diff --git a/drivers/vfio/group.c b/drivers/vfio/group.c
> index 2a13442add43..ed3ffe7ceb3f 100644
> --- a/drivers/vfio/group.c
> +++ b/drivers/vfio/group.c
> @@ -777,6 +777,11 @@ void vfio_device_group_unregister(struct vfio_device
> *device)
> mutex_unlock(>group->device_lock);
> }
>
> +bool vfio_device_group_uses_container(struct vfio_device *device)
> +{
> + return READ_ONCE(device->group->container);
> +}
As I said this should take in the vfio_device_file because as long as
a vfio_device_file exists then group->contianer is required to be stable.
> diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
> index 121a75fadceb..4b5b17e8aaa1 100644
> --- a/drivers/vfio/vfio_main.c
> +++ b/drivers/vfio/vfio_main.c
> @@ -422,9 +422,22 @@ static int vfio_device_first_open(struct
> vfio_device_file *df)
> if (!try_module_get(device->dev->driver->owner))
> return -ENODEV;
>
> + /*
> + * The handling here depends on what the user is using.
> + *
> + * If user uses iommufd in the group compat mode or the
> + * cdev path, call vfio_iommufd_bind().
> + *
> + * If user uses container in the group legacy mode, call
> + * vfio_device_group_use_iommu().
> + *
> + * If user doesn't use iommufd nor container, this is
> + * the noiommufd mode in the cdev path, nothing needs
> + * to be done here just go ahead to open device.
> + */
> if (iommufd)
> ret = vfio_iommufd_bind(device, iommufd);
> - else
> + else if (vfio_device_group_uses_container(device))
> ret = vfio_device_group_use_iommu(device);
But yes, this makes alot more sense..
Jason
Re: [Intel-gfx] [PATCH v5 16/19] vfio: Add VFIO_DEVICE_BIND_IOMMUFD
On Wed, Mar 01, 2023 at 09:19:07AM +, Liu, Yi L wrote:
> > From: Liu, Yi L
> > Sent: Monday, February 27, 2023 7:12 PM
> [...]
> > +long vfio_device_ioctl_bind_iommufd(struct vfio_device_file *df,
> > + unsigned long arg)
> > +{
> > + struct vfio_device *device = df->device;
> > + struct vfio_device_bind_iommufd bind;
> > + struct iommufd_ctx *iommufd = NULL;
> > + unsigned long minsz;
> > + int ret;
> > +
> > + minsz = offsetofend(struct vfio_device_bind_iommufd, out_devid);
> > +
> > + if (copy_from_user(, (void __user *)arg, minsz))
> > + return -EFAULT;
> > +
> > + if (bind.argsz < minsz || bind.flags)
> > + return -EINVAL;
> > +
> > + if (!device->ops->bind_iommufd)
> > + return -ENODEV;
>
> Hi Jason,
>
> Per the comment in vfio_iommufd_bind(), such device driver
> won't provide .bind_iommufd(). So shall we allow this ioctl
> to go longer to call .open_device() instead of failing it here?
> I think we need to allow it to go further. E.g. leave the check
> to be in vfio_iommufd_bind(). Otherwise, user may not able
> to use such devices. Is it?
You are thinking about the crazy mdev samples?
We should probably just change them to provide a 'no dma' set of ops.
> > +struct vfio_device_bind_iommufd {
> > + __u32 argsz;
> > + __u32 flags;
> > + __aligned_u64 dev_cookie;
> > + __s32 iommufd;
> > + __u32 out_devid;
>
> As above, for the devices that do not do DMA, there is no .bind_iommufd
> op, hence no iommufd_device generated. This means no good value
> can be filled in this out_devid field. So this field is optional. Only
> for the devices which do DMA, should this out_devid field return a
> valid ID otherwise an invalid ID would be filled (e.g. value #0 is an
> invalid value in the iommufd object id pool). Userspace needs to
> check if the out_devid is valid or not before use. This ID can be further
> used in iommufd uAPIs like IOMMU_HWPT_ALLOC, IOMMU_DEVICE_GET_INFO
> and etc.
I would say create an access and harmonize the no-DMA devices with the
emulated devices.
What should we return here anyhow if an access was created?
Jason
[Intel-gfx] [PATCH v3 2/2] drm/i915: Reject wm levels that exceed vblank time
From: Ville Syrjälä
The pipe needs a certain amount of time during vblank to prefill
sufficiently. If the vblank is too short the relevant watermark
level must be disabled.
Start implementing the necessary calculations to check this.
Scaler and DSC prefill are left out for now as handling those
is not entirely trivial.
Also the PSR latency reporting override chicken bits would
need to be correctly configured based on the results of these
calculations. Just add some FIXMEs for now.
TODO: bspec isn't exactly crystal clear in its explanations
so quite a few open questions remain...
v2: Skip inacive pipes
Handle SAGV latency
v3: Rebase
Reviewed-by: Jouni Högander
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_watermark.c | 117 ++-
1 file changed, 115 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index 7d49a42b9d90..f76a27f0091f 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -12,6 +12,7 @@
#include "intel_atomic.h"
#include "intel_atomic_plane.h"
#include "intel_bw.h"
+#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_display.h"
#include "intel_display_power.h"
@@ -721,7 +722,7 @@ static unsigned int skl_wm_latency(struct drm_i915_private
*i915, int level,
skl_watermark_ipc_enabled(i915))
latency += 4;
- if (skl_needs_memory_bw_wa(i915) && wp->x_tiled)
+ if (skl_needs_memory_bw_wa(i915) && wp && wp->x_tiled)
latency += 15;
return latency;
@@ -2201,6 +2202,118 @@ static int icl_build_plane_wm(struct intel_crtc_state
*crtc_state,
return 0;
}
+static bool
+skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
+ int wm0_lines, int latency)
+{
+ const struct drm_display_mode *adjusted_mode =
+ _state->hw.adjusted_mode;
+
+ /* FIXME missing scaler and DSC pre-fill time */
+ return crtc_state->framestart_delay +
+ intel_usecs_to_scanlines(adjusted_mode, latency) +
+ wm0_lines >
+ adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
+}
+
+static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum plane_id plane_id;
+ int wm0_lines = 0;
+
+ for_each_plane_id_on_crtc(crtc, plane_id) {
+ const struct skl_plane_wm *wm =
_state->wm.skl.optimal.planes[plane_id];
+
+ /* FIXME what about !skl_wm_has_lines() platforms? */
+ wm0_lines = max_t(int, wm0_lines, wm->wm[0].lines);
+ }
+
+ return wm0_lines;
+}
+
+static int skl_max_wm_level_for_vblank(struct intel_crtc_state *crtc_state,
+ int wm0_lines)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ int level;
+
+ for (level = i915->display.wm.num_levels - 1; level >= 0; level--) {
+ int latency;
+
+ /*
+* FIXME is it correct to use 0 latency for wm0 here?
+* FIXME should we care about the latency w/a's?
+* FIXME what if we don't have latency for all levels?
+*/
+ latency = level == 0 ?
+ 0 : skl_wm_latency(i915, level, NULL);
+
+ if (!skl_is_vblank_too_short(crtc_state, wm0_lines, latency))
+ return level;
+ }
+
+ return -EINVAL;
+}
+
+static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ int wm0_lines, level;
+
+ if (!crtc_state->hw.active)
+ return 0;
+
+ wm0_lines = skl_max_wm0_lines(crtc_state);
+
+ level = skl_max_wm_level_for_vblank(crtc_state, wm0_lines);
+ if (level < 0)
+ return level;
+
+ /*
+* FIXME PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_*
+* based on whether we're limited by the vblank duration.
+*
+* FIXME also related to skl+ w/a 1136 (also unimplemented as of
+* now) perhaps?
+*/
+
+ for (level++; level < i915->display.wm.num_levels; level++) {
+ enum plane_id plane_id;
+
+ for_each_plane_id_on_crtc(crtc, plane_id) {
+ struct skl_plane_wm *wm =
+ _state->wm.skl.optimal.planes[plane_id];
+
+ /*
+* FIXME just clear enable or flag the entire
+* thing as bad via min_ddb_alloc=U16_MAX?
+*/
+
[Intel-gfx] [PATCH v3 1/2] drm/i915: Extract skl_wm_latency()
From: Ville Syrjälä
Extract the skl+ wm latency determination into a small helper
so that everyone has the same idea what the latency should be.
This introduces a slight functional change in that
skl_cursor_allocation() will now start to account for the
extra 4 usec that the kbk/cfl/cml IPC w/a adds.
v2: Rebase
Reviewed-by: Jouni Högander
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_watermark.c | 40 +---
1 file changed, 26 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index 1300965d328a..7d49a42b9d90 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -705,6 +705,28 @@ static void skl_compute_plane_wm(const struct
intel_crtc_state *crtc_state,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */);
+static unsigned int skl_wm_latency(struct drm_i915_private *i915, int level,
+ const struct skl_wm_params *wp)
+{
+ unsigned int latency = i915->display.wm.skl_latency[level];
+
+ if (latency == 0)
+ return 0;
+
+ /*
+* WaIncreaseLatencyIPCEnabled: kbl,cfl
+* Display WA #1141: kbl,cfl
+*/
+ if ((IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) &&
+ skl_watermark_ipc_enabled(i915))
+ latency += 4;
+
+ if (skl_needs_memory_bw_wa(i915) && wp->x_tiled)
+ latency += 15;
+
+ return latency;
+}
+
static unsigned int
skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
int num_active)
@@ -724,7 +746,7 @@ skl_cursor_allocation(const struct intel_crtc_state
*crtc_state,
drm_WARN_ON(>drm, ret);
for (level = 0; level < i915->display.wm.num_levels; level++) {
- unsigned int latency = i915->display.wm.skl_latency[level];
+ unsigned int latency = skl_wm_latency(i915, level, );
skl_compute_plane_wm(crtc_state, plane, level, latency, ,
, );
if (wm.min_ddb_alloc == U16_MAX)
@@ -1840,17 +1862,6 @@ static void skl_compute_plane_wm(const struct
intel_crtc_state *crtc_state,
return;
}
- /*
-* WaIncreaseLatencyIPCEnabled: kbl,cfl
-* Display WA #1141: kbl,cfl
-*/
- if ((IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) &&
- skl_watermark_ipc_enabled(i915))
- latency += 4;
-
- if (skl_needs_memory_bw_wa(i915) && wp->x_tiled)
- latency += 15;
-
method1 = skl_wm_method1(i915, wp->plane_pixel_rate,
wp->cpp, latency, wp->dbuf_block_size);
method2 = skl_wm_method2(wp->plane_pixel_rate,
@@ -1977,7 +1988,7 @@ skl_compute_wm_levels(const struct intel_crtc_state
*crtc_state,
for (level = 0; level < i915->display.wm.num_levels; level++) {
struct skl_wm_level *result = [level];
- unsigned int latency = i915->display.wm.skl_latency[level];
+ unsigned int latency = skl_wm_latency(i915, level, wm_params);
skl_compute_plane_wm(crtc_state, plane, level, latency,
wm_params, result_prev, result);
@@ -1997,7 +2008,8 @@ static void tgl_compute_sagv_wm(const struct
intel_crtc_state *crtc_state,
unsigned int latency = 0;
if (i915->display.sagv.block_time_us)
- latency = i915->display.sagv.block_time_us +
i915->display.wm.skl_latency[0];
+ latency = i915->display.sagv.block_time_us +
+ skl_wm_latency(i915, 0, wm_params);
skl_compute_plane_wm(crtc_state, plane, 0, latency,
wm_params, [0],
--
2.39.2
[Intel-gfx] [PATCH v3 0/2] drm/i915: vblank stuff
From: Ville Syrjälä Remainder of the vblank length/start stuff, rebased to deal with the watermark max_level vs. num_level changes. Ville Syrjälä (2): drm/i915: Extract skl_wm_latency() drm/i915: Reject wm levels that exceed vblank time drivers/gpu/drm/i915/display/skl_watermark.c | 155 +-- 1 file changed, 140 insertions(+), 15 deletions(-) -- 2.39.2
Re: [Intel-gfx] [PATCH] drm/i915/dsi: fix DSS CTL register offsets for TGL+
On Wed, Mar 01, 2023 at 05:38:39PM +0200, Ville Syrjälä wrote: > On Wed, Mar 01, 2023 at 05:14:09PM +0200, Jani Nikula wrote: > > On TGL+ the DSS control registers are at different offsets, and there's > > one per pipe. Fix the offsets to fix dual link DSI for TGL+. > > > > There would be helpers for this in the DSC code, but just do the quick > > fix now for DSI. Long term, we should probably move all the DSS handling > > into intel_vdsc.c, so exporting the helpers seems counter-productive. > > I'm not entirely happy with intel_vdsc.c since it handles > both the hardware VDSC block (which includes DSS, and so > also uncompressed joiner and MSO), and also some actual > DSC calculations/etc. Might be nice to have a cleaner > split of some sort. > > That also reminds me that MSO+dsc/joiner is probably going > to fail miserably given that neither side knows about the > other and both poke the DSS registers. I suppose MSO+joiner should just be rejected outright since the splitter seems to sit before the joiner in the path. We'd need them to be the other way around. But MSO+DSC does look plausible. -- Ville Syrjälä Intel
Re: [Intel-gfx] [PATCH] drm/i915: Get HDR DPCD refresh timeout from VBT
On Wed, Mar 01, 2023 at 05:21:10PM +0200, Jani Nikula wrote:
> On Wed, 01 Mar 2023, "Hogander, Jouni" wrote:
> > On Mon, 2023-02-20 at 18:47 +0200, Ville Syrjala wrote:
> >> From: Ville Syrjälä
> >>
> >> Grab the HDR DPCD refresh timeout (time we need to wait after
> >> writing the sourc OUI before the HDR DPCD registers are ready)
> >> from the VBT.
> >>
> >> Windows doesn't even seem to have any default value for this,
> >> which is perhaps a bit weird since the VBT value is documented
> >> as TGL+ and I thought the HDR backlight stuff might already be
> >> used on earlier platforms. To play it safe I left the old
> >> hardcoded 30ms default in place. Digging through some internal
> >> stuff that seems to have been a number given by the vendor for
> >> one particularly slow TCON. Although I did see 50ms mentioned
> >> somewhere as well.
> >>
> >> Let's also include the value in the debug print to ease
> >> debugging, and toss in the customary connector id+name as well.
> >>
> >> The TGL Thinkpad T14 I have sets this to 0 btw. So the delay
> >> is now gone on this machine:
> >> [CONNECTOR:308:eDP-1] Detected Intel HDR backlight interface version
> >> 1
> >> [CONNECTOR:308:eDP-1] Using Intel proprietary eDP backlight controls
> >> [CONNECTOR:308:eDP-1] SDR backlight is controlled through PWM
> >> [CONNECTOR:308:eDP-1] Using native PCH PWM for backlight control
> >> (controller=0)
> >> [CONNECTOR:308:eDP-1] Using AUX HDR interface for backlight control
> >> (range 0..496)
> >> [CONNECTOR:308:eDP-1] Performing OUI wait (0 ms)
> >
> > Reviewed-by: Jouni Högander
>
> Cc: sta...@vger.kernel.org
>
> ?
Not aware of anythigng actually getting fixed by this. I suspect
it's usually more of an optimization since the original 30ms was
supposedly only needed by some especially slow TCONs.
>
> >
> >>
> >> Cc: Lyude Paul
> >> Signed-off-by: Ville Syrjälä
> >> ---
> >> drivers/gpu/drm/i915/display/intel_bios.c | 6 ++
> >> drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
> >> drivers/gpu/drm/i915/display/intel_dp.c | 9 +++--
> >> 3 files changed, 14 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> >> b/drivers/gpu/drm/i915/display/intel_bios.c
> >> index f35ef3675d39..f16887aed56d 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> >> @@ -1084,6 +1084,12 @@ parse_lfp_backlight(struct drm_i915_private
> >> *i915,
> >> panel->vbt.backlight.min_brightness = entry-
> >> >min_brightness;
> >> }
> >>
> >> + if (i915->display.vbt.version >= 239)
> >> + panel->vbt.backlight.hdr_dpcd_refresh_timeout =
> >> + DIV_ROUND_UP(backlight_data-
> >> >hdr_dpcd_refresh_timeout[panel_type], 100);
> >> + else
> >> + panel->vbt.backlight.hdr_dpcd_refresh_timeout = 30;
> >> +
> >> drm_dbg_kms(>drm,
> >> "VBT backlight PWM modulation frequency %u Hz, "
> >> "active %s, min brightness %u, level %u,
> >> controller %u\n",
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> >> b/drivers/gpu/drm/i915/display/intel_display_types.h
> >> index 748b0cd411fa..76f47ba3be45 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> >> @@ -326,6 +326,7 @@ struct intel_vbt_panel_data {
> >> struct {
> >> u16 pwm_freq_hz;
> >> u16 brightness_precision_bits;
> >> + u16 hdr_dpcd_refresh_timeout;
> >> bool present;
> >> bool active_low_pwm;
> >> u8 min_brightness; /* min_brightness/255 of max
> >> */
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> >> b/drivers/gpu/drm/i915/display/intel_dp.c
> >> index b77bd4565864..3734e7567230 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >> @@ -2293,10 +2293,15 @@ intel_edp_init_source_oui(struct intel_dp
> >> *intel_dp, bool careful)
> >>
> >> void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
> >> {
> >> + struct intel_connector *connector = intel_dp-
> >> >attached_connector;
> >> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> >>
> >> - drm_dbg_kms(>drm, "Performing OUI wait\n");
> >> - wait_remaining_ms_from_jiffies(intel_dp->last_oui_write, 30);
> >> + drm_dbg_kms(>drm, "[CONNECTOR:%d:%s] Performing OUI
> >> wait (%u ms)\n",
> >> + connector->base.base.id, connector->base.name,
> >> + connector-
> >> >panel.vbt.backlight.hdr_dpcd_refresh_timeout);
> >> +
> >> + wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,
> >> + connector-
> >> >panel.vbt.backlight.hdr_dpcd_refresh_timeout);
> >> }
> >>
> >> /* If the
Re: [Intel-gfx] [PATCH] drm/i915/dsi: fix DSS CTL register offsets for TGL+
On Wed, Mar 01, 2023 at 05:14:09PM +0200, Jani Nikula wrote:
> On TGL+ the DSS control registers are at different offsets, and there's
> one per pipe. Fix the offsets to fix dual link DSI for TGL+.
>
> There would be helpers for this in the DSC code, but just do the quick
> fix now for DSI. Long term, we should probably move all the DSS handling
> into intel_vdsc.c, so exporting the helpers seems counter-productive.
I'm not entirely happy with intel_vdsc.c since it handles
both the hardware VDSC block (which includes DSS, and so
also uncompressed joiner and MSO), and also some actual
DSC calculations/etc. Might be nice to have a cleaner
split of some sort.
That also reminds me that MSO+dsc/joiner is probably going
to fail miserably given that neither side knows about the
other and both poke the DSS registers.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8232
> Cc: Ville Syrjala
> Cc: sta...@vger.kernel.org
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 18 +++---
> 1 file changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index b5316715bb3b..5a17ab3f0d1a 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -277,9 +277,21 @@ static void configure_dual_link_mode(struct
> intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> + i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
> u32 dss_ctl1;
>
> - dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1);
> + /* FIXME: Move all DSS handling to intel_vdsc.c */
> + if (DISPLAY_VER(dev_priv) >= 12) {
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> +
> + dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
> + dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe);
> + } else {
> + dss_ctl1_reg = DSS_CTL1;
> + dss_ctl2_reg = DSS_CTL2;
> + }
> +
> + dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg);
Side note: should get rid of this rmw to make sure the thing
fully configuerd the way we want...
Anyways, this seems fine for now:
Reviewed-by: Ville Syrjälä
> dss_ctl1 |= SPLITTER_ENABLE;
> dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
> dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
> @@ -299,14 +311,14 @@ static void configure_dual_link_mode(struct
> intel_encoder *encoder,
>
> dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
> dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
> - intel_de_rmw(dev_priv, DSS_CTL2, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
> + intel_de_rmw(dev_priv, dss_ctl2_reg,
> RIGHT_DL_BUF_TARGET_DEPTH_MASK,
>RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth));
> } else {
> /* Interleave */
> dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
> }
>
> - intel_de_write(dev_priv, DSS_CTL1, dss_ctl1);
> + intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1);
> }
>
> /* aka DSI 8X clock */
> --
> 2.39.1
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH] drm/i915: Get HDR DPCD refresh timeout from VBT
On Wed, 01 Mar 2023, "Hogander, Jouni" wrote:
> On Mon, 2023-02-20 at 18:47 +0200, Ville Syrjala wrote:
>> From: Ville Syrjälä
>>
>> Grab the HDR DPCD refresh timeout (time we need to wait after
>> writing the sourc OUI before the HDR DPCD registers are ready)
>> from the VBT.
>>
>> Windows doesn't even seem to have any default value for this,
>> which is perhaps a bit weird since the VBT value is documented
>> as TGL+ and I thought the HDR backlight stuff might already be
>> used on earlier platforms. To play it safe I left the old
>> hardcoded 30ms default in place. Digging through some internal
>> stuff that seems to have been a number given by the vendor for
>> one particularly slow TCON. Although I did see 50ms mentioned
>> somewhere as well.
>>
>> Let's also include the value in the debug print to ease
>> debugging, and toss in the customary connector id+name as well.
>>
>> The TGL Thinkpad T14 I have sets this to 0 btw. So the delay
>> is now gone on this machine:
>> [CONNECTOR:308:eDP-1] Detected Intel HDR backlight interface version
>> 1
>> [CONNECTOR:308:eDP-1] Using Intel proprietary eDP backlight controls
>> [CONNECTOR:308:eDP-1] SDR backlight is controlled through PWM
>> [CONNECTOR:308:eDP-1] Using native PCH PWM for backlight control
>> (controller=0)
>> [CONNECTOR:308:eDP-1] Using AUX HDR interface for backlight control
>> (range 0..496)
>> [CONNECTOR:308:eDP-1] Performing OUI wait (0 ms)
>
> Reviewed-by: Jouni Högander
Cc: sta...@vger.kernel.org
?
>
>>
>> Cc: Lyude Paul
>> Signed-off-by: Ville Syrjälä
>> ---
>> drivers/gpu/drm/i915/display/intel_bios.c | 6 ++
>> drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
>> drivers/gpu/drm/i915/display/intel_dp.c | 9 +++--
>> 3 files changed, 14 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
>> b/drivers/gpu/drm/i915/display/intel_bios.c
>> index f35ef3675d39..f16887aed56d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
>> @@ -1084,6 +1084,12 @@ parse_lfp_backlight(struct drm_i915_private
>> *i915,
>> panel->vbt.backlight.min_brightness = entry-
>> >min_brightness;
>> }
>>
>> + if (i915->display.vbt.version >= 239)
>> + panel->vbt.backlight.hdr_dpcd_refresh_timeout =
>> + DIV_ROUND_UP(backlight_data-
>> >hdr_dpcd_refresh_timeout[panel_type], 100);
>> + else
>> + panel->vbt.backlight.hdr_dpcd_refresh_timeout = 30;
>> +
>> drm_dbg_kms(>drm,
>> "VBT backlight PWM modulation frequency %u Hz, "
>> "active %s, min brightness %u, level %u,
>> controller %u\n",
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 748b0cd411fa..76f47ba3be45 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -326,6 +326,7 @@ struct intel_vbt_panel_data {
>> struct {
>> u16 pwm_freq_hz;
>> u16 brightness_precision_bits;
>> + u16 hdr_dpcd_refresh_timeout;
>> bool present;
>> bool active_low_pwm;
>> u8 min_brightness; /* min_brightness/255 of max
>> */
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index b77bd4565864..3734e7567230 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -2293,10 +2293,15 @@ intel_edp_init_source_oui(struct intel_dp
>> *intel_dp, bool careful)
>>
>> void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
>> {
>> + struct intel_connector *connector = intel_dp-
>> >attached_connector;
>> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>>
>> - drm_dbg_kms(>drm, "Performing OUI wait\n");
>> - wait_remaining_ms_from_jiffies(intel_dp->last_oui_write, 30);
>> + drm_dbg_kms(>drm, "[CONNECTOR:%d:%s] Performing OUI
>> wait (%u ms)\n",
>> + connector->base.base.id, connector->base.name,
>> + connector-
>> >panel.vbt.backlight.hdr_dpcd_refresh_timeout);
>> +
>> + wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,
>> + connector-
>> >panel.vbt.backlight.hdr_dpcd_refresh_timeout);
>> }
>>
>> /* If the device supports it, try to set the power state
>> appropriately */
>
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH] drm/i915/display: split out DSC and DSS registers
Relatively few places need the DSC and DSS register definitions. Move
them to intel_vdsc_regs.h.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c| 1 +
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_vdsc.c | 1 +
.../gpu/drm/i915/display/intel_vdsc_regs.h| 462 ++
drivers/gpu/drm/i915/i915_reg.h | 450 -
6 files changed, 466 insertions(+), 450 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_vdsc_regs.h
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index b5316715bb3b..9b83fdc89fa2 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -45,6 +45,7 @@
#include "intel_dsi_vbt.h"
#include "intel_panel.h"
#include "intel_vdsc.h"
+#include "intel_vdsc_regs.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index e5979427b38b..0c58f042cc7e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -68,6 +68,7 @@
#include "intel_sprite.h"
#include "intel_tc.h"
#include "intel_vdsc.h"
+#include "intel_vdsc_regs.h"
#include "intel_vrr.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a1fbdf32bd21..edbcb1273ca2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -116,6 +116,7 @@
#include "intel_tv.h"
#include "intel_vblank.h"
#include "intel_vdsc.h"
+#include "intel_vdsc_regs.h"
#include "intel_vga.h"
#include "intel_vrr.h"
#include "intel_wm.h"
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 207b2a648d32..09b32ffdc552 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -17,6 +17,7 @@
#include "intel_dsi.h"
#include "intel_qp_tables.h"
#include "intel_vdsc.h"
+#include "intel_vdsc_regs.h"
enum ROW_INDEX_BPP {
ROW_INDEX_6BPP = 0,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
new file mode 100644
index ..02cd89077eb6
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -0,0 +1,462 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef __INTEL_VDSC_REGS_H__
+#define __INTEL_VDSC_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+/* Display Stream Splitter Control */
+#define DSS_CTL1 _MMIO(0x67400)
+#define SPLITTER_ENABLE (1 << 31)
+#define JOINER_ENABLE (1 << 30)
+#define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
+#define DUAL_LINK_MODE_FRONTBACK (0 << 24)
+#define OVERLAP_PIXELS_MASK (0xf << 16)
+#define OVERLAP_PIXELS(pixels)((pixels) << 16)
+#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
+#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
+#define MAX_DL_BUFFER_TARGET_DEPTH0x5a0
+
+#define DSS_CTL2 _MMIO(0x67404)
+#define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
+#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
+#define RIGHT_DL_BUF_TARGET_DEPTH_MASK(0xfff << 0)
+#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
+
+#define _ICL_PIPE_DSS_CTL1_PB 0x78200
+#define _ICL_PIPE_DSS_CTL1_PC 0x78400
+#define ICL_PIPE_DSS_CTL1(pipe)_MMIO_PIPE((pipe) -
PIPE_B, \
+
_ICL_PIPE_DSS_CTL1_PB, \
+
_ICL_PIPE_DSS_CTL1_PC)
+#define BIG_JOINER_ENABLE (1 << 29)
+#define MASTER_BIG_JOINER_ENABLE (1 << 28)
+#define VGA_CENTERING_ENABLE (1 << 27)
+#define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
+#define SPLITTER_CONFIGURATION_2_SEGMENT
REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
+#define SPLITTER_CONFIGURATION_4_SEGMENT
REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
+#define UNCOMPRESSED_JOINER_MASTER(1 << 21)
+#define UNCOMPRESSED_JOINER_SLAVE (1 << 20)
+
+#define _ICL_PIPE_DSS_CTL2_PB 0x78204
+#define _ICL_PIPE_DSS_CTL2_PC 0x78404
+#define ICL_PIPE_DSS_CTL2(pipe)_MMIO_PIPE((pipe) -
PIPE_B, \
+
_ICL_PIPE_DSS_CTL2_PB, \
+
[Intel-gfx] [PATCH] drm/i915/dsi: fix DSS CTL register offsets for TGL+
On TGL+ the DSS control registers are at different offsets, and there's
one per pipe. Fix the offsets to fix dual link DSI for TGL+.
There would be helpers for this in the DSC code, but just do the quick
fix now for DSI. Long term, we should probably move all the DSS handling
into intel_vdsc.c, so exporting the helpers seems counter-productive.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8232
Cc: Ville Syrjala
Cc: sta...@vger.kernel.org
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index b5316715bb3b..5a17ab3f0d1a 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -277,9 +277,21 @@ static void configure_dual_link_mode(struct intel_encoder
*encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+ i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
u32 dss_ctl1;
- dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1);
+ /* FIXME: Move all DSS handling to intel_vdsc.c */
+ if (DISPLAY_VER(dev_priv) >= 12) {
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+
+ dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
+ dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe);
+ } else {
+ dss_ctl1_reg = DSS_CTL1;
+ dss_ctl2_reg = DSS_CTL2;
+ }
+
+ dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg);
dss_ctl1 |= SPLITTER_ENABLE;
dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
@@ -299,14 +311,14 @@ static void configure_dual_link_mode(struct intel_encoder
*encoder,
dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
- intel_de_rmw(dev_priv, DSS_CTL2, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
+ intel_de_rmw(dev_priv, dss_ctl2_reg,
RIGHT_DL_BUF_TARGET_DEPTH_MASK,
RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth));
} else {
/* Interleave */
dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
}
- intel_de_write(dev_priv, DSS_CTL1, dss_ctl1);
+ intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1);
}
/* aka DSI 8X clock */
--
2.39.1
Re: [Intel-gfx] [PATCH v2] drm/edid: Fix csync detailed mode parsing
On Wed, Mar 01, 2023 at 10:49:26AM +0200, Jani Nikula wrote: > On Tue, 28 Feb 2023, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Remove the bogus csync check and replace it with something that: > > - triggers for all forms of csync, not just the basic analog variant > > - actually populates the mode csync flags so that drivers can > > decide what to do with the mode > > > > Originally the code tried to outright reject csync, but that > > apparently broke some bogus LCD monitor that claimed to have > > a detailed mode that uses analog csync, despite also claiming > > the monitor only support separate sync: > > https://bugzilla.redhat.com/show_bug.cgi?id=540024 > > Potentially that monitor should just be quirked or something. > > > > Anyways, what we are dealing with now is some kind of funny i915 > > JSL machine with eDP where the panel claims to support a sensible > > 60Hz separate sync mode, and a 50Hz mode with bipolar analog > > csync. The 50Hz mode does not work so we want to not use it. > > Easiest way is to just correctly flag it as csync and the driver > > will reject it. > > > > TODO: or should we just reject any form of csync (or at least > > the analog variants) for digital display interfaces? > > > > v2: Grab digital csync polarity from hsync polarity bit (Jani) > > > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8146 > > Reviewed-by: Jani Nikula #v1 > > Yup. Fingers crossed. Thought it best to give this plenty of time to soak, so pushed to drm-misc-next. Thanks for the review. -- Ville Syrjälä Intel
Re: [Intel-gfx] [PATCH] drm/i915: Get HDR DPCD refresh timeout from VBT
On Mon, 2023-02-20 at 18:47 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Grab the HDR DPCD refresh timeout (time we need to wait after
> writing the sourc OUI before the HDR DPCD registers are ready)
> from the VBT.
>
> Windows doesn't even seem to have any default value for this,
> which is perhaps a bit weird since the VBT value is documented
> as TGL+ and I thought the HDR backlight stuff might already be
> used on earlier platforms. To play it safe I left the old
> hardcoded 30ms default in place. Digging through some internal
> stuff that seems to have been a number given by the vendor for
> one particularly slow TCON. Although I did see 50ms mentioned
> somewhere as well.
>
> Let's also include the value in the debug print to ease
> debugging, and toss in the customary connector id+name as well.
>
> The TGL Thinkpad T14 I have sets this to 0 btw. So the delay
> is now gone on this machine:
> [CONNECTOR:308:eDP-1] Detected Intel HDR backlight interface version
> 1
> [CONNECTOR:308:eDP-1] Using Intel proprietary eDP backlight controls
> [CONNECTOR:308:eDP-1] SDR backlight is controlled through PWM
> [CONNECTOR:308:eDP-1] Using native PCH PWM for backlight control
> (controller=0)
> [CONNECTOR:308:eDP-1] Using AUX HDR interface for backlight control
> (range 0..496)
> [CONNECTOR:308:eDP-1] Performing OUI wait (0 ms)
Reviewed-by: Jouni Högander
>
> Cc: Lyude Paul
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 6 ++
> drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 9 +++--
> 3 files changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index f35ef3675d39..f16887aed56d 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1084,6 +1084,12 @@ parse_lfp_backlight(struct drm_i915_private
> *i915,
> panel->vbt.backlight.min_brightness = entry-
> >min_brightness;
> }
>
> + if (i915->display.vbt.version >= 239)
> + panel->vbt.backlight.hdr_dpcd_refresh_timeout =
> + DIV_ROUND_UP(backlight_data-
> >hdr_dpcd_refresh_timeout[panel_type], 100);
> + else
> + panel->vbt.backlight.hdr_dpcd_refresh_timeout = 30;
> +
> drm_dbg_kms(>drm,
> "VBT backlight PWM modulation frequency %u Hz, "
> "active %s, min brightness %u, level %u,
> controller %u\n",
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 748b0cd411fa..76f47ba3be45 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -326,6 +326,7 @@ struct intel_vbt_panel_data {
> struct {
> u16 pwm_freq_hz;
> u16 brightness_precision_bits;
> + u16 hdr_dpcd_refresh_timeout;
> bool present;
> bool active_low_pwm;
> u8 min_brightness; /* min_brightness/255 of max
> */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index b77bd4565864..3734e7567230 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2293,10 +2293,15 @@ intel_edp_init_source_oui(struct intel_dp
> *intel_dp, bool careful)
>
> void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
> {
> + struct intel_connector *connector = intel_dp-
> >attached_connector;
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> - drm_dbg_kms(>drm, "Performing OUI wait\n");
> - wait_remaining_ms_from_jiffies(intel_dp->last_oui_write, 30);
> + drm_dbg_kms(>drm, "[CONNECTOR:%d:%s] Performing OUI
> wait (%u ms)\n",
> + connector->base.base.id, connector->base.name,
> + connector-
> >panel.vbt.backlight.hdr_dpcd_refresh_timeout);
> +
> + wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,
> + connector-
> >panel.vbt.backlight.hdr_dpcd_refresh_timeout);
> }
>
> /* If the device supports it, try to set the power state
> appropriately */
Re: [Intel-gfx] [PATCH v5 17/19] vfio: Add VFIO_DEVICE_AT[DE]TACH_IOMMUFD_PT
> From: Jason Gunthorpe
> Sent: Tuesday, February 28, 2023 10:38 PM
>
> On Tue, Feb 28, 2023 at 02:01:36PM +, Liu, Yi L wrote:
> > > From: Jason Gunthorpe
> > > Sent: Tuesday, February 28, 2023 9:44 PM
> > >
> > > On Tue, Feb 28, 2023 at 01:36:24PM +, Liu, Yi L wrote:
> > > > > From: Jason Gunthorpe
> > > > > Sent: Tuesday, February 28, 2023 9:26 PM
> > > > >
> > > > > On Tue, Feb 28, 2023 at 01:22:50PM +, Liu, Yi L wrote:
> > > > >
> > > > > > > A null iommufd pointer and a bound df flag is sufficient to see
> that
> > > > > > > it is compat mode.
> > > > > >
> > > > > > Hope df->is_cdev_device suits your expectation.:-) The code will
> look
> > > > > > like below:
> > > > >
> > > > > Yes, this is better.. However I'd suggest 'uses_container' as it is
> > > > > clearer what the special case is
> > > >
> > > > Surely doable. Need to add a helper like below:
> > > >
> > > > bool vfio_device_group_uses_container()
> > > > {
> > > > lockdep_assert_held(>group->group_lock);
> > > > return device->group->container;
> > > > }
> > >
> > > It should come from the df.
> > >
> > > If you have a df then by definition:
> > > smp_load_acquire(..) == false - Not bound
> > > df->device->iommufd_ctx != NULL - Using iommufd
> > > df->group->containter != NULL - Using legacy container
> > > all other cases - NO_IOMMU
> > >
> > > No locking required since all these cases after the smp_load_acquire
> > > must be fixed for the lifetime of the df.
> >
> > Do you mean the df->access_granted (introduced in patch 07) or a new
> > flag?
>
> yes
>
> > Following your suggestion, it seems a mandatory requirement to do the
> > smp_load_acquire(..) == false check first, and then call into the
> vfio_device_open()
> > which further calls vfio_device_first_open() to check the iommufd/
> > legacy container/noiommu stuffs. Is it?
>
> Figuring out if an open should happen or not is a different operation,
> you already build exclusion between cdev/group so we don't need to
> care about the open path.
Ok.
> > df->group->containter this may need a helper to avoid decoding group
> > field. May be just store container in df?
>
> At worst a flag, but a helper seems like a good idea anyhow, then it
> can be compiled out
I add a separate commit as below. vfio_device_group_uses_container() is
added.
>From 0ce86e6b71d1884e9f5de30ba23e3aa93cc84db9 Mon Sep 17 00:00:00 2001
From: Yi Liu
Date: Wed, 1 Mar 2023 02:24:43 -0800
Subject: [PATCH 15/22] vfio: Make vfio_device_first_open() to cover the
noiommu mode in cdev path
vfio_device_first_open() now covers the below two cases:
1) user uses iommufd (e.g. the group path in iommufd compat mode);
2) user uses container (e.g. the group path in legacy mode);
The above two paths have their own noiommu mode support accordingly.
The cdev path also uses iommufd, so for the case user provides a valid
iommufd, this helper is able to support it. But for noiommu mode, the
cdev path just provides a NULL iommufd. So this needs to be able to cover
it. As there is no special things to do for the cdev path in noiommu
mode, it can be covered by simply differentiate it from the container
case. If user is not using iommufd nor container, it is the noiommu
mode.
Signed-off-by: Yi Liu
---
drivers/vfio/group.c | 5 +
drivers/vfio/vfio.h | 1 +
drivers/vfio/vfio_main.c | 19 ---
3 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/drivers/vfio/group.c b/drivers/vfio/group.c
index 2a13442add43..ed3ffe7ceb3f 100644
--- a/drivers/vfio/group.c
+++ b/drivers/vfio/group.c
@@ -777,6 +777,11 @@ void vfio_device_group_unregister(struct vfio_device
*device)
mutex_unlock(>group->device_lock);
}
+bool vfio_device_group_uses_container(struct vfio_device *device)
+{
+ return READ_ONCE(device->group->container);
+}
+
int vfio_device_group_use_iommu(struct vfio_device *device)
{
struct vfio_group *group = device->group;
diff --git a/drivers/vfio/vfio.h b/drivers/vfio/vfio.h
index 68d35e1d7b87..e1f5a0310551 100644
--- a/drivers/vfio/vfio.h
+++ b/drivers/vfio/vfio.h
@@ -95,6 +95,7 @@ int vfio_device_set_group(struct vfio_device *device,
void vfio_device_remove_group(struct vfio_device *device);
void vfio_device_group_register(struct vfio_device *device);
void vfio_device_group_unregister(struct vfio_device *device);
+bool vfio_device_group_uses_container(struct vfio_device *device);
int vfio_device_group_use_iommu(struct vfio_device *device);
void vfio_device_group_unuse_iommu(struct vfio_device *device);
void vfio_device_group_close(struct vfio_device_file *df);
diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
index 121a75fadceb..4b5b17e8aaa1 100644
--- a/drivers/vfio/vfio_main.c
+++ b/drivers/vfio/vfio_main.c
@@ -422,9 +422,22 @@ static int vfio_device_first_open(struct vfio_device_file
*df)
if (!try_module_get(device->dev->driver->owner))
return
Re: [Intel-gfx] [PATCH v5 18/19] vfio: Compile group optionally
> From: Jason Gunthorpe > Sent: Tuesday, February 28, 2023 8:36 PM > > On Tue, Feb 28, 2023 at 06:00:09AM +, Liu, Yi L wrote: > > > From: Liu, Yi L > > > Sent: Monday, February 27, 2023 7:12 PM > > > > > > group code is not needed for vfio device cdev, so with vfio device cdev > > > introduced, the group infrastructures can be compiled out if only cdev > > > is needed. > > > > > > Signed-off-by: Yi Liu > > > --- > > > drivers/vfio/Kconfig | 14 + > > > drivers/vfio/Makefile | 2 +- > > > drivers/vfio/vfio.h | 72 > > > +++ > > > include/linux/vfio.h | 24 ++- > > > 4 files changed, 110 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/vfio/Kconfig b/drivers/vfio/Kconfig > > > index 169762316513..c3ab06c314ea 100644 > > > --- a/drivers/vfio/Kconfig > > > +++ b/drivers/vfio/Kconfig > > > @@ -4,6 +4,8 @@ menuconfig VFIO > > > select IOMMU_API > > > depends on IOMMUFD || !IOMMUFD > > > select INTERVAL_TREE > > > + select VFIO_GROUP if SPAPR_TCE_IOMMU > > > + select VFIO_DEVICE_CDEV if !VFIO_GROUP && (X86 || S390 || ARM > || ARM64) > > > > Got below warning when IOMMUFD=n, VFIO_GROUP=n. so may remove > > this select or needs to let VFIO_DEVICE_CDEV select IOMMUFD instead of > > depends on IOMMUFD. > > Add > > select VFIO_GROUP if !IOMMUFD Done. Regards, Yi Liu
Re: [Intel-gfx] [PATCH v5 14/19] vfio: Make vfio_device_open() single open for device cdev path
> From: Jason Gunthorpe > Sent: Tuesday, February 28, 2023 8:34 PM > > On Tue, Feb 28, 2023 at 03:11:34AM +, Liu, Yi L wrote: > > > From: Jason Gunthorpe > > > Sent: Tuesday, February 28, 2023 2:52 AM > > > > > > On Mon, Feb 27, 2023 at 03:11:30AM -0800, Yi Liu wrote: > > > > @@ -535,7 +542,8 @@ static int vfio_device_fops_release(struct > inode > > > *inode, struct file *filep) > > > > struct vfio_device_file *df = filep->private_data; > > > > struct vfio_device *device = df->device; > > > > > > > > - vfio_device_group_close(df); > > > > + if (!df->is_cdev_device) > > > > + vfio_device_group_close(df); > > > > > > This hunk should go in another patch > > > > Patch 15 or 16? Which one is your preference? To me, I guess patch > > 15 is better since the user may open cdev fds after it. But its release > > op should not call vfio_device_group_close(); > > It should go with the patch that allows creating the struct file > withotu calling vfio_device_group_open() Sure. I moved it to the patch which adds cdev as this patch starts to have df->is_cdev_device == 1. Regards, Yi Liu
[Intel-gfx] [PATCH 6/6] drm/i915/clock: mass rename dev_priv to i915
Follow the contemporary naming style. Include some indentation fixes
while at it on the affected statements.
One function needs to keep using dev_priv due to implicit dev_priv usage
in a macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_clock_gating.c | 589 +++---
1 file changed, 296 insertions(+), 293 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c
b/drivers/gpu/drm/i915/intel_clock_gating.c
index 8cfc19b48760..2c5302bcba19 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -44,9 +44,9 @@ struct drm_i915_clock_gating_funcs {
void (*init_clock_gating)(struct drm_i915_private *i915);
};
-static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
+static void gen9_init_clock_gating(struct drm_i915_private *i915)
{
- if (HAS_LLC(dev_priv)) {
+ if (HAS_LLC(i915)) {
/*
* WaCompressedResourceDisplayNewHashMode:skl,kbl
* Display WA #0390: skl,kbl
@@ -54,41 +54,42 @@ static void gen9_init_clock_gating(struct drm_i915_private
*dev_priv)
* Must match Sampler, Pixel Back End, and Media. See
* WaCompressedResourceSamplerPbeMediaNewHashMode.
*/
- intel_uncore_rmw(_priv->uncore, CHICKEN_PAR1_1, 0,
SKL_DE_COMPRESSED_HASH_MODE);
+ intel_uncore_rmw(>uncore, CHICKEN_PAR1_1, 0,
SKL_DE_COMPRESSED_HASH_MODE);
}
/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
- intel_uncore_rmw(_priv->uncore, CHICKEN_PAR1_1, 0,
SKL_EDP_PSR_FIX_RDWRAP);
+ intel_uncore_rmw(>uncore, CHICKEN_PAR1_1, 0,
SKL_EDP_PSR_FIX_RDWRAP);
/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
- intel_uncore_rmw(_priv->uncore, GEN8_CHICKEN_DCPR_1, 0,
MASK_WAKEMEM);
+ intel_uncore_rmw(>uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);
/*
* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
* Display WA #0859: skl,bxt,kbl,glk,cfl
*/
- intel_uncore_rmw(_priv->uncore, DISP_ARB_CTL, 0,
DISP_FBC_MEMORY_WAKE);
+ intel_uncore_rmw(>uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
}
-static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
+static void bxt_init_clock_gating(struct drm_i915_private *i915)
{
- gen9_init_clock_gating(dev_priv);
+ gen9_init_clock_gating(i915);
/* WaDisableSDEUnitClockGating:bxt */
- intel_uncore_rmw(_priv->uncore, GEN8_UCGCTL6, 0,
GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+ intel_uncore_rmw(>uncore, GEN8_UCGCTL6, 0,
GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
/*
* FIXME:
* GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
*/
- intel_uncore_rmw(_priv->uncore, GEN8_UCGCTL6, 0,
GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
+ intel_uncore_rmw(>uncore, GEN8_UCGCTL6, 0,
GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
/*
* Wa: Backlight PWM may stop in the asserted state, causing backlight
* to stay fully on.
*/
- intel_uncore_write(_priv->uncore, GEN9_CLKGATE_DIS_0,
intel_uncore_read(_priv->uncore, GEN9_CLKGATE_DIS_0) |
- PWM1_GATING_DIS | PWM2_GATING_DIS);
+ intel_uncore_write(>uncore, GEN9_CLKGATE_DIS_0,
+ intel_uncore_read(>uncore, GEN9_CLKGATE_DIS_0)
|
+ PWM1_GATING_DIS | PWM2_GATING_DIS);
/*
* Lower the display internal timeout.
@@ -96,42 +97,43 @@ static void bxt_init_clock_gating(struct drm_i915_private
*dev_priv)
* is off and a MMIO access is attempted by any privilege
* application, using batch buffers or any other means.
*/
- intel_uncore_write(_priv->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
+ intel_uncore_write(>uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
/*
* WaFbcTurnOffFbcWatermark:bxt
* Display WA #0562: bxt
*/
- intel_uncore_rmw(_priv->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+ intel_uncore_rmw(>uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
/*
* WaFbcHighMemBwCorruptionAvoidance:bxt
* Display WA #0883: bxt
*/
- intel_uncore_rmw(_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), 0,
DPFC_DISABLE_DUMMY0);
+ intel_uncore_rmw(>uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), 0,
DPFC_DISABLE_DUMMY0);
}
-static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
+static void glk_init_clock_gating(struct drm_i915_private *i915)
{
- gen9_init_clock_gating(dev_priv);
+ gen9_init_clock_gating(i915);
/*
* WaDisablePWMClockGating:glk
* Backlight PWM may stop in the asserted state, causing backlight
* to stay fully on.
*/
- intel_uncore_write(_priv->uncore, GEN9_CLKGATE_DIS_0,
intel_uncore_read(_priv->uncore, GEN9_CLKGATE_DIS_0) |
-
[Intel-gfx] [PATCH 5/6] drm/i915: rename intel_pm.[ch] to intel_clock_gating.[ch]
Observe that intel_pm.[ch] is now purely about clock gating, so rename
them to intel_clock_gating.[ch]. Rename the functions to
intel_clock_gating_*() to follow coding conventions.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
drivers/gpu/drm/i915/i915_driver.c | 8
drivers/gpu/drm/i915/i915_gem.c| 8
.../i915/{intel_pm.c => intel_clock_gating.c} | 8
drivers/gpu/drm/i915/intel_clock_gating.h | 14 ++
drivers/gpu/drm/i915/intel_pm.h| 18 --
drivers/gpu/drm/i915/vlv_suspend.c | 4 ++--
8 files changed, 31 insertions(+), 35 deletions(-)
rename drivers/gpu/drm/i915/{intel_pm.c => intel_clock_gating.c} (99%)
create mode 100644 drivers/gpu/drm/i915/intel_clock_gating.h
delete mode 100644 drivers/gpu/drm/i915/intel_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index b2f91a1f8268..b88df8c10781 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -47,10 +47,10 @@ i915-y += i915_driver.o \
i915_switcheroo.o \
i915_sysfs.o \
i915_utils.o \
+ intel_clock_gating.o \
intel_device_info.o \
intel_memory_region.o \
intel_pcode.o \
- intel_pm.o \
intel_region_ttm.o \
intel_runtime_pm.o \
intel_sbi.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a1fbdf32bd21..3f1b90a2f57c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -63,6 +63,7 @@
#include "intel_audio.h"
#include "intel_bw.h"
#include "intel_cdclk.h"
+#include "intel_clock_gating.h"
#include "intel_color.h"
#include "intel_crt.h"
#include "intel_crtc.h"
@@ -105,7 +106,6 @@
#include "intel_pcode.h"
#include "intel_pipe_crc.h"
#include "intel_plane_initial.h"
-#include "intel_pm.h"
#include "intel_pps.h"
#include "intel_psr.h"
#include "intel_quirks.h"
@@ -850,7 +850,7 @@ void intel_display_finish_reset(struct drm_i915_private
*i915)
*/
intel_pps_unlock_regs_wa(i915);
intel_modeset_init_hw(i915);
- intel_init_clock_gating(i915);
+ intel_clock_gating_init(i915);
intel_hpd_init(i915);
ret = __intel_display_resume(i915, state, ctx);
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index a53fd339e2cc..e4809485e47c 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -79,11 +79,11 @@
#include "soc/intel_dram.h"
#include "soc/intel_gmch.h"
-#include "i915_file_private.h"
#include "i915_debugfs.h"
#include "i915_driver.h"
#include "i915_drm_client.h"
#include "i915_drv.h"
+#include "i915_file_private.h"
#include "i915_getparam.h"
#include "i915_hwmon.h"
#include "i915_ioc32.h"
@@ -97,11 +97,11 @@
#include "i915_sysfs.h"
#include "i915_utils.h"
#include "i915_vgpu.h"
+#include "intel_clock_gating.h"
#include "intel_gvt.h"
#include "intel_memory_region.h"
#include "intel_pci_config.h"
#include "intel_pcode.h"
-#include "intel_pm.h"
#include "intel_region_ttm.h"
#include "vlv_suspend.h"
@@ -252,7 +252,7 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
intel_irq_init(dev_priv);
intel_init_display_hooks(dev_priv);
- intel_init_clock_gating_hooks(dev_priv);
+ intel_clock_gating_hooks_init(dev_priv);
intel_detect_preproduction_hw(dev_priv);
@@ -1238,7 +1238,7 @@ static int i915_drm_resume(struct drm_device *dev)
i915_gem_resume(dev_priv);
intel_modeset_init_hw(dev_priv);
- intel_init_clock_gating(dev_priv);
+ intel_clock_gating_init(dev_priv);
intel_hpd_init(dev_priv);
/* MST sideband requires HPD interrupts enabled */
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 35950fa91406..6b6b0e575ef3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -58,7 +58,7 @@
#include "i915_file_private.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
-#include "intel_pm.h"
+#include "intel_clock_gating.h"
static int
insert_mappable_node(struct i915_ggtt *ggtt, struct drm_mm_node *node, u32
size)
@@ -1164,7 +1164,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
}
/*
-* Despite its name intel_init_clock_gating applies both display
+* Despite its name intel_clock_gating_init applies both display
* clock gating workarounds; GT mmio workarounds and the occasional
* GT power context workaround. Worse, sometimes it includes a context
* register workaround which we need to apply before we record the
@@ -1172,7
[Intel-gfx] [PATCH 4/6] drm/i915: remove unnecessary intel_pm.h includes
As intel_pm.[ch] used to contain much more, intel_pm.h was included in a
lot of places. Many of them are now unnecessary. Remove.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 1 -
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 1 -
drivers/gpu/drm/i915/display/intel_modeset_setup.c | 1 -
drivers/gpu/drm/i915/display/skl_watermark.c | 1 -
drivers/gpu/drm/i915/gt/intel_gt.c | 1 -
drivers/gpu/drm/i915/gt/intel_gt_pm.c| 1 -
drivers/gpu/drm/i915/gt/selftest_llc.c | 1 -
drivers/gpu/drm/i915/i915_debugfs.c | 1 -
drivers/gpu/drm/i915/i915_irq.c | 1 -
drivers/gpu/drm/i915/i915_pmu.c | 1 -
drivers/gpu/drm/i915/i915_request.c | 1 -
drivers/gpu/drm/i915/i915_sysfs.c| 1 -
drivers/gpu/drm/i915/intel_uncore.c | 1 -
13 files changed, 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c
b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 3d4687efe4dd..caef72d38798 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -9,7 +9,6 @@
#include "intel_display.h"
#include "intel_display_trace.h"
#include "intel_mchbar_regs.h"
-#include "intel_pm.h"
#include "intel_wm.h"
#include "skl_watermark.h"
#include "vlv_sideband.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 25013f303c82..1e654ddd0815 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -26,7 +26,6 @@
#include "intel_hdmi.h"
#include "intel_hotplug.h"
#include "intel_panel.h"
-#include "intel_pm.h"
#include "intel_psr.h"
#include "intel_sprite.h"
#include "intel_wm.h"
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 60f71e6f0491..7ff083ec2d1d 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -25,7 +25,6 @@
#include "intel_fifo_underrun.h"
#include "intel_modeset_setup.h"
#include "intel_pch_display.h"
-#include "intel_pm.h"
#include "intel_wm.h"
#include "skl_watermark.h"
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index 1300965d328a..f0af997d2a23 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -18,7 +18,6 @@
#include "intel_display_types.h"
#include "intel_fb.h"
#include "intel_pcode.h"
-#include "intel_pm.h"
#include "intel_wm.h"
#include "skl_watermark.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index f7f271708fc7..6ca944d01eb6 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -28,7 +28,6 @@
#include "intel_migrate.h"
#include "intel_mocs.h"
#include "intel_pci_config.h"
-#include "intel_pm.h"
#include "intel_rc6.h"
#include "intel_renderstate.h"
#include "intel_rps.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index cef3d6f5c34e..85ae7dc079f2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -17,7 +17,6 @@
#include "intel_gt_print.h"
#include "intel_gt_requests.h"
#include "intel_llc.h"
-#include "intel_pm.h"
#include "intel_rc6.h"
#include "intel_rps.h"
#include "intel_wakeref.h"
diff --git a/drivers/gpu/drm/i915/gt/selftest_llc.c
b/drivers/gpu/drm/i915/gt/selftest_llc.c
index cfd736d88939..779fadcec7c4 100644
--- a/drivers/gpu/drm/i915/gt/selftest_llc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_llc.c
@@ -3,7 +3,6 @@
* Copyright © 2019 Intel Corporation
*/
-#include "intel_pm.h" /* intel_gpu_freq() */
#include "selftest_llc.h"
#include "intel_rps.h"
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 45773ce1deac..16011c0286ad 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -52,7 +52,6 @@
#include "i915_irq.h"
#include "i915_scheduler.h"
#include "intel_mchbar_regs.h"
-#include "intel_pm.h"
static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
{
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 417c981e4968..6ce3c934d832 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -52,7 +52,6 @@
#include "i915_driver.h"
#include "i915_drv.h"
#include "i915_irq.h"
-#include "intel_pm.h"
/**
* DOC: interrupt handling
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 52531ab28c5f..a76c5ce9513d 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -17,7 +17,6 @@
#include
[Intel-gfx] [PATCH 3/6] drm/i915/pm: drop intel_suspend_hw()
All intel_suspend_hw() does is clear PCH_LP_PARTITION_LEVEL_DISABLE bit
in SOUTH_DSPCLK_GATE_D for LPT LP. intel_suspend_hw() gets called from
i915_drm_suspend().
However, i915_drm_suspend_late() calls
intel_display_power_suspend_late(), which in turn calls hsw_enable_pc8()
on HSW and BDW. The first thing that does is clear
PCH_LP_PARTITION_LEVEL_DISABLE bit in SOUTH_DSPCLK_GATE_D.
Remove the duplicated clearing of the bit, effectively delaying it from
i915_drm_suspend() to i915_drm_suspend_late(), and remove the
unnecessary intel_suspend_hw() function altogether.
Cc: Imre Deak
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_driver.c | 2 --
drivers/gpu/drm/i915/intel_pm.c| 16
drivers/gpu/drm/i915/intel_pm.h| 1 -
3 files changed, 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index 171ff4edabd6..a53fd339e2cc 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1079,8 +1079,6 @@ static int i915_drm_suspend(struct drm_device *dev)
intel_suspend_encoders(dev_priv);
- intel_suspend_hw(dev_priv);
-
/* Must be called before GGTT is suspended. */
intel_dpt_suspend(dev_priv);
i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8b02af531e82..c45af0d981fd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -320,16 +320,6 @@ static void lpt_init_clock_gating(struct drm_i915_private
*dev_priv)
0, TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
}
-static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
-{
- if (HAS_PCH_LPT_LP(dev_priv)) {
- u32 val = intel_uncore_read(_priv->uncore,
SOUTH_DSPCLK_GATE_D);
-
- val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
- intel_uncore_write(_priv->uncore, SOUTH_DSPCLK_GATE_D, val);
- }
-}
-
static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
int general_prio_credits,
int high_prio_credits)
@@ -789,12 +779,6 @@ void intel_init_clock_gating(struct drm_i915_private
*dev_priv)
dev_priv->clock_gating_funcs->init_clock_gating(dev_priv);
}
-void intel_suspend_hw(struct drm_i915_private *dev_priv)
-{
- if (HAS_PCH_LPT(dev_priv))
- lpt_suspend_hw(dev_priv);
-}
-
static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
{
drm_dbg_kms(_priv->drm,
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 1dd464d2d186..f774bddcdca6 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -13,7 +13,6 @@ struct intel_crtc_state;
struct intel_plane_state;
void intel_init_clock_gating(struct drm_i915_private *dev_priv);
-void intel_suspend_hw(struct drm_i915_private *dev_priv);
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
#endif /* __INTEL_PM_H__ */
--
2.39.1
[Intel-gfx] [PATCH 2/6] drm/i915/pm: drop intel_pm_setup()
All the init in intel_pm_setup() is related to runtime pm. Move them to
intel_runtime_pm_init_early(), and remove intel_pm_setup().
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_driver.c | 1 -
drivers/gpu/drm/i915/intel_pm.c | 6 --
drivers/gpu/drm/i915/intel_pm.h | 1 -
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 ++
4 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index 8bc76dede332..171ff4edabd6 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -250,7 +250,6 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
/* This must be called before any calls to HAS_PCH_* */
intel_detect_pch(dev_priv);
- intel_pm_setup(dev_priv);
intel_irq_init(dev_priv);
intel_init_display_hooks(dev_priv);
intel_init_clock_gating_hooks(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ddf004e5bb4b..8b02af531e82 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -899,9 +899,3 @@ void intel_init_clock_gating_hooks(struct drm_i915_private
*dev_priv)
dev_priv->clock_gating_funcs = _clock_gating_funcs;
}
}
-
-void intel_pm_setup(struct drm_i915_private *dev_priv)
-{
- dev_priv->runtime_pm.suspended = false;
- atomic_set(_priv->runtime_pm.wakeref_count, 0);
-}
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index eab60df0c6bb..1dd464d2d186 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -15,6 +15,5 @@ struct intel_plane_state;
void intel_init_clock_gating(struct drm_i915_private *dev_priv);
void intel_suspend_hw(struct drm_i915_private *dev_priv);
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
-void intel_pm_setup(struct drm_i915_private *dev_priv);
#endif /* __INTEL_PM_H__ */
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 129746713d07..cf5122299b6b 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -652,6 +652,8 @@ void intel_runtime_pm_init_early(struct intel_runtime_pm
*rpm)
rpm->kdev = kdev;
rpm->available = HAS_RUNTIME_PM(i915);
+ rpm->suspended = false;
+ atomic_set(>wakeref_count, 0);
init_intel_runtime_pm_wakeref(rpm);
INIT_LIST_HEAD(>lmem_userfault_list);
--
2.39.1
[Intel-gfx] [PATCH 1/6] drm/i915/wm: remove display/ prefix from include
Remove the leftover from moving and renaming the file from driver top
level.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_wm_types.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_wm_types.h
b/drivers/gpu/drm/i915/display/intel_wm_types.h
index bac2b6fdc5d0..628b7c0ce484 100644
--- a/drivers/gpu/drm/i915/display/intel_wm_types.h
+++ b/drivers/gpu/drm/i915/display/intel_wm_types.h
@@ -8,7 +8,7 @@
#include
-#include "display/intel_display_limits.h"
+#include "intel_display_limits.h"
enum intel_ddb_partitioning {
INTEL_DDB_PART_1_2,
--
2.39.1
[Intel-gfx] [PATCH 0/6] drm/i915: pm cleanups, rename to clock gating
Finish off some of the cleanups done earlier in intel_pm.[ch] Jani Nikula (6): drm/i915/wm: remove display/ prefix from include drm/i915/pm: drop intel_pm_setup() drm/i915/pm: drop intel_suspend_hw() drm/i915: remove unnecessary intel_pm.h includes drm/i915: rename intel_pm.[ch] to intel_clock_gating.[ch] drm/i915/clock: mass rename dev_priv to i915 drivers/gpu/drm/i915/Makefile | 2 +- drivers/gpu/drm/i915/display/i9xx_wm.c| 1 - drivers/gpu/drm/i915/display/intel_display.c | 4 +- .../drm/i915/display/intel_display_debugfs.c | 1 - .../drm/i915/display/intel_modeset_setup.c| 1 - drivers/gpu/drm/i915/display/intel_wm_types.h | 2 +- drivers/gpu/drm/i915/display/skl_watermark.c | 1 - drivers/gpu/drm/i915/gt/intel_gt.c| 1 - drivers/gpu/drm/i915/gt/intel_gt_pm.c | 1 - drivers/gpu/drm/i915/gt/selftest_llc.c| 1 - drivers/gpu/drm/i915/i915_debugfs.c | 1 - drivers/gpu/drm/i915/i915_driver.c| 11 +- drivers/gpu/drm/i915/i915_gem.c | 8 +- drivers/gpu/drm/i915/i915_irq.c | 1 - drivers/gpu/drm/i915/i915_pmu.c | 1 - drivers/gpu/drm/i915/i915_request.c | 1 - drivers/gpu/drm/i915/i915_sysfs.c | 1 - drivers/gpu/drm/i915/intel_clock_gating.c | 888 + drivers/gpu/drm/i915/intel_clock_gating.h | 14 + drivers/gpu/drm/i915/intel_pm.c | 907 -- drivers/gpu/drm/i915/intel_pm.h | 20 - drivers/gpu/drm/i915/intel_runtime_pm.c | 2 + drivers/gpu/drm/i915/intel_uncore.c | 1 - drivers/gpu/drm/i915/vlv_suspend.c| 4 +- 24 files changed, 918 insertions(+), 957 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_clock_gating.c create mode 100644 drivers/gpu/drm/i915/intel_clock_gating.h delete mode 100644 drivers/gpu/drm/i915/intel_pm.c delete mode 100644 drivers/gpu/drm/i915/intel_pm.h -- 2.39.1
[Intel-gfx] [PATCH v4 5/5] drm/i915/dmc: mass rename dev_priv to i915
Follow the contemporary convention for struct drm_i915_private * naming.
Cc: Imre Deak
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dmc.c | 166 +++
1 file changed, 81 insertions(+), 85 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 302a465ceb1f..6b162f77340e 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -313,12 +313,12 @@ intel_get_stepping_info(struct drm_i915_private *i915,
return si;
}
-static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
+static void gen9_set_dc_state_debugmask(struct drm_i915_private *i915)
{
/* The below bit doesn't need to be cleared ever afterwards */
- intel_de_rmw(dev_priv, DC_STATE_DEBUG, 0,
+ intel_de_rmw(i915, DC_STATE_DEBUG, 0,
DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP);
- intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
+ intel_de_posting_read(i915, DC_STATE_DEBUG);
}
static void disable_event_handler(struct drm_i915_private *i915,
@@ -476,33 +476,33 @@ void intel_dmc_disable_pipe(struct drm_i915_private
*i915, enum pipe pipe)
/**
* intel_dmc_load_program() - write the firmware from memory to register.
- * @dev_priv: i915 drm device.
+ * @i915: i915 drm device.
*
* DMC firmware is read from a .bin file and kept in internal memory one time.
* Everytime display comes back from low power state this function is called to
* copy the firmware from internal memory to registers.
*/
-void intel_dmc_load_program(struct drm_i915_private *dev_priv)
+void intel_dmc_load_program(struct drm_i915_private *i915)
{
- struct i915_power_domains *power_domains =
_priv->display.power.domains;
- struct intel_dmc *dmc = i915_to_dmc(dev_priv);
+ struct i915_power_domains *power_domains = >display.power.domains;
+ struct intel_dmc *dmc = i915_to_dmc(i915);
enum intel_dmc_id dmc_id;
u32 i;
- if (!intel_dmc_has_payload(dev_priv))
+ if (!intel_dmc_has_payload(i915))
return;
- pipedmc_clock_gating_wa(dev_priv, true);
+ pipedmc_clock_gating_wa(i915, true);
- disable_all_event_handlers(dev_priv);
+ disable_all_event_handlers(i915);
- assert_rpm_wakelock_held(_priv->runtime_pm);
+ assert_rpm_wakelock_held(>runtime_pm);
preempt_disable();
for_each_dmc_id(dmc_id) {
for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) {
- intel_de_write_fw(dev_priv,
+ intel_de_write_fw(i915,
DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i),
dmc->dmc_info[dmc_id].payload[i]);
}
@@ -512,23 +512,23 @@ void intel_dmc_load_program(struct drm_i915_private
*dev_priv)
for_each_dmc_id(dmc_id) {
for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {
- intel_de_write(dev_priv,
dmc->dmc_info[dmc_id].mmioaddr[i],
+ intel_de_write(i915, dmc->dmc_info[dmc_id].mmioaddr[i],
dmc->dmc_info[dmc_id].mmiodata[i]);
}
}
power_domains->dc_state = 0;
- gen9_set_dc_state_debugmask(dev_priv);
+ gen9_set_dc_state_debugmask(i915);
/*
* Flip queue events need to be disabled before enabling DC5/6.
* i915 doesn't use the flip queue feature, so disable it already
* here.
*/
- disable_all_flip_queue_events(dev_priv);
+ disable_all_flip_queue_events(i915);
- pipedmc_clock_gating_wa(dev_priv, false);
+ pipedmc_clock_gating_wa(i915, false);
}
/**
@@ -839,12 +839,12 @@ static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
static void parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw)
{
- struct drm_i915_private *dev_priv = dmc->i915;
+ struct drm_i915_private *i915 = dmc->i915;
struct intel_css_header *css_header;
struct intel_package_header *package_header;
struct intel_dmc_header_base *dmc_header;
struct stepping_info display_info = { '*', '*'};
- const struct stepping_info *si = intel_get_stepping_info(dev_priv,
_info);
+ const struct stepping_info *si = intel_get_stepping_info(i915,
_info);
enum intel_dmc_id dmc_id;
u32 readcount = 0;
u32 r, offset;
@@ -874,7 +874,7 @@ static void parse_dmc_fw(struct intel_dmc *dmc, const
struct firmware *fw)
offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4;
if (offset > fw->size) {
- drm_err(_priv->drm, "Reading beyond the fw_size\n");
+ drm_err(>drm, "Reading beyond the fw_size\n");
continue;
[Intel-gfx] [PATCH v4 3/5] drm/i915/dmc: add i915_to_dmc() and dmc->i915 and use them
Start preparing for dynamically allocated struct intel_dmc by adding
i915_to_dmc() and dmc->i915, and using them. Take the future NULL dmc
pointer into account already now, and add separate logging for
initialization in the DMC debugfs.
v3:
- Obtain runtime pm reference first (Imre)
v2:
- Don't reduce debugfs output (Imre)
Cc: Imre Deak
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dmc.c | 94 ++--
drivers/gpu/drm/i915/display/intel_dmc.h | 1 +
2 files changed, 56 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 599fb92a5161..acd792480aba 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -38,6 +38,11 @@
* low-power state and comes back to normal.
*/
+static struct intel_dmc *i915_to_dmc(struct drm_i915_private *i915)
+{
+ return >display.dmc;
+}
+
#define DMC_VERSION(major, minor) ((major) << 16 | (minor))
#define DMC_VERSION_MAJOR(version) ((version) >> 16)
#define DMC_VERSION_MINOR(version) ((version) & 0x)
@@ -259,7 +264,9 @@ static bool is_valid_dmc_id(enum intel_dmc_id dmc_id)
static bool has_dmc_id_fw(struct drm_i915_private *i915, enum intel_dmc_id
dmc_id)
{
- return i915->display.dmc.dmc_info[dmc_id].payload;
+ struct intel_dmc *dmc = i915_to_dmc(i915);
+
+ return dmc && dmc->dmc_info[dmc_id].payload;
}
bool intel_dmc_has_payload(struct drm_i915_private *i915)
@@ -450,7 +457,7 @@ void intel_dmc_disable_pipe(struct drm_i915_private *i915,
enum pipe pipe)
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
struct i915_power_domains *power_domains =
_priv->display.power.domains;
- struct intel_dmc *dmc = _priv->display.dmc;
+ struct intel_dmc *dmc = i915_to_dmc(dev_priv);
enum intel_dmc_id dmc_id;
u32 i;
@@ -515,8 +522,11 @@ void intel_dmc_disable_program(struct drm_i915_private
*i915)
void assert_dmc_loaded(struct drm_i915_private *i915)
{
- drm_WARN_ONCE(>drm,
- !intel_de_read(i915,
DMC_PROGRAM(i915->display.dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
+ struct intel_dmc *dmc = i915_to_dmc(i915);
+
+ drm_WARN_ONCE(>drm, !dmc, "DMC not initialized\n");
+ drm_WARN_ONCE(>drm, dmc &&
+ !intel_de_read(i915,
DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
"DMC program storage start is NULL\n");
drm_WARN_ONCE(>drm, !intel_de_read(i915, DMC_SSP_BASE),
"DMC SSP Base Not fine\n");
@@ -551,11 +561,10 @@ static void dmc_set_fw_offset(struct intel_dmc *dmc,
const struct stepping_info *si,
u8 package_ver)
{
+ struct drm_i915_private *i915 = dmc->i915;
enum intel_dmc_id dmc_id;
unsigned int i;
- struct drm_i915_private *i915 = container_of(dmc, typeof(*i915),
display.dmc);
-
for (i = 0; i < num_entries; i++) {
dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id;
@@ -582,7 +591,7 @@ static bool dmc_mmio_addr_sanity_check(struct intel_dmc
*dmc,
const u32 *mmioaddr, u32 mmio_count,
int header_ver, enum intel_dmc_id dmc_id)
{
- struct drm_i915_private *i915 = container_of(dmc, typeof(*i915),
display.dmc);
+ struct drm_i915_private *i915 = dmc->i915;
u32 start_range, end_range;
int i;
@@ -615,7 +624,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
const struct intel_dmc_header_base *dmc_header,
size_t rem_size, enum intel_dmc_id dmc_id)
{
- struct drm_i915_private *i915 = container_of(dmc, typeof(*i915),
display.dmc);
+ struct drm_i915_private *i915 = dmc->i915;
struct dmc_fw_info *dmc_info = >dmc_info[dmc_id];
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
const u32 *mmioaddr, *mmiodata;
@@ -726,7 +735,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
const struct stepping_info *si,
size_t rem_size)
{
- struct drm_i915_private *i915 = container_of(dmc, typeof(*i915),
display.dmc);
+ struct drm_i915_private *i915 = dmc->i915;
u32 package_size = sizeof(struct intel_package_header);
u32 num_entries, max_entries;
const struct intel_fw_info *fw_info;
@@ -780,7 +789,7 @@ static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
struct intel_css_header *css_header,
size_t rem_size)
{
- struct drm_i915_private *i915 = container_of(dmc, typeof(*i915),
display.dmc);
+ struct drm_i915_private *i915 = dmc->i915;
if (rem_size < sizeof(struct intel_css_header)) {
drm_err(>drm,
[Intel-gfx] [PATCH v4 4/5] drm/i915/dmc: allocate dmc structure dynamically
sizeof(struct intel_dmc) > 1024 bytes, allocated on all platforms as
part of struct drm_i915_private, whether they have DMC or not.
Allocate struct intel_dmc dynamically, and hide all the dmc details
behind an opaque pointer in intel_dmc.c.
Care must be taken to take into account all cases: DMC not supported on
the platform, DMC supported but not initialized, and DMC initialized but
not loaded. For the second case, we need to move the wakeref out of
struct intel_dmc.
v2:
- Rebase to kzalloc dmc after runtime pm get (Imre)
Cc: Imre Deak
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/intel_display_core.h | 8 ++-
drivers/gpu/drm/i915/display/intel_dmc.c | 50 +--
drivers/gpu/drm/i915/display/intel_dmc.h | 34 +
.../drm/i915/display/intel_modeset_setup.c| 1 +
4 files changed, 53 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 631a7b17899e..fdab7bb93a7d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -19,7 +19,6 @@
#include "intel_cdclk.h"
#include "intel_display_limits.h"
#include "intel_display_power.h"
-#include "intel_dmc.h"
#include "intel_dpll_mgr.h"
#include "intel_fbc.h"
#include "intel_global_state.h"
@@ -40,6 +39,7 @@ struct intel_cdclk_vals;
struct intel_color_funcs;
struct intel_crtc;
struct intel_crtc_state;
+struct intel_dmc;
struct intel_dpll_funcs;
struct intel_dpll_mgr;
struct intel_fbdev;
@@ -340,6 +340,11 @@ struct intel_display {
spinlock_t phy_lock;
} dkl;
+ struct {
+ struct intel_dmc *dmc;
+ intel_wakeref_t wakeref;
+ } dmc;
+
struct {
/* VLV/CHV/BXT/GLK DSI MMIO register base address */
u32 mmio_base;
@@ -467,7 +472,6 @@ struct intel_display {
/* Grouping using named structs. Keep sorted. */
struct intel_audio audio;
- struct intel_dmc dmc;
struct intel_dpll dpll;
struct intel_fbc *fbc[I915_MAX_FBCS];
struct intel_frontbuffer_tracking fb_tracking;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index acd792480aba..302a465ceb1f 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -38,9 +38,37 @@
* low-power state and comes back to normal.
*/
+enum intel_dmc_id {
+ DMC_FW_MAIN = 0,
+ DMC_FW_PIPEA,
+ DMC_FW_PIPEB,
+ DMC_FW_PIPEC,
+ DMC_FW_PIPED,
+ DMC_FW_MAX
+};
+
+struct intel_dmc {
+ struct drm_i915_private *i915;
+ struct work_struct work;
+ const char *fw_path;
+ u32 max_fw_size; /* bytes */
+ u32 version;
+ struct dmc_fw_info {
+ u32 mmio_count;
+ i915_reg_t mmioaddr[20];
+ u32 mmiodata[20];
+ u32 dmc_offset;
+ u32 start_mmioaddr;
+ u32 dmc_fw_size; /*dwords */
+ u32 *payload;
+ bool present;
+ } dmc_info[DMC_FW_MAX];
+};
+
+/* Note: This may be NULL. */
static struct intel_dmc *i915_to_dmc(struct drm_i915_private *i915)
{
- return >display.dmc;
+ return i915->display.dmc.dmc;
}
#define DMC_VERSION(major, minor) ((major) << 16 | (minor))
@@ -947,7 +975,10 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
*/
intel_dmc_runtime_pm_get(dev_priv);
- dmc = i915_to_dmc(dev_priv);
+ dmc = kzalloc(sizeof(*dmc), GFP_KERNEL);
+ if (!dmc)
+ return;
+
dmc->i915 = dev_priv;
INIT_WORK(>work, dmc_load_work_fn);
@@ -991,10 +1022,9 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
if (dev_priv->params.dmc_firmware_path) {
if (strlen(dev_priv->params.dmc_firmware_path) == 0) {
- dmc->fw_path = NULL;
drm_info(_priv->drm,
"Disabling DMC firmware and runtime PM\n");
- return;
+ goto out;
}
dmc->fw_path = dev_priv->params.dmc_firmware_path;
@@ -1003,11 +1033,18 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
if (!dmc->fw_path) {
drm_dbg_kms(_priv->drm,
"No known DMC firmware for platform, disabling
runtime PM\n");
- return;
+ goto out;
}
+ dev_priv->display.dmc.dmc = dmc;
+
drm_dbg_kms(_priv->drm, "Loading %s\n", dmc->fw_path);
schedule_work(>work);
+
+ return;
+
+out:
+ kfree(dmc);
}
/**
@@ -1074,6 +,9 @@ void intel_dmc_fini(struct drm_i915_private *dev_priv)
if (dmc) {
for_each_dmc_id(dmc_id)
kfree(dmc->dmc_info[dmc_id].payload);
+
+
[Intel-gfx] [PATCH v4 2/5] drm/i915/dmc: use has_dmc_id_fw() instead of poking dmc->dmc_info directly
This will help in follow-up changes. Cc: Imre Deak Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index ab4fdedd4c5f..599fb92a5161 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -1098,12 +1098,12 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) seq_printf(m, "Pipe A fw needed: %s\n", str_yes_no(GRAPHICS_VER(i915) >= 12)); seq_printf(m, "Pipe A fw loaded: %s\n", - str_yes_no(dmc->dmc_info[DMC_FW_PIPEA].payload)); + str_yes_no(has_dmc_id_fw(i915, DMC_FW_PIPEA))); seq_printf(m, "Pipe B fw needed: %s\n", str_yes_no(IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)); seq_printf(m, "Pipe B fw loaded: %s\n", - str_yes_no(dmc->dmc_info[DMC_FW_PIPEB].payload)); + str_yes_no(has_dmc_id_fw(i915, DMC_FW_PIPEB))); if (!intel_dmc_has_payload(i915)) goto out; -- 2.39.1
[Intel-gfx] [PATCH v4 1/5] drm/i915/power: move dc state members to struct i915_power_domains
There's only one reference to the struct intel_dmc members dc_state,
target_dc_state, and allowed_dc_mask within intel_dmc.c, begging the
question why they are under struct intel_dmc to begin with.
Moreover, the only references to i915->display.dmc outside of
intel_dmc.c are to these members.
They don't belong. Move them from struct intel_dmc to struct
i915_power_domains, which seems like a more suitable place.
Cc: Imre Deak
Reviewed-by: Imre Deak
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_power.c| 25 ---
.../drm/i915/display/intel_display_power.h| 4 +++
.../i915/display/intel_display_power_well.c | 31 +++
drivers/gpu/drm/i915/display/intel_dmc.c | 3 +-
drivers/gpu/drm/i915/display/intel_dmc.h | 3 --
drivers/gpu/drm/i915/display/intel_psr.c | 3 +-
6 files changed, 39 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 743b919bb2cf..f085ae971150 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -264,9 +264,10 @@ bool intel_display_power_is_enabled(struct
drm_i915_private *dev_priv,
}
static u32
-sanitize_target_dc_state(struct drm_i915_private *dev_priv,
+sanitize_target_dc_state(struct drm_i915_private *i915,
u32 target_dc_state)
{
+ struct i915_power_domains *power_domains = >display.power.domains;
static const u32 states[] = {
DC_STATE_EN_UPTO_DC6,
DC_STATE_EN_UPTO_DC5,
@@ -279,7 +280,7 @@ sanitize_target_dc_state(struct drm_i915_private *dev_priv,
if (target_dc_state != states[i])
continue;
- if (dev_priv->display.dmc.allowed_dc_mask & target_dc_state)
+ if (power_domains->allowed_dc_mask & target_dc_state)
break;
target_dc_state = states[i + 1];
@@ -312,7 +313,7 @@ void intel_display_power_set_target_dc_state(struct
drm_i915_private *dev_priv,
state = sanitize_target_dc_state(dev_priv, state);
- if (state == dev_priv->display.dmc.target_dc_state)
+ if (state == power_domains->target_dc_state)
goto unlock;
dc_off_enabled = intel_power_well_is_enabled(dev_priv, power_well);
@@ -323,7 +324,7 @@ void intel_display_power_set_target_dc_state(struct
drm_i915_private *dev_priv,
if (!dc_off_enabled)
intel_power_well_enable(dev_priv, power_well);
- dev_priv->display.dmc.target_dc_state = state;
+ power_domains->target_dc_state = state;
if (!dc_off_enabled)
intel_power_well_disable(dev_priv, power_well);
@@ -992,10 +993,10 @@ int intel_power_domains_init(struct drm_i915_private
*dev_priv)
dev_priv->params.disable_power_well =
sanitize_disable_power_well_option(dev_priv,
dev_priv->params.disable_power_well);
- dev_priv->display.dmc.allowed_dc_mask =
+ power_domains->allowed_dc_mask =
get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc);
- dev_priv->display.dmc.target_dc_state =
+ power_domains->target_dc_state =
sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
mutex_init(_domains->lock);
@@ -2032,7 +2033,7 @@ void intel_power_domains_suspend(struct drm_i915_private
*i915,
* resources as required and also enable deeper system power states
* that would be blocked if the firmware was inactive.
*/
- if (!(i915->display.dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&
+ if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC9) &&
suspend_mode == I915_DRM_SUSPEND_IDLE &&
intel_dmc_has_payload(i915)) {
intel_display_power_flush_work(i915);
@@ -2221,22 +,22 @@ void intel_display_power_suspend(struct
drm_i915_private *i915)
void intel_display_power_resume(struct drm_i915_private *i915)
{
+ struct i915_power_domains *power_domains = >display.power.domains;
+
if (DISPLAY_VER(i915) >= 11) {
bxt_disable_dc9(i915);
icl_display_core_init(i915, true);
if (intel_dmc_has_payload(i915)) {
- if (i915->display.dmc.allowed_dc_mask &
- DC_STATE_EN_UPTO_DC6)
+ if (power_domains->allowed_dc_mask &
DC_STATE_EN_UPTO_DC6)
skl_enable_dc6(i915);
- else if (i915->display.dmc.allowed_dc_mask &
-DC_STATE_EN_UPTO_DC5)
+ else if (power_domains->allowed_dc_mask &
DC_STATE_EN_UPTO_DC5)
gen9_enable_dc5(i915);
}
} else if (IS_GEMINILAKE(i915) ||
Re: [Intel-gfx] [Intel-gfx V2] drm/i915/selftests: Fix live_requests for all engines
Hi Tejas, On Tue, Feb 28, 2023 at 10:13:07AM +0530, Tejas Upadhyay wrote: > From: Tvrtko Ursulin > > After the abandonment of i915->kernel_context and since we have started to > create per-gt engine->kernel_context, these tests need to be updated to > instantiate the batch buffer VMA in the correct PPGTT for the context used > to execute each spinner. > > v2(Tejas): > - Clean commit message - Matt > - Add BUG_ON to match vm > v3(Tejas): > - Fix dim checkpatch warnings > > Acked-by: Andi Shyti > Signed-off-by: Tvrtko Ursulin > Signed-off-by: Tejas Upadhyay pushed in drm-intel-gt-next. Thanks, Andi
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v3,1/4] drm/i915/power: move dc state members to struct i915_power_domains (rev2)
== Series Details == Series: series starting with [v3,1/4] drm/i915/power: move dc state members to struct i915_power_domains (rev2) URL : https://patchwork.freedesktop.org/series/114431/ State : success == Summary == CI Bug Log - changes from CI_DRM_12794_full -> Patchwork_114431v2_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 11) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_114431v2_full that come from known issues: ### IGT changes ### Issues hit * igt@api_intel_bb@crc32: - shard-tglu-10: NOTRUN -> [SKIP][1] ([i915#6230]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/shard-tglu-10/igt@api_intel...@crc32.html * igt@device_reset@cold-reset-bound: - shard-tglu-10: NOTRUN -> [SKIP][2] ([i915#7701]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/shard-tglu-10/igt@device_re...@cold-reset-bound.html * igt@fbdev@write: - shard-tglu-9: NOTRUN -> [SKIP][3] ([i915#2582]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/shard-tglu-9/igt@fb...@write.html * igt@feature_discovery@display-2x: - shard-tglu-10: NOTRUN -> [SKIP][4] ([i915#1839]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/shard-tglu-10/igt@feature_discov...@display-2x.html * igt@gem_basic@multigpu-create-close: - shard-tglu-9: NOTRUN -> [SKIP][5] ([i915#7697]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/shard-tglu-9/igt@gem_ba...@multigpu-create-close.html * igt@gem_ccs@ctrl-surf-copy: - shard-tglu-10: NOTRUN -> [SKIP][6] ([i915#3555] / [i915#5325]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/shard-tglu-10/igt@gem_...@ctrl-surf-copy.html * igt@gem_ccs@ctrl-surf-copy-new-ctx: - shard-tglu-10: NOTRUN -> [SKIP][7] ([i915#5325]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/shard-tglu-10/igt@gem_...@ctrl-surf-copy-new-ctx.html * igt@gem_close_race@multigpu-basic-threads: - shard-tglu-10: NOTRUN -> [SKIP][8] ([i915#7697]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/shard-tglu-10/igt@gem_close_r...@multigpu-basic-threads.html * igt@gem_ctx_exec@basic-nohangcheck: - shard-tglu-10: NOTRUN -> [FAIL][9] ([i915#6268]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/shard-tglu-10/igt@gem_ctx_e...@basic-nohangcheck.html * igt@gem_ctx_persistence@processes: - shard-snb: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#1099]) +3 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/shard-snb6/igt@gem_ctx_persiste...@processes.html * igt@gem_ctx_sseu@invalid-args: - shard-tglu-10: NOTRUN -> [SKIP][11] ([i915#280]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/shard-tglu-10/igt@gem_ctx_s...@invalid-args.html * igt@gem_eio@reset-stress: - shard-snb: NOTRUN -> [TIMEOUT][12] ([i915#3063]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/shard-snb6/igt@gem_...@reset-stress.html * igt@gem_exec_capture@capture-recoverable: - shard-tglu-10: NOTRUN -> [SKIP][13] ([i915#6344]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/shard-tglu-10/igt@gem_exec_capt...@capture-recoverable.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-tglu-9: NOTRUN -> [FAIL][14] ([i915#2842]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/shard-tglu-9/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_params@secure-non-master: - shard-tglu-10: NOTRUN -> [SKIP][15] ([fdo#112283]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/shard-tglu-10/igt@gem_exec_par...@secure-non-master.html * igt@gem_huc_copy@huc-copy: - shard-tglu-10: NOTRUN -> [SKIP][16] ([i915#2190]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/shard-tglu-10/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@heavy-verify-multi: - shard-tglu-10: NOTRUN -> [SKIP][17] ([i915#4613]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/shard-tglu-10/igt@gem_lmem_swapp...@heavy-verify-multi.html * igt@gem_lmem_swapping@massive-random: - shard-tglu-9: NOTRUN -> [SKIP][18] ([i915#4613]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/shard-tglu-9/igt@gem_lmem_swapp...@massive-random.html * igt@gem_lmem_swapping@verify: - shard-glk: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/shard-glk8/igt@gem_lmem_swapp...@verify.html * igt@gem_media_vme: -
Re: [Intel-gfx] [PATCH 1/2] drm/i915/selftest: Fix engine timestamp and ktime disparity
LGTM
Reviewed-by: Badal Nilawar
On 23-02-2023 15:35, Anshuman Gupta wrote:
While reading the engine timestamps there can be uncontrollable
concurrent mmio access via other i915 child drivers and by GuC,
which is not truly atomic context as expected by this selftest,
which may cause mmio latency to read the engine timestamps,
Account such latency to calculate time to read engine timestamp
such that selftest can validate the timestamp and ktime pair.
Cc: Chris Wilson
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_rps.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
index b46425aeb2f0..0971241707ce 100644
--- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
@@ -63,8 +63,8 @@ static void measure_clocks(struct intel_engine_cs *engine,
udelay(1000);
- dt[i] = ktime_sub(ktime_get(), dt[i]);
cycles[i] += read_timestamp(engine);
+ dt[i] = ktime_sub(ktime_get(), dt[i]);
local_irq_enable();
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 6755bbc4ebda..c0cc0dd78c7c 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -299,13 +299,13 @@ int live_rps_clock_interval(void *arg)
for (i = 0; i < 5; i++) {
preempt_disable();
-dt_[i] = ktime_get();
cycles_[i] = -intel_uncore_read_fw(gt->uncore,
GEN6_RP_CUR_UP_EI);
+ dt_[i] = ktime_get();
udelay(1000);
-dt_[i] = ktime_sub(ktime_get(), dt_[i]);
cycles_[i] += intel_uncore_read_fw(gt->uncore,
GEN6_RP_CUR_UP_EI);
+ dt_[i] = ktime_sub(ktime_get(), dt_[i]);
preempt_enable();
}
Re: [Intel-gfx] [PATCH 2/2] drm/i915/selftest: Fix ktime_get() and h/w access order
LGTM
Reviewed-by: Badal Nilawar
On 23-02-2023 15:35, Anshuman Gupta wrote:
Use ktime_get() after accessing the mmio or any driver resource,
while using wall time for various calculation that depends on
the inserted delay in order to account any mmio and resource
access latency.
Cc: Chris Wilson
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gt/selftest_rps.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c
b/drivers/gpu/drm/i915/gt/selftest_rps.c
index c0cc0dd78c7c..84e77e8dbba1 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -537,8 +537,8 @@ static u64 __measure_frequency(u32 *cntr, int duration_ms)
{
u64 dc, dt;
- dt = ktime_get();
dc = READ_ONCE(*cntr);
+ dt = ktime_get();
usleep_range(1000 * duration_ms, 2000 * duration_ms);
dc = READ_ONCE(*cntr) - dc;
dt = ktime_get() - dt;
@@ -566,8 +566,8 @@ static u64 __measure_cs_frequency(struct intel_engine_cs
*engine,
{
u64 dc, dt;
- dt = ktime_get();
dc = intel_uncore_read_fw(engine->uncore, CS_GPR(0));
+ dt = ktime_get();
usleep_range(1000 * duration_ms, 2000 * duration_ms);
dc = intel_uncore_read_fw(engine->uncore, CS_GPR(0)) - dc;
dt = ktime_get() - dt;
@@ -1094,8 +1094,8 @@ static u64 __measure_power(int duration_ms)
{
u64 dE, dt;
- dt = ktime_get();
dE = librapl_energy_uJ();
+ dt = ktime_get();
usleep_range(1000 * duration_ms, 2000 * duration_ms);
dE = librapl_energy_uJ() - dE;
dt = ktime_get() - dt;
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/mtl: Apply Wa_14017073508 for MTL Media Step
== Series Details == Series: drm/i915/mtl: Apply Wa_14017073508 for MTL Media Step URL : https://patchwork.freedesktop.org/series/114508/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12795 -> Patchwork_114508v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_114508v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_114508v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v1/index.html Participating hosts (38 -> 38) -- Additional (1): fi-kbl-soraka Missing(1): fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_114508v1: ### IGT changes ### Possible regressions * igt@dmabuf@all-tests@dma_fence: - bat-dg2-8: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12795/bat-dg2-8/igt@dmabuf@all-tests@dma_fence.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v1/bat-dg2-8/igt@dmabuf@all-tests@dma_fence.html * igt@dmabuf@all-tests@sanitycheck: - bat-dg2-8: [PASS][3] -> [ABORT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12795/bat-dg2-8/igt@dmabuf@all-te...@sanitycheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v1/bat-dg2-8/igt@dmabuf@all-te...@sanitycheck.html Known issues Here are the changes found in Patchwork_114508v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-apl-guc: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v1/fi-apl-guc/igt@gem_lmem_swapp...@basic.html - fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][8] ([i915#1886]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@guc: - bat-rpls-2: [PASS][9] -> [DMESG-WARN][10] ([i915#7852]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12795/bat-rpls-2/igt@i915_selftest@l...@guc.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v1/bat-rpls-2/igt@i915_selftest@l...@guc.html * igt@i915_selftest@live@hangcheck: - fi-kbl-soraka: NOTRUN -> [INCOMPLETE][11] ([i915#7913]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v1/fi-kbl-soraka/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium_frames@hdmi-crc-fast: - fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271]) +16 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v1/fi-kbl-soraka/igt@kms_chamelium_fra...@hdmi-crc-fast.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - fi-apl-guc: NOTRUN -> [SKIP][13] ([fdo#109271]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v1/fi-apl-guc/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@read-crc: - bat-adlp-9: NOTRUN -> [SKIP][14] ([i915#3546]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v1/bat-adlp-9/igt@kms_pipe_crc_ba...@read-crc.html Possible fixes * igt@i915_module_load@reload: - fi-apl-guc: [ABORT][15] -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12795/fi-apl-guc/igt@i915_module_l...@reload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v1/fi-apl-guc/igt@i915_module_l...@reload.html Warnings * igt@i915_selftest@live@slpc: - bat-rpls-2: [DMESG-FAIL][17] ([i915#6367] / [i915#6997] / [i915#7913]) -> [DMESG-FAIL][18] ([i915#6997] / [i915#7913]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12795/bat-rpls-2/igt@i915_selftest@l...@slpc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114508v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#3546]:
Re: [Intel-gfx] [PATCH] drm/i915/hwmon: Accept writes of value 0 to power1_max_interval
On 28-02-2023 10:13, Ashutosh Dixit wrote:
The value shown by power1_max_interval in millisec is essentially:
((1.x * power(2,y)) * 1000) >> 10
Where x and y are read from a HW register. On ATSM, x and y are 0 on
power-up so the value shown is 0.
Writes of 0 to power1_max_interval had previously been disallowed to avoid
computing ilog2(0) but this resulted in the corner-case bug
below. Therefore allow writes of 0 now but special case that write to
x = y = 0.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7754
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_hwmon.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c
b/drivers/gpu/drm/i915/i915_hwmon.c
index 7c20a6f47b92e..596dd2c070106 100644
--- a/drivers/gpu/drm/i915/i915_hwmon.c
+++ b/drivers/gpu/drm/i915/i915_hwmon.c
@@ -218,11 +218,15 @@ hwm_power1_max_interval_store(struct device *dev,
/* val in hw units */
val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME);
/* Convert to 1.x * power(2,y) */
- if (!val)
- return -EINVAL;
- y = ilog2(val);
- /* x = (val - (1 << y)) >> (y - 2); */
- x = (val - (1ul << y)) << x_w >> y;
+ if (!val) {
+ /* Avoid ilog2(0) */
+ y = 0;
+ x = 0;
+ } else {
+ y = ilog2(val);
+ /* x = (val - (1 << y)) >> (y - 2); */
+ x = (val - (1ul << y)) << x_w >> y;
+ }
Reviewed-by: Badal Nilawar
rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) | REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y);
[Intel-gfx] [PATCH v2 2/2] drm/i915/debugfs: Enable upper layer interfaces to act on all gt's
The commit 82a149a62b6b5 ('drm/i915/gt: move remaining debugfs
interfaces into gt') moved gt-related debugfs files in the gtX/
directories to operate on individual gt's.
However, the original files were only functioning on the root
tile (tile 0) and have been left in the same location to maintain
compatibility with userspace users.
Add multiplexing functionality to the higher directories' files.
This enables the operations to be performed on all the tiles with
a single write. In the case of reads, the files provide an or'ed
value across all the tiles.
Signed-off-by: Andi Shyti
Cc: Maciej Patelczyk
---
drivers/gpu/drm/i915/i915_debugfs.c | 38 ++---
1 file changed, 34 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 45773ce1deac2..90663f251fd10 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -575,14 +575,36 @@ static int i915_wa_registers(struct seq_file *m, void
*unused)
static int i915_wedged_get(void *data, u64 *val)
{
struct drm_i915_private *i915 = data;
+ struct intel_gt *gt;
+ unsigned int i;
- return intel_gt_debugfs_reset_show(to_gt(i915), val);
+ *val = 0;
+
+ for_each_gt(gt, i915, i) {
+ int ret;
+ u64 v;
+
+ ret = intel_gt_debugfs_reset_show(gt, );
+ if (ret)
+ return ret;
+
+ /* at least one tile should be wedged */
+ *val |= !!v;
+ if (*val)
+ break;
+ }
+
+ return 0;
}
static int i915_wedged_set(void *data, u64 val)
{
struct drm_i915_private *i915 = data;
- intel_gt_debugfs_reset_store(to_gt(i915), val);
+ struct intel_gt *gt;
+ unsigned int i;
+
+ for_each_gt(gt, i915, i)
+ intel_gt_debugfs_reset_store(gt, val);
return 0;
}
@@ -733,7 +755,11 @@ static int i915_sseu_status(struct seq_file *m, void
*unused)
static int i915_forcewake_open(struct inode *inode, struct file *file)
{
struct drm_i915_private *i915 = inode->i_private;
- intel_gt_pm_debugfs_forcewake_user_open(to_gt(i915));
+ struct intel_gt *gt;
+ unsigned int i;
+
+ for_each_gt(gt, i915, i)
+ intel_gt_pm_debugfs_forcewake_user_open(gt);
return 0;
}
@@ -741,7 +767,11 @@ static int i915_forcewake_open(struct inode *inode, struct
file *file)
static int i915_forcewake_release(struct inode *inode, struct file *file)
{
struct drm_i915_private *i915 = inode->i_private;
- intel_gt_pm_debugfs_forcewake_user_release(to_gt(i915));
+ struct intel_gt *gt;
+ unsigned int i;
+
+ for_each_gt(gt, i915, i)
+ intel_gt_pm_debugfs_forcewake_user_release(gt);
return 0;
}
--
2.39.1
[Intel-gfx] [PATCH v2 1/2] drm/i915/gt: Create per-tile debugfs files
To support multi-GT configurations, we need to generate
independent debug files for each GT.
To achieve this create a separate directory for each GT under the
debugfs directory. For instance, in a system with two tiles, the
debugfs structure would look like this:
/sys/kernel/debug/dri
└── 0
├── gt0
│ ├── drpc
│ ├── engines
│ ├── forcewake
│ ├── frequency
│ └── rps_boost
└── gt1
: ├── drpc
: ├── engines
: ├── forcewake
├── frequency
└── rps_boost
Signed-off-by: Andi Shyti
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c| 4 +++-
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 5 -
drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c | 2 ++
4 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
index 5fc2df01aa0df..4dc23b8d3aa2d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
@@ -83,11 +83,13 @@ static void gt_debugfs_register(struct intel_gt *gt, struct
dentry *root)
void intel_gt_debugfs_register(struct intel_gt *gt)
{
struct dentry *root;
+ char gtname[4];
if (!gt->i915->drm.primary->debugfs_root)
return;
- root = debugfs_create_dir("gt", gt->i915->drm.primary->debugfs_root);
+ snprintf(gtname, sizeof(gtname), "gt%u", gt->info.id);
+ root = debugfs_create_dir(gtname, gt->i915->drm.primary->debugfs_root);
if (IS_ERR(root))
return;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index bb4dfe707a7d0..e46aac1a41e6d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -42,6 +42,8 @@ struct intel_guc {
/** @capture: the error-state-capture module's data and objects */
struct intel_guc_state_capture *capture;
+ struct dentry *dbgfs_node;
+
/** @sched_engine: Global engine used to submit requests to GuC */
struct i915_sched_engine *sched_engine;
/**
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 195db8c9d4200..55bc8b55fbc05 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -542,8 +542,11 @@ static int guc_log_relay_create(struct intel_guc_log *log)
*/
n_subbufs = 8;
+ if (!guc->dbgfs_node)
+ return -ENOENT;
+
guc_log_relay_chan = relay_open("guc_log",
- i915->drm.primary->debugfs_root,
+ guc->dbgfs_node,
subbuf_size, n_subbufs,
_callbacks, i915);
if (!guc_log_relay_chan) {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
index 284d6fbc2d08c..2f93cc4e408a8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
@@ -54,6 +54,8 @@ void intel_uc_debugfs_register(struct intel_uc *uc, struct
dentry *gt_root)
if (IS_ERR(root))
return;
+ uc->guc.dbgfs_node = root;
+
intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), uc);
intel_guc_debugfs_register(>guc, root);
--
2.39.1
[Intel-gfx] [PATCH v2 0/2] Some debugfs refactoring and improvements
Hi, These two patches aim to enhance the multi-GT capabilities of the debugfs. The first patch reorganizes the file structure, while the second patch extends the functionality of the original files in the upper directories to operate on all tiles with a single write, providing an or'ed value among them in the read case. Andi Changelog = v1 -> v2 - add patch 2 for multiplexing - improve commit log in patch 1. Andi Shyti (2): drm/i915/gt: Create per-tile debugfs files drm/i915/debugfs: Enable upper layer interfaces to act on all gt's drivers/gpu/drm/i915/gt/intel_gt_debugfs.c| 4 +- drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 + drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 5 ++- drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c | 2 + drivers/gpu/drm/i915/i915_debugfs.c | 38 +-- 5 files changed, 45 insertions(+), 6 deletions(-) -- 2.39.1
Re: [Intel-gfx] [PATCH v3 4/4] drm/i915/dmc: allocate dmc structure dynamically
On Wed, 01 Mar 2023, Imre Deak wrote:
> On Mon, Feb 27, 2023 at 07:25:21PM +0200, Jani Nikula wrote:
>> sizeof(struct intel_dmc) > 1024 bytes, allocated on all platforms as
>> part of struct drm_i915_private, whether they have DMC or not.
>>
>> Allocate struct intel_dmc dynamically, and hide all the dmc details
>> behind an opaque pointer in intel_dmc.c.
>>
>> Care must be taken to take into account all cases: DMC not supported on
>> the platform, DMC supported but not initialized, and DMC initialized but
>> not loaded. For the second case, we need to move the wakeref out of
>> struct intel_dmc.
>>
>> Cc: Imre Deak
>> Signed-off-by: Jani Nikula
>> ---
>> .../gpu/drm/i915/display/intel_display_core.h | 8 ++-
>> drivers/gpu/drm/i915/display/intel_dmc.c | 50 +--
>> drivers/gpu/drm/i915/display/intel_dmc.h | 34 +
>> .../drm/i915/display/intel_modeset_setup.c| 1 +
>> 4 files changed, 53 insertions(+), 40 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
>> b/drivers/gpu/drm/i915/display/intel_display_core.h
>> index 631a7b17899e..fdab7bb93a7d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -19,7 +19,6 @@
>> #include "intel_cdclk.h"
>> #include "intel_display_limits.h"
>> #include "intel_display_power.h"
>> -#include "intel_dmc.h"
>> #include "intel_dpll_mgr.h"
>> #include "intel_fbc.h"
>> #include "intel_global_state.h"
>> @@ -40,6 +39,7 @@ struct intel_cdclk_vals;
>> struct intel_color_funcs;
>> struct intel_crtc;
>> struct intel_crtc_state;
>> +struct intel_dmc;
>> struct intel_dpll_funcs;
>> struct intel_dpll_mgr;
>> struct intel_fbdev;
>> @@ -340,6 +340,11 @@ struct intel_display {
>> spinlock_t phy_lock;
>> } dkl;
>>
>> +struct {
>> +struct intel_dmc *dmc;
>> +intel_wakeref_t wakeref;
>> +} dmc;
>> +
>> struct {
>> /* VLV/CHV/BXT/GLK DSI MMIO register base address */
>> u32 mmio_base;
>> @@ -467,7 +472,6 @@ struct intel_display {
>>
>> /* Grouping using named structs. Keep sorted. */
>> struct intel_audio audio;
>> -struct intel_dmc dmc;
>> struct intel_dpll dpll;
>> struct intel_fbc *fbc[I915_MAX_FBCS];
>> struct intel_frontbuffer_tracking fb_tracking;
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
>> b/drivers/gpu/drm/i915/display/intel_dmc.c
>> index 0b54b9b96249..8deebd4b62fb 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>> @@ -38,9 +38,37 @@
>> * low-power state and comes back to normal.
>> */
>>
>> +enum intel_dmc_id {
>> +DMC_FW_MAIN = 0,
>> +DMC_FW_PIPEA,
>> +DMC_FW_PIPEB,
>> +DMC_FW_PIPEC,
>> +DMC_FW_PIPED,
>> +DMC_FW_MAX
>> +};
>> +
>> +struct intel_dmc {
>> +struct drm_i915_private *i915;
>> +struct work_struct work;
>> +const char *fw_path;
>> +u32 max_fw_size; /* bytes */
>> +u32 version;
>> +struct dmc_fw_info {
>> +u32 mmio_count;
>> +i915_reg_t mmioaddr[20];
>> +u32 mmiodata[20];
>> +u32 dmc_offset;
>> +u32 start_mmioaddr;
>> +u32 dmc_fw_size; /*dwords */
>> +u32 *payload;
>> +bool present;
>> +} dmc_info[DMC_FW_MAX];
>> +};
>> +
>> +/* Note: This may be NULL. */
>> static struct intel_dmc *i915_to_dmc(struct drm_i915_private *i915)
>> {
>> -return >display.dmc;
>> +return i915->display.dmc.dmc;
>> }
>>
>> #define DMC_VERSION(major, minor) ((major) << 16 | (minor))
>> @@ -937,7 +965,10 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
>> if (!HAS_DMC(dev_priv))
>> return;
>>
>> -dmc = i915_to_dmc(dev_priv);
>> +dmc = kzalloc(sizeof(*dmc), GFP_KERNEL);
>> +if (!dmc)
>> +return;
>
> I missed this in my review: the above implies the same thing as the
> firmware not being loaded for other reasons, so it would still require
> calling intel_dmc_runtime_pm_get() as it's done in those cases.
Aye. Good catch.
>
>> +
>> dmc->i915 = dev_priv;
>>
>> INIT_WORK(>work, dmc_load_work_fn);
>> @@ -991,10 +1022,9 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
>>
>> if (dev_priv->params.dmc_firmware_path) {
>> if (strlen(dev_priv->params.dmc_firmware_path) == 0) {
>> -dmc->fw_path = NULL;
>> drm_info(_priv->drm,
>> "Disabling DMC firmware and runtime PM\n");
>> -return;
>> +goto out;
>> }
>>
>> dmc->fw_path = dev_priv->params.dmc_firmware_path;
>> @@ -1003,11 +1033,18 @@ void intel_dmc_init(struct drm_i915_private
>> *dev_priv)
>> if (!dmc->fw_path) {
>> drm_dbg_kms(_priv->drm,
>> "No known DMC firmware
Re: [Intel-gfx] [PATCH v3 4/4] drm/i915/dmc: allocate dmc structure dynamically
On Mon, Feb 27, 2023 at 07:25:21PM +0200, Jani Nikula wrote:
> sizeof(struct intel_dmc) > 1024 bytes, allocated on all platforms as
> part of struct drm_i915_private, whether they have DMC or not.
>
> Allocate struct intel_dmc dynamically, and hide all the dmc details
> behind an opaque pointer in intel_dmc.c.
>
> Care must be taken to take into account all cases: DMC not supported on
> the platform, DMC supported but not initialized, and DMC initialized but
> not loaded. For the second case, we need to move the wakeref out of
> struct intel_dmc.
>
> Cc: Imre Deak
> Signed-off-by: Jani Nikula
> ---
> .../gpu/drm/i915/display/intel_display_core.h | 8 ++-
> drivers/gpu/drm/i915/display/intel_dmc.c | 50 +--
> drivers/gpu/drm/i915/display/intel_dmc.h | 34 +
> .../drm/i915/display/intel_modeset_setup.c| 1 +
> 4 files changed, 53 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 631a7b17899e..fdab7bb93a7d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -19,7 +19,6 @@
> #include "intel_cdclk.h"
> #include "intel_display_limits.h"
> #include "intel_display_power.h"
> -#include "intel_dmc.h"
> #include "intel_dpll_mgr.h"
> #include "intel_fbc.h"
> #include "intel_global_state.h"
> @@ -40,6 +39,7 @@ struct intel_cdclk_vals;
> struct intel_color_funcs;
> struct intel_crtc;
> struct intel_crtc_state;
> +struct intel_dmc;
> struct intel_dpll_funcs;
> struct intel_dpll_mgr;
> struct intel_fbdev;
> @@ -340,6 +340,11 @@ struct intel_display {
> spinlock_t phy_lock;
> } dkl;
>
> + struct {
> + struct intel_dmc *dmc;
> + intel_wakeref_t wakeref;
> + } dmc;
> +
> struct {
> /* VLV/CHV/BXT/GLK DSI MMIO register base address */
> u32 mmio_base;
> @@ -467,7 +472,6 @@ struct intel_display {
>
> /* Grouping using named structs. Keep sorted. */
> struct intel_audio audio;
> - struct intel_dmc dmc;
> struct intel_dpll dpll;
> struct intel_fbc *fbc[I915_MAX_FBCS];
> struct intel_frontbuffer_tracking fb_tracking;
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 0b54b9b96249..8deebd4b62fb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -38,9 +38,37 @@
> * low-power state and comes back to normal.
> */
>
> +enum intel_dmc_id {
> + DMC_FW_MAIN = 0,
> + DMC_FW_PIPEA,
> + DMC_FW_PIPEB,
> + DMC_FW_PIPEC,
> + DMC_FW_PIPED,
> + DMC_FW_MAX
> +};
> +
> +struct intel_dmc {
> + struct drm_i915_private *i915;
> + struct work_struct work;
> + const char *fw_path;
> + u32 max_fw_size; /* bytes */
> + u32 version;
> + struct dmc_fw_info {
> + u32 mmio_count;
> + i915_reg_t mmioaddr[20];
> + u32 mmiodata[20];
> + u32 dmc_offset;
> + u32 start_mmioaddr;
> + u32 dmc_fw_size; /*dwords */
> + u32 *payload;
> + bool present;
> + } dmc_info[DMC_FW_MAX];
> +};
> +
> +/* Note: This may be NULL. */
> static struct intel_dmc *i915_to_dmc(struct drm_i915_private *i915)
> {
> - return >display.dmc;
> + return i915->display.dmc.dmc;
> }
>
> #define DMC_VERSION(major, minor)((major) << 16 | (minor))
> @@ -937,7 +965,10 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
> if (!HAS_DMC(dev_priv))
> return;
>
> - dmc = i915_to_dmc(dev_priv);
> + dmc = kzalloc(sizeof(*dmc), GFP_KERNEL);
> + if (!dmc)
> + return;
I missed this in my review: the above implies the same thing as the
firmware not being loaded for other reasons, so it would still require
calling intel_dmc_runtime_pm_get() as it's done in those cases.
> +
> dmc->i915 = dev_priv;
>
> INIT_WORK(>work, dmc_load_work_fn);
> @@ -991,10 +1022,9 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
>
> if (dev_priv->params.dmc_firmware_path) {
> if (strlen(dev_priv->params.dmc_firmware_path) == 0) {
> - dmc->fw_path = NULL;
> drm_info(_priv->drm,
>"Disabling DMC firmware and runtime PM\n");
> - return;
> + goto out;
> }
>
> dmc->fw_path = dev_priv->params.dmc_firmware_path;
> @@ -1003,11 +1033,18 @@ void intel_dmc_init(struct drm_i915_private *dev_priv)
> if (!dmc->fw_path) {
> drm_dbg_kms(_priv->drm,
> "No known DMC firmware for platform, disabling
> runtime PM\n");
> - return;
> + goto out;
> }
>
> + dev_priv->display.dmc.dmc = dmc;
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/4] drm/i915/power: move dc state members to struct i915_power_domains (rev2)
== Series Details == Series: series starting with [v3,1/4] drm/i915/power: move dc state members to struct i915_power_domains (rev2) URL : https://patchwork.freedesktop.org/series/114431/ State : success == Summary == CI Bug Log - changes from CI_DRM_12794 -> Patchwork_114431v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/index.html Participating hosts (39 -> 37) -- Missing(2): fi-kbl-soraka fi-snb-2520m Known issues Here are the changes found in Patchwork_114431v2 that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@module-reload: - bat-dg1-7: [PASS][1] -> [SKIP][2] ([i915#7855]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12794/bat-dg1-7/igt@i915_pm_...@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/bat-dg1-7/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live@hangcheck: - bat-adlp-9: [PASS][3] -> [INCOMPLETE][4] ([i915#7677]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12794/bat-adlp-9/igt@i915_selftest@l...@hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/bat-adlp-9/igt@i915_selftest@l...@hangcheck.html * igt@i915_selftest@live@requests: - bat-rpls-1: [PASS][5] -> [ABORT][6] ([i915#4983] / [i915#7694] / [i915#7911]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12794/bat-rpls-1/igt@i915_selftest@l...@requests.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/bat-rpls-1/igt@i915_selftest@l...@requests.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-dg2-11: NOTRUN -> [SKIP][7] ([i915#7828]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html Possible fixes * igt@gem_exec_gttfill@basic: - fi-pnv-d510:[FAIL][8] ([i915#7229]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12794/fi-pnv-d510/igt@gem_exec_gttf...@basic.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/fi-pnv-d510/igt@gem_exec_gttf...@basic.html * igt@gem_exec_suspend@basic-s3@smem: - bat-dg2-11: [INCOMPLETE][10] ([i915#6311]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12794/bat-dg2-11/igt@gem_exec_suspend@basic...@smem.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/bat-dg2-11/igt@gem_exec_suspend@basic...@smem.html * igt@i915_selftest@live@hangcheck: - fi-skl-guc: [DMESG-WARN][12] ([i915#8073]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12794/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html * igt@i915_selftest@live@migrate: - bat-atsm-1: [DMESG-FAIL][14] ([i915#7699]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12794/bat-atsm-1/igt@i915_selftest@l...@migrate.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/bat-atsm-1/igt@i915_selftest@l...@migrate.html * igt@i915_selftest@live@workarounds: - bat-rpls-2: [DMESG-WARN][16] ([i915#7852]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12794/bat-rpls-2/igt@i915_selftest@l...@workarounds.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/bat-rpls-2/igt@i915_selftest@l...@workarounds.html Warnings * igt@i915_selftest@live@slpc: - bat-rpls-2: [DMESG-FAIL][18] ([i915#6997]) -> [DMESG-FAIL][19] ([i915#6367] / [i915#7913] / [i915#7996]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12794/bat-rpls-2/igt@i915_selftest@l...@slpc.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114431v2/bat-rpls-2/igt@i915_selftest@l...@slpc.html [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#6311]: https://gitlab.freedesktop.org/drm/intel/issues/6311 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997 [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229 [i915#7677]: https://gitlab.freedesktop.org/drm/intel/issues/7677 [i915#7694]: https://gitlab.freedesktop.org/drm/intel/issues/7694 [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7852]: https://gitlab.freedesktop.org/drm/intel/issues/7852 [i915#7855]: https://gitlab.freedesktop.org/drm/intel/issues/7855 [i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911 [i915#7913]:
[Intel-gfx] [PATCH v2] drm/i915/mtl: Apply Wa_14017073508 for MTL Media Step
Apply Wa_14017073508 for MTL Media step instead of graphics step.
v2: Use Media stepping instead of SoC die stepping (Matt)
Bspec: 66623
Fixes: 8f70f1ec587d ("drm/i915/mtl: Add Wa_14017073508 for SAMedia")
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index cef3d6f5c34e..a14f23b3355a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -29,7 +29,7 @@
static void mtl_media_busy(struct intel_gt *gt)
{
/* Wa_14017073508: mtl */
- if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) &&
+ if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
gt->type == GT_MEDIA)
snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE,
PCODE_MBOX_GT_STATE_MEDIA_BUSY,
@@ -39,7 +39,7 @@ static void mtl_media_busy(struct intel_gt *gt)
static void mtl_media_idle(struct intel_gt *gt)
{
/* Wa_14017073508: mtl */
- if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) &&
+ if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
gt->type == GT_MEDIA)
snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE,
PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
index fcf51614f9a4..a53a995c3950 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
@@ -19,7 +19,7 @@ static bool __guc_rc_supported(struct intel_guc *guc)
* Do not enable gucrc to avoid additional interrupts which
* may disrupt pcode wa.
*/
- if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) &&
+ if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
gt->type == GT_MEDIA)
return false;
--
2.25.1
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/4] drm/i915/power: move dc state members to struct i915_power_domains (rev2)
== Series Details == Series: series starting with [v3,1/4] drm/i915/power: move dc state members to struct i915_power_domains (rev2) URL : https://patchwork.freedesktop.org/series/114431/ State : warning == Summary == Error: dim checkpatch failed 4a10ed5e711d drm/i915/power: move dc state members to struct i915_power_domains e87932026c47 drm/i915/dmc: use has_dmc_id_fw() instead of poking dmc->dmc_info directly 7e082d99c2f8 drm/i915/dmc: add i915_to_dmc() and dmc->i915 and use them -:63: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #63: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:529: + !intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)), total: 0 errors, 1 warnings, 0 checks, 270 lines checked 9a7f2c315baa drm/i915/dmc: allocate dmc structure dynamically
Re: [Intel-gfx] [PATCH v5 07/19] vfio: Block device access via device fd until device is opened
> From: Liu, Yi L
> Sent: Monday, February 27, 2023 7:11 PM
>
> Allow the vfio_device file to be in a state where the device FD is
> opened but the device cannot be used by userspace (i.e. its .open_device()
> hasn't been called). This inbetween state is not used when the device
> FD is spawned from the group FD, however when we create the device FD
> directly by opening a cdev it will be opened in the blocked state.
>
> The reason for the inbetween state is that userspace only gets a FD but
> doesn't gain access permission until binding the FD to an iommufd. So in
> the blocked state, only the bind operation is allowed. Completing bind
> will allow user to further access the device.
>
> This is implemented by adding a flag in struct vfio_device_file to mark
> the blocked state and using a simple smp_load_acquire() to obtain the
> flag value and serialize all the device setup with the thread accessing
> this device.
>
> Following this lockless scheme, it can safely handle the device FD
> unbound->bound but it cannot handle bound->unbound. To allow this we'd
> need to add a lock on all the vfio ioctls which seems costly. So once
> device FD is bound, it remains bound until the FD is closed.
>
> Suggested-by: Jason Gunthorpe
> Signed-off-by: Yi Liu
> Reviewed-by: Kevin Tian
> ---
> drivers/vfio/group.c | 6 ++
> drivers/vfio/vfio.h | 1 +
> drivers/vfio/vfio_main.c | 16
> 3 files changed, 23 insertions(+)
>
> diff --git a/drivers/vfio/group.c b/drivers/vfio/group.c
> index 960b1bcb606b..d8771d585cb1 100644
> --- a/drivers/vfio/group.c
> +++ b/drivers/vfio/group.c
> @@ -197,6 +197,12 @@ static int vfio_device_group_open(struct
> vfio_device_file *df)
> if (device->open_count == 0)
> vfio_device_put_kvm(device);
>
> + /*
> + * Paired with smp_load_acquire() in vfio_device_fops::ioctl/
> + * read/write/mmap
> + */
> + smp_store_release(>access_granted, true);
> +
A bug. If ret is false, it should not set df->access_granted. Would
be fixed in the next version.
Regards,
Yi Liu
> mutex_unlock(>dev_set->lock);
>
> out_unlock:
> diff --git a/drivers/vfio/vfio.h b/drivers/vfio/vfio.h
> index 7c1ea870d8f3..2e3cb284711d 100644
> --- a/drivers/vfio/vfio.h
> +++ b/drivers/vfio/vfio.h
> @@ -18,6 +18,7 @@ struct vfio_container;
>
> struct vfio_device_file {
> struct vfio_device *device;
> + bool access_granted;
> spinlock_t kvm_ref_lock; /* protect kvm field */
> struct kvm *kvm;
> struct iommufd_ctx *iommufd; /* protected by struct
> vfio_device_set::lock */
> diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
> index 609700748082..d16ac573e290 100644
> --- a/drivers/vfio/vfio_main.c
> +++ b/drivers/vfio/vfio_main.c
> @@ -1106,6 +1106,10 @@ static long vfio_device_fops_unl_ioctl(struct file
> *filep,
> struct vfio_device *device = df->device;
> int ret;
>
> + /* Paired with smp_store_release() in vfio_device_group_open()
> */
> + if (!smp_load_acquire(>access_granted))
> + return -EINVAL;
> +
> ret = vfio_device_pm_runtime_get(device);
> if (ret)
> return ret;
> @@ -1133,6 +1137,10 @@ static ssize_t vfio_device_fops_read(struct file
> *filep, char __user *buf,
> struct vfio_device_file *df = filep->private_data;
> struct vfio_device *device = df->device;
>
> + /* Paired with smp_store_release() in vfio_device_group_open()
> */
> + if (!smp_load_acquire(>access_granted))
> + return -EINVAL;
> +
> if (unlikely(!device->ops->read))
> return -EINVAL;
>
> @@ -1146,6 +1154,10 @@ static ssize_t vfio_device_fops_write(struct file
> *filep,
> struct vfio_device_file *df = filep->private_data;
> struct vfio_device *device = df->device;
>
> + /* Paired with smp_store_release() in vfio_device_group_open()
> */
> + if (!smp_load_acquire(>access_granted))
> + return -EINVAL;
> +
> if (unlikely(!device->ops->write))
> return -EINVAL;
>
> @@ -1157,6 +1169,10 @@ static int vfio_device_fops_mmap(struct file
> *filep, struct vm_area_struct *vma)
> struct vfio_device_file *df = filep->private_data;
> struct vfio_device *device = df->device;
>
> + /* Paired with smp_store_release() in vfio_device_group_open()
> */
> + if (!smp_load_acquire(>access_granted))
> + return -EINVAL;
> +
> if (unlikely(!device->ops->mmap))
> return -EINVAL;
>
> --
> 2.34.1
Re: [Intel-gfx] [PATCH v5 16/19] vfio: Add VFIO_DEVICE_BIND_IOMMUFD
> From: Liu, Yi L
> Sent: Monday, February 27, 2023 7:12 PM
[...]
> +long vfio_device_ioctl_bind_iommufd(struct vfio_device_file *df,
> + unsigned long arg)
> +{
> + struct vfio_device *device = df->device;
> + struct vfio_device_bind_iommufd bind;
> + struct iommufd_ctx *iommufd = NULL;
> + unsigned long minsz;
> + int ret;
> +
> + minsz = offsetofend(struct vfio_device_bind_iommufd, out_devid);
> +
> + if (copy_from_user(, (void __user *)arg, minsz))
> + return -EFAULT;
> +
> + if (bind.argsz < minsz || bind.flags)
> + return -EINVAL;
> +
> + if (!device->ops->bind_iommufd)
> + return -ENODEV;
Hi Jason,
Per the comment in vfio_iommufd_bind(), such device driver
won't provide .bind_iommufd(). So shall we allow this ioctl
to go longer to call .open_device() instead of failing it here?
I think we need to allow it to go further. E.g. leave the check
to be in vfio_iommufd_bind(). Otherwise, user may not able
to use such devices. Is it?
> +
> + ret = vfio_device_block_group(device);
> + if (ret)
> + return ret;
> +
> + mutex_lock(>dev_set->lock);
> + /*
> + * If already been bound to an iommufd, or already set noiommu
> + * then fail it.
> + */
> + if (df->iommufd || df->noiommu) {
> + ret = -EINVAL;
> + goto out_unlock;
> + }
> +
> + /* iommufd < 0 means noiommu mode */
> + if (bind.iommufd < 0) {
> + if (!capable(CAP_SYS_RAWIO)) {
> + ret = -EPERM;
> + goto out_unlock;
> + }
> + df->noiommu = true;
> + } else {
> + iommufd = vfio_get_iommufd_from_fd(bind.iommufd);
> + if (IS_ERR(iommufd)) {
> + ret = PTR_ERR(iommufd);
> + goto out_unlock;
> + }
> + }
> +
> + /*
> + * Before the device open, get the KVM pointer currently
> + * associated with the device file (if there is) and obtain
> + * a reference. This reference is held until device closed.
> + * Save the pointer in the device for use by drivers.
> + */
> + vfio_device_get_kvm_safe(df);
> +
> + df->iommufd = iommufd;
> + ret = vfio_device_open(df, _devid, NULL);
> + if (ret)
> + goto out_put_kvm;
[...]
>
> /* --- IOCTLs for DEVICE file descriptors --- */
>
> +/*
> + * VFIO_DEVICE_BIND_IOMMUFD - _IOR(VFIO_TYPE, VFIO_BASE + 19,
> + * struct vfio_device_bind_iommufd)
> + *
> + * Bind a vfio_device to the specified iommufd.
> + *
> + * The user should provide a device cookie when calling this ioctl. The
> + * cookie is carried only in event e.g. I/O fault reported to userspace
> + * via iommufd. The user should use devid returned by this ioctl to mark
> + * the target device in other ioctls (e.g. capability query via iommufd).
> + *
> + * User is not allowed to access the device before the binding operation
> + * is completed.
> + *
> + * Unbind is automatically conducted when device fd is closed.
> + *
> + * @argsz:user filled size of this data.
> + * @flags:reserved for future extension.
> + * @dev_cookie: a per device cookie provided by userspace.
> + * @iommufd: iommufd to bind. a negative value means noiommu.
> + * @out_devid:the device id generated by this bind.
> + *
> + * Return: 0 on success, -errno on failure.
> + */
> +struct vfio_device_bind_iommufd {
> + __u32 argsz;
> + __u32 flags;
> + __aligned_u64 dev_cookie;
> + __s32 iommufd;
> + __u32 out_devid;
As above, for the devices that do not do DMA, there is no .bind_iommufd
op, hence no iommufd_device generated. This means no good value
can be filled in this out_devid field. So this field is optional. Only
for the devices which do DMA, should this out_devid field return a
valid ID otherwise an invalid ID would be filled (e.g. value #0 is an
invalid value in the iommufd object id pool). Userspace needs to
check if the out_devid is valid or not before use. This ID can be further
used in iommufd uAPIs like IOMMU_HWPT_ALLOC, IOMMU_DEVICE_GET_INFO
and etc.
> +};
> +
> +#define VFIO_DEVICE_BIND_IOMMUFD _IO(VFIO_TYPE, VFIO_BASE
> + 19)
> +
> /**
> * VFIO_DEVICE_GET_INFO - _IOR(VFIO_TYPE, VFIO_BASE + 7,
> * struct vfio_device_info)
> --
> 2.34.1
Regards,
Yi Liu
[Intel-gfx] [CI v2 1/1] drm/i915/active: Fix misuse of non-idle barriers as fence trackers
Users reported oopses on list corruptions when using i915 perf with a
number of concurrently running graphics applications. Root cause analysis
pointed at an issue in barrier processing code -- a race among perf open /
close replacing active barriers with perf requests on kernel context and
concurrent barrier preallocate / acquire operations performed during user
context first pin / last unpin.
When adding a request to a composite tracker, we try to reuse an existing
fence tracker, already allocated and registered with that composite. The
tracker we obtain may already track another fence, may be an idle barrier,
or an active barrier.
If the tracker we get occurs a non-idle barrier then we try to delete that
barrier from a list of barrier tasks it belongs to. However, while doing
that we don't respect return value from a function that performs the
barrier deletion. Should the deletion ever failed, we would end up
reusing the tracker still registered as a barrier task. Since the same
structure field is reused with both fence callback lists and barrier
tasks list, list corruptions would likely occur.
Barriers are now deleted from a barrier tasks list by temporarily removing
the list content, traversing that content with skip over the node to be
deleted, then populating the list back with the modified content. Should
that intentionally racy concurrent deletion attempts be not serialized,
one or more of those may fail because of the list being temporary empty.
Related code that ignores the results of barrier deletion was initially
introduced in v5.4 by commit d8af05ff38ae ("drm/i915: Allow sharing the
idle-barrier from other kernel requests"). However, all users of the
barrier deletion routine were apparently serialized at that time, then the
issue didn't exhibit itself. Results of git bisect with help of a newly
developed igt@gem_barrier_race@remote-request IGT test indicate that list
corruptions might start to appear after commit 311770173fac ("drm/i915/gt:
Schedule request retirement when timeline idles"), introduced in v5.5.
Respect results of barrier deletion attempts -- mark the barrier as idle
only if successfully deleted from the list. Then, before proceeding with
setting our fence as the one currently tracked, make sure that the tracker
we've got is not a non-idle barrier. If that check fails then don't use
that tracker but go back and try to acquire a new, usable one.
v2: no code changes,
- blame commit 311770173fac ("drm/i915/gt: Schedule request retirement
when timeline idles"), v5.5, not commit d8af05ff38ae ("drm/i915: Allow
sharing the idle-barrier from other kernel requests"), v5.4,
- reword commit description.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6333
Fixes: 311770173fac ("drm/i915/gt: Schedule request retirement when timeline
idles")
Cc: Chris Wilson
Cc: sta...@vger.kernel.org # v5.5
Signed-off-by: Janusz Krzysztofik
---
drivers/gpu/drm/i915/i915_active.c | 25 ++---
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_active.c
b/drivers/gpu/drm/i915/i915_active.c
index 7412abf166a8c..f9282b8c87c1c 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -422,12 +422,12 @@ replace_barrier(struct i915_active *ref, struct
i915_active_fence *active)
* we can use it to substitute for the pending idle-barrer
* request that we want to emit on the kernel_context.
*/
- __active_del_barrier(ref, node_from_active(active));
- return true;
+ return __active_del_barrier(ref, node_from_active(active));
}
int i915_active_add_request(struct i915_active *ref, struct i915_request *rq)
{
+ u64 idx = i915_request_timeline(rq)->fence_context;
struct dma_fence *fence = >fence;
struct i915_active_fence *active;
int err;
@@ -437,16 +437,19 @@ int i915_active_add_request(struct i915_active *ref,
struct i915_request *rq)
if (err)
return err;
- active = active_instance(ref, i915_request_timeline(rq)->fence_context);
- if (!active) {
- err = -ENOMEM;
- goto out;
- }
+ do {
+ active = active_instance(ref, idx);
+ if (!active) {
+ err = -ENOMEM;
+ goto out;
+ }
+
+ if (replace_barrier(ref, active)) {
+ RCU_INIT_POINTER(active->fence, NULL);
+ atomic_dec(>count);
+ }
+ } while (is_barrier(active));
- if (replace_barrier(ref, active)) {
- RCU_INIT_POINTER(active->fence, NULL);
- atomic_dec(>count);
- }
if (!__i915_active_fence_set(active, fence))
__i915_active_acquire(ref);
--
2.25.1
[Intel-gfx] [CI v2 0/1] drm/i915/active: Fix misuse of non-idle barriers as fence trackers
Dummy cover letter to prevent CI / patchwork from picking up a previous one with an outdated Test-with: clause. Janusz Krzysztofik (1): drm/i915/active: Fix misuse of non-idle barriers as fence trackers drivers/gpu/drm/i915/i915_active.c | 25 ++--- 1 file changed, 14 insertions(+), 11 deletions(-) -- 2.25.1
Re: [Intel-gfx] [Intel-gfx V2] drm/i915/selftests: Fix live_requests for all engines
Hi Tejas, On Tue, Feb 28, 2023 at 10:13:07AM +0530, Tejas Upadhyay wrote: > From: Tvrtko Ursulin > > After the abandonment of i915->kernel_context and since we have started to > create per-gt engine->kernel_context, these tests need to be updated to > instantiate the batch buffer VMA in the correct PPGTT for the context used > to execute each spinner. > > v2(Tejas): > - Clean commit message - Matt > - Add BUG_ON to match vm > v3(Tejas): > - Fix dim checkpatch warnings > > Acked-by: Andi Shyti > Signed-off-by: Tvrtko Ursulin > Signed-off-by: Tejas Upadhyay Reviewed-by: Andi Shyti Thanks Tejas, Andi
[Intel-gfx] [CI v2 1/1] drm/i915/active: Fix misuse of non-idle barriers as fence trackers
Users reported oopses on list corruptions when using i915 perf with a
number of concurrently running graphics applications. Root cause analysis
pointed at an issue in barrier processing code -- a race among perf open /
close replacing active barriers with perf requests on kernel context and
concurrent barrier preallocate / acquire operations performed during user
context first pin / last unpin.
When adding a request to a composite tracker, we try to reuse an existing
fence tracker, already allocated and registered with that composite. The
tracker we obtain may already track another fence, may be an idle barrier,
or an active barrier.
If the tracker we get occurs a non-idle barrier then we try to delete that
barrier from a list of barrier tasks it belongs to. However, while doing
that we don't respect return value from a function that performs the
barrier deletion. Should the deletion ever failed, we would end up
reusing the tracker still registered as a barrier task. Since the same
structure field is reused with both fence callback lists and barrier
tasks list, list corruptions would likely occur.
Barriers are now deleted from a barrier tasks list by temporarily removing
the list content, traversing that content with skip over the node to be
deleted, then populating the list back with the modified content. Should
that intentionally racy concurrent deletion attempts be not serialized,
one or more of those may fail because of the list being temporary empty.
Related code that ignores the results of barrier deletion was initially
introduced in v5.4 by commit d8af05ff38ae ("drm/i915: Allow sharing the
idle-barrier from other kernel requests"). However, all users of the
barrier deletion routine were apparently serialized at that time, then the
issue didn't exhibit itself. Results of git bisect with help of a newly
developed igt@gem_barrier_race@remote-request IGT test indicate that list
corruptions might start to appear after commit 311770173fac ("drm/i915/gt:
Schedule request retirement when timeline idles"), introduced in v5.5.
Respect results of barrier deletion attempts -- mark the barrier as idle
only if successfully deleted from the list. Then, before proceeding with
setting our fence as the one currently tracked, make sure that the tracker
we've got is not a non-idle barrier. If that check fails then don't use
that tracker but go back and try to acquire a new, usable one.
v2: no code changes,
- blame commit 311770173fac ("drm/i915/gt: Schedule request retirement
when timeline idles"), v5.5, not commit d8af05ff38ae ("drm/i915: Allow
sharing the idle-barrier from other kernel requests"), v5.4,
- reword commit description.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6333
Fixes: 311770173fac ("drm/i915/gt: Schedule request retirement when timeline
idles")
Cc: Chris Wilson
Cc: sta...@vger.kernel.org # v5.5
Signed-off-by: Janusz Krzysztofik
---
drivers/gpu/drm/i915/i915_active.c | 25 ++---
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_active.c
b/drivers/gpu/drm/i915/i915_active.c
index 7412abf166a8c..f9282b8c87c1c 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -422,12 +422,12 @@ replace_barrier(struct i915_active *ref, struct
i915_active_fence *active)
* we can use it to substitute for the pending idle-barrer
* request that we want to emit on the kernel_context.
*/
- __active_del_barrier(ref, node_from_active(active));
- return true;
+ return __active_del_barrier(ref, node_from_active(active));
}
int i915_active_add_request(struct i915_active *ref, struct i915_request *rq)
{
+ u64 idx = i915_request_timeline(rq)->fence_context;
struct dma_fence *fence = >fence;
struct i915_active_fence *active;
int err;
@@ -437,16 +437,19 @@ int i915_active_add_request(struct i915_active *ref,
struct i915_request *rq)
if (err)
return err;
- active = active_instance(ref, i915_request_timeline(rq)->fence_context);
- if (!active) {
- err = -ENOMEM;
- goto out;
- }
+ do {
+ active = active_instance(ref, idx);
+ if (!active) {
+ err = -ENOMEM;
+ goto out;
+ }
+
+ if (replace_barrier(ref, active)) {
+ RCU_INIT_POINTER(active->fence, NULL);
+ atomic_dec(>count);
+ }
+ } while (is_barrier(active));
- if (replace_barrier(ref, active)) {
- RCU_INIT_POINTER(active->fence, NULL);
- atomic_dec(>count);
- }
if (!__i915_active_fence_set(active, fence))
__i915_active_acquire(ref);
--
2.25.1
[Intel-gfx] [CI v2 0/1] drm/i915/active: Fix misuse of non-idle barriers as fence trackers
Dummy cover letter to prevent CI / patchwork from picking up a previous one with an outdated Test-with: clause. Janusz Krzysztofik (1): drm/i915/active: Fix misuse of non-idle barriers as fence trackers drivers/gpu/drm/i915/i915_active.c | 25 ++--- 1 file changed, 14 insertions(+), 11 deletions(-) -- 2.25.1
Re: [Intel-gfx] [PATCH v2] drm/edid: Fix csync detailed mode parsing
On Tue, 28 Feb 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Remove the bogus csync check and replace it with something that:
> - triggers for all forms of csync, not just the basic analog variant
> - actually populates the mode csync flags so that drivers can
> decide what to do with the mode
>
> Originally the code tried to outright reject csync, but that
> apparently broke some bogus LCD monitor that claimed to have
> a detailed mode that uses analog csync, despite also claiming
> the monitor only support separate sync:
> https://bugzilla.redhat.com/show_bug.cgi?id=540024
> Potentially that monitor should just be quirked or something.
>
> Anyways, what we are dealing with now is some kind of funny i915
> JSL machine with eDP where the panel claims to support a sensible
> 60Hz separate sync mode, and a 50Hz mode with bipolar analog
> csync. The 50Hz mode does not work so we want to not use it.
> Easiest way is to just correctly flag it as csync and the driver
> will reject it.
>
> TODO: or should we just reject any form of csync (or at least
> the analog variants) for digital display interfaces?
>
> v2: Grab digital csync polarity from hsync polarity bit (Jani)
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8146
> Reviewed-by: Jani Nikula #v1
Yup. Fingers crossed.
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_edid.c | 29 +
> include/drm/drm_edid.h | 12 +---
> 2 files changed, 30 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index ebab862b8b1a..c18ec866678d 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -3424,10 +3424,6 @@ static struct drm_display_mode
> *drm_mode_detailed(struct drm_connector *connecto
> connector->base.id, connector->name);
> return NULL;
> }
> - if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
> - drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not
> supported\n",
> - connector->base.id, connector->name);
> - }
>
> /* it is incorrect if hsync/vsync width is zero */
> if (!hsync_pulse_width || !vsync_pulse_width) {
> @@ -3474,10 +3470,27 @@ static struct drm_display_mode
> *drm_mode_detailed(struct drm_connector *connecto
> if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
> mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
> } else {
> - mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
> - DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
> - mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
> - DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
> + switch (pt->misc & DRM_EDID_PT_SYNC_MASK) {
> + case DRM_EDID_PT_ANALOG_CSYNC:
> + case DRM_EDID_PT_BIPOLAR_ANALOG_CSYNC:
> + drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Analog composite
> sync!\n",
> + connector->base.id, connector->name);
> + mode->flags |= DRM_MODE_FLAG_CSYNC |
> DRM_MODE_FLAG_NCSYNC;
> + break;
> + case DRM_EDID_PT_DIGITAL_CSYNC:
> + drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Digital composite
> sync!\n",
> + connector->base.id, connector->name);
> + mode->flags |= DRM_MODE_FLAG_CSYNC;
> + mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
> + DRM_MODE_FLAG_PCSYNC : DRM_MODE_FLAG_NCSYNC;
> + break;
> + case DRM_EDID_PT_DIGITAL_SEPARATE_SYNC:
> + mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
> + DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
> + mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
> + DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
> + break;
> + }
> }
>
> set_size:
> diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
> index 70ae6c290bdc..571885d32907 100644
> --- a/include/drm/drm_edid.h
> +++ b/include/drm/drm_edid.h
> @@ -61,9 +61,15 @@ struct std_timing {
> u8 vfreq_aspect;
> } __attribute__((packed));
>
> -#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
> -#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
> -#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
> +#define DRM_EDID_PT_SYNC_MASK (3 << 3)
> +# define DRM_EDID_PT_ANALOG_CSYNC (0 << 3)
> +# define DRM_EDID_PT_BIPOLAR_ANALOG_CSYNC (1 << 3)
> +# define DRM_EDID_PT_DIGITAL_CSYNC (2 << 3)
> +# define DRM_EDID_PT_CSYNC_ON_RGB (1 << 1) /* analog csync only */
> +# define DRM_EDID_PT_CSYNC_SERRATE(1 << 2)
> +# define DRM_EDID_PT_DIGITAL_SEPARATE_SYNC (3 << 3)
> +# define
