== Series Details ==
Series: drm/i915/mtl: Add Support for C10 phy
URL : https://patchwork.freedesktop.org/series/116191/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12981_full -> Patchwork_116191v1_full
Summary
---
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: e134c93f788fb93fd6a3ec3af9af850a2048c7e6 Add linux-next specific
files for 20230406
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202303082135.njdx1bij-...@intel.com
https
> From: Alex Williamson
> Sent: Friday, April 7, 2023 2:58 AM
> > >
> > > You don't say anything about potential restriction, ie. what if the user
> > > calls
> > > KVM_DEV_VFIO_FILE with device fds while it has been using legacy
> container/group
> > > API?
> >
> > legacy container/group path
Hi Dmitry
> -Original Message-
> From: Dmitry Baryshkov
> Sent: Friday, April 7, 2023 8:28 AM
> To: Kandpal, Suraj ; Jani Nikula
> ; dri-de...@lists.freedesktop.org; intel-
> g...@lists.freedesktop.org
> Cc: Nautiyal, Ankit K ; Shankar, Uma
> ; Maarten Lankhorst
>
> Subject: Re: [PATCH
Hi Suraj
On 28/03/2023 16:20, Kandpal, Suraj wrote:
-Original Message-
From: dri-devel On Behalf Of Jani
Nikula
Sent: Wednesday, March 8, 2023 5:00 PM
To: Kandpal, Suraj ; dri-
de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
Cc: Dmitry Baryshkov ; Nautiyal, Ankit K
;
On Fri, Mar 31, 2023 at 03:52:16PM -0700, john.c.harri...@intel.com wrote:
From: John Harrison
First release of GuC for Meteorlake.
NB: As this is still pre-release and likely to change, use explicit
versioning for now. The official, full release will use reduced
version naming.
== Series Details ==
Series: Improvements to GuC error capture list processing
URL : https://patchwork.freedesktop.org/series/116219/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12981 -> Patchwork_116219v1
Summary
== Series Details ==
Series: Improvements to GuC error capture list processing
URL : https://patchwork.freedesktop.org/series/116219/
State : warning
== Summary ==
Error: dim checkpatch failed
71d5e265121d drm/i915/guc: Don't capture Gen8 regs on Xe devices
-:35: ERROR:COMPLEX_MACRO: Macros
== Series Details ==
Series: drm/i915: Query compressed bpp properly using correct DPCD and DP Spec
info
URL : https://patchwork.freedesktop.org/series/116179/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12979_full -> Patchwork_116179v1_full
From: John Harrison
Don't use GEN9 as a prefix for register lists that contain all GEN8
registers.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
From: John Harrison
A pair of pre-Xe registers were being included in the Xe capture list.
GuC was rejecting those as being invalid and logging errors about
them. So, stop doing it.
Signed-off-by: John Harrison
Fixes: dce2bd542337 ("drm/i915/guc: Add Gen9 registers for GuC error state
From: John Harrison
Fix Xe_LP name.
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 44 +--
1 file changed, 21 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
From: John Harrison
Remove 99% duplicated steered register list code. Also, include the
pre-Xe steered registers in the pre-Xe list generation.
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 112 +-
1 file changed, 29 insertions(+), 83
From: John Harrison
The GuC error capture list creation was including Gen8 registers on Xe
platforms. While fixing that, it was noticed that there were other
issues. The platform naming was wrong, the naming of lists was
misleading, the steered register code was duplicated and steered
registers
From: John Harrison
Don't use 'xe_lp*' prefixes for register lists that are common with
Gen8.
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 30 +--
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git
On Thu, Apr 06, 2023 at 04:02:18PM +0300, Mika Kahola wrote:
> C10 phys uses direct mapping internally for voltage and pre-emphasis levels.
> Program the levels directly to the fields in the VDR Registers.
>
> Bspec: 65449
>
> v2: From table "C10: Tx EQ settings for DP 1.4x" it shows level 1
>
On Thu, Mar 30, 2023 at 11:42:28PM +0300, Lionel Landwerlin wrote:
> By default the indirect state sampler data (border colors) are stored
> in the same heap as the SAMPLER_STATE structure. For userspace drivers
> that can be 2 different heaps (dynamic state heap & bindless sampler
> state heap).
On Thu, Apr 06, 2023 at 07:31:28AM -0700, José Roberto de Souza wrote:
> dsparb_lock it not used anymore, nuke it.
Well, this doesn't exist in our drm-tip baseline, so it would be good
if this patch is a fixup! to whatever patch is adding this back here.
Take a look to the Jani series I just
On Thu, 6 Apr 2023 10:49:45 +
"Liu, Yi L" wrote:
> Hi Eric,
>
> > From: Eric Auger
> > Sent: Thursday, April 6, 2023 5:47 PM
> >
> > Hi Yi,
> >
> > On 4/1/23 17:18, Yi Liu wrote:
> > > This defines KVM_DEV_VFIO_FILE* and make alias with KVM_DEV_VFIO_GROUP*.
> > > Old userspace uses
== Series Details ==
Series: drm/i915/pxp: Add MTL PXP Support (rev7)
URL : https://patchwork.freedesktop.org/series/112647/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12981 -> Patchwork_112647v7
Summary
---
== Series Details ==
Series: drm/i915/pxp: Add MTL PXP Support (rev7)
URL : https://patchwork.freedesktop.org/series/112647/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/pxp: Add MTL PXP Support (rev7)
URL : https://patchwork.freedesktop.org/series/112647/
State : warning
== Summary ==
Error: dim checkpatch failed
495f3b5c4d82 drm/i915/pxp: Add GSC-CS back-end resource init and cleanup
Traceback (most recent call last):
== Series Details ==
Series: Move dma-buf mmap() reservation locking down to exporters (rev2)
URL : https://patchwork.freedesktop.org/series/116000/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12981 -> Patchwork_116000v2
>Subject: Re: [Intel-gfx] [PATCH 1/7] drm/i915/mtl: Define MOCS and PAT tables
>for MTL
>
> Hi Fei,
>
> On Mon, Apr 03, 2023 at 03:50:26PM +0300, Jani Nikula wrote:
>> On Fri, 31 Mar 2023, fei.y...@intel.com wrote:
>>> From: Fei Yang
>>>
>>> On MTL, GT can no longer allocate on LLC - only the
On Thu, Apr 06, 2023 at 04:02:17PM +0300, Mika Kahola wrote:
> From: Radhakrishna Sripada
>
> XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
> has a dedicated PIPE 5.2 Message bus for configuration. This message
> bus is used to configure the phy internal registers.
>
>
Hi Fei,
On 4/6/2023 4:55 PM, Yang, Fei wrote:
> On 4/1/2023 8:38 AM, fei.y...@intel.com wrote:
>> From: Fei Yang
>>
>> On MTL, GT can no longer allocate on LLC - only the CPU can.
>> This, along with addition of support for ADM/L4 cache calls a
>> MOCS/PAT table update.
>> Also add PTE encode
== Series Details ==
Series: Move dma-buf mmap() reservation locking down to exporters (rev2)
URL : https://patchwork.freedesktop.org/series/116000/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Thu, 6 Apr 2023 10:02:10 +
"Liu, Yi L" wrote:
> > From: Jason Gunthorpe
> > Sent: Thursday, April 6, 2023 7:23 AM
> >
> > On Wed, Apr 05, 2023 at 01:49:45PM -0600, Alex Williamson wrote:
> >
> > > > > QEMU can make a policy decision today because the kernel provides a
> > > > >
1. UAPI update:
Without actually changing backward compatible behavior, update
i915's drm-uapi comments that describe the possible error values
when creating a context with I915_CONTEXT_PARAM_PROTECTED_CONTENT.
Since the first merge of PXP support on ADL, i915 returns
-ENXIO if a dependency such
Enable PXP with MTL-GSC-CS: add the has_pxp into device info
and increase the debugfs teardown timeouts to align with
new GSC-CS + firmware specs.
Now that we have 3 places that are selecting pxp timeouts
based on tee vs gsccs back-end, let's add a helper.
Signed-off-by: Alan Previn
On legacy platforms, KCR HW enabling is done at the time the mei
component interface is bound. It's also disabled during unbind.
However, for MTL onwards, we don't depend on a tee component
to start sending GSC-CS firmware messages.
Thus, immediately enable (or disable) KCR HW on PXP's init,
fini
Add MTL hw-plumbing enabling for KCR operation under PXP
which includes:
1. Updating 'pick-gt' to get the media tile for
KCR interrupt handling
2. Adding MTL's KCR registers for PXP operation
(init, status-checking, etc.).
While doing #2, lets create a separate registers header file for
Add GSC engine based method for sending PXP firmware packets
to the GSC firmware for MTL (and future) products.
Use the newly added helpers to populate the GSC-CS memory
header and send the message packet to the FW by dispatching
the GSC_HECI_CMD_PKT instruction on the GSC engine.
We use
Add helper functions into a new file for heci-packet-submission.
The helpers will handle generating the MTL GSC-CS Memory-Header
and submission of the Heci-Cmd-Packet instructions to the engine.
NOTE1: These common functions for heci-packet-submission will be used
by different i915 callers:
Add MTL's function for ARB session creation using PXP firmware
version 4.3 ABI structure format.
Also add MTL's function for ARB session invalidation but this
reuses PXP firmware version 4.2 ABI structure format.
For both cases, in the back-end gsccs functions for sending messages
to the
This series enables PXP on MTL. On ADL/TGL platforms, we rely on
the mei driver via the i915-mei PXP component interface to establish
a connection to the security firmware via the HECI device interface.
That interface is used to create and teardown the PXP ARB session.
PXP ARB session is created
For MTL, the PXP back-end transport uses the GSC engine to submit
HECI packets through the HW to the GSC firmware for PXP arb
session management. This submission uses a non-priveleged
batch buffer, a buffer for the command packet and of course
a context targeting the GSC-CS.
Thus for MTL, we need
== Series Details ==
Series: drm/i915/guc: Disable PL1 power limit when loading GuC firmware
URL : https://patchwork.freedesktop.org/series/116172/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12976_full -> Patchwork_116172v1_full
On Thu, 6 Apr 2023 06:34:08 +
"Liu, Yi L" wrote:
> Hi Alex,
>
> > From: Alex Williamson
> > Sent: Thursday, April 6, 2023 3:50 AM
> >
> > On Wed, 5 Apr 2023 16:21:09 -0300
> > Jason Gunthorpe wrote:
> >
> > > On Wed, Apr 05, 2023 at 12:56:21PM -0600, Alex Williamson wrote:
> > > >
== Series Details ==
Series: series starting with [1/2] drm/dsc: fix drm_edp_dsc_sink_output_bpp()
DPCD high byte usage
URL : https://patchwork.freedesktop.org/series/116192/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12981 -> Patchwork_116192v1
Hi Yi,
On 4/1/23 17:18, Yi Liu wrote:
> VFIO group has historically allowed multi-open of the device FD. This
> was made secure because the "open" was executed via an ioctl to the
> group FD which is itself only single open.
>
> However, no known use of multiple device FDs today. It is kind of a
== Series Details ==
Series: series starting with [1/2] drm/dsc: fix drm_edp_dsc_sink_output_bpp()
DPCD high byte usage
URL : https://patchwork.freedesktop.org/series/116192/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be
On 3/31/23 01:02, Jani Nikula wrote:
On Thu, 30 Mar 2023, "Gustavo A. R. Silva" wrote:
Friendly ping: who can take this, please?
It's in drm-intel-gt-next.
Awesome. :) Thank you!
--
Gustavo
commit 02abecdeebfcd3848b26b70778dd7f6eb0db65e1
Author: Gustavo A. R. Silva
On Thu, Apr 06, 2023 at 10:03:51AM -0400, Rodrigo Vivi wrote:
> Hi Daniel,
>
> Here goes drm-intel-next-2023-04-06:
>
> - Fix DPT+shmem combo and add i915.enable_dpt modparam (Ville)
> - i915.enable_sagv module parameter (Ville)
> - Correction to QGV related register addresses (Vinod)
> - IPS
Don't assert held dma-buf reservation lock on memory mapping of exported
buffer.
We're going to change dma-buf mmap() locking policy such that exporters
will have to handle the lock. The previous locking policy caused deadlock
problem for DRM drivers in a case of self-imported dma-bufs once these
Change locking policy of mmap() callback, making exporters responsible
for handling dma-buf reservation locking. Previous locking policy stated
that dma-buf is locked for both importers and exporters by the dma-buf
core, which caused a deadlock problem for DRM drivers in a case of
self-imported
Replace all drm-shmem locks with a GEM reservation lock. This makes locks
consistent with dma-buf locking convention where importers are responsible
for holding reservation lock for all operations performed over dma-bufs,
preventing deadlock between dma-buf importers and exporters.
Suggested-by:
Don't assert held dma-buf reservation lock on memory mapping of exported
buffer.
We're going to change dma-buf mmap() locking policy such that exporters
will have to handle the lock. The previous locking policy caused deadlock
problem for DRM drivers in a case of self-imported dma-bufs once these
Don't assert held dma-buf reservation lock on memory mapping of exported
buffer.
We're going to change dma-buf mmap() locking policy such that exporters
will have to handle the lock. The previous locking policy caused deadlock
problem for DRM drivers in a case of self-imported dma-bufs once these
Don't assert held dma-buf reservation lock on memory mapping of exported
buffer.
We're going to change dma-buf mmap() locking policy such that exporters
will have to handle the lock. The previous locking policy caused deadlock
problem for DRM drivers in a case of self-imported dma-bufs once these
Don't assert held dma-buf reservation lock on memory mapping of exported
buffer.
We're going to change dma-buf mmap() locking policy such that exporters
will have to handle the lock. The previous locking policy caused deadlock
problem for DRM drivers in a case of self-imported dma-bufs once these
This patchset makes dma-buf exporters responisble for taking care of
the reservation lock. I also included patch that moves drm-shmem to use
reservation lock, to let CI test the whole set. I'm going to take all
the patches via the drm-misc tree, please give an ack.
Previous policy stated that
== Series Details ==
Series: drm/i915/mtl: Add Support for C10 phy
URL : https://patchwork.freedesktop.org/series/116191/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12981 -> Patchwork_116191v1
Summary
---
== Series Details ==
Series: drm/i915/mtl: Add Support for C10 phy
URL : https://patchwork.freedesktop.org/series/116191/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/mtl: Add Support for C10 phy
URL : https://patchwork.freedesktop.org/series/116191/
State : warning
== Summary ==
Error: dim checkpatch failed
09ec7a640ab5 drm/i915/mtl: Initial DDI port setup
581165ce249c drm/i915/mtl: Add DP rates
bee5f7f012de
> On 4/1/2023 8:38 AM, fei.y...@intel.com wrote:
>> From: Fei Yang
>>
>> On MTL, GT can no longer allocate on LLC - only the CPU can.
>> This, along with addition of support for ADM/L4 cache calls a
>> MOCS/PAT table update.
>> Also add PTE encode functions for MTL as it has different PAT
>>
This spin lock will not be used in older display versions, so no need
to initialize it.
Cc: intel-gfx@lists.freedesktop.org
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_dkl_phy.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
dsparb_lock it not used anymore, nuke it.
Cc: intel-gfx@lists.freedesktop.org
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display_core.h | 3 ---
drivers/gpu/drm/i915/i915_driver.c| 1 -
2 files changed, 4 deletions(-)
diff --git
Start to move the initialization of some lock from
i915_driver_early_probe().
This will also fix a warning in Xe kmd:
[ 201.894839] xe :00:02.0: [drm] [ENCODER:235:DDI A/PHY A] failed to
retrieve link info, disabling eDP
[ 202.136336] xe :00:02.0: [drm] *ERROR* Failed to write source
On 06/04/2023 15:21, Rob Clark wrote:
On Thu, Apr 6, 2023 at 4:08 AM Tvrtko Ursulin
wrote:
On 05/04/2023 18:57, Rob Clark wrote:
On Tue, Jan 31, 2023 at 3:33 AM Tvrtko Ursulin
wrote:
From: Tvrtko Ursulin
Rudimentary vendor agnostic example of how lib_igt_drm_clients can be used
to
On Thu, Apr 6, 2023 at 4:08 AM Tvrtko Ursulin
wrote:
>
>
> On 05/04/2023 18:57, Rob Clark wrote:
> > On Tue, Jan 31, 2023 at 3:33 AM Tvrtko Ursulin
> > wrote:
> >>
> >> From: Tvrtko Ursulin
> >>
> >> Rudimentary vendor agnostic example of how lib_igt_drm_clients can be used
> >> to display a
From: Tvrtko Ursulin
Rudimentary vendor agnostic example of how lib_igt_drm_clients can be used
to display a sorted by card and usage list of processes using GPUs.
Borrows a bit of code from intel_gpu_top but for now omits the fancy
features like interactive functionality, card selection,
From: Tvrtko Ursulin
Intel_gpu_top gets it's main engine configuration data via PMU probe and
uses that for per client view as well. Furthemore code so far assumed only
clients belonging from a single DRM card would be tracked in a single
clients list.
Break this inter-dependency by moving the
From: Tvrtko Ursulin
Some libdrmclient operations require that inactive clients are last in the
list. Rather than relying on callers of the library sort routine to
implement their comparison callbacks correctly, enforce this order
directly in the library and let callers comparison callbacks
From: Tvrtko Ursulin
Prep code for incoming work.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_fdinfo.c | 2 ++
lib/igt_drm_fdinfo.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/lib/igt_drm_fdinfo.c b/lib/igt_drm_fdinfo.c
index 68c89ad2c17e..b850d2210ae7 100644
---
From: Tvrtko Ursulin
Require DRM minor match during client lookup.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_clients.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/lib/igt_drm_clients.c b/lib/igt_drm_clients.c
index c23a3fae9793..e11c8b18188f 100644
From: Tvrtko Ursulin
Instead of hard coding the engine names, allow a map of names to indices
to either be passed in or it gets auto-detected (less efficient) while
parsing.
---
lib/igt_drm_clients.c | 18 +---
lib/igt_drm_clients.h | 3 ++-
lib/igt_drm_fdinfo.c| 48
From: Tvrtko Ursulin
Prepare for supporting clients belonging to multiple DRM cards by storing
the DRM minor in the client record.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_clients.c | 22 ++
lib/igt_drm_clients.h | 1 +
2 files changed, 15 insertions(+), 8
From: Tvrtko Ursulin
This is a pile of patches which implements a rudimentary vendor agnostic gputop
tool based of the new DRM spec as documented in
Documentation/gpu/drm-usage-stats.rst.
First part of the series is code refactoring which should be reasonably stable.
I've tested it all while
From: Tvrtko Ursulin
Extract some code into a new library to prepare for further work towards
making a vendor agnostic gputop tool.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_clients.c | 432 +++
lib/igt_drm_clients.h | 85 +++
lib/meson.build |
Hi Yi,
On 4/1/23 17:18, Yi Liu wrote:
> for counting the devices that are opened via the cdev path. This count
> is increased and decreased by the cdev path. The group path checks it
> to achieve exclusion with the cdev path. With this, only one path (group
> path or cdev path) will claim DMA
On 4/1/23 17:18, Yi Liu wrote:
> Allow the vfio_device file to be in a state where the device FD is
> opened but the device cannot be used by userspace (i.e. its .open_device()
> hasn't been called). This inbetween state is not used when the device
> FD is spawned from the group FD, however
Hi Daniel,
Here goes drm-intel-next-2023-04-06:
- Fix DPT+shmem combo and add i915.enable_dpt modparam (Ville)
- i915.enable_sagv module parameter (Ville)
- Correction to QGV related register addresses (Vinod)
- IPS debugfs per-crtc and new file for false_color (Ville)
- More clean-up and
On Thu, 06 Apr 2023, Jani Nikula wrote:
> On Thu, 06 Apr 2023, "Lisovskiy, Stanislav"
> wrote:
>> Not planning to upstream that actually, just for some bug on gitlab.
>> Want to see if that helps the reporter, then at least there is an idea whats
>> the problem.
>
> The issue in
The macro values just don't match the specs. Fix them.
Fixes: 1482ec00be4a ("drm: Add missing DP DSC extended capability definitions.")
Cc: Vinod Govindapillai
Cc: Stanislav Lisovskiy
Signed-off-by: Jani Nikula
---
include/drm/display/drm_dp.h | 4 ++--
1 file changed, 2 insertions(+), 2
The operator precedence between << and & is wrong, leading to the high
byte being completely ignored. For example, with the 6.4 format, 32
becomes 0 and 24 becomes 8. Fix it, and remove the slightly confusing
and unnecessary DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT macro while at it.
Fixes:
== Series Details ==
Series: drm/atomic-helper: Don't set deadline for modesets (rev2)
URL : https://patchwork.freedesktop.org/series/116140/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12974_full -> Patchwork_116140v2_full
From: Ankit Nautiyal
MTL requires the PORT_CTL_WIDTH, TRANS_DDI_FUNC_CTL and DDI_BUF_CTL
to be filled with 4 lanes for TMDS mode.
This patch enables D2D link and fills PORT_WIDTH in appropriate
registers.
v2:
- Added fixes from Clint's Add HDMI implementation changes.
- Modified commit
From: José Roberto de Souza
The differences between MTL and TGL DP sequences are big enough to
MTL have its own functions.
Also it is much easier to follow MTL sequences against spec with
its own functions.
One change worthy to mention is the move of
'intel_display_power_get(dev_priv,
Create a separate file to store registers for PICA chips
C10 and C20.
v2: Rename file (Jani)
v3: Use _PICK_EVEN_2RANGES() macro (Lucas)
Coding style fixed (Lucas)
v4: Redefine macros (Imre)
Reviewed-by: Vinod Govindapillai (v3)
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
PICA is used for DP alt mode and TBT modes. Hotplug interruption is routed
from PICA chip to south display engine and from there to north display
engine. This patch adds functionality to enable hotplug detection for
all Type-C ports (4 ports available).
Differently from HPD in south display, PICA
Add DP rates for Meteorlake.
Reviewed-by: Vinod Govindapillai
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_dp.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
From: Radhakrishna Sripada
XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
has a dedicated PIPE 5.2 Message bus for configuration. This message
bus is used to configure the phy internal registers.
XELPDP has C10 phys to drive output to the EDP and the native output
from
C10 phys uses direct mapping internally for voltage and pre-emphasis levels.
Program the levels directly to the fields in the VDR Registers.
Bspec: 65449
v2: From table "C10: Tx EQ settings for DP 1.4x" it shows level 1
and preemphasis 1 instead of two times of level 1 preemphasis 0.
Fix
Phy programming support for C10 phy. This is the first part of
the series that adds support for PICA phy. Later stage the support
for C20 phy is added. This series gets the eDP going.
v2: Register refinitions in intel_cx0_phy_regs.h file (Jani)
v3: Add waits for between message bus writes (Imre)
From: Clint Taylor
Initialization sequences and C10 phy are in place to be able to enable
the first 2 ports of MTL. The other ports use C20 phy that still need
to be properly added. Enable the first ports for now, keeping a TODO
comment about the others.
Cc: Radhakrishna Sripada
Reviewed-by:
On Thu, Apr 06, 2023 at 03:34:04PM +0300, Jani Nikula wrote:
> On Thu, 06 Apr 2023, Maarten Lankhorst
> wrote:
> > Hi Dave, Daniel,
> > Pull request to avoid backmerges. ;)
> > Cheers,
> > ~Maarten
>
> Not using dim for this? Is the subject line copy-pasted from another
> pull request? :)
dim
On Wed, 05 Apr 2023, "Govindapillai, Vinod"
wrote:
> On Wed, 2023-04-05 at 13:41 +0300, Jani Nikula wrote:
>> There's not much point in a static work function having a kernel-doc
>> comment. Just clean it up and make it a regular comment.
>>
>> This fixes the kernel-doc warnings:
>>
>>
Hi Yi,
On 4/1/23 17:18, Yi Liu wrote:
> This avoids passing too much parameters in multiple functions.
> Reviewed-by: Kevin Tian
> Reviewed-by: Jason Gunthorpe
> Tested-by: Terrence Xu
> Tested-by: Nicolin Chen
> Tested-by: Matthew Rosato
> Tested-by: Yanting Jiang
> Signed-off-by: Yi Liu
On Thu, Apr 06, 2023 at 11:18:06AM +0300, Joonas Lahtinen wrote:
> Hi Dave & Daniel,
>
> Here goes the final drm-intel-gt-next pull request for v6.4.
>
> As top items we have a fix for context runtime accounting, Meteorlake
> enabling, DMAR error noise elimination due to GPU error capture, BAR
>
On Thu, Apr 06, 2023 at 01:56:00PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 06, 2023 at 12:59:40PM +0300, Jani Nikula wrote:
> > On Thu, 06 Apr 2023, Stanislav Lisovskiy
> > wrote:
> > > Currently we seem to be using wrong DPCD register for reading compressed
> > > bpps,
> > > reading min/max
== Series Details ==
Series: series starting with [1/2] drm/i915/tc: demote a kernel-doc comment to
a regular comment
URL : https://patchwork.freedesktop.org/series/116144/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12974_full -> Patchwork_116144v1_full
On Thu, 06 Apr 2023, Maarten Lankhorst
wrote:
> Hi Dave, Daniel,
> Pull request to avoid backmerges. ;)
> Cheers,
> ~Maarten
Not using dim for this? Is the subject line copy-pasted from another
pull request? :)
BR,
Jani.
>
> drm-misc-next-2023-04-06:
> drm-misc-next for v6.4-rc1:
>
> UAPI
On Fri, 31 Mar 2023, "Christian König" wrote:
> We only keept that around for API compatibility with drivers. Clean all
> this up and use the per device debugfs directory.
>
> Signed-off-by: Christian König
> ---
> drivers/accel/drm_accel.c | 2 --
>
On Thu, Apr 06, 2023 at 01:56:00PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 06, 2023 at 12:59:40PM +0300, Jani Nikula wrote:
> > On Thu, 06 Apr 2023, Stanislav Lisovskiy
> > wrote:
> > > Currently we seem to be using wrong DPCD register for reading compressed
> > > bpps,
> > > reading min/max
On 4/6/2023 4:40 PM, Ville Syrjälä wrote:
On Thu, Apr 06, 2023 at 04:26:48PM +0530, Nautiyal, Ankit K wrote:
Hi Ville,
HDMI1.4b indeed says max value for 16bpc as 60160 (0xeb00)
And black level of 4096.
Got me thinking that we might need to consider bpc for getting the
Coeffs and the
Hi Dave, Daniel,
Pull request to avoid backmerges. ;)
Cheers,
~Maarten
drm-misc-next-2023-04-06:
drm-misc-next for v6.4-rc1:
UAPI Changes:
Cross-subsystem Changes:
- Document port and rotation dt bindings better.
- For panel timing DT bindings, document that vsync and hsync are
first, rather
On Thu, Apr 6, 2023 at 9:32 AM Daniel Vetter wrote:
>
> On Wed, 5 Apr 2023 at 19:46, Patrik Jakobsson
> wrote:
> >
> > On Wed, Apr 5, 2023 at 7:15 PM Daniel Vetter wrote:
> > >
> > > On Wed, 5 Apr 2023 at 18:54, Javier Martinez Canillas
> > > wrote:
> > > >
> > > > Daniel Vetter writes:
> > >
On Thu, Apr 06, 2023 at 04:26:48PM +0530, Nautiyal, Ankit K wrote:
> Hi Ville,
>
> HDMI1.4b indeed says max value for 16bpc as 60160 (0xeb00)
> And black level of 4096.
>
> Got me thinking that we might need to consider bpc for getting the
> Coeffs and the offsets.
> IIUC for CSC Full range to
On 05/04/2023 18:57, Rob Clark wrote:
On Tue, Jan 31, 2023 at 3:33 AM Tvrtko Ursulin
wrote:
From: Tvrtko Ursulin
Rudimentary vendor agnostic example of how lib_igt_drm_clients can be used
to display a sorted by card and usage list of processes using GPUs.
Borrows a bit of code from
1 - 100 of 140 matches
Mail list logo
