On Tue, Apr 11, 2023 at 05:07:01PM -0700, Manasi Navare wrote:
> On Tue, Apr 11, 2023 at 10:42 AM Ville Syrjälä
> wrote:
> >
> > On Tue, Apr 11, 2023 at 05:34:08PM +, Manasi Navare wrote:
> > > In the function intel_dp_max_bpp(), currently if bpc < 0 in case of error,
> > > we return 0
== Series Details ==
Series: drm/i915/hdcp: Fix CP current state
URL : https://patchwork.freedesktop.org/series/116359/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12993 -> Patchwork_116359v1
Summary
---
On Mon, Mar 06, 2023 at 06:51:48PM +0700, Ammar Faizi wrote:
> On Mon, Mar 06, 2023 at 12:54:59PM +0200, Jani Nikula wrote:
> > Please file a bug at fdo gitlab:
> >
> > https://gitlab.freedesktop.org/drm/intel/wikis/How-to-file-i915-bugs
>
> OK, I posted it here
In many cases there is a need to change the CP property to desired
even if not modeset has been requested yet on such situation being
lid gets closed while DP is still connected in this case HDCP
authentication needs to be reenabled.
Remove Fix me as we now send a uevent via
== Series Details ==
Series: drm/i915: CTM stuff mostly
URL : https://patchwork.freedesktop.org/series/116345/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12993 -> Patchwork_116345v1
Summary
---
**FAILURE**
== Series Details ==
Series: drm/i915: CTM stuff mostly
URL : https://patchwork.freedesktop.org/series/116345/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: CTM stuff mostly
URL : https://patchwork.freedesktop.org/series/116345/
State : warning
== Summary ==
Error: dim checkpatch failed
1df4dcef2824 drm/uapi: Document CTM matrix better
34492a0f013b drm/i915: Expose crtc CTM property on ilk/snb
b387b1e950f3
== Series Details ==
Series: PCI: Move VMD ASPM/LTR fix to PCI quirk
URL : https://patchwork.freedesktop.org/series/116343/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/116343/revisions/1/mbox/ not
applied
Applying: PCI: Move VMD ASPM/LTR fix
== Series Details ==
Series: drm/hdcp: Pull HDCP auth/exchange/check into helpers (rev9)
URL : https://patchwork.freedesktop.org/series/94712/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/94712/revisions/9/mbox/ not
applied
Applying: drm/hdcp:
== Series Details ==
Series: drm/i915: (mostly) PSR related register cleanups (rev3)
URL : https://patchwork.freedesktop.org/series/115708/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12993 -> Patchwork_115708v3
Summary
== Series Details ==
Series: drm/i915: (mostly) PSR related register cleanups (rev3)
URL : https://patchwork.freedesktop.org/series/115708/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: (mostly) PSR related register cleanups (rev3)
URL : https://patchwork.freedesktop.org/series/115708/
State : warning
== Summary ==
Error: dim checkpatch failed
bbba159d0621 drm/i915: Fix up whitespace in some display chicken registers
9133d1719ae0
Trying out for CI. Do not review.
Signed-off-by: Vinay Belgaumkar
---
tests/intel-ci/fast-feedback.testlist | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tests/intel-ci/fast-feedback.testlist
b/tests/intel-ci/fast-feedback.testlist
index d9fcb62d..653668dd 100644
---
Validate basic api for GT freq control. Also test
interaction with GT reset. We skip rps tests with
SLPC enabled, this will re-introduce some coverage.
SLPC selftests are already covering some other workload
related scenarios.
v2: Rename test (Rodrigo)
v3: Review comments (Ashutosh)
Reviewed-by:
These can be used to open per-gt debugfs files.
Reviewed-by: Ashutosh Dixit
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Vinay Belgaumkar
---
lib/igt_debugfs.c | 60 +++
lib/igt_debugfs.h | 4
2 files changed, 64 insertions(+)
diff --git
Borrow some subtests from xe_guc_pc. Also add per GT debugfs helpers.
v3: Review comments and add HAX patch
Signed-off-by: Vinay Belgaumkar
Vinay Belgaumkar (3):
lib/debugfs: Add per GT debugfs helpers
i915_pm_freq_api: Add some basic SLPC igt tests
HAX: tests/i915: Try out the SLPC IGT
== Series Details ==
Series: drm/i915/display: Return correct err code for bpc < 0
URL : https://patchwork.freedesktop.org/series/116331/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12993 -> Patchwork_116331v1
Summary
On Tue, Apr 11, 2023 at 10:42 AM Ville Syrjälä
wrote:
>
> On Tue, Apr 11, 2023 at 05:34:08PM +, Manasi Navare wrote:
> > In the function intel_dp_max_bpp(), currently if bpc < 0 in case of error,
> > we return 0 instead of returning an err code of -EINVAL.
> > This throws off the logic in the
On Tue, Apr 11, 2023 at 03:58:27PM -0600, Alex Williamson wrote:
> > Management tools already need to understand dev_set if they want to
> > offer reliable reset support to the VMs. Same as today.
>
> I don't think that's true. Our primary hot-reset use case is GPUs and
> subordinate functions,
== Series Details ==
Series: drm/i915: Initialize dkl_phy spin lock from display code path
URL : https://patchwork.freedesktop.org/series/116325/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12993 -> Patchwork_116325v1
Hi Mark,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-intel/for-linux-next-fixes]
[also build test WARNING on drm/drm-next linus/master v6.3-rc6 next-20230411]
[cannot apply to drm-tip/drm-tip drm-misc/drm-misc-next
drm-intel/for-linux-next]
[If your
== Series Details ==
Series: drm/i915/display: remove unnecessary i915_debugfs.h includes
URL : https://patchwork.freedesktop.org/series/116315/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12993 -> Patchwork_116315v1
From: Rob Clark
Signed-off-by: Rob Clark
---
drivers/gpu/drm/i915/i915_driver.c | 3 ++-
drivers/gpu/drm/i915/i915_drm_client.c | 18 +-
drivers/gpu/drm/i915/i915_drm_client.h | 2 +-
3 files changed, 8 insertions(+), 15 deletions(-)
diff --git
From: Rob Clark
Similar motivation to other similar recent attempt[1]. But with an
attempt to have some shared code for this. As well as documentation.
It is probably a bit UMA-centric, I guess devices with VRAM might want
some placement stats as well. But this seems like a reasonable start.
Quoting Mika Kahola (2023-04-03 05:50:43)
> Display14 introduces a new way to instruct the PUnit with
> power and bandwidth requirements of DE. Add the functionality
> to program the registers and handle waits using interrupts.
> The current wait time for timeouts is programmed for 10 msecs to
>
== Series Details ==
Series: drm/i915: hide mkwrite_device_info() better (rev2)
URL : https://patchwork.freedesktop.org/series/113017/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12993 -> Patchwork_113017v2
Summary
== Series Details ==
Series: drm/i915: hide mkwrite_device_info() better (rev2)
URL : https://patchwork.freedesktop.org/series/113017/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: hide mkwrite_device_info() better (rev2)
URL : https://patchwork.freedesktop.org/series/113017/
State : warning
== Summary ==
Error: dim checkpatch failed
cc64436ad4b4 drm/i915: hide mkwrite_device_info() better
-:21: WARNING:COMMIT_LOG_LONG_LINE:
From: Ville Syrjälä
In order to validate LUT programming more thoroughly let's
do a state check for all color management updates as well.
Not sure we really want this outside CI. It is rather heavy
and color management updates could become rather common
with all the HDR/etc. stuff happening.
From: Ville Syrjälä
The CHV CGM CSC coefficients are in s4.12 two's complement
format. Fix the CTM->CGM conversion to handle that correctly
instead of pretending that the hw coefficients are also
in some sign-magnitude format.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Apparently desktop gen3 parts don't support the
10bit gamma mode at all. Stop claiming otherwise.
As is the case with pipe A on gen3 mobile parts, the
PIPECONF gamma mode bit can be set but it has no
effect on the output.
PNV seems to be the only slight exception, but
From: Ville Syrjälä
VLV has a so called "wide gamut color correction" unit (WGC).
What it is is a 3x3 matrix similar to the later CHV CGM
CSC, which less precisions/range. In fact CHV also has the WGC
but using it there doesn't reall make sense when you have the
superior CGM CSC around.
Hook up
From: Ville Syrjälä
The ilk/snb code is internally fully capable of handling the
CTM property, so expose it.
Note that we still choose not to expose DEGAMMA_LUT though.
The hardware is capable if degamma or gamma, but not both
similtanously due to lack of the split gamma mode. Exposing
both
From: Ville Syrjälä
Document in which order the CTM matrix elements are stored.
Signed-off-by: Ville Syrjälä
---
include/uapi/drm/drm_mode.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 46becedf5b2f..43691058d28f
From: Ville Syrjälä
Mostly some CTM stuff:
- document the uapi better
- fix CHV CSC negative coefficients
- expose CTM on ilk/snb/vlv
- a bonus gamma patch for gen3
Test-with: 20230411161555.10001-1-ville.syrj...@linux.intel.com
Ville Syrjälä (6):
drm/uapi: Document CTM matrix better
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 009795d283d1f9f043e5a4ff97d4140cde17e2d3 Add linux-next specific
files for 20230411
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202303161521.jbgbafjj-...@intel.com
https
== Series Details ==
Series: series starting with [v2,1/2] drm: Spelling s/sempahore/semaphore/
URL : https://patchwork.freedesktop.org/series/116309/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12993 -> Patchwork_116309v1
On Tue, 11 Apr 2023 15:40:07 -0300
Jason Gunthorpe wrote:
> On Tue, Apr 11, 2023 at 11:11:17AM -0600, Alex Williamson wrote:
> > [Appears the list got dropped, replying to my previous message to re-add]
>
> Wowo this got mesed up alot, mutt drops the cc when replying for some
> reason. I
== Series Details ==
Series: series starting with [v2,1/2] drm: Spelling s/sempahore/semaphore/
URL : https://patchwork.freedesktop.org/series/116309/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
> Subject: Re: [Intel-gfx] [PATCH 1/8] drm/i915/mtl: Define MOCS and PAT tables
> for MTL
>
> On Mon, Apr 10, 2023 at 08:55:16PM -0700, Yang, Fei wrote:
> ...
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
>>
b/drivers/gpu/drm/i915/gt/intel_gtt.h
>>
index
== Series Details ==
Series: series starting with [1/2] drm: Spelling s/sempahore/semaphore/
URL : https://patchwork.freedesktop.org/series/116307/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12993 -> Patchwork_116307v1
In commit f492edb40b54 ("PCI: vmd: Add quirk to configure PCIe ASPM and
LTR") the VMD driver calls pci_enabled_link_state as a callback from
pci_bus_walk. Both will acquire the pci_bus_sem lock leading to a lockdep
warning. Instead of doing the pci_bus_walk, move the fix to quirks.c using
On Thu, Apr 06, 2023 at 04:02:20PM +0300, Mika Kahola wrote:
> From: Ankit Nautiyal
>
> MTL requires the PORT_CTL_WIDTH, TRANS_DDI_FUNC_CTL and DDI_BUF_CTL
> to be filled with 4 lanes for TMDS mode.
> This patch enables D2D link and fills PORT_WIDTH in appropriate
> registers.
>
> v2:
> -
== Series Details ==
Series: series starting with [1/2] drm: Spelling s/sempahore/semaphore/
URL : https://patchwork.freedesktop.org/series/116307/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Tue, Apr 11, 2023 at 08:07:12PM +, Jose Souza wrote:
On Tue, 2023-04-11 at 12:59 -0700, Lucas De Marchi wrote:
On Tue, Apr 11, 2023 at 10:51:04AM -0400, Rodrigo Vivi wrote:
> On Tue, Apr 11, 2023 at 12:14:36PM +0300, Jani Nikula wrote:
> > On Tue, 11 Apr 2023, Ville Syrjälä wrote:
> > >
== Series Details ==
Series: drm/i915: Query compressed bpp properly using correct DPCD and DP Spec
info (rev2)
URL : https://patchwork.freedesktop.org/series/116179/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12993 -> Patchwork_116179v2
== Series Details ==
Series: drm/i915: Query compressed bpp properly using correct DPCD and DP Spec
info (rev2)
URL : https://patchwork.freedesktop.org/series/116179/
State : warning
== Summary ==
Error: dim checkpatch failed
dc818fbee1db drm/i915: Query compressed bpp properly using correct
On Tue, 2023-04-11 at 12:59 -0700, Lucas De Marchi wrote:
> On Tue, Apr 11, 2023 at 10:51:04AM -0400, Rodrigo Vivi wrote:
> > On Tue, Apr 11, 2023 at 12:14:36PM +0300, Jani Nikula wrote:
> > > On Tue, 11 Apr 2023, Ville Syrjälä wrote:
> > > > On Tue, Apr 11, 2023 at 11:51:33AM +0300, Jani Nikula
On Tue, Apr 11, 2023 at 10:51:04AM -0400, Rodrigo Vivi wrote:
On Tue, Apr 11, 2023 at 12:14:36PM +0300, Jani Nikula wrote:
On Tue, 11 Apr 2023, Ville Syrjälä wrote:
> On Tue, Apr 11, 2023 at 11:51:33AM +0300, Jani Nikula wrote:
>> On Tue, 11 Apr 2023, Ville Syrjälä wrote:
>> > On Mon, Apr 10,
On Mon, Apr 10, 2023 at 08:55:16PM -0700, Yang, Fei wrote:
...
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
>
>>> b/drivers/gpu/drm/i915/gt/intel_gtt.h
>
>>> index 69ce55f517f5..b632167eaf2e 100644
>
>>> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
>
>>> +++
From: Sean Paul
Add HDCP 1.x support to msm DP bridges using the new HDCP
helpers.
Cc: Stephen Boyd
Reviewed-by: Stephen Boyd
Signed-off-by: Sean Paul
Signed-off-by: Mark Yacoub
---
Changes in v2:
-Squash [1] into this patch with the following changes (Stephen)
-Update the sc7180 dtsi
From: Sean Paul
Now that all of the HDCP 1.x logic has been migrated to the central HDCP
helpers, use it in the i915 driver.
The majority of the driver code for HDCP 1.x will live in intel_hdcp.c,
however there are a few helper hooks which are connector-specific and
need to be partially or
From: Sean Paul
Add the register ranges required for HDCP key injection and
HDCP TrustZone interaction as described in the dt-bindings for the
sc7180 dp controller.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Douglas Anderson
Signed-off-by: Sean Paul
Signed-off-by: Mark Yacoub
---
Changes
From: Sean Paul
Add the bindings for the MSM DisplayPort HDCP registers
which are required to write the HDCP key into the display controller as
well as the registers to enable HDCP authentication/key
exchange/encryption.
Cc: Rob Herring
Cc: Stephen Boyd
Reviewed-by: Rob Herring
Reviewed-by:
From: Sean Paul
The shim functions return error codes, but they are discarded in
intel_hdcp.c. This patch plumbs the return codes through so they are
properly handled.
Acked-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
Reviewed-by: Suraj Kandpal
Signed-off-by: Sean Paul
Signed-off-by: Mark
From: Sean Paul
Stick all of the setup for HDCP into a dedicated function. No functional
change, but this will facilitate moving HDCP logic into helpers.
Acked-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
Signed-off-by: Sean Paul
---
Changes in v2:
-None
Changes in v3:
-None
Changes in v4:
From: Sean Paul
Expand upon the HDCP helper library to manage HDCP enable, disable, and check.
Previous to this patch, the majority of the state management and sink
interaction is tucked inside the Intel driver with the understanding
that once a new platform supported HDCP we could make good
From: Sean Paul
Update the connector's property value in 2 cases which were
previously missed:
1- Content type changes. The value should revert back to DESIRED from
ENABLED in case the driver must re-authenticate the link due to the
new content type.
2- Userspace sets value to DESIRED
From: Sean Paul
Instead of forcing a modeset in the hdcp atomic check, rename to
drm_hdcp_has_changed and return true if the content protection value
is changing and let the driver decide whether a modeset is required or not.
Acked-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
Signed-off-by: Sean
From: Sean Paul
Move the hdcp atomic check from i915 to drm_hdcp so other
drivers can use it. No functional changes, just cleaned up some of the
code when moving it over.
Acked-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Sean Paul
Signed-off-by:
Hi all,
This is v7 of the HDCP patches. The patches are authored by Sean Paul.
I rebased and addressed the review comments in v6-v9.
Main change in v9 is renaming i915 priv data and moving the display type
specific init to the drm helper instead of the driver.
Patches 1-4 focus on moving the
From: Ville Syrjälä
Reduce the 'intel_dp' stuff a bit by introducing local
cpu_transcoder variables.
Ideally I'd like the whole PSR code to stop using intel_dp
except during a full modeset, but dunno yet if that's
possible. But the less 'intel_dp' we have sprad around
the easier that should be
From: Ville Syrjälä
The fact that DC states reset the PSR perofrmance counter
is no reason not to include it in the debug output.
But let's keep the comment there to remind people about
that caveat.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr.c | 10 --
1
From: Ville Syrjälä
Modernize a bunch of display chicken registers by using
REG_BIT() & co.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 114 +---
1 file changed, 59 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
From: Ville Syrjälä
We need to disable PSR when we are doing AUX by hand, otherwise
it's possible that the PSR hardware could be using the AUX CH
while we try to do our manual stuff. Add a FIXME for now.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 5 +
1
From: Ville Syrjälä
Replace some hand rolled RMW stuff with intel_de_rmw().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr.c | 32 ++--
1 file changed, 13 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
From: Ville Syrjälä
Define more of the PSR mask bits, and describe in detail
what some of them do. Even if we don't set them all from
the driver they can be very useful during PSR debugging.
Having to trawl through bspec every time to find them is
not fun, and re-reverse engineering the
From: Ville Syrjälä
Use REG_BIT() & co. to make the PSR register definitions
nicer.
v2: Rebase due to intel_psr_regs.h
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr.c | 34 ++-
drivers/gpu/drm/i915/display/intel_psr_regs.h | 197 +-
2 files
From: Ville Syrjälä
Fix a bunch of whitespace issues in some display register
definitons. Only touching the bits alerayd using REG_BIT() &
co. here. The rest will come later.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 70 -
1 file
From: Ville Syrjälä
Some cleanups around mostly PSR/related registers.
v2: Improve the mask bit docs and rebase due to
intel_psr_regs.h
Ville Syrjälä (8):
drm/i915: Fix up whitespace in some display chicken registers
drm/i915: Clean up various display chicken registers
drm/i915/psr:
On Tue, Apr 11, 2023 at 11:11:17AM -0600, Alex Williamson wrote:
> [Appears the list got dropped, replying to my previous message to re-add]
Wowo this got mesed up alot, mutt drops the cc when replying for some
reason. I think it is fixed up now
> > Our cdev model says that opening a cdev locks
On Tue, Apr 11, 2023 at 05:34:08PM +, Manasi Navare wrote:
> In the function intel_dp_max_bpp(), currently if bpc < 0 in case of error,
> we return 0 instead of returning an err code of -EINVAL.
> This throws off the logic in the calling function.
What logic? The caller doesn't expect to get
On Thu, Apr 06, 2023 at 04:02:19PM +0300, Mika Kahola wrote:
> PICA is used for DP alt mode and TBT modes. Hotplug interruption is routed
> from PICA chip to south display engine and from there to north display
> engine. This patch adds functionality to enable hotplug detection for
> all Type-C
In the function intel_dp_max_bpp(), currently if bpc < 0 in case of error,
we return 0 instead of returning an err code of -EINVAL.
This throws off the logic in the calling function. Fix this by returning
-EINVAL in case bpc < 0 which would be an error.
Cc: Ville Syrjälä
Cc: Ankit Nautiyal
Cc:
On Tue, Apr 11, 2023 at 09:41:04AM -0700, John Harrison wrote:
> On 4/11/2023 07:41, Rodrigo Vivi wrote:
> > On Mon, Apr 10, 2023 at 12:25:21PM -0700, john.c.harri...@intel.com wrote:
> > > From: John Harrison
> > >
> > > Sometimes, the only effective way to debug an issue is to dump all the
> >
On 4/11/2023 07:41, Rodrigo Vivi wrote:
On Mon, Apr 10, 2023 at 12:25:21PM -0700, john.c.harri...@intel.com wrote:
From: John Harrison
Sometimes, the only effective way to debug an issue is to dump all the
interesting information at the point of failure. So add support for
doing that.
No!
On Tue, 04 Apr 2023 10:07:37 -0700, Lucas De Marchi wrote:
> Since we are now using unversioned GuC/HuC, it's useful to be able to
> dump the firmware blob and get that information from the CSS header.
> Add a tool that decodes that information and dumps the raw header.
>
> Example output:
>
>
Hi Daniel,
On Tue, Apr 11, 2023 at 3:44 PM Daniel Vetter wrote:
> On Tue, Apr 04, 2023 at 09:39:34PM +0200, Daniel Vetter wrote:
> > This is an oversight from dc5bdb68b5b3 ("drm/fb-helper: Fix vt
> > restore") - I failed to realize that nasty userspace could set this.
> >
> > It's not pretty to
Start to move the initialization of display locks from
i915_driver_early_probe(), this way it is also executed when running
Xe kmd.
This will fix a warning in Xe kmd:
[ 201.894839] xe :00:02.0: [drm] [ENCODER:235:DDI A/PHY A] failed to
retrieve link info, disabling eDP
[ 202.136336] xe
On Tue, Apr 11, 2023 at 7:44 AM Geert Uytterhoeven
wrote:
>
> Fix a misspelling of "rendez-vouz".
>
> Signed-off-by: Geert Uytterhoeven
> ---
> include/drm/task_barrier.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/drm/task_barrier.h
On 4/11/23 06:52, Geert Uytterhoeven wrote:
Fix misspellings of "semaphore".
Signed-off-by: Geert Uytterhoeven
Series is
Reviewed-by: Hamza Mahfooz
---
drivers/gpu/drm/i915/i915_request.c | 2 +-
drivers/gpu/drm/radeon/cik.c| 2 +-
drivers/gpu/drm/radeon/r600.c | 2 +-
On Tue, 11 Apr 2023, Rodrigo Vivi wrote:
> On Mon, Apr 10, 2023 at 11:14:37AM -0700, José Roberto de Souza wrote:
>> Start to move the initialization of some lock from
>> i915_driver_early_probe().
>> No dkl function is called prior to intel_setup_outputs(), so this is
>> a good place to
On Tue, Apr 11, 2023 at 12:14:36PM +0300, Jani Nikula wrote:
> On Tue, 11 Apr 2023, Ville Syrjälä wrote:
> > On Tue, Apr 11, 2023 at 11:51:33AM +0300, Jani Nikula wrote:
> >> On Tue, 11 Apr 2023, Ville Syrjälä wrote:
> >> > On Mon, Apr 10, 2023 at 11:32:14AM -0700, José Roberto de Souza wrote:
>
On Mon, Apr 10, 2023 at 11:14:37AM -0700, José Roberto de Souza wrote:
> Start to move the initialization of some lock from
> i915_driver_early_probe().
> No dkl function is called prior to intel_setup_outputs(), so this is
> a good place to initialize it.
>
> This will also fix a warning in Xe
On Mon, Apr 10, 2023 at 12:25:21PM -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Sometimes, the only effective way to debug an issue is to dump all the
> interesting information at the point of failure. So add support for
> doing that.
No! Please no!
We have some of this on
On Tue, Apr 11, 2023 at 08:39:00AM +0200, Das, Nirmoy wrote:
>
> On 3/8/2023 10:41 AM, Andi Shyti wrote:
> > Currently, when we perform operations such as clearing or copying
> > large blocks of memory, we generate multiple requests that are
> > executed in a chain.
> >
> > However, if one of
On Thu, 2023-03-16 at 13:13 +0200, Mika Kahola wrote:
> From: Anusha Srivatsa
>
> Unlike previous platforms that used PORT_TX_DFLEXDPSP
> for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
> from which the max_lanes has to be calculated.
>
> Bspec: 50235, 65380
>
> Cc: Mika Kahola
> Cc:
On 4/11/2023 3:19 PM, Jani Nikula wrote:
Leftovers from before display debugfs was separated to its own file.
Signed-off-by: Jani Nikula
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/display/intel_dp.c | 1 -
drivers/gpu/drm/i915/display/intel_hdmi.c | 1 -
2 files changed, 2
On Tue, Apr 11, 2023 at 04:03:24PM +0200, Javier Martinez Canillas wrote:
> Daniel Vetter writes:
>
> > This is an oversight from dc5bdb68b5b3 ("drm/fb-helper: Fix vt
> > restore") - I failed to realize that nasty userspace could set this.
> >
> > It's not pretty to mix up kernel-internal and
Daniel Vetter writes:
> This is an oversight from dc5bdb68b5b3 ("drm/fb-helper: Fix vt
> restore") - I failed to realize that nasty userspace could set this.
>
> It's not pretty to mix up kernel-internal and userspace uapi flags
> like this, but since the entire fb_var_screeninfo structure is
On 2023-04-11 15:44, Daniel Vetter wrote:
On Tue, Apr 04, 2023 at 09:39:34PM +0200, Daniel Vetter wrote:
This is an oversight from dc5bdb68b5b3 ("drm/fb-helper: Fix vt
restore") - I failed to realize that nasty userspace could set this.
It's not pretty to mix up kernel-internal and userspace
On Tue, Apr 11, 2023 at 02:11:18PM +0200, Christian König wrote:
> Am 11.04.23 um 11:51 schrieb Daniel Vetter:
> > On Tue, Apr 04, 2023 at 10:06:49PM +0200, Thomas Hellström wrote:
> > > When swapping out, we will split multi-order pages both in order to
> > > move them to the swap-cache and to be
On Tue, Apr 04, 2023 at 09:39:34PM +0200, Daniel Vetter wrote:
> This is an oversight from dc5bdb68b5b3 ("drm/fb-helper: Fix vt
> restore") - I failed to realize that nasty userspace could set this.
>
> It's not pretty to mix up kernel-internal and userspace uapi flags
> like this, but since the
On Sun, Apr 09, 2023 at 07:29:51AM -0600, Alex Williamson wrote:
> > struct vfio_device_info_cap_pci_bdf {
> > struct vfio_info_cap_header header;
> > __u32 group_id;
> > __u16 segment;
> > __u8bus;
> > __u8devfn; /* Use PCI_SLOT/PCI_FUNC
On Fri, Apr 07, 2023 at 03:07:21PM -0600, Alex Williamson wrote:
> I think we need to revisit the question of why allocating an IOMMU
> group for a no-iommu device is exclusive to the vfio group support.
One of the points of this effort is to remove the co-mingling of iommu
and VFIO so much. We
On Thu, Apr 06, 2023 at 11:53:47AM -0600, Alex Williamson wrote:
> Where whether a device is opened is subject to change outside of the
> user's control. This essentially allows the user to perform hot-resets
> of devices outside of their ownership so long as the device is not
> used elsewhere,
On Tue, 2023-04-11 at 11:33 +0300, Jani Nikula wrote:
> On Tue, 11 Apr 2023, Jani Nikula wrote:
> > On Mon, 10 Apr 2023, José Roberto de Souza wrote:
> > > Start to move the initialization of some lock from
> > > i915_driver_early_probe().
> >
> > Please send this as standalone patch to i915.
Leftovers from before display debugfs was separated to its own file.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 1 -
drivers/gpu/drm/i915/display/intel_hdmi.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
Am 11.04.23 um 11:51 schrieb Daniel Vetter:
On Tue, Apr 04, 2023 at 10:06:49PM +0200, Thomas Hellström wrote:
When swapping out, we will split multi-order pages both in order to
move them to the swap-cache and to be able to return memory to the
swap cache as soon as possible on a page-by-page
The goal has been to just make device info a pointer to static const
data, i.e. the static const structs in i915_pci.c. See [1]. However,
there were issues with intel_device_info_runtime_init() clearing the
display sub-struct of device info on the !HAS_DISPLAY() path, which
consequently disables a
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