Add MTL's function for ARB session creation using PXP firmware
version 4.3 ABI structure format.
While relooking at the ARB session creation flow in intel_pxp_start,
let's address missing UAPI documentation. Without actually changing
backward compatible behavior, update i915's drm-uapi comments
Because of the additional firmware, component-driver and
initialization depedencies required on MTL platform before a
PXP context can be created, UMD calling for PXP creation as a
way to get-caps can take a long time. An actual real world
customer stack has seen this happen in the 4-to-8 second
On legacy platforms, KCR HW enabling is done at the time the mei
component interface is bound. It's also disabled during unbind.
However, for MTL onwards, we don't depend on a tee component
to start sending GSC-CS firmware messages.
Thus, immediately enable (or disable) KCR HW on PXP's init,
fini
Enable PXP with MTL-GSC-CS: add the has_pxp into device info
and increase the debugfs teardown timeouts to align with
new GSC-CS + firmware specs.
Now that we have 3 places that are selecting pxp timeouts
based on tee vs gsccs back-end, let's add a helper.
Signed-off-by: Alan Previn
Add helper functions into a new file for heci-packet-submission.
The helpers will handle generating the MTL GSC-CS Memory-Header
and submission of the Heci-Cmd-Packet instructions to the engine.
NOTE1: These common functions for heci-packet-submission will be used
by different i915 callers:
Add MTL hw-plumbing enabling for KCR operation under PXP
which includes:
1. Updating 'pick-gt' to get the media tile for
KCR interrupt handling
2. Adding MTL's KCR registers for PXP operation
(init, status-checking, etc.).
While doing #2, lets create a separate registers header file for
Add GSC engine based method for sending PXP firmware packets
to the GSC firmware for MTL (and future) products.
Use the newly added helpers to populate the GSC-CS memory
header and send the message packet to the FW by dispatching
the GSC_HECI_CMD_PKT instruction on the GSC engine.
We use
For MTL, the PXP back-end transport uses the GSC engine to submit
HECI packets through the HW to the GSC firmware for PXP arb
session management. This submission uses a non-priveleged
batch buffer, a buffer for the command packet and of course
a context targeting the GSC-CS.
Thus for MTL, we need
This series enables PXP on MTL. On ADL/TGL platforms, we rely on
the mei driver via the i915-mei PXP component interface to establish
a connection to the security firmware via the HECI device interface.
That interface is used to create and teardown the PXP ARB session.
PXP ARB session is created
On Fri, 2023-04-21 at 02:02 +, Patchwork wrote:
Patch Details
Series: drm/i915: Initialize dkl_phy spin lock from display code path (rev4)
URL:https://patchwork.freedesktop.org/series/116325/
State: failure
Details:
== Series Details ==
Series: Improvements to uc firmare management (rev2)
URL : https://patchwork.freedesktop.org/series/116517/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13036 -> Patchwork_116517v2
Summary
---
== Series Details ==
Series: Improvements to uc firmare management (rev2)
URL : https://patchwork.freedesktop.org/series/116517/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Improvements to uc firmare management (rev2)
URL : https://patchwork.freedesktop.org/series/116517/
State : warning
== Summary ==
Error: dim checkpatch failed
5f4add3122b0 drm/i915/guc: Decode another GuC load failure case
2b35e460865b drm/i915/guc: Print status
== Series Details ==
Series: drm/i915: Initialize dkl_phy spin lock from display code path (rev4)
URL : https://patchwork.freedesktop.org/series/116325/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13034_full -> Patchwork_116325v4_full
On Thu, Apr 20, 2023 at 6:11 AM Tvrtko Ursulin
wrote:
>
>
> On 19/04/2023 15:38, Rob Clark wrote:
> > On Wed, Apr 19, 2023 at 7:06 AM Tvrtko Ursulin
> > wrote:
> >>
> >>
> >> On 18/04/2023 17:08, Rob Clark wrote:
> >>> On Tue, Apr 18, 2023 at 7:58 AM Tvrtko Ursulin
> >>> wrote:
> On
On Thu, Apr 20, 2023 at 6:14 AM Tvrtko Ursulin
wrote:
>
>
> On 19/04/2023 15:32, Rob Clark wrote:
> > On Wed, Apr 19, 2023 at 6:16 AM Tvrtko Ursulin
> > wrote:
> >>
> >>
> >> On 18/04/2023 18:18, Rob Clark wrote:
> >>> On Mon, Apr 17, 2023 at 8:56 AM Tvrtko Ursulin
> >>> wrote:
>
>
From: John Harrison
The validation of the firmware table was being done inside the code
for scanning the table for the next available firmware blob. Which is
unnecessary. So pull it out into a separate function that is only
called once per blob type at init time.
Also, drop the CONFIG_SELFTEST
From: John Harrison
If the DEBUG_GEM config option is set then escalate the 'unexpected
firmware version' message from a notice to an error. This will ensure
that the CI system treats such occurences as a failure and logs a bug
about it (or fails the pre-merge testing).
Signed-off-by: John
From: John Harrison
It was noticed that duplicate entries in the firmware table could cause
an infinite loop in the firmware loading code if that entry failed to
load. Duplicate entries are a bug anyway and so should never happen.
Ensure they don't by tweaking the table validation code to reject
From: John Harrison
Explain another potential firmware failure mode and early exit the
long wait if hit.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 6 ++
2
From: John Harrison
When reduced version firmware files were added (matching major
component being the only strict requirement), the minor version was
still tracked and a notification reported if it was older. However,
the patch version should really be tracked as well for the same
reasons. The
From: John Harrison
Enhance the firmware table verification code to catch more potential
errors and to generally improve the code itself.
Track patch level version even on reduced version files to allow user
notification of missing bug fixes.
Detect another immediate failure case when loading
From: John Harrison
If the GuC load is taking an excessively long time, the wait loop
currently prints the GT frequency. Extend that to include the GuC
status as well so we can see if the GuC is actually making progress or
not.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
I think we are also bottom-ing on the opens fo this patch too:
On Thu, 2023-04-20 at 13:21 -0700, Ceraolo Spurio, Daniele wrote:
> On 4/20/2023 11:49 AM, Teres Alexis, Alan Previn wrote:
> > On Wed, 2023-03-29 at 09:56 -0700, Ceraolo Spurio, Daniele wrote:
> > > The GSC notifies us of a proxy
== Series Details ==
Series: drm/i915/guc: Disable PL1 power limit when loading GuC firmware
URL : https://patchwork.freedesktop.org/series/116768/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13034_full -> Patchwork_116768v1_full
i guess we are settled with this patch...
On Thu, 2023-04-20 at 15:04 -0700, Ceraolo Spurio, Daniele wrote:
> On 4/18/2023 11:57 PM, Teres Alexis, Alan Previn wrote:
> > On Wed, 2023-03-29 at 09:56 -0700, Ceraolo Spurio, Daniele wrote:
> > > From: Alexander Usyskin
> > >
> > > Add GSC proxy
On Thu, Apr 20, 2023 at 04:51:23PM +0530, Tejas Upadhyay wrote:
> WA 18018781329 is applicable now across all MTL
> steppings.
>
> Cc: Matt Roper
> Signed-off-by: Tejas Upadhyay
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 +---
> 1 file changed, 13 insertions(+), 7
On 4/20/2023 3:04 PM, Ceraolo Spurio, Daniele wrote:
On 4/18/2023 11:57 PM, Teres Alexis, Alan Previn wrote:
On Wed, 2023-03-29 at 09:56 -0700, Ceraolo Spurio, Daniele wrote:
From: Alexander Usyskin
Add GSC proxy driver. It to allows messaging between GSC component
on Intel on board
On 4/17/2023 10:56 AM, Teres Alexis, Alan Previn wrote:
On Mon, 2023-04-10 at 09:10 -0700, Ceraolo Spurio, Daniele wrote:
alan:snip
+int
+intel_gsc_uc_heci_cmd_submit_nonpriv(struct intel_gsc_uc *gsc,
+struct intel_context *ce,
+
On Thu, Apr 20, 2023 at 01:05:27PM -0700, Umesh Nerlige Ramappa wrote:
> On Thu, Mar 16, 2023 at 01:25:48PM -0700, Radhakrishna Sripada wrote:
> > From: Vinay Belgaumkar
> >
> > If BIOS enables/disables C6, i915 should do the same. Also, retain
> > this value across driver reloads. This is
== Series Details ==
Series: series starting with [1/2] drm/i915/mtl: Add the missing CPU transcoder
mask in intel_device_info
URL : https://patchwork.freedesktop.org/series/116781/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13035 -> Patchwork_116781v1
== Series Details ==
Series: series starting with [1/2] drm/i915/mtl: Add the missing CPU transcoder
mask in intel_device_info
URL : https://patchwork.freedesktop.org/series/116781/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit
== Series Details ==
Series: series starting with [1/2] drm/i915/mtl: Add the missing CPU transcoder
mask in intel_device_info
URL : https://patchwork.freedesktop.org/series/116781/
State : warning
== Summary ==
Error: dim checkpatch failed
0e167372bec6 drm/i915/mtl: Add the missing CPU
== Series Details ==
Series: drm/i915/mtl: Define MOCS and PAT tables for MTL (rev9)
URL : https://patchwork.freedesktop.org/series/115980/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13035 -> Patchwork_115980v9
Summary
== Series Details ==
Series: drm/i915/mtl: Define MOCS and PAT tables for MTL (rev9)
URL : https://patchwork.freedesktop.org/series/115980/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
From: Stanislav Lisovskiy
We try to verify pll registers in sw state for slave crtc with the hw state.
However in case of bigjoiner we don't calculate those at all, so this
verification
will then always fail.
So we should either skip the verification for Bigjoiner slave crtc or copy sw
state
CPU transcoder mask is used to iterate over the available
CPU transcoders in the macro for_each_cpu_transcoder().
The macro is broken on MTL and got highlighted when audio
state was being tracked for each transcoder added in [1].
Add the missing CPU transcoder mask which is similar to ADL-P
mask
== Series Details ==
Series: drm/i915/mtl: workaround coherency issue for Media (rev2)
URL : https://patchwork.freedesktop.org/series/116751/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13035 -> Patchwork_116751v2
On 4/18/2023 11:57 PM, Teres Alexis, Alan Previn wrote:
On Wed, 2023-03-29 at 09:56 -0700, Ceraolo Spurio, Daniele wrote:
From: Alexander Usyskin
Add GSC proxy driver. It to allows messaging between GSC component
on Intel on board graphics card and CSE device.
alan:nit: isn't "Intel
On Thu, Apr 20, 2023 at 02:23:22PM -0700, Matt Roper wrote:
> On Thu, Apr 20, 2023 at 11:13:52PM +0200, Andi Shyti wrote:
> > From: Madhumitha Tolakanahalli Pradeep
> >
> >
> > On MTL, GT can no longer allocate on LLC - only the CPU can.
> > This, along with addition of support for L4 cache
== Series Details ==
Series: drm/i915/mtl: Add support for C20 phy
URL : https://patchwork.freedesktop.org/series/116755/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13034_full -> Patchwork_116755v1_full
Summary
---
On Thu, Apr 20, 2023 at 01:38:59PM +0200, Nirmoy Das wrote:
> From: Fei Yang
>
> This patch implements Wa_22016122933.
>
> In MTL, memory writes initiated by Media tile update the whole
> cache line even for partial writes. This creates a coherency
> problem for cacheable memory if both CPU and
On Thu, Apr 20, 2023 at 11:13:52PM +0200, Andi Shyti wrote:
> From: Madhumitha Tolakanahalli Pradeep
>
>
> On MTL, GT can no longer allocate on LLC - only the CPU can.
> This, along with addition of support for L4 cache calls for
> a MOCS/PAT table update.
> Also the PAT index registers are
From: Madhumitha Tolakanahalli Pradeep
On MTL, GT can no longer allocate on LLC - only the CPU can.
This, along with addition of support for L4 cache calls for
a MOCS/PAT table update.
Also the PAT index registers are multicasted for primary GT,
and there is an address jump from index 7 to 8.
On Wed, Apr 19, 2023 at 04:00:56PM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> This patch is a preparation for replacing enum i915_cache_level with PAT
> index. Caching policy for buffer objects is set through the PAT index in
> PTE, the old i915_cache_level is not sufficient to
On Wed, Apr 19, 2023 at 04:00:55PM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> The design is to keep Buffer Object's caching policy immutable through
> out its life cycle. This patch ends the support for set caching ioctl
> from MTL onward. While doing that we also set BO's to be 1-way
On Wed, Apr 19, 2023 at 04:00:54PM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> This patch implements Wa_22016122933.
>
> In MTL, memory writes initiated by Media tile update the whole
> cache line even for partial writes. This creates a coherency
> problem for cacheable memory if both
== Series Details ==
Series: drm/i915/mtl: workaround coherency issue for Media
URL : https://patchwork.freedesktop.org/series/116751/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13034_full -> Patchwork_116751v1_full
On Wed, Apr 19, 2023 at 04:00:53PM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> PTE encode functions are platform dependent. This patch implements
> PTE functions for MTL, and ensures the correct PTE encode function
> is used by calling pte_encode function pointer instead of the
>
On Wed, Apr 19, 2023 at 04:00:52PM -0700, fei.y...@intel.com wrote:
> From: Madhumitha Tolakanahalli Pradeep
>
>
> On MTL, GT can no longer allocate on LLC - only the CPU can.
> This, along with addition of support for L4 cache calls for
> a MOCS/PAT table update.
> Also the PAT index registers
On 4/20/2023 11:49 AM, Teres Alexis, Alan Previn wrote:
On Wed, 2023-03-29 at 09:56 -0700, Ceraolo Spurio, Daniele wrote:
The GSC notifies us of a proxy request via the HECI2 interrupt. The
alan:snip
@@ -256,6 +262,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
u32 irqs =
On Fri, Mar 31, 2023 at 02:02:40PM +0100, Tvrtko Ursulin wrote:
On 30/03/2023 19:31, Umesh Nerlige Ramappa wrote:
+ Joonas for comments on this
On Thu, Mar 30, 2023 at 02:38:03PM +0100, Tvrtko Ursulin wrote:
On 30/03/2023 01:41, Umesh Nerlige Ramappa wrote:
MTL introduces separate GTs for
On Thu, Mar 16, 2023 at 01:25:48PM -0700, Radhakrishna Sripada wrote:
From: Vinay Belgaumkar
If BIOS enables/disables C6, i915 should do the same. Also, retain
this value across driver reloads. This is needed only for MTL as
of now due to an existing bug in OA which needs C6 disabled for
it to
On Wed, 2023-03-29 at 09:56 -0700, Ceraolo Spurio, Daniele wrote:
> The GSC notifies us of a proxy request via the HECI2 interrupt. The
alan:snip
> @@ -256,6 +262,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
> u32 irqs = GT_RENDER_USER_INTERRUPT;
> u32 guc_mask =
== Series Details ==
Series: drm/i915: Initialize dkl_phy spin lock from display code path (rev4)
URL : https://patchwork.freedesktop.org/series/116325/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13034 -> Patchwork_116325v4
On Thu, 2023-04-20 at 09:35 -0700, Lucas De Marchi wrote:
> On Thu, Apr 20, 2023 at 08:36:37AM -0700, Jose Souza wrote:
> > On Thu, 2023-04-20 at 11:27 -0400, Rodrigo Vivi wrote:
> > > On Thu, Apr 20, 2023 at 09:19:09AM -0400, Souza, Jose wrote:
> > > > On Wed, 2023-04-19 at 00:29 -0700, Lucas De
== Series Details ==
Series: drm/i915/guc: Disable PL1 power limit when loading GuC firmware
URL : https://patchwork.freedesktop.org/series/116768/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13034 -> Patchwork_116768v1
drm/i915: Initialize dkl_phy spin lock from display code path
Start moving the initialization of display locks from
i915_driver_early_probe().
Display locks should be initialized from display-only code paths.
It was also agreed that if a variable is only used in one file, it
should be
== Series Details ==
Series: drm/i915/guc: Disable PL1 power limit when loading GuC firmware
URL : https://patchwork.freedesktop.org/series/116768/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Thu, Apr 20, 2023 at 08:36:37AM -0700, Jose Souza wrote:
On Thu, 2023-04-20 at 11:27 -0400, Rodrigo Vivi wrote:
On Thu, Apr 20, 2023 at 09:19:09AM -0400, Souza, Jose wrote:
> On Wed, 2023-04-19 at 00:29 -0700, Lucas De Marchi wrote:
> > On Wed, Apr 19, 2023 at 10:16:22AM +0300, Jani Nikula
Hi Fei,
> >>> To comply with the design that buffer objects shall have immutable
> >>> cache setting through out their life cycle, {set, get}_caching ioctl's
> >>> are no longer supported from MTL onward. With that change caching
> >>> policy can only be set at object creation time. The current
On Thu, 20 Apr 2023 08:43:52 -0700, Rodrigo Vivi wrote:
>
Hi Rodrigo,
> On Thu, Apr 20, 2023 at 08:57:24AM +0100, Tvrtko Ursulin wrote:
> >
> > On 19/04/2023 23:10, Dixit, Ashutosh wrote:
> > > On Wed, 19 Apr 2023 06:21:27 -0700, Tvrtko Ursulin wrote:
> > > >
> > >
> > > Hi Tvrtko,
> > >
> > > >
On dGfx, the PL1 power limit being enabled and set to a low value results
in a low GPU operating freq. It also negates the freq raise operation which
is done before GuC firmware load. As a result GuC firmware load can time
out. Such timeouts were seen in the GL #8062 bug below (where the PL1 power
Instead of erroring out when GuC reset is in progress, block waiting for
GuC reset to complete which is a more reasonable uapi behavior.
v2: Avoid race between wake_up_all and waiting for wakeup (Rodrigo)
v3: Remove timeout when blocked (Tvrtko)
Signed-off-by: Ashutosh Dixit
Reviewed-by:
v6: Update Patch 3 to remove the timeout when blocked
v1-v5: Please see individual patches for revision history
Ashutosh Dixit (3):
drm/i915/hwmon: Get mutex and rpm ref just once in hwm_power_max_write
drm/i915/guc: Disable PL1 power limit when loading GuC firmware
drm/i915/hwmon: Block
In preparation for follow-on patches, refactor hwm_power_max_write to take
hwmon_lock and runtime pm wakeref at start of the function and release them
at the end, therefore acquiring these just once each.
Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
---
> On 20/04/2023 12:39, Andi Shyti wrote:
>> Hi Fei,
>>
>>> To comply with the design that buffer objects shall have immutable
>>> cache setting through out their life cycle, {set, get}_caching ioctl's
>>> are no longer supported from MTL onward. With that change caching
>>> policy can only be set
== Series Details ==
Series: drm/i915/mtl: Add support for C20 phy
URL : https://patchwork.freedesktop.org/series/116755/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13034 -> Patchwork_116755v1
Summary
---
On Wed, Apr 19, 2023 at 03:13:08PM -0700, Dixit, Ashutosh wrote:
> On Wed, 19 Apr 2023 12:40:44 -0700, Rodrigo Vivi wrote:
> >
>
> Hi Rodrigo,
>
> > On Tue, Apr 18, 2023 at 10:23:50AM -0700, Dixit, Ashutosh wrote:
> > > On Mon, 17 Apr 2023 22:35:58 -0700, Rodrigo Vivi wrote:
> > > >
> > >
> > >
On Thu, Apr 20, 2023 at 08:57:24AM +0100, Tvrtko Ursulin wrote:
>
> On 19/04/2023 23:10, Dixit, Ashutosh wrote:
> > On Wed, 19 Apr 2023 06:21:27 -0700, Tvrtko Ursulin wrote:
> > >
> >
> > Hi Tvrtko,
> >
> > > On 10/04/2023 23:35, Ashutosh Dixit wrote:
> > > > Instead of erroring out when GuC
On Thu, 2023-04-20 at 11:27 -0400, Rodrigo Vivi wrote:
> On Thu, Apr 20, 2023 at 09:19:09AM -0400, Souza, Jose wrote:
> > On Wed, 2023-04-19 at 00:29 -0700, Lucas De Marchi wrote:
> > > On Wed, Apr 19, 2023 at 10:16:22AM +0300, Jani Nikula wrote:
> > > > On Tue, 18 Apr 2023, Lucas De Marchi
== Series Details ==
Series: drm/i915/mtl: Add support for C20 phy
URL : https://patchwork.freedesktop.org/series/116755/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/mtl: Add support for C20 phy
URL : https://patchwork.freedesktop.org/series/116755/
State : warning
== Summary ==
Error: dim checkpatch failed
46e88ddde94d drm/i915/mtl: C20 PLL programming
-:155: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
On Thu, Apr 20, 2023 at 09:19:09AM -0400, Souza, Jose wrote:
> On Wed, 2023-04-19 at 00:29 -0700, Lucas De Marchi wrote:
> > On Wed, Apr 19, 2023 at 10:16:22AM +0300, Jani Nikula wrote:
> > > On Tue, 18 Apr 2023, Lucas De Marchi wrote:
> > > > On Tue, Apr 18, 2023 at 11:30:18PM -0700, Lucas De
On Fri, 2023-03-17 at 17:58 -0700, Radhakrishna Sripada wrote:
> Communicating QGV points restriction to PUnit happens via PM Demand
> instead of the Pcode mailbox in the previous platforms. GV point
> restriction is handled by the PM demand code.
>
> Signed-off-by: Radhakrishna Sripada
> ---
== Series Details ==
Series: drm/i915/mtl: Add workaround 14018778641
URL : https://patchwork.freedesktop.org/series/116750/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13033_full -> Patchwork_116750v1_full
Summary
== Series Details ==
Series: drm/i915/mtl: workaround coherency issue for Media
URL : https://patchwork.freedesktop.org/series/116751/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13034 -> Patchwork_116751v1
Summary
== Series Details ==
Series: drm/i915/mtl: Set has_llc=0
URL : https://patchwork.freedesktop.org/series/116747/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13033_full -> Patchwork_116747v1_full
Summary
---
On Thu, 20 Apr 2023 12:10:20 +
"Liu, Yi L" wrote:
> > From: Alex Williamson
> > Sent: Wednesday, April 19, 2023 2:39 AM
> >
> > On Tue, 18 Apr 2023 09:57:32 -0300
> > Jason Gunthorpe wrote:
> >
> > > On Mon, Apr 17, 2023 at 02:06:42PM -0600, Alex Williamson wrote:
> > > > On Mon, 17
On Wed, 2023-04-19 at 00:29 -0700, Lucas De Marchi wrote:
> On Wed, Apr 19, 2023 at 10:16:22AM +0300, Jani Nikula wrote:
> > On Tue, 18 Apr 2023, Lucas De Marchi wrote:
> > > On Tue, Apr 18, 2023 at 11:30:18PM -0700, Lucas De Marchi wrote:
> > > > On Tue, Apr 18, 2023 at 09:43:37AM -0700, Jose
On 19/04/2023 15:32, Rob Clark wrote:
On Wed, Apr 19, 2023 at 6:16 AM Tvrtko Ursulin
wrote:
On 18/04/2023 18:18, Rob Clark wrote:
On Mon, Apr 17, 2023 at 8:56 AM Tvrtko Ursulin
wrote:
From: Tvrtko Ursulin
For drivers who only wish to show one memory region called 'system,
and only
On 19/04/2023 15:38, Rob Clark wrote:
On Wed, Apr 19, 2023 at 7:06 AM Tvrtko Ursulin
wrote:
On 18/04/2023 17:08, Rob Clark wrote:
On Tue, Apr 18, 2023 at 7:58 AM Tvrtko Ursulin
wrote:
On 18/04/2023 15:39, Rob Clark wrote:
On Mon, Apr 17, 2023 at 8:56 AM Tvrtko Ursulin
wrote:
From:
On 20/04/2023 12:39, Andi Shyti wrote:
Hi Fei,
To comply with the design that buffer objects shall have immutable
cache setting through out their life cycle, {set, get}_caching ioctl's
are no longer supported from MTL onward. With that change caching
policy can only be set at object creation
LGTM.
Reviewed-by: Ankit Nautiyal
On 4/6/2023 7:16 PM, Jani Nikula wrote:
The macro values just don't match the specs. Fix them.
Fixes: 1482ec00be4a ("drm: Add missing DP DSC extended capability definitions.")
Cc: Vinod Govindapillai
Cc: Stanislav Lisovskiy
Signed-off-by: Jani Nikula
---
Finally, we can enable TC ports for Meteorlake.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index
From: Anusha Srivatsa
Unlike previous platforms that used PORT_TX_DFLEXDPSP
for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
from which the max_lanes has to be calculated.
Bspec: 50235, 65380
Signed-off-by: Anusha Srivatsa
Signed-off-by: Jose Roberto de Souza
Signed-off-by: Mika
Add register writes to enable powering up Type-C subsystem i.e. TCSS.
For MeteorLake we need to request TCSS to power up and check the TCSS
power state after 500 us.
In addition, for PICA we need to set/clear the Type-C PHY ownnership
bit when Type-C device is connected/disconnected.
DP1.4 and DP20 voltage swing sequence for C20 phy.
Bspec: 65449, 67636, 67610
Signed-off-by: Mika Kahola
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++
.../drm/i915/display/intel_ddi_buf_trans.c| 53
Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
Enabling and disabling sequence for Thunderbolt PLL.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 135 ++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 7 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
3 files changed, 138
From: Gustavo Sousa
Xe_LPD+ defines interrupt bits for only DDI ports in the DE Port
Interrupt registers. The bits for Type-C ports are defined in the PICA
interrupt registers.
BSpec: 50064
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/i915_irq.c | 5 -
1 file changed, 4
From: Imre Deak
The HPD live status for MTL has to be read from different set of
registers. MTL deserves a new function for this purpose
and cannot reuse the existing HPD live status detection
Signed-off-by: Anusha Srivatsa
Signed-off-by: Imre Deak
Signed-off-by: Mika Kahola
---
As we already do with C10 chip, let's dump the pll
hw state for C20 as well.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
3 files
Readout hw state for Thunderbolt.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++-
3 files changed, 32 insertions(+), 2
Calculate port clock with C20 phy.
BSpec: 64568
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 45 +++
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++
Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
The PLL settings are based on table, not for algorithmic alternative.
For DP 1.4 only MPLLB is in use.
Once register settings are done, we read back C20 HW state.
BSpec: 64568
Signed-off-by: Mika Kahola
Signed-off-by: Arun R Murthy
C20 phy PLL programming sequence for DP, DP2.0, HDMI2.x non-FRL and
HDMI2.x FRL. This enables C20 MPLLA and MPLLB programming sequence. add
4 lane support for c20.
Signed-off-by: José Roberto de Souza
Signed-off-by: Mika Kahola
Signed-off-by: Bhanuprakash Modem
Signed-off-by: Imre Deak
Add support for C20 phy for Type-C connections. C20 phy differs from
C10 and hence we need to separately handle this case.
Signed-off-by: Mika Kahola
Anusha Srivatsa (1):
drm/i915/mtl: Pin assignment for TypeC
Gustavo Sousa (1):
drm/i915/mtl: Define mask for DDI AUX interrupts
Imre Deak
On 20/04/2023 11:13, Andrzej Hajda wrote:
On 20.04.2023 01:00, fei.y...@intel.com wrote:
From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy
for
buffer objects. This is flaky because the PAT index which really controls
the caching behavior in PTE has far
LGTM.
Reviewed-by: Ankit Nautiyal
On 4/6/2023 7:16 PM, Jani Nikula wrote:
The operator precedence between << and & is wrong, leading to the high
byte being completely ignored. For example, with the 6.4 format, 32
becomes 0 and 24 becomes 8. Fix it, and remove the slightly confusing
and
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