== Series Details ==
Series: drm/i915: use pat_index instead of cache_level
URL : https://patchwork.freedesktop.org/series/117480/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13124_full -> Patchwork_117480v1_full
Summary
== Series Details ==
Series: Fixed-width mask/bit helpers
URL : https://patchwork.freedesktop.org/series/117490/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Fixed-width mask/bit helpers
URL : https://patchwork.freedesktop.org/series/117490/
State : warning
== Summary ==
Error: dim checkpatch failed
ebd974edde6a drm/amd: Remove wrapper macros over get_u{32, 16, 8}
-:69: ERROR:CODE_INDENT: code indent should use tabs
Convert the REG_* macros from i915_reg_defs.h to use the new macros
defined in linux/bits.h. This is just to help on the implementation
of the new macros and not intended to be applied.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg_defs.h | 28 +---
1
Both amdgpu and radeon use some wrapper macros over get_u{32,16,8}()
functions which end up adding an implicit argument. Instead of using
the macros, just call the functions directly without hiding the context
that is being passed. This will allow the macros to be used in a more
global context
Generalize the REG_GENMASK*() and REG_BIT*() macros so they can be used
by other drivers. The intention is to migrate i915 to the generic
helpers and also make use of them on the upcoming xe driver. There are
possibly other users in the kernel that need u32/u16/u8 bit handling.
First patch is one
Add GENMASK_U32(), GENMASK_U16() and GENMASK_U8() macros to create
masks for fixed-width types and also the corresponding BIT_U32(),
BIT_U16() and BIT_U8().
All of those depend on a new "U" suffix added to the integer constant.
Due to naming clashes it's better to call the macro U32. Since C
== Series Details ==
Series: drm/i915: use pat_index instead of cache_level
URL : https://patchwork.freedesktop.org/series/117478/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13123_full -> Patchwork_117478v1_full
Summary
== Series Details ==
Series: drm/i915: Allow user to set cache at BO creation (rev6)
URL : https://patchwork.freedesktop.org/series/116870/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13124 -> Patchwork_116870v6
Summary
== Series Details ==
Series: drm/i915: Allow user to set cache at BO creation (rev6)
URL : https://patchwork.freedesktop.org/series/116870/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: use pat_index instead of cache_level
URL : https://patchwork.freedesktop.org/series/117480/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13124 -> Patchwork_117480v1
Summary
---
== Series Details ==
Series: drm/i915: use pat_index instead of cache_level
URL : https://patchwork.freedesktop.org/series/117480/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
> On Sun, May 07, 2023 at 11:39:18PM -0700, Yang, Fei wrote:
>>> On Wed, May 03, 2023 at 03:50:59PM -0700, fei.y...@intel.com wrote:
From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy for
buffer objects. This is flaky because the PAT index
From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy for
buffer objects. This is flaky because the PAT index which really controls
the caching behavior in PTE has far more levels than what's defined in the
enum. In addition, the PAT index is platform dependent,
From: Fei Yang
To comply with the design that buffer objects shall have immutable
cache setting through out their life cycle, {set, get}_caching ioctl's
are no longer supported from MTL onward. With that change caching
policy can only be set at object creation time. The current code
applies a
From: Fei Yang
The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
From: Fei Yang
This patch is a preparation for replacing enum i915_cache_level with PAT
index. Caching policy for buffer objects is set through the PAT index in
PTE, the old i915_cache_level is not sufficient to represent all caching
modes supported by the hardware.
Preparing the transition by
From: Fei Yang
The first three patches in this series are taken from
https://patchwork.freedesktop.org/series/116868/
These patches are included here because the last patch
has dependency on the pat_index refactor.
This series is focusing on uAPI changes,
1. end support for set caching ioctl
From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy for
buffer objects. This is flaky because the PAT index which really controls
the caching behavior in PTE has far more levels than what's defined in the
enum. In addition, the PAT index is platform dependent,
From: Fei Yang
This patch is a preparation for replacing enum i915_cache_level with PAT
index. Caching policy for buffer objects is set through the PAT index in
PTE, the old i915_cache_level is not sufficient to represent all caching
modes supported by the hardware.
Preparing the transition by
From: Fei Yang
This patch set was posted at
https://patchwork.freedesktop.org/series/116868/
Change title since the PTE patch was merged separately.
These patches are extracted from series
https://patchwork.freedesktop.org/series/115980/
This series refactor the cache policy programming so
== Series Details ==
Series: drm/i915: use pat_index instead of cache_level
URL : https://patchwork.freedesktop.org/series/117478/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13123 -> Patchwork_117478v1
Summary
---
== Series Details ==
Series: drm/i915: use pat_index instead of cache_level
URL : https://patchwork.freedesktop.org/series/117478/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: use pat_index instead of cache_level
URL : https://patchwork.freedesktop.org/series/117478/
State : warning
== Summary ==
Error: dim checkpatch failed
cc05bc57e9a5 drm/i915: preparation for using PAT index
db9174616b6f drm/i915: use pat_index instead of
From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy for
buffer objects. This is flaky because the PAT index which really controls
the caching behavior in PTE has far more levels than what's defined in the
enum. In addition, the PAT index is platform dependent,
From: Fei Yang
This patch set was posted at
https://patchwork.freedesktop.org/series/116868/
Change title since the PTE patch was merged separately.
These patches are extracted from series
https://patchwork.freedesktop.org/series/115980/
This series refactor the cache policy programming so
From: Fei Yang
This patch is a preparation for replacing enum i915_cache_level with PAT
index. Caching policy for buffer objects is set through the PAT index in
PTE, the old i915_cache_level is not sufficient to represent all caching
modes supported by the hardware.
Preparing the transition by
On Mon, 8 May 2023 15:32:44 +
"Liu, Yi L" wrote:
> > From: Alex Williamson
> > Sent: Friday, April 28, 2023 4:16 AM
> >
> > > > + *
> > > > * Return: 0 on success, -errno on failure:
> > > > * -enospc = insufficient buffer, -enodev = unsupported for device.
> > > > */
> > > >
== Series Details ==
Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev14)
URL : https://patchwork.freedesktop.org/series/107550/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13120_full -> Patchwork_107550v14_full
On 5/4/2023 8:35 AM, Dmitry Baryshkov wrote:
DSC model contains pre-SCR RC parameters for other bpp/bpc combinations,
include them here for completeness. The values were generated from the
'pre_scr_cfg_files_for_reference' files found in DSC models 20210623.
The same fileset is a part of DSC
== Series Details ==
Series: drm/i915: Fix wrong condition in bxt_set_cdclk for DG2 (rev2)
URL : https://patchwork.freedesktop.org/series/117420/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13120_full -> Patchwork_117420v2_full
On Fri, May 05, 2023 at 05:58:16PM -0700, Umesh Nerlige Ramappa wrote:
From: Tvrtko Ursulin
Start exporting frequency and RC6 counters from all tiles.
Existing counters keep their names and config values and new one use the
namespace added in the previous patch, with the "-gtN" added to their
On Fri, May 05, 2023 at 05:58:15PM -0700, Umesh Nerlige Ramappa wrote:
From: Tvrtko Ursulin
Reserve some bits in the counter config namespace which will carry the
tile id and prepare the code to handle this.
No per tile counters have been added yet.
v2:
- Fix checkpatch issues
- Use 4 bits
On Fri, May 05, 2023 at 05:58:14PM -0700, Umesh Nerlige Ramappa wrote:
From: Tvrtko Ursulin
We do not want to have timers per tile and waste CPU cycles and energy via
multiple wake-up sources, for a relatively un-important task of PMU
sampling, so keeping a single timer works well. But we also
On Fri, May 05, 2023 at 05:58:13PM -0700, Umesh Nerlige Ramappa wrote:
From: Tvrtko Ursulin
Trivial prep work for full multi-tile enablement later.
Some more description on what this does OR how park/unpark affects pmu
counters would help.
Thanks,
Umesh
Signed-off-by: Tvrtko Ursulin
On Fri, May 05, 2023 at 05:58:12PM -0700, Umesh Nerlige Ramappa wrote:
From: Tvrtko Ursulin
As we have more and more engines do not waste time sampling the ones no-
one is monitoring.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 3
On Fri, May 05, 2023 at 05:58:11PM -0700, Umesh Nerlige Ramappa wrote:
From: Tvrtko Ursulin
Given how the metrics are already exported, we also need to run sampling
over engines from all GTs.
Problem of GT frequencies is left for later.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Umesh
On Fri, 2023-05-05 at 00:39 -0700, Justen, Jordan L wrote:
> On 2023-05-04 22:30:07, Teres Alexis, Alan Previn wrote:
> > On Thu, 2023-04-27 at 16:48 -0700, Teres Alexis, Alan Previn wrote:
> > > Because of the additional firmware, component-driver and
> > > initialization depedencies required on
On Sun, May 07, 2023 at 11:39:18PM -0700, Yang, Fei wrote:
>> On Wed, May 03, 2023 at 03:50:59PM -0700, fei.y...@intel.com wrote:
>>> From: Fei Yang
>>>
>>> Currently the KMD is using enum i915_cache_level to set caching policy
>for
>>> buffer objects. This is flaky
On 05.05.2023 22:06, Rodrigo Vivi wrote:
On Thu, May 04, 2023 at 06:27:53PM +0200, Andrzej Hajda wrote:
Hi maintainers of net and i915,
On 25.04.2023 00:05, Andrzej Hajda wrote:
This is revived patchset improving ref_tracker library and converting
i915 internal tracker to ref_tracker.
The old
Thank you all for the reviews. Pushed the changes.
-Radhakrishna(RK) Sripada
> -Original Message-
> From: Upadhyay, Tejas
> Sent: Monday, May 8, 2023 5:22 AM
> To: Sripada, Radhakrishna ; intel-
> g...@lists.freedesktop.org
> Cc: Roper, Matthew D
> Subject: RE: [Intel-gfx] [PATCH]
== Series Details ==
Series: drm/i915: Fix memory leaks in function live_nop_switch (rev2)
URL : https://patchwork.freedesktop.org/series/117458/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/117458/revisions/2/mbox/ not
applied
Applying:
On Mon, May 08, 2023 at 04:50:15PM +0800, Cong Liu wrote:
> Be sure to properly free the allocated memory before exiting
> the live_nop_switch function.
>
> Signed-off-by: Cong Liu
> ---
> drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 4 +++-
> 1 file changed, 3 insertions(+), 1
> From: Liu, Yi L
> Sent: Wednesday, May 3, 2023 5:49 PM
>
> > From: Jason Gunthorpe
> > Sent: Wednesday, May 3, 2023 2:12 AM
> >
> > On Sat, Apr 29, 2023 at 12:07:24AM +0800, Yi Liu wrote:
> > > > The emulated stuff is for mdev only, it should not be confused with
> > > > no-iommu
> > >
> > >
> From: Alex Williamson
> Sent: Friday, April 28, 2023 4:16 AM
>
> > > + *
> > > * Return: 0 on success, -errno on failure:
> > > * -enospc = insufficient buffer, -enodev = unsupported for device.
> > > */
> > > struct vfio_pci_dependent_device {
> > > - __u32 group_id;
> > > +
== Series Details ==
Series: drm/i915: Fix memory leaks in function live_nop_switch
URL : https://patchwork.freedesktop.org/series/117458/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13121 -> Patchwork_117458v1
Summary
On Sat, May 06, 2023, Yan Zhao wrote:
> On Sat, May 06, 2023 at 02:35:41PM +0800, Yan Zhao wrote:
> > > > Maybe the checking of PageTransHuge(cur_page) and bailing out is not
> > > > necessary.
> > > > If a page is not transparent huge, but there are 512 contigous 4K
> > > > pages, I think it's
Quoting Ankit Nautiyal (2023-05-05 08:09:17)
>For ADL-P the timeout for DDI_BUF_CTL active is 500usec.
>Update the same as per Bspec:55424.
I think the Bspec number could go as a trailer. We could also add BSpec 49191
here.
Acked-by: Gustavo Sousa
>
>Fixes: 5add4575c298 ("drm/i915/ddi: Align
== Series Details ==
Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev14)
URL : https://patchwork.freedesktop.org/series/107550/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13120 -> Patchwork_107550v14
Quoting Clint Taylor (2023-05-05 15:46:40)
>Use algorithm to generate HDMI C20 PLL clock frequencies.
>
>BSPEC: 64568
>Cc: Radhakrishna Sripada
>Cc: Mika Kahola
>Cc: Anusha Srivatsa
>Cc: Gustavo Sousa
>Signed-off-by: Clint Taylor
Reviewed-by: Gustavo Sousa
>---
>
== Series Details ==
Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev14)
URL : https://patchwork.freedesktop.org/series/107550/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Quoting Clint Taylor (2023-05-05 15:46:39)
>Add the support macros to define/extract bits as 16bits.
>
>Signed-off-by: Clint Taylor
>---
> drivers/gpu/drm/i915/i915_reg_defs.h | 49
> 1 file changed, 49 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
Be sure to properly free the allocated memory before exiting
the live_nop_switch function.
Signed-off-by: Cong Liu
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
Add a wrapper function to check dp_downstream clock/bandwidth
constraints. Based on whether the sink supports FRL/TMDS the wrapper
calls the appropriate FRL/TMDS functions.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 43 +++--
1 file changed,
During FRL bandwidth check for downstream HDMI2.1 sink,
the min BPC supported is incorrectly taken for DP, and the check does
not consider ybcr420 only modes.
This patch fixes the bandwidth calculation similar to the TMDS case, by
taking min 8Bpc and considering Ycbcr420 only modes.
v2: Rebase
Currently we use the highest input BPC supported by DP sink while using
DSC.In cases where PCON with HDMI2.1 as branch device, if PCON supports
DSC but HDMI2.1 sink does not supports DSC, The PCON tries to use same
input BPC that is used between Source and the PCON without DSC, which
might not
Currently there are many places where we use output_bpp for link bpp and
compressed bpp.
Lets use consistent naming:
output_bpp : The intermediate value taking into account the
output_format chroma subsampling.
compressed_bpp : target bpp for the DSC encoder.
link_bpp : final bpp used in the link.
The final link bpp used to calculate the m_n values depend on the
output_format. Though the output_format is set to RGB for MST case and
the link bpp will be same as the pipe bpp, for the sake of semantics,
lets calculate the m_n values with the link bpp, instead of pipe_bpp.
Signed-off-by: Ankit
While using DSC the compressed bpp is computed assuming RGB output
format. Consider the output_format and compute the compressed bpp
during mode valid and compute config steps.
For DP-MST we currently use RGB output format only, so continue
using RGB while computing compressed bpp for MST case.
This series fixes issues faced when an HDMI2.1 sink that does not
support DSC is connected via HDMI2.1PCON. It also includes other minor
HDMI2.1 PCON fixes/refactoring.
Patch 1-3 Have minor fixes to consider output_format while computing
dsc_bpp and have consistent naming for pipe_bpp, link_bpp
== Series Details ==
Series: drm/i915: Fix wrong condition in bxt_set_cdclk for DG2 (rev2)
URL : https://patchwork.freedesktop.org/series/117420/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13120 -> Patchwork_117420v2
> -Original Message-
> From: Intel-gfx On Behalf Of
> Radhakrishna Sripada
> Sent: Saturday, May 6, 2023 5:16 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Roper, Matthew D
> Subject: [Intel-gfx] [PATCH] drm/i915/mtl: Fix the wa number for
> Wa_22016670082
>
> Fixes the right
== Series Details ==
Series: drm/i915: Fix wrong condition in bxt_set_cdclk for DG2 (rev2)
URL : https://patchwork.freedesktop.org/series/117420/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
> -Original Message-
> From: Intel-gfx On Behalf Of
> Juha-Pekka Heikkila
> Sent: Thursday, May 4, 2023 1:28 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 4/4] drm/i915/mtl: Add handling for MTL ccs
> modifiers
>
> Add Tile4 ccs modifiers w/ auxbuffer handling
On 06.05.2023 16:42, Stanislav Lisovskiy wrote:
By my own mistake, after adding !IS_DG2 into wrong branch,
bxt_set_cdclk started to execute code intended for platforms
gen < 11, which is wrong.
Move IS_DG2 check to better place.
Fixes: ceb0cc3b4288 ("drm/i915: Communicate display power demands
Pushed the series to drm-intel-gt-next.
This should handle few long standing MTL failures.
On 5/5/2023 4:40 PM, Nirmoy Das wrote:
From: Pallavi Mishra
Remove FLAT CCS check from XY_FAST_COLOR_BLT usage, thus
enabling MTL to use it.
Signed-off-by: Pallavi Mishra
Signed-off-by: Juha-Pekka
On Sat, 2023-05-06 at 17:42 +0300, Stanislav Lisovskiy wrote:
> By my own mistake, after adding !IS_DG2 into wrong branch,
> bxt_set_cdclk started to execute code intended for platforms
> gen < 11, which is wrong.
> Move IS_DG2 check to better place.
>
> Fixes: ceb0cc3b4288 ("drm/i915:
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