Re: [Intel-gfx] [PATCH v3 21/28] KVM: x86/mmu: Use page-track notifiers iff there are external users
Reviewed-by: Yan Zhao
On Fri, May 12, 2023 at 05:35:53PM -0700, Sean Christopherson wrote:
> Disable the page-track notifier code at compile time if there are no
> external users, i.e. if CONFIG_KVM_EXTERNAL_WRITE_TRACKING=n. KVM itself
> now hooks emulated writes directly instead of relying on the page-track
> mechanism.
>
> Provide a stub for "struct kvm_page_track_notifier_node" so that including
> headers directly from the command line, e.g. for testing include guards,
> doesn't fail due to a struct having an incomplete type.
>
> Signed-off-by: Sean Christopherson
> ---
> arch/x86/include/asm/kvm_host.h | 2 ++
> arch/x86/include/asm/kvm_page_track.h | 22 +---
> arch/x86/kvm/mmu/page_track.c | 10 -
> arch/x86/kvm/mmu/page_track.h | 29 +++
> 4 files changed, 47 insertions(+), 16 deletions(-)
>
> diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
> index 113598d3e886..5ce06a75d3de 100644
> --- a/arch/x86/include/asm/kvm_host.h
> +++ b/arch/x86/include/asm/kvm_host.h
> @@ -1247,7 +1247,9 @@ struct kvm_arch {
>* create an NX huge page (without hanging the guest).
>*/
> struct list_head possible_nx_huge_pages;
> +#ifdef CONFIG_KVM_EXTERNAL_WRITE_TRACKING
> struct kvm_page_track_notifier_head track_notifier_head;
> +#endif
> /*
>* Protects marking pages unsync during page faults, as TDP MMU page
>* faults only take mmu_lock for read. For simplicity, the unsync
> diff --git a/arch/x86/include/asm/kvm_page_track.h
> b/arch/x86/include/asm/kvm_page_track.h
> index 76c0070dfe2a..61adb07b5927 100644
> --- a/arch/x86/include/asm/kvm_page_track.h
> +++ b/arch/x86/include/asm/kvm_page_track.h
> @@ -9,6 +9,14 @@ enum kvm_page_track_mode {
> KVM_PAGE_TRACK_MAX,
> };
>
> +void kvm_slot_page_track_add_page(struct kvm *kvm,
> + struct kvm_memory_slot *slot, gfn_t gfn,
> + enum kvm_page_track_mode mode);
> +void kvm_slot_page_track_remove_page(struct kvm *kvm,
> + struct kvm_memory_slot *slot, gfn_t gfn,
> + enum kvm_page_track_mode mode);
> +
> +#ifdef CONFIG_KVM_EXTERNAL_WRITE_TRACKING
> /*
> * The notifier represented by @kvm_page_track_notifier_node is linked into
> * the head which will be notified when guest is triggering the track event.
> @@ -48,18 +56,18 @@ struct kvm_page_track_notifier_node {
> struct kvm_page_track_notifier_node *node);
> };
>
> -void kvm_slot_page_track_add_page(struct kvm *kvm,
> - struct kvm_memory_slot *slot, gfn_t gfn,
> - enum kvm_page_track_mode mode);
> -void kvm_slot_page_track_remove_page(struct kvm *kvm,
> - struct kvm_memory_slot *slot, gfn_t gfn,
> - enum kvm_page_track_mode mode);
> -
> void
> kvm_page_track_register_notifier(struct kvm *kvm,
>struct kvm_page_track_notifier_node *n);
> void
> kvm_page_track_unregister_notifier(struct kvm *kvm,
> struct kvm_page_track_notifier_node *n);
> +#else
> +/*
> + * Allow defining a node in a structure even if page tracking is disabled,
> e.g.
> + * to play nice with testing headers via direct inclusion from the command
> line.
> + */
> +struct kvm_page_track_notifier_node {};
> +#endif /* CONFIG_KVM_EXTERNAL_WRITE_TRACKING */
>
> #endif
> diff --git a/arch/x86/kvm/mmu/page_track.c b/arch/x86/kvm/mmu/page_track.c
> index e15329d48f95..b20aad7ac3fe 100644
> --- a/arch/x86/kvm/mmu/page_track.c
> +++ b/arch/x86/kvm/mmu/page_track.c
> @@ -194,6 +194,7 @@ bool kvm_slot_page_track_is_active(struct kvm *kvm,
> return !!READ_ONCE(slot->arch.gfn_track[mode][index]);
> }
>
> +#ifdef CONFIG_KVM_EXTERNAL_WRITE_TRACKING
> void kvm_page_track_cleanup(struct kvm *kvm)
> {
> struct kvm_page_track_notifier_head *head;
> @@ -255,14 +256,13 @@ EXPORT_SYMBOL_GPL(kvm_page_track_unregister_notifier);
> * The node should figure out if the written page is the one that node is
> * interested in by itself.
> */
> -void kvm_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, const u8 *new,
> - int bytes)
> +void __kvm_page_track_write(struct kvm *kvm, gpa_t gpa, const u8 *new, int
> bytes)
> {
> struct kvm_page_track_notifier_head *head;
> struct kvm_page_track_notifier_node *n;
> int idx;
>
> - head = >kvm->arch.track_notifier_head;
> + head = >arch.track_notifier_head;
>
> if (hlist_empty(>track_notifier_list))
> return;
> @@ -273,8 +273,6 @@ void kvm_page_track_write(struct kvm_vcpu *vcpu, gpa_t
> gpa, const u8 *new,
> if (n->track_write)
> n->track_write(gpa, new, bytes, n);
>
Re: [Intel-gfx] [Freedreno] [PATCH v5 6/8] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
> -Original Message-
> From: Dmitry Baryshkov
> Sent: Wednesday, May 17, 2023 5:33 AM
> To: Kandpal, Suraj ; David Airlie
> ; Daniel Vetter ; Jani Nikula
> ; Joonas Lahtinen
> ; Vivi, Rodrigo ;
> Tvrtko Ursulin ; Rob Clark
> ; Abhinav Kumar ;
> Sean Paul ; Marijn Suijten
>
> Cc: linux-arm-...@vger.kernel.org; intel-gfx@lists.freedesktop.org;
> freedr...@lists.freedesktop.org; dri-de...@lists.freedesktop.org; Ville
> Syrjälä
> Subject: Re: [Freedreno] [PATCH v5 6/8] drm/display/dsc: split DSC 1.2 and
> DSC 1.1 (pre-SCR) parameters
>
> On 16/05/2023 21:46, Kandpal, Suraj wrote:
> >>
> >> The array of rc_parameters contains a mixture of parameters from DSC
> >> 1.1 and DSC 1.2 standards. Split these tow configuration arrays in
> >> preparation to adding more configuration data.
> >>
> >
> > Hi ,
> > Needed to add some more comments apart from the previous ones
> already
> > given
> >
>
> [skipped]
>
>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> index d4340b18c18d..bd9116d2cd76 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> @@ -226,7 +226,15 @@ int intel_dsc_compute_params(struct
> >> intel_crtc_state *pipe_config)
> >>if (DISPLAY_VER(dev_priv) >= 13) {
> >>calculate_rc_params(vdsc_cfg);
> >>} else {
> >> - ret = drm_dsc_setup_rc_params(vdsc_cfg);
> >> + if ((compressed_bpp == 8 ||
> >> + compressed_bpp == 12) &&
> >> + (vdsc_cfg->bits_per_component == 8 ||
> >> + vdsc_cfg->bits_per_component == 10 ||
> >> + vdsc_cfg->bits_per_component == 12))
> >> + ret = drm_dsc_setup_rc_params(vdsc_cfg,
> >> DRM_DSC_1_1_PRE_SCR);
> >> + else
> >> + ret = drm_dsc_setup_rc_params(vdsc_cfg,
> >> DRM_DSC_1_2_444);
> >> +
> >
> > I do not think this kind of assignment works as you will also be
> > adding
> > DRM_DSC_1_2_422 and DRM_DSC_1_2_420 in further patches and AFAICS
> > There is no where in patch 8 that you have accounted for when 422 or 420
> will be used.
> > Maybe you can add an if case inside the else block to check
> > pipe_config->output_format to pass the rc_param_data in patch 8
>
> I don't think this is necessary for now. The driver doesn't support YUV 422.
> The YUV 420 is supported only for DISPLAY_VER(dev_priv) >= 14, however
> these helpers are only used for DISPLAY_VER(dev_priv) < 13.
>
> I did not move RC calculation to drm_dsc_helpers.c (yet ?), which is used for
> DISPLAY_VER >= 13.
Hmm. I see I'll work on it once this patch series is merged
Regards,
Suraj Kandpal
>
> >
> > Regards,
> > Suraj Kandpal
> >>if (ret)
> >>return ret;
> >>
> >> diff --git a/include/drm/display/drm_dsc_helper.h
> >> b/include/drm/display/drm_dsc_helper.h
> >> index 1681791f65a5..c634bb2935d3 100644
> >> --- a/include/drm/display/drm_dsc_helper.h
> >> +++ b/include/drm/display/drm_dsc_helper.h
> >> @@ -10,12 +10,17 @@
> >>
> >> #include
> >>
> >> +enum drm_dsc_params_kind {
> >> + DRM_DSC_1_2_444,
> >> + DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */ };
> >> +
> >> void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
> >> int
> >> drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8
> >> rc_buffer_size); void drm_dsc_pps_payload_pack(struct
> >> drm_dsc_picture_parameter_set *pps_sdp,
> >> const struct drm_dsc_config *dsc_cfg); void
> >> drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg); -int
> >> drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
> >> +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum
> >> +drm_dsc_params_kind kind);
> >> int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
> >>
> >> #endif /* _DRM_DSC_HELPER_H_ */
> >> --
> >> 2.39.2
> >
>
> --
> With best wishes
> Dmitry
Re: [Intel-gfx] [PATCH v6 6/8] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
>
> The array of rc_parameters contains a mixture of parameters from DSC 1.1
> and DSC 1.2 standards. Split these tow configuration arrays in preparation to
> adding more configuration data.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 139 ++
> drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
> include/drm/display/drm_dsc_helper.h | 7 +-
> 3 files changed, 129 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c
> b/drivers/gpu/drm/display/drm_dsc_helper.c
> index acb93d4116e0..f9d01d72c1ff 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -325,10 +325,88 @@ struct rc_parameters_data {
> #define DSC_BPP(bpp) ((bpp) << 4)
>
> /*
> - * Selected Rate Control Related Parameter Recommended Values
> - * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> + * Rate Control Related Parameter Recommended Values from DSC_v1.1
> spec
> + prior
> + * to DSC 1.1 fractional bpp underflow SCR (DSC_v1.1_E1.pdf)
> + *
> + * Cross-checked against C Model releases: DSC_model_20161212 and
> + 20210623
> */
> -static const struct rc_parameters_data rc_parameters[] = {
> +static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> + {
> + .bpp = DSC_BPP(8), .bpc = 8,
> + { 512, 12, 6144, 3, 12, 11, 11, {
> + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12,
> -12 },
> + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(8), .bpc = 10,
> + { 512, 12, 6144, 7, 16, 15, 15, {
> + /*
> + * DSC model/pre-SCR-cfg has 8 for
> range_max_qp[0], however
> + * VESA DSC 1.1 Table E-5 sets it to 4.
> + */
> + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12,
> -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16,
> -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(8), .bpc = 12,
> + { 512, 12, 6144, 11, 20, 19, 19, {
> + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11,
> 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 8,
> + { 341, 15, 2048, 3, 12, 11, 11, {
> + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13,
> 15, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 10,
> + { 341, 15, 2048, 7, 16, 15, 15, {
> + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8
> },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16,
> -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 12,
> + { 341, 15, 2048, 11, 20, 19, 19, {
> + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11,
> 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> + },
> + { /* sentinel */ }
> +};
> +
> +/*
> + * Selected Rate Control Related Parameter Recommended Values from DSC
> +v1.2, v1.2a, v1.2b and
> + * DSC_v1.1_E1 specs.
> + *
> + * Cross-checked against C Model releases: DSC_model_20161212 and
> +20210623 */ static const struct rc_parameters_data
> +rc_parameters_1_2_444[] = {
> {
> .bpp = DSC_BPP(6), .bpc = 8,
> { 768, 15, 6144, 3, 13, 11, 11, {
> @@ -388,22 +466,18 @@ static const struct
Re: [Intel-gfx] [PATCH v3 12/28] KVM: x86/mmu: Don't rely on page-track mechanism to flush on memslot change
Reviewed-by: Yan Zhao
On Fri, May 12, 2023 at 05:35:44PM -0700, Sean Christopherson wrote:
> Call kvm_mmu_zap_all_fast() directly when flushing a memslot instead of
> bouncing through the page-track mechanism. KVM (unfortunately) needs to
> zap and flush all page tables on memslot DELETE/MOVE irrespective of
> whether KVM is shadowing guest page tables.
>
> This will allow changing KVM to register a page-track notifier on the
> first shadow root allocation, and will also allow deleting the misguided
> kvm_page_track_flush_slot() hook itself once KVM-GT also moves to a
> different method for reacting to memslot changes.
>
> No functional change intended.
>
> Cc: Yan Zhao
> Link: https://lore.kernel.org/r/20221110014821.1548347-2-sea...@google.com
> Signed-off-by: Sean Christopherson
> ---
> arch/x86/kvm/mmu/mmu.c | 10 ++
> 1 file changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
> index 2e4476d38377..23a79723031b 100644
> --- a/arch/x86/kvm/mmu/mmu.c
> +++ b/arch/x86/kvm/mmu/mmu.c
> @@ -6184,13 +6184,6 @@ static bool kvm_has_zapped_obsolete_pages(struct kvm
> *kvm)
> return unlikely(!list_empty_careful(>arch.zapped_obsolete_pages));
> }
>
> -static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
> - struct kvm_memory_slot *slot,
> - struct kvm_page_track_notifier_node *node)
> -{
> - kvm_mmu_zap_all_fast(kvm);
> -}
> -
> int kvm_mmu_init_vm(struct kvm *kvm)
> {
> struct kvm_page_track_notifier_node *node = >arch.mmu_sp_tracker;
> @@ -6208,7 +6201,6 @@ int kvm_mmu_init_vm(struct kvm *kvm)
> }
>
> node->track_write = kvm_mmu_pte_write;
> - node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
> kvm_page_track_register_notifier(kvm, node);
>
> kvm->arch.split_page_header_cache.kmem_cache = mmu_page_header_cache;
> @@ -6750,6 +6742,8 @@ void kvm_arch_flush_shadow_all(struct kvm *kvm)
> void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
> struct kvm_memory_slot *slot)
> {
> + kvm_mmu_zap_all_fast(kvm);
> +
> kvm_page_track_flush_slot(kvm, slot);
> }
>
> --
> 2.40.1.606.ga4b1b128d6-goog
>
Re: [Intel-gfx] [v2, 11/12] drm/fbdev-generic: Implement dedicated fbdev I/O helpers
Hi, Thomas
After apply your patch set, the kernel with
arch/loongarch/configs/loongson3_defconfig
can not finish compile anymore. gcc complains:
AR drivers/gpu/built-in.a
AR drivers/built-in.a
AR built-in.a
AR vmlinux.a
LD vmlinux.o
OBJCOPY modules.builtin.modinfo
GEN modules.builtin
GEN .vmlinux.objs
MODPOST Module.symvers
ERROR: modpost: "fb_sys_write" [drivers/gpu/drm/drm_kms_helper.ko]
undefined!
ERROR: modpost: "sys_imageblit" [drivers/gpu/drm/drm_kms_helper.ko]
undefined!
ERROR: modpost: "sys_fillrect" [drivers/gpu/drm/drm_kms_helper.ko]
undefined!
ERROR: modpost: "sys_copyarea" [drivers/gpu/drm/drm_kms_helper.ko]
undefined!
ERROR: modpost: "fb_sys_read" [drivers/gpu/drm/drm_kms_helper.ko] undefined!
make[1]: *** [scripts/Makefile.modpost:136: Module.symvers] Error 1
make: *** [Makefile:1978: modpost] Error 2
On 2023/5/15 17:40, Thomas Zimmermann wrote:
Implement dedicated fbdev helpers for framebuffer I/O instead
of using DRM's helpers. Fbdev-generic was the only caller of the
DRM helpers, so remove them from the helper module.
v2:
* use FB_SYS_HELPERS_DEFERRED option
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/Kconfig | 6 +-
drivers/gpu/drm/drm_fb_helper.c | 107
drivers/gpu/drm/drm_fbdev_generic.c | 47 ++--
include/drm/drm_fb_helper.h | 41 ---
4 files changed, 43 insertions(+), 158 deletions(-)
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 77fb10ddd8a2..92a782827b7b 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -95,6 +95,7 @@ config DRM_KUNIT_TEST
config DRM_KMS_HELPER
tristate
depends on DRM
+ select FB_SYS_HELPERS_DEFERRED if DRM_FBDEV_EMULATION
Here, select FB_SYS_HELPERS helps resolve the above issue mentioned.
help
CRTC helpers for KMS drivers.
@@ -135,11 +136,6 @@ config DRM_FBDEV_EMULATION
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
- select FB_DEFERRED_IO
- select FB_SYS_FOPS
- select FB_SYS_FILLRECT
- select FB_SYS_COPYAREA
- select FB_SYS_IMAGEBLIT
select FRAMEBUFFER_CONSOLE if !EXPERT
select FRAMEBUFFER_CONSOLE_DETECT_PRIMARY if FRAMEBUFFER_CONSOLE
default y
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 8724e08c518b..ba0a808f14ee 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -729,113 +729,6 @@ void drm_fb_helper_deferred_io(struct fb_info *info,
struct list_head *pagerefli
}
EXPORT_SYMBOL(drm_fb_helper_deferred_io);
-/**
- * drm_fb_helper_sys_read - Implements struct _ops.fb_read for system memory
- * @info: fb_info struct pointer
- * @buf: userspace buffer to read from framebuffer memory
- * @count: number of bytes to read from framebuffer memory
- * @ppos: read offset within framebuffer memory
- *
- * Returns:
- * The number of bytes read on success, or an error code otherwise.
- */
-ssize_t drm_fb_helper_sys_read(struct fb_info *info, char __user *buf,
- size_t count, loff_t *ppos)
-{
- return fb_sys_read(info, buf, count, ppos);
-}
-EXPORT_SYMBOL(drm_fb_helper_sys_read);
-
-/**
- * drm_fb_helper_sys_write - Implements struct _ops.fb_write for system
memory
- * @info: fb_info struct pointer
- * @buf: userspace buffer to write to framebuffer memory
- * @count: number of bytes to write to framebuffer memory
- * @ppos: write offset within framebuffer memory
- *
- * Returns:
- * The number of bytes written on success, or an error code otherwise.
- */
-ssize_t drm_fb_helper_sys_write(struct fb_info *info, const char __user *buf,
- size_t count, loff_t *ppos)
-{
- struct drm_fb_helper *helper = info->par;
- loff_t pos = *ppos;
- ssize_t ret;
- struct drm_rect damage_area;
-
- ret = fb_sys_write(info, buf, count, ppos);
- if (ret <= 0)
- return ret;
-
- if (helper->funcs->fb_dirty) {
- drm_fb_helper_memory_range_to_clip(info, pos, ret,
_area);
- drm_fb_helper_damage(helper, damage_area.x1, damage_area.y1,
-drm_rect_width(_area),
-drm_rect_height(_area));
- }
-
- return ret;
-}
-EXPORT_SYMBOL(drm_fb_helper_sys_write);
-
-/**
- * drm_fb_helper_sys_fillrect - wrapper around sys_fillrect
- * @info: fbdev registered by the helper
- * @rect: info about rectangle to fill
- *
- * A wrapper around sys_fillrect implemented by fbdev core
- */
-void drm_fb_helper_sys_fillrect(struct fb_info *info,
- const struct fb_fillrect *rect)
-{
- struct drm_fb_helper *helper = info->par;
-
- sys_fillrect(info, rect);
-
- if (helper->funcs->fb_dirty)
-
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/2] drm/i915/mtl: Add MTL performance tuning changes
== Series Details ==
Series: series starting with [v4,1/2] drm/i915/mtl: Add MTL performance tuning
changes
URL : https://patchwork.freedesktop.org/series/117847/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13154 -> Patchwork_117847v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117847v1/index.html
Participating hosts (38 -> 37)
--
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_117847v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3@smem:
- bat-rpls-2: NOTRUN -> [FAIL][1] ([fdo#103375]) +2 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117847v1/bat-rpls-2/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: [PASS][2] -> [DMESG-FAIL][3] ([i915#5334] /
[i915#7872])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117847v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: [PASS][4] -> [DMESG-WARN][5] ([i915#6367])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-rpls-2/igt@i915_selftest@l...@slpc.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117847v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-rpls-2: NOTRUN -> [SKIP][6] ([i915#7828])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117847v1/bat-rpls-2/igt@kms_chamelium_...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][7] ([i915#1845] / [i915#5354]) +2
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117847v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-rpls-2: NOTRUN -> [SKIP][8] ([i915#1845])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117847v1/bat-rpls-2/igt@kms_pipe_crc_ba...@suspend-read-crc.html
Possible fixes
* igt@i915_selftest@live@requests:
- {bat-mtlp-8}: [ABORT][9] ([i915#4983] / [i915#7920]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-mtlp-8/igt@i915_selftest@l...@requests.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117847v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html
- {bat-mtlp-6}: [ABORT][11] ([i915#4983] / [i915#7920]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-mtlp-6/igt@i915_selftest@l...@requests.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117847v1/bat-mtlp-6/igt@i915_selftest@l...@requests.html
Warnings
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: [ABORT][13] ([i915#6687]) -> [FAIL][14] ([fdo#103375])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117847v1/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: [SKIP][15] ([i915#3555] / [i915#4579]) -> [ABORT][16]
([i915#4579] / [i915#8260])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117847v1/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
[i915#7920]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v4,1/2] drm/i915/mtl: Add MTL performance tuning changes
== Series Details == Series: series starting with [v4,1/2] drm/i915/mtl: Add MTL performance tuning changes URL : https://patchwork.freedesktop.org/series/117847/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./drivers/gpu/drm/i915/intel_uncore.h:346:1: warning: trying to copy expression type 31 +./drivers/gpu/drm/i915/intel_uncore.h:351:1: warning: trying to copy expression type 31 +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask'
Re: [Intel-gfx] [PATCH v3 07/28] drm/i915/gvt: Don't rely on KVM's gfn_to_pfn() to query possible 2M GTT
Reviewed-by: Yan Zhao
Tested-by: Yan Zhao
On Fri, May 12, 2023 at 05:35:39PM -0700, Sean Christopherson wrote:
> Now that gvt_pin_guest_page() explicitly verifies the pinned PFN is a
> transparent hugepage page, don't use KVM's gfn_to_pfn() to pre-check if a
> 2MiB GTT entry is possible and instead just try to map the GFN with a 2MiB
> entry. Using KVM to query pfn that is ultimately managed through VFIO is
> odd, and KVM's gfn_to_pfn() is not intended for non-KVM consumption; it's
> exported only because of KVM vendor modules (x86 and PPC).
>
> Open code the check on 2MiB support instead of keeping
> is_2MB_gtt_possible() around for a single line of code.
>
> Move the call to intel_gvt_dma_map_guest_page() for a 4KiB entry into its
> case statement, i.e. fork the common path into the 4KiB and 2MiB "direct"
> shadow paths. Keeping the call in the "common" path is arguably more in
> the spirit of "one change per patch", but retaining the local "page_size"
> variable is silly, i.e. the call site will be changed either way, and
> jumping around the no-longer-common code is more subtle and rather odd,
> i.e. would just need to be immediately cleaned up.
>
> Drop the error message from gvt_pin_guest_page() when KVMGT attempts to
> shadow a 2MiB guest page that isn't backed by a compatible hugepage in the
> host. Dropping the pre-check on a THP makes it much more likely that the
> "error" will be encountered in normal operation.
>
> Signed-off-by: Sean Christopherson
> ---
> drivers/gpu/drm/i915/gvt/gtt.c | 49 ++--
> drivers/gpu/drm/i915/gvt/kvmgt.c | 1 -
> 2 files changed, 8 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> index 61e38acee2d5..f505be9e647a 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.c
> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> @@ -1145,36 +1145,6 @@ static inline void ppgtt_generate_shadow_entry(struct
> intel_gvt_gtt_entry *se,
> ops->set_pfn(se, s->shadow_page.mfn);
> }
>
> -/*
> - * Check if can do 2M page
> - * @vgpu: target vgpu
> - * @entry: target pfn's gtt entry
> - *
> - * Return 1 if 2MB huge gtt shadowing is possible, 0 if miscondition,
> - * negative if found err.
> - */
> -static int is_2MB_gtt_possible(struct intel_vgpu *vgpu,
> - struct intel_gvt_gtt_entry *entry)
> -{
> - const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
> - kvm_pfn_t pfn;
> - int ret;
> -
> - if (!HAS_PAGE_SIZES(vgpu->gvt->gt->i915, I915_GTT_PAGE_SIZE_2M))
> - return 0;
> -
> - pfn = gfn_to_pfn(vgpu->vfio_device.kvm, ops->get_pfn(entry));
> - if (is_error_noslot_pfn(pfn))
> - return -EINVAL;
> -
> - if (!pfn_valid(pfn))
> - return -EINVAL;
> -
> - ret = PageTransHuge(pfn_to_page(pfn));
> - kvm_release_pfn_clean(pfn);
> - return ret;
> -}
> -
> static int split_2MB_gtt_entry(struct intel_vgpu *vgpu,
> struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
> struct intel_gvt_gtt_entry *se)
> @@ -1268,7 +1238,7 @@ static int ppgtt_populate_shadow_entry(struct
> intel_vgpu *vgpu,
> {
> const struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
> struct intel_gvt_gtt_entry se = *ge;
> - unsigned long gfn, page_size = PAGE_SIZE;
> + unsigned long gfn;
> dma_addr_t dma_addr;
> int ret;
>
> @@ -1283,6 +1253,9 @@ static int ppgtt_populate_shadow_entry(struct
> intel_vgpu *vgpu,
> switch (ge->type) {
> case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
> gvt_vdbg_mm("shadow 4K gtt entry\n");
> + ret = intel_gvt_dma_map_guest_page(vgpu, gfn, PAGE_SIZE,
> _addr);
> + if (ret)
> + return -ENXIO;
> break;
> case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
> gvt_vdbg_mm("shadow 64K gtt entry\n");
> @@ -1294,12 +1267,10 @@ static int ppgtt_populate_shadow_entry(struct
> intel_vgpu *vgpu,
> return split_64KB_gtt_entry(vgpu, spt, index, );
> case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
> gvt_vdbg_mm("shadow 2M gtt entry\n");
> - ret = is_2MB_gtt_possible(vgpu, ge);
> - if (ret == 0)
> + if (!HAS_PAGE_SIZES(vgpu->gvt->gt->i915, I915_GTT_PAGE_SIZE_2M)
> ||
> + intel_gvt_dma_map_guest_page(vgpu, gfn,
> + I915_GTT_PAGE_SIZE_2M,
> _addr))
> return split_2MB_gtt_entry(vgpu, spt, index, );
> - else if (ret < 0)
> - return ret;
> - page_size = I915_GTT_PAGE_SIZE_2M;
> break;
> case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
> gvt_vgpu_err("GVT doesn't support 1GB entry\n");
> @@ -1309,11 +1280,7 @@ static int ppgtt_populate_shadow_entry(struct
> intel_vgpu *vgpu,
> return -EINVAL;
> }
>
> - /* direct shadow */
> - ret = intel_gvt_dma_map_guest_page(vgpu,
[Intel-gfx] [PATCH v4 2/2] drm/i915/mtl: Extend Wa_16014892111 to MTL A-step
Like DG2, MTL a-step hardware is subject to Wa_16014892111 which requires that any changes made to the DRAW_WATERMARK register be done via an INDIRECT_CTX batch buffer rather than through a regular context workaround. The bspec gives the same non-default recommended tuning value for DRAW_WATERMARK as DG2, so we can re-use the INDIRECT_CTX code to apply that tuning setting on A-step hardware. Application of the tuning setting on B-step and later does not need INDIRECT_CTX handling and is already done in mtl_ctx_workarounds_init() as usual. v2: Limit the WA for A-step v3: Update the commit message. v4: Reorder platform checks and update commit message. Bspec: 68331 Cc: Haridhar Kalvala Cc: Gustavo Sousa Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 81a96c52a92b..a4ec20aaafe2 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1370,7 +1370,9 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs) cs, GEN12_GFX_CCS_AUX_NV); /* Wa_16014892111 */ - if (IS_DG2(ce->engine->i915)) + if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) || + IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) || + IS_DG2(ce->engine->i915)) cs = dg2_emit_draw_watermark_setting(cs); return cs; -- 2.34.1
[Intel-gfx] [PATCH v4 1/2] drm/i915/mtl: Add MTL performance tuning changes
MTL reuses the tuning parameters for DG2. Extend the dg2
performance tuning parameters to MTL.
v2: Add DRAW_WATERMARK tuning parameter.
v3: Limit DRAW_WATERMARK tuning to non A0 step.
v4: Reorder platform checks.
Restrict Blend fill caching optimization to Render GT.
Bspec: 68331
Cc: Haridhar Kalvala
Cc: Matt Roper
Cc: Gustavo Sousa
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 786349e95487..b6d3185cf868 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -817,6 +817,12 @@ static void mtl_ctx_workarounds_init(struct
intel_engine_cs *engine,
{
struct drm_i915_private *i915 = engine->i915;
+ dg2_ctx_gt_tuning_init(engine, wal);
+
+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
+ wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
+
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
/* Wa_14014947963 */
@@ -1748,6 +1754,13 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct
i915_wa_list *wal)
*/
static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
{
+ if (IS_METEORLAKE(gt->i915)) {
+ if (gt->type != GT_MEDIA)
+ wa_mcr_write_or(wal, XEHP_L3SCQREG7,
BLEND_FILL_CACHING_OPT_DIS);
+
+ wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
+ }
+
if (IS_PONTEVECCHIO(gt->i915)) {
wa_mcr_write(wal, XEHPC_L3SCRUB,
SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
@@ -2944,7 +2957,7 @@ static void
add_render_compute_tuning_settings(struct drm_i915_private *i915,
struct i915_wa_list *wal)
{
- if (IS_DG2(i915))
+ if (IS_METEORLAKE(i915) || IS_DG2(i915))
wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL,
STACKID_CTRL_512);
/*
--
2.34.1
Re: [Intel-gfx] [PATCH v5 6/7] drm/i915/pmu: Prepare for multi-tile non-engine counters
On Tue, 16 May 2023 16:35:33 -0700, Umesh Nerlige Ramappa wrote:
>
Hi Umesh,
> +static u64 frequency_enabled_mask(void)
u32
> +{
> + unsigned int i;
> + u64 mask = 0;
u32
> +
> + for (i = 0; i < I915_PMU_MAX_GTS; i++)
> + mask |= config_mask(__I915_PMU_ACTUAL_FREQUENCY(i)) |
> + config_mask(__I915_PMU_REQUESTED_FREQUENCY(i));
> +
> + return mask;
> +}
> +
> static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active)
> {
> struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
> - u32 enable;
> + u64 enable;
u32
>
> /*
>* Only some counters need the sampling timer.
> @@ -131,9 +155,7 @@ static bool pmu_needs_timer(struct i915_pmu *pmu, bool
> gpu_active)
>* Mask out all the ones which do not need the timer, or in
>* other words keep all the ones that could need the timer.
>*/
> - enable &= config_mask(I915_PMU_ACTUAL_FREQUENCY) |
> - config_mask(I915_PMU_REQUESTED_FREQUENCY) |
> - ENGINE_SAMPLE_MASK;
> + enable &= frequency_enabled_mask() | ENGINE_SAMPLE_MASK;
>
> /*
>* When the GPU is idle per-engine counters do not need to be
/snip/
> diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
> index 3a811266ac6a..f88de9ae1ebb 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.h
> +++ b/drivers/gpu/drm/i915/i915_pmu.h
> @@ -38,13 +38,16 @@ enum {
> __I915_NUM_PMU_SAMPLERS
> };
>
> +#define I915_PMU_MAX_GTS 2
> +
> /*
> * How many different events we track in the global PMU mask.
> *
> * It is also used to know to needed number of event reference counters.
> */
> #define I915_PMU_MASK_BITS \
> - (I915_ENGINE_SAMPLE_COUNT + __I915_PMU_TRACKED_EVENT_COUNT)
> + (I915_ENGINE_SAMPLE_COUNT + \
> + I915_PMU_MAX_GTS * __I915_PMU_TRACKED_EVENT_COUNT)
>
> #define I915_ENGINE_SAMPLE_COUNT (I915_SAMPLE_SEMA + 1)
>
> @@ -95,7 +98,7 @@ struct i915_pmu {
>*
>* Low bits are engine samplers and other events continue from there.
>*/
> - u32 enable;
> + u64 enable;
u32
Thanks.
--
Ashutosh
[Intel-gfx] ✓ Fi.CI.BAT: success for Add MTL PMU support for multi-gt
== Series Details == Series: Add MTL PMU support for multi-gt URL : https://patchwork.freedesktop.org/series/117843/ State : success == Summary == CI Bug Log - changes from CI_DRM_13154 -> Patchwork_117843v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/index.html Participating hosts (38 -> 36) -- Missing(2): fi-kbl-soraka fi-snb-2520m Known issues Here are the changes found in Patchwork_117843v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3@smem: - fi-rkl-11600: [PASS][1] -> [FAIL][2] ([fdo#103375]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html * igt@i915_selftest@live@gt_heartbeat: - fi-cfl-8109u: [PASS][3] -> [DMESG-FAIL][4] ([i915#5334]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/fi-cfl-8109u/igt@i915_selftest@live@gt_heartbeat.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/fi-cfl-8109u/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_mocs: - bat-dg1-7: [PASS][5] -> [ABORT][6] ([i915#4983]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-dg1-7/igt@i915_selftest@live@gt_mocs.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/bat-dg1-7/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@migrate: - bat-adls-5: [PASS][7] -> [ABORT][8] ([i915#4391] / [i915#7913]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-adls-5/igt@i915_selftest@l...@migrate.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/bat-adls-5/igt@i915_selftest@l...@migrate.html * igt@i915_selftest@live@requests: - bat-rpls-1: [PASS][9] -> [ABORT][10] ([i915#4983] / [i915#7911] / [i915#7920]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-rpls-1/igt@i915_selftest@l...@requests.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/bat-rpls-1/igt@i915_selftest@l...@requests.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#1845] / [i915#5354]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html * igt@prime_vgem@basic-userptr: - bat-atsm-1: NOTRUN -> [SKIP][12] ([fdo#109295]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/bat-atsm-1/igt@prime_v...@basic-userptr.html - fi-cfl-guc: NOTRUN -> [SKIP][13] ([fdo#109271]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/fi-cfl-guc/igt@prime_v...@basic-userptr.html - bat-jsl-3: NOTRUN -> [SKIP][14] ([fdo#109295] / [i915#3301]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/bat-jsl-3/igt@prime_v...@basic-userptr.html - bat-dg2-9: NOTRUN -> [SKIP][15] ([i915#3708] / [i915#4873]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/bat-dg2-9/igt@prime_v...@basic-userptr.html - fi-kbl-x1275: NOTRUN -> [SKIP][16] ([fdo#109271]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/fi-kbl-x1275/igt@prime_v...@basic-userptr.html - fi-hsw-4770:NOTRUN -> [SKIP][17] ([fdo#109271]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/fi-hsw-4770/igt@prime_v...@basic-userptr.html - fi-cfl-8109u: NOTRUN -> [SKIP][18] ([fdo#109271]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/fi-cfl-8109u/igt@prime_v...@basic-userptr.html - fi-kbl-8809g: NOTRUN -> [SKIP][19] ([fdo#109271]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/fi-kbl-8809g/igt@prime_v...@basic-userptr.html - bat-rpls-2: NOTRUN -> [SKIP][20] ([fdo#109295] / [i915#3708]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/bat-rpls-2/igt@prime_v...@basic-userptr.html - fi-elk-e7500: NOTRUN -> [SKIP][21] ([fdo#109271]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/fi-elk-e7500/igt@prime_v...@basic-userptr.html - bat-dg2-8: NOTRUN -> [SKIP][22] ([i915#3708] / [i915#4873]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/bat-dg2-8/igt@prime_v...@basic-userptr.html - fi-kbl-guc: NOTRUN -> [SKIP][23] ([fdo#109271]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/fi-kbl-guc/igt@prime_v...@basic-userptr.html - bat-adlm-1: NOTRUN -> [SKIP][24] ([i915#3708]) [24]:
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: move DSC RC tables to drm_dsc_helper.c (rev7)
== Series Details ==
Series: drm/i915: move DSC RC tables to drm_dsc_helper.c (rev7)
URL : https://patchwork.freedesktop.org/series/114473/
State : failure
== Summary ==
Error: make failed
CALLscripts/checksyscalls.sh
DESCEND objtool
INSTALL libsubcmd_headers
AR drivers/gpu/drm/xlnx/built-in.a
AR drivers/gpu/drm/gud/built-in.a
AR drivers/gpu/drm/solomon/built-in.a
CC [M] drivers/gpu/drm/display/drm_dsc_helper.o
drivers/gpu/drm/display/drm_dsc_helper.c: In function ‘drm_dsc_setup_rc_params’:
drivers/gpu/drm/display/drm_dsc_helper.c:1230:10: error: ‘kind’ undeclared
(first use in this function)
1230 | switch (kind) {
| ^~~~
drivers/gpu/drm/display/drm_dsc_helper.c:1230:10: note: each undeclared
identifier is reported only once for each function it appears in
make[5]: *** [scripts/Makefile.build:252:
drivers/gpu/drm/display/drm_dsc_helper.o] Error 1
make[4]: *** [scripts/Makefile.build:494: drivers/gpu/drm/display] Error 2
make[3]: *** [scripts/Makefile.build:494: drivers/gpu/drm] Error 2
make[2]: *** [scripts/Makefile.build:494: drivers/gpu] Error 2
make[1]: *** [scripts/Makefile.build:494: drivers] Error 2
make: *** [Makefile:2026: .] Error 2
Build failed, no error log produced
Re: [Intel-gfx] [PATCH v5 1/7] drm/i915/pmu: Change bitmask of enabled events to u32
On Tue, 16 May 2023 16:35:28 -0700, Umesh Nerlige Ramappa wrote:
>
Hi Umesh/Tvrtko,
Mostly repeating comments/questions made on the previous patch below.
> From: Tvrtko Ursulin
>
> Having it as u64 was a confusing (but harmless) mistake.
>
> Also add some asserts to make sure the internal field does not overflow
> in the future.
>
> v2: Fix WARN_ON firing for INTERRUPT event (Umesh)
>
> Signed-off-by: Tvrtko Ursulin
> Signed-off-by: Umesh Nerlige Ramappa
> Cc: Ashutosh Dixit
> ---
> drivers/gpu/drm/i915/i915_pmu.c | 26 ++
> 1 file changed, 18 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> index 7ece883a7d95..96543dce2db1 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -50,7 +50,7 @@ static u8 engine_event_instance(struct perf_event *event)
> return (event->attr.config >> I915_PMU_SAMPLE_BITS) & 0xff;
> }
>
> -static bool is_engine_config(u64 config)
> +static bool is_engine_config(const u64 config)
> {
> return config < __I915_PMU_OTHER(0);
> }
> @@ -88,9 +88,20 @@ static unsigned int config_bit(const u64 config)
> return other_bit(config);
> }
>
> -static u64 config_mask(u64 config)
> +static u32 config_mask(const u64 config)
> {
> - return BIT_ULL(config_bit(config));
> + unsigned int bit = config_bit(config);
Give that config_bit() can return -1 (I understand it is avoided in moving
the code to config_mask from config_bit), maybe the code below should also
have that check?
int bit = config_bit(config);
if (bit != -1)
{
...
}
Though as mentioned below the 'if (__builtin_constant_p())' would have to
go. Maybe the code could even have stayed in config_bit with the check.
> +
> + if (__builtin_constant_p(config))
> + BUILD_BUG_ON(bit >
> + BITS_PER_TYPE(typeof_member(struct i915_pmu,
> + enable)) - 1);
Given that config comes from the event (it is event->attr.config), can this
ever be a builtin constant?
> + else
> + WARN_ON_ONCE(bit >
> + BITS_PER_TYPE(typeof_member(struct i915_pmu,
> + enable)) - 1);
There is really an even stricter limit on what the bit can be, which is the
total number of possible events but anyway this is good enough.
After addressing the above, this patch is:
Reviewed-by: Ashutosh Dixit
> +
> + return BIT(config_bit(config));
> }
>
> static bool is_engine_event(struct perf_event *event)
> @@ -633,11 +644,10 @@ static void i915_pmu_enable(struct perf_event *event)
> {
> struct drm_i915_private *i915 =
> container_of(event->pmu, typeof(*i915), pmu.base);
> + const unsigned int bit = event_bit(event);
> struct i915_pmu *pmu = >pmu;
> unsigned long flags;
> - unsigned int bit;
>
> - bit = event_bit(event);
> if (bit == -1)
> goto update;
>
> @@ -651,7 +661,7 @@ static void i915_pmu_enable(struct perf_event *event)
> GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count));
> GEM_BUG_ON(pmu->enable_count[bit] == ~0);
>
> - pmu->enable |= BIT_ULL(bit);
> + pmu->enable |= BIT(bit);
> pmu->enable_count[bit]++;
>
> /*
> @@ -698,7 +708,7 @@ static void i915_pmu_disable(struct perf_event *event)
> {
> struct drm_i915_private *i915 =
> container_of(event->pmu, typeof(*i915), pmu.base);
> - unsigned int bit = event_bit(event);
> + const unsigned int bit = event_bit(event);
> struct i915_pmu *pmu = >pmu;
> unsigned long flags;
>
> @@ -734,7 +744,7 @@ static void i915_pmu_disable(struct perf_event *event)
>* bitmask when the last listener on an event goes away.
>*/
> if (--pmu->enable_count[bit] == 0) {
> - pmu->enable &= ~BIT_ULL(bit);
> + pmu->enable &= ~BIT(bit);
> pmu->timer_enabled &= pmu_needs_timer(pmu, true);
> }
>
> --
> 2.36.1
>
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,DO_NOT_MERGE,1/2] drm/i915/mtl: do not enable render power-gating on MTL
== Series Details ==
Series: series starting with [CI,DO_NOT_MERGE,1/2] drm/i915/mtl: do not enable
render power-gating on MTL
URL : https://patchwork.freedesktop.org/series/117839/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13154 -> Patchwork_117839v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117839v1/index.html
Participating hosts (38 -> 36)
--
Missing(2): fi-kbl-soraka fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_117839v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@basic-rte:
- {bat-mtlp-8}: [PASS][1] -> [TIMEOUT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-mtlp-8/igt@i915_pm_...@basic-rte.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117839v1/bat-mtlp-8/igt@i915_pm_...@basic-rte.html
Known issues
Here are the changes found in Patchwork_117839v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-tgl-1115g4: [PASS][3] -> [ABORT][4] ([i915#8189] / [i915#8213])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/fi-tgl-1115g4/igt@i915_susp...@basic-s2idle-without-i915.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117839v1/fi-tgl-1115g4/igt@i915_susp...@basic-s2idle-without-i915.html
Possible fixes
* igt@i915_selftest@live@migrate:
- bat-dg2-11: [DMESG-WARN][5] ([i915#7699]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-dg2-11/igt@i915_selftest@l...@migrate.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117839v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html
* igt@i915_selftest@live@requests:
- {bat-mtlp-8}: [ABORT][7] ([i915#4983] / [i915#7920]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-mtlp-8/igt@i915_selftest@l...@requests.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117839v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html
- {bat-mtlp-6}: [ABORT][9] ([i915#4983] / [i915#7920]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-mtlp-6/igt@i915_selftest@l...@requests.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117839v1/bat-mtlp-6/igt@i915_selftest@l...@requests.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
[i915#8189]: https://gitlab.freedesktop.org/drm/intel/issues/8189
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
Build changes
-
* Linux: CI_DRM_13154 -> Patchwork_117839v1
CI-20190529: 20190529
CI_DRM_13154: d04e82f5245c285e7ae36955d89c4d217d04d664 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7292: 9d9475ffd3b5ae18fd8ec120595385f6c562f249 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_117839v1: d04e82f5245c285e7ae36955d89c4d217d04d664 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
6e6a565e8ee5 drm/i915/gt: do not enable render and media power-gating on RPL-S
bc12366471fe drm/i915/mtl: do not enable render power-gating on MTL
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117839v1/index.html
[Intel-gfx] [PATCH v6 4/8] drm/i915/dsc: stop using interim structure for calculated params
Stop using an interim structure rc_parameters for storing calculated
params and then setting drm_dsc_config using that structure. Instead put
calculated params into the struct drm_dsc_config directly.
Reviewed-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 100 ++
1 file changed, 26 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index d0536582e4b9..d4340b18c18d 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -19,17 +19,6 @@
#include "intel_vdsc.h"
#include "intel_vdsc_regs.h"
-struct rc_parameters {
- u16 initial_xmit_delay;
- u8 first_line_bpg_offset;
- u16 initial_offset;
- u8 flatness_min_qp;
- u8 flatness_max_qp;
- u8 rc_quant_incr_limit0;
- u8 rc_quant_incr_limit1;
- struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
-};
-
bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
{
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -64,8 +53,7 @@ static bool is_pipe_dsc(struct intel_crtc *crtc, enum
transcoder cpu_transcoder)
}
static void
-calculate_rc_params(struct rc_parameters *rc,
- struct drm_dsc_config *vdsc_cfg)
+calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
{
int bpc = vdsc_cfg->bits_per_component;
int bpp = vdsc_cfg->bits_per_pixel >> 4;
@@ -85,56 +73,57 @@ calculate_rc_params(struct rc_parameters *rc,
u32 res, buf_i, bpp_i;
if (vdsc_cfg->slice_height >= 8)
- rc->first_line_bpg_offset =
+ vdsc_cfg->first_line_bpg_offset =
12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height -
8)), 100);
else
- rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
+ vdsc_cfg->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height -
1);
/* Our hw supports only 444 modes as of today */
if (bpp >= 12)
- rc->initial_offset = 2048;
+ vdsc_cfg->initial_offset = 2048;
else if (bpp >= 10)
- rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584),
2);
+ vdsc_cfg->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) *
3584), 2);
else if (bpp >= 8)
- rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
+ vdsc_cfg->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) *
512), 2);
else
- rc->initial_offset = 6144;
+ vdsc_cfg->initial_offset = 6144;
/* initial_xmit_delay = rc_model_size/2/compression_bpp */
- rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
+ vdsc_cfg->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2
* bpp);
- rc->flatness_min_qp = 3 + qp_bpc_modifier;
- rc->flatness_max_qp = 12 + qp_bpc_modifier;
+ vdsc_cfg->flatness_min_qp = 3 + qp_bpc_modifier;
+ vdsc_cfg->flatness_max_qp = 12 + qp_bpc_modifier;
- rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
- rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
+ vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
+ vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
bpp_i = (2 * (bpp - 6));
for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
+ u8 range_bpg_offset;
+
/* Read range_minqp and range_max_qp from qp tables */
- rc->rc_range_params[buf_i].range_min_qp =
+ vdsc_cfg->rc_range_params[buf_i].range_min_qp =
intel_lookup_range_min_qp(bpc, buf_i, bpp_i,
vdsc_cfg->native_420);
- rc->rc_range_params[buf_i].range_max_qp =
+ vdsc_cfg->rc_range_params[buf_i].range_max_qp =
intel_lookup_range_max_qp(bpc, buf_i, bpp_i,
vdsc_cfg->native_420);
- /* Calculate range_bgp_offset */
+ /* Calculate range_bpg_offset */
if (bpp <= 6) {
- rc->rc_range_params[buf_i].range_bpg_offset =
ofs_und6[buf_i];
+ range_bpg_offset = ofs_und6[buf_i];
} else if (bpp <= 8) {
res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] -
ofs_und6[buf_i])), 2);
- rc->rc_range_params[buf_i].range_bpg_offset =
- ofs_und6[buf_i]
+ res;
+ range_bpg_offset = ofs_und6[buf_i] + res;
} else if (bpp <= 12) {
- rc->rc_range_params[buf_i].range_bpg_offset =
- ofs_und8[buf_i];
+ range_bpg_offset = ofs_und8[buf_i];
} else if (bpp <= 15)
[Intel-gfx] [PATCH v6 6/8] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
The array of rc_parameters contains a mixture of parameters from DSC 1.1
and DSC 1.2 standards. Split these tow configuration arrays in
preparation to adding more configuration data.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dsc_helper.c | 139 ++
drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
include/drm/display/drm_dsc_helper.h | 7 +-
3 files changed, 129 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c
b/drivers/gpu/drm/display/drm_dsc_helper.c
index acb93d4116e0..f9d01d72c1ff 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -325,10 +325,88 @@ struct rc_parameters_data {
#define DSC_BPP(bpp) ((bpp) << 4)
/*
- * Selected Rate Control Related Parameter Recommended Values
- * from DSC_v1.11 spec & C Model release: DSC_model_20161212
+ * Rate Control Related Parameter Recommended Values from DSC_v1.1 spec prior
+ * to DSC 1.1 fractional bpp underflow SCR (DSC_v1.1_E1.pdf)
+ *
+ * Cross-checked against C Model releases: DSC_model_20161212 and 20210623
*/
-static const struct rc_parameters_data rc_parameters[] = {
+static const struct rc_parameters_data rc_parameters_pre_scr[] = {
+ {
+ .bpp = DSC_BPP(8), .bpc = 8,
+ { 512, 12, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12,
-12 },
+ { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 10,
+ { 512, 12, 6144, 7, 16, 15, 15, {
+ /*
+* DSC model/pre-SCR-cfg has 8 for range_max_qp[0],
however
+* VESA DSC 1.1 Table E-5 sets it to 4.
+*/
+ { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12,
-8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16,
-12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 12,
+ { 512, 12, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11,
16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 8,
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
+ { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13,
15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 10,
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8
},
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16,
-12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 12,
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11,
16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+ },
+ { /* sentinel */ }
+};
+
+/*
+ * Selected Rate Control Related Parameter Recommended Values from DSC v1.2,
v1.2a, v1.2b and
+ * DSC_v1.1_E1 specs.
+ *
+ * Cross-checked against C Model releases: DSC_model_20161212 and 20210623
+ */
+static const struct rc_parameters_data rc_parameters_1_2_444[] = {
{
.bpp = DSC_BPP(6), .bpc = 8,
{ 768, 15, 6144, 3, 13, 11, 11, {
@@ -388,22 +466,18 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 512, 12, 6144, 3, 12, 11, 11, {
{ 0, 4,
[Intel-gfx] [PATCH v6 8/8] drm/display/dsc: add YCbCr 4:2:2 and 4:2:0 RC parameters
Include RC parameters for YCbCr 4:2:2 and 4:2:0 configurations.
Reviewed-by: Suraj Kandpal
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dsc_helper.c | 450 +++
include/drm/display/drm_dsc_helper.h | 2 +
2 files changed, 452 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c
b/drivers/gpu/drm/display/drm_dsc_helper.c
index 6d9bf9ce543b..44876a715e5a 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -748,6 +748,450 @@ static const struct rc_parameters_data
rc_parameters_1_2_444[] = {
{ /* sentinel */ }
};
+/*
+ * Selected Rate Control Related Parameter Recommended Values for 4:2:2 from
+ * DSC v1.2, v1.2a, v1.2b
+ *
+ * Cross-checked against C Model releases: DSC_model_20161212 and 20210623
+ */
+static const struct rc_parameters_data rc_parameters_1_2_422[] = {
+ {
+ .bpp = DSC_BPP(6), .bpc = 8,
+ { 512, 15, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11,
-12 },
+ { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 10,
+ { 512, 15, 6144, 7, 16, 15, 15, {
+ { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12,
-8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15,
-12 },
+ { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 12,
+ { 512, 15, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11,
16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
+ { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 14,
+ { 512, 15, 6144, 15, 24, 23, 23, {
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2
},
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15,
20, -8 },
+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 16,
+ { 512, 15, 6144, 19, 28, 27, 27, {
+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2
},
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19,
24, -8 },
+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
+ { 28, 29, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(7), .bpc = 8,
+ { 410, 15, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10,
-10 },
+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(7), .bpc = 10,
+ { 410, 15, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12,
-8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14,
-10 },
+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(7), .bpc = 12,
+ { 410, 15, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2
},
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11,
16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
+ { 19, 20, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(7), .bpc = 14,
+ { 410,
[Intel-gfx] [PATCH v6 5/8] drm/display/dsc: use flat array for rc_parameters lookup
Next commits are going to add support for additional RC parameter lookup
tables. These tables are going to use different bpp/bpc combinations,
thus it makes little sense to keep the 2d array for RC parameters.
Switch to using the flat array.
Reviewed-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dsc_helper.c | 228 +++
1 file changed, 108 insertions(+), 120 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c
b/drivers/gpu/drm/display/drm_dsc_helper.c
index 122a292bbc8f..acb93d4116e0 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -305,24 +305,6 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config
*vdsc_cfg)
}
EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
-enum ROW_INDEX_BPP {
- ROW_INDEX_6BPP = 0,
- ROW_INDEX_8BPP,
- ROW_INDEX_10BPP,
- ROW_INDEX_12BPP,
- ROW_INDEX_15BPP,
- MAX_ROW_INDEX
-};
-
-enum COLUMN_INDEX_BPC {
- COLUMN_INDEX_8BPC = 0,
- COLUMN_INDEX_10BPC,
- COLUMN_INDEX_12BPC,
- COLUMN_INDEX_14BPC,
- COLUMN_INDEX_16BPC,
- MAX_COLUMN_INDEX
-};
-
struct rc_parameters {
u16 initial_xmit_delay;
u8 first_line_bpg_offset;
@@ -334,21 +316,31 @@ struct rc_parameters {
struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
};
+struct rc_parameters_data {
+ u8 bpp;
+ u8 bpc;
+ struct rc_parameters params;
+};
+
+#define DSC_BPP(bpp) ((bpp) << 4)
+
/*
* Selected Rate Control Related Parameter Recommended Values
* from DSC_v1.11 spec & C Model release: DSC_model_20161212
*/
-static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
+static const struct rc_parameters_data rc_parameters[] = {
{
- /* 6BPP/8BPC */
+ .bpp = DSC_BPP(6), .bpc = 8,
{ 768, 15, 6144, 3, 13, 11, 11, {
{ 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
{ 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
{ 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10,
12, -12 },
{ 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
}
- },
- /* 6BPP/10BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 10,
{ 768, 15, 6144, 7, 17, 15, 15, {
{ 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4
},
{ 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14,
-8 },
@@ -356,8 +348,10 @@ static const struct rc_parameters
rc_parameters[][MAX_COLUMN_INDEX] = {
{ 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
{ 17, 18, -12 }
}
- },
- /* 6BPP/12BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 12,
{ 768, 15, 6144, 11, 21, 19, 19, {
{ 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16,
-4 },
{ 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14,
18, -8 },
@@ -365,8 +359,10 @@ static const struct rc_parameters
rc_parameters[][MAX_COLUMN_INDEX] = {
{ 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
{ 21, 22, -12 }
}
- },
- /* 6BPP/14BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 14,
{ 768, 15, 6144, 15, 25, 23, 23, {
{ 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20,
-4 },
{ 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18,
22, -8 },
@@ -374,8 +370,10 @@ static const struct rc_parameters
rc_parameters[][MAX_COLUMN_INDEX] = {
{ 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
{ 25, 26, -12 }
}
- },
- /* 6BPP/16BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 16,
{ 768, 15, 6144, 19, 29, 27, 27, {
{ 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24,
-4 },
{ 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22,
26, -8 },
@@ -383,18 +381,20 @@ static const struct rc_parameters
rc_parameters[][MAX_COLUMN_INDEX] = {
{ 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
{ 29, 30, -12 }
}
- },
+ }
},
{
- /* 8BPP/8BPC */
+ .bpp = DSC_BPP(8), .bpc = 8,
{ 512, 12, 6144, 3, 12, 11, 11, {
{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
{ 3, 7, -4 }, { 3, 7, -6 }, { 3,
[Intel-gfx] [PATCH v6 7/8] drm/display/dsc: include the rest of pre-SCR parameters
DSC model contains pre-SCR RC parameters for other bpp/bpc combinations,
include them here for completeness. The values were generated from the
'pre_scr_cfg_files_for_reference' files found in DSC models 20210623.
The same fileset is a part of DSC model 20161212.
Reviewed-by: Jessica Zhang
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dsc_helper.c | 72
1 file changed, 72 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c
b/drivers/gpu/drm/display/drm_dsc_helper.c
index f9d01d72c1ff..6d9bf9ce543b 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -331,6 +331,16 @@ struct rc_parameters_data {
* Cross-checked against C Model releases: DSC_model_20161212 and 20210623
*/
static const struct rc_parameters_data rc_parameters_pre_scr[] = {
+ {
+ .bpp = DSC_BPP(6), .bpc = 8,
+ { 683, 15, 6144, 3, 13, 11, 11, {
+ { 0, 2, 0 }, { 1, 4, -2 }, { 3, 6, -2 }, { 4, 6, -4 },
+ { 5, 7, -6 }, { 5, 7, -6 }, { 6, 7, -6 }, { 6, 8, -8 },
+ { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 }, { 10, 12,
-12 },
+ { 10, 13, -12 }, { 12, 14, -12 }, { 15, 15, -12 }
+ }
+ }
+ },
{
.bpp = DSC_BPP(8), .bpc = 8,
{ 512, 12, 6144, 3, 12, 11, 11, {
@@ -366,6 +376,37 @@ static const struct rc_parameters_data
rc_parameters_pre_scr[] = {
}
}
},
+ {
+ .bpp = DSC_BPP(10), .bpc = 8,
+ { 410, 12, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 11,
-10 },
+ { 5, 12, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 10,
+ { 410, 12, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12,
-8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 15,
-10 },
+ { 9, 16, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 12,
+ { 410, 12, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2
},
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11,
16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 19, -10 }, { 13, 20, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+ },
{
.bpp = DSC_BPP(12), .bpc = 8,
{ 341, 15, 2048, 3, 12, 11, 11, {
@@ -397,6 +438,37 @@ static const struct rc_parameters_data
rc_parameters_pre_scr[] = {
}
}
},
+ {
+ .bpp = DSC_BPP(15), .bpc = 8,
+ { 273, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 4, -2 }, { 2, 4, -4 },
+ { 3, 4, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 5, 7, -10
},
+ { 5, 8, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(15), .bpc = 10,
+ { 273, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 8, -2 }, { 6, 8, -4 },
+ { 7, 8, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11,
-10 },
+ { 9, 12, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(15), .bpc = 12,
+ { 273, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4
},
+ { 11, 12, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 16, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+ },
{ /* sentinel */ }
};
--
2.39.2
[Intel-gfx] [PATCH v6 2/8] drm/i915/dsc: move rc_buf_thresh values to common helper
The rc_buf_thresh values are common to all DSC implementations. Move
them to the common helper together with the code to propagate them to
the drm_dsc_config.
Reviewed-by: Jani Nikula
Reviewed-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dsc_helper.c | 35 +++
drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +---
include/drm/display/drm_dsc_helper.h | 1 +
3 files changed, 37 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c
b/drivers/gpu/drm/display/drm_dsc_helper.c
index c869c6e51e2b..be91abe2cfb2 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -270,6 +270,41 @@ void drm_dsc_pps_payload_pack(struct
drm_dsc_picture_parameter_set *pps_payload,
}
EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
+/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
+static const u16 drm_dsc_rc_buf_thresh[] = {
+ 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
+ 7744, 7872, 8000, 8064
+};
+
+/**
+ * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
+ * in accordance with the DSC 1.2 specification.
+ *
+ * @vdsc_cfg: DSC Configuration data partially filled by driver
+ */
+void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
+{
+ int i;
+
+ BUILD_BUG_ON(ARRAY_SIZE(drm_dsc_rc_buf_thresh) !=
+DSC_NUM_BUF_RANGES - 1);
+ BUILD_BUG_ON(ARRAY_SIZE(drm_dsc_rc_buf_thresh) !=
+ARRAY_SIZE(vdsc_cfg->rc_buf_thresh));
+
+ for (i = 0; i < ARRAY_SIZE(drm_dsc_rc_buf_thresh); i++)
+ vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
+
+ /*
+* For 6bpp, RC Buffer threshold 12 and 13 need a different value
+* as per C Model
+*/
+ if (vdsc_cfg->bits_per_pixel == 6 << 4) {
+ vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
+ vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
+ }
+}
+EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
+
/**
* drm_dsc_compute_rc_parameters() - Write rate control
* parameters to the dsc configuration defined in
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 7003ae9f683a..2fd08375bbe3 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -37,12 +37,6 @@ enum COLUMN_INDEX_BPC {
MAX_COLUMN_INDEX
};
-/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
-static const u16 rc_buf_thresh[] = {
- 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
- 7744, 7872, 8000, 8064
-};
-
struct rc_parameters {
u16 initial_xmit_delay;
u8 first_line_bpg_offset;
@@ -543,23 +537,7 @@ int intel_dsc_compute_params(struct intel_crtc_state
*pipe_config)
vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
- for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
- /*
-* six 0s are appended to the lsb of each threshold value
-* internally in h/w.
-* Only 8 bits are allowed for programming RcBufThreshold
-*/
- vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
- }
-
- /*
-* For 6bpp, RC Buffer threshold 12 and 13 need a different value
-* as per C Model
-*/
- if (compressed_bpp == 6) {
- vdsc_cfg->rc_buf_thresh[12] = 0x7C;
- vdsc_cfg->rc_buf_thresh[13] = 0x7D;
- }
+ drm_dsc_set_rc_buf_thresh(vdsc_cfg);
/*
* From XE_LPD onwards we supports compression bpps in steps of 1
diff --git a/include/drm/display/drm_dsc_helper.h
b/include/drm/display/drm_dsc_helper.h
index 8b41edbbabab..706ba1d34742 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header
*pps_header);
int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
+void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
#endif /* _DRM_DSC_HELPER_H_ */
--
2.39.2
[Intel-gfx] [PATCH v6 3/8] drm/i915/dsc: move DSC tables to DRM DSC helper
Move DSC RC tables to DRM DSC helper. No additional code changes
and/or cleanups are a part of this commit, it will be cleaned up in the
followup commits.
Reviewed-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dsc_helper.c | 372 ++
drivers/gpu/drm/i915/display/intel_vdsc.c | 319 +--
include/drm/display/drm_dsc_helper.h | 1 +
3 files changed, 380 insertions(+), 312 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c
b/drivers/gpu/drm/display/drm_dsc_helper.c
index be91abe2cfb2..122a292bbc8f 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -305,6 +305,378 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config
*vdsc_cfg)
}
EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
+enum ROW_INDEX_BPP {
+ ROW_INDEX_6BPP = 0,
+ ROW_INDEX_8BPP,
+ ROW_INDEX_10BPP,
+ ROW_INDEX_12BPP,
+ ROW_INDEX_15BPP,
+ MAX_ROW_INDEX
+};
+
+enum COLUMN_INDEX_BPC {
+ COLUMN_INDEX_8BPC = 0,
+ COLUMN_INDEX_10BPC,
+ COLUMN_INDEX_12BPC,
+ COLUMN_INDEX_14BPC,
+ COLUMN_INDEX_16BPC,
+ MAX_COLUMN_INDEX
+};
+
+struct rc_parameters {
+ u16 initial_xmit_delay;
+ u8 first_line_bpg_offset;
+ u16 initial_offset;
+ u8 flatness_min_qp;
+ u8 flatness_max_qp;
+ u8 rc_quant_incr_limit0;
+ u8 rc_quant_incr_limit1;
+ struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+};
+
+/*
+ * Selected Rate Control Related Parameter Recommended Values
+ * from DSC_v1.11 spec & C Model release: DSC_model_20161212
+ */
+static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
+ {
+ /* 6BPP/8BPC */
+ { 768, 15, 6144, 3, 13, 11, 11, {
+ { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
+ { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
+ { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10,
12, -12 },
+ { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
+ }
+ },
+ /* 6BPP/10BPC */
+ { 768, 15, 6144, 7, 17, 15, 15, {
+ { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4
},
+ { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14,
-8 },
+ { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
+ { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
+ { 17, 18, -12 }
+ }
+ },
+ /* 6BPP/12BPC */
+ { 768, 15, 6144, 11, 21, 19, 19, {
+ { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16,
-4 },
+ { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14,
18, -8 },
+ { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
+ { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
+ { 21, 22, -12 }
+ }
+ },
+ /* 6BPP/14BPC */
+ { 768, 15, 6144, 15, 25, 23, 23, {
+ { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20,
-4 },
+ { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18,
22, -8 },
+ { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
+ { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
+ { 25, 26, -12 }
+ }
+ },
+ /* 6BPP/16BPC */
+ { 768, 15, 6144, 19, 29, 27, 27, {
+ { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24,
-4 },
+ { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22,
26, -8 },
+ { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
+ { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
+ { 29, 30, -12 }
+ }
+ },
+ },
+ {
+ /* 8BPP/8BPC */
+ { 512, 12, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12,
-12 },
+ { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ },
+ /* 8BPP/10BPC */
+ { 512, 12, 6144, 7, 16, 15, 15, {
+ /*
+* DSC model/pre-SCR-cfg has 8 for range_max_qp[0],
however
+* VESA DSC 1.1 Table E-5 sets it to 4.
+*/
+ { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+
[Intel-gfx] [PATCH v6 1/8] drm/i915/dsc: change DSC param tables to follow the DSC model
After cross-checking DSC models (20150914, 20161212, 20210623) change
values in rc_parameters tables to follow config files present inside
the DSC model. Handle two places, where i915 tables diverged from the
model, by patching the rc values in the code.
Note: I left one case uncorrected, 8bpp/10bpc/range_max_qp[0], because
the table in the VESA DSC 1.1 sets it to 4.
Reviewed-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 8e787c13d26d..7003ae9f683a 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -87,7 +87,7 @@ static const struct rc_parameters
rc_parameters[][MAX_COLUMN_INDEX] = {
}
},
/* 6BPP/14BPC */
- { 768, 15, 6144, 15, 25, 23, 27, {
+ { 768, 15, 6144, 15, 25, 23, 23, {
{ 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
{ 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
{ 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
@@ -116,6 +116,10 @@ static const struct rc_parameters
rc_parameters[][MAX_COLUMN_INDEX] = {
},
/* 8BPP/10BPC */
{ 512, 12, 6144, 7, 16, 15, 15, {
+ /*
+* DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
+* VESA DSC 1.1 Table E-5 sets it to 4.
+*/
{ 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
@@ -133,7 +137,7 @@ static const struct rc_parameters
rc_parameters[][MAX_COLUMN_INDEX] = {
},
/* 8BPP/14BPC */
{ 512, 12, 6144, 15, 24, 23, 23, {
- { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
{ 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
{ 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
@@ -598,6 +602,20 @@ int intel_dsc_compute_params(struct intel_crtc_state
*pipe_config)
DSC_RANGE_BPG_OFFSET_MASK;
}
+ if (DISPLAY_VER(dev_priv) < 13) {
+ /*
+* FIXME: verify that the hardware actually needs these
+* modifications rather than them being simple typos.
+*/
+ if (compressed_bpp == 6 &&
+ vdsc_cfg->bits_per_component == 8)
+ vdsc_cfg->rc_quant_incr_limit1 = 23;
+
+ if (compressed_bpp == 8 &&
+ vdsc_cfg->bits_per_component == 14)
+ vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
+ }
+
/*
* BitsPerComponent value determines mux_word_size:
* When BitsPerComponent is less than or 10bpc, muxWordSize will be
equal to
--
2.39.2
[Intel-gfx] [PATCH v6 0/8] drm/i915: move DSC RC tables to drm_dsc_helper.c
Other platforms (msm) will benefit from sharing the DSC config setup functions. This series moves parts of static DSC config data from the i915 driver to the common helpers to be used by other drivers. Note: the RC parameters were cross-checked against config files found in DSC model 2021062, 20161212 (and 20150914). The first patch modifies tables according to those config files, while preserving parameter values using the code. I have not changed one of the values in the pre-SCR config file as it clearly looks like a typo in the config file, considering the table E in DSC 1.1 and in the DSC 1.1 SCR. Chances since v5: - Fixed typo in patch #2 commit message (Marijn) - Reworded/fixed RC table comments to mention DSC standards and C model versions (Suraj) - Renamed enum drm_dsc_param_kind to drm_dsc_param_type (Suraj). Chances since v4: - Rebased on top of drm-intel-next - Cut the first 8 patches of the series to ease merging. The rest of the patches will go afterwards. Chances since v3: - Rebased on top of drm-intel-next - Dropped the msm patch to make patchset fully mergeable through drm-intel - Made drm_dsc_set_const_params() ignore rc_model_size, picked up drm_dsc_set_initial_scale_value() patch by Jessica and switched intel_vdsc.c to use those two helpers. - Added a patch to make i915 actually use rc_tgt_offset_high, rc_tgt_offset_low and rc_edge_factor from struct drm_dsc_config. Chances since v2: - Rebased on top of drm-intel-next Dmitry Baryshkov (8): drm/i915/dsc: change DSC param tables to follow the DSC model drm/i915/dsc: move rc_buf_thresh values to common helper drm/i915/dsc: move DSC tables to DRM DSC helper drm/i915/dsc: stop using interim structure for calculated params drm/display/dsc: use flat array for rc_parameters lookup drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters drm/display/dsc: include the rest of pre-SCR parameters drm/display/dsc: add YCbCr 4:2:2 and 4:2:0 RC parameters drivers/gpu/drm/display/drm_dsc_helper.c | 1006 + drivers/gpu/drm/i915/display/intel_vdsc.c | 443 + include/drm/display/drm_dsc_helper.h |9 + 3 files changed, 1062 insertions(+), 396 deletions(-) -- 2.39.2
Re: [Intel-gfx] [Freedreno] [PATCH v5 6/8] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
On 16/05/2023 21:46, Kandpal, Suraj wrote:
The array of rc_parameters contains a mixture of parameters from DSC 1.1
and DSC 1.2 standards. Split these tow configuration arrays in preparation to
adding more configuration data.
Hi ,
Needed to add some more comments apart from the previous ones already given
[skipped]
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index d4340b18c18d..bd9116d2cd76 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -226,7 +226,15 @@ int intel_dsc_compute_params(struct
intel_crtc_state *pipe_config)
if (DISPLAY_VER(dev_priv) >= 13) {
calculate_rc_params(vdsc_cfg);
} else {
- ret = drm_dsc_setup_rc_params(vdsc_cfg);
+ if ((compressed_bpp == 8 ||
+compressed_bpp == 12) &&
+ (vdsc_cfg->bits_per_component == 8 ||
+vdsc_cfg->bits_per_component == 10 ||
+vdsc_cfg->bits_per_component == 12))
+ ret = drm_dsc_setup_rc_params(vdsc_cfg,
DRM_DSC_1_1_PRE_SCR);
+ else
+ ret = drm_dsc_setup_rc_params(vdsc_cfg,
DRM_DSC_1_2_444);
+
I do not think this kind of assignment works as you will also be adding
DRM_DSC_1_2_422 and DRM_DSC_1_2_420 in further patches and AFAICS
There is no where in patch 8 that you have accounted for when 422 or 420 will
be used.
Maybe you can add an if case inside the else block to check
pipe_config->output_format
to pass the rc_param_data in patch 8
I don't think this is necessary for now. The driver doesn't support YUV
422. The YUV 420 is supported only for DISPLAY_VER(dev_priv) >= 14,
however these helpers are only used for DISPLAY_VER(dev_priv) < 13.
I did not move RC calculation to drm_dsc_helpers.c (yet ?), which is
used for DISPLAY_VER >= 13.
Regards,
Suraj Kandpal
if (ret)
return ret;
diff --git a/include/drm/display/drm_dsc_helper.h
b/include/drm/display/drm_dsc_helper.h
index 1681791f65a5..c634bb2935d3 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -10,12 +10,17 @@
#include
+enum drm_dsc_params_kind {
+ DRM_DSC_1_2_444,
+ DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */ };
+
void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header); int
drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set
*pps_sdp,
const struct drm_dsc_config *dsc_cfg); void
drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg); -int
drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum
+drm_dsc_params_kind kind);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
#endif /* _DRM_DSC_HELPER_H_ */
--
2.39.2
--
With best wishes
Dmitry
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,DO_NOT_MERGE,1/2] drm/i915/mtl: do not enable render power-gating on MTL
== Series Details == Series: series starting with [CI,DO_NOT_MERGE,1/2] drm/i915/mtl: do not enable render power-gating on MTL URL : https://patchwork.freedesktop.org/series/117839/ State : warning == Summary == Error: dim checkpatch failed 00ac40784ada drm/i915/mtl: do not enable render power-gating on MTL -:11: WARNING:COMMIT_LOG_USE_LINK: Unknown link reference 'References:', use 'Link:' or 'Closes:' instead #11: References: https://gitlab.freedesktop.org/drm/intel/-/issues/4983 -:29: ERROR:CODE_INDENT: code indent should use tabs where possible #29: FILE: drivers/gpu/drm/i915/gt/intel_rc6.c:125: +^I IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))$ total: 1 errors, 1 warnings, 0 checks, 14 lines checked d2a0fe552d4d drm/i915/gt: do not enable render and media power-gating on RPL-S -:10: WARNING:COMMIT_LOG_USE_LINK: Unknown link reference 'References:', use 'Link:' or 'Closes:' instead #10: References: https://gitlab.freedesktop.org/drm/intel/-/issues/4983 total: 0 errors, 1 warnings, 0 checks, 9 lines checked
Re: [Intel-gfx] [PATCH] drm/i915/pmu: Change bitmask of enabled events to u32
On Tue, May 16, 2023 at 03:13:01PM -0700, Umesh Nerlige Ramappa wrote:
On Tue, May 16, 2023 at 10:24:45AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Having it as u64 was a confusing (but harmless) mistake.
Also add some asserts to make sure the internal field does not overflow
in the future.
Signed-off-by: Tvrtko Ursulin
Cc: Ashutosh Dixit
Cc: Umesh Nerlige Ramappa
---
I am not entirely sure the __builtin_constant_p->BUILD_BUG_ON branch will
work with all compilers. Lets see...
Compile tested only.
---
drivers/gpu/drm/i915/i915_pmu.c | 32 ++--
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 7ece883a7d95..8736b3418f88 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -50,7 +50,7 @@ static u8 engine_event_instance(struct perf_event *event)
return (event->attr.config >> I915_PMU_SAMPLE_BITS) & 0xff;
}
-static bool is_engine_config(u64 config)
+static bool is_engine_config(const u64 config)
{
return config < __I915_PMU_OTHER(0);
}
@@ -82,15 +82,28 @@ static unsigned int other_bit(const u64 config)
static unsigned int config_bit(const u64 config)
{
+ unsigned int bit;
+
if (is_engine_config(config))
- return engine_config_sample(config);
+ bit = engine_config_sample(config);
else
- return other_bit(config);
+ bit = other_bit(config);
+
+ if (__builtin_constant_p(config))
+ BUILD_BUG_ON(bit >
+BITS_PER_TYPE(typeof_member(struct i915_pmu,
+enable)) - 1);
+ else
+ WARN_ON_ONCE(bit >
+BITS_PER_TYPE(typeof_member(struct i915_pmu,
+enable)) - 1);
The else is firing for the INTERRUPT event because event_bit() also
calls config_bit(). It would be best to move this check to
config_mask() and leave this function as is.
I posted the modified version here -
https://patchwork.freedesktop.org/patch/537361/?series=117843=1 as
part of the MTL PMU series so that it Tests out with IGT patches.
Thanks,
Umesh
Thanks,
Umesh
+
+ return bit;
}
-static u64 config_mask(u64 config)
+static u32 config_mask(const u64 config)
{
- return BIT_ULL(config_bit(config));
+ return BIT(config_bit(config));
}
static bool is_engine_event(struct perf_event *event)
@@ -633,11 +646,10 @@ static void i915_pmu_enable(struct perf_event *event)
{
struct drm_i915_private *i915 =
container_of(event->pmu, typeof(*i915), pmu.base);
+ const unsigned int bit = event_bit(event);
struct i915_pmu *pmu = >pmu;
unsigned long flags;
- unsigned int bit;
- bit = event_bit(event);
if (bit == -1)
goto update;
@@ -651,7 +663,7 @@ static void i915_pmu_enable(struct perf_event *event)
GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count));
GEM_BUG_ON(pmu->enable_count[bit] == ~0);
- pmu->enable |= BIT_ULL(bit);
+ pmu->enable |= BIT(bit);
pmu->enable_count[bit]++;
/*
@@ -698,7 +710,7 @@ static void i915_pmu_disable(struct perf_event *event)
{
struct drm_i915_private *i915 =
container_of(event->pmu, typeof(*i915), pmu.base);
- unsigned int bit = event_bit(event);
+ const unsigned int bit = event_bit(event);
struct i915_pmu *pmu = >pmu;
unsigned long flags;
@@ -734,7 +746,7 @@ static void i915_pmu_disable(struct perf_event *event)
* bitmask when the last listener on an event goes away.
*/
if (--pmu->enable_count[bit] == 0) {
- pmu->enable &= ~BIT_ULL(bit);
+ pmu->enable &= ~BIT(bit);
pmu->timer_enabled &= pmu_needs_timer(pmu, true);
}
--
2.39.2
[Intel-gfx] [PATCH v5 4/7] drm/i915/pmu: Transform PMU parking code to be GT based
From: Tvrtko Ursulin
Trivial prep work for full multi-tile enablement later.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Vinay Belgaumkar
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++--
drivers/gpu/drm/i915/i915_pmu.c | 16
drivers/gpu/drm/i915/i915_pmu.h | 9 +
3 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index e02cb90723ae..c2e69bafd02b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -87,7 +87,7 @@ static int __gt_unpark(struct intel_wakeref *wf)
intel_rc6_unpark(>rc6);
intel_rps_unpark(>rps);
- i915_pmu_gt_unparked(i915);
+ i915_pmu_gt_unparked(gt);
intel_guc_busyness_unpark(gt);
intel_gt_unpark_requests(gt);
@@ -109,7 +109,7 @@ static int __gt_park(struct intel_wakeref *wf)
intel_guc_busyness_park(gt);
i915_vma_parked(gt);
- i915_pmu_gt_parked(i915);
+ i915_pmu_gt_parked(gt);
intel_rps_park(>rps);
intel_rc6_park(>rc6);
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 6d594f67f365..890693fdaf9e 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -228,11 +228,11 @@ static void init_rc6(struct i915_pmu *pmu)
}
}
-static void park_rc6(struct drm_i915_private *i915)
+static void park_rc6(struct intel_gt *gt)
{
- struct i915_pmu *pmu = >pmu;
+ struct i915_pmu *pmu = >i915->pmu;
- pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(to_gt(i915));
+ pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(gt);
pmu->sleep_last = ktime_get_raw();
}
@@ -247,16 +247,16 @@ static void __i915_pmu_maybe_start_timer(struct i915_pmu
*pmu)
}
}
-void i915_pmu_gt_parked(struct drm_i915_private *i915)
+void i915_pmu_gt_parked(struct intel_gt *gt)
{
- struct i915_pmu *pmu = >pmu;
+ struct i915_pmu *pmu = >i915->pmu;
if (!pmu->base.event_init)
return;
spin_lock_irq(>lock);
- park_rc6(i915);
+ park_rc6(gt);
/*
* Signal sampling timer to stop if only engine events are enabled and
@@ -267,9 +267,9 @@ void i915_pmu_gt_parked(struct drm_i915_private *i915)
spin_unlock_irq(>lock);
}
-void i915_pmu_gt_unparked(struct drm_i915_private *i915)
+void i915_pmu_gt_unparked(struct intel_gt *gt)
{
- struct i915_pmu *pmu = >pmu;
+ struct i915_pmu *pmu = >i915->pmu;
if (!pmu->base.event_init)
return;
diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
index c30f43319a78..a686fd7ccedf 100644
--- a/drivers/gpu/drm/i915/i915_pmu.h
+++ b/drivers/gpu/drm/i915/i915_pmu.h
@@ -13,6 +13,7 @@
#include
struct drm_i915_private;
+struct intel_gt;
/*
* Non-engine events that we need to track enabled-disabled transition and
@@ -151,15 +152,15 @@ int i915_pmu_init(void);
void i915_pmu_exit(void);
void i915_pmu_register(struct drm_i915_private *i915);
void i915_pmu_unregister(struct drm_i915_private *i915);
-void i915_pmu_gt_parked(struct drm_i915_private *i915);
-void i915_pmu_gt_unparked(struct drm_i915_private *i915);
+void i915_pmu_gt_parked(struct intel_gt *gt);
+void i915_pmu_gt_unparked(struct intel_gt *gt);
#else
static inline int i915_pmu_init(void) { return 0; }
static inline void i915_pmu_exit(void) {}
static inline void i915_pmu_register(struct drm_i915_private *i915) {}
static inline void i915_pmu_unregister(struct drm_i915_private *i915) {}
-static inline void i915_pmu_gt_parked(struct drm_i915_private *i915) {}
-static inline void i915_pmu_gt_unparked(struct drm_i915_private *i915) {}
+static inline void i915_pmu_gt_parked(struct intel_gt *gt) {}
+static inline void i915_pmu_gt_unparked(struct intel_gt *gt) {}
#endif
#endif
--
2.36.1
[Intel-gfx] [PATCH v5 5/7] drm/i915/pmu: Add reference counting to the sampling timer
From: Tvrtko Ursulin
We do not want to have timers per tile and waste CPU cycles and energy via
multiple wake-up sources, for a relatively un-important task of PMU
sampling, so keeping a single timer works well. But we also do not want
the first GT which goes idle to turn off the timer.
Add some reference counting, via a mask of unparked GTs, to solve this.
v2: Drop the check for unparked in i915_sample (Ashutosh)
v3: Revert v2 (Tvrtko)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_pmu.c | 12 ++--
drivers/gpu/drm/i915/i915_pmu.h | 4
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 890693fdaf9e..ecb57a94143e 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -262,7 +262,9 @@ void i915_pmu_gt_parked(struct intel_gt *gt)
* Signal sampling timer to stop if only engine events are enabled and
* GPU went idle.
*/
- pmu->timer_enabled = pmu_needs_timer(pmu, false);
+ pmu->unparked &= ~BIT(gt->info.id);
+ if (pmu->unparked == 0)
+ pmu->timer_enabled = pmu_needs_timer(pmu, false);
spin_unlock_irq(>lock);
}
@@ -279,7 +281,10 @@ void i915_pmu_gt_unparked(struct intel_gt *gt)
/*
* Re-enable sampling timer when GPU goes active.
*/
- __i915_pmu_maybe_start_timer(pmu);
+ if (pmu->unparked == 0)
+ __i915_pmu_maybe_start_timer(pmu);
+
+ pmu->unparked |= BIT(gt->info.id);
spin_unlock_irq(>lock);
}
@@ -449,6 +454,9 @@ static enum hrtimer_restart i915_sample(struct hrtimer
*hrtimer)
*/
for_each_gt(gt, i915, i) {
+ if (!(pmu->unparked & BIT(i)))
+ continue;
+
engines_sample(gt, period_ns);
if (i == 0) /* FIXME */
diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
index a686fd7ccedf..3a811266ac6a 100644
--- a/drivers/gpu/drm/i915/i915_pmu.h
+++ b/drivers/gpu/drm/i915/i915_pmu.h
@@ -76,6 +76,10 @@ struct i915_pmu {
* @lock: Lock protecting enable mask and ref count handling.
*/
spinlock_t lock;
+ /**
+* @unparked: GT unparked mask.
+*/
+ unsigned int unparked;
/**
* @timer: Timer for internal i915 PMU sampling.
*/
--
2.36.1
[Intel-gfx] [PATCH v5 6/7] drm/i915/pmu: Prepare for multi-tile non-engine counters
From: Tvrtko Ursulin
Reserve some bits in the counter config namespace which will carry the
tile id and prepare the code to handle this.
No per tile counters have been added yet.
v2:
- Fix checkpatch issues
- Use 4 bits for gt id in non-engine counters. Drop FIXME.
- Set MAX GTs to 4. Drop FIXME.
v3: (Ashutosh, Tvrtko)
- Drop BUG_ON that would never fire
- Make enable u64
- Pull in some code from next patch
v4: Set I915_PMU_MAX_GTS to 2 (Tvrtko)
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_pmu.c | 148 +++-
drivers/gpu/drm/i915/i915_pmu.h | 11 ++-
include/uapi/drm/i915_drm.h | 17 +++-
3 files changed, 129 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index ecb57a94143e..dc1ca3a15ff6 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -56,11 +56,21 @@ static bool is_engine_config(const u64 config)
return config < __I915_PMU_OTHER(0);
}
+static unsigned int config_gt_id(const u64 config)
+{
+ return config >> __I915_PMU_GT_SHIFT;
+}
+
+static u64 config_counter(const u64 config)
+{
+ return config & ~(~0ULL << __I915_PMU_GT_SHIFT);
+}
+
static unsigned int other_bit(const u64 config)
{
unsigned int val;
- switch (config) {
+ switch (config_counter(config)) {
case I915_PMU_ACTUAL_FREQUENCY:
val = __I915_PMU_ACTUAL_FREQUENCY_ENABLED;
break;
@@ -78,7 +88,9 @@ static unsigned int other_bit(const u64 config)
return -1;
}
- return I915_ENGINE_SAMPLE_COUNT + val;
+ return I915_ENGINE_SAMPLE_COUNT +
+ config_gt_id(config) * __I915_PMU_TRACKED_EVENT_COUNT +
+ val;
}
static unsigned int config_bit(const u64 config)
@@ -115,10 +127,22 @@ static unsigned int event_bit(struct perf_event *event)
return config_bit(event->attr.config);
}
+static u64 frequency_enabled_mask(void)
+{
+ unsigned int i;
+ u64 mask = 0;
+
+ for (i = 0; i < I915_PMU_MAX_GTS; i++)
+ mask |= config_mask(__I915_PMU_ACTUAL_FREQUENCY(i)) |
+ config_mask(__I915_PMU_REQUESTED_FREQUENCY(i));
+
+ return mask;
+}
+
static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active)
{
struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
- u32 enable;
+ u64 enable;
/*
* Only some counters need the sampling timer.
@@ -131,9 +155,7 @@ static bool pmu_needs_timer(struct i915_pmu *pmu, bool
gpu_active)
* Mask out all the ones which do not need the timer, or in
* other words keep all the ones that could need the timer.
*/
- enable &= config_mask(I915_PMU_ACTUAL_FREQUENCY) |
- config_mask(I915_PMU_REQUESTED_FREQUENCY) |
- ENGINE_SAMPLE_MASK;
+ enable &= frequency_enabled_mask() | ENGINE_SAMPLE_MASK;
/*
* When the GPU is idle per-engine counters do not need to be
@@ -175,9 +197,37 @@ static inline s64 ktime_since_raw(const ktime_t kt)
return ktime_to_ns(ktime_sub(ktime_get_raw(), kt));
}
+static unsigned int
+__sample_idx(struct i915_pmu *pmu, unsigned int gt_id, int sample)
+{
+ unsigned int idx = gt_id * __I915_NUM_PMU_SAMPLERS + sample;
+
+ GEM_BUG_ON(idx >= ARRAY_SIZE(pmu->sample));
+
+ return idx;
+}
+
+static u64 read_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample)
+{
+ return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur;
+}
+
+static void
+store_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample, u64 val)
+{
+ pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val;
+}
+
+static void
+add_sample_mult(struct i915_pmu *pmu, unsigned int gt_id, int sample, u32 val,
u32 mul)
+{
+ pmu->sample[__sample_idx(pmu, gt_id, sample)].cur += mul_u32_u32(val,
mul);
+}
+
static u64 get_rc6(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
+ const unsigned int gt_id = gt->info.id;
struct i915_pmu *pmu = >pmu;
unsigned long flags;
bool awake = false;
@@ -192,7 +242,7 @@ static u64 get_rc6(struct intel_gt *gt)
spin_lock_irqsave(>lock, flags);
if (awake) {
- pmu->sample[__I915_SAMPLE_RC6].cur = val;
+ store_sample(pmu, gt_id, __I915_SAMPLE_RC6, val);
} else {
/*
* We think we are runtime suspended.
@@ -201,14 +251,14 @@ static u64 get_rc6(struct intel_gt *gt)
* on top of the last known real value, as the approximated RC6
* counter value.
*/
- val = ktime_since_raw(pmu->sleep_last);
- val += pmu->sample[__I915_SAMPLE_RC6].cur;
+ val = ktime_since_raw(pmu->sleep_last[gt_id]);
+
[Intel-gfx] [PATCH v5 2/7] drm/i915/pmu: Support PMU for all engines
From: Tvrtko Ursulin
Given how the metrics are already exported, we also need to run sampling
over engines from all GTs.
Problem of GT frequencies is left for later.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 96543dce2db1..9edf87ee5d10 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -10,6 +10,7 @@
#include "gt/intel_engine_pm.h"
#include "gt/intel_engine_regs.h"
#include "gt/intel_engine_user.h"
+#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_gt_regs.h"
#include "gt/intel_rc6.h"
@@ -425,8 +426,9 @@ static enum hrtimer_restart i915_sample(struct hrtimer
*hrtimer)
struct drm_i915_private *i915 =
container_of(hrtimer, struct drm_i915_private, pmu.timer);
struct i915_pmu *pmu = >pmu;
- struct intel_gt *gt = to_gt(i915);
unsigned int period_ns;
+ struct intel_gt *gt;
+ unsigned int i;
ktime_t now;
if (!READ_ONCE(pmu->timer_enabled))
@@ -442,8 +444,13 @@ static enum hrtimer_restart i915_sample(struct hrtimer
*hrtimer)
* grabbing the forcewake. However the potential error from timer call-
* back delay greatly dominates this so we keep it simple.
*/
- engines_sample(gt, period_ns);
- frequency_sample(gt, period_ns);
+
+ for_each_gt(gt, i915, i) {
+ engines_sample(gt, period_ns);
+
+ if (i == 0) /* FIXME */
+ frequency_sample(gt, period_ns);
+ }
hrtimer_forward(hrtimer, now, ns_to_ktime(PERIOD));
--
2.36.1
[Intel-gfx] [PATCH v5 7/7] drm/i915/pmu: Export counters from all tiles
From: Tvrtko Ursulin
Start exporting frequency and RC6 counters from all tiles.
Existing counters keep their names and config values and new one use the
namespace added in the previous patch, with the "-gtN" added to their
names.
Interrupts counter is an odd one off. Because it is the global device
counters (not only GT) we choose not to add per tile versions for now.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Aravind Iddamsetty
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 82 ++---
1 file changed, 55 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index dc1ca3a15ff6..dbb24c0c6093 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -940,11 +940,20 @@ static const struct attribute_group
i915_pmu_cpumask_attr_group = {
.attrs = i915_cpumask_attrs,
};
-#define __event(__config, __name, __unit) \
+#define __event(__counter, __name, __unit) \
{ \
- .config = (__config), \
+ .counter = (__counter), \
.name = (__name), \
.unit = (__unit), \
+ .global = false, \
+}
+
+#define __global_event(__counter, __name, __unit) \
+{ \
+ .counter = (__counter), \
+ .name = (__name), \
+ .unit = (__unit), \
+ .global = true, \
}
#define __engine_event(__sample, __name) \
@@ -983,15 +992,16 @@ create_event_attributes(struct i915_pmu *pmu)
{
struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
static const struct {
- u64 config;
+ unsigned int counter;
const char *name;
const char *unit;
+ bool global;
} events[] = {
- __event(I915_PMU_ACTUAL_FREQUENCY, "actual-frequency", "M"),
- __event(I915_PMU_REQUESTED_FREQUENCY, "requested-frequency",
"M"),
- __event(I915_PMU_INTERRUPTS, "interrupts", NULL),
- __event(I915_PMU_RC6_RESIDENCY, "rc6-residency", "ns"),
- __event(I915_PMU_SOFTWARE_GT_AWAKE_TIME,
"software-gt-awake-time", "ns"),
+ __event(0, "actual-frequency", "M"),
+ __event(1, "requested-frequency", "M"),
+ __global_event(2, "interrupts", NULL),
+ __event(3, "rc6-residency", "ns"),
+ __event(4, "software-gt-awake-time", "ns"),
};
static const struct {
enum drm_i915_pmu_engine_sample sample;
@@ -1006,12 +1016,17 @@ create_event_attributes(struct i915_pmu *pmu)
struct i915_ext_attribute *i915_attr = NULL, *i915_iter;
struct attribute **attr = NULL, **attr_iter;
struct intel_engine_cs *engine;
- unsigned int i;
+ struct intel_gt *gt;
+ unsigned int i, j;
/* Count how many counters we will be exposing. */
- for (i = 0; i < ARRAY_SIZE(events); i++) {
- if (!config_status(i915, events[i].config))
- count++;
+ for_each_gt(gt, i915, j) {
+ for (i = 0; i < ARRAY_SIZE(events); i++) {
+ u64 config = ___I915_PMU_OTHER(j, events[i].counter);
+
+ if (!config_status(i915, config))
+ count++;
+ }
}
for_each_uabi_engine(engine, i915) {
@@ -1041,26 +1056,39 @@ create_event_attributes(struct i915_pmu *pmu)
attr_iter = attr;
/* Initialize supported non-engine counters. */
- for (i = 0; i < ARRAY_SIZE(events); i++) {
- char *str;
-
- if (config_status(i915, events[i].config))
- continue;
-
- str = kstrdup(events[i].name, GFP_KERNEL);
- if (!str)
- goto err;
+ for_each_gt(gt, i915, j) {
+ for (i = 0; i < ARRAY_SIZE(events); i++) {
+ u64 config = ___I915_PMU_OTHER(j, events[i].counter);
+ char *str;
- *attr_iter++ = _iter->attr.attr;
- i915_iter = add_i915_attr(i915_iter, str, events[i].config);
+ if (config_status(i915, config))
+ continue;
- if (events[i].unit) {
- str = kasprintf(GFP_KERNEL, "%s.unit", events[i].name);
+ if (events[i].global || !HAS_EXTRA_GT_LIST(i915))
+ str = kstrdup(events[i].name, GFP_KERNEL);
+ else
+ str = kasprintf(GFP_KERNEL, "%s-gt%u",
+ events[i].name, j);
if (!str)
goto err;
- *attr_iter++ = _iter->attr.attr;
- pmu_iter = add_pmu_attr(pmu_iter, str, events[i].unit);
+
[Intel-gfx] [PATCH v5 3/7] drm/i915/pmu: Skip sampling engines with no enabled counters
From: Tvrtko Ursulin
As we have more and more engines do not waste time sampling the ones no-
one is monitoring.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 9edf87ee5d10..6d594f67f365 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -350,6 +350,9 @@ engines_sample(struct intel_gt *gt, unsigned int period_ns)
return;
for_each_engine(engine, gt, id) {
+ if (!engine->pmu.enable)
+ continue;
+
if (!intel_engine_pm_get_if_awake(engine))
continue;
--
2.36.1
[Intel-gfx] [PATCH v5 1/7] drm/i915/pmu: Change bitmask of enabled events to u32
From: Tvrtko Ursulin
Having it as u64 was a confusing (but harmless) mistake.
Also add some asserts to make sure the internal field does not overflow
in the future.
v2: Fix WARN_ON firing for INTERRUPT event (Umesh)
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Umesh Nerlige Ramappa
Cc: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_pmu.c | 26 ++
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 7ece883a7d95..96543dce2db1 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -50,7 +50,7 @@ static u8 engine_event_instance(struct perf_event *event)
return (event->attr.config >> I915_PMU_SAMPLE_BITS) & 0xff;
}
-static bool is_engine_config(u64 config)
+static bool is_engine_config(const u64 config)
{
return config < __I915_PMU_OTHER(0);
}
@@ -88,9 +88,20 @@ static unsigned int config_bit(const u64 config)
return other_bit(config);
}
-static u64 config_mask(u64 config)
+static u32 config_mask(const u64 config)
{
- return BIT_ULL(config_bit(config));
+ unsigned int bit = config_bit(config);
+
+ if (__builtin_constant_p(config))
+ BUILD_BUG_ON(bit >
+BITS_PER_TYPE(typeof_member(struct i915_pmu,
+enable)) - 1);
+ else
+ WARN_ON_ONCE(bit >
+BITS_PER_TYPE(typeof_member(struct i915_pmu,
+enable)) - 1);
+
+ return BIT(config_bit(config));
}
static bool is_engine_event(struct perf_event *event)
@@ -633,11 +644,10 @@ static void i915_pmu_enable(struct perf_event *event)
{
struct drm_i915_private *i915 =
container_of(event->pmu, typeof(*i915), pmu.base);
+ const unsigned int bit = event_bit(event);
struct i915_pmu *pmu = >pmu;
unsigned long flags;
- unsigned int bit;
- bit = event_bit(event);
if (bit == -1)
goto update;
@@ -651,7 +661,7 @@ static void i915_pmu_enable(struct perf_event *event)
GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count));
GEM_BUG_ON(pmu->enable_count[bit] == ~0);
- pmu->enable |= BIT_ULL(bit);
+ pmu->enable |= BIT(bit);
pmu->enable_count[bit]++;
/*
@@ -698,7 +708,7 @@ static void i915_pmu_disable(struct perf_event *event)
{
struct drm_i915_private *i915 =
container_of(event->pmu, typeof(*i915), pmu.base);
- unsigned int bit = event_bit(event);
+ const unsigned int bit = event_bit(event);
struct i915_pmu *pmu = >pmu;
unsigned long flags;
@@ -734,7 +744,7 @@ static void i915_pmu_disable(struct perf_event *event)
* bitmask when the last listener on an event goes away.
*/
if (--pmu->enable_count[bit] == 0) {
- pmu->enable &= ~BIT_ULL(bit);
+ pmu->enable &= ~BIT(bit);
pmu->timer_enabled &= pmu_needs_timer(pmu, true);
}
--
2.36.1
[Intel-gfx] [PATCH v5 0/7] Add MTL PMU support for multi-gt
With MTL, frequency and rc6 counters are specific to a gt. Export these counters via gt-specific events to the user space. v2: Remove aggregation support from kernel v3: Review comments (Ashutosh, Tvrtko) v4: - Include R-b for 6/6 - Add Test-with - Fix versioning info in cover letter v5: - Include "drm/i915/pmu: Change bitmask of enabled events to u32" Signed-off-by: Umesh Nerlige Ramappa Test-with: 20230513022234.2832233-1-umesh.nerlige.rama...@intel.com Tvrtko Ursulin (7): drm/i915/pmu: Change bitmask of enabled events to u32 drm/i915/pmu: Support PMU for all engines drm/i915/pmu: Skip sampling engines with no enabled counters drm/i915/pmu: Transform PMU parking code to be GT based drm/i915/pmu: Add reference counting to the sampling timer drm/i915/pmu: Prepare for multi-tile non-engine counters drm/i915/pmu: Export counters from all tiles drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +- drivers/gpu/drm/i915/i915_pmu.c | 292 ++ drivers/gpu/drm/i915/i915_pmu.h | 24 ++- include/uapi/drm/i915_drm.h | 17 +- 4 files changed, 240 insertions(+), 97 deletions(-) -- 2.36.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Allow user to set cache at BO creation (rev9)
== Series Details ==
Series: drm/i915: Allow user to set cache at BO creation (rev9)
URL : https://patchwork.freedesktop.org/series/116870/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13154 -> Patchwork_116870v9
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v9/index.html
Participating hosts (38 -> 37)
--
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_116870v9 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@reset:
- bat-rpls-2: [PASS][1] -> [ABORT][2] ([i915#4983] / [i915#7461] /
[i915#7913] / [i915#8347])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-rpls-2/igt@i915_selftest@l...@reset.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v9/bat-rpls-2/igt@i915_selftest@l...@reset.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][3] ([i915#1845] / [i915#5354]) +2
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v9/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
- bat-dg2-8: [PASS][4] -> [FAIL][5] ([i915#7932]) +1 similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v9/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
Possible fixes
* igt@i915_selftest@live@migrate:
- bat-dg2-11: [DMESG-WARN][6] ([i915#7699]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-dg2-11/igt@i915_selftest@l...@migrate.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v9/bat-dg2-11/igt@i915_selftest@l...@migrate.html
* igt@i915_selftest@live@requests:
- {bat-mtlp-8}: [ABORT][8] ([i915#4983] / [i915#7920]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-mtlp-8/igt@i915_selftest@l...@requests.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v9/bat-mtlp-8/igt@i915_selftest@l...@requests.html
* igt@i915_selftest@live@slpc:
- bat-rpls-1: [DMESG-WARN][10] ([i915#6367]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-rpls-1/igt@i915_selftest@l...@slpc.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v9/bat-rpls-1/igt@i915_selftest@l...@slpc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
Build changes
-
* Linux: CI_DRM_13154 -> Patchwork_116870v9
CI-20190529: 20190529
CI_DRM_13154: d04e82f5245c285e7ae36955d89c4d217d04d664 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7292: 9d9475ffd3b5ae18fd8ec120595385f6c562f249 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116870v9: d04e82f5245c285e7ae36955d89c4d217d04d664 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
83771dfc5043 drm/i915: Allow user to set cache at BO creation
e46d6ff10c8b drm/i915/mtl: end support for set caching ioctl
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v9/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Allow user to set cache at BO creation (rev9)
== Series Details == Series: drm/i915: Allow user to set cache at BO creation (rev9) URL : https://patchwork.freedesktop.org/series/116870/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc/slpc: Disable rps_boost debugfs (rev2)
== Series Details ==
Series: drm/i915/guc/slpc: Disable rps_boost debugfs (rev2)
URL : https://patchwork.freedesktop.org/series/117711/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13154 -> Patchwork_117711v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v2/index.html
Participating hosts (38 -> 36)
--
Missing(2): fi-kbl-soraka fi-snb-2520m
Known issues
Here are the changes found in Patchwork_117711v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@gt_engines:
- bat-atsm-1: [PASS][1] -> [FAIL][2] ([i915#6268])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-atsm-1/igt@i915_selftest@live@gt_engines.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v2/bat-atsm-1/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@requests:
- bat-rpls-2: [PASS][3] -> [ABORT][4] ([i915#7913] / [i915#7982])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-rpls-2/igt@i915_selftest@l...@requests.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v2/bat-rpls-2/igt@i915_selftest@l...@requests.html
* igt@i915_selftest@live@reset:
- bat-rpls-1: [PASS][5] -> [ABORT][6] ([i915#4983] / [i915#7461] /
[i915#8347] / [i915#8384])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-rpls-1/igt@i915_selftest@l...@reset.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v2/bat-rpls-1/igt@i915_selftest@l...@reset.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-1:
- bat-dg2-8: [PASS][7] -> [FAIL][8] ([i915#7932])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-c-dp-1.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v2/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-c-dp-1.html
Possible fixes
* igt@i915_selftest@live@migrate:
- bat-dg2-11: [DMESG-WARN][9] ([i915#7699]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-dg2-11/igt@i915_selftest@l...@migrate.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v2/bat-dg2-11/igt@i915_selftest@l...@migrate.html
* igt@i915_selftest@live@requests:
- {bat-mtlp-8}: [ABORT][11] ([i915#4983] / [i915#7920]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-mtlp-8/igt@i915_selftest@l...@requests.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v2/bat-mtlp-8/igt@i915_selftest@l...@requests.html
- {bat-mtlp-6}: [ABORT][13] ([i915#4983] / [i915#7920]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-mtlp-6/igt@i915_selftest@l...@requests.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v2/bat-mtlp-6/igt@i915_selftest@l...@requests.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7982]: https://gitlab.freedesktop.org/drm/intel/issues/7982
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
[i915#8384]: https://gitlab.freedesktop.org/drm/intel/issues/8384
Build changes
-
* Linux: CI_DRM_13154 -> Patchwork_117711v2
CI-20190529: 20190529
CI_DRM_13154: d04e82f5245c285e7ae36955d89c4d217d04d664 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7292: 9d9475ffd3b5ae18fd8ec120595385f6c562f249 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_117711v2: d04e82f5245c285e7ae36955d89c4d217d04d664 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
2edfd2dd7718 drm/i915/guc/slpc: Disable rps_boost debugfs
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v2/index.html
Re: [Intel-gfx] [PATCH] drm/i915/pmu: Change bitmask of enabled events to u32
On Tue, May 16, 2023 at 10:24:45AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Having it as u64 was a confusing (but harmless) mistake.
Also add some asserts to make sure the internal field does not overflow
in the future.
Signed-off-by: Tvrtko Ursulin
Cc: Ashutosh Dixit
Cc: Umesh Nerlige Ramappa
---
I am not entirely sure the __builtin_constant_p->BUILD_BUG_ON branch will
work with all compilers. Lets see...
Compile tested only.
---
drivers/gpu/drm/i915/i915_pmu.c | 32 ++--
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 7ece883a7d95..8736b3418f88 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -50,7 +50,7 @@ static u8 engine_event_instance(struct perf_event *event)
return (event->attr.config >> I915_PMU_SAMPLE_BITS) & 0xff;
}
-static bool is_engine_config(u64 config)
+static bool is_engine_config(const u64 config)
{
return config < __I915_PMU_OTHER(0);
}
@@ -82,15 +82,28 @@ static unsigned int other_bit(const u64 config)
static unsigned int config_bit(const u64 config)
{
+ unsigned int bit;
+
if (is_engine_config(config))
- return engine_config_sample(config);
+ bit = engine_config_sample(config);
else
- return other_bit(config);
+ bit = other_bit(config);
+
+ if (__builtin_constant_p(config))
+ BUILD_BUG_ON(bit >
+BITS_PER_TYPE(typeof_member(struct i915_pmu,
+enable)) - 1);
+ else
+ WARN_ON_ONCE(bit >
+BITS_PER_TYPE(typeof_member(struct i915_pmu,
+enable)) - 1);
The else is firing for the INTERRUPT event because event_bit() also
calls config_bit(). It would be best to move this check to config_mask()
and leave this function as is.
Thanks,
Umesh
+
+ return bit;
}
-static u64 config_mask(u64 config)
+static u32 config_mask(const u64 config)
{
- return BIT_ULL(config_bit(config));
+ return BIT(config_bit(config));
}
static bool is_engine_event(struct perf_event *event)
@@ -633,11 +646,10 @@ static void i915_pmu_enable(struct perf_event *event)
{
struct drm_i915_private *i915 =
container_of(event->pmu, typeof(*i915), pmu.base);
+ const unsigned int bit = event_bit(event);
struct i915_pmu *pmu = >pmu;
unsigned long flags;
- unsigned int bit;
- bit = event_bit(event);
if (bit == -1)
goto update;
@@ -651,7 +663,7 @@ static void i915_pmu_enable(struct perf_event *event)
GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count));
GEM_BUG_ON(pmu->enable_count[bit] == ~0);
- pmu->enable |= BIT_ULL(bit);
+ pmu->enable |= BIT(bit);
pmu->enable_count[bit]++;
/*
@@ -698,7 +710,7 @@ static void i915_pmu_disable(struct perf_event *event)
{
struct drm_i915_private *i915 =
container_of(event->pmu, typeof(*i915), pmu.base);
- unsigned int bit = event_bit(event);
+ const unsigned int bit = event_bit(event);
struct i915_pmu *pmu = >pmu;
unsigned long flags;
@@ -734,7 +746,7 @@ static void i915_pmu_disable(struct perf_event *event)
* bitmask when the last listener on an event goes away.
*/
if (--pmu->enable_count[bit] == 0) {
- pmu->enable &= ~BIT_ULL(bit);
+ pmu->enable &= ~BIT(bit);
pmu->timer_enabled &= pmu_needs_timer(pmu, true);
}
--
2.39.2
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Dump error capture to kernel log
On 5/16/2023 13:52, Rodrigo Vivi wrote:
On Tue, May 16, 2023 at 12:21:05PM -0700, John Harrison wrote:
On 5/16/2023 12:17, Belgaumkar, Vinay wrote:
> On 4/18/2023 11:17 AM, [1]john.c.harri...@intel.com wrote:
>> From: John Harrison [2]
>> This is useful for getting debug information out in certain
>> situations, such as failing kernel selftests and CI runs that don't
>> log error captures. It is especially useful for things like retrieving
>> GuC logs as GuC operation can't be tracked by adding printk or ftrace
>> entries.
>> v2: Add CONFIG_DRM_I915_DEBUG_GEM wrapper (review feedback by Rodrigo).
Thanks
> Do the CI sparse warnings hold water? With that looked at,
You mean this one totally fatal and absolutely must be fixed error?
Fast mode used, each commit won't be checked separately.
You should never rely on this assumption. There are bisects and autobisects
out there. Also every patch needs to be independently available for backport.
So, if there's any issue it needs to be fix before we merge.
What assumption? That sparse claims failure even when there are no
errors at all, just a notice about 'fast mode used'? If there are
errors, please point out where I can find them. AFAICT, the sparse email
is actually saying the patch set is clean despite the fact it has a big
red cross on it.
John.
Does anyone even know what that means or why it (apparently totally
randomly) hits some patch sets and not others?
If you mean the checkpatch warnings. One is about not reporting out of
memory errors (because you are supposed to return -ENOMEM and let the user
handle it instead), but that doesn't apply for an internal kernel only
thing which is already just a debug print. The other is about macro
argument re-use, which is not an issue in this case and not worth
re-writing the code to avoid.
John.
> LGTM,
> Reviewed-by: Vinay Belgaumkar [3]
>> Signed-off-by: John Harrison [4]
>> ---
>> drivers/gpu/drm/i915/i915_gpu_error.c | 132
>> ++
>> drivers/gpu/drm/i915/i915_gpu_error.h | 10 ++
>> 2 files changed, 142 insertions(+)
>> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
>> b/drivers/gpu/drm/i915/i915_gpu_error.c
>> index f020c0086fbcd..03d62c250c465 100644
>> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
>> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
>> @@ -2219,3 +2219,135 @@ void i915_disable_error_state(struct
>> drm_i915_private *i915, int err)
>> i915->gpu_error.first_error = ERR_PTR(err);
>> spin_unlock_irq(>gpu_error.lock);
>> }
>> +
>> +#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
>> +void intel_klog_error_capture(struct intel_gt *gt,
>> + intel_engine_mask_t engine_mask)
>> +{
>> + static int g_count;
>> + struct drm_i915_private *i915 = gt->i915;
>> + struct i915_gpu_coredump *error;
>> + intel_wakeref_t wakeref;
>> + size_t buf_size = PAGE_SIZE * 128;
>> + size_t pos_err;
>> + char *buf, *ptr, *next;
>> + int l_count = g_count++;
>> + int line = 0;
>> +
>> + /* Can't allocate memory during a reset */
>> + if (test_bit(I915_RESET_BACKOFF, >reset.flags)) {
>> + drm_err(>i915->drm, "[Capture/%d.%d] Inside GT reset,
>> skipping error capture :(\n",
>> + l_count, line++);
>> + return;
>> + }
>> +
>> + error = READ_ONCE(i915->gpu_error.first_error);
>> + if (error) {
>> + drm_err(>drm, "[Capture/%d.%d] Clearing existing error
>> capture first...\n",
>> + l_count, line++);
>> + i915_reset_error_state(i915);
>> + }
>> +
>> +
[Intel-gfx] [CI DO_NOT_MERGE 1/2] drm/i915/mtl: do not enable render power-gating on MTL
Multiple CI tests fails if render power gatins is enabled, with forcewake ack timeouts. BSpec 52698 clearly states it should be 0. Media gate seems also problematic. References: https://gitlab.freedesktop.org/drm/intel/-/issues/4983 Signed-off-by: Andrzej Hajda --- Let's try disabling render and media pg. --- drivers/gpu/drm/i915/gt/intel_rc6.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 908a3d0f2343f4..cd63eaf0d0c8de 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -117,9 +117,12 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) GEN6_RC_CTL_RC6_ENABLE | GEN6_RC_CTL_EI_MODE(1); + /* BSpec: 52698, GEN9_RENDER_PG_ENABLE must be 0 for MTL */ + if (IS_METEORLAKE(gt->i915)) + pg_enable = 0; /* Wa_16011777198 - Render powergating must remain disabled */ - if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || - IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) + else if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || +IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) pg_enable = GEN9_MEDIA_PG_ENABLE | GEN11_MEDIA_SAMPLER_PG_ENABLE; -- 2.34.1
[Intel-gfx] [CI DO_NOT_MERGE 2/2] drm/i915/gt: do not enable render and media power-gating on RPL-S
Multiple CI tests fails with forcewake timeouts. Disabling power gating for render and media solves the issue. References: https://gitlab.freedesktop.org/drm/intel/-/issues/4983 Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/i915/gt/intel_rc6.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index cd63eaf0d0c8de..3f8238c95fccd6 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -126,6 +126,9 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) pg_enable = GEN9_MEDIA_PG_ENABLE | GEN11_MEDIA_SAMPLER_PG_ENABLE; + /* Testing */ + else if (IS_ADLS_RPLS(gt->i915)) + pg_enable = 0; else pg_enable = GEN9_RENDER_PG_ENABLE | -- 2.34.1
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,DO_NOT_MERGE,1/3] drm/i915/mtl: do not enable render power-gating on MTL
== Series Details ==
Series: series starting with [CI,DO_NOT_MERGE,1/3] drm/i915/mtl: do not enable
render power-gating on MTL
URL : https://patchwork.freedesktop.org/series/117819/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13154 -> Patchwork_117819v1
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_117819v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_117819v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117819v1/index.html
Participating hosts (38 -> 36)
--
Missing(2): fi-snb-2520m bat-mtlp-6
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_117819v1:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@uncore:
- bat-rpls-1: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-rpls-1/igt@i915_selftest@l...@uncore.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117819v1/bat-rpls-1/igt@i915_selftest@l...@uncore.html
Known issues
Here are the changes found in Patchwork_117819v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [PASS][3] -> [ABORT][4] ([i915#7911] / [i915#7913])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117819v1/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@uncore:
- bat-rpls-2: [PASS][5] -> [INCOMPLETE][6] ([i915#7913])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-rpls-2/igt@i915_selftest@l...@uncore.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117819v1/bat-rpls-2/igt@i915_selftest@l...@uncore.html
- bat-dg2-11: [PASS][7] -> [ABORT][8] ([i915#7913])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-dg2-11/igt@i915_selftest@l...@uncore.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117819v1/bat-dg2-11/igt@i915_selftest@l...@uncore.html
- fi-kbl-soraka: [PASS][9] -> [ABORT][10] ([i915#7913] / [i915#8405])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/fi-kbl-soraka/igt@i915_selftest@l...@uncore.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117819v1/fi-kbl-soraka/igt@i915_selftest@l...@uncore.html
- bat-adls-5: [PASS][11] -> [ABORT][12] ([i915#7913])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-adls-5/igt@i915_selftest@l...@uncore.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117819v1/bat-adls-5/igt@i915_selftest@l...@uncore.html
- bat-dg2-9: [PASS][13] -> [ABORT][14] ([i915#7913] / [i915#8405])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-dg2-9/igt@i915_selftest@l...@uncore.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117819v1/bat-dg2-9/igt@i915_selftest@l...@uncore.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
- bat-dg2-8: [PASS][15] -> [FAIL][16] ([i915#7932]) +1 similar
issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117819v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
Possible fixes
* igt@i915_selftest@live@requests:
- {bat-mtlp-8}: [ABORT][17] ([i915#4983] / [i915#7920]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-mtlp-8/igt@i915_selftest@l...@requests.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117819v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html
* igt@i915_selftest@live@slpc:
- bat-rpls-1: [DMESG-WARN][19] ([i915#6367]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/bat-rpls-1/igt@i915_selftest@l...@slpc.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117819v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,DO_NOT_MERGE,1/3] drm/i915/mtl: do not enable render power-gating on MTL
== Series Details == Series: series starting with [CI,DO_NOT_MERGE,1/3] drm/i915/mtl: do not enable render power-gating on MTL URL : https://patchwork.freedesktop.org/series/117819/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./drivers/gpu/drm/i915/intel_uncore.h:346:1: warning: trying to copy expression type 31 +./drivers/gpu/drm/i915/intel_uncore.h:351:1: warning: trying to copy expression type 31 +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask'
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,DO_NOT_MERGE,1/3] drm/i915/mtl: do not enable render power-gating on MTL
== Series Details == Series: series starting with [CI,DO_NOT_MERGE,1/3] drm/i915/mtl: do not enable render power-gating on MTL URL : https://patchwork.freedesktop.org/series/117819/ State : warning == Summary == Error: dim checkpatch failed e0f1fa65f100 drm/i915/mtl: do not enable render power-gating on MTL -:10: WARNING:COMMIT_LOG_USE_LINK: Unknown link reference 'References:', use 'Link:' or 'Closes:' instead #10: References: https://gitlab.freedesktop.org/drm/intel/-/issues/4983 -:28: ERROR:CODE_INDENT: code indent should use tabs where possible #28: FILE: drivers/gpu/drm/i915/gt/intel_rc6.c:125: +^I IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))$ total: 1 errors, 1 warnings, 0 checks, 14 lines checked 496a05f3de25 drm/i915/gt: do not enable render and media power-gating on RPL-S -:10: WARNING:COMMIT_LOG_USE_LINK: Unknown link reference 'References:', use 'Link:' or 'Closes:' instead #10: References: https://gitlab.freedesktop.org/drm/intel/-/issues/4983 total: 0 errors, 1 warnings, 0 checks, 9 lines checked b0d1f92bc92f drm/i915/selftests: add forcewake_with_spinners tests -:78: CHECK:SPACING: No space is necessary after a cast #78: FILE: drivers/gpu/drm/i915/selftests/intel_uncore.c:397: + intel_klog_error_capture(gt, (intel_engine_mask_t) ~0U); -:84: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst #84: FILE: drivers/gpu/drm/i915/selftests/intel_uncore.c:403: + msleep(3); total: 0 errors, 1 warnings, 1 checks, 104 lines checked
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: fix intel_display_irq.c include order
== Series Details ==
Series: drm/i915: fix intel_display_irq.c include order
URL : https://patchwork.freedesktop.org/series/117816/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13151_full -> Patchwork_117816v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_117816v1_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@syncobj_wait@reset-unsignaled:
- {shard-dg1}:[PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-dg1-14/igt@syncobj_w...@reset-unsignaled.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117816v1/shard-dg1-16/igt@syncobj_w...@reset-unsignaled.html
Known issues
Here are the changes found in Patchwork_117816v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-glk1/igt@gem_exec_fair@basic-p...@vcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117816v1/shard-glk3/igt@gem_exec_fair@basic-p...@vcs0.html
* igt@i915_pm_rps@reset:
- shard-snb: [PASS][5] -> [DMESG-FAIL][6] ([i915#8319])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-snb4/igt@i915_pm_...@reset.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117816v1/shard-snb6/igt@i915_pm_...@reset.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#2346])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-glk4/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117816v1/shard-glk9/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#79])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-glk6/igt@kms_flip@flip-vs-expired-vbl...@b-hdmi-a2.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117816v1/shard-glk8/igt@kms_flip@flip-vs-expired-vbl...@b-hdmi-a2.html
Possible fixes
* igt@drm_fdinfo@virtual-idle:
- {shard-rkl}:[FAIL][11] ([i915#7742]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-rkl-2/igt@drm_fdi...@virtual-idle.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117816v1/shard-rkl-7/igt@drm_fdi...@virtual-idle.html
* igt@gem_exec_fair@basic-none@bcs0:
- {shard-rkl}:[FAIL][13] ([i915#2842]) -> [PASS][14] +2 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-rkl-7/igt@gem_exec_fair@basic-n...@bcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117816v1/shard-rkl-1/igt@gem_exec_fair@basic-n...@bcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][15] ([i915#2842]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117816v1/shard-glk1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
- {shard-tglu}: [FAIL][17] ([i915#2842]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-tglu-9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117816v1/shard-tglu-3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- {shard-rkl}:[SKIP][19] ([i915#1397]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-rkl-7/igt@i915_pm_...@modeset-non-lpsp-stress-no-wait.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117816v1/shard-rkl-1/igt@i915_pm_...@modeset-non-lpsp-stress-no-wait.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1:
- shard-glk: [FAIL][21] ([i915#79]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-hdmi-a1.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117816v1/shard-glk6/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1:
- shard-apl: [FAIL][23] ([i915#79]) -> [PASS][24]
[23]:
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Dump error capture to kernel log
On Tue, May 16, 2023 at 12:21:05PM -0700, John Harrison wrote: >On 5/16/2023 12:17, Belgaumkar, Vinay wrote: > > > >> On 4/18/2023 11:17 AM, [1]john.c.harri...@intel.com wrote: > > > >>> From: John Harrison [2] > > > >>> This is useful for getting debug information out in certain > >>> situations, such as failing kernel selftests and CI runs that don't > >>> log error captures. It is especially useful for things like retrieving > >>> GuC logs as GuC operation can't be tracked by adding printk or ftrace > >>> entries. > > > >>> v2: Add CONFIG_DRM_I915_DEBUG_GEM wrapper (review feedback by Rodrigo). > Thanks > > >> Do the CI sparse warnings hold water? With that looked at, > > > >You mean this one totally fatal and absolutely must be fixed error? > > > >Fast mode used, each commit won't be checked separately. > You should never rely on this assumption. There are bisects and autobisects out there. Also every patch needs to be independently available for backport. So, if there's any issue it needs to be fix before we merge. > > >Does anyone even know what that means or why it (apparently totally > >randomly) hits some patch sets and not others? > > > >If you mean the checkpatch warnings. One is about not reporting out of > >memory errors (because you are supposed to return -ENOMEM and let the user > >handle it instead), but that doesn't apply for an internal kernel only > >thing which is already just a debug print. The other is about macro > >argument re-use, which is not an issue in this case and not worth > >re-writing the code to avoid. > > > >John. > > > >> LGTM, > > > >> Reviewed-by: Vinay Belgaumkar [3] > > > >>> Signed-off-by: John Harrison [4] > >>> --- > >>> drivers/gpu/drm/i915/i915_gpu_error.c | 132 > >>> ++ > >>> drivers/gpu/drm/i915/i915_gpu_error.h | 10 ++ > >>> 2 files changed, 142 insertions(+) > > > >>> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c > >>> b/drivers/gpu/drm/i915/i915_gpu_error.c > >>> index f020c0086fbcd..03d62c250c465 100644 > >>> --- a/drivers/gpu/drm/i915/i915_gpu_error.c > >>> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > >>> @@ -2219,3 +2219,135 @@ void i915_disable_error_state(struct > >>> drm_i915_private *i915, int err) > >>> i915->gpu_error.first_error = ERR_PTR(err); > >>> spin_unlock_irq(>gpu_error.lock); > >>> } > >>> + > >>> +#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) > >>> +void intel_klog_error_capture(struct intel_gt *gt,
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gem: Use large rings for compute contexts
== Series Details ==
Series: drm/i915/gem: Use large rings for compute contexts
URL : https://patchwork.freedesktop.org/series/117814/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13151_full -> Patchwork_117814v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_117814v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2:
- shard-glk: [PASS][1] -> [FAIL][2] ([i915#79])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-glk6/igt@kms_flip@flip-vs-expired-vbl...@b-hdmi-a2.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v1/shard-glk3/igt@kms_flip@flip-vs-expired-vbl...@b-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend@b-dp1:
- shard-apl: [PASS][3] -> [ABORT][4] ([i915#180])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-apl1/igt@kms_flip@flip-vs-susp...@b-dp1.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v1/shard-apl3/igt@kms_flip@flip-vs-susp...@b-dp1.html
Possible fixes
* igt@gem_exec_fair@basic-none@bcs0:
- {shard-rkl}:[FAIL][5] ([i915#2842]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-rkl-7/igt@gem_exec_fair@basic-n...@bcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v1/shard-rkl-6/igt@gem_exec_fair@basic-n...@bcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][7] ([i915#2842]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v1/shard-glk1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@i915_pm_dc@dc9-dpms:
- {shard-tglu}: [SKIP][9] ([i915#4281]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-tglu-6/igt@i915_pm...@dc9-dpms.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v1/shard-tglu-4/igt@i915_pm...@dc9-dpms.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- {shard-dg1}:[FAIL][11] ([i915#3591]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v1/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- {shard-rkl}:[SKIP][13] ([i915#1397]) -> [PASS][14] +1 similar
issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-rkl-6/igt@i915_pm_...@dpms-mode-unset-lpsp.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v1/shard-rkl-7/igt@i915_pm_...@dpms-mode-unset-lpsp.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [FAIL][15] ([i915#2346]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-glk1/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v1/shard-glk5/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1:
- shard-glk: [FAIL][17] ([i915#79]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-hdmi-a1.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v1/shard-glk6/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-hdmi-a1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3638]:
Re: [Intel-gfx] [PATCH v5 7/8] drm/i915/mtl: Add support for PM DEMAND
Hi, Vinod.
I have provided a comment inline below. Also note that I have replied to
some of your comments on the previous version [1].
[1]
https://patchwork.freedesktop.org/patch/534347/?series=116949=4#comment_973634
Quoting Vinod Govindapillai (2023-05-11 20:17:49)
>From: Mika Kahola
>
>Display14 introduces a new way to instruct the PUnit with
>power and bandwidth requirements of DE. Add the functionality
>to program the registers and handle waits using interrupts.
>The current wait time for timeouts is programmed for 10 msecs to
>factor in the worst case scenarios. Changes made to use REG_BIT
>for a register that we touched(GEN8_DE_MISC_IER _MMIO).
>
>Wa_14016740474 is added which applies to Xe_LPD+ display
>
>v2: checkpatch warning fixes, simplify program pmdemand part
>
>v3: update to dbufs and pipes values to pmdemand register(stan)
>Removed the macro usage in update_pmdemand_values()
>
>v4: move the pmdemand_pre_plane_update before cdclk update
>pmdemand_needs_update included cdclk params comparisons
>pmdemand_state NULL check (Gustavo)
>pmdemand.o in sorted order in the makefile (Jani)
>update pmdemand misc irq handler loop (Gustavo)
>active phys bitmask and programming correction (Gustavo)
>
>Bspec: 66451, 64636, 64602, 64603
>Cc: Matt Atwood
>Cc: Matt Roper
>Cc: Lucas De Marchi
>Cc: Gustavo Sousa
>Signed-off-by: José Roberto de Souza
>Signed-off-by: Radhakrishna Sripada
>Signed-off-by: Gustavo Sousa
>Signed-off-by: Mika Kahola
>Signed-off-by: Vinod Govindapillai
>---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 14 +
> .../gpu/drm/i915/display/intel_display_core.h | 6 +
> .../drm/i915/display/intel_display_driver.c | 7 +
> .../drm/i915/display/intel_display_power.c| 8 +
> drivers/gpu/drm/i915/display/intel_pmdemand.c | 465 ++
> drivers/gpu/drm/i915/display/intel_pmdemand.h | 24 +
> drivers/gpu/drm/i915/i915_irq.c | 23 +-
> drivers/gpu/drm/i915/i915_reg.h | 36 +-
> 9 files changed, 580 insertions(+), 4 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h
>
>diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
>index d97d45ae1a0d..a7c2cf21cbfc 100644
>--- a/drivers/gpu/drm/i915/Makefile
>+++ b/drivers/gpu/drm/i915/Makefile
>@@ -270,6 +270,7 @@ i915-y += \
> display/intel_pch_display.o \
> display/intel_pch_refclk.o \
> display/intel_plane_initial.o \
>+display/intel_pmdemand.o \
> display/intel_psr.o \
> display/intel_quirks.o \
> display/intel_sprite.o \
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index 1d5d42a40803..dd390a0586ef 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -99,6 +99,7 @@
> #include "intel_pcode.h"
> #include "intel_pipe_crc.h"
> #include "intel_plane_initial.h"
>+#include "intel_pmdemand.h"
> #include "intel_pps.h"
> #include "intel_psr.h"
> #include "intel_sdvo.h"
>@@ -6315,6 +6316,10 @@ int intel_atomic_check(struct drm_device *dev,
> return ret;
> }
>
>+ret = intel_pmdemand_atomic_check(state);
>+if (ret)
>+goto fail;
>+
> ret = intel_atomic_check_crtcs(state);
> if (ret)
> goto fail;
>@@ -6960,6 +6965,14 @@ static void intel_atomic_commit_tail(struct
>intel_atomic_state *state)
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
> crtc->config = new_crtc_state;
>
>+/*
>+ * In D14 Pmdemand combines many paramters such as voltage index,
>plls,
>+ * cdclk frequency, QGV point selection parameter etc. Voltage index,
>+ * cdclk/ddiclk frequencies are supposed to be configured before the
>+ * cdclk config is set.
>+ */
>+intel_pmdemand_pre_plane_update(state);
>+
> if (state->modeset) {
> drm_atomic_helper_update_legacy_modeset_state(dev,
> >base);
>
>@@ -7079,6 +7092,7 @@ static void intel_atomic_commit_tail(struct
>intel_atomic_state *state)
> intel_verify_planes(state);
>
> intel_sagv_post_plane_update(state);
>+intel_pmdemand_post_plane_update(state);
>
> drm_atomic_helper_commit_hw_done(>base);
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
>b/drivers/gpu/drm/i915/display/intel_display_core.h
>index 9f66d734edf6..9471a052aa57 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_core.h
>+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>@@ -345,6 +345,12 @@ struct intel_display {
> struct intel_global_obj obj;
> } dbuf;
>
>+struct {
>+wait_queue_head_t waitqueue;
>+
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Dump error capture to kernel log
On 5/16/2023 12:17, Belgaumkar, Vinay wrote:
On 4/18/2023 11:17 AM, john.c.harri...@intel.com wrote:
From: John Harrison
This is useful for getting debug information out in certain
situations, such as failing kernel selftests and CI runs that don't
log error captures. It is especially useful for things like retrieving
GuC logs as GuC operation can't be tracked by adding printk or ftrace
entries.
v2: Add CONFIG_DRM_I915_DEBUG_GEM wrapper (review feedback by Rodrigo).
Do the CI sparse warnings hold water? With that looked at,
You mean this one totally fatal and absolutely must be fixed error?
Fast mode used, each commit won't be checked separately.
Does anyone even know what that means or why it (apparently totally
randomly) hits some patch sets and not others?
If you mean the checkpatch warnings. One is about not reporting out of
memory errors (because you are supposed to return -ENOMEM and let the
user handle it instead), but that doesn't apply for an internal kernel
only thing which is already just a debug print. The other is about macro
argument re-use, which is not an issue in this case and not worth
re-writing the code to avoid.
John.
LGTM,
Reviewed-by: Vinay Belgaumkar
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/i915_gpu_error.c | 132 ++
drivers/gpu/drm/i915/i915_gpu_error.h | 10 ++
2 files changed, 142 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index f020c0086fbcd..03d62c250c465 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -2219,3 +2219,135 @@ void i915_disable_error_state(struct
drm_i915_private *i915, int err)
i915->gpu_error.first_error = ERR_PTR(err);
spin_unlock_irq(>gpu_error.lock);
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
+void intel_klog_error_capture(struct intel_gt *gt,
+ intel_engine_mask_t engine_mask)
+{
+ static int g_count;
+ struct drm_i915_private *i915 = gt->i915;
+ struct i915_gpu_coredump *error;
+ intel_wakeref_t wakeref;
+ size_t buf_size = PAGE_SIZE * 128;
+ size_t pos_err;
+ char *buf, *ptr, *next;
+ int l_count = g_count++;
+ int line = 0;
+
+ /* Can't allocate memory during a reset */
+ if (test_bit(I915_RESET_BACKOFF, >reset.flags)) {
+ drm_err(>i915->drm, "[Capture/%d.%d] Inside GT reset,
skipping error capture :(\n",
+ l_count, line++);
+ return;
+ }
+
+ error = READ_ONCE(i915->gpu_error.first_error);
+ if (error) {
+ drm_err(>drm, "[Capture/%d.%d] Clearing existing error
capture first...\n",
+ l_count, line++);
+ i915_reset_error_state(i915);
+ }
+
+ with_intel_runtime_pm(>runtime_pm, wakeref)
+ error = i915_gpu_coredump(gt, engine_mask,
CORE_DUMP_FLAG_NONE);
+
+ if (IS_ERR(error)) {
+ drm_err(>drm, "[Capture/%d.%d] Failed to capture error
capture: %ld!\n",
+ l_count, line++, PTR_ERR(error));
+ return;
+ }
+
+ buf = kvmalloc(buf_size, GFP_KERNEL);
+ if (!buf) {
+ drm_err(>drm, "[Capture/%d.%d] Failed to allocate
buffer for error capture!\n",
+ l_count, line++);
+ i915_gpu_coredump_put(error);
+ return;
+ }
+
+ drm_info(>drm, "[Capture/%d.%d] Dumping i915 error capture
for %ps...\n",
+ l_count, line++, __builtin_return_address(0));
+
+ /* Largest string length safe to print via dmesg */
+# define MAX_CHUNK 800
+
+ pos_err = 0;
+ while (1) {
+ ssize_t got = i915_gpu_coredump_copy_to_buffer(error, buf,
pos_err, buf_size - 1);
+
+ if (got <= 0)
+ break;
+
+ buf[got] = 0;
+ pos_err += got;
+
+ ptr = buf;
+ while (got > 0) {
+ size_t count;
+ char tag[2];
+
+ next = strnchr(ptr, got, '\n');
+ if (next) {
+ count = next - ptr;
+ *next = 0;
+ tag[0] = '>';
+ tag[1] = '<';
+ } else {
+ count = got;
+ tag[0] = '}';
+ tag[1] = '{';
+ }
+
+ if (count > MAX_CHUNK) {
+ size_t pos;
+ char *ptr2 = ptr;
+
+ for (pos = MAX_CHUNK; pos < count; pos += MAX_CHUNK) {
+ char chr = ptr[pos];
+
+ ptr[pos] = 0;
+ drm_info(>drm, "[Capture/%d.%d] }%s{\n",
+ l_count, line++, ptr2);
+ ptr[pos] = chr;
+ ptr2 = ptr + pos;
+
+ /*
+ * If spewing large amounts of data via a serial
console,
+ * this can be a very slow process. So be
friendly and try
+ * not to cause 'softlockup on CPU' problems.
+ */
+ cond_resched();
+ }
+
+
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: tweak language in fastset pipe config compare logging
== Series Details ==
Series: drm/i915: tweak language in fastset pipe config compare logging
URL : https://patchwork.freedesktop.org/series/117807/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13151_full -> Patchwork_117807v1_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_117807v1_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_117807v1_full, please notify your bug team to allow
them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_117807v1_full:
### IGT changes ###
Possible regressions
* igt@i915_suspend@debugfs-reader:
- shard-apl: [PASS][1] -> [ABORT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-apl6/igt@i915_susp...@debugfs-reader.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117807v1/shard-apl3/igt@i915_susp...@debugfs-reader.html
Known issues
Here are the changes found in Patchwork_117807v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2346])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-glk4/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117807v1/shard-glk1/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
Possible fixes
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- {shard-rkl}:[FAIL][5] ([i915#7742]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-rkl-7/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117807v1/shard-rkl-2/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
* igt@gem_exec_fair@basic-none@bcs0:
- {shard-rkl}:[FAIL][7] ([i915#2842]) -> [PASS][8] +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-rkl-7/igt@gem_exec_fair@basic-n...@bcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117807v1/shard-rkl-2/igt@gem_exec_fair@basic-n...@bcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][9] ([i915#2842]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117807v1/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
- {shard-tglu}: [FAIL][11] ([i915#2842]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-tglu-9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117807v1/shard-tglu-5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- {shard-dg1}:[FAIL][13] ([i915#3591]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117807v1/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html
* igt@i915_pm_rps@engine-order:
- shard-apl: [FAIL][15] ([i915#6537]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-apl1/igt@i915_pm_...@engine-order.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117807v1/shard-apl6/igt@i915_pm_...@engine-order.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-apl: [FAIL][17] ([i915#2346]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-apl4/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117807v1/shard-apl1/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1:
- shard-glk: [FAIL][19] ([i915#79]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-hdmi-a1.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117807v1/shard-glk5/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1:
- shard-apl: [FAIL][21] ([i915#79]) -> [PASS][22]
[21]:
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/guc: Dump error capture to dmesg on CTB error
On 4/18/2023 11:17 AM, john.c.harri...@intel.com wrote:
From: John Harrison
In the past, There have been sporadic CTB failures which proved hard
to reproduce manually. The most effective solution was to dump the GuC
log at the point of failure and let the CI system do the repro. It is
preferable not to dump the GuC log via dmesg for all issues as it is
not always necessary and is not helpful for end users. But rather than
trying to re-invent the code to do this each time it is wanted, commit
the code but for DEBUG_GUC builds only.
v2: Use IS_ENABLED for testing config options.
LGTM,
Reviewed-by: Vinay Belgaumkar
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 53 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 6 +++
2 files changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 1803a633ed648..dc5cd712f1ff5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -13,6 +13,30 @@
#include "intel_guc_ct.h"
#include "intel_guc_print.h"
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GUC)
+enum {
+ CT_DEAD_ALIVE = 0,
+ CT_DEAD_SETUP,
+ CT_DEAD_WRITE,
+ CT_DEAD_DEADLOCK,
+ CT_DEAD_H2G_HAS_ROOM,
+ CT_DEAD_READ,
+ CT_DEAD_PROCESS_FAILED,
+};
+
+static void ct_dead_ct_worker_func(struct work_struct *w);
+
+#define CT_DEAD(ct, reason)\
+ do { \
+ if (!(ct)->dead_ct_reported) { \
+ (ct)->dead_ct_reason |= 1 << CT_DEAD_##reason; \
+ queue_work(system_unbound_wq, &(ct)->dead_ct_worker); \
+ } \
+ } while (0)
+#else
+#define CT_DEAD(ct, reason)do { } while (0)
+#endif
+
static inline struct intel_guc *ct_to_guc(struct intel_guc_ct *ct)
{
return container_of(ct, struct intel_guc, ct);
@@ -93,6 +117,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct)
spin_lock_init(>requests.lock);
INIT_LIST_HEAD(>requests.pending);
INIT_LIST_HEAD(>requests.incoming);
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GUC)
+ INIT_WORK(>dead_ct_worker, ct_dead_ct_worker_func);
+#endif
INIT_WORK(>requests.worker, ct_incoming_request_worker_func);
tasklet_setup(>receive_tasklet, ct_receive_tasklet_func);
init_waitqueue_head(>wq);
@@ -319,11 +346,16 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
ct->enabled = true;
ct->stall_time = KTIME_MAX;
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GUC)
+ ct->dead_ct_reported = false;
+ ct->dead_ct_reason = CT_DEAD_ALIVE;
+#endif
return 0;
err_out:
CT_PROBE_ERROR(ct, "Failed to enable CTB (%pe)\n", ERR_PTR(err));
+ CT_DEAD(ct, SETUP);
return err;
}
@@ -434,6 +466,7 @@ static int ct_write(struct intel_guc_ct *ct,
corrupted:
CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
desc->head, desc->tail, desc->status);
+ CT_DEAD(ct, WRITE);
ctb->broken = true;
return -EPIPE;
}
@@ -504,6 +537,7 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct)
CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head);
CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail);
+ CT_DEAD(ct, DEADLOCK);
ct->ctbs.send.broken = true;
}
@@ -552,6 +586,7 @@ static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw)
head, ctb->size);
desc->status |= GUC_CTB_STATUS_OVERFLOW;
ctb->broken = true;
+ CT_DEAD(ct, H2G_HAS_ROOM);
return false;
}
@@ -908,6 +943,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
desc->head, desc->tail, desc->status);
ctb->broken = true;
+ CT_DEAD(ct, READ);
return -EPIPE;
}
@@ -1057,6 +1093,7 @@ static bool ct_process_incoming_requests(struct intel_guc_ct *ct)
if (unlikely(err)) {
CT_ERROR(ct, "Failed to process CT message (%pe) %*ph\n",
ERR_PTR(err), 4 * request->size, request->msg);
+ CT_DEAD(ct, PROCESS_FAILED);
ct_free_msg(request);
}
@@ -1233,3 +1270,19 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct,
drm_printf(p, "Tail: %u\n",
ct->ctbs.recv.desc->tail);
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GUC)
+static void ct_dead_ct_worker_func(struct work_struct *w)
+{
+ struct intel_guc_ct *ct = container_of(w, struct intel_guc_ct,
dead_ct_worker);
+ struct intel_guc *guc = ct_to_guc(ct);
+
+ if (ct->dead_ct_reported)
+ return;
+
+ ct->dead_ct_reported = true;
+
+ guc_info(guc, "CTB is dead -
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Dump error capture to kernel log
On 4/18/2023 11:17 AM, john.c.harri...@intel.com wrote:
From: John Harrison
This is useful for getting debug information out in certain
situations, such as failing kernel selftests and CI runs that don't
log error captures. It is especially useful for things like retrieving
GuC logs as GuC operation can't be tracked by adding printk or ftrace
entries.
v2: Add CONFIG_DRM_I915_DEBUG_GEM wrapper (review feedback by Rodrigo).
Do the CI sparse warnings hold water? With that looked at,
LGTM,
Reviewed-by: Vinay Belgaumkar
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/i915_gpu_error.c | 132 ++
drivers/gpu/drm/i915/i915_gpu_error.h | 10 ++
2 files changed, 142 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index f020c0086fbcd..03d62c250c465 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -2219,3 +2219,135 @@ void i915_disable_error_state(struct drm_i915_private
*i915, int err)
i915->gpu_error.first_error = ERR_PTR(err);
spin_unlock_irq(>gpu_error.lock);
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
+void intel_klog_error_capture(struct intel_gt *gt,
+ intel_engine_mask_t engine_mask)
+{
+ static int g_count;
+ struct drm_i915_private *i915 = gt->i915;
+ struct i915_gpu_coredump *error;
+ intel_wakeref_t wakeref;
+ size_t buf_size = PAGE_SIZE * 128;
+ size_t pos_err;
+ char *buf, *ptr, *next;
+ int l_count = g_count++;
+ int line = 0;
+
+ /* Can't allocate memory during a reset */
+ if (test_bit(I915_RESET_BACKOFF, >reset.flags)) {
+ drm_err(>i915->drm, "[Capture/%d.%d] Inside GT reset, skipping
error capture :(\n",
+ l_count, line++);
+ return;
+ }
+
+ error = READ_ONCE(i915->gpu_error.first_error);
+ if (error) {
+ drm_err(>drm, "[Capture/%d.%d] Clearing existing error capture
first...\n",
+ l_count, line++);
+ i915_reset_error_state(i915);
+ }
+
+ with_intel_runtime_pm(>runtime_pm, wakeref)
+ error = i915_gpu_coredump(gt, engine_mask, CORE_DUMP_FLAG_NONE);
+
+ if (IS_ERR(error)) {
+ drm_err(>drm, "[Capture/%d.%d] Failed to capture error
capture: %ld!\n",
+ l_count, line++, PTR_ERR(error));
+ return;
+ }
+
+ buf = kvmalloc(buf_size, GFP_KERNEL);
+ if (!buf) {
+ drm_err(>drm, "[Capture/%d.%d] Failed to allocate buffer for
error capture!\n",
+ l_count, line++);
+ i915_gpu_coredump_put(error);
+ return;
+ }
+
+ drm_info(>drm, "[Capture/%d.%d] Dumping i915 error capture for
%ps...\n",
+l_count, line++, __builtin_return_address(0));
+
+ /* Largest string length safe to print via dmesg */
+# define MAX_CHUNK800
+
+ pos_err = 0;
+ while (1) {
+ ssize_t got = i915_gpu_coredump_copy_to_buffer(error, buf,
pos_err, buf_size - 1);
+
+ if (got <= 0)
+ break;
+
+ buf[got] = 0;
+ pos_err += got;
+
+ ptr = buf;
+ while (got > 0) {
+ size_t count;
+ char tag[2];
+
+ next = strnchr(ptr, got, '\n');
+ if (next) {
+ count = next - ptr;
+ *next = 0;
+ tag[0] = '>';
+ tag[1] = '<';
+ } else {
+ count = got;
+ tag[0] = '}';
+ tag[1] = '{';
+ }
+
+ if (count > MAX_CHUNK) {
+ size_t pos;
+ char *ptr2 = ptr;
+
+ for (pos = MAX_CHUNK; pos < count; pos +=
MAX_CHUNK) {
+ char chr = ptr[pos];
+
+ ptr[pos] = 0;
+ drm_info(>drm, "[Capture/%d.%d]
}%s{\n",
+l_count, line++, ptr2);
+ ptr[pos] = chr;
+ ptr2 = ptr + pos;
+
+ /*
+* If spewing large amounts of data via
a serial console,
+* this can be a very slow process. So
be friendly and try
+* not to cause 'softlockup on CPU'
problems.
+*/
+ cond_resched();
Re: [Intel-gfx] [PATCH v2 0/2] Add support for dumping error captures via kernel logging
On 4/18/2023 11:17 AM, john.c.harri...@intel.com wrote: From: John Harrison Sometimes, the only effective way to debug an issue is to dump all the interesting information at the point of failure. So add support for doing that. v2: Extra CONFIG wrapping (review feedback from Rodrigo) Signed-off-by: John Harrison series LGTM, Reviewed-by: Vinay Belgaumkar John Harrison (2): drm/i915: Dump error capture to kernel log drm/i915/guc: Dump error capture to dmesg on CTB error drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 53 + drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 6 + drivers/gpu/drm/i915/i915_gpu_error.c | 132 ++ drivers/gpu/drm/i915/i915_gpu_error.h | 10 ++ 4 files changed, 201 insertions(+)
Re: [Intel-gfx] [PATCH v5 6/8] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
>
> The array of rc_parameters contains a mixture of parameters from DSC 1.1
> and DSC 1.2 standards. Split these tow configuration arrays in preparation to
> adding more configuration data.
>
Hi ,
Needed to add some more comments apart from the previous ones already given
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 127 ++
> drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
> include/drm/display/drm_dsc_helper.h | 7 +-
> 3 files changed, 119 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c
> b/drivers/gpu/drm/display/drm_dsc_helper.c
> index acb93d4116e0..35b39f3109c4 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -324,11 +324,81 @@ struct rc_parameters_data {
>
> #define DSC_BPP(bpp) ((bpp) << 4)
>
> +static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> + {
> + .bpp = DSC_BPP(8), .bpc = 8,
> + { 512, 12, 6144, 3, 12, 11, 11, {
> + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12,
> -12 },
> + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(8), .bpc = 10,
> + { 512, 12, 6144, 7, 16, 15, 15, {
> + /*
> + * DSC model/pre-SCR-cfg has 8 for
> range_max_qp[0], however
> + * VESA DSC 1.1 Table E-5 sets it to 4.
> + */
> + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12,
> -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16,
> -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(8), .bpc = 12,
> + { 512, 12, 6144, 11, 20, 19, 19, {
> + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11,
> 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 8,
> + { 341, 15, 2048, 3, 12, 11, 11, {
> + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13,
> 15, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 10,
> + { 341, 15, 2048, 7, 16, 15, 15, {
> + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8
> },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16,
> -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 12,
> + { 341, 15, 2048, 11, 20, 19, 19, {
> + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11,
> 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> + },
> + { /* sentinel */ }
> +};
> +
> /*
> * Selected Rate Control Related Parameter Recommended Values
> * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> */
> -static const struct rc_parameters_data rc_parameters[] = {
> +static const struct rc_parameters_data rc_parameters_1_2_444[] = {
> {
> .bpp = DSC_BPP(6), .bpc = 8,
> { 768, 15, 6144, 3, 13, 11, 11, {
> @@ -388,22 +458,18 @@ static const struct rc_parameters_data
> rc_parameters[] = {
> { 512, 12, 6144, 3, 12, 11, 11, {
> { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12,
> -12 },
> - { 5, 13, -12 }, { 7, 13, -12
[Intel-gfx] [PATCH v9 1/2] drm/i915/mtl: end support for set caching ioctl
From: Fei Yang
The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
cache. For userspace components needing to fine tune the caching policy
for BO's, a follow up patch will extend the GEM_CREATE uAPI to allow
them specify caching mode at BO creation time.
Signed-off-by: Fei Yang
Reviewed-by: Andi Shyti
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 9 -
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 05107a6efe45..dfaaa8b66ac3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -350,6 +350,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void
*data,
if (IS_DGFX(i915))
return -ENODEV;
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+ return -EOPNOTSUPP;
+
switch (args->caching) {
case I915_CACHING_NONE:
level = I915_CACHE_NONE;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 37d1efcd3ca6..cad4a6017f4b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -601,7 +601,14 @@ static int shmem_object_init(struct intel_memory_region
*mem,
obj->write_domain = I915_GEM_DOMAIN_CPU;
obj->read_domains = I915_GEM_DOMAIN_CPU;
- if (HAS_LLC(i915))
+ /*
+* MTL doesn't snoop CPU cache by default for GPU access (namely
+* 1-way coherency). However some UMD's are currently depending on
+* that. Make 1-way coherent the default setting for MTL. A follow
+* up patch will extend the GEM_CREATE uAPI to allow UMD's specify
+* caching mode at BO creation time
+*/
+ if (HAS_LLC(i915) || (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)))
/* On some devices, we can have the GPU use the LLC (the CPU
* cache) for about a 10% performance improvement
* compared to uncached. Graphics requests other than
--
2.25.1
[Intel-gfx] [PATCH v9 2/2] drm/i915: Allow user to set cache at BO creation
From: Fei Yang
To comply with the design that buffer objects shall have immutable
cache setting through out their life cycle, {set, get}_caching ioctl's
are no longer supported from MTL onward. With that change caching
policy can only be set at object creation time. The current code
applies a default (platform dependent) cache setting for all objects.
However this is not optimal for performance tuning. The patch extends
the existing gem_create uAPI to let user set PAT index for the object
at creation time.
The new extension is platform independent, so UMD's can switch to using
this extension for older platforms as well, while {set, get}_caching are
still supported on these legacy paltforms for compatibility reason.
Test igt@gem_create@create_ext_set_pat posted at
https://patchwork.freedesktop.org/series/117695/
Tested with https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878
Signed-off-by: Fei Yang
Cc: Chris Wilson
Cc: Matt Roper
Cc: Andi Shyti
Reviewed-by: Andi Shyti
Tested-by: Jordan Justen
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 36 +++
drivers/gpu/drm/i915/gem/i915_gem_object.c | 6
include/uapi/drm/i915_drm.h| 42 ++
tools/include/uapi/drm/i915_drm.h | 42 ++
4 files changed, 126 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index bfe1dbda4cb7..644a936248ad 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -245,6 +245,7 @@ struct create_ext {
unsigned int n_placements;
unsigned int placement_mask;
unsigned long flags;
+ unsigned int pat_index;
};
static void repr_placements(char *buf, size_t size,
@@ -394,11 +395,39 @@ static int ext_set_protected(struct i915_user_extension
__user *base, void *data
return 0;
}
+static int ext_set_pat(struct i915_user_extension __user *base, void *data)
+{
+ struct create_ext *ext_data = data;
+ struct drm_i915_private *i915 = ext_data->i915;
+ struct drm_i915_gem_create_ext_set_pat ext;
+ unsigned int max_pat_index;
+
+ BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=
+offsetofend(struct drm_i915_gem_create_ext_set_pat, rsvd));
+
+ if (copy_from_user(, base, sizeof(ext)))
+ return -EFAULT;
+
+ max_pat_index = INTEL_INFO(i915)->max_pat_index;
+
+ if (ext.pat_index > max_pat_index) {
+ drm_dbg(>drm, "PAT index is invalid: %u\n",
+ ext.pat_index);
+ return -EINVAL;
+ }
+
+ ext_data->pat_index = ext.pat_index;
+
+ return 0;
+}
+
static const i915_user_extension_fn create_extensions[] = {
[I915_GEM_CREATE_EXT_MEMORY_REGIONS] = ext_set_placements,
[I915_GEM_CREATE_EXT_PROTECTED_CONTENT] = ext_set_protected,
+ [I915_GEM_CREATE_EXT_SET_PAT] = ext_set_pat,
};
+#define PAT_INDEX_NOT_SET 0x
/**
* i915_gem_create_ext_ioctl - Creates a new mm object and returns a handle to
it.
* @dev: drm device pointer
@@ -418,6 +447,7 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void
*data,
if (args->flags & ~I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS)
return -EINVAL;
+ ext_data.pat_index = PAT_INDEX_NOT_SET;
ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
create_extensions,
ARRAY_SIZE(create_extensions),
@@ -454,5 +484,11 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void
*data,
if (IS_ERR(obj))
return PTR_ERR(obj);
+ if (ext_data.pat_index != PAT_INDEX_NOT_SET) {
+ i915_gem_object_set_pat_index(obj, ext_data.pat_index);
+ /* Mark pat_index is set by UMD */
+ obj->pat_set_by_user = true;
+ }
+
return i915_gem_publish(obj, file, >size, >handle);
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 46a19b099ec8..97ac6fb37958 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -208,6 +208,12 @@ bool i915_gem_object_can_bypass_llc(struct
drm_i915_gem_object *obj)
if (!(obj->flags & I915_BO_ALLOC_USER))
return false;
+ /*
+* Always flush cache for UMD objects at creation time.
+*/
+ if (obj->pat_set_by_user)
+ return true;
+
/*
* EHL and JSL add the 'Bypass LLC' MOCS entry, which should make it
* possible for userspace to bypass the GTT caching bits set by the
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index ba40855dbc93..4f3fd650e5e1 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -3664,9 +3664,13 @@ struct
[Intel-gfx] [PATCH v9 0/2] drm/i915: Allow user to set cache at BO creation
From: Fei Yang
This series introduce a new extension for GEM_CREATE,
1. end support for set caching ioctl [PATCH 4/5]
2. add set_pat extension for gem_create [PATCH 5/5]
v2: drop one patch that was merged separately
commit 341ad0e8e254 ("drm/i915/mtl: Add PTE encode function")
v3: rebased on https://patchwork.freedesktop.org/series/117082/
v4: fix missing unlock introduced in v3, and
solve a rebase conflict
v5: replace obj->cache_level with pat_set_by_user,
fix i915_cache_level_str() for legacy platforms.
v6: rebased on https://patchwork.freedesktop.org/series/117480/
v7: rebased on https://patchwork.freedesktop.org/series/117528/
v8: dropped the two dependent patches that has been merged
separately. Add IGT link and Tested-by (MESA).
v9: addressing comments (Andi)
Fei Yang (2):
drm/i915/mtl: end support for set caching ioctl
drm/i915: Allow user to set cache at BO creation
drivers/gpu/drm/i915/gem/i915_gem_create.c | 36 +++
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 ++
drivers/gpu/drm/i915/gem/i915_gem_object.c | 6
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 9 -
include/uapi/drm/i915_drm.h| 42 ++
tools/include/uapi/drm/i915_drm.h | 42 ++
6 files changed, 137 insertions(+), 1 deletion(-)
--
2.25.1
Re: [Intel-gfx] [PATCH v5 6/8] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
> Subject: [PATCH v5 6/8] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR)
> parameters
>
> The array of rc_parameters contains a mixture of parameters from DSC 1.1
> and DSC 1.2 standards. Split these tow configuration arrays in preparation to
> adding more configuration data.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 127 ++
> drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
> include/drm/display/drm_dsc_helper.h | 7 +-
> 3 files changed, 119 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c
> b/drivers/gpu/drm/display/drm_dsc_helper.c
> index acb93d4116e0..35b39f3109c4 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -324,11 +324,81 @@ struct rc_parameters_data {
>
> #define DSC_BPP(bpp) ((bpp) << 4)
>
Maybe comment here mentioning the DSC version and the C Model
we follow would be useful
> +static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> + {
> + .bpp = DSC_BPP(8), .bpc = 8,
> + { 512, 12, 6144, 3, 12, 11, 11, {
> + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12,
> -12 },
> + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(8), .bpc = 10,
> + { 512, 12, 6144, 7, 16, 15, 15, {
> + /*
> + * DSC model/pre-SCR-cfg has 8 for
> range_max_qp[0], however
> + * VESA DSC 1.1 Table E-5 sets it to 4.
> + */
> + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12,
> -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16,
> -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(8), .bpc = 12,
> + { 512, 12, 6144, 11, 20, 19, 19, {
> + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11,
> 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 8,
> + { 341, 15, 2048, 3, 12, 11, 11, {
> + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13,
> 15, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 10,
> + { 341, 15, 2048, 7, 16, 15, 15, {
> + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8
> },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16,
> -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 12,
> + { 341, 15, 2048, 11, 20, 19, 19, {
> + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11,
> 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> + },
> + { /* sentinel */ }
> +};
> +
> /*
> * Selected Rate Control Related Parameter Recommended Values
> * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> */
The above comment shouldn't be above this function anymore since
This represent dsc_v1.2 I presume maybe move this comment above
and add a new comment for this function.
> -static const struct rc_parameters_data rc_parameters[] = {
> +static const struct rc_parameters_data rc_parameters_1_2_444[] = {
> {
> .bpp = DSC_BPP(6), .bpc = 8,
> { 768, 15, 6144, 3, 13, 11, 11, {
> @@ -388,22 +458,18 @@ static const struct rc_parameters_data
> rc_parameters[] = {
> { 512, 12, 6144, 3, 12, 11, 11, {
> {
Re: [Intel-gfx] [PATCH] drm/i915/pmu: Change bitmask of enabled events to u32
On Tue, 16 May 2023 02:24:45 -0700, Tvrtko Ursulin wrote:
>
> From: Tvrtko Ursulin
>
> Having it as u64 was a confusing (but harmless) mistake.
>
> Also add some asserts to make sure the internal field does not overflow
> in the future.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Ashutosh Dixit
> Cc: Umesh Nerlige Ramappa
> ---
> I am not entirely sure the __builtin_constant_p->BUILD_BUG_ON branch will
> work with all compilers. Lets see...
>
> Compile tested only.
> ---
> drivers/gpu/drm/i915/i915_pmu.c | 32 ++--
> 1 file changed, 22 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> index 7ece883a7d95..8736b3418f88 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -50,7 +50,7 @@ static u8 engine_event_instance(struct perf_event *event)
> return (event->attr.config >> I915_PMU_SAMPLE_BITS) & 0xff;
> }
>
> -static bool is_engine_config(u64 config)
> +static bool is_engine_config(const u64 config)
> {
> return config < __I915_PMU_OTHER(0);
> }
> @@ -82,15 +82,28 @@ static unsigned int other_bit(const u64 config)
>
> static unsigned int config_bit(const u64 config)
> {
> + unsigned int bit;
> +
> if (is_engine_config(config))
> - return engine_config_sample(config);
> + bit = engine_config_sample(config);
> else
> - return other_bit(config);
> + bit = other_bit(config);
> +
> + if (__builtin_constant_p(config))
> + BUILD_BUG_ON(bit >
> + BITS_PER_TYPE(typeof_member(struct i915_pmu,
> + enable)) - 1);
Given that config comes from the event (it is event->attr.config), can this
ever be a builtin constant?
> + else
> + WARN_ON_ONCE(bit >
> + BITS_PER_TYPE(typeof_member(struct i915_pmu,
> + enable)) - 1);
There is really an even stricter limit on what the bit can be, which is the
total number of possible events but anyway this is good enough. So this
patch is:
Reviewed-by: Ashutosh Dixit
> +
> + return bit;
> }
>
> -static u64 config_mask(u64 config)
> +static u32 config_mask(const u64 config)
> {
> - return BIT_ULL(config_bit(config));
> + return BIT(config_bit(config));
> }
>
> static bool is_engine_event(struct perf_event *event)
> @@ -633,11 +646,10 @@ static void i915_pmu_enable(struct perf_event *event)
> {
> struct drm_i915_private *i915 =
> container_of(event->pmu, typeof(*i915), pmu.base);
> + const unsigned int bit = event_bit(event);
> struct i915_pmu *pmu = >pmu;
> unsigned long flags;
> - unsigned int bit;
>
> - bit = event_bit(event);
> if (bit == -1)
> goto update;
>
> @@ -651,7 +663,7 @@ static void i915_pmu_enable(struct perf_event *event)
> GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count));
> GEM_BUG_ON(pmu->enable_count[bit] == ~0);
>
> - pmu->enable |= BIT_ULL(bit);
> + pmu->enable |= BIT(bit);
> pmu->enable_count[bit]++;
>
> /*
> @@ -698,7 +710,7 @@ static void i915_pmu_disable(struct perf_event *event)
> {
> struct drm_i915_private *i915 =
> container_of(event->pmu, typeof(*i915), pmu.base);
> - unsigned int bit = event_bit(event);
> + const unsigned int bit = event_bit(event);
> struct i915_pmu *pmu = >pmu;
> unsigned long flags;
>
> @@ -734,7 +746,7 @@ static void i915_pmu_disable(struct perf_event *event)
>* bitmask when the last listener on an event goes away.
>*/
> if (--pmu->enable_count[bit] == 0) {
> - pmu->enable &= ~BIT_ULL(bit);
> + pmu->enable &= ~BIT(bit);
> pmu->timer_enabled &= pmu_needs_timer(pmu, true);
> }
>
> --
> 2.39.2
>
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/syncmap: squelch a sparse warning
== Series Details ==
Series: drm/i915/syncmap: squelch a sparse warning
URL : https://patchwork.freedesktop.org/series/117802/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13151_full -> Patchwork_117802v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_117802v1_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_ctx_isolation@preservation-s3@vecs0:
- {shard-dg1}:[PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-dg1-17/igt@gem_ctx_isolation@preservation...@vecs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117802v1/shard-dg1-16/igt@gem_ctx_isolation@preservation...@vecs0.html
Known issues
Here are the changes found in Patchwork_117802v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_barrier_race@remote-request@rcs0:
- shard-apl: [PASS][3] -> [ABORT][4] ([i915#7461] / [i915#8211] /
[i915#8234])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-apl3/igt@gem_barrier_race@remote-requ...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117802v1/shard-apl2/igt@gem_barrier_race@remote-requ...@rcs0.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][5] -> [FAIL][6] ([i915#2346])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-glk4/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117802v1/shard-glk2/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
Possible fixes
* igt@gem_exec_fair@basic-none@bcs0:
- {shard-rkl}:[FAIL][7] ([i915#2842]) -> [PASS][8] +2 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-rkl-7/igt@gem_exec_fair@basic-n...@bcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117802v1/shard-rkl-2/igt@gem_exec_fair@basic-n...@bcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][9] ([i915#2842]) -> [PASS][10] +1 similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117802v1/shard-glk3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- {shard-dg1}:[FAIL][11] ([i915#3591]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117802v1/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- {shard-rkl}:[SKIP][13] ([i915#1397]) -> [PASS][14] +1 similar
issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-rkl-6/igt@i915_pm_...@dpms-mode-unset-lpsp.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117802v1/shard-rkl-7/igt@i915_pm_...@dpms-mode-unset-lpsp.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-apl: [FAIL][15] ([i915#2346]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-apl4/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117802v1/shard-apl4/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1:
- shard-glk: [FAIL][17] ([i915#79]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-hdmi-a1.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117802v1/shard-glk6/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1:
- shard-apl: [FAIL][19] ([i915#79]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-apl1/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-dp1.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117802v1/shard-apl7/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-dp1.html
* igt@perf_pmu@idle@rcs0:
- {shard-dg1}:[FAIL][21] ([i915#4349]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-dg1-13/igt@perf_pmu@i...@rcs0.html
[22]:
Re: [Intel-gfx] [PATCH 4/6] drm/i915/pmu: Add reference counting to the sampling timer
On Tue, 16 May 2023 00:12:45 -0700, Tvrtko Ursulin wrote:
>
> On 15/05/2023 22:24, Dixit, Ashutosh wrote:
> > On Mon, 15 May 2023 02:52:35 -0700, Tvrtko Ursulin wrote:
> >>
> >> On 13/05/2023 00:44, Umesh Nerlige Ramappa wrote:
> >>> On Fri, May 12, 2023 at 04:20:19PM -0700, Dixit, Ashutosh wrote:
> On Fri, 12 May 2023 15:44:00 -0700, Umesh Nerlige Ramappa wrote:
> >
> > On Fri, May 12, 2023 at 03:29:03PM -0700, Dixit, Ashutosh wrote:
> >> On Fri, 05 May 2023 17:58:14 -0700, Umesh Nerlige Ramappa wrote:
> >>>
> >>
> >> Hi Umesh/Tvrtko,
> >>
> >>> From: Tvrtko Ursulin
> >>>
> >>> We do not want to have timers per tile and waste CPU cycles and
> > energy via
> >>> multiple wake-up sources, for a relatively un-important task of PMU
> >>> sampling, so keeping a single timer works well. But we also do not
> > want
> >>> the first GT which goes idle to turn off the timer.
> >>>
> >>> Add some reference counting, via a mask of unparked GTs, to solve
> > this.
> >>>
> >>> Signed-off-by: Tvrtko Ursulin
> >>> Signed-off-by: Umesh Nerlige Ramappa
> >
> >>> ---
> >>> drivers/gpu/drm/i915/i915_pmu.c | 12 ++--
> >>> drivers/gpu/drm/i915/i915_pmu.h | 4
> >>> 2 files changed, 14 insertions(+), 2 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/i915_pmu.c
> > b/drivers/gpu/drm/i915/i915_pmu.c
> >>> index 2b63ee31e1b3..669a42e44082 100644
> >>> --- a/drivers/gpu/drm/i915/i915_pmu.c
> >>> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> >>> @@ -251,7 +251,9 @@ void i915_pmu_gt_parked(struct intel_gt *gt)
> >>> * Signal sampling timer to stop if only engine events are
> > enabled and
> >>> * GPU went idle.
> >>> */
> >>> - pmu->timer_enabled = pmu_needs_timer(pmu, false);
> >>> + pmu->unparked &= ~BIT(gt->info.id);
> >>> + if (pmu->unparked == 0)
> >>> + pmu->timer_enabled = pmu_needs_timer(pmu, false);
> >>>
> >>> spin_unlock_irq(>lock);
> >>> }
> >>> @@ -268,7 +270,10 @@ void i915_pmu_gt_unparked(struct intel_gt *gt)
> >>> /*
> >>> * Re-enable sampling timer when GPU goes active.
> >>> */
> >>> - __i915_pmu_maybe_start_timer(pmu);
> >>> + if (pmu->unparked == 0)
> >>> + __i915_pmu_maybe_start_timer(pmu);
> >>> +
> >>> + pmu->unparked |= BIT(gt->info.id);
> >>>
> >>> spin_unlock_irq(>lock);
> >>> }
> >>> @@ -438,6 +443,9 @@ static enum hrtimer_restart i915_sample(struct
> > hrtimer *hrtimer)
> >>> */
> >>>
> >>> for_each_gt(gt, i915, i) {
> >>> + if (!(pmu->unparked & BIT(i)))
> >>> + continue;
> >>> +
> >>
> >> This is not correct. In this series we are at least sampling
> > frequencies
> >> (calling frequency_sample) even when GT is parked. So these 3 lines
> > should be
> >> deleted. engines_sample will get called and will return without doing
> >> anything if engine events are disabled.
> >
> > Not sure I understand. This is checking pmu->'un'parked bits.
>
> Sorry, my bad. Not "engines_sample will get called and will return
> without
> doing anything if engine events are disabled" but "engines_sample will
> get
> called and will return without doing anything if GT is not awake". This
> is
> the same as the previous behavior before this series.
>
> Umesh and I discussed this but writing this out in case Tvrtko takes a
> look.
> >>>
> >>> Sounds good, Dropping the check here in the new revision.
> >
> > Hi Tvrtko,
> >
> >> I think it is safe to not have the check, but I didn't quite understand the
> >> "this is not correct" part. I can only see the argument that it could be
> >> redundant, not that it is incorrect.
> >
> > I said that it looks incorrect to me because in this series we are still
> > sampling freq when gt is parked and we would be skipping that if we
> > included:
> > if (!(pmu->unparked & BIT(i)))
> > continue;
>
> Ah okay. We concluded in your upstream patch that looks like an omission.
>
> >> In which case I think it should better stay since it is way more efficient,
> >> given this gets called at 200Hz, than the *atomic* atomic_inc_not_zero
> >> (from intel_wakeref_get_if_active).
> >
> > Where efficiency goes, when we merge the patch below (I have a v2 based on
> > your suggestion but I am waiting till Umesh's series gets merged):
> >
> > https://patchwork.freedesktop.org/series/117658/
> >
> > this will turn off the timer itself which will be even more
> > efficient. Rather than use the above code where the timer is running and
> > then we skip. So after the link above is merged the above code will be
> > truly redundant. That was a second reason why I said delete it.
>
> On multi-tile
Re: [Intel-gfx] [PATCH] drm/ttm: let struct ttm_device_funcs be placed in rodata
On Tue, May 16, 2023 at 4:05 AM Jani Nikula wrote:
>
> On Thu, 09 Mar 2023, Jani Nikula wrote:
> > On Thu, 09 Mar 2023, Christian König wrote:
> >> Am 09.03.23 um 13:37 schrieb Jani Nikula:
> >>> Make the struct ttm_device_funcs pointers const so the data can be placed
> >>> in rodata.
> >>>
> >>> Cc: Christian Koenig
> >>> Cc: Huang Rui
> >>> Signed-off-by: Jani Nikula
> >>
> >> Good idea, Reviewed-by: Christian König
> >
> > Thanks!
> >
> >> Should I push it to drm-misc-next or do you need it on some other branch?
> >
> > Go ahead, I'm not urgently depending on it.
>
> Christian, I guess this fell between the cracks? Can I just push it to
> drm-misc-next?
Go ahead. Christian is out of the office this week.
Alex
>
> BR,
> Jani.
>
>
> >
> > BR,
> > Jani.
> >
> >>
> >> Christian.
> >>
> >>> ---
> >>> drivers/gpu/drm/ttm/ttm_device.c | 2 +-
> >>> include/drm/ttm/ttm_device.h | 4 ++--
> >>> 2 files changed, 3 insertions(+), 3 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/ttm/ttm_device.c
> >>> b/drivers/gpu/drm/ttm/ttm_device.c
> >>> index ae2f19dc9f81..a71bb1362de4 100644
> >>> --- a/drivers/gpu/drm/ttm/ttm_device.c
> >>> +++ b/drivers/gpu/drm/ttm/ttm_device.c
> >>> @@ -190,7 +190,7 @@ EXPORT_SYMBOL(ttm_device_swapout);
> >>>* Returns:
> >>>* !0: Failure.
> >>>*/
> >>> -int ttm_device_init(struct ttm_device *bdev, struct ttm_device_funcs
> >>> *funcs,
> >>> +int ttm_device_init(struct ttm_device *bdev, const struct
> >>> ttm_device_funcs *funcs,
> >>> struct device *dev, struct address_space *mapping,
> >>> struct drm_vma_offset_manager *vma_manager,
> >>> bool use_dma_alloc, bool use_dma32)
> >>> diff --git a/include/drm/ttm/ttm_device.h b/include/drm/ttm/ttm_device.h
> >>> index 56e82ba2d046..c22f30535c84 100644
> >>> --- a/include/drm/ttm/ttm_device.h
> >>> +++ b/include/drm/ttm/ttm_device.h
> >>> @@ -223,7 +223,7 @@ struct ttm_device {
> >>> * @funcs: Function table for the device.
> >>> * Constant after bo device init
> >>> */
> >>> - struct ttm_device_funcs *funcs;
> >>> + const struct ttm_device_funcs *funcs;
> >>>
> >>> /**
> >>> * @sysman: Resource manager for the system domain.
> >>> @@ -287,7 +287,7 @@ static inline void ttm_set_driver_manager(struct
> >>> ttm_device *bdev, int type,
> >>> bdev->man_drv[type] = manager;
> >>> }
> >>>
> >>> -int ttm_device_init(struct ttm_device *bdev, struct ttm_device_funcs
> >>> *funcs,
> >>> +int ttm_device_init(struct ttm_device *bdev, const struct
> >>> ttm_device_funcs *funcs,
> >>> struct device *dev, struct address_space *mapping,
> >>> struct drm_vma_offset_manager *vma_manager,
> >>> bool use_dma_alloc, bool use_dma32);
> >>
>
> --
> Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH] drm/ttm: let struct ttm_device_funcs be placed in rodata
Am 09.03.23 um 13:37 schrieb Jani Nikula:
Make the struct ttm_device_funcs pointers const so the data can be placed in
rodata.
Cc: Christian Koenig
Cc: Huang Rui
Signed-off-by: Jani Nikula
Reviewed-by: Thomas Zimmermann
---
drivers/gpu/drm/ttm/ttm_device.c | 2 +-
include/drm/ttm/ttm_device.h | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c
index ae2f19dc9f81..a71bb1362de4 100644
--- a/drivers/gpu/drm/ttm/ttm_device.c
+++ b/drivers/gpu/drm/ttm/ttm_device.c
@@ -190,7 +190,7 @@ EXPORT_SYMBOL(ttm_device_swapout);
* Returns:
* !0: Failure.
*/
-int ttm_device_init(struct ttm_device *bdev, struct ttm_device_funcs *funcs,
+int ttm_device_init(struct ttm_device *bdev, const struct ttm_device_funcs
*funcs,
struct device *dev, struct address_space *mapping,
struct drm_vma_offset_manager *vma_manager,
bool use_dma_alloc, bool use_dma32)
diff --git a/include/drm/ttm/ttm_device.h b/include/drm/ttm/ttm_device.h
index 56e82ba2d046..c22f30535c84 100644
--- a/include/drm/ttm/ttm_device.h
+++ b/include/drm/ttm/ttm_device.h
@@ -223,7 +223,7 @@ struct ttm_device {
* @funcs: Function table for the device.
* Constant after bo device init
*/
- struct ttm_device_funcs *funcs;
+ const struct ttm_device_funcs *funcs;
/**
* @sysman: Resource manager for the system domain.
@@ -287,7 +287,7 @@ static inline void ttm_set_driver_manager(struct ttm_device
*bdev, int type,
bdev->man_drv[type] = manager;
}
-int ttm_device_init(struct ttm_device *bdev, struct ttm_device_funcs *funcs,
+int ttm_device_init(struct ttm_device *bdev, const struct ttm_device_funcs
*funcs,
struct device *dev, struct address_space *mapping,
struct drm_vma_offset_manager *vma_manager,
bool use_dma_alloc, bool use_dma32);
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Frankenstrasse 146, 90461 Nuernberg, Germany
GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman
HRB 36809 (AG Nuernberg)
OpenPGP_signature
Description: OpenPGP digital signature
Re: [Intel-gfx] [PATCH i-g-t v2] tests/i915: Exercise coherency of mmapped frame buffers
Hi Andrzej,
Thanks for review.
On Tuesday, 16 May 2023 16:08:26 CEST Andrzej Hajda wrote:
> On 16.05.2023 12:05, Janusz Krzysztofik wrote:
> > Visible glitches have been observed when running graphics applications on
> > Linux under Xen hypervisor. Those observations have been confirmed with
> > failures from kms_pwrite_crc IGT test that verifies data coherency of DRM
> > frame buffer objects using hardware CRC checksums calculated by display
> > controllers, exposed to userspace via debugfs. Since not all applications
> > exhibit the issue, we need to exercise more methods than just pwrite in
> > order to identify all affected processing paths.
> >
> > Create a new test focused on exercising coherency of future scanout
> > buffers populated over mmap. Cover all available mmap methods and caching
> > modes expected to be device coherent.
> >
> > v2: Drop unused functions -- left-overs from unsuccessful negative subtest
> > attempts requiring consistent crc mismatches in non-coherent modes,
> >- since all subtests now call igt_assert_crc_equal(), move it from
> > subtest bodies to an updated and renamed helper,
> >- drop "derived from ..." info from copyrights comment (Kamil),
> >- fix order of includes (Kamil),
> >- fix whitespace (Kamil),
> >- Cc: Bhanuprakash (Kamil).
> >
> > Link: https://gitlab.freedesktop.org/drm/intel/-/issues/7648
> > Signed-off-by: Janusz Krzysztofik
> > Cc: Bhanuprakash Modem
> > ---
> > tests/i915/kms_fb_coherency.c | 305 ++
> > tests/meson.build | 1 +
> > 2 files changed, 306 insertions(+)
> > create mode 100644 tests/i915/kms_fb_coherency.c
> >
> > diff --git a/tests/i915/kms_fb_coherency.c b/tests/i915/kms_fb_coherency.c
> > new file mode 100644
> > index 00..b3f055c2b1
> > --- /dev/null
> > +++ b/tests/i915/kms_fb_coherency.c
> > @@ -0,0 +1,305 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2023 Intel Corporation
> > + */
> > +
> > +/**
> > + * TEST: kms_fb_coherency
> > + * Description: Exercise coherency of future scanout buffer objects
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +#include "igt.h"
> > +
> > +typedef struct {
> > + int drm_fd;
> > + igt_display_t display;
> > + struct igt_fb fb[2];
> > + igt_output_t *output;
> > + igt_plane_t *primary;
> > + enum pipe pipe;
> > + igt_crc_t ref_crc;
> > + igt_pipe_crc_t *pipe_crc;
> > + uint32_t devid;
> > +} data_t;
> > +
> > +static void prepare_crtc(data_t *data)
> > +{
> > + igt_display_t *display = >display;
> > + igt_output_t *output = data->output;
> > + drmModeModeInfo *mode;
> > +
> > + igt_display_reset(display);
> > + /* select the pipe we want to use */
> > + igt_output_set_pipe(output, data->pipe);
> > +
> > + mode = igt_output_get_mode(output);
> > +
> > + /* create a white reference fb and flip to it */
> > + igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
> > + DRM_FORMAT_XRGB, DRM_FORMAT_MOD_LINEAR,
> > + 1.0, 1.0, 1.0, >fb[0]);
> > +
> > + data->primary = igt_output_get_plane_type(output,
> > DRM_PLANE_TYPE_PRIMARY);
> > +
> > + igt_plane_set_fb(data->primary, >fb[0]);
> > + igt_display_commit(display);
> > +
> > + if (data->pipe_crc)
> > + igt_pipe_crc_free(data->pipe_crc);
> > +
> > + data->pipe_crc = igt_pipe_crc_new(data->drm_fd, data->pipe,
> > + IGT_PIPE_CRC_SOURCE_AUTO);
> > +
> > + /* get reference crc for the white fb */
> > + igt_pipe_crc_collect_crc(data->pipe_crc, >ref_crc);
> > +}
> > +
> > +static struct igt_fb *prepare_fb(data_t *data)
> > +{
> > + igt_output_t *output = data->output;
> > + struct igt_fb *fb = >fb[1];
> > + drmModeModeInfo *mode;
> > +
> > + prepare_crtc(data);
> > +
> > + mode = igt_output_get_mode(output);
> > +
> > + /* create a non-white fb we can overwrite later */
> > + igt_create_pattern_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
> > + DRM_FORMAT_XRGB, DRM_FORMAT_MOD_LINEAR, fb);
> > +
> > + /* flip to it to make it UC/WC and fully flushed */
> > + drmModeSetPlane(data->drm_fd,
> > + data->primary->drm_plane->plane_id,
> > + output->config.crtc->crtc_id,
> > + fb->fb_id, 0,
> > + 0, 0, fb->width, fb->height,
> > + 0, 0, fb->width << 16, fb->height << 16);
> > +
> > + /* flip back the original white buffer */
> > + drmModeSetPlane(data->drm_fd,
> > + data->primary->drm_plane->plane_id,
> > + output->config.crtc->crtc_id,
> > + data->fb[0].fb_id, 0,
> > + 0, 0, fb->width, fb->height,
> > + 0, 0, fb->width << 16, fb->height << 16);
> > +
> > + if (!gem_has_lmem(data->drm_fd)) {
> > +
[Intel-gfx] [PATCH] drm/i915/guc/slpc: Disable rps_boost debugfs
rps_boost debugfs shows host turbo related info. This is not valid
when SLPC is enabled. guc_slpc_info already shows the number of boosts.
Add num_waiters there as well and disable rps_boost when SLPC is
enabled.
v2: Replace Bug with Link to resolve checkpatch warning
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/7632
Reviewed-by: Ashutosh Dixit
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 5 -
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 2 ++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 80dbbef86b1d..357e2f865727 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -539,7 +539,10 @@ static bool rps_eval(void *data)
{
struct intel_gt *gt = data;
- return HAS_RPS(gt->i915);
+ if (intel_guc_slpc_is_used(>uc.guc))
+ return false;
+ else
+ return HAS_RPS(gt->i915);
}
DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(rps_boost);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 56dbba1ef668..01b75529311c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -837,6 +837,8 @@ int intel_guc_slpc_print_info(struct intel_guc_slpc *slpc,
struct drm_printer *p
slpc_decode_min_freq(slpc));
drm_printf(p, "\twaitboosts: %u\n",
slpc->num_boosts);
+ drm_printf(p, "\tBoosts outstanding: %u\n",
+ atomic_read(>num_waiters));
}
}
--
2.38.1
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: constify pointers to hwmon_channel_info (rev2)
== Series Details ==
Series: drm/i915: constify pointers to hwmon_channel_info (rev2)
URL : https://patchwork.freedesktop.org/series/117750/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13151_full -> Patchwork_117750v2_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_117750v2_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][1] -> [FAIL][2] ([i915#2346])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-glk4/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117750v2/shard-glk1/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [PASS][3] -> [FAIL][4] ([i915#2346])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-apl2/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117750v2/shard-apl2/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
Possible fixes
* igt@gem_exec_fair@basic-none@vcs0:
- {shard-rkl}:[FAIL][5] ([i915#2842]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-rkl-7/igt@gem_exec_fair@basic-n...@vcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117750v2/shard-rkl-7/igt@gem_exec_fair@basic-n...@vcs0.html
* igt@i915_pm_dc@dc9-dpms:
- {shard-tglu}: [SKIP][7] ([i915#4281]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-tglu-6/igt@i915_pm...@dc9-dpms.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117750v2/shard-tglu-4/igt@i915_pm...@dc9-dpms.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- {shard-dg1}:[FAIL][9] ([i915#3591]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117750v2/shard-dg1-13/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- {shard-rkl}:[SKIP][11] ([i915#1397]) -> [PASS][12] +1 similar
issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-rkl-6/igt@i915_pm_...@dpms-mode-unset-lpsp.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117750v2/shard-rkl-7/igt@i915_pm_...@dpms-mode-unset-lpsp.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1:
- shard-glk: [FAIL][13] ([i915#79]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-hdmi-a1.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117750v2/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1:
- shard-apl: [FAIL][15] ([i915#79]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-apl1/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-dp1.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117750v2/shard-apl6/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-dp1.html
* igt@perf_pmu@idle@rcs0:
- {shard-dg1}:[FAIL][17] ([i915#4349]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/shard-dg1-13/igt@perf_pmu@i...@rcs0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117750v2/shard-dg1-18/igt@perf_pmu@i...@rcs0.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4579]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: fix intel_display_irq.c include order
== Series Details ==
Series: drm/i915: fix intel_display_irq.c include order
URL : https://patchwork.freedesktop.org/series/117816/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13151 -> Patchwork_117816v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117816v1/index.html
Participating hosts (38 -> 37)
--
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_117816v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@load:
- bat-adls-5: [PASS][1] -> [ABORT][2] ([i915#4391])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-adls-5/igt@i915_module_l...@load.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117816v1/bat-adls-5/igt@i915_module_l...@load.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][3] ([i915#6367])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117816v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: NOTRUN -> [ABORT][4] ([i915#6687])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117816v1/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html
Possible fixes
* igt@i915_pm_rpm@basic-rte:
- {bat-mtlp-8}: [TIMEOUT][5] -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-mtlp-8/igt@i915_pm_...@basic-rte.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117816v1/bat-mtlp-8/igt@i915_pm_...@basic-rte.html
* igt@i915_selftest@live@requests:
- {bat-mtlp-8}: [ABORT][7] ([i915#4983] / [i915#7920] / [i915#7953])
-> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-mtlp-8/igt@i915_selftest@l...@requests.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117816v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html
* igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][9] ([i915#4983] / [i915#7461] / [i915#7913] /
[i915#8347]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-rpls-2/igt@i915_selftest@l...@reset.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117816v1/bat-rpls-2/igt@i915_selftest@l...@reset.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck@pipe-d-dp-1:
- bat-dg2-8: [FAIL][11] ([i915#7932]) -> [PASS][12] +2 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-dg2-8/igt@kms_pipe_crc_basic@compare-crc-sanitych...@pipe-d-dp-1.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117816v1/bat-dg2-8/igt@kms_pipe_crc_basic@compare-crc-sanitych...@pipe-d-dp-1.html
Warnings
* igt@i915_selftest@live@slpc:
- bat-rpls-1: [DMESG-WARN][13] ([i915#6367] / [i915#7953]) ->
[DMESG-WARN][14] ([i915#6367])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-rpls-1/igt@i915_selftest@l...@slpc.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117816v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-tgl-1115g4: [INCOMPLETE][15] ([i915#7443] / [i915#7953] /
[i915#8102]) -> [INCOMPLETE][16] ([i915#7443] / [i915#8102])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/fi-tgl-1115g4/igt@i915_susp...@basic-s3-without-i915.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117816v1/fi-tgl-1115g4/igt@i915_susp...@basic-s3-without-i915.html
- bat-rpls-1: [ABORT][17] ([i915#6687] / [i915#7953] / [i915#7978])
-> [ABORT][18] ([i915#6687] / [i915#7978])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117816v1/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
[i915#7932]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Use large rings for compute contexts
== Series Details ==
Series: drm/i915/gem: Use large rings for compute contexts
URL : https://patchwork.freedesktop.org/series/117814/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13151 -> Patchwork_117814v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v1/index.html
Participating hosts (38 -> 37)
--
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_117814v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@load:
- bat-adls-5: [PASS][1] -> [ABORT][2] ([i915#4391])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-adls-5/igt@i915_module_l...@load.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v1/bat-adls-5/igt@i915_module_l...@load.html
* igt@i915_selftest@live@gt_engines:
- bat-atsm-1: [PASS][3] -> [FAIL][4] ([i915#6268])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-atsm-1/igt@i915_selftest@live@gt_engines.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v1/bat-atsm-1/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@hangcheck:
- bat-dg2-11: [PASS][5] -> [ABORT][6] ([i915#7913] / [i915#7979])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v1/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- bat-rpls-1: [PASS][7] -> [ABORT][8] ([i915#4983] / [i915#7911] /
[i915#7920])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-rpls-1/igt@i915_selftest@l...@requests.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v1/bat-rpls-1/igt@i915_selftest@l...@requests.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][9] ([i915#6367])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: NOTRUN -> [ABORT][10] ([i915#6687])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v1/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#1845] / [i915#5354])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
Possible fixes
* igt@i915_pm_rpm@basic-rte:
- {bat-mtlp-8}: [TIMEOUT][12] -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-mtlp-8/igt@i915_pm_...@basic-rte.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v1/bat-mtlp-8/igt@i915_pm_...@basic-rte.html
* igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][14] ([i915#4983] / [i915#7461] / [i915#7913]
/ [i915#8347]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-rpls-2/igt@i915_selftest@l...@reset.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v1/bat-rpls-2/igt@i915_selftest@l...@reset.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
- bat-dg2-8: [FAIL][16] ([i915#7932]) -> [PASS][17] +1 similar
issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
Warnings
* igt@i915_suspend@basic-s3-without-i915:
- fi-tgl-1115g4: [INCOMPLETE][18] ([i915#7443] / [i915#7953] /
[i915#8102]) -> [INCOMPLETE][19] ([i915#7443] / [i915#8102])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/fi-tgl-1115g4/igt@i915_susp...@basic-s3-without-i915.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v1/fi-tgl-1115g4/igt@i915_susp...@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
Re: [Intel-gfx] [PATCH i-g-t v2] tests/i915: Exercise coherency of mmapped frame buffers
On 16.05.2023 12:05, Janusz Krzysztofik wrote:
Visible glitches have been observed when running graphics applications on
Linux under Xen hypervisor. Those observations have been confirmed with
failures from kms_pwrite_crc IGT test that verifies data coherency of DRM
frame buffer objects using hardware CRC checksums calculated by display
controllers, exposed to userspace via debugfs. Since not all applications
exhibit the issue, we need to exercise more methods than just pwrite in
order to identify all affected processing paths.
Create a new test focused on exercising coherency of future scanout
buffers populated over mmap. Cover all available mmap methods and caching
modes expected to be device coherent.
v2: Drop unused functions -- left-overs from unsuccessful negative subtest
attempts requiring consistent crc mismatches in non-coherent modes,
- since all subtests now call igt_assert_crc_equal(), move it from
subtest bodies to an updated and renamed helper,
- drop "derived from ..." info from copyrights comment (Kamil),
- fix order of includes (Kamil),
- fix whitespace (Kamil),
- Cc: Bhanuprakash (Kamil).
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/7648
Signed-off-by: Janusz Krzysztofik
Cc: Bhanuprakash Modem
---
tests/i915/kms_fb_coherency.c | 305 ++
tests/meson.build | 1 +
2 files changed, 306 insertions(+)
create mode 100644 tests/i915/kms_fb_coherency.c
diff --git a/tests/i915/kms_fb_coherency.c b/tests/i915/kms_fb_coherency.c
new file mode 100644
index 00..b3f055c2b1
--- /dev/null
+++ b/tests/i915/kms_fb_coherency.c
@@ -0,0 +1,305 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+/**
+ * TEST: kms_fb_coherency
+ * Description: Exercise coherency of future scanout buffer objects
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "igt.h"
+
+typedef struct {
+ int drm_fd;
+ igt_display_t display;
+ struct igt_fb fb[2];
+ igt_output_t *output;
+ igt_plane_t *primary;
+ enum pipe pipe;
+ igt_crc_t ref_crc;
+ igt_pipe_crc_t *pipe_crc;
+ uint32_t devid;
+} data_t;
+
+static void prepare_crtc(data_t *data)
+{
+ igt_display_t *display = >display;
+ igt_output_t *output = data->output;
+ drmModeModeInfo *mode;
+
+ igt_display_reset(display);
+ /* select the pipe we want to use */
+ igt_output_set_pipe(output, data->pipe);
+
+ mode = igt_output_get_mode(output);
+
+ /* create a white reference fb and flip to it */
+ igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
+ DRM_FORMAT_XRGB, DRM_FORMAT_MOD_LINEAR,
+ 1.0, 1.0, 1.0, >fb[0]);
+
+ data->primary = igt_output_get_plane_type(output,
DRM_PLANE_TYPE_PRIMARY);
+
+ igt_plane_set_fb(data->primary, >fb[0]);
+ igt_display_commit(display);
+
+ if (data->pipe_crc)
+ igt_pipe_crc_free(data->pipe_crc);
+
+ data->pipe_crc = igt_pipe_crc_new(data->drm_fd, data->pipe,
+ IGT_PIPE_CRC_SOURCE_AUTO);
+
+ /* get reference crc for the white fb */
+ igt_pipe_crc_collect_crc(data->pipe_crc, >ref_crc);
+}
+
+static struct igt_fb *prepare_fb(data_t *data)
+{
+ igt_output_t *output = data->output;
+ struct igt_fb *fb = >fb[1];
+ drmModeModeInfo *mode;
+
+ prepare_crtc(data);
+
+ mode = igt_output_get_mode(output);
+
+ /* create a non-white fb we can overwrite later */
+ igt_create_pattern_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
+ DRM_FORMAT_XRGB, DRM_FORMAT_MOD_LINEAR, fb);
+
+ /* flip to it to make it UC/WC and fully flushed */
+ drmModeSetPlane(data->drm_fd,
+ data->primary->drm_plane->plane_id,
+ output->config.crtc->crtc_id,
+ fb->fb_id, 0,
+ 0, 0, fb->width, fb->height,
+ 0, 0, fb->width << 16, fb->height << 16);
+
+ /* flip back the original white buffer */
+ drmModeSetPlane(data->drm_fd,
+ data->primary->drm_plane->plane_id,
+ output->config.crtc->crtc_id,
+ data->fb[0].fb_id, 0,
+ 0, 0, fb->width, fb->height,
+ 0, 0, fb->width << 16, fb->height << 16);
+
+ if (!gem_has_lmem(data->drm_fd)) {
+ uint32_t caching;
+
+ /* make sure caching mode has become UC/WT */
+ caching = gem_get_caching(data->drm_fd, fb->gem_handle);
+ igt_assert(caching == I915_CACHING_NONE ||
+ caching == I915_CACHING_DISPLAY);
+ }
+
+ return fb;
+}
+
+static void check_buf_crc(data_t *data, void *buf, igt_fb_t *fb)
+{
+ igt_crc_t crc;
+
+
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tc: Add a workaround for an IOM/TCSS firmware hang issue (rev13)
On Sat, May 13, 2023 at 01:08:42AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/tc: Add a workaround for an IOM/TCSS firmware hang issue
> (rev13)
> URL : https://patchwork.freedesktop.org/series/117004/
> State : success
Patchset is pushed to -din, thanks for the reviews.
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_13143_full -> Patchwork_117004v13_full
>
>
> Summary
> ---
>
> **SUCCESS**
>
> No regressions found.
>
>
>
> Participating hosts (7 -> 7)
> --
>
> No changes in participating hosts
>
> Known issues
>
>
> Here are the changes found in Patchwork_117004v13_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gem_exec_fair@basic-pace-share@rcs0:
> - shard-glk: [PASS][1] -> [FAIL][2] ([i915#2842])
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
>
> * igt@gem_lmem_swapping@massive-random:
> - shard-glk: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613])
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/shard-glk8/igt@gem_lmem_swapp...@massive-random.html
>
> * igt@kms_chamelium_color@ctm-max:
> - shard-glk: NOTRUN -> [SKIP][4] ([fdo#109271]) +26 similar
> issues
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/shard-glk8/igt@kms_chamelium_co...@ctm-max.html
>
> * igt@kms_content_protection@atomic:
> - shard-glk: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4579])
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/shard-glk8/igt@kms_content_protect...@atomic.html
>
> * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
> - shard-glk: [PASS][6] -> [FAIL][7] ([i915#2346])
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-glk5/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/shard-glk3/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
>
> * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
> - shard-glk: [PASS][8] -> [FAIL][9] ([i915#79])
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@ab-hdmi-a1-hdmi-a2.html
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@ab-hdmi-a1-hdmi-a2.html
>
> * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
> - shard-glk: [PASS][10] -> [FAIL][11] ([i915#2122]) +1 similar
> issue
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@bc-hdmi-a1-hdmi-a2.html
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@bc-hdmi-a1-hdmi-a2.html
>
>
> Possible fixes
>
> * igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
> - {shard-rkl}:[FAIL][12] ([i915#7742]) -> [PASS][13]
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-rkl-2/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/shard-rkl-7/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
>
> * igt@gem_barrier_race@remote-request@rcs0:
> - shard-glk: [ABORT][14] ([i915#7461] / [i915#8211]) ->
> [PASS][15]
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-glk2/igt@gem_barrier_race@remote-requ...@rcs0.html
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/shard-glk1/igt@gem_barrier_race@remote-requ...@rcs0.html
>
> * igt@gem_ctx_freq@sysfs:
> - {shard-dg1}:[FAIL][16] ([i915#6786]) -> [PASS][17]
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-dg1-15/igt@gem_ctx_f...@sysfs.html
>[17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/shard-dg1-17/igt@gem_ctx_f...@sysfs.html
>
> * igt@gem_eio@in-flight-contexts-10ms:
> - {shard-tglu}: [TIMEOUT][18] ([i915#3063] / [i915#7941]) ->
> [PASS][19]
>[18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-tglu-3/igt@gem_...@in-flight-contexts-10ms.html
>[19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/shard-tglu-2/igt@gem_...@in-flight-contexts-10ms.html
>
> * igt@gem_exec_fair@basic-deadline:
> - shard-glk: [FAIL][20] ([i915#2846]) -> [PASS][21]
>[20]:
>
[Intel-gfx] [CI DO_NOT_MERGE 1/3] drm/i915/mtl: do not enable render power-gating on MTL
Multiple CI tests fails if render power gatins is enabled, with forcewake ack timeouts. BSpec 52698 clearly states it should be 0. References: https://gitlab.freedesktop.org/drm/intel/-/issues/4983 Signed-off-by: Andrzej Hajda --- Let's see if disabling render pg is enough. --- drivers/gpu/drm/i915/gt/intel_rc6.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 908a3d0f2343f4..0819576ffeb5df 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -117,9 +117,12 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) GEN6_RC_CTL_RC6_ENABLE | GEN6_RC_CTL_EI_MODE(1); + /* BSpec: 52698, GEN9_RENDER_PG_ENABLE must be 0 for MTL */ + if (IS_METEORLAKE(gt->i915)) + pg_enable = GEN9_MEDIA_PG_ENABLE; /* Wa_16011777198 - Render powergating must remain disabled */ - if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || - IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) + else if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || +IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) pg_enable = GEN9_MEDIA_PG_ENABLE | GEN11_MEDIA_SAMPLER_PG_ENABLE; -- 2.34.1
[Intel-gfx] [CI DO_NOT_MERGE 3/3] drm/i915/selftests: add forcewake_with_spinners tests
The test examines if running spinners do not interfere with forcewake.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/i915/selftests/intel_uncore.c | 85 +++
1 file changed, 85 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c
b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index e4281508d5808b..0ce8a5c5ee0064 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -22,7 +22,10 @@
*
*/
+#include
+#include
#include "../i915_selftest.h"
+#include
static int intel_fw_table_check(const struct intel_forcewake_range *ranges,
unsigned int num_ranges,
@@ -342,12 +345,94 @@ static int live_fw_table(void *arg)
GRAPHICS_VER(gt->i915) >= 9);
}
+static int live_forcewake_with_spinners(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_uncore_forcewake_domain *domain;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ intel_wakeref_t wakeref;
+ struct igt_spinner spin;
+ unsigned int tmp;
+ int err;
+
+ wakeref = intel_runtime_pm_get(gt->uncore->rpm);
+
+ err = igt_spinner_init(, gt);
+ if (err)
+ goto err_rpm;
+
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce;
+ struct i915_request *rq;
+
+ if (!intel_engine_can_store_dword(engine))
+ continue;
+
+ pr_info("%s: Spinning %s\n", __func__, engine->name);
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce)) {
+ err = PTR_ERR(ce);
+ goto err_spin;
+ }
+ rq = igt_spinner_create_request(, ce, MI_ARB_CHECK);
+ intel_context_put(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_spin;
+ }
+ i915_request_add(rq);
+ }
+
+ intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
+ for_each_fw_domain(domain, gt->uncore, tmp) {
+ if (readl(domain->reg_ack) & FORCEWAKE_KERNEL)
+ continue;
+ pr_err("%s: not acked\n",
intel_uncore_forcewake_domain_to_str(domain->id));
+ err = -EINVAL;
+ }
+ if (err) {
+#if defined(CONFIG_DRM_I915_DEBUG_WAKEREF) // Ugly test of presence of
intel_klog_error_capture
+ intel_klog_error_capture(gt, (intel_engine_mask_t) ~0U);
+#else
+ pr_err("Time to catch GuC logs.\n");
+ msleep(4000);
+#endif
+ }
+ msleep(3);
+ intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
+
+err_spin:
+ igt_spinner_fini();
+err_rpm:
+ intel_runtime_pm_put(gt->uncore->rpm, wakeref);
+
+ return err;
+}
+
+static int live_forcewake_with_spinners_25s(void *arg)
+{
+ ktime_t t = ktime_get();
+ int err = 0;
+
+ while (ktime_ms_delta(ktime_get(), t) < 25000) {
+ err = live_forcewake_with_spinners(arg);
+ if (err)
+ break;
+ }
+
+ return err;
+}
+
int intel_uncore_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(live_fw_table),
SUBTEST(live_forcewake_ops),
SUBTEST(live_forcewake_domains),
+ SUBTEST(live_forcewake_with_spinners),
+ SUBTEST(live_forcewake_with_spinners_25s),
};
return intel_gt_live_subtests(tests, to_gt(i915));
--
2.34.1
[Intel-gfx] [CI DO_NOT_MERGE 2/3] drm/i915/gt: do not enable render and media power-gating on RPL-S
Multiple CI tests fails with forcewake timeouts. Disabling power gating for render and media solves the issue. References: https://gitlab.freedesktop.org/drm/intel/-/issues/4983 Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/i915/gt/intel_rc6.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 0819576ffeb5df..c405b209e47922 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -126,6 +126,9 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) pg_enable = GEN9_MEDIA_PG_ENABLE | GEN11_MEDIA_SAMPLER_PG_ENABLE; + /* Testing */ + else if (IS_ADLS_RPLS(gt->i915)) + pg_enable = 0; else pg_enable = GEN9_RENDER_PG_ENABLE | -- 2.34.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: tweak language in fastset pipe config compare logging
== Series Details ==
Series: drm/i915: tweak language in fastset pipe config compare logging
URL : https://patchwork.freedesktop.org/series/117807/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13151 -> Patchwork_117807v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117807v1/index.html
Participating hosts (38 -> 36)
--
Missing(2): fi-kbl-soraka fi-snb-2520m
Known issues
Here are the changes found in Patchwork_117807v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@load:
- bat-adls-5: [PASS][1] -> [ABORT][2] ([i915#4391])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-adls-5/igt@i915_module_l...@load.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117807v1/bat-adls-5/igt@i915_module_l...@load.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][3] -> [DMESG-FAIL][4] ([i915#5334])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117807v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][5] ([i915#6367])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117807v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html
* igt@i915_selftest@live@workarounds:
- bat-rpls-1: [PASS][6] -> [INCOMPLETE][7] ([i915#7677])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-rpls-1/igt@i915_selftest@l...@workarounds.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117807v1/bat-rpls-1/igt@i915_selftest@l...@workarounds.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: NOTRUN -> [ABORT][8] ([i915#6687])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117807v1/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html
Possible fixes
* igt@i915_pm_rpm@basic-rte:
- {bat-mtlp-8}: [TIMEOUT][9] -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-mtlp-8/igt@i915_pm_...@basic-rte.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117807v1/bat-mtlp-8/igt@i915_pm_...@basic-rte.html
* igt@i915_selftest@live@requests:
- {bat-mtlp-8}: [ABORT][11] ([i915#4983] / [i915#7920] / [i915#7953])
-> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-mtlp-8/igt@i915_selftest@l...@requests.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117807v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html
* igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][13] ([i915#4983] / [i915#7461] / [i915#7913]
/ [i915#8347]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-rpls-2/igt@i915_selftest@l...@reset.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117807v1/bat-rpls-2/igt@i915_selftest@l...@reset.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck@pipe-d-dp-1:
- bat-dg2-8: [FAIL][15] ([i915#7932]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-dg2-8/igt@kms_pipe_crc_basic@compare-crc-sanitych...@pipe-d-dp-1.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117807v1/bat-dg2-8/igt@kms_pipe_crc_basic@compare-crc-sanitych...@pipe-d-dp-1.html
Warnings
* igt@i915_suspend@basic-s3-without-i915:
- fi-tgl-1115g4: [INCOMPLETE][17] ([i915#7443] / [i915#7953] /
[i915#8102]) -> [INCOMPLETE][18] ([i915#7443] / [i915#8102])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/fi-tgl-1115g4/igt@i915_susp...@basic-s3-without-i915.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117807v1/fi-tgl-1115g4/igt@i915_susp...@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7677]: https://gitlab.freedesktop.org/drm/intel/issues/7677
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
Re: [Intel-gfx] [PATCH v2 03/12] drm/exynos: Use regular fbdev I/O helpers
Hi Sam
Am 15.05.23 um 19:43 schrieb Sam Ravnborg:
Hi Thomas,
On Mon, May 15, 2023 at 11:40:24AM +0200, Thomas Zimmermann wrote:
Use the regular fbdev helpers for framebuffer I/O instead of DRM's
helpers. Exynos does not use damage handling, so DRM's fbdev helpers
are mere wrappers around the fbdev code.
By using fbdev helpers directly within each DRM fbdev emulation,
we can eventually remove DRM's wrapper functions entirely.
v2:
* use FB_IO_HELPERS option
Signed-off-by: Thomas Zimmermann
Cc: Inki Dae
Cc: Seung-Woo Kim
Cc: Kyungmin Park
Cc: Krzysztof Kozlowski
Cc: Alim Akhtar
---
drivers/gpu/drm/exynos/Kconfig| 1 +
drivers/gpu/drm/exynos/Makefile | 2 +-
drivers/gpu/drm/exynos/exynos_drm_fbdev.c | 10 +-
3 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index 0cb92d651ff1..7ca7e1dab52c 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -7,6 +7,7 @@ config DRM_EXYNOS
select DRM_DISPLAY_HELPER if DRM_EXYNOS_DP
select DRM_KMS_HELPER
select VIDEOMODE_HELPERS
+ select FB_IO_HELPERS if DRM_FBDEV_EMULATION
select SND_SOC_HDMI_CODEC if SND_SOC
help
Choose this option if you have a Samsung SoC Exynos chipset.
diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile
index 2fd2f3ee4fcf..233a66036584 100644
--- a/drivers/gpu/drm/exynos/Makefile
+++ b/drivers/gpu/drm/exynos/Makefile
@@ -6,7 +6,6 @@
exynosdrm-y := exynos_drm_drv.o exynos_drm_crtc.o exynos_drm_fb.o \
exynos_drm_gem.o exynos_drm_plane.o exynos_drm_dma.o
-exynosdrm-$(CONFIG_DRM_FBDEV_EMULATION) += exynos_drm_fbdev.o
exynosdrm-$(CONFIG_DRM_EXYNOS_FIMD) += exynos_drm_fimd.o
exynosdrm-$(CONFIG_DRM_EXYNOS5433_DECON) += exynos5433_drm_decon.o
exynosdrm-$(CONFIG_DRM_EXYNOS7_DECON) += exynos7_drm_decon.o
@@ -23,5 +22,6 @@ exynosdrm-$(CONFIG_DRM_EXYNOS_ROTATOR)+=
exynos_drm_rotator.o
exynosdrm-$(CONFIG_DRM_EXYNOS_SCALER) += exynos_drm_scaler.o
exynosdrm-$(CONFIG_DRM_EXYNOS_GSC)+= exynos_drm_gsc.o
exynosdrm-$(CONFIG_DRM_EXYNOS_MIC) += exynos_drm_mic.o
+exynosdrm-$(CONFIG_DRM_FBDEV_EMULATION)+= exynos_drm_fbdev.o
What does this change do?
Maybe something that was left by accident?
It reorders the statements alphabetically. I can remove this, if unwanted.
Best regards
Thomas
Sam
obj-$(CONFIG_DRM_EXYNOS) += exynosdrm.o
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
index ea4b3d248aac..bdd1d087 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
@@ -8,6 +8,8 @@
*Seung-Woo Kim
*/
+#include
+
#include
#include
#include
@@ -49,11 +51,9 @@ static const struct fb_ops exynos_drm_fb_ops = {
.owner = THIS_MODULE,
DRM_FB_HELPER_DEFAULT_OPS,
.fb_mmap= exynos_drm_fb_mmap,
- .fb_read= drm_fb_helper_cfb_read,
- .fb_write = drm_fb_helper_cfb_write,
- .fb_fillrect= drm_fb_helper_cfb_fillrect,
- .fb_copyarea= drm_fb_helper_cfb_copyarea,
- .fb_imageblit = drm_fb_helper_cfb_imageblit,
+ .fb_fillrect= cfb_fillrect,
+ .fb_copyarea= cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
.fb_destroy = exynos_drm_fb_destroy,
};
--
2.40.1
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Frankenstrasse 146, 90461 Nuernberg, Germany
GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman
HRB 36809 (AG Nuernberg)
OpenPGP_signature
Description: OpenPGP digital signature
Re: [Intel-gfx] [PATCH v2 02/12] drm/armada: Use regular fbdev I/O helpers
Hi
Am 15.05.23 um 20:04 schrieb Russell King (Oracle):
On Mon, May 15, 2023 at 07:55:44PM +0200, Sam Ravnborg wrote:
Hi Thomas,
On Mon, May 15, 2023 at 11:40:23AM +0200, Thomas Zimmermann wrote:
Use the regular fbdev helpers for framebuffer I/O instead of DRM's
helpers. Armada does not use damage handling, so DRM's fbdev helpers
are mere wrappers around the fbdev code.
By using fbdev helpers directly within each DRM fbdev emulation,
we can eventually remove DRM's wrapper functions entirely.
v2:
* use FB_IO_HELPERS option
Signed-off-by: Thomas Zimmermann
Cc: Russell King
---
drivers/gpu/drm/armada/Kconfig| 1 +
drivers/gpu/drm/armada/armada_fbdev.c | 9 -
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/armada/Kconfig b/drivers/gpu/drm/armada/Kconfig
index f5c66d89ba99..5afade25e217 100644
--- a/drivers/gpu/drm/armada/Kconfig
+++ b/drivers/gpu/drm/armada/Kconfig
@@ -3,6 +3,7 @@ config DRM_ARMADA
tristate "DRM support for Marvell Armada SoCs"
depends on DRM && HAVE_CLK && ARM && MMU
select DRM_KMS_HELPER
+ select FB_IO_HELPERS if DRM_FBDEV_EMULATION
help
Support the "LCD" controllers found on the Marvell Armada 510
devices. There are two controllers on the device, each controller
diff --git a/drivers/gpu/drm/armada/armada_fbdev.c
b/drivers/gpu/drm/armada/armada_fbdev.c
index 0a5fd1aa86eb..6c3bbaf53569 100644
--- a/drivers/gpu/drm/armada/armada_fbdev.c
+++ b/drivers/gpu/drm/armada/armada_fbdev.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include
@@ -34,11 +35,9 @@ static void armada_fbdev_fb_destroy(struct fb_info *info)
static const struct fb_ops armada_fb_ops = {
.owner = THIS_MODULE,
DRM_FB_HELPER_DEFAULT_OPS,
- .fb_read= drm_fb_helper_cfb_read,
- .fb_write = drm_fb_helper_cfb_write,
I had expected to see
.fb_read = fb_io_read,
But maybe this only used when using damage handling?
Likewise for drm_fb_helper_cfb_write.
??
- .fb_fillrect= drm_fb_helper_cfb_fillrect,
- .fb_copyarea= drm_fb_helper_cfb_copyarea,
- .fb_imageblit = drm_fb_helper_cfb_imageblit,
+ .fb_fillrect= cfb_fillrect,
+ .fb_copyarea= cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
This part is as expected.
Well, to me it looks like this has gone through an entire circular set
of revisions:
commit e8b70e4dd7b5dad7c2379de6e0851587bf86bfd6
Author: Archit Taneja
Date: Wed Jul 22 14:58:04 2015 +0530
drm/armada: Use new drm_fb_helper functions
- .fb_fillrect= cfb_fillrect,
- .fb_copyarea= cfb_copyarea,
- .fb_imageblit = cfb_imageblit,
+ .fb_fillrect= drm_fb_helper_cfb_fillrect,
+ .fb_copyarea= drm_fb_helper_cfb_copyarea,
+ .fb_imageblit = drm_fb_helper_cfb_imageblit,
commit 983780918c759fdbbf0bf033e701bbff75d2af23
Author: Thomas Zimmermann
Date: Thu Nov 3 16:14:40 2022 +0100
drm/fb-helper: Perform all fbdev I/O with the same implementation
+ .fb_read= drm_fb_helper_cfb_read,
+ .fb_write = drm_fb_helper_cfb_write,
and now effectively those two changes are being reverted, so we'd
now be back to the pre-July 2015 state of affairs. As I believe
the fbdev layer has been stable, this change merely reverts the
driver back to what it once was.
Not quite. One long-standing problem has been that fbdev does not
protect its public interfaces with CONFIG_FB. If fbdev had been
disabled, DRM drivers could no longer be linked/loaded. DRM wrappers
solved this. The issue has recently been fixed for all of DRM. DRM does
not build it's fbdev emulation if CONFIG_FB has been disabled.
Another thing was that the original DRM wrappers might have been
different from fbdev's I/O helpers in subtle ways. But now they are
simple wrappers around their fbdev counterparts; plus the option of
additional damage handling. But such damage handling is better
implemented by the driver itself. The two cases that require it, i915
and fbdev-generic, are different enough that each should probably have
it's own code.
Best regards
Thomas
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Frankenstrasse 146, 90461 Nuernberg, Germany
GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman
HRB 36809 (AG Nuernberg)
OpenPGP_signature
Description: OpenPGP digital signature
Re: [Intel-gfx] [PATCH] drm/i915: fix intel_display_irq.c include order
Quoting Jani Nikula (2023-05-16 09:29:26)
>I meant to sort the includes before submitting commit 2b874a027810
>("drm/i915/irq: split out display irq handling") but forgot, and it
>wasn't noticed in review either. Sort the includes.
Oops... My bad.
>
>Cc: Gustavo Sousa
>Signed-off-by: Jani Nikula
Reviewed-by: Gustavo Sousa
>---
> drivers/gpu/drm/i915/display/intel_display_irq.c | 16
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
>b/drivers/gpu/drm/i915/display/intel_display_irq.c
>index 0eedd1ebb389..3b2a287d2041 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
>@@ -3,23 +3,23 @@
> * Copyright © 2023 Intel Corporation
> */
>
>+#include "gt/intel_rps.h"
> #include "i915_drv.h"
> #include "i915_irq.h"
> #include "i915_reg.h"
> #include "icl_dsi_regs.h"
>-#include "intel_display_irq.h"
>-#include "intel_display_types.h"
>-#include "intel_hotplug_irq.h"
>-#include "intel_psr_regs.h"
> #include "intel_crtc.h"
>+#include "intel_de.h"
>+#include "intel_display_irq.h"
> #include "intel_display_trace.h"
>+#include "intel_display_types.h"
> #include "intel_dp_aux.h"
>-#include "intel_gmbus.h"
>+#include "intel_fdi_regs.h"
> #include "intel_fifo_underrun.h"
>+#include "intel_gmbus.h"
>+#include "intel_hotplug_irq.h"
> #include "intel_psr.h"
>-#include "intel_fdi_regs.h"
>-#include "gt/intel_rps.h"
>-#include "intel_de.h"
>+#include "intel_psr_regs.h"
>
> static void
> intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
>--
>2.39.2
>
Re: [Intel-gfx] [PATCH v2 02/12] drm/armada: Use regular fbdev I/O helpers
Hi
Am 15.05.23 um 19:55 schrieb Sam Ravnborg:
Hi Thomas,
On Mon, May 15, 2023 at 11:40:23AM +0200, Thomas Zimmermann wrote:
Use the regular fbdev helpers for framebuffer I/O instead of DRM's
helpers. Armada does not use damage handling, so DRM's fbdev helpers
are mere wrappers around the fbdev code.
By using fbdev helpers directly within each DRM fbdev emulation,
we can eventually remove DRM's wrapper functions entirely.
v2:
* use FB_IO_HELPERS option
Signed-off-by: Thomas Zimmermann
Cc: Russell King
---
drivers/gpu/drm/armada/Kconfig| 1 +
drivers/gpu/drm/armada/armada_fbdev.c | 9 -
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/armada/Kconfig b/drivers/gpu/drm/armada/Kconfig
index f5c66d89ba99..5afade25e217 100644
--- a/drivers/gpu/drm/armada/Kconfig
+++ b/drivers/gpu/drm/armada/Kconfig
@@ -3,6 +3,7 @@ config DRM_ARMADA
tristate "DRM support for Marvell Armada SoCs"
depends on DRM && HAVE_CLK && ARM && MMU
select DRM_KMS_HELPER
+ select FB_IO_HELPERS if DRM_FBDEV_EMULATION
help
Support the "LCD" controllers found on the Marvell Armada 510
devices. There are two controllers on the device, each controller
diff --git a/drivers/gpu/drm/armada/armada_fbdev.c
b/drivers/gpu/drm/armada/armada_fbdev.c
index 0a5fd1aa86eb..6c3bbaf53569 100644
--- a/drivers/gpu/drm/armada/armada_fbdev.c
+++ b/drivers/gpu/drm/armada/armada_fbdev.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include
@@ -34,11 +35,9 @@ static void armada_fbdev_fb_destroy(struct fb_info *info)
static const struct fb_ops armada_fb_ops = {
.owner = THIS_MODULE,
DRM_FB_HELPER_DEFAULT_OPS,
- .fb_read= drm_fb_helper_cfb_read,
- .fb_write = drm_fb_helper_cfb_write,
I had expected to see
.fb_read = fb_io_read,
But maybe this only used when using damage handling?
fb_io_read() and fb_io_write() are the default implementations. They are
called when no callback has been set. All the other fbdev drivers leave
them out, so I kept this pattern for the DRM side as well.
Best regards
Thomas
Likewise for drm_fb_helper_cfb_write.
??
- .fb_fillrect= drm_fb_helper_cfb_fillrect,
- .fb_copyarea= drm_fb_helper_cfb_copyarea,
- .fb_imageblit = drm_fb_helper_cfb_imageblit,
+ .fb_fillrect= cfb_fillrect,
+ .fb_copyarea= cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
This part is as expected.
Sam
.fb_destroy = armada_fbdev_fb_destroy,
};
--
2.40.1
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Frankenstrasse 146, 90461 Nuernberg, Germany
GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman
HRB 36809 (AG Nuernberg)
OpenPGP_signature
Description: OpenPGP digital signature
Re: [Intel-gfx] [PATCH v5 0/8] drm/i915: move DSC RC tables to drm_dsc_helper.c
On 15/05/2023 12:12, Jani Nikula wrote: On Thu, 04 May 2023, Dmitry Baryshkov wrote: Other platforms (msm) will benefit from sharing the DSC config setup functions. This series moves parts of static DSC config data from the i915 driver to the common helpers to be used by other drivers. Note: the RC parameters were cross-checked against config files found in DSC model 2021062, 20161212 (and 20150914). The first patch modifies tables according to those config files, while preserving parameter values using the code. I have not changed one of the values in the pre-SCR config file as it clearly looks like a typo in the config file, considering the table E in DSC 1.1 and in the DSC 1.1 SCR. As I believe I've said before, I think it's fine to merge these either via drm-intel or drm-misc. Which do you prefer? No strong preference. Maybe drm-misc would be easier for us to back-merge it into msm/next. Otherwise it is up to you. BR, Jani. Chances since v4: - Rebased on top of drm-intel-next - Cut the first 8 patches of the series to ease merging. The rest of the patches will go afterwards. Chances since v3: - Rebased on top of drm-intel-next - Dropped the msm patch to make patchset fully mergeable through drm-intel - Made drm_dsc_set_const_params() ignore rc_model_size, picked up drm_dsc_set_initial_scale_value() patch by Jessica and switched intel_vdsc.c to use those two helpers. - Added a patch to make i915 actually use rc_tgt_offset_high, rc_tgt_offset_low and rc_edge_factor from struct drm_dsc_config. Chances since v2: - Rebased on top of drm-intel-next Chances since v1: - Made drm_dsc_rc_buf_thresh static rather than exporting it - Switched drm_dsc_rc_buf_thresh loop to use ARRAY_SIZE. Added BUILD_BUG_ON's to be sure that array sizes are correct - Fixed rc_parameters_data indentation to be logical and tidy - Fixed drm_dsc_setup_rc_params() kerneldoc - Added a clause to drm_dsc_setup_rc_params() to verify bpp and bpc being set. - Fixed range_bpg_offset programming in calculate_rc_params() - Fixed bpp vs bpc bug in intel_dsc_compute_params() - Added FIXME comment next to the customizations in intel_dsc_compute_params(). Dmitry Baryshkov (8): drm/i915/dsc: change DSC param tables to follow the DSC model drm/i915/dsc: move rc_buf_thresh values to common helper drm/i915/dsc: move DSC tables to DRM DSC helper drm/i915/dsc: stop using interim structure for calculated params drm/display/dsc: use flat array for rc_parameters lookup drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters drm/display/dsc: include the rest of pre-SCR parameters drm/display/dsc: add YCbCr 4:2:2 and 4:2:0 RC parameters drivers/gpu/drm/display/drm_dsc_helper.c | 986 ++ drivers/gpu/drm/i915/display/intel_vdsc.c | 443 ++ include/drm/display/drm_dsc_helper.h | 9 + 3 files changed, 1042 insertions(+), 396 deletions(-) -- With best wishes Dmitry
Re: [Intel-gfx] [PATCH] drm/i915/gem: Use large rings for compute contexts
On Tue, 16 May 2023, Tejas Upadhyay wrote: > From: Chris Wilson > > Allow compute contexts to submit the maximal amount of work without > blocking userspace. > > The original size for user LRC ring's (SZ_16K) was chosen to minimise > memory consumption, without being so small as to frequently stall in the > middle of workloads. With the main consumers being GL / media pipelines > of 2 or 3 batches per frame, we want to support ~10 requests in flight > to allow for the application to control throttling without stalling > within a frame. > > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c > b/drivers/gpu/drm/i915/gem/i915_gem_context.c > index 5402a7bbcb1d..0edb7be6fa5e 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c > @@ -965,6 +965,8 @@ static int intel_context_set_gem(struct intel_context *ce, > > GEM_BUG_ON(intel_context_is_pinned(ce)); > ce->ring_size = SZ_16K; > + if (ce->engine->class == COMPUTE_CLASS) > + ce->ring_size = SZ_512K; Not a huge fan of first initializing something, and then changing it in some cases. Why not if (ce->engine->class == COMPUTE_CLASS) ... else ...? BR, Jani. > > i915_vm_put(ce->vm); > ce->vm = i915_gem_context_get_eb_vm(ctx); -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH] drm/i915: fix intel_display_irq.c include order
I meant to sort the includes before submitting commit 2b874a027810
("drm/i915/irq: split out display irq handling") but forgot, and it
wasn't noticed in review either. Sort the includes.
Cc: Gustavo Sousa
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 0eedd1ebb389..3b2a287d2041 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -3,23 +3,23 @@
* Copyright © 2023 Intel Corporation
*/
+#include "gt/intel_rps.h"
#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_reg.h"
#include "icl_dsi_regs.h"
-#include "intel_display_irq.h"
-#include "intel_display_types.h"
-#include "intel_hotplug_irq.h"
-#include "intel_psr_regs.h"
#include "intel_crtc.h"
+#include "intel_de.h"
+#include "intel_display_irq.h"
#include "intel_display_trace.h"
+#include "intel_display_types.h"
#include "intel_dp_aux.h"
-#include "intel_gmbus.h"
+#include "intel_fdi_regs.h"
#include "intel_fifo_underrun.h"
+#include "intel_gmbus.h"
+#include "intel_hotplug_irq.h"
#include "intel_psr.h"
-#include "intel_fdi_regs.h"
-#include "gt/intel_rps.h"
-#include "intel_de.h"
+#include "intel_psr_regs.h"
static void
intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
--
2.39.2
[Intel-gfx] [PATCH] drm/i915/gem: Use large rings for compute contexts
From: Chris Wilson Allow compute contexts to submit the maximal amount of work without blocking userspace. The original size for user LRC ring's (SZ_16K) was chosen to minimise memory consumption, without being so small as to frequently stall in the middle of workloads. With the main consumers being GL / media pipelines of 2 or 3 batches per frame, we want to support ~10 requests in flight to allow for the application to control throttling without stalling within a frame. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 5402a7bbcb1d..0edb7be6fa5e 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -965,6 +965,8 @@ static int intel_context_set_gem(struct intel_context *ce, GEM_BUG_ON(intel_context_is_pinned(ce)); ce->ring_size = SZ_16K; + if (ce->engine->class == COMPUTE_CLASS) + ce->ring_size = SZ_512K; i915_vm_put(ce->vm); ce->vm = i915_gem_context_get_eb_vm(ctx); -- 2.25.1
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/pmu: Change bitmask of enabled events to u32
== Series Details ==
Series: drm/i915/pmu: Change bitmask of enabled events to u32
URL : https://patchwork.freedesktop.org/series/117805/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13151 -> Patchwork_117805v1
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_117805v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_117805v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117805v1/index.html
Participating hosts (38 -> 37)
--
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_117805v1:
### IGT changes ###
Possible regressions
* igt@gem_exec_parallel@engines@fds:
- bat-atsm-1: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-atsm-1/igt@gem_exec_parallel@engi...@fds.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117805v1/bat-atsm-1/igt@gem_exec_parallel@engi...@fds.html
Known issues
Here are the changes found in Patchwork_117805v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@load:
- bat-adls-5: [PASS][3] -> [ABORT][4] ([i915#4391])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-adls-5/igt@i915_module_l...@load.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117805v1/bat-adls-5/igt@i915_module_l...@load.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: [PASS][5] -> [DMESG-FAIL][6] ([i915#5334] /
[i915#7872])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117805v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
- bat-jsl-1: [PASS][7] -> [DMESG-FAIL][8] ([i915#5334])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-jsl-1/igt@i915_selftest@live@gt_heartbeat.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117805v1/bat-jsl-1/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- fi-skl-guc: [PASS][9] -> [DMESG-WARN][10] ([i915#8073])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117805v1/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: NOTRUN -> [ABORT][11] ([i915#6687])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117805v1/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][12] ([i915#1845] / [i915#5354]) +2
similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117805v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
Possible fixes
* igt@i915_pm_rpm@basic-rte:
- {bat-mtlp-8}: [TIMEOUT][13] -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-mtlp-8/igt@i915_pm_...@basic-rte.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117805v1/bat-mtlp-8/igt@i915_pm_...@basic-rte.html
* igt@i915_selftest@live@requests:
- {bat-mtlp-8}: [ABORT][15] ([i915#4983] / [i915#7920] / [i915#7953])
-> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-mtlp-8/igt@i915_selftest@l...@requests.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117805v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html
- {bat-mtlp-6}: [ABORT][17] ([i915#4983] / [i915#7920] / [i915#7953])
-> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-mtlp-6/igt@i915_selftest@l...@requests.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117805v1/bat-mtlp-6/igt@i915_selftest@l...@requests.html
* igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][19] ([i915#4983] / [i915#7461] / [i915#7913]
/ [i915#8347]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-rpls-2/igt@i915_selftest@l...@reset.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117805v1/bat-rpls-2/igt@i915_selftest@l...@reset.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck@pipe-d-dp-1:
- bat-dg2-8: [FAIL][21] ([i915#7932]) -> [PASS][22] +2 similar
issues
[21]:
Re: [Intel-gfx] [PATCH 12/13] drm/i915/dp: Get optimal link config to have best compressed bpp
On Tue, May 16, 2023 at 01:43:44PM +0300, Lisovskiy, Stanislav wrote:
> On Fri, May 12, 2023 at 11:54:16AM +0530, Ankit Nautiyal wrote:
> > Currently, we take the max lane, rate and pipe bpp, to get the maximum
> > compressed bpp possible. We then set the output bpp to this value.
> > This patch provides support to have max bpp, min rate and min lanes,
> > that can support the min compressed bpp.
> >
> > v2:
> > -Avoid ending up with compressed bpp, same as pipe bpp. (Stan)
> > -Fix the checks for limits->max/min_bpp while iterating over list of
> > valid DSC bpcs. (Stan)
> >
> > v3:
> > -Refactor the code to have pipe bpp/compressed bpp computation and slice
> > count calculation separately for different cases.
> >
> > v4:
> > -Separate the pipe_bpp calculation for eDP and DP.
> >
> > Signed-off-by: Ankit Nautiyal
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 305 +++-
> > 1 file changed, 245 insertions(+), 60 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 39e2bf3d738d..578320220c9a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1642,6 +1642,209 @@ static bool intel_dp_dsc_supports_format(struct
> > intel_dp *intel_dp,
> > return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
> > sink_dsc_format);
> > }
> >
> > +static bool is_dsc_bw_sufficient(int link_rate, int lane_count, int
> > compressed_bpp,
> > +const struct drm_display_mode *adjusted_mode)
> > +{
> > + int mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
> > compressed_bpp);
> > + int link_avail = intel_dp_max_data_rate(link_rate, lane_count);
> > +
> > + return mode_rate <= link_avail;
> > +}
> > +
> > +static int dsc_compute_link_config(struct intel_dp *intel_dp,
> > + struct intel_crtc_state *pipe_config,
> > + struct link_config_limits *limits,
> > + int pipe_bpp,
> > + u16 compressed_bpp,
> > + int timeslots)
> > +{
> > + const struct drm_display_mode *adjusted_mode =
> > + _config->hw.adjusted_mode;
> > + int link_rate, lane_count;
> > + int dsc_max_bpp;
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > + int i;
> > +
> > + for (i = 0; i < intel_dp->num_common_rates; i++) {
> > + link_rate = intel_dp_common_rate(intel_dp, i);
> > + if (link_rate < limits->min_rate || link_rate >
> > limits->max_rate)
> > + continue;
> > +
> > + for (lane_count = limits->min_lane_count;
> > +lane_count <= limits->max_lane_count;
> > +lane_count <<= 1) {
> > + dsc_max_bpp =
> > intel_dp_dsc_get_max_compressed_bpp(dev_priv,
> > +
> > link_rate,
> > +
> > lane_count,
> > +
> > adjusted_mode->crtc_clock,
> > +
> > adjusted_mode->crtc_hdisplay,
> > +
> > pipe_config->bigjoiner_pipes,
> > +
> > pipe_config->output_format,
> > +
> > pipe_bpp, timeslots);
> > + /*
> > +* According to DSC 1.2a Section 4.1.1 Table 4.1 the
> > maximum
> > +* supported PPS value can be 63.9375 and with the
> > further
> > +* mention that bpp should be programmed double the
> > target bpp
> > +* restricting our target bpp to be 31.9375 at max
> > +*/
> > + if (pipe_config->output_format ==
> > INTEL_OUTPUT_FORMAT_YCBCR420)
> > + dsc_max_bpp = min_t(u16, dsc_max_bpp, 31);
> > +
> > + if (compressed_bpp > dsc_max_bpp)
> > + continue;
> > +
> > + if (!is_dsc_bw_sufficient(link_rate, lane_count,
> > + compressed_bpp,
> > adjusted_mode))
> > + continue;
> > +
> > + pipe_config->lane_count = lane_count;
> > + pipe_config->port_clock = link_rate;
> > +
> > + return 0;
> > + }
> > + }
> > +
> > + return -EINVAL;
> > +}
> > +
> > +static
> > +u16 intel_dp_dsc_max_sink_compressed_bppx16(struct intel_dp *intel_dp,
> > + struct intel_crtc_state
> > *pipe_config,
> > +
Re: [Intel-gfx] [PATCH v4 0/4] Fix modeset locking issue in HDCP MST
> -Original Message- > From: Intel-gfx On Behalf Of Suraj > Kandpal > Sent: Monday, May 15, 2023 4:02 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH v4 0/4] Fix modeset locking issue in HDCP MST > > HDCP MST scenario sees modeset locking issue ever since topology_state was > added to drm_atomic_state and all modeset locks were being taken for us > causing a locking issue to occur when we iterate over connectors to assign > vcpi id, the fix being to pass acquire_ctx to drm_modeset_lock. > > --v2 > -call intel_hdcp_prepare_stream instead of intel_hdcp_required_stream in > the beginning [Ankit] -replace intel_connector argument with intel_encoder > [Jani] > > --v3 > -break intel_hdcp_required_stream to two parts and call > intel_hdcp_set_content_streams at beginning [Ankit] -Move encoder_type0 > out of loop [Ankit] > > --v4 > -rename intel_set_content_stream [Ankit] -remove return type from > intel_hdcp_prepare_stream and intel_hdcp_required_content_stream > [Ankit] > > Signed-off-by: Suraj Kandpal > > Suraj Kandpal (4): > drm/i915/hdcp: add intel_atomic_state argument to hdcp_enable function > drm/i915/hdcp: Remove enforce_type0 check outside loop > drm/i915/hdcp: Fix modeset locking issue in hdcp mst > drm/i915/hdcp: Fill hdcp2_streamid_type and k in appropriate places Pushed the changes to din. Thanks for patches. Regards, Animesh > > drivers/gpu/drm/i915/display/intel_ddi.c| 4 +- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +- > drivers/gpu/drm/i915/display/intel_hdcp.c | 143 ++-- > drivers/gpu/drm/i915/display/intel_hdcp.h | 6 +- > 4 files changed, 81 insertions(+), 76 deletions(-) > > -- > 2.25.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/syncmap: squelch a sparse warning
== Series Details ==
Series: drm/i915/syncmap: squelch a sparse warning
URL : https://patchwork.freedesktop.org/series/117802/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13151 -> Patchwork_117802v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117802v1/index.html
Participating hosts (38 -> 37)
--
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_117802v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@load:
- bat-adls-5: [PASS][1] -> [DMESG-WARN][2] ([i915#4391])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-adls-5/igt@i915_module_l...@load.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117802v1/bat-adls-5/igt@i915_module_l...@load.html
* igt@i915_selftest@live@gt_engines:
- bat-atsm-1: [PASS][3] -> [FAIL][4] ([i915#6268])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-atsm-1/igt@i915_selftest@live@gt_engines.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117802v1/bat-atsm-1/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: [PASS][5] -> [DMESG-FAIL][6] ([i915#5334] /
[i915#7872])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117802v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@uncore:
- bat-adls-5: [PASS][7] -> [ABORT][8] ([i915#4391] / [i915#7913])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-adls-5/igt@i915_selftest@l...@uncore.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117802v1/bat-adls-5/igt@i915_selftest@l...@uncore.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][9] ([i915#1845] / [i915#5354])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117802v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
Possible fixes
* igt@i915_selftest@live@requests:
- {bat-mtlp-6}: [ABORT][10] ([i915#4983] / [i915#7920] / [i915#7953])
-> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-mtlp-6/igt@i915_selftest@l...@requests.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117802v1/bat-mtlp-6/igt@i915_selftest@l...@requests.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck@pipe-d-dp-1:
- bat-dg2-8: [FAIL][12] ([i915#7932]) -> [PASS][13] +2 similar
issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-dg2-8/igt@kms_pipe_crc_basic@compare-crc-sanitych...@pipe-d-dp-1.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117802v1/bat-dg2-8/igt@kms_pipe_crc_basic@compare-crc-sanitych...@pipe-d-dp-1.html
Warnings
* igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][14] ([i915#4983] / [i915#7461] / [i915#7913]
/ [i915#8347]) -> [ABORT][15] ([i915#4983] / [i915#7461] / [i915#7913] /
[i915#7981] / [i915#8347])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-rpls-2/igt@i915_selftest@l...@reset.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117802v1/bat-rpls-2/igt@i915_selftest@l...@reset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7953]: https://gitlab.freedesktop.org/drm/intel/issues/7953
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
Build changes
-
* Linux: CI_DRM_13151 -> Patchwork_117802v1
CI-20190529: 20190529
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/syncmap: squelch a sparse warning
== Series Details == Series: drm/i915/syncmap: squelch a sparse warning URL : https://patchwork.freedesktop.org/series/117802/ State : warning == Summary == Error: dim checkpatch failed 2e08e006d88c drm/i915/syncmap: squelch a sparse warning -:4: WARNING:EMAIL_SUBJECT: A patch subject line should describe the change not the tool that found it #4: Subject: [PATCH] drm/i915/syncmap: squelch a sparse warning total: 0 errors, 1 warnings, 0 checks, 8 lines checked
Re: [Intel-gfx] [PATCH 12/13] drm/i915/dp: Get optimal link config to have best compressed bpp
On Fri, May 12, 2023 at 11:54:16AM +0530, Ankit Nautiyal wrote:
> Currently, we take the max lane, rate and pipe bpp, to get the maximum
> compressed bpp possible. We then set the output bpp to this value.
> This patch provides support to have max bpp, min rate and min lanes,
> that can support the min compressed bpp.
>
> v2:
> -Avoid ending up with compressed bpp, same as pipe bpp. (Stan)
> -Fix the checks for limits->max/min_bpp while iterating over list of
> valid DSC bpcs. (Stan)
>
> v3:
> -Refactor the code to have pipe bpp/compressed bpp computation and slice
> count calculation separately for different cases.
>
> v4:
> -Separate the pipe_bpp calculation for eDP and DP.
>
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 305 +++-
> 1 file changed, 245 insertions(+), 60 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 39e2bf3d738d..578320220c9a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1642,6 +1642,209 @@ static bool intel_dp_dsc_supports_format(struct
> intel_dp *intel_dp,
> return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
> sink_dsc_format);
> }
>
> +static bool is_dsc_bw_sufficient(int link_rate, int lane_count, int
> compressed_bpp,
> + const struct drm_display_mode *adjusted_mode)
> +{
> + int mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
> compressed_bpp);
> + int link_avail = intel_dp_max_data_rate(link_rate, lane_count);
> +
> + return mode_rate <= link_avail;
> +}
> +
> +static int dsc_compute_link_config(struct intel_dp *intel_dp,
> +struct intel_crtc_state *pipe_config,
> +struct link_config_limits *limits,
> +int pipe_bpp,
> +u16 compressed_bpp,
> +int timeslots)
> +{
> + const struct drm_display_mode *adjusted_mode =
> + _config->hw.adjusted_mode;
> + int link_rate, lane_count;
> + int dsc_max_bpp;
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + int i;
> +
> + for (i = 0; i < intel_dp->num_common_rates; i++) {
> + link_rate = intel_dp_common_rate(intel_dp, i);
> + if (link_rate < limits->min_rate || link_rate >
> limits->max_rate)
> + continue;
> +
> + for (lane_count = limits->min_lane_count;
> + lane_count <= limits->max_lane_count;
> + lane_count <<= 1) {
> + dsc_max_bpp =
> intel_dp_dsc_get_max_compressed_bpp(dev_priv,
> +
> link_rate,
> +
> lane_count,
> +
> adjusted_mode->crtc_clock,
> +
> adjusted_mode->crtc_hdisplay,
> +
> pipe_config->bigjoiner_pipes,
> +
> pipe_config->output_format,
> +
> pipe_bpp, timeslots);
> + /*
> + * According to DSC 1.2a Section 4.1.1 Table 4.1 the
> maximum
> + * supported PPS value can be 63.9375 and with the
> further
> + * mention that bpp should be programmed double the
> target bpp
> + * restricting our target bpp to be 31.9375 at max
> + */
> + if (pipe_config->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR420)
> + dsc_max_bpp = min_t(u16, dsc_max_bpp, 31);
> +
> + if (compressed_bpp > dsc_max_bpp)
> + continue;
> +
> + if (!is_dsc_bw_sufficient(link_rate, lane_count,
> + compressed_bpp,
> adjusted_mode))
> + continue;
> +
> + pipe_config->lane_count = lane_count;
> + pipe_config->port_clock = link_rate;
> +
> + return 0;
> + }
> + }
> +
> + return -EINVAL;
> +}
> +
> +static
> +u16 intel_dp_dsc_max_sink_compressed_bppx16(struct intel_dp *intel_dp,
> + struct intel_crtc_state
> *pipe_config,
> + int bpc)
> +{
> + u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd);
> +
> + if (max_bppx16)
> + return max_bppx16;
> + /*
> + * If support not given in DPCD
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/mtl: Fix expected reg value for Thunderbolt PLL disabling (rev3)
== Series Details ==
Series: drm/i915/mtl: Fix expected reg value for Thunderbolt PLL disabling
(rev3)
URL : https://patchwork.freedesktop.org/series/117690/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13148_full -> Patchwork_117690v3_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_117690v3_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-4:
- {shard-dg1}:[PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13148/shard-dg1-15/igt@kms_cursor_crc@cursor-susp...@pipe-d-hdmi-a-4.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v3/shard-dg1-13/igt@kms_cursor_crc@cursor-susp...@pipe-d-hdmi-a-4.html
Known issues
Here are the changes found in Patchwork_117690v3_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_barrier_race@remote-request@rcs0:
- shard-glk: [PASS][3] -> [ABORT][4] ([i915#7461] / [i915#8211])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13148/shard-glk4/igt@gem_barrier_race@remote-requ...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v3/shard-glk2/igt@gem_barrier_race@remote-requ...@rcs0.html
* igt@gem_lmem_swapping@smem-oom:
- shard-glk: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v3/shard-glk2/igt@gem_lmem_swapp...@smem-oom.html
* igt@gem_pwrite@basic-exhaustion:
- shard-glk: NOTRUN -> [WARN][6] ([i915#2658])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v3/shard-glk2/igt@gem_pwr...@basic-exhaustion.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
- shard-glk: NOTRUN -> [SKIP][7] ([fdo#109271]) +37 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v3/shard-glk2/igt@kms_big...@yf-tiled-64bpp-rotate-180.html
* igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#3886]) +3
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v3/shard-glk2/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-4_tiled_dg2_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][9] ([fdo#109271]) +4 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v3/shard-apl3/igt@kms_ccs@pipe-b-crc-primary-rotation-180-4_tiled_dg2_mc_ccs.html
*
igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-glk: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4579]) +1
similar issue
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v3/shard-glk2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscal...@pipe-a-valid-mode.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-glk: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#658])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v3/shard-glk2/igt@kms_psr2_su@page_flip-nv12.html
Possible fixes
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-tglu}: [FAIL][12] ([i915#6268]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13148/shard-tglu-6/igt@gem_ctx_e...@basic-nohangcheck.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v3/shard-tglu-2/igt@gem_ctx_e...@basic-nohangcheck.html
* igt@gem_eio@unwedge-stress:
- {shard-dg1}:[FAIL][14] ([i915#5784]) -> [PASS][15] +1 similar
issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13148/shard-dg1-17/igt@gem_...@unwedge-stress.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v3/shard-dg1-12/igt@gem_...@unwedge-stress.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- {shard-rkl}:[SKIP][16] ([i915#1937] / [i915#4579]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13148/shard-rkl-6/igt@i915_pm_lpsp@kms-l...@kms-lpsp-hdmi-a.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v3/shard-rkl-7/igt@i915_pm_lpsp@kms-l...@kms-lpsp-hdmi-a.html
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- {shard-rkl}:[SKIP][18] ([i915#1397]) -> [PASS][19] +1 similar
issue
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13148/shard-rkl-7/igt@i915_pm_...@dpms-mode-unset-non-lpsp.html
[19]:
Re: [Intel-gfx] [PATCH] drm/i915: tweak language in fastset pipe config compare logging
>
> The "fastset mismatch" debug logging has been slightly confusing, leading
> people to believe some error happened. Change it to the more informative
> "fastset requirement not met", and add a final message about this leading to
> full modeset.
>
LGTM.
Reviewed-by: Suraj Kandpal
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 15 ++-
> 1 file changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 4b70b389e0cb..8afbaf8d1196 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4857,7 +4857,7 @@ pipe_config_infoframe_mismatch(struct
> drm_i915_private *dev_priv,
> return;
>
> drm_dbg_kms(_priv->drm,
> - "fastset mismatch in %s infoframe\n", name);
> + "fastset requirement not met in %s infoframe\n",
> name);
> drm_dbg_kms(_priv->drm, "expected:\n");
> hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
> drm_dbg_kms(_priv->drm, "found:\n"); @@ -4882,7
> +4882,7 @@ pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private
> *dev_priv,
> return;
>
> drm_dbg_kms(_priv->drm,
> - "fastset mismatch in %s dp sdp\n", name);
> + "fastset requirement not met in %s dp sdp\n",
> name);
> drm_dbg_kms(_priv->drm, "expected:\n");
> drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
> drm_dbg_kms(_priv->drm, "found:\n"); @@ -4923,7
> +4923,7 @@ pipe_config_buffer_mismatch(struct drm_i915_private
> *dev_priv,
> len = memcmp_diff_len(a, b, len);
>
> drm_dbg_kms(_priv->drm,
> - "fastset mismatch in %s buffer\n", name);
> + "fastset requirement not met in %s buffer\n",
> name);
> print_hex_dump(KERN_DEBUG, "expected: ",
> DUMP_PREFIX_NONE,
> 16, 0, a, len, false);
> print_hex_dump(KERN_DEBUG, "found: ",
> DUMP_PREFIX_NONE, @@ -4954,7 +4954,7 @@ pipe_config_mismatch(bool
> fastset, const struct intel_crtc *crtc,
>
> if (fastset)
> drm_dbg_kms(>drm,
> - "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
> + "[CRTC:%d:%s] fastset requirement not met in %s
> %pV\n",
> crtc->base.base.id, crtc->base.name, name, );
> else
> drm_err(>drm, "[CRTC:%d:%s] mismatch in %s
> %pV\n", @@ -5542,8 +5542,13 @@ static int intel_modeset_checks(struct
> intel_atomic_state *state) static void intel_crtc_check_fastset(const struct
> intel_crtc_state *old_crtc_state,
>struct intel_crtc_state *new_crtc_state) {
> - if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
> + struct drm_i915_private *i915 =
> +to_i915(old_crtc_state->uapi.crtc->dev);
> +
> + if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
> {
> + drm_dbg_kms(>drm, "fastset requirement not met,
> forcing full
> +modeset\n");
> +
> return;
> + }
>
> new_crtc_state->uapi.mode_changed = false;
> if (!intel_crtc_needs_modeset(new_crtc_state))
> --
> 2.39.2
Re: [Intel-gfx] [PATCH 05/13] drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlck
On Mon, May 15, 2023 at 05:44:51PM +0300, Ville Syrjälä wrote:
> On Fri, May 12, 2023 at 11:54:09AM +0530, Ankit Nautiyal wrote:
> > As per Bsepc:49259, Bigjoiner BW check puts restriction on the
> > compressed bpp for a given CDCLK, pixelclock in cases where
> > Bigjoiner + DSC are used.
> >
> > Currently compressed bpp is computed first, and it is ensured that
> > the bpp will work at least with the max CDCLK freq.
> >
> > Since the CDCLK is computed later, lets account for Bigjoiner BW
> > check while calculating Min CDCLK.
> >
> > Signed-off-by: Ankit Nautiyal
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 49 ++
> > 1 file changed, 42 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 6bed75f1541a..3532640c5027 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -2520,6 +2520,46 @@ static int intel_planes_min_cdclk(const struct
> > intel_crtc_state *crtc_state)
> > return min_cdclk;
> > }
> >
> > +static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
> > +{
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > + int min_cdclk = 0;
> > +
> > + /*
> > +* When we decide to use only one VDSC engine, since
> > +* each VDSC operates with 1 ppc throughput, pixel clock
> > +* cannot be higher than the VDSC clock (cdclk)
> > +*/
> > + if (!crtc_state->dsc.dsc_split)
> > + min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
> > +
> > + if (crtc_state->bigjoiner_pipes) {
> > + /*
> > +* According to Bigjoiner bw check:
> > +* compressed_bpp <= PPC * CDCLK * Big joiner Interface bits /
> > Pixel clock
> > +*
> > +* We have already computed compressed_bpp, so now compute the
> > min CDCLK that
> > +* is required to support this compressed_bpp.
> > +*
> > +* => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner
> > Interface bits)
> > +*
> > +* Since Num of pipes joined = 2, and PPC = 2 with bigjoiner
> > +* => CDCLK >= compressed_bpp * pixel_rate / Bigjoiner
> > Interface bits
> > +*
> > +* #TODO Bspec mentions to account for FEC overhead while using
> > pixel clock.
> > +* Check if we need to use FEC overhead in the above
> > calculations.
> > +*/
> > + int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;
> > + int min_cdclk_bj = crtc_state->dsc.compressed_bpp *
> > crtc_state->pixel_rate /
> > + bigjoiner_interface_bits;
>
> pixel_rate is the downscale adjusted thing, so it doesn't seem
> like the correct thing to use here.
>
> Hmm. Assuming that the single VDSC engine really throttles the entire
> pipe to 1 PPC then we should probably account for the 1 vs. 2 PPC
> difference in *_plane_min_cdclk() and intel_pixel_rate_to_cdclk()
> directly. Currently all of those assume 2 PPC.
Main thing is to properly align that one you propose above with that check,
where we decide how many VDSC engines to use:
/*
* VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
* is greater than the maximum Cdclock and if slice count is even
* then we need to use 2 VDSC instances.
*/
if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
if (pipe_config->dsc.slice_count > 1) {
pipe_config->dsc.dsc_split = true;
} else {
drm_dbg_kms(_priv->drm,
"Cannot split stream to use 2 VDSC
instances\n");
return -EINVAL;
}
}
Otherwise I agree that we should do that check preferrably in *_plane_min_cdclk
and use plane data rate which is adjusted after scaling is applied(I think we
even have correspondent function there)
It is strange that scaling wasn't mentioned in BSpec formula.
I would also say that we should account for number of slices(i.e VDSC engines)
now only in Bigjoiner case, but always, as I understand that number can be
different not only for Bigjoiner cases.
Stan
>
> > +
> > + min_cdclk = max(min_cdclk, min_cdclk_bj);
> > + }
> > +
> > + return min_cdclk;
> > +}
> > +
> > int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> > {
> > struct drm_i915_private *dev_priv =
> > @@ -2591,13 +2631,8 @@ int intel_crtc_compute_min_cdclk(const struct
> > intel_crtc_state *crtc_state)
> > /* Account for additional needs from the planes */
> > min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
> >
> > - /*
> > -* When we decide to
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: constify pointers to hwmon_channel_info (rev2)
== Series Details ==
Series: drm/i915: constify pointers to hwmon_channel_info (rev2)
URL : https://patchwork.freedesktop.org/series/117750/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13151 -> Patchwork_117750v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117750v2/index.html
Participating hosts (38 -> 37)
--
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_117750v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@load:
- bat-adls-5: [PASS][1] -> [ABORT][2] ([i915#4391])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-adls-5/igt@i915_module_l...@load.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117750v2/bat-adls-5/igt@i915_module_l...@load.html
* igt@i915_selftest@live@guc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][3] ([i915#7852])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117750v2/bat-rpls-2/igt@i915_selftest@l...@guc.html
* igt@i915_selftest@live@migrate:
- bat-dg2-11: [PASS][4] -> [DMESG-WARN][5] ([i915#7699] /
[i915#7953])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-dg2-11/igt@i915_selftest@l...@migrate.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117750v2/bat-dg2-11/igt@i915_selftest@l...@migrate.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: NOTRUN -> [ABORT][6] ([i915#6687])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117750v2/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html
Possible fixes
* igt@i915_pm_rpm@basic-rte:
- {bat-mtlp-8}: [TIMEOUT][7] -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-mtlp-8/igt@i915_pm_...@basic-rte.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117750v2/bat-mtlp-8/igt@i915_pm_...@basic-rte.html
* igt@i915_selftest@live@requests:
- {bat-mtlp-6}: [ABORT][9] ([i915#4983] / [i915#7920] / [i915#7953])
-> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-mtlp-6/igt@i915_selftest@l...@requests.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117750v2/bat-mtlp-6/igt@i915_selftest@l...@requests.html
* igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][11] ([i915#4983] / [i915#7461] / [i915#7913]
/ [i915#8347]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-rpls-2/igt@i915_selftest@l...@reset.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117750v2/bat-rpls-2/igt@i915_selftest@l...@reset.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck@pipe-d-dp-1:
- bat-dg2-8: [FAIL][13] ([i915#7932]) -> [PASS][14] +2 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-dg2-8/igt@kms_pipe_crc_basic@compare-crc-sanitych...@pipe-d-dp-1.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117750v2/bat-dg2-8/igt@kms_pipe_crc_basic@compare-crc-sanitych...@pipe-d-dp-1.html
Warnings
* igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: [SKIP][15] ([i915#3555] / [i915#4579]) -> [ABORT][16]
([i915#4579] / [i915#8260])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13151/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117750v2/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7852]: https://gitlab.freedesktop.org/drm/intel/issues/7852
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7953]: https://gitlab.freedesktop.org/drm/intel/issues/7953
[i915#8260]:
[Intel-gfx] [PATCH i-g-t v2] tests/i915: Exercise coherency of mmapped frame buffers
Visible glitches have been observed when running graphics applications on
Linux under Xen hypervisor. Those observations have been confirmed with
failures from kms_pwrite_crc IGT test that verifies data coherency of DRM
frame buffer objects using hardware CRC checksums calculated by display
controllers, exposed to userspace via debugfs. Since not all applications
exhibit the issue, we need to exercise more methods than just pwrite in
order to identify all affected processing paths.
Create a new test focused on exercising coherency of future scanout
buffers populated over mmap. Cover all available mmap methods and caching
modes expected to be device coherent.
v2: Drop unused functions -- left-overs from unsuccessful negative subtest
attempts requiring consistent crc mismatches in non-coherent modes,
- since all subtests now call igt_assert_crc_equal(), move it from
subtest bodies to an updated and renamed helper,
- drop "derived from ..." info from copyrights comment (Kamil),
- fix order of includes (Kamil),
- fix whitespace (Kamil),
- Cc: Bhanuprakash (Kamil).
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/7648
Signed-off-by: Janusz Krzysztofik
Cc: Bhanuprakash Modem
---
tests/i915/kms_fb_coherency.c | 305 ++
tests/meson.build | 1 +
2 files changed, 306 insertions(+)
create mode 100644 tests/i915/kms_fb_coherency.c
diff --git a/tests/i915/kms_fb_coherency.c b/tests/i915/kms_fb_coherency.c
new file mode 100644
index 00..b3f055c2b1
--- /dev/null
+++ b/tests/i915/kms_fb_coherency.c
@@ -0,0 +1,305 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+/**
+ * TEST: kms_fb_coherency
+ * Description: Exercise coherency of future scanout buffer objects
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "igt.h"
+
+typedef struct {
+ int drm_fd;
+ igt_display_t display;
+ struct igt_fb fb[2];
+ igt_output_t *output;
+ igt_plane_t *primary;
+ enum pipe pipe;
+ igt_crc_t ref_crc;
+ igt_pipe_crc_t *pipe_crc;
+ uint32_t devid;
+} data_t;
+
+static void prepare_crtc(data_t *data)
+{
+ igt_display_t *display = >display;
+ igt_output_t *output = data->output;
+ drmModeModeInfo *mode;
+
+ igt_display_reset(display);
+ /* select the pipe we want to use */
+ igt_output_set_pipe(output, data->pipe);
+
+ mode = igt_output_get_mode(output);
+
+ /* create a white reference fb and flip to it */
+ igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
+ DRM_FORMAT_XRGB, DRM_FORMAT_MOD_LINEAR,
+ 1.0, 1.0, 1.0, >fb[0]);
+
+ data->primary = igt_output_get_plane_type(output,
DRM_PLANE_TYPE_PRIMARY);
+
+ igt_plane_set_fb(data->primary, >fb[0]);
+ igt_display_commit(display);
+
+ if (data->pipe_crc)
+ igt_pipe_crc_free(data->pipe_crc);
+
+ data->pipe_crc = igt_pipe_crc_new(data->drm_fd, data->pipe,
+ IGT_PIPE_CRC_SOURCE_AUTO);
+
+ /* get reference crc for the white fb */
+ igt_pipe_crc_collect_crc(data->pipe_crc, >ref_crc);
+}
+
+static struct igt_fb *prepare_fb(data_t *data)
+{
+ igt_output_t *output = data->output;
+ struct igt_fb *fb = >fb[1];
+ drmModeModeInfo *mode;
+
+ prepare_crtc(data);
+
+ mode = igt_output_get_mode(output);
+
+ /* create a non-white fb we can overwrite later */
+ igt_create_pattern_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
+ DRM_FORMAT_XRGB, DRM_FORMAT_MOD_LINEAR, fb);
+
+ /* flip to it to make it UC/WC and fully flushed */
+ drmModeSetPlane(data->drm_fd,
+ data->primary->drm_plane->plane_id,
+ output->config.crtc->crtc_id,
+ fb->fb_id, 0,
+ 0, 0, fb->width, fb->height,
+ 0, 0, fb->width << 16, fb->height << 16);
+
+ /* flip back the original white buffer */
+ drmModeSetPlane(data->drm_fd,
+ data->primary->drm_plane->plane_id,
+ output->config.crtc->crtc_id,
+ data->fb[0].fb_id, 0,
+ 0, 0, fb->width, fb->height,
+ 0, 0, fb->width << 16, fb->height << 16);
+
+ if (!gem_has_lmem(data->drm_fd)) {
+ uint32_t caching;
+
+ /* make sure caching mode has become UC/WT */
+ caching = gem_get_caching(data->drm_fd, fb->gem_handle);
+ igt_assert(caching == I915_CACHING_NONE ||
+ caching == I915_CACHING_DISPLAY);
+ }
+
+ return fb;
+}
+
+static void check_buf_crc(data_t *data, void *buf, igt_fb_t *fb)
+{
+ igt_crc_t crc;
+
+ /* use memset to make the mmapped fb all white */
+
Re: [Intel-gfx] [PATCH v3 03/28] drm/i915/gvt: Verify hugepages are contiguous in physical address space
hi Sean
Do you think it's necessary to double check that struct page pointers
are also contiguous?
And do you like to also include a fix as below, which is to remove the
warning in vfio_device_container_unpin_pages() when npage is 0?
@ -169,7 +173,8 @@ static int gvt_pin_guest_page(struct intel_vgpu *vgpu,
unsigned long gfn,
*page = base_page;
return 0;
err:
- gvt_unpin_guest_page(vgpu, gfn, npage * PAGE_SIZE);
+ if (npage)
+ gvt_unpin_guest_page(vgpu, gfn, npage * PAGE_SIZE);
return ret;
}
BTW, I've sent a separate fix for vfio_iommu_type1_pin_pages() to ensure
struct page is a valid address.
https://lore.kernel.org/lkml/20230516093007.15234-1-yan.y.z...@intel.com/
On Fri, May 12, 2023 at 05:35:35PM -0700, Sean Christopherson wrote:
> When shadowing a GTT entry with a 2M page, verify that the pfns are
> contiguous, not just that the struct page pointers are contiguous. The
> memory map is virtual contiguous if "CONFIG_FLATMEM=y ||
> CONFIG_SPARSEMEM_VMEMMAP=y", but not for "CONFIG_SPARSEMEM=y &&
> CONFIG_SPARSEMEM_VMEMMAP=n", so theoretically KVMGT could encounter struct
> pages that are virtually contiguous, but not physically contiguous.
>
> In practice, this flaw is likely a non-issue as it would cause functional
> problems iff a section isn't 2M aligned _and_ is directly adjacent to
> another section with discontiguous pfns.
>
> Signed-off-by: Sean Christopherson
> ---
> drivers/gpu/drm/i915/gvt/kvmgt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c
> b/drivers/gpu/drm/i915/gvt/kvmgt.c
> index de675d799c7d..429f0f993a13 100644
> --- a/drivers/gpu/drm/i915/gvt/kvmgt.c
> +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
> @@ -161,7 +161,7 @@ static int gvt_pin_guest_page(struct intel_vgpu *vgpu,
> unsigned long gfn,
>
> if (npage == 0)
> base_page = cur_page;
> - else if (base_page + npage != cur_page) {
> + else if (page_to_pfn(base_page) + npage !=
> page_to_pfn(cur_page)) {
> gvt_vgpu_err("The pages are not continuous\n");
> ret = -EINVAL;
> npage++;
> --
> 2.40.1.606.ga4b1b128d6-goog
>
[Intel-gfx] ✓ Fi.CI.IGT: success for Fix modeset locking issue in HDCP MST (rev5)
== Series Details ==
Series: Fix modeset locking issue in HDCP MST (rev5)
URL : https://patchwork.freedesktop.org/series/117615/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13148_full -> Patchwork_117615v5_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 9)
--
Additional (2): shard-rkl0 shard-tglu0
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_117615v5_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_dc@dc9-dpms:
- {shard-dg1}:[PASS][1] -> ([DMESG-WARN][2], [PASS][3])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13148/shard-dg1-18/igt@i915_pm...@dc9-dpms.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-dg1-17/igt@i915_pm...@dc9-dpms.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-dg1-13/igt@i915_pm...@dc9-dpms.html
Known issues
Here are the changes found in Patchwork_117615v5_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_nop@basic-sequential:
- shard-glk: [PASS][4] -> ([DMESG-WARN][5], [PASS][6]) ([i915#118])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13148/shard-glk7/igt@gem_exec_...@basic-sequential.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk7/igt@gem_exec_...@basic-sequential.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk8/igt@gem_exec_...@basic-sequential.html
* igt@gem_lmem_swapping@heavy-verify-multi:
- shard-glk: NOTRUN -> ([SKIP][7], [SKIP][8]) ([fdo#109271] /
[i915#4613]) +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk3/igt@gem_lmem_swapp...@heavy-verify-multi.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk2/igt@gem_lmem_swapp...@heavy-verify-multi.html
* igt@gem_pwrite@basic-exhaustion:
- shard-glk: NOTRUN -> ([WARN][9], [WARN][10]) ([i915#2658])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk2/igt@gem_pwr...@basic-exhaustion.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk3/igt@gem_pwr...@basic-exhaustion.html
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [PASS][11] -> ([ABORT][12], [PASS][13]) ([i915#5566])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13148/shard-apl6/igt@gen9_exec_pa...@allowed-all.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-apl2/igt@gen9_exec_pa...@allowed-all.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-apl4/igt@gen9_exec_pa...@allowed-all.html
* igt@i915_module_load@reload-no-display:
- shard-snb: [PASS][14] -> ([ABORT][15], [PASS][16]) ([i915#4528]
/ [i915#8393])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13148/shard-snb6/igt@i915_module_l...@reload-no-display.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-snb7/igt@i915_module_l...@reload-no-display.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-snb6/igt@i915_module_l...@reload-no-display.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-glk: [PASS][17] -> ([PASS][18], [DMESG-FAIL][19])
([i915#5334])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13148/shard-glk5/igt@i915_selftest@live@gt_heartbeat.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk5/igt@i915_selftest@live@gt_heartbeat.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk3/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
- shard-glk: NOTRUN -> ([SKIP][20], [SKIP][21]) ([fdo#109271]) +42
similar issues
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk2/igt@kms_big...@yf-tiled-64bpp-rotate-180.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk3/igt@kms_big...@yf-tiled-64bpp-rotate-180.html
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> ([SKIP][22], [SKIP][23]) ([fdo#109271] /
[i915#3886]) +3 similar issues
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk3/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk2/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-4_tiled_dg2_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][24]
[Intel-gfx] ✓ Fi.CI.IGT: success for Fix modeset locking issue in HDCP MST (rev5)
== Series Details ==
Series: Fix modeset locking issue in HDCP MST (rev5)
URL : https://patchwork.freedesktop.org/series/117615/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13148_full -> Patchwork_117615v5_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 9)
--
Additional (2): shard-rkl0 shard-tglu0
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_117615v5_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_dc@dc9-dpms:
- {shard-dg1}:[PASS][1] -> ([DMESG-WARN][2], [PASS][3])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13148/shard-dg1-18/igt@i915_pm...@dc9-dpms.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-dg1-17/igt@i915_pm...@dc9-dpms.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-dg1-13/igt@i915_pm...@dc9-dpms.html
Known issues
Here are the changes found in Patchwork_117615v5_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_nop@basic-sequential:
- shard-glk: [PASS][4] -> ([PASS][5], [DMESG-WARN][6]) ([i915#118])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13148/shard-glk7/igt@gem_exec_...@basic-sequential.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk8/igt@gem_exec_...@basic-sequential.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk7/igt@gem_exec_...@basic-sequential.html
* igt@gem_lmem_swapping@heavy-verify-multi:
- shard-glk: NOTRUN -> ([SKIP][7], [SKIP][8]) ([fdo#109271] /
[i915#4613]) +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk3/igt@gem_lmem_swapp...@heavy-verify-multi.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk2/igt@gem_lmem_swapp...@heavy-verify-multi.html
* igt@gem_pwrite@basic-exhaustion:
- shard-glk: NOTRUN -> ([WARN][9], [WARN][10]) ([i915#2658])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk2/igt@gem_pwr...@basic-exhaustion.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk3/igt@gem_pwr...@basic-exhaustion.html
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [PASS][11] -> ([ABORT][12], [PASS][13]) ([i915#5566])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13148/shard-apl6/igt@gen9_exec_pa...@allowed-all.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-apl2/igt@gen9_exec_pa...@allowed-all.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-apl4/igt@gen9_exec_pa...@allowed-all.html
* igt@i915_module_load@reload-no-display:
- shard-snb: [PASS][14] -> ([ABORT][15], [PASS][16]) ([i915#4528]
/ [i915#8393])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13148/shard-snb6/igt@i915_module_l...@reload-no-display.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-snb7/igt@i915_module_l...@reload-no-display.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-snb6/igt@i915_module_l...@reload-no-display.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-glk: [PASS][17] -> ([PASS][18], [DMESG-FAIL][19])
([i915#5334])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13148/shard-glk5/igt@i915_selftest@live@gt_heartbeat.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk5/igt@i915_selftest@live@gt_heartbeat.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk3/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
- shard-glk: NOTRUN -> ([SKIP][20], [SKIP][21]) ([fdo#109271]) +42
similar issues
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk2/igt@kms_big...@yf-tiled-64bpp-rotate-180.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk3/igt@kms_big...@yf-tiled-64bpp-rotate-180.html
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> ([SKIP][22], [SKIP][23]) ([fdo#109271] /
[i915#3886]) +3 similar issues
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk3/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117615v5/shard-glk2/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-4_tiled_dg2_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][24]
[Intel-gfx] [PATCH] drm/i915: tweak language in fastset pipe config compare logging
The "fastset mismatch" debug logging has been slightly confusing,
leading people to believe some error happened. Change it to the more
informative "fastset requirement not met", and add a final message about
this leading to full modeset.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 4b70b389e0cb..8afbaf8d1196 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4857,7 +4857,7 @@ pipe_config_infoframe_mismatch(struct drm_i915_private
*dev_priv,
return;
drm_dbg_kms(_priv->drm,
- "fastset mismatch in %s infoframe\n", name);
+ "fastset requirement not met in %s infoframe\n",
name);
drm_dbg_kms(_priv->drm, "expected:\n");
hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
drm_dbg_kms(_priv->drm, "found:\n");
@@ -4882,7 +4882,7 @@ pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private
*dev_priv,
return;
drm_dbg_kms(_priv->drm,
- "fastset mismatch in %s dp sdp\n", name);
+ "fastset requirement not met in %s dp sdp\n", name);
drm_dbg_kms(_priv->drm, "expected:\n");
drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
drm_dbg_kms(_priv->drm, "found:\n");
@@ -4923,7 +4923,7 @@ pipe_config_buffer_mismatch(struct drm_i915_private
*dev_priv,
len = memcmp_diff_len(a, b, len);
drm_dbg_kms(_priv->drm,
- "fastset mismatch in %s buffer\n", name);
+ "fastset requirement not met in %s buffer\n", name);
print_hex_dump(KERN_DEBUG, "expected: ", DUMP_PREFIX_NONE,
16, 0, a, len, false);
print_hex_dump(KERN_DEBUG, "found: ", DUMP_PREFIX_NONE,
@@ -4954,7 +4954,7 @@ pipe_config_mismatch(bool fastset, const struct
intel_crtc *crtc,
if (fastset)
drm_dbg_kms(>drm,
- "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
+ "[CRTC:%d:%s] fastset requirement not met in %s
%pV\n",
crtc->base.base.id, crtc->base.name, name, );
else
drm_err(>drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
@@ -5542,8 +5542,13 @@ static int intel_modeset_checks(struct
intel_atomic_state *state)
static void intel_crtc_check_fastset(const struct intel_crtc_state
*old_crtc_state,
struct intel_crtc_state *new_crtc_state)
{
- if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
+ struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev);
+
+ if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) {
+ drm_dbg_kms(>drm, "fastset requirement not met, forcing
full modeset\n");
+
return;
+ }
new_crtc_state->uapi.mode_changed = false;
if (!intel_crtc_needs_modeset(new_crtc_state))
--
2.39.2
[Intel-gfx] [PATCH] drm/i915/pmu: Change bitmask of enabled events to u32
From: Tvrtko Ursulin
Having it as u64 was a confusing (but harmless) mistake.
Also add some asserts to make sure the internal field does not overflow
in the future.
Signed-off-by: Tvrtko Ursulin
Cc: Ashutosh Dixit
Cc: Umesh Nerlige Ramappa
---
I am not entirely sure the __builtin_constant_p->BUILD_BUG_ON branch will
work with all compilers. Lets see...
Compile tested only.
---
drivers/gpu/drm/i915/i915_pmu.c | 32 ++--
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 7ece883a7d95..8736b3418f88 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -50,7 +50,7 @@ static u8 engine_event_instance(struct perf_event *event)
return (event->attr.config >> I915_PMU_SAMPLE_BITS) & 0xff;
}
-static bool is_engine_config(u64 config)
+static bool is_engine_config(const u64 config)
{
return config < __I915_PMU_OTHER(0);
}
@@ -82,15 +82,28 @@ static unsigned int other_bit(const u64 config)
static unsigned int config_bit(const u64 config)
{
+ unsigned int bit;
+
if (is_engine_config(config))
- return engine_config_sample(config);
+ bit = engine_config_sample(config);
else
- return other_bit(config);
+ bit = other_bit(config);
+
+ if (__builtin_constant_p(config))
+ BUILD_BUG_ON(bit >
+BITS_PER_TYPE(typeof_member(struct i915_pmu,
+enable)) - 1);
+ else
+ WARN_ON_ONCE(bit >
+BITS_PER_TYPE(typeof_member(struct i915_pmu,
+enable)) - 1);
+
+ return bit;
}
-static u64 config_mask(u64 config)
+static u32 config_mask(const u64 config)
{
- return BIT_ULL(config_bit(config));
+ return BIT(config_bit(config));
}
static bool is_engine_event(struct perf_event *event)
@@ -633,11 +646,10 @@ static void i915_pmu_enable(struct perf_event *event)
{
struct drm_i915_private *i915 =
container_of(event->pmu, typeof(*i915), pmu.base);
+ const unsigned int bit = event_bit(event);
struct i915_pmu *pmu = >pmu;
unsigned long flags;
- unsigned int bit;
- bit = event_bit(event);
if (bit == -1)
goto update;
@@ -651,7 +663,7 @@ static void i915_pmu_enable(struct perf_event *event)
GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count));
GEM_BUG_ON(pmu->enable_count[bit] == ~0);
- pmu->enable |= BIT_ULL(bit);
+ pmu->enable |= BIT(bit);
pmu->enable_count[bit]++;
/*
@@ -698,7 +710,7 @@ static void i915_pmu_disable(struct perf_event *event)
{
struct drm_i915_private *i915 =
container_of(event->pmu, typeof(*i915), pmu.base);
- unsigned int bit = event_bit(event);
+ const unsigned int bit = event_bit(event);
struct i915_pmu *pmu = >pmu;
unsigned long flags;
@@ -734,7 +746,7 @@ static void i915_pmu_disable(struct perf_event *event)
* bitmask when the last listener on an event goes away.
*/
if (--pmu->enable_count[bit] == 0) {
- pmu->enable &= ~BIT_ULL(bit);
+ pmu->enable &= ~BIT(bit);
pmu->timer_enabled &= pmu_needs_timer(pmu, true);
}
--
2.39.2
Re: [Intel-gfx] [PATCH i-g-t] tests/i915: Exercise coherency of mmapped frame buffers
Hi Kamil,
Thanks for review.
On Monday, 15 May 2023 22:02:51 CEST Kamil Konieczny wrote:
> Hi Janusz,
>
> On 2023-05-15 at 10:50:20 +0200, Janusz Krzysztofik wrote:
> > Visible glitches have been observed when running graphics applications on
> > Linux under Xen hypervisor. Those observations have been confirmed with
> > failures from kms_pwrite_crc IGT test that verifies data coherency of DRM
> > frame buffer objects using hardware CRC checksums calculated by display
> > controllers, exposed to userspace via debugfs. Since not all applications
> > exhibit the issue, we need to exercise more methods than just pwrite in
> > order to identify all affected processing paths.
> >
> > Create a new test focused on exercising coherency of future scanout
> > buffers populated over mmap. Cover all available mmap methods and caching
> > modes expected to be device coherent.
> >
>
> +cc kms dev Bhanuprakash Modem
OK.
>
> > Link: https://gitlab.freedesktop.org/drm/intel/-/issues/7648
> > Signed-off-by: Janusz Krzysztofik
> > ---
> > tests/i915/kms_fb_coherency.c | 354 ++
> > tests/meson.build | 1 +
> > 2 files changed, 355 insertions(+)
> > create mode 100644 tests/i915/kms_fb_coherency.c
> >
> > diff --git a/tests/i915/kms_fb_coherency.c b/tests/i915/kms_fb_coherency.c
> > new file mode 100644
> > index 00..9223f13b05
> > --- /dev/null
> > +++ b/tests/i915/kms_fb_coherency.c
> > @@ -0,0 +1,354 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2023 Intel Corporation
> > + *
> > + * Derived from tests/i915/kms_pwrite_crc.c
> > + * Copyright © 2014 Intel Corporation
>
> imho you do not need above two lines, you already wrote this
> in description.
OK.
>
> > + */
> > +
> > +/**
> > + * TEST: kms_fb_coherency
> > + * Description: Exercise coherency of future scanout buffer objects
> > + */
> > +
> > +#include "igt.h"
>
> Put this after sys includes below.
Copy-pasted from kms_pwrite_crc.c. I'll fix it.
>
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
>
> Here put any igt include(s).
Yes.
>
> > +
> > +typedef struct {
> > + int drm_fd;
> > + igt_display_t display;
> > + struct igt_fb fb[2];
> > + igt_output_t *output;
> > + igt_plane_t *primary;
> > + enum pipe pipe;
> > + igt_crc_t ref_crc;
> > + igt_pipe_crc_t *pipe_crc;
> > + uint32_t devid;
> > +} data_t;
> > +
> > +static void prepare_crtc(data_t *data)
> > +{
> > + igt_display_t *display = >display;
> > + igt_output_t *output = data->output;
> > + drmModeModeInfo *mode;
> > +
> > + igt_display_reset(display);
> > + /* select the pipe we want to use */
> > + igt_output_set_pipe(output, data->pipe);
> > +
> > + mode = igt_output_get_mode(output);
> > +
> > + /* create a white reference fb and flip to it */
> > + igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
> > + DRM_FORMAT_XRGB, DRM_FORMAT_MOD_LINEAR,
> > + 1.0, 1.0, 1.0, >fb[0]);
> > +
> > + data->primary = igt_output_get_plane_type(output,
> > DRM_PLANE_TYPE_PRIMARY);
> > +
> > + igt_plane_set_fb(data->primary, >fb[0]);
> > + igt_display_commit(display);
> > +
> > + if (data->pipe_crc)
> > + igt_pipe_crc_free(data->pipe_crc);
> > +
> > + data->pipe_crc = igt_pipe_crc_new(data->drm_fd, data->pipe,
> > + IGT_PIPE_CRC_SOURCE_AUTO);
> > +
> > + /* get reference crc for the white fb */
> > + igt_pipe_crc_collect_crc(data->pipe_crc, >ref_crc);
> > +}
> > +
> > +static struct igt_fb *prepare_fb(data_t *data)
> > +{
> > + igt_output_t *output = data->output;
> > + struct igt_fb *fb = >fb[1];
> > + drmModeModeInfo *mode;
> > +
> > + prepare_crtc(data);
> > +
> > + mode = igt_output_get_mode(output);
> > +
> > + /* create a non-white fb we can overwrite later */
> > + igt_create_pattern_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
> > + DRM_FORMAT_XRGB, DRM_FORMAT_MOD_LINEAR, fb);
> > +
> > + /* flip to it to make it UC/WC and fully flushed */
> > + drmModeSetPlane(data->drm_fd,
> > + data->primary->drm_plane->plane_id,
> > + output->config.crtc->crtc_id,
> > + fb->fb_id, 0,
> > + 0, 0, fb->width, fb->height,
> > + 0, 0, fb->width << 16, fb->height << 16);
> > +
> > + /* flip back the original white buffer */
> > + drmModeSetPlane(data->drm_fd,
> > + data->primary->drm_plane->plane_id,
> > + output->config.crtc->crtc_id,
> > + data->fb[0].fb_id, 0,
> > + 0, 0, fb->width, fb->height,
> > + 0, 0, fb->width << 16, fb->height << 16);
> > +
> > + if (!gem_has_lmem(data->drm_fd)) {
> > + uint32_t caching;
> > +
> > + /* make sure caching mode has become UC/WT */
> > +
