== Series Details ==
Series: drm/tests: Fix incorrect argument in drm_test_mm_insert_range
URL : https://patchwork.freedesktop.org/series/123541/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13622_full -> Patchwork_123541v1_full
> Subject: [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format
>
> From: Ankit Nautiyal
>
> DSC parameter bits_per_pixel is stored in U6.4 format.
> The 4 bits represent the fractional part of the bpp.
> Currently we use compressed_bpp member of dsc structure to store only the
>
> Subject: [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp
> prescision
>
> From: Ankit Nautiyal
>
> Add helper to get the DSC bits_per_pixel precision for the DP sink.
>
LGTM.
Reviewed-by: Suraj Kandpal
> Signed-off-by: Ankit Nautiyal
> ---
>
Hi Jani,
On 9/12/23 07:52, Randy Dunlap wrote:
>
>
> On 9/12/23 00:47, Jani Nikula wrote:
>> On Mon, 11 Sep 2023, Randy Dunlap wrote:
>>> On 9/10/23 19:11, Stephen Rothwell wrote:
Hi all,
Please do *not* include material destined for v6.7 in your linux-next
included
On Tue, 12 Sep 2023 18:25:16 -0700, Umesh Nerlige Ramappa wrote:
>
Hi Umesh,
> On Fri, Sep 08, 2023 at 06:16:24PM -0700, Ashutosh Dixit wrote:
> > The code in oa_buffer_check_unlocked() is correct only if the OA buffer is
> > 16 MB aligned (which seems to be the case today in i915). However when
On Fri, Sep 08, 2023 at 06:24:16PM -0700, Dixit, Ashutosh wrote:
On Fri, 08 Sep 2023 18:16:26 -0700, Ashutosh Dixit wrote:
Hi Umesh,
From: Umesh Nerlige Ramappa
Correct values for OAR counters are still dependent on enabling the
GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE in OAG_OACONTROL.
On Fri, Sep 08, 2023 at 06:16:25PM -0700, Ashutosh Dixit wrote:
There is no reason to add gtt_offset to the cached head/tail pointers
stream->oa_buffer.head and stream->oa_buffer.tail. This causes the code to
constantly add gtt_offset and subtract gtt_offset and is error
prone (e.g. see previous
On Fri, Sep 08, 2023 at 06:16:24PM -0700, Ashutosh Dixit wrote:
The code in oa_buffer_check_unlocked() is correct only if the OA buffer is
16 MB aligned (which seems to be the case today in i915). However when the
16 MB alignment is dropped, when we "Subtract partial amount off the tail",
the "&
== Series Details ==
Series: drm/i915/huc: silence injected failure in the load via GSC path (rev5)
URL : https://patchwork.freedesktop.org/series/121080/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13623 -> Patchwork_121080v5
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/mediatek/mtk_dpi.c
between commits:
47d4bb6bbcdb ("drm/mediatek: mtk_dpi: Simplify with devm_drm_bridge_add()")
90c95c3892dd ("drm/mediatek: mtk_dpi: Switch to .remove_new() void callback")
from
== Series Details ==
Series: series starting with [1/3] drm/i915: move more of the display probe to
display code (rev2)
URL : https://patchwork.freedesktop.org/series/123600/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13623 -> Patchwork_123600v2
== Series Details ==
Series: series starting with [1/3] drm/i915: move more of the display probe to
display code (rev2)
URL : https://patchwork.freedesktop.org/series/123600/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be
== Series Details ==
Series: i915/pmu: Move execlist stats initialization to execlist specific setup
URL : https://patchwork.freedesktop.org/series/123616/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13623 -> Patchwork_123616v1
== Series Details ==
Series: drm/i915/cx0: Add step for programming msgbus timer (rev2)
URL : https://patchwork.freedesktop.org/series/123551/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13623_full -> Patchwork_123551v2_full
== Series Details ==
Series: Add DSC fractional bpp support (rev6)
URL : https://patchwork.freedesktop.org/series/111391/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13623 -> Patchwork_111391v6
Summary
---
== Series Details ==
Series: Add DSC fractional bpp support (rev6)
URL : https://patchwork.freedesktop.org/series/111391/
State : warning
== Summary ==
Error: dim checkpatch failed
7058c3132171 drm/display/dp: Add helper function to get DSC bpp prescision
eef79ef63c3a drm/i915/display: Store
== Series Details ==
Series: Add DSC fractional bpp support (rev6)
URL : https://patchwork.freedesktop.org/series/111391/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/huc: silence injected failure in the load via GSC path (rev4)
URL : https://patchwork.freedesktop.org/series/121080/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13623 -> Patchwork_121080v4
On Tue, 12 Sep 2023, Matt Roper wrote:
> On Tue, Sep 12, 2023 at 03:05:37PM +0300, Jani Nikula wrote:
>> Don't hide display probe in device info code.
>>
>> Cc: Matt Roper
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/i915_driver.c | 2 ++
>>
engine->stats is a union of execlist and guc stat objects. When execlist
specific fields are initialized, the initial state of guc stats is
affected. This results in bad busyness values when using GuC mode. Move
the execlist initialization from common code to execlist specific code.
Fixes:
== Series Details ==
Series: drm/i915/cx0: Add step for programming msgbus timer (rev2)
URL : https://patchwork.freedesktop.org/series/123551/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13623 -> Patchwork_123551v2
On Tue, Sep 12, 2023 at 09:35:21AM +0200, Andrzej Hajda wrote:
> Some DG2 firmware locks this register for modification. Using wa_add
> with read_mask 0 allows to skip checks of such registers.
>
> Signed-off-by: Andrzej Hajda
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +--
> 1
On Tue, Sep 12, 2023 at 03:05:37PM +0300, Jani Nikula wrote:
> Don't hide display probe in device info code.
>
> Cc: Matt Roper
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_driver.c | 2 ++
> drivers/gpu/drm/i915/intel_device_info.c | 2 --
>
== Series Details ==
Series: drm/i915/cx0: Add step for programming msgbus timer (rev2)
URL : https://patchwork.freedesktop.org/series/123551/
State : warning
== Summary ==
Error: dim checkpatch failed
93b3c1241b14 drm/i915/cx0: Add step for programming msgbus timer
-:213: WARNING:LONG_LINE:
== Series Details ==
Series: Apply Wa_16018031267 / Wa_16018063123
URL : https://patchwork.freedesktop.org/series/123605/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13623 -> Patchwork_123605v1
Summary
---
== Series Details ==
Series: Apply Wa_16018031267 / Wa_16018063123
URL : https://patchwork.freedesktop.org/series/123605/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Apply Wa_16018031267 / Wa_16018063123
URL : https://patchwork.freedesktop.org/series/123605/
State : warning
== Summary ==
Error: dim checkpatch failed
380b113032b9 drm/i915: Reserve some kernel space per vm
-:31: WARNING:AVOID_BUG: Do not crash the kernel unless
On 9/12/2023 9:35 AM, Andrzej Hajda wrote:
Some DG2 firmware locks this register for modification. Using wa_add
with read_mask 0 allows to skip checks of such registers.
Signed-off-by: Andrzej Hajda
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +--
1
== Series Details ==
Series: series starting with [1/3] drm/i915: move more of the display probe to
display code
URL : https://patchwork.freedesktop.org/series/123600/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13623 -> Patchwork_123600v1
== Series Details ==
Series: series starting with [1/3] drm/i915: move more of the display probe to
display code
URL : https://patchwork.freedesktop.org/series/123600/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
Hey,
On 2023-09-01 12:56, Ville Syrjälä wrote:
On Fri, Sep 01, 2023 at 12:16:21PM +0200, Maarten Lankhorst wrote:
Hey,
Den 2023-08-31 kl. 18:26, skrev Ville Syrjala:
From: Ville Syrjälä
The cursor hardware only does sync updates, and thus the hardware
will be scanning out from the old fb
== Series Details ==
Series: drm/i915: prepare for xe driver display integration
URL : https://patchwork.freedesktop.org/series/123595/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13623 -> Patchwork_123595v1
Summary
== Series Details ==
Series: drm/i915: prepare for xe driver display integration
URL : https://patchwork.freedesktop.org/series/123595/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: prepare for xe driver display integration
URL : https://patchwork.freedesktop.org/series/123595/
State : warning
== Summary ==
Error: dim checkpatch failed
f4942d5a5a1e drm/i915: define I915 during i915 driver build
b938b39e0624 drm/i915/display: add
== Series Details ==
Series: Update GGTT with MI_UPDATE_GTT on MTL (rev3)
URL : https://patchwork.freedesktop.org/series/123329/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13623 -> Patchwork_123329v3
Summary
---
== Series Details ==
Series: Update GGTT with MI_UPDATE_GTT on MTL (rev3)
URL : https://patchwork.freedesktop.org/series/123329/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Update GGTT with MI_UPDATE_GTT on MTL (rev3)
URL : https://patchwork.freedesktop.org/series/123329/
State : warning
== Summary ==
Error: dim checkpatch failed
9cea16eb6ab8 drm/i915: Lift runtime-pm acquire callbacks out of
intel_wakeref.mutex
-:57:
On Mon, Sep 11, 2023 at 09:48:16PM -0700, Lucas De Marchi wrote:
From: Clint Taylor
We use multiple variables for HDMI and DisplayPort to store the value of
DDI_BUF_CTL register (now called DDI_CTL_DE in the spec). Consolidate it
to just one in struct intel_digital_port. This is a preparation
From: Swati Sharma
If force_dsc_fractional_bpp_en is set through debugfs allow DSC iff
compressed bpp is fractional. Continue if the computed compressed bpp
turns out to be a integer.
v2:
-Use helpers for fractional, integral bits of bits_per_pixel. (Suraj)
-Fix comment (Suraj)
Signed-off-by:
From: Swati Sharma
DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
to depict sink's precision.
Also, new debugfs entry is created to enforce fractional bpp.
If Force_DSC_Fractional_BPP_en is set then while iterating over
output bpp with fractional step size we will continue if
From: Vandita Kulkarni
Consider the fractional bpp while reading the qp values.
v2: Use helpers for fractional, integral bits of bits_per_pixel. (Suraj)
Signed-off-by: Vandita Kulkarni
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
---
.../gpu/drm/i915/display/intel_qp_tables.c
From: Ankit Nautiyal
This patch adds support to iterate over compressed output bpp as per the
fractional step, supported by DP sink.
v2:
-Avoid ending up with compressed bpp, same as pipe bpp. (Stan)
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
---
From: Ankit Nautiyal
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate the precision during calculation of transfer unit data
for hblank_early calculation.
v2:
-Fixed tu_data calculation while dealing with U6.4
From: Ankit Nautiyal
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate this precision while computing m_n values.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
---
From: Ankit Nautiyal
Add helper to get the DSC bits_per_pixel precision for the DP sink.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/display/drm_dp_helper.c | 27 +
include/drm/display/drm_dp_helper.h | 1 +
2 files changed, 28 insertions(+)
diff --git
From: Ankit Nautiyal
DSC parameter bits_per_pixel is stored in U6.4 format.
The 4 bits represent the fractional part of the bpp.
Currently we use compressed_bpp member of dsc structure to store
only the integral part of the bits_per_pixel.
To store the full bits_per_pixel along with the
This patch series adds support for DSC fractional compressed bpp
for MTL+. The series starts with some fixes, followed by patches that
lay groundwork to iterate over valid compressed bpps to select the
'best' compressed bpp with optimal link configuration (taken from
upstream series:
== Series Details ==
Series: drm/i915/gt: skip WA verfication for GEN7_MISCCPCTL on DG2
URL : https://patchwork.freedesktop.org/series/123583/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13623 -> Patchwork_123583v1
On Tue, Sep 12, 2023 at 09:04:17AM -0700, Matt Roper wrote:
On Mon, Sep 11, 2023 at 09:48:24PM -0700, Lucas De Marchi wrote:
From: Ravi Kumar Vodapalli
Add Display Power Well for LNL platform. It's mostly the same as MTL
It might be better to say "Xe2_LPD" and "Xe_LPD+" instead of LNL/MTL?
== Series Details ==
Series: drm/i915/gt: skip WA verfication for GEN7_MISCCPCTL on DG2
URL : https://patchwork.freedesktop.org/series/123583/
State : warning
== Summary ==
Error: dim checkpatch failed
cd1b67e90fe1 drm/i915/gt: skip WA verfication for GEN7_MISCCPCTL on DG2
-:4:
On Mon, Sep 11, 2023 at 09:48:24PM -0700, Lucas De Marchi wrote:
> From: Ravi Kumar Vodapalli
>
> Add Display Power Well for LNL platform. It's mostly the same as MTL
It might be better to say "Xe2_LPD" and "Xe_LPD+" instead of LNL/MTL?
> platform so reuse the code. PGPICA1 contains type-C
On Tue, Sep 12, 2023 at 08:32:54AM -0700, Matt Roper wrote:
On Mon, Sep 11, 2023 at 09:48:21PM -0700, Lucas De Marchi wrote:
Fix some whitespace issues for register definitions and keep the defines
for DP_AUX_CH_CTL and DP_AUX_CH_DATA in the right place: together with
the bit definition.
While
There was a recent update in the BSpec adding an extra step to the PLL
enable sequence, which is for programming the msgbus timer. Since we
also touch PHY registers during hw readout, let's do the programming
when starting a transaction rather than only when doing the PLL enable
sequence.
This
Quoting Lucas De Marchi (2023-09-12 01:48:18-03:00)
>Some registers for DDI A/B moved to PICA and now follow the same format
>as the ones for the PORT_TC ports. The wrapper here deals with 2 issues:
>
>- Share the implementation between xe2lpd and previous
> platforms: there are
On Mon, Sep 11, 2023 at 09:48:23PM -0700, Lucas De Marchi wrote:
> The address of CTL and DATA registers for DP AUX were changed in Xe2_LPD:
> now they are all in a single range, with CH_A and CH_B coming right after
> the USBC instances. Like was done when moving registers to PICA, use
> a helper
On Mon, Sep 11, 2023 at 09:48:22PM -0700, Lucas De Marchi wrote:
> XELPDP_DP_AUX_CH_CTL() and XELPDP_DP_AUX_CH_DATA() use 2 ranges. Prefer
> using _PICK_EVEN_2RANGES() over PICK().
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> .../gpu/drm/i915/display/intel_dp_aux_regs.h
On Mon, Sep 11, 2023 at 09:48:21PM -0700, Lucas De Marchi wrote:
> Fix some whitespace issues for register definitions and keep the defines
> for DP_AUX_CH_CTL and DP_AUX_CH_DATA in the right place: together with
> the bit definition.
>
> While at it add a TODO entry that those defines shouldn't
On Tue, Sep 12, 2023 at 08:13:38AM -0700, Matt Roper wrote:
On Mon, Sep 11, 2023 at 09:48:09PM -0700, Lucas De Marchi wrote:
Add a FEATURES macro for XE_LPD+ as this is expected to be the baseline
for Xe2_LPD and will allow to see the delta more easily.
v2: Move everything from xe_lpdp_display
On Mon, Sep 11, 2023 at 09:48:10PM -0700, Lucas De Marchi wrote:
> From: Balasubramani Vivekanandan
>
> Add Lunar Lake platform definitions for i915 display. The support for
> LNL will be added to the xe driver, with i915 only driving the display
> side. Xe2 display is derived from the Xe_LPD+
On Mon, Sep 11, 2023 at 09:48:09PM -0700, Lucas De Marchi wrote:
> Add a FEATURES macro for XE_LPD+ as this is expected to be the baseline
> for Xe2_LPD and will allow to see the delta more easily.
>
> v2: Move everything from xe_lpdp_display to the new macro and remove
> the version setting:
On Mon, Sep 11, 2023 at 09:48:32PM -0700, Lucas De Marchi wrote:
> From: Stanislav Lisovskiy
>
> Add a new CDCLK table for Lunar Lake.
>
> v2:
> - Remove mdclk from the table as it's not needed (Matt Roper)
> - Update waveform values to the latest from spec (Matt Roper)
> - Rename
On 9/12/23 00:47, Jani Nikula wrote:
> On Mon, 11 Sep 2023, Randy Dunlap wrote:
>> On 9/10/23 19:11, Stephen Rothwell wrote:
>>> Hi all,
>>>
>>> Please do *not* include material destined for v6.7 in your linux-next
>>> included branches until *after* v6.6-rc1 has been released. Also,
>>> do
Apply WABB blit for Wa_16018031267 / Wa_16018063123.
Additionally, update the lrc selftest to exercise the new
WABB changes.
Co-developed-by: Nirmoy Das
Signed-off-by: Jonathan Cavitt
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +
drivers/gpu/drm/i915/gt/intel_gt.h | 4 +
Set copy engine arbitration into round robin mode
for part of Wa_16018031267 / Wa_16018063123 mitigation.
Signed-off-by: Nirmoy Das
Signed-off-by: Jonathan Cavitt
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
2 files changed, 8
Apply Wa_16018031267 / Wa_16018063123. This necessitates submitting a
fastcolor blit as WABB and setting the copy engine arbitration to
round-robin mode.
v2:
- Rename old platform check in second patch to match
declaration in first patch.
- Refactor second patch name to match first patch.
v3:
Reserve a page in each vm for kernel space to use for things
such as workarounds.
Signed-off-by: Jonathan Cavitt
Suggested-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 7 +++
drivers/gpu/drm/i915/gt/intel_gtt.h | 1 +
2 files changed, 8 insertions(+)
diff --git
On Tue, Sep 12, 2023 at 03:21:02PM +0200, Miquel Raynal wrote:
> alexander.usys...@intel.com wrote on Tue, 12 Sep 2023 13:15:58 +:
> > > No SPI controllers are directly visible to userspace, some SPI devices
> > > are selectively exposed but that needs to be explicitly requested and is
> > >
>
> > The spi controller on discreet graphics card is not visible to user-space.
> > Spi access flows are supported by another hardware module and relevant
> registers are
> > available on graphics device memory bar.
>
> No SPI controllers are directly visible to userspace, some SPI devices
>
Quoting Kahola, Mika (2023-09-12 09:26:59-03:00)
>> -Original Message-
>> From: Sousa, Gustavo
>> Sent: Monday, September 11, 2023 7:16 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Kahola, Mika ; Taylor, Clinton A
>>
>> Subject: [PATCH] drm/i915/cx0: Add step for programming msgbus
On Mon, Aug 28, 2023 at 12:04:50PM +0530, Tejas Upadhyay wrote:
> Now this workaround is permanent workaround on MTL and DG2,
since this also impacts DG2, the subject 'drm/i915/mtl'
is wrong. I know, this is water under the bridge now.
Another thing is this patch doesn't apply clean on
On Tue, Sep 12, 2023 at 03:05:37PM +0300, Jani Nikula wrote:
> Don't hide display probe in device info code.
>
> Cc: Matt Roper
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_driver.c | 2 ++
> drivers/gpu/drm/i915/intel_device_info.c | 2 --
>
On Tue, Sep 12, 2023 at 03:05:35PM +0300, Jani Nikula wrote:
> Initializing i915->display.info.__device_info and DISPLAY_RUNTIME_INFO()
> really belongs in display code. Move them there.
>
> Cc: Matt Roper
> Signed-off-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
> ---
>
On Tue, Sep 12, 2023 at 03:05:36PM +0300, Jani Nikula wrote:
> Move gmdid selection one abstraction level higher.
>
> Cc: Matt Roper
> Signed-off-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
> ---
> .../gpu/drm/i915/display/intel_display_device.c | 17 +
> 1 file changed, 9
> -Original Message-
> From: Sousa, Gustavo
> Sent: Monday, September 11, 2023 7:16 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kahola, Mika ; Taylor, Clinton A
>
> Subject: [PATCH] drm/i915/cx0: Add step for programming msgbus timer
>
> There was a recent update in the BSpec adding
On Tue, Sep 12, 2023 at 10:50:22AM +, Usyskin, Alexander wrote:
> The spi controller on discreet graphics card is not visible to user-space.
> Spi access flows are supported by another hardware module and relevant
> registers are
> available on graphics device memory bar.
No SPI controllers
Initializing i915->display.info.__device_info and DISPLAY_RUNTIME_INFO()
really belongs in display code. Move them there.
Cc: Matt Roper
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_device.c | 24 ---
.../drm/i915/display/intel_display_device.h | 4
Move gmdid selection one abstraction level higher.
Cc: Matt Roper
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/intel_display_device.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
Don't hide display probe in device info code.
Cc: Matt Roper
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_driver.c | 2 ++
drivers/gpu/drm/i915/intel_device_info.c | 2 --
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 ++
3 files changed, 4
Add stubs for !I915.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_sdvo.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.h
b/drivers/gpu/drm/i915/display/intel_sdvo.h
index 2868852c85f2..d1815b4103d4 100644
---
Add stubs for !I915.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/g4x_hdmi.h | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.h
b/drivers/gpu/drm/i915/display/g4x_hdmi.h
index 1e3ea7f3c846..817f55c7a3a1 100644
---
Add stubs for !I915.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/vlv_dsi.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.h
b/drivers/gpu/drm/i915/display/vlv_dsi.h
index 0c2b279df9d4..cf9d7b82f288 100644
---
Add stubs for !I915.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dpio_phy.h | 96 +++
1 file changed, 96 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.h
b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
index
Add stubs for !I915.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_wm.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.h
b/drivers/gpu/drm/i915/display/i9xx_wm.h
index b87ae369685a..de0920730ab2 100644
---
Add stubs for !I915.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_crt.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.h
b/drivers/gpu/drm/i915/display/intel_crt.h
index c6071efd93ce..fe7690c2b948 100644
---
Add stubs for !I915. Not all the functions need to be stubbed.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/vlv_dsi_pll.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.h
b/drivers/gpu/drm/i915/display/vlv_dsi_pll.h
index
Add stubs for !I915.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/g4x_dp.h | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.h
b/drivers/gpu/drm/i915/display/g4x_dp.h
index a38b3e1e01d3..a10638ab749c 100644
---
Add stubs for !I915.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_tv.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_tv.h
b/drivers/gpu/drm/i915/display/intel_tv.h
index 44518575ec5c..f08827b8bf2b 100644
---
Add stubs for !I915.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_overlay.h | 35
1 file changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.h
b/drivers/gpu/drm/i915/display/intel_overlay.h
index
Add stubs for !I915.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dvo.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.h
b/drivers/gpu/drm/i915/display/intel_dvo.h
index 3ed0fdf8efff..bf7a356422ab 100644
---
Add stubs for !I915.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_sprite.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.h
b/drivers/gpu/drm/i915/display/intel_sprite.h
index 91c6dca342b2..044a032e41b9 100644
---
Add stubs for !I915.
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/intel_pch_display.h | 53 +++
1 file changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.h
b/drivers/gpu/drm/i915/display/intel_pch_display.h
index
Add stubs for !I915.
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/intel_pch_refclk.h | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.h
b/drivers/gpu/drm/i915/display/intel_pch_refclk.h
index
Add stubs for !I915.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_lpe_audio.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.h
b/drivers/gpu/drm/i915/display/intel_lpe_audio.h
index
Add stubs for !I915.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_plane.h | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.h
b/drivers/gpu/drm/i915/display/i9xx_plane.h
index 027b66053984..b3d724a144cb
The upcoming drm/xe driver [1][2] will reuse the drm/i915 display code,
initially by compiling the relevant compilation units separately as part
of the xe driver. This series prepares for that in i915 side.
The first patch defines I915 during the i915 driver build, to allow
conditional
Add stubs for !I915.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/hsw_ips.h | 35 ++
1 file changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/hsw_ips.h
b/drivers/gpu/drm/i915/display/hsw_ips.h
index 4eb83b350791..35364228e1c1 100644
---
Add stubs for !I915.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_lvds.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.h
b/drivers/gpu/drm/i915/display/intel_lvds.h
index 9d3372dc503f..7ad5fa9c0434 100644
The xe driver will reuse i915 display code by compiling it separately as
part of xe. We'll want to be able to distinguish between building the
i915 display code for i915 and xe. Define I915 when building i915.
Cc: David Airlie
Cc: Daniel Vetter
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Tvrtko
>
> > Add driver for access to the discrete graphics card
> > internal SPI device.
> > Expose device on auxiliary bus and provide driver to register
> > this device with MTD framework.
>
> Maybe you can explain why you think auxiliary bus is relevant here? The
> cover letter might maybe be a bit
> On Sun, 10 Sep 2023, Alexander Usyskin
> wrote:
> > From: Jani Nikula
>
> I'm almost certain I did not write this patch originally. The authorship
> may have been changed accidentally along the way, but it's not mine.
>
> BR,
> Jani.
>
Sorry for that, seems like some rebase flux in the
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