Hi Jani,
> -Original Message-
> From: Jani Nikula
> Sent: Thursday, December 21, 2023 2:04 AM
> To: Sripada, Radhakrishna ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [PATCH v2 0/4] TC phy check cleanup
>
> On Wed, 20 Dec 2023, Radhakrishna Sripada
> wrote:
> > We are relying
Hello,
These are now pushed to drm-intel-next. There are BAT and IGT results
available in patchwork:
https://patchwork.freedesktop.org/series/127803/
Due to problems with our CI result mails were not sent and not all
checks were run on version 2. I checked IGT failures and they are not
related
Reviewed-by: Ankit Nautiyal
On 12/15/2023 10:39 AM, Suraj Kandpal wrote:
Fail repeater authentication step in case RX_INFO indicates
HDCP1.x or HDCP2.0/2.1 device is present downstream in repeater
topology and content type set by userspace is Type1.
--v2
-Fix build error.
--v3
-remove mst
> -Original Message-
> From: Ville Syrjälä
> Sent: Wednesday, December 20, 2023 8:19 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 8/9] drm/i915: Perform vblank evasion around legacy cursor
> updates
>
> On Wed, Dec 20, 2023 at 11:45:44AM +,
The hardware is not able to dynamically balance the load between
CCS engines. Wa_16016805146 suggests disabling it for all
platforms.
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Niranjana Vishwanathapura
Cc: Tejas Upadhyay
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h
Now that the CCS mode is configurable, an interface has been
exposed in the GT's sysfs set of files, allowing users to set the
mode.
Additionally, another interface has been added to display the
number of available slices, named 'num_slices.'
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc:
The CCS mode involves assigning CCS engines to slices depending
on the number of slices and the number of engines the user wishes
to set.
In this patch, the default CCS setting is established during the
initial GT settings. It involves assigning only one CCS to all
the slices.
Based on a patch
Hi,
This series aims to disable the CCS hardware load balancing, as recommended by
hardware directives in Wa_16016805146.
In the meantime, we need to define and support a fixed CCS mode of balancing
that can be configured by the user.
Thanks,
Andi
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc:
On Thu, Dec 21, 2023 at 08:02:21PM +0530, Haridhar Kalvala wrote:
> From: Harish Chegondi
>
> Xe_LPG+ (IP version 12.74) should take the same general code
> paths as Xe_LPG (versions 12.70 and 12.71).
>
> Xe_LPG+'s workaround list will be handled by the next patch.
>
> Signed-off-by: Harish
From: Matt Roper
Some of our existing Xe_LPG workarounds and tuning are also applicable
to the version 12.74 variant. Extend the condition bounds accordingly.
Also fix the comment on Wa_14018575942 while we're at it.
v2: Extend some more workarounds (Harish)
Signed-off-by: Matt Roper
From: Harish Chegondi
Xe_LPG+ (IP version 12.74) should take the same general code
paths as Xe_LPG (versions 12.70 and 12.71).
Xe_LPG+'s workaround list will be handled by the next patch.
Signed-off-by: Harish Chegondi
Signed-off-by: Haridhar Kalvala
---
From: Matt Roper
Our existing MTL driver handling is also sufficient to handle ARL, so
these IDs are simply added to the MTL ID list.
Bspec: 55420
Signed-off-by: Matt Roper
---
include/drm/i915_pciids.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/i915_pciids.h
Some SKUs of Arrow Lake use a slightly newer Xe_LPG+ graphics
IP (version 12.74). Add some additional PCI IDs and extend the
code to support this newer IP version. The general code flow
should continue to match existing MTL and Xe_LPG code paths.
Harish Chegondi (1):
drm/i915/xelpg: Extend
Hi Dave & Sima -
A bit more than I'd like at this stage, but next week will be quiet.
drm-intel-fixes-2023-12-21:
drm/i915 fixes for v6.7-rc7:
- Fix state readout and check for DSC and bigjoiner combo
- Fix a potential integer overflow
- Reject async flips with bigjoiner
- Fix MTL HDMI/DP PLL
On 12/6/2023 9:46 PM, Andi Shyti wrote:
Get the guc reference from the ce using the ce_to_guc() helper.
Just a leftover from previous cleanups.
Signed-off-by: Andi Shyti
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
1 file changed, 1
We can calculate the hw port clock during the hw readout
and store it as pll_state->clock for C20 state verification.
In order to do that we need to move intel_c20pll_calc_port_clock()
function.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 97
Add pll selection check for C20 as well as
clock state verification0. We have been relying
on sw state to select A or B pll's. This is incorrect
as the hw might see this selection differently. This
patch fixes this shortcoming by reading pll selection
for both sw and hw states and compares if
The function intel_c20_use_mplla() is not really
widely used and can be replaced with the more suitable
pll->tx[0] & C20_PHY_USE_MPLLB
expression. Let's remove the intel_c20_use_mplla()
alltogether and replace mplla/mpllb selection by
checking mpllb bit.
Signed-off-by: Mika Kahola
---
Add pll selection check for C20 as well as
clock state verification0. We have been relying
on sw state to select A or B pll's. This is incorrect
as the hw might see this selection differently. This
patch fixes this shortcoming by reading pll selection
for both sw and hw states and compares if
Remove some unused declarations probably left behind after some
refactoring.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h
b/drivers/gpu/drm/i915/display/intel_bios.h
On Wed, 20 Dec 2023, Radhakrishna Sripada
wrote:
> We are relying on end-less if-else ladders for a type-c phy
> capabilities check. Though it made sense when platforms supported
> legacy type-c support, modern platforms rely on the information
> passed by vbt. This cleanup restricts the if-else
On 12/21/2023 3:41 AM, Matt Roper wrote:
On Wed, Dec 20, 2023 at 12:22:33AM +0530, Haridhar Kalvala wrote:
Correct the implementation trying to detect MTL PCH with
the MTL fake PCH id.
On MTL, both the North Display (NDE) and South Display (SDE) functionality
reside on the same die (the SoC
On 12/6/2023 9:46 PM, Andi Shyti wrote:
Get the guc reference from the gt using the gt_to_guc() helper.
Signed-off-by: Andi Shyti
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/i915_debugfs_params.c | 2 +-
drivers/gpu/drm/i915/selftests/intel_scheduler_helpers.c | 4
On 12/6/2023 9:46 PM, Andi Shyti wrote:
Get the guc reference from the gt using the gt_to_guc() helper.
Signed-off-by: Andi Shyti
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 4 +--
drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c | 3 +-
On 12/6/2023 9:46 PM, Andi Shyti wrote:
We already have guc_to_gt() and getting to guc from the GT it
requires some mental effort. Add the gt_to_guc().
Given the reference to the "gt", the gt_to_guc() will return the
pinter to the "guc".
Update all the files under the gt/ directory.
Hi,
Here's this week drm-misc-next-fixes PR
Thanks!
Maxime
drm-misc-next-fixes-2023-12-21:
More fixes for the new imagination drier, a DT node refcount fix for the
new aux bridge driver and a missing header fix for the LUT management
code.
The following changes since commit
26 matches
Mail list logo
