[Intel-gfx] [PATCH 0/2] Security mitigation for Intel Gen7/7.5 HWs

Intel ID: PSIRT-TA-201910-001 CVEID: CVE-2019-14615 Summary of Vulnerability Insufficient control flow in certain data structures for some Intel(R) Processors with Intel Processor Graphics may allow an unauthenticated user to potentially enable information disclosure via

[Intel-gfx] [PATCH 2/2] drm/i915/gen7: Clear all EU/L3 residual contexts

context switching. This security mitigation change does not trigger any performance regression. Performance is on par with current mainline/drm-tip. Signed-off-by: Mika Kuoppala Signed-off-by: Prathap Kumar Valsan Signed-off-by: Akeem G Abodunrin Cc: Chris Wilson Cc: Balestrieri Francesco Cc

[Intel-gfx] [PATCH 1/2] drm/i915: Add mechanism to submit a context WA on ring submission

with current mainline/drm-tip. Signed-off-by: Mika Kuoppala Signed-off-by: Prathap Kumar Valsan Signed-off-by: Akeem G Abodunrin Cc: Chris Wilson Cc: Balestrieri Francesco Cc: Bloomfield Jon Cc: Dutt Sudeep --- .../gpu/drm/i915/gt/intel_ring_submission.c | 132 +- 1 file

[Intel-gfx] [PATCH v2 0/2] Security mitigation for Intel Gen7/7.5 HWs

Intel ID: PSIRT-TA-201910-001 CVEID: CVE-2019-14615 Summary of Vulnerability Insufficient control flow in certain data structures for some Intel(R) Processors with Intel Processor Graphics may allow an unauthenticated user to potentially enable information disclosure via

[Intel-gfx] [PATCH v2 1/2] drm/i915: Add mechanism to submit a context WA on ring submission

with current mainline/drm-tip. v2: Update vm_alias params to point to correct address space "vm" due to changes made in the patch "f21613797bae98773" Signed-off-by: Mika Kuoppala Signed-off-by: Prathap Kumar Valsan Signed-off-by: Akeem G Abodunrin Cc: Chris Wilson Cc: Bales

[Intel-gfx] [PATCH v2 2/2] drm/i915/gen7: Clear all EU/L3 residual contexts

Signed-off-by: Prathap Kumar Valsan Signed-off-by: Akeem G Abodunrin Cc: Chris Wilson Cc: Balestrieri Francesco Cc: Bloomfield Jon Cc: Dutt Sudeep --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/gen7_5_clearbuffer.h | 69 +++ drivers/gpu/drm/i915/gt

[Intel-gfx] [PATCH v4 2/2] drm/i915/gen7: Clear all EU/L3 residual contexts

with newly generated, and imported CB kernel. v4: Include new igt generated CB kernel for gen7 and gen7.5. Also add code formatting and compiler warnings changes (Chris Wilson) Signed-off-by: Mika Kuoppala Signed-off-by: Prathap Kumar Valsan Signed-off-by: Akeem G Abodunrin Cc: Chris Wilson Cc

[Intel-gfx] [PATCH v4 1/2] drm/i915: Add mechanism to submit a context WA on ring submission

with current mainline/drm-tip. v2: Update vm_alias params to point to correct address space "vm" due to changes made in the patch "f21613797bae98773" v3-v4: none Signed-off-by: Mika Kuoppala Signed-off-by: Prathap Kumar Valsan Signed-off-by: Akeem G Abodunrin Cc: Chris Wil

[Intel-gfx] [PATCH v4 0/2] Security mitigation for Intel Gen7/7.5 HWs

Intel ID: PSIRT-TA-201910-001 CVEID: CVE-2019-14615 Summary of Vulnerability Insufficient control flow in certain data structures for some Intel(R) Processors with Intel Processor Graphics may allow an unauthenticated user to potentially enable information disclosure via

[Intel-gfx] [PATCH 2/2] drm/i915/gen7: Clear all EU/L3 residual contexts

with newly generated, and imported CB kernel. v4: Include new igt generated CB kernel for gen7 and gen7.5. Also add code formatting and compiler warnings changes (Chris Wilson) Signed-off-by: Mika Kuoppala Signed-off-by: Prathap Kumar Valsan Signed-off-by: Akeem G Abodunrin Cc: Chris Wilson Cc

[Intel-gfx] [PATCH 1/2] drm/i915: Add mechanism to submit a context WA on ring submission

with current mainline/drm-tip. v2: Update vm_alias params to point to correct address space "vm" due to changes made in the patch "f21613797bae98773" v3-v4: none Signed-off-by: Mika Kuoppala Signed-off-by: Prathap Kumar Valsan Signed-off-by: Akeem G Abodunrin Cc: Chris Wil

[Intel-gfx] [PATCH 0/2] Security mitigation for Intel Gen7/7.5 HWs

Intel ID: PSIRT-TA-201910-001 CVEID: CVE-2019-14615 Summary of Vulnerability Insufficient control flow in certain data structures for some Intel(R) Processors with Intel Processor Graphics may allow an unauthenticated user to potentially enable information disclosure via

[Intel-gfx] [PATCH v3 1/2] drm/i915: Add mechanism to submit a context WA on ring submission

with current mainline/drm-tip. v2: Update vm_alias params to point to correct address space "vm" due to changes made in the patch "f21613797bae98773" Signed-off-by: Mika Kuoppala Signed-off-by: Prathap Kumar Valsan Signed-off-by: Akeem G Abodunrin Cc: Chris Wilson Cc: Bales

[Intel-gfx] [PATCH v3 2/2] drm/i915/gen7: Clear all EU/L3 residual contexts

with newly generated, and imported CB kernel. Signed-off-by: Mika Kuoppala Signed-off-by: Prathap Kumar Valsan Signed-off-by: Akeem G Abodunrin Cc: Chris Wilson Cc: Balestrieri Francesco Cc: Bloomfield Jon Cc: Dutt Sudeep --- drivers/gpu/drm/i915/Makefile | 1 + drivers

[Intel-gfx] [PATCH v3 0/2] Security mitigation for Intel Gen7/7.5 HWs

Intel ID: PSIRT-TA-201910-001 CVEID: CVE-2019-14615 Summary of Vulnerability Insufficient control flow in certain data structures for some Intel(R) Processors with Intel Processor Graphics may allow an unauthenticated user to potentially enable information disclosure via

[Intel-gfx] [RFC PATCH 2/2] drm/i915/gen7: Clear all EU/L3 residual contexts

context switching. Signed-off-by: Mika Kuoppala Signed-off-by: Prathap Kumar Valsan Signed-off-by: Akeem G Abodunrin Cc: Chris Wilson Cc: Balestrieri Francesco Cc: Bloomfield Jon Cc: Dutt Sudeep --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt

[Intel-gfx] [RFC PATCH 0/2] Security mitigation for Intel Gen7 and Gen7.5

Intel ID: PSIRT-TA-201910-001 CVEID: CVE-2019-14615 Summary of Vulnerability Insufficient control flow in certain data structures for some Intel(R) Processors with Intel Processor Graphics may allow an unauthenticated user to potentially enable information disclosure via

[Intel-gfx] [RFC PATCH 1/2] drm/i915: Add mechanism to submit a context WA on ring submission

From: Mika Kuoppala This patch adds framework to submit an arbitrary batchbuffer on each context switch to clear residual state for render engine on Gen7/7.5 devices. Signed-off-by: Mika Kuoppala Signed-off-by: Akeem G Abodunrin Cc: Kumar Valsan Prathap Cc: Chris Wilson Cc: Balestrieri

[Intel-gfx] [RFC PATCH v2 2/2] drm/i915/gen7: Clear all EU/L3 residual contexts

context switching. V2: Addressed comments about unused code, code formatting, and include additional debug code Signed-off-by: Mika Kuoppala Signed-off-by: Prathap Kumar Valsan Signed-off-by: Akeem G Abodunrin Cc: Chris Wilson Cc: Balestrieri Francesco Cc: Bloomfield Jon Cc: Dutt Sudeep

[Intel-gfx] [RFC PATCH v2 0/2] Security mitigation for Intel Gen7 HWs

Intel ID: PSIRT-TA-201910-001 CVEID: CVE-2019-14615 Summary of Vulnerability Insufficient control flow in certain data structures for some Intel(R) Processors with Intel Processor Graphics may allow an unauthenticated user to potentially enable information disclosure via

[Intel-gfx] [RFC PATCH v2 1/2] drm/i915: Add mechanism to submit a context WA on ring submission

From: Mika Kuoppala This patch adds framework to submit an arbitrary batchbuffer on each context switch to clear residual state for render engine on Gen7/7.5 devices. Signed-off-by: Mika Kuoppala Signed-off-by: Akeem G Abodunrin Cc: Kumar Valsan Prathap Cc: Chris Wilson Cc: Balestrieri

[Intel-gfx] [RFC PATCH v3 0/2] Security mitigation for Intel Gen7 HWs

NOTE: This series is in active development and is not intended to be merged to mainline in its current form. The intent of the RFC is simply to outline the strategy for the mitigation, as a focus for active discussion, and to openly share progress. There has been only minimal attention

[Intel-gfx] [RFC PATCH v3 1/2] drm/i915: Add mechanism to submit a context WA on ring submission

record a context switch when we are sure the next request will be emitted. v2: No change v3: elide optimization patch squashed, courtesy of Chris Wilson - the changes show significant performance improvements, on par with current drm-tips. Signed-off-by: Mika Kuoppala Signed-off-by: Akeem G Abodunrin

[Intel-gfx] [RFC PATCH v3 2/2] drm/i915/gen7: Clear all EU/L3 residual contexts

by Chris Wilson. v3: Expand debug code for every batch_alloc_items() call... Current patch series shows significant performance improvements, on par with current drm-tips. Signed-off-by: Mika Kuoppala Signed-off-by: Prathap Kumar Valsan Signed-off-by: Akeem G Abodunrin Cc: Chris Wilson Cc