On Fri, 15 Mar 2019 10:01:51 -0700
Rodrigo Vivi wrote:
> On Fri, Mar 15, 2019 at 09:55:47AM -0700, Bob Paauwe wrote:
> > On Fri, 15 Mar 2019 09:09:11 +
> > Chris Wilson wrote:
> >
> > > Quoting Rodrigo Vivi (2019-03-14 22:53:44)
> > > > On Th
that into a common routine.
> > >
> > > Signed-off-by: Chris Wilson
> > > Cc: Bob Paauwe
> > > Cc: Matthew Auld
> > > Cc: Joonas Lahtinen
> >
> > Reviewed-by: Rodrigo Vivi
>
> I've pushed this series so that 36 bits should be a ni
Chris,
Any thoughts on how I can best address your comment on this patch?
Bob
On Thu, 7 Feb 2019 11:13:15 -0800
Bob Paauwe wrote:
> On Thu, 7 Feb 2019 16:41:58 +
> Chris Wilson wrote:
>
> > Quoting Bob Paauwe (2019-02-07 16:29:53)
> > > With the address range
On Fri, 15 Mar 2019 10:57:11 -0700
Rodrigo Vivi wrote:
> From: Anusha Srivatsa
>
> EHL uses the same firmware as ICL.
Reviewed-by: Bob Paauwe
>
> Cc: Bob Paauwe
> Signed-off-by: Anusha Srivatsa
> Signed-off-by: Rodrigo Vivi
> Reviewed-by: Lucas De
> patch cc'ing the appropriated list and maintainers for
> > proper ack.
> > v3: (Rodrigo): - Removed .num_pipes = 3 that is coming since
> > GEN&_FEATURES.
> >- Added ppgtt type and size after rework from Bob and
> >
Unlike ICL, all of the output ports are combo phys so just return
true in intel_port_is_combophy for all EHL ports to indicate that.
v2: Return false in intel_port_is_tc since no EHL ports are TC. (Jose)
Cc: Jose Souza
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm
on current drm-tip
Signed-off-by: Bob Paauwe
CC: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 7 ++-
drivers/gpu/drm/i915/i915_drv.h | 8 +---
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2
ppgtt (both 3-lvl and 4-lvl) so name cap
define appropriately (Chris)
v9: rebase on latest
v10: fix missed vgpu change of FULL_48BIT to FULL in CAPS define (Bob)
v11: rebase on current drm-tip
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thierry
CC: Chris Wilson
---
drivers/g
We no longer need to differentiate between 4LVL and FULL ppgtt as
the number of bits in the address range provides that information now.
Signed-off-by: Bob Paauwe
CC: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_pci.c | 4
On Thu, 7 Feb 2019 16:41:58 +
Chris Wilson wrote:
> Quoting Bob Paauwe (2019-02-07 16:29:53)
> > With the address range being specified for each platform, we can use
> > that instead of the .ppgtt enum to handle the differences between
> > 3 level and 4 level PPGTT. In
the ability to configure the GPU "idle" frequecy
using the same method that already exists for minimum and maximum
frequencies.
In addition, parking the idle frequency may reduce spool up latencies
on GPU workloads.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915_sy
On Mon, 15 Apr 2019 17:33:30 -0700
Vanshidhar Konda wrote:
> On Mon, Apr 15, 2019 at 04:05:26PM -0700, Bob Paauwe wrote:
> >There are real-time use cases where having deterministic CPU processes
> >can be more important than GPU power/performance. Parking the GPU at a
>
nal code"). What got merged fails to do cdclk init/uninit on
> ehl.
Good catch!
Reviewed-by: Bob Paauwe
>
> Fixes: 39564ae86d51 ("drm/i915/ehl: Inherit Ice Lake conditional code")
> Cc: José Roberto de Souza
> Cc: Lucas De Marchi
> Cc: Bob Paauwe
> Cc: Rodri
> (combo port A external usage).
>
> - DPLL4 cannot be enabled when DC5 or DC6 are enabled.
>
> - The DPLL4 enable, lock, power enabled, and power state are connected
> to the MGPLL1_ENABLE register.
>
> v2: (suggestions from Bob Paauwe)
> - Rework ehl_get_dpll
On Tue, 16 Apr 2019 16:56:26 +0100
Chris Wilson wrote:
> Quoting Bob Paauwe (2019-04-16 00:05:26)
> > There are real-time use cases where having deterministic CPU processes
> > can be more important than GPU power/performance. Parking the GPU at a
> > specific freqency
.
v12:
Reviewed-by: Ville Syrjälä
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 9 insertions
.
Added format to ICL format lists.
v12:
Reviewed-by: Ville Syrjälä
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
This has been updated to support GEN11 along with rebasing it to
the latest drm-tip. A patch to igt has also been posted that gives
igt the ability
Add XYUV to the list of DRM Formats to test.
Also fix the byte order for the format.
Signed-off-by: Bob Paauwe
---
lib/igt_color_encoding.c | 1 +
lib/igt_fb.c | 6 +++---
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/lib/igt_color_encoding.c b/lib
gt; [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46
> [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
> [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
> [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
> [i915#677]: https://gitlab.
Test-with: 20200127192859.20029-1-bob.j.paa...@intel.com
Stanislav Lisovskiy (1):
drm/i915: Adding YUV444 packed format support for skl+ (V15)
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 8
drivers/gpu/drm/i915/i915_reg.h
Roper
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 8
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 14 insertions(+), 1 deletion(-)
diff
Add XYUV to the list of DRM Formats to test.
Also fix the byte order for the format.
Signed-off-by: Bob Paauwe
Reviewed-by: Uma Shankar
---
lib/igt_color_encoding.c | 1 +
lib/igt_fb.c | 6 +++---
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/lib
.
Added format to ICL format lists.
v12:
Reviewed-by: Ville Syrjälä
Reviewed-by: Matt Roper
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 5 +
drivers/gpu/drm/i915
Test-with: 20200127192859.20029-1-bob.j.paa...@intel.com
Stanislav Lisovskiy (1):
drm/i915: Adding YUV444 packed format support for skl+ (V14)
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++
drivers/gpu/drm/i915/i915_reg.h
.
Added format to ICL format lists.
V14: Added format to TGL format lists.
Rebased.
v12:
Reviewed-by: Ville Syrjälä
Reviewed-by: Matt Roper
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915
Roper
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 8
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 14 insertions(+), 1 deletion(-)
diff
Test-with: <20200407215146.5331-1-bob.j.paa...@intel.com>
Stanislav Lisovskiy (1):
drm/i915: Adding YUV444 packed format support for skl+ (V15)
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 8
drivers/gpu/drm/i915/i915_reg.h
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