On 2014/6/25 15:55, Paolo Bonzini wrote:
Il 25/06/2014 09:34, Chen, Tiejun ha scritto:
On 2014/6/25 14:48, Paolo Bonzini wrote:
Second problem. Your IGD passthrough code currently works with QEMU's
PIIX4-based machine. But what happens if you try to extend it, so that
Yes, current xen
On 2014/6/30 19:18, Michael S. Tsirkin wrote:
On Thu, Jun 19, 2014 at 05:53:51PM +0800, Tiejun Chen wrote:
Originally the reason to probe ISA bridge instead of Dev31:Fun0
is to make graphics device passthrough work easy for VMM, that
only need to expose ISA bridge to let driver know the real
On 2014/7/2 14:21, Michael S. Tsirkin wrote:
On Thu, Jun 19, 2014 at 05:53:51PM +0800, Tiejun Chen wrote:
Originally the reason to probe ISA bridge instead of Dev31:Fun0
is to make graphics device passthrough work easy for VMM, that
only need to expose ISA bridge to let driver know the real
On 2014/7/16 22:20, Konrad Rzeszutek Wilk wrote:
On Thu, Jul 03, 2014 at 11:27:40PM +0300, Michael S. Tsirkin wrote:
On Thu, Jul 03, 2014 at 12:09:28PM -0700, Jesse Barnes wrote:
On Thu, 3 Jul 2014 14:26:12 -0400
Konrad Rzeszutek Wilk konrad.w...@oracle.com wrote:
On Thu, Jul 03, 2014 at
; Zhang, Yang Z; Chen, Tiejun
Subject: Re: [Intel-gfx] ResettRe: [Xen-devel] [v5][PATCH 0/5] xen: add Intel
IGD passthrough support
On Thu, Jul 17, 2014 at 05:37:12PM +, Kay, Allen M wrote:
That sounds great. Tiejun could you confirm that with windows driver guys too?
I believe windows
On 2014/7/26 1:01, Konrad Rzeszutek Wilk wrote:
On Thu, Jul 24, 2014 at 09:44:41AM +0800, Chen, Tiejun wrote:
On 2014/7/24 4:54, Konrad Rzeszutek Wilk wrote:
On Sat, Jul 19, 2014 at 12:27:21AM +, Kay, Allen M wrote:
For the MCH PCI registers that do need to be read - can you tell us which
On 2014/7/29 16:32, Paolo Bonzini wrote:
Il 29/07/2014 08:59, Chen, Tiejun ha scritto:
(see https://lkml.org/lkml/2014/6/19/121)
gpu:drm:i915:intel_detect_pch: back to check devfn instead of check
class
type. Because Windows always use this way, so I think this point
should be
same between
On 2014/8/18 16:21, Michael S. Tsirkin wrote:
On Mon, Aug 18, 2014 at 11:06:29AM +0800, Chen, Tiejun wrote:
On 2014/8/17 18:32, Michael S. Tsirkin wrote:
On Fri, Aug 15, 2014 at 09:58:40AM +0800, Chen, Tiejun wrote:
Michael and Paolo,
Please re-post discussion on list. These off list ones
On 2014/8/18 17:58, Michael S. Tsirkin wrote:
On Mon, Aug 18, 2014 at 05:01:25PM +0800, Chen, Tiejun wrote:
On 2014/8/18 16:21, Michael S. Tsirkin wrote:
On Mon, Aug 18, 2014 at 11:06:29AM +0800, Chen, Tiejun wrote:
On 2014/8/17 18:32, Michael S. Tsirkin wrote:
On Fri, Aug 15, 2014 at 09
On 2014/8/20 5:51, Michael S. Tsirkin wrote:
On Tue, Aug 19, 2014 at 09:24:03PM +, Kay, Allen M wrote:
Allen,
Could you reply this?
Let me summarized what we have discussed and learned so far:
1) Future Windows/Linux IGD drivers will be modified to restrain from accessing
MCH/PCH
Just ping, any comments?
Thanks
Tiejun
On 2014/6/19 17:53, Tiejun Chen wrote:
Originally the reason to probe ISA bridge instead of Dev31:Fun0
is to make graphics device passthrough work easy for VMM, that
only need to expose ISA bridge to let driver know the real
hardware underneath. This is a
. And especially, we wouldn't
provide that ISA bridge with an explicit class type in qemu-upstream, so
we need to the i915 driver to probe pch by checking devfn.
This should work both on the native case and the virtualized case.
Thanks
Tiejun
-Daniel
On Fri, Jun 20, 2014 at 11:40 AM, Chen
On 2014/6/20 20:48, Paolo Bonzini wrote:
Il 19/06/2014 11:53, Tiejun Chen ha scritto:
so this mean that isa bridge is still represented with Dev31:Func0
like the native OS. Furthermore, currently we're pushing VGA
passthrough support into qemu upstream, and with some discussion,
we wouldn't set
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